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ORCIDJose Luis Garcia-Gervacio
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2010 – 2019
- 2018
[j5]Gilberto Domínguez Rodríguez, Jose Luis Garcia-Gervacio, Héctor Vázquez-Leal:
Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations. IEICE Electron. Express 15(14): 20180475 (2018)- [j4]Alfonso Herrera-Moreno, Jose Luis Garcia-Gervacio, Héctor Villacorta-Minaya, Héctor Vázquez-Leal:
TCAD analysis and modeling for NBTI mechanism in FinFET transistors. IEICE Electron. Express 15(14): 20180502 (2018) - 2016
- [c8]Jose Adrian Ruiz Carmona, Julio Cesar Munoz Benitez, Jose Luis Garcia-Gervacio:
SCADA system design: A proposal for optimizing a production line. CONIELECOMP 2016: 192-197 - 2015
- [j3]Hector Villacorta, Jose Luis Garcia-Gervacio, Jaume Segura
, Víctor H. Champac:
Low VDD and body bias conditions for testing bridge defects in the presence of process variations. Microelectron. J. 46(5): 398-403 (2015) - [j2]Jose Luis Garcia-Gervacio, Alejandro Nocua, Víctor H. Champac:
Screening small-delay defects using inter-path correlation to reduce reliability risk. Microelectron. Reliab. 55(6): 1005-1011 (2015) - 2014
- [c7]Jose Luis Garcia-Gervacio, Jaime Martínez-Castillo, Víctor H. Champac:
Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies. LATW 2014: 1-6 - 2013
- [c6]Hector Villacorta, Jose Luis Garcia-Gervacio, Víctor H. Champac, Sebastià A. Bota, Jaime Martínez-Castillo, Jaume Segura:
Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias. LATW 2013: 1-6 - [c5]Jose Luis Garcia-Gervacio, Agustín Leobardo Herrera-May, Gregorio Zamora-Mejía, Jaime Martínez-Castillo, Alejandro Díaz-Sánchez:
Voltage Regulation System for UHF RFID Tags. SBCCI 2013: 1-6 - 2012
- [c4]Francisco J. Galarza-Medina, Jose Luis Garcia-Gervacio, Víctor H. Champac, Alex Orailoglu:
Small-delay defects detection under process variation using Inter-Path Correlation. VTS 2012: 127-132 - 2011
- [j1]Jose Luis Garcia-Gervacio, Víctor H. Champac:
Computing the Detection Probability for Small Delay Defects of Nanometer ICs. J. Electron. Test. 27(6): 741-752 (2011) - 2010
- [c3]Jose Luis Garcia-Gervacio, Víctor H. Champac:
Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. ETS 2010: 126-131
2000 – 2009
- 2009
- [c2]Jose Luis Garcia-Gervacio, Víctor H. Champac:
Detectability analysis of small delays due to resistive opens considering process variations. IOLTS 2009: 195-197 - 2008
- [c1]Daniel Iparraguirre-Cardenas, Jose Luis Garcia-Gervacio, Víctor H. Champac:
A design methodology for logic paths tolerant to local intra-die variations. ISCAS 2008: 596-599
Coauthor Index
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