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2020 – today
- 2024
[c68]Haley M. So, Laurie Bose, Piotr Dudek, Gordon Wetzstein:
PixelRNN: In-pixel Recurrent Neural Networks for End-to-end-optimized Perception with Neural Sensors. CVPR 2024: 25233-25244- [i9]Piotr Dudek:
Factor Machine: Mixed-signal Architecture for Fine-Grained Graph-Based Computing. CoRR abs/2402.12130 (2024) - [i8]Laurie Bose, Piotr Dudek:
Mapping Image Transformations Onto Pixel Processor Arrays. CoRR abs/2403.16994 (2024) - 2023
- [c67]Laurie Bose, Piotr Dudek, Stephen J. Carey, Jianing Chen:
Live Demonstration: SCAMP-7. CVPR Workshops 2023: 3995-3996 - [i7]Haley M. So, Laurie Bose, Piotr Dudek, Gordon Wetzstein:
PixelRNN: In-pixel Recurrent Neural Networks for End-to-end-optimized Perception with Neural Sensors. CoRR abs/2304.05440 (2023) - 2022
- [j17]Piotr Dudek
, Tom Richardson, Laurie Bose, Stephen J. Carey, Jianing Chen, Colin Greatwood, Yanan Liu, Walterio W. Mayol-Cuevas:
Sensor-level computer vision with pixel processor arrays for agile robots. Sci. Robotics 7(67) (2022) - [c66]Haley M. So, Julien N. P. Martel, Gordon Wetzstein, Piotr Dudek:
MantissaCam: Learning Snapshot High-dynamic-range Imaging with Perceptually-based In-pixel Irradiance Encoding. ICCP 2022: 1-12 - [c65]Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek:
Pixel Processor Arrays For Low Latency Gaze Estimation. VR Workshops 2022: 970-971 - 2021
- [j16]Yanan Liu, Laurie Bose, Colin Greatwood, Jianing Chen, Rui Fan, Thomas Richardson, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas:
Agile reactive navigation for a non-holonomic mobile robot using a pixel processor array. IET Image Process. 15(9): 1883-1892 (2021) - [i6]Yanan Liu, Jianing Chen, Laurie Bose, Piotr Dudek, Walterio W. Mayol-Cuevas:
Bringing A Robot Simulator to the SCAMP Vision System. CoRR abs/2105.10479 (2021) - [i5]Yanan Liu, Jianing Chen, Laurie Bose, Piotr Dudek, Walterio W. Mayol-Cuevas:
Direct Servo Control from In-Sensor CNN Inference with A Pixel Processor Array. CoRR abs/2106.07561 (2021) - [i4]Haley M. So, Julien N. P. Martel, Piotr Dudek, Gordon Wetzstein:
MantissaCam: Learning Snapshot High-dynamic-range Imaging with Perceptually-based In-pixel Irradiance Encoding. CoRR abs/2112.05221 (2021) - 2020
- [j15]Alexander McConville, Laurie Bose, Robert Clarke, Walterio W. Mayol-Cuevas, Jianing Chen, Colin Greatwood, Stephen J. Carey, Piotr Dudek, Thomas Richardson:
Visual Odometry Using Pixel Processor Arrays for Unmanned Aerial Systems in GPS Denied Environments. Frontiers Robotics AI 7: 126 (2020) - [j14]Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Piotr Dudek, Gordon Wetzstein:
Neural Sensors: Learning Pixel Exposures for HDR Imaging and Video Compressive Sensing With Programmable Sensors. IEEE Trans. Pattern Anal. Mach. Intell. 42(7): 1642-1653 (2020) - [c64]Yanan Liu, Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas:
High-speed Light-weight CNN Inference via Strided Convolutions on a Pixel Processor Array. BMVC 2020 - [c63]Laurie Bose, Piotr Dudek, Jianing Chen, Stephen J. Carey, Walterio W. Mayol-Cuevas:
Fully Embedding Fast Convolutional Networks on Pixel Processor Arrays. ECCV (29) 2020: 488-503 - [c62]Jianing Chen, Yanan Liu, Stephen J. Carey, Piotr Dudek:
Proximity Estimation Using Vision Features Computed On Sensor. ICRA 2020: 2689-2695 - [c61]Stephen J. Carey, Laurie Bose, Thomas S. Richardson, Walterio W. Mayol-Cuevas, Jianing Chen, Piotr Dudek:
Live Demonstration: CNN Inference on the Focal Plane with a Pixel Processor Array. ISCAS 2020: 1 - [c60]Tobi Delbrück, Ibrahim Abe M. Elfadel, Shahzad Muzaffar, Germain Haessig, Bo Wang, Amine Bermak, Rui Graca, Luis A. Camuñas-Mesa, Bathiya Senevirathna, Pamela Abshire, Bernabé Linares-Barranco, Saeed Afshar, Shih-Chii Liu, Runchun Mark Wang, Piotr Dudek, Stephen J. Carey, José M. de la Rosa, Marc Dandin, Sheung Lu, Vincent Frick, Teresa Serrano-Gotarredona, Paula López, Melika Payvand, Advait Madhavan, Eric R. Fossum, Juan Camilo Vasquez Tieck, Ian Williams, Yan Liu, Timothy G. Constandinou, Alexander Serb, Ricardo Carmona-Galán, Robert Nawrocki, Walter D. Leon-Salas:
Lessons Learned the Hard Way. ISCAS 2020: 1-18 - [c59]Germain Haessig, Daniel García-Lesta, Gregor Lenz, Ryad Benosman, Piotr Dudek:
A Mixed-Signal Spatio-Temporal Signal Classifier for On-Sensor Spike Sorting. ISCAS 2020: 1-5 - [i3]Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas:
Fully Embedding Fast Convolutional Networks on Pixel Processor Arrays. CoRR abs/2004.12525 (2020) - [i2]Yanan Liu, Laurie Bose, Colin Greatwood, Jianing Chen, Rui Fan, Thomas S. Richardson, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas:
Agile Reactive Navigation for A Non-Holonomic Mobile Robot Using A Pixel Processor Array. CoRR abs/2009.12796 (2020)
2010 – 2019
- 2019
- [c58]Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas:
Live Demonstration: Digit Recognition on Pixel Processor Arrays. CVPR Workshops 2019: 1705-1706 - [c57]Laurie Bose, Piotr Dudek, Jianing Chen, Stephen J. Carey, Walterio W. Mayol-Cuevas:
A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays. ICCV 2019: 1335-1344 - [i1]Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas:
A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays. CoRR abs/1909.05647 (2019) - 2018
- [j13]Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Jonathan Müller, Yulia Sandamirskaya, Piotr Dudek:
Real-Time Depth From Focus on a Programmable Focal Plane Processor. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 925-934 (2018) - [c56]Jianing Chen, Stephen J. Carey, Piotr Dudek:
Scamp5d Vision System and Development Framework. ICDSC 2018: 23:1-23:2 - [c55]Colin Greatwood, Laurie Bose, Thomas Richardson, Walterio W. Mayol-Cuevas, Jianing Chen, Stephen J. Carey, Piotr Dudek:
Perspective Correcting Visual Odometry for Agile MAVs using a Pixel Processor Array. IROS 2018: 987-994 - 2017
- [c54]Laurie Bose, Jianing Chen, Stephen J. Carey, Piotr Dudek, Walterio W. Mayol-Cuevas:
Visual Odometry for Pixel Processor Arrays. ICCV 2017: 4614-4622 - [c53]Colin Greatwood, Laurie Bose, Thomas S. Richardson, Walterio W. Mayol-Cuevas, Jianing Chen, Stephen J. Carey, Piotr Dudek:
Tracking control of a UAV with a parallel visual processor. IROS 2017: 4248-4254 - [c52]Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Piotr Dudek:
High-speed depth from focus on a programmable vision chip using a focus tunable lens. ISCAS 2017: 1-4 - [c51]Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Jonathan Müller, Yulia Sandamirskaya, Piotr Dudek:
Live demonstration: Depth from focus on a focal plane processor using a focus tunable liquid lens. ISCAS 2017: 1 - 2016
- [c50]Julien N. P. Martel, Yulia Sandamirskaya, Piotr Dudek:
A Demonstration of Tracking using Dynamic Neural Fields on a Programmable Vision Chip: Demo. ICDSC 2016: 212-213 - [c49]Julien N. P. Martel, Lorenz K. Müller, Stephen J. Carey, Piotr Dudek:
Parallel HDR tone mapping and auto-focus on a cellular processor array vision chip. ISCAS 2016: 1430-1433 - 2015
- [j12]Przemyslaw Mroszczyk, Piotr Dudek:
Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 497-506 (2015) - [c48]Julien N. P. Martel, Miguel Chau, Matthew Cook, Piotr Dudek:
Pixel interlacing to trade off the resolution of a cellular processor array against more registers. ECCTD 2015: 1-4 - [c47]Manu V. Nair, Piotr Dudek:
Gradient-descent-based learning in memristive crossbar arrays. IJCNN 2015: 1-7 - [c46]Declan Walsh, Piotr Dudek:
An event-driven massively parallel fine-grained processor array. ISCAS 2015: 1346-1349 - [c45]Julien N. P. Martel, Miguel Chau, Piotr Dudek, Matthew Cook:
Toward joint approximate inference of visual quantities on cellular processor arrays. ISCAS 2015: 2061-2064 - 2014
- [j11]Przemyslaw Mroszczyk, Piotr Dudek:
Tunable CMOS Delay Gate With Improved Matching Properties. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2586-2595 (2014) - [c44]Bin Wang, Piotr Dudek:
A Fast Self-Tuning Background Subtraction Algorithm. CVPR Workshops 2014: 401-404 - [c43]Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek:
Live demonstration: A sensor-processor array integrated circuit for high-speed real-time machine vision. ISCAS 2014: 447 - [c42]Przemyslaw Mroszczyk, Piotr Dudek:
The accuracy and scalability of continuous-time Bayesian inference in analogue CMOS circuits. ISCAS 2014: 1576-1579 - [c41]Stephen J. Carey, Ákos Zarándy, Piotr Dudek:
Characterization of processing errors on analog fully-programmable cellular sensor-processor arrays. ISCAS 2014: 1580-1583 - 2013
- [j10]Stephen J. Carey, David Robert Wallace Barr, Piotr Dudek:
Low power high-performance smart camera system based on SCAMP vision sensor. J. Syst. Archit. 59(10-A): 889-899 (2013) - [c40]Alexey Lopich, Piotr Dudek:
A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array. CICC 2013: 1-4 - [c39]Przemyslaw Mroszczyk, Piotr Dudek:
Trigger-wave propagation in arbitrary metrics in asynchronous cellular logic arrays. ECCTD 2013: 1-4 - [c38]Bin Wang, Piotr Dudek:
AMBER: Adapting multi-resolution background extractor. ICIP 2013: 3417-3421 - [c37]Przemyslaw Mroszczyk, Piotr Dudek:
Tunable CMOS delay gate with reduced impact of fabrication mismatch on timing parameters. NEWCAS 2013: 1-4 - [c36]Ioannis Georgilas, Andrew Adamatzky, David Robert Wallace Barr, Piotr Dudek, Chris Melhuish:
Metachronal Waves in Cellular Automata: Cilia-Like Manipulation in Actuator Arrays. NICSO 2013: 261-271 - [c35]David Robert Wallace Barr, Declan Walsh, Piotr Dudek:
A Smart Surface Simulation Environment. SMC 2013: 4456-4461 - 2012
- [c34]Declan Walsh, Piotr Dudek:
A field programmable array core for image processing (abstract only). FPGA 2012: 266 - [c33]Tao Zhou, Piotr Dudek, Bertram E. Shi:
Development of robot self-identification based on visuomotor prediction. ICDL-EPIROB 2012: 1-2 - [c32]Stephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek:
Mixed signal SIMD cellular processor array vision chip operating at 30, 000 fps. ICECS 2012: 324-327 - [c31]Jayawan H. B. Wijekoon, Piotr Dudek:
Heterogeneous neurons and plastic synapses in a reconfigurable cortical neural network IC. ISCAS 2012: 2417-2420 - [c30]Przemyslaw Mroszczyk, Piotr Dudek:
Trigger-wave collision detecting asynchronous cellular logic array for fast image skeletonization. ISCAS 2012: 2653-2656 - 2011
- [j9]Alexey Lopich, Piotr Dudek:
Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array. Int. J. Circuit Theory Appl. 39(9): 963-972 (2011) - [j8]Alexey Lopich, Piotr Dudek:
A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(10): 2420-2431 (2011) - [c29]Stephen J. Carey, David Robert Wallace Barr, Piotr Dudek:
Demonstration of a low power image processing system using a SCAMP3 vision chip. ICDSC 2011: 1-2 - [c28]Tao Zhou, Piotr Dudek, Bertram E. Shi:
Self-Organizing Neural Population Coding for improving robotic visuomotor coordination. IJCNN 2011: 1437-1444 - [c27]Jayawan H. B. Wijekoon, Piotr Dudek:
Analogue CMOS circuit implementation of a dopamine modulated synapse. ISCAS 2011: 877-880 - [c26]Pamela Abshire, Amine Bermak, Raphael Berner, Gert Cauwenberghs, Shoushun Chen, Jennifer Blain Christen, Timothy G. Constandinou, Eugenio Culurciello, Marc Dandin, Timir Datta, Tobi Delbrück, Piotr Dudek, Amir Eftekhar, Ralph Etienne-Cummings, Giacomo Indiveri, Matthew K. Law, Bernabé Linares-Barranco, Jonathan Tapson, Wei Tang, Yiming Zhai:
Confession session: Learning from others mistakes. ISCAS 2011: 1149-1162 - [c25]Stephen J. Carey, Alexey Lopich, Piotr Dudek:
A processor element for a mixed signal cellular processor array vision chip. ISCAS 2011: 1564-1567 - [c24]Alexey Lopich, David Robert Wallace Barr, Bin Wang, Piotr Dudek:
Live demonstration: Real-time image processing on ASPA2 vision system. ISCAS 2011: 1989 - [c23]Alexey Lopich, Piotr Dudek:
Architecture and design of a programmable 3D-integrated cellular processor array for image processing. VLSI-SoC 2011: 349-353 - 2010
- [c22]Kevin Brohan, Kevin N. Gurney, Piotr Dudek:
Using Reinforcement Learning to Guide the Development of Self-organised Feature Maps for Visual Orienting. ICANN (2) 2010: 180-189 - [c21]Alexey Lopich, Piotr Dudek:
An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology. ISCAS 2010: 4257-4260
2000 – 2009
- 2009
- [j7]David Robert Wallace Barr, Piotr Dudek:
APRON: A Cellular Processor Array Simulation and Hardware Design Tool. EURASIP J. Adv. Signal Process. 2009 (2009) - [j6]Alexey Lopich, Piotr Dudek:
Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing. J. Signal Process. Syst. 56(1): 91-103 (2009) - [c20]Piotr Dudek, Alexey Lopich, Viktor Gruev:
A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology. ECCTD 2009: 193-196 - 2008
- [j5]Carmen Alonso-Montes, David López Vilariño, Piotr Dudek, Manuel G. Penedo:
Fast retinal vessel tree extraction: A pixel parallel approach. Int. J. Circuit Theory Appl. 36(5-6): 641-651 (2008) - [j4]Jayawan H. B. Wijekoon, Piotr Dudek:
Compact silicon neuron circuit with spiking and bursting behaviour. Neural Networks 21(2-3): 524-534 (2008) - [c19]Martin Hülse, David Robert Wallace Barr, Piotr Dudek:
Cellular automata and non-static image processing for embodied robot systems on a massively parallel processor array. Automata 2008: 504-513 - [c18]Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dudek, Thomas Dowrick, Liam McDaid:
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks. FPL 2008: 483-486 - [c17]Alexey Lopich, Piotr Dudek:
ASPA: Focal Plane digital processor array with asynchronous processing capabilities. ISCAS 2008: 1592-1595 - [c16]David López Vilariño, Piotr Dudek, Diego Cabello:
Focal-plane moving object segmentation for realtime video surveillance. ISCAS 2008: 1600-1603 - [c15]Jayawan H. B. Wijekoon, Piotr Dudek:
Integrated circuit implementation of a cortical neuron. ISCAS 2008: 1784-1787 - 2007
- [c14]Alexey Lopich, Piotr Dudek:
Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array. ECCTD 2007: 84-87 - [c13]Carmen Alonso-Montes, Piotr Dudek, David López Vilariño, Manuel G. Penedo:
On chip implementation of a pixel-parallel approach for retinal vessel tree extraction. ECCTD 2007: 511-514 - [c12]Jayawan H. B. Wijekoon, Piotr Dudek:
Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit. IJCNN 2007: 1332-1337 - [c11]David Robert Wallace Barr, Piotr Dudek, Jonathan M. Chambers, Kevin N. Gurney:
Implementation of multi-layer leaky integrator networks on a cellular processor array. IJCNN 2007: 1560-1565 - [c10]David López Vilariño, Piotr Dudek:
Evolution of Pixel Level Snakes towards an efficient hardware implementation. ISCAS 2007: 2678-2681 - 2006
- [j3]Piotr Dudek:
An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 354-358 (2006) - [c9]Jayawan H. B. Wijekoon, Piotr Dudek:
Simple Analogue VLSI Circuit of a Cortical Neuron. ICECS 2006: 1344-1347 - [c8]Alexey Lopich, Piotr Dudek:
Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing. ISCAS 2006 - 2005
- [j2]Piotr Dudek, Peter J. Hicks:
A general-purpose processor-per-pixel analog SIMD vision chip. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(1): 13-20 (2005) - [c7]Aliaksei Lopich, Piotr Dudek:
Architecture of asynchronous cellular processor array for image skeletonization. ECCTD 2005: 81-84 - [c6]Piotr Dudek, V. D. Juncu:
An area and power efficient discrete-time chaos generator circuit. ECCTD 2005: 87-90 - [c5]Piotr Dudek:
Implementation of SIMD vision chip with 128×128 array of analogue processing elements. ISCAS (6) 2005: 5806-5809 - 2004
- [c4]Piotr Dudek:
A 39×48 general-purpose focal-plane processor array integrated circuit. ISCAS (5) 2004: 448-452 - 2003
- [c3]Piotr Dudek:
A flexible global readout architecture for an analogue SIMD vision chip. ISCAS (3) 2003: 782-785 - 2001
- [c2]Piotr Dudek, Peter J. Hicks:
An analogue SIMD focal-plane processor array. ISCAS (4) 2001: 490-493 - 2000
- [j1]Piotr Dudek, Stanislaw Szczepanski, John V. Hatfield:
A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. IEEE J. Solid State Circuits 35(2): 240-247 (2000) - [c1]Piotr Dudek, Peter J. Hicks:
A CMOS general-purpose sampled-data analogue microprocessor. ISCAS 2000: 417-420
Coauthor Index
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