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2020 – today
- 2023
[c17]Gabriel H. Loh
, Michael J. Schulte, Mike Ignatowski, Vignesh Adhinarayanan, Shaizeen Aga, Derrick Aguren, Varun Agrawal, Ashwin M. Aji, Johnathan Alsop, Paul T. Bauman, Bradford M. Beckmann, Majed Valad Beigi, Sergey Blagodurov, Travis Boraten, Michael Boyer, William C. Brantley, Noel Chalmers, Shaoming Chen, Kevin Cheng, Michael L. Chu, David Cownie, Nicholas Curtis, Joris Del Pino, Nam Duong, Alexandru Dutu, Yasuko Eckert, Christopher Erb, Chip Freitag, Joseph L. Greathouse, Sudhanva Gurumurthi, Anthony Gutierrez, Khaled Hamidouche, Sachin Hossamani, Wei Huang, Mahzabeen Islam, Nuwan Jayasena, John Kalamatianos, Onur Kayiran, Jagadish Kotra, Alan Lee, Daniel Lowell, Niti Madan, Abhinandan Majumdar, Nicholas Malaya, Srilatha Manne, Susumu Mashimo, Damon McDougall, Elliot Mednick, Michael Mishkin, Mark Nutter, Indrani Paul, Matthew Poremba, Brandon Potter, Kishore Punniyamurthy, Sooraj Puthoor, Steven E. Raasch, Karthik Rao, Gregory Rodgers, Marko Scrbak, Mohammad Seyedzadeh, John Slice, Vilas Sridharan, René van Oostrum, Eric Van Tassell, Abhinav Vishnu, Samuel Wasmundt, Mark Wilkening, Noah Wolfe, Mark Wyse, Adithya Yalavarti, Dmitri Yudanov:
A Research Retrospective on AMD's Exascale Computing Journey. ISCA 2023: 81:1-81:14
2010 – 2019
- 2018
- [c16]Anthony Gutierrez, Bradford M. Beckmann, Alexandru Dutu, Joseph Gross, Michael LeBeane, John Kalamatianos, Onur Kayiran, Matthew Poremba, Brandon Potter, Sooraj Puthoor, Matthew D. Sinclair, Mark Wyse, Jieming Yin, Xianwei Zhang, Akshay Jain, Timothy G. Rogers:
Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level. HPCA 2018: 608-619 - [c15]Jieming Yin, Zhifeng Lin, Onur Kayiran, Matthew Poremba, Muhammad Shoaib Bin Altaf, Natalie D. Enright Jerger, Gabriel H. Loh:
Modular Routing Design for Chiplet-Based Systems. ISCA 2018: 726-738 - 2017
- [c14]Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan:
Design and Analysis of an APU for Exascale Computing. HPCA 2017: 85-96 - [c13]Matthew Poremba, Itir Akgun, Jieming Yin, Onur Kayiran, Yuan Xie, Gabriel H. Loh:
There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes. ISCA 2017: 678-690 - 2016
- [c12]Matthew Poremba, Tao Zhang, Yuan Xie:
Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision. DAC 2016: 168:1-168:6 - [c11]Jieming Yin, Onur Kayiran, Matthew Poremba, Natalie D. Enright Jerger, Gabriel H. Loh:
Efficient synthetic traffic models for large, complex SoCs. HPCA 2016: 297-308 - 2015
- [j2]Matthew Poremba, Tao Zhang, Yuan Xie:
NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems. IEEE Comput. Archit. Lett. 14(2): 140-143 (2015) - [j1]Hsiang-Yun Cheng, Matt Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie:
EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors. ACM Trans. Archit. Code Optim. 12(2): 17:1-17:22 (2015) - [c10]Qiaosha Zou, Matthew Poremba, Rui He, Wei Yang, Junfeng Zhao, Yuan Xie:
Heterogeneous architecture design with emerging 3D and non-volatile memory technologies. ASP-DAC 2015: 785-790 - [c9]Matt Poremba, Sparsh Mittal, Dong Li, Jeffrey S. Vetter, Yuan Xie:
DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches. DATE 2015: 1543-1546 - 2014
- [c8]Qiaosha Zou, Matt Poremba, Yuan Xie:
A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests. 3DIC 2014: 1-7 - [c7]Qiaosha Zou, Jia Zhan, Fen Ge, Matt Poremba, Yuan Xie:
Designing vertical bandwidth reconfigurable 3D NoCs for many core systems. 3DIC 2014: 1-7 - [c6]Jia Zhan, Matthew Poremba, Yi Xu, Yuan Xie:
NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores. ASP-DAC 2014: 586-591 - [c5]Tao Zhang, Matthew Poremba, Cong Xu, Guangyu Sun, Yuan Xie:
CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture. HPCA 2014: 368-379 - [c4]Hsiang-Yun Cheng, Matthew Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie:
EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors. ISLPED 2014: 303-306 - 2013
- [c3]Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Matthew Poremba, Vijaykrishnan Narayanan, Yuan Xie, Chung-Ta King:
TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network. HPCA 2013: 390-399 - 2012
- [c2]Matthew Poremba, Yuan Xie:
NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories. ISVLSI 2012: 392-397 - 2010
- [c1]Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie:
Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip. ICCAD 2010: 477-482
Coauthor Index
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