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2020 – today
- 2024
[c23]Zhenhui Dai, Jiawei Wang, Yi Zhong, Kunyu Feng, Cheng Zhao, Yuanyuan Jiang, Peiyu Chen
, Yuan Wang, Dunshan Yu, Xiaoxin Cui:
An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow. ISCAS 2024: 1-5- 2023
- [j25]Ye Zhou, Wengao Lu, Shanzhe Yu, Dunshan Yu, Yacong Zhang, Zhongjian Chen:
A multichannel readout integrated circuit with column-wise pseudo differential extended counting ADCs for an uncooled infrared focal plane array based on silicon diodes. Microelectron. J. 139: 105909 (2023) - [j24]Yuxuan Zhao, Xinyan Cao, Jinlong Lin, Dunshan Yu, Xixin Cao:
Multimodal Affective States Recognition Based on Multiscale CNNs and Biologically Inspired Decision Fusion Model. IEEE Trans. Affect. Comput. 14(2): 1391-1403 (2023) - 2022
- [j23]Yisong Kuang, Xiaoxin Cui, Zilin Wang, Chenglong Zou, Yi Zhong, Kefei Liu, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang:
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1631-1641 (2022) - [c22]Yisong Kuang, Xiaoxin Cui, Chenglong Zou, Yi Zhong, Zhenhui Dai, Zilin Wang, Kefei Liu, Dunshan Yu, Yuan Wang:
An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight. ISCAS 2022: 3468-3472 - 2021
- [j22]Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Yuan Wang, Dunshan Yu, Ru Huang:
A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2655-2659 (2021) - [c21]Timothy Dunlap, Omid Aramoon, Gang Qu, Tian Wang, Xiaoxin Cui, Dunshan Yu:
A Novel Circuit Authentication Scheme Based on Partial Polymorphic Gates. AsianHOST 2021: 1-4 - [c20]Ye Zhou, Shanzhe Yu, Wengao Lu, Dunshan Yu, Yacong Zhang, Zhongjian Chen:
Low Power Readout Integrated Circuit with PFM-based ADCs Employing Residue Quantization for Uncooled Infrared Imagers. ASICON 2021: 1-4 - [c19]Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang:
A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. ISCAS 2021: 1-5 - 2020
- [j21]Yinxuan Lyu, Jianhua Feng, Kai Zhu, Hongfei Ye, Dunshan Yu:
Fully on-chip clock jitter and skew measurement scheme via incoherent subsampling. Microelectron. J. 96: 104684 (2020) - [c18]Yuxuan Zhao, Jin Yang, Jinlong Lin, Dunshan Yu, Xixin Cao:
A 3D Convolutional Neural Network for Emotion Recognition based on EEG Signals. IJCNN 2020: 1-6
2010 – 2019
- 2019
- [j20]Weijun Lu, Chao Geng, Dunshan Yu:
A New Method for Futures Price Trends Forecasting Based on BPNN and Structuring Data. IEICE Trans. Inf. Syst. 102-D(9): 1882-1886 (2019) - [c17]Yi-Hsiang Chen, Xiaoxin Cui, Kanglin Xiao, Dunshan Yu:
Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing. ASICON 2019: 1-4 - [c16]Lingjuan Wu, Wenqian Zhao, Dunshan Yu:
Designing a 3D Graphics Processor for Mobile Applications. ASICON 2019: 1-4 - [c15]Hao Xie, Guoqing Xiang, Dunshan Yu, Hong Yu, Yuan Li, Wei Yan:
Perceptual Fast CU Size Decision Algorithm for AVS2 Intra Coding. BigMM 2019: 277-281 - [c14]Qi Zhang, Jian Cao, Ying Zhang, Shiguang Zhang, Quan Zhang, Dunshan Yu:
FPGA Implementation of Quantized Convolutional Neural Networks. ICCT 2019: 1605-1610 - [i1]Yuxuan Zhao, Xinyan Cao, Jinlong Lin, Dunshan Yu, Xixin Cao:
Multimodal Emotion Recognition Model using Physiological Signals. CoRR abs/1911.12918 (2019) - 2018
- [j19]Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Dunshan Yu, Xiaole Cui:
Design of Low-Power High-Performance FinFET Standard Cells. Circuits Syst. Signal Process. 37(5): 1789-1806 (2018) - [j18]Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui:
Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1922-1929 (2018) - [c13]Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui:
Polymorphic gate based IC watermarking techniques. ASP-DAC 2018: 90-96 - [c12]Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui:
A Novel Polymorphic Gate Based Circuit Fingerprinting Technique. ACM Great Lakes Symposium on VLSI 2018: 141-146 - [c11]Yinxuan Lyu, Jianhua Feng, Chenfeng Tu, Linqi Shi, Hongfei Ye, Weixin Gai, Dunshan Yu:
A 108fsrms 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching. ISCAS 2018: 1-5 - 2017
- [j17]Nan Liao, Xiaoxin Cui, Kai Liao, Tian Wang, Dunshan Yu, Xiaole Cui:
Improving DFA attacks on AES with unknown and random faults. Sci. China Inf. Sci. 60(4): 42401 (2017) - [j16]Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui:
High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ). IEEE Trans. Ind. Electron. 64(1): 727-738 (2017) - [c10]Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui, Gang Qu:
A practical cold boot attack on RSA private keys. AsianHOST 2017: 55-60 - 2016
- [j15]Yanbin Zhang, Weijun Lu, Ruiyuan Liu, Dunshan Yu:
Improving tracking accuracy with subcarrier assistance and code monitoring for BOC modulated signal. Comput. Electr. Eng. 53: 374-384 (2016) - [j14]Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui:
Ultralow-power high-speed flip-flop based on multimode FinFETs. Sci. China Inf. Sci. 59(4): 042404:1-042404:11 (2016) - [j13]Weijun Lu, Yanbin Zhang, Dengyun Lei, Dunshan Yu:
Efficient Weak Signals Acquisition Strategy for GNSS Receivers. IEICE Trans. Commun. 99-B(1): 288-295 (2016) - [j12]Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Xiaole Cui, Dunshan Yu:
Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology. IEICE Trans. Electron. 99-C(8): 974-983 (2016) - 2015
- [j11]Kaisheng Ma, Xiaoxin Cui, Kai Liao, Nan Liao, Di Wu, Dunshan Yu:
Key characterization factors of accurate power modeling for FinFET circuits. Sci. China Inf. Sci. 58(2): 1-13 (2015) - [j10]Dengyun Lei, Weijun Lu, Yanbin Zhang, Dunshan Yu:
Balance Differential Coherent Bit Synchronization Algorithm for GNSS Receiver. IEICE Trans. Commun. 98-B(6): 1133-1140 (2015) - [c9]Nan Liao, Xiaoxin Cui, Tian Wang, Kai Liao, Yewen Ni, Dunshan Yu, Xiaole Cui:
A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications. ASICON 2015: 1-4 - [c8]Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui:
Employing the mixed FBB/RBB in the design of FinFET logic gates. ASICON 2015: 1-4 - 2014
- [j9]Nan Liao, Xiaoxin Cui, Kai Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu:
Low power adiabatic logic based on FinFETs. Sci. China Inf. Sci. 57(2): 1-13 (2014) - [j8]Kai Liao, Xiaoxin Cui, Nan Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu:
Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs. Sci. China Inf. Sci. 57(4): 1-13 (2014) - [j7]Dengyun Lei, Weijun Lu, Dunshan Yu:
Resource-efficient acquisition architecture for BOC-modulated signals. IEICE Electron. Express 11(11): 20140358 (2014) - [j6]Yanbin Zhang, WeiJun Lu, Dengyun Lei, Yongcan Huang, Dunshan Yu:
Effective PPS Signal Generation with Predictive Synchronous Loop for GPS. IEICE Trans. Commun. 97-B(8): 1742-1749 (2014) - [c7]Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Xiao Zhang, Ying Huang, Dunshan Yu:
High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2m). ISCAS 2014: 818-821 - 2013
- [j5]Lingjuan Wu, Ryan Kastner, Bo Gu, Dunshan Yu:
Design of a Reconfigurable Acoustic Modem for Underwater Sensor Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(4): 821-823 (2013) - [j4]Ran Fang, Wengao Lu, Guannan Wang, Tingting Tao, Yacong Zhang, Zhongjian Chen, Dunshan Yu:
A Low-noise High-voltage Interface Circuit for capacitive MEMS gyroscope. J. Circuits Syst. Comput. 22(9) (2013) - [j3]Ran Fang, Wengao Lu, Guannan Wang, Tingting Tao, Yacong Zhang, Zhongjian Chen, Dunshan Yu:
A capacitive Interface Circuit with capacitor mismatch Auto-compensation for MEMS gyroscope. J. Circuits Syst. Comput. 22(10) (2013) - [c6]Xiaoxin Cui, Kaisheng Ma, Kai Liao, Nan Liao, Di Wu, Wei Wei, Rui Li, Dunshan Yu:
A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs. ISCAS 2013: 129-132 - 2011
- [c5]Xun Jiang, Xiaoxin Cui, Dunshan Yu:
A JTAG-based configuration circuit applied in SerDes chip. ASICON 2011: 707-710
2000 – 2009
- 2009
- [j2]Teng Lin, Jianhua Feng, Dunshan Yu:
Application-Dependent Interconnect Testing of Xilinx FPGAs Based on Line Branches Partitioning. IEICE Trans. Inf. Syst. 92-D(5): 1197-1199 (2009) - [j1]WeiJun Lu, Ying Li, Dunshan Yu, Xing Zhang:
A Low Cost Correlator Structure in the Pseudo-Noise Code Acquisition System. IEICE Trans. Commun. 92-B(5): 1888-1891 (2009) - 2006
- [c4]Xin Zhang, Dunshan Yu, Shimin Sheng:
A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs. APCCAS 2006: 9-12 - [c3]Xiaoxin Cui, Dunshan Yu, Shimin Sheng, Xiaole Cui:
Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm. APCCAS 2006: 1753-1756 - [c2]Shiqun Zhang, Dunshan Yu, Shimin Sheng:
A Discrete STFT Processor for Real-time Spectrum Analysis. APCCAS 2006: 1943-1946 - [c1]Xixin Cao, Qingqing Xie, Chungan Peng, Qingchun Wang, Dunshan Yu:
An Efficient VLSI Implementation of Distributed Architecture for DWT. MMSP 2006: 364-367
Coauthor Index
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last updated on 2024-10-07 22:24 CEST by the dblp team
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