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ORCIDSeetal Potluri
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2020 – today
- 2024
[i7]Seetal Potluri, Farinaz Koushanfar:
SoK: Model Reverse Engineering Threats for Neural Network Hardware. IACR Cryptol. ePrint Arch. 2024: 913 (2024)- 2023
- [j13]Seetal Potluri
, Shamik Kundu, Akash Kumar, Kanad Basu, Aydin Aysu:
SeqL+: Secure Scan-Obfuscation With Theoretical and Empirical Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1406-1410 (2023) - [c21]Shui Jiang, Seetal Potluri, Tsung-Yi Ho:
Scalable Scan-Chain-Based Extraction of Neural Network Models. DATE 2023: 1-6 - 2022
- [c20]Emre Karabulut, Chandu Yuvarajappa, Mohammed Iliyas Shaik, Seetal Potluri, Amro Awad, Aydin Aysu:
PR Crisis: Analyzing and Fixing Partial Reconfiguration in Multi-Tenant Cloud FPGAs. ASHES@CCS 2022: 101-106 - [c19]Furkan Aydin, Emre Karabulut, Seetal Potluri, Erdem Alkim, Aydin Aysu:
RevEAL: Single-Trace Side-Channel Leakage of the SEAL Homomorphic Encryption Library. DATE 2022: 1527-1532 - [c18]Hossein Sayadi, Mehrdad Aliasgari, Furkan Aydin, Seetal Potluri, Aydin Aysu, Jack Edmonds, Sara Tehranipoor:
Towards AI-Enabled Hardware Security: Challenges and Opportunities. IOLTS 2022: 1-10 - [i6]Furkan Aydin, Emre Karabulut, Seetal Potluri, Erdem Alkim, Aydin Aysu:
RevEAL: Single-Trace Side-Channel Leakage of the SEAL Homomorphic Encryption Library. IACR Cryptol. ePrint Arch. 2022: 204 (2022) - 2021
- [j12]Priyank Kashyap, Furkan Aydin, Seetal Potluri, Paul D. Franzon, Aydin Aysu:
2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(6): 1217-1229 (2021) - [c17]Gregor Haas, Seetal Potluri, Aydin Aysu:
iTimed: Cache Attacks on the Apple A10 Fusion SoC. HOST 2021: 80-90 - [c16]Seetal Potluri, Aydin Aysu:
Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware. ICCAD 2021: 1-8 - [i5]Seetal Potluri, Aydin Aysu:
Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware. IACR Cryptol. ePrint Arch. 2021: 167 (2021) - [i4]Gregor Haas, Seetal Potluri, Aydin Aysu:
iTimed: Cache Attacks on the Apple A10 Fusion SoC. IACR Cryptol. ePrint Arch. 2021: 464 (2021) - [i3]Seetal Potluri, Shamik Kundu, Akash Kumar, Kanad Basu, Aydin Aysu:
SeqL+: Secure Scan-Obfuscation with Theoretical and Empirical Validation. IACR Cryptol. ePrint Arch. 2021: 1245 (2021) - 2020
- [j11]Gokulkrishnan Vadakkeveedu, Kamakoti Veezhinathan, Nitin Chandrachoodan, Seetal Potluri:
Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips. IET Comput. Digit. Tech. 14(3): 122-131 (2020) - [j10]Huili Chen, Seetal Potluri, Farinaz Koushanfar:
Security of Microfluidic Biochip: Practical Attacks and Countermeasures. ACM Trans. Design Autom. Electr. Syst. 25(3): 27:1-27:29 (2020) - [c15]Francesco Regazzoni, Shivam Bhasin, Amir Alipour, Ihab Alshaer, Furkan Aydin, Aydin Aysu, Vincent Beroulle, Giorgio Di Natale, Paul D. Franzon, David Hély, Naofumi Homma, Akira Ito, Dirmanto Jap, Priyank Kashyap, Ilia Polian, Seetal Potluri, Rei Ueno, Elena Ioana Vatajelu, Ville Yli-Mäyry:
Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-. ICCAD 2020: 141:1-141:6 - [c14]Qinhan Tan, Seetal Potluri, Aydin Aysu:
Efficacy of Satisfiability-Based Attacks in the Presence of Circuit Reverse-Engineering Errors. ISCAS 2020: 1-5 - [c13]Seetal Potluri, Aydin Aysu, Akash Kumar:
SeqL: Secure Scan-Locking for IP Protection. ISQED 2020: 7-13 - [c12]Huili Chen, Seetal Potluri, Farinaz Koushanfar:
FlowTrojan: Insertion and Detection of Hardware Trojans on Flow-Based Microfluidic Biochips. NEWCAS 2020: 158-161 - [c11]Furkan Aydin, Priyank Kashyap, Seetal Potluri, Paul D. Franzon, Aydin Aysu:
DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks. SAMOS 2020: 262-280 - [i2]Seetal Potluri, Aydin Aysu, Akash Kumar:
SeqL: Secure Scan-Locking for IP Protection. CoRR abs/2005.13032 (2020) - [i1]Qinhan Tan, Seetal Potluri, Aydin Aysu:
Efficacy of Satisfiability Based Attacks in the Presence of Circuit Reverse Engineering Errors. CoRR abs/2005.13048 (2020)
2010 – 2019
- 2019
- [j9]Seetal Potluri, Paul Pop, Jan Madsen:
Design-for-Testability of On-Chip Control in mVLSI Biochips. IEEE Des. Test 36(1): 48-56 (2019) - 2018
- [j8]Patanjali SLPSK, Milan Patnaik, Seetal Potluri, V. Kamakoti:
MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis. J. Low Power Electron. 14(2): 285-301 (2018) - 2017
- [j7]Satya Trinadh Adireddy, Seetal Potluri, Ch. Sobhan Babu, Veezhinathan Kamakoti, Shiv Govind Singh:
Optimal Don't Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing. ACM Trans. Design Autom. Electr. Syst. 23(1): 5:1-5:26 (2017) - [c10]Seetal Potluri, Aaron Mathew, Rambabu Nerukonda, Ismed Hartanto, Shahin Toutounchi:
Cell-Aware ATPG to Improve Defect Coverage for FPGA IPs and Next Generation Zynq® MPSoCs. ATS 2017: 157-162 - [c9]Seetal Potluri, Alexander Schneider, Martin Horslev-Petersen, Paul Pop, Jan Madsen:
Synthesis of on-chip control circuits for mVLSI biochips. DATE 2017: 1799-1804 - [c8]Gokulkrishnan Vadakkeveedu, V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri:
A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips. DFT 2017: 1-4 - [c7]Huili Chen, Seetal Potluri, Farinaz Koushanfar:
BioChipWork: Reverse Engineering of Microfluidic Biochips. ICCD 2017: 9-16 - 2016
- [j6]Sanjay Burman, Seetal Potluri, Debdeep Mukhopadhyay, Kamakoti Veezhinathan:
Power Consumption versus Hardware Security: Feasibility Study of Differential Power Attack on Linear Feedback Shift Register Based Stream Ciphers and Its Countermeasures. J. Low Power Electron. 12(2): 99-106 (2016) - [c6]Morten Chabert Eskesen, Paul Pop, Seetal Potluri:
Architecture synthesis for cost-constrained fault-tolerant flow-based biochips. DATE 2016: 618-623 - [c5]Seetal Potluri, Satya Trinadh, Siddhant Saraf, Kamakoti Veezhinathan:
Component fault localization using switching current measurements. ETS 2016: 1-2 - 2015
- [j5]Seetal Potluri, Satya Trinadh, Ch. Sobhan Babu, V. Kamakoti, Nitin Chandrachoodan:
DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing. ACM Trans. Design Autom. Electr. Syst. 21(1): 14:1-14:25 (2015) - [c4]Satya Trinadh, Ch. Sobhan Babu, Shiv Govind Singh, Seetal Potluri, V. Kamakoti:
DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests. DATE 2015: 836-841 - 2014
- [j4]Satya Trinadh, Seetal Potluri, Shankar Balachandran, Ch. Sobhan Babu, V. Kamakoti:
XStat: Statistical X-Filling Algorithm for Peak Capture Power Reduction in Scan Tests. J. Low Power Electron. 10(1): 107-115 (2014) - 2013
- [j3]Satya Trinadh, Seetal Potluri, Ch. Sobhan Babu, V. Kamakoti:
An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test. J. Low Power Electron. 9(2): 264-274 (2013) - [c3]Seetal Potluri, Satya Trinadh, Roopashree Baskaran, Nitin Chandrachoodan, V. Kamakoti:
PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information. ETS 2013: 1 - [c2]Seetal Potluri, Satya Trinadh Adireddy, Chidhambaranathan Rajamanikkam, Shankar Balachandran:
LPScan: An algorithm for supply scaling and switching activity minimization during test. ICCD 2013: 463-466 - 2012
- [j2]Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti:
Interconnect Aware Test Power Reduction. J. Low Power Electron. 8(4): 516-525 (2012) - [j1]Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti:
Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. J. Low Power Electron. 8(5): 684-695 (2012) - 2011
- [c1]Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti:
Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. ISVLSI 2011: 319-320
Coauthor Index
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