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ORCIDRohit Kapur
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2020 – today
- 2021
[j23]Pralhadrao V. Shantagiri
, Rohit Kapur, Chandrasekar Shastry:
New scan compression approach to reduce the test data volume. IET Comput. Digit. Tech. 15(4): 251-262 (2021)- 2020
- [j22]Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur:
A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 546-550 (2020)
2010 – 2019
- 2018
- [j21]Pralhadrao V. Shantagiri, Rohit Kapur:
Handling Unknown with Blend of Scan and Scan Compression. J. Electron. Test. 34(2): 135-146 (2018) - [i1]Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur:
Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits. CoRR abs/1801.04961 (2018) - 2017
- [c64]Subhadip Kundu, Kuldip Kumar, Rishi Kumar, Rohit Kapur:
Diagnosing multiple faulty chains with low pin convolution compressor using compressed production test set. ITC 2017: 1-7 - [c63]Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur:
Enhancing security of logic encryption using embedded key generation unit. ITC-Asia 2017: 131-136 - [c62]Kanad Basu, Rishi Kumar, Santosh Kulkarni, Rohit Kapur:
Deterministic Shift Power Reduction in Test Compression. VDAT 2017: 155-167 - [c61]Rajit Karmakar, N. Prasad, Santanu Chattopadhyay, Rohit Kapur, Indranil Sengupta:
A New Logic Encryption Strategy Ensuring Key Interdependency. VLSID 2017: 429-434 - 2016
- [j20]Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Small Test Set Generation with High Diagnosability. J. Circuits Syst. Comput. 25(4): 1650024:1-1650024:18 (2016) - [c60]Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur:
Handling wrong mapping: A new direction towards better diagnosis with low pin convolution compressors. ITC 2016: 1-7 - 2015
- [j19]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1185-1195 (2015) - [c59]Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur:
Fault diagnosis in designs with extreme low pin test data compressors. DATE 2015: 1285-1288 - [c58]Subramanian Chebiyam, Anshuman Chandra, Rohit Kapur:
Designing effective scan compression solutions for industrial circuits. ISQED 2015: 167-172 - [c57]Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
GA based diagnostic test pattern generation for transition faults. VDAT 2015: 1-6 - [c56]Anshuman Chandra, Santosh Kulkarni, Subramanian Chebiyam, Rohit Kapur:
Designing efficient combinational compression architecture for testing industrial circuits. VDAT 2015: 1-6 - 2014
- [j18]Subhadip Kundu, Aniket Jha, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Framework for Multiple-Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 696-700 (2014) - [c55]Anshuman Chandra, Subramanian Chebiyam, Rohit Kapur:
A Case Study on Implementing Compressed DFT Architecture. ATS 2014: 336-341 - [c54]Swapnil Bahl, Shreyans Rungta, Shray Khullar, Rohit Kapur, Anshuman Chandra, Salvatore Talluto, Pramod Notiyath, Ajay Rajagopalan:
Unifying scan compression. DFT 2014: 191-196 - [c53]Rohit Kapur, Irith Pomeranz:
Innovative practices session 10C: Advances in DFT and compression. VTS 2014: 1 - 2013
- [j17]Subhadip Kundu, Sankhadeep Pal, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
A Metric for Test Set Characterization and Customization Toward Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1824-1828 (2013) - [c52]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
An ATE assisted DFD technique for volume diagnosis of scan chains. DAC 2013: 31:1-31:6 - [c51]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Aggresive scan chain masking for improved diagnosis of multiple scan chain failures. ETS 2013: 1 - 2012
- [c50]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection. VLSI Design 2012: 436-441 - 2011
- [c49]Uzair Shah Syed, Krishnendu Chakrabarty, Anshuman Chandra, Rohit Kapur:
3D-Scalable Adaptive Scan (3D-SAS). 3DIC 2011: 1-6 - [c48]Jyotirmoy Saikia, Pramod Notiyath, Santosh Kulkarni, Ashok Anbalan, Rajesh Uppuluri, Tammy Fernandes, Parthajit Bhattacharya, Rohit Kapur:
Predicting Scan Compression IP Configurations for Better QoR. Asian Test Symposium 2011: 261-266 - [c47]Anshuman Chandra, Jyotirmoy Saikia, Rohit Kapur:
Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C). Asian Test Symposium 2011: 432-437 - [c46]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. VLSI Design 2011: 364-369 - [c45]Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg:
Special session 5B: Panel How much toggle activity should we be testing with? VTS 2011: 114 - 2010
- [j16]Rohit Kapur:
Conference Reports. IEEE Des. Test Comput. 27(2): 75 (2010) - [j15]Rohit Kapur:
Conference Reports. IEEE Des. Test Comput. 27(3): 75 (2010) - [j14]Rohit Kapur:
Conference Reports. IEEE Des. Test Comput. 27(4): 77 (2010)
2000 – 2009
- 2009
- [j13]Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller:
CTL and Its Usage in the EDA Industry. IEEE Des. Test Comput. 26(1): 36-43 (2009) - [c44]Anshuman Chandra, Rohit Kapur, Yasunari Kanzawa:
Scalable Adaptive Scan (SAS). DATE 2009: 1476-1481 - [c43]Anshuman Chandra, Yasunari Kanzawa, Rohit Kapur:
Proactive management of X's in scan chains for compression. ISQED 2009: 260-265 - 2008
- [j12]Rohit Kapur, Subhasish Mitra, Thomas W. Williams:
Historical Perspective on Scan Compression. IEEE Des. Test Comput. 25(2): 114-120 (2008) - [c42]Anshuman Chandra, Rohit Kapur:
Not All Xs are Bad for Scan Compression. ATS 2008: 7-12 - [c41]Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, Thomas W. Williams:
Evaluation of Entropy Driven Compression Bounds on Industrial Designs. ATS 2008: 13-18 - [c40]Anshuman Chandra, Felix Ng, Rohit Kapur:
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction. DATE 2008: 462-467 - [c39]Anshuman Chandra, Rohit Kapur:
Interval Based X-Masking for Scan Compression Architectures. ISQED 2008: 821-826 - [c38]Anshuman Chandra, Rohit Kapur:
Bounded Adjacent Fill for Low Capture Power Scan Testing. VTS 2008: 131-138 - 2007
- [j11]Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri:
DFT MAX and Power. J. Low Power Electron. 3(2): 199-205 (2007) - [c37]Rajesh Galivanche, Rohit Kapur, Antonio Rubio:
Testing in the year 2020. DATE 2007: 960-965 - [c36]Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams:
Accurately Determining Bridging Defects from Layout. DDECS 2007: 87-90 - [c35]Rohit Kapur, Jindrich Zejda, Thomas W. Williams:
Fundamentals of timing information for test: How simple can we get? ITC 2007: 1-7 - [c34]Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini:
Minimizing the Impact of Scan Compression. VTS 2007: 67-74 - [c33]Anshuman Chandra, Haihua Yan, Rohit Kapur:
Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction. VTS 2007: 84-92 - 2006
- [c32]Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie:
OCI: Open Compression Interface. ITC 2006: 1-4 - 2005
- [c31]Rohit Kapur:
Test the test experts: do we know what we are doing? ITC 2005: 1 - [c30]Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur:
Efficient compression of deterministic patterns into multiple PRPG seeds. ITC 2005: 10 - 2004
- [c29]Rohit Kapur:
Security vs. Test Quality: Are they mutually exclusive? ITC 2004: 1414 - [c28]Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams:
Changing the Scan Enable during Shift. VTS 2004: 73-78 - 2003
- [j10]Bruce Cory, Rohit Kapur, Bill Underwood:
Speed Binning with Path Delay Test in 150-nm Technology. IEEE Des. Test Comput. 20(5): 41-45 (2003) - [c27]Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch:
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. DATE 2003: 10110-10115 - [c26]Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur:
Overview of the IEEE P1500 Standard. ITC 2003: 988-997 - [c25]Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams:
A Reconfigurable Shared Scan-in Architecture. VTS 2003: 9-14 - 2002
- [j9]Samitha Samaranayake, Nodari Sitchinava, Rohit Kapur, Minesh B. Amin, Thomas W. Williams:
Dynamic Scan: Driving Down the Cost of Test. Computer 35(10): 63-68 (2002) - [j8]Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian:
On IEEE P1500's Standard for Embedded Core Test. J. Electron. Test. 18(4-5): 365-383 (2002) - [c24]Rohit Kapur, Thomas W. Williams:
Manufacturing Test of SoCs. Asian Test Symposium 2002: 317-319 - [c23]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC 2002: 371-374 - [c22]Rohit Kapur, Thomas W. Williams, M. Ray Mercer:
Directed-Binary Search in Logic BIST Diagnostics. DATE 2002: 1121 - [c21]Nahmsuk Oh, Rohit Kapur, Thomas W. Williams:
Fast seed computation for reseeding shift register in test pattern compression. ICCAD 2002: 76-81 - [c20]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC 2002: 407-416 - [c19]Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur:
Integrating DFT in the Physical Synthesis Flow. ITC 2002: 788-795 - 2001
- [j7]Rohit Kapur, R. Chandramouli, Thomas W. Williams:
Strategies for Low-Cost Test. IEEE Des. Test Comput. 18(6): 47-54 (2001) - [c18]Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay:
CTL the language for describing core-based test. ITC 2001: 131-139 - [c17]Rohit Kapur, Thomas W. Williams:
Tester retargetable patterns. ITC 2001: 721-727 - [c16]Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir:
A new methodology for improved tester utilization. ITC 2001: 916-923 - [c15]Dwayne Burek, Garen Darbinyan, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti:
IP and Automation to Support IEEE P1500. VTS 2001: 411-412 - 2000
- [j6]Rohit Kapur, Cy Hay, Thomas W. Williams:
The Mutating Metric for Benchmarking Test. IEEE Des. Test Comput. 17(3): 18-21 (2000) - [c14]Farhad Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu:
DFT closure. Asian Test Symposium 2000: 8-9 - [c13]Thomas W. Williams, Rohit Kapur:
Design for Testability in Nanometer Technologies; Searching for Quality. ISQED 2000: 167-172 - [c12]Yervant Zorian, Erik Jan Marinissen, Rohit Kapur:
On using IEEE P1500 SECT for test plug-n-play. ITC 2000: 770-777
1990 – 1999
- 1999
- [j5]Rohit Kapur, Thomas W. Williams:
Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction. Computer 32(11): 42-45 (1999) - [c11]Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel:
Towards a standard for embedded core test: an example. ITC 1999: 616-627 - [c10]Rohit Kapur:
High level ATPG is important and is on its way! ITC 1999: 1115-1116 - 1997
- [j4]Magdy S. Abadir, Rohit Kapur:
Cost-Driven Ranking of Memory Elements for Partial Intrusion. IEEE Des. Test Comput. 14(3): 45-50 (1997) - 1996
- [j3]Rohit Kapur, Edward F. Miller:
System Test and Reliability: Techniques for Avoiding Failure (Guest Editors' Introduction). Computer 29(11): 28-30 (1996) - [j2]Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams:
A weighted random pattern test generation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8): 1020-1025 (1996) - [c9]Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly:
Iddq Testing for High Performance CMOS - The Next Ten Years. ED&TC 1996: 578-583 - [c8]Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly:
IDDQ Test: Sensitivity Analysis of Scaling. ITC 1996: 786-792 - 1994
- [c7]Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams:
Design of an Efficient Weighted-Random-Pattern Generation System. ITC 1994: 491-500 - [c6]Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams:
Limitations in predicting defect level based on stuck-at fault coverage. VTS 1994: 186-191 - 1992
- [j1]Rohit Kapur, M. Ray Mercer:
Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes. IEEE Trans. Computers 41(12): 1580-1588 (1992) - [c5]M. Ray Mercer, Rohit Kapur, Don E. Ross:
Functional Approaches to Generating Orderings for Efficient Symbolic Representations. DAC 1992: 624-627 - [c4]Rohit Kapur, Jaehong Park, M. Ray Mercer:
All Tests for a Fault Are Not Equally Valuable for Defect Detection. ITC 1992: 762-769 - [c3]Kenneth M. Butler, Rohit Kapur, M. Ray Mercer, Don E. Ross:
The roles of controllability and observability in design for test. VTS 1992: 211-216 - 1991
- [c2]Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer:
Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. DAC 1991: 417-420 - [c1]Don E. Ross, Kenneth M. Butler, Rohit Kapur, M. Ray Mercer:
Fast functional evaluation of candidate OBDD variable orderings. EURO-DAC 1991: 4-10
Coauthor Index
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