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ORCIDKeiji Kimura
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2020 – today
- 2024
[j22]Keiji Kimura
, Bryan R. Moser:
Engineering systems analysis of mobility in Odawara city: New transportation services impacts on community engagement. Syst. Eng. 27(3): 499-519 (2024)- 2023
- [j21]Dina Aboutahoun, Rami Zewail, Keiji Kimura, Mostafa I. Soliman:
Lightweight Histological Tumor Classification Using a Joint Sparsity-Quantization Aware Training Framework. IEEE Access 11: 119342-119351 (2023) - [c49]Dina Aboutahoun, Rami Zewail, Keiji Kimura, Mostafa I. Soliman:
Cross-Domain Few-Shot Sparse-Quantization Aware Learning for Lymphoblast Detection in Blood Smear Images. ACPR (3) 2023: 213-226 - [c48]Akihiro Saiki, Yu Omori, Keiji Kimura:
Parallel Verification in RISC-V Secure Boot. MCSoC 2023: 568-575 - 2022
- [j20]Mostafa M. Abbas, Mostafa I. Soliman, Sherif I. Rabia, Keiji Kimura, Ahmed El-Mahdy:
Accelerating Data Dependence Profiling Through Abstract Interpretation of Loop Instructions. IEEE Access 10: 31626-31640 (2022) - [j19]Yu Omori, Keiji Kimura:
Open-Source Hardware Memory Protection Engine Integrated With NVMM Simulator. IEEE Comput. Archit. Lett. 21(2): 77-80 (2022) - [j18]Christophe Cérin, Keiji Kimura, Mamadou Sow:
Data stream clustering for low-cost machines. J. Parallel Distributed Comput. 166: 57-70 (2022) - [c47]Tohma Kawasumi, Yuta Tsumura, Hiroki Mikami, Tomoya Yoshikawa, Takero Hosomi, Shingo Oidate, Keiji Kimura, Hironori Kasahara:
Parallelizing Factory Automation Ladder Programs by OSCAR Automatic Parallelizing Compiler. LCPC 2022: 123-138 - [c46]Hugo Thievenaz, Keiji Kimura, Christophe Alias:
Lightweight Array Contraction by Trace-Based Polyhedral Analysis. ISC Workshops 2022: 20-32 - 2021
- [j17]Jonas T. Agyepong, Mostafa Soliman, Yasutaka Wada, Keiji Kimura, Ahmed El-Mahdy:
Secure Image Inference Using Pairwise Activation Functions. IEEE Access 9: 118271-118290 (2021) - [j16]Yu Omori, Keiji Kimura:
Non-Volatile Main Memory Emulator for Embedded Systems Employing Three NVMM Behaviour Models. IEICE Trans. Inf. Syst. 104-D(5): 697-708 (2021) - [j15]Jixin Han, Keiji Kimura:
Durable Queue Implementations Built on a Formally Defined Strand Persistency Model. J. Inf. Process. 29: 823-838 (2021) - [c45]Jixin Han, Tomofumi Yuki, Michelle Mills Strout, Dan Umeda, Hironori Kasahara, Keiji Kimura:
Parallelizing Compiler Translation Validation Using Happens-Before and Task-Set. CANDAR (Workshops) 2021: 87-93 - [c44]Birk Martin Magnussen, Tohma Kawasumi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara:
Performance Evaluation of OSCAR Multi-target Automatic Parallelizing Compiler on Intel, AMD, Arm and RISC-V Multicores. LCPC 2021: 50-64 - [c43]Hironori Kasahara, Keiji Kimura, Toshiaki Kitamura, Hiroki Mikami, Kazutaka Morita, Kazuki Fujita, Kazuki Yamamoto, Tohma Kawasumi:
OSCAR Parallelizing and Power Reducing Compiler and API for Heterogeneous Multicores : (Invited Paper). PEHC@SC 2021: 10-19 - 2020
- [j14]Boma A. Adhi, Tomoya Kashimata, Ken Takahashi, Keiji Kimura, Hironori Kasahara:
Compiler Software Coherent Control for Embedded High Performance Multicore. IEICE Trans. Electron. 103-C(3): 85-97 (2020) - [j13]Yoshitake Oki, Yuto Abe, Kazuki Yamamoto, Kohei Yamamoto, Tomoya Shirakawa, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara:
Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler. IEICE Trans. Electron. 103-C(3): 98-109 (2020) - [j12]Reem Elkhouly, Mohammad A. Alshboul, Akihiro Hayashi, Yan Solihin, Keiji Kimura:
Compiler-support for Critical Data Persistence in NVM. ACM Trans. Archit. Code Optim. 16(4): 54:1-54:25 (2020) - [c42]Ardhi Wiratama Baskara Yudha, Keiji Kimura, Huiyang Zhou, Yan Solihin:
Scalable and Fast Lazy Persistency on GPUs. IISWC 2020: 252-263
2010 – 2019
- 2019
- [j11]Mohammad A. Alshboul, Hussein Elnawawy, Reem Elkhouly, Keiji Kimura, James Tuck, Yan Solihin:
Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory. ACM Trans. Archit. Code Optim. 16(2): 18:1-18:27 (2019) - [c41]Tohma Kawasumi, Ryota Tamura, Yuya Asada, Jixin Han, Hiroki Mikami, Keiji Kimura, Hironori Kasahara:
Fast and Highly Optimizing Separate Compilation for Automatic Parallelization. HPCS 2019: 478-485 - [c40]Yoshitake Oki, Hiroki Mikami, Hikaru Nishida, Dan Umeda, Keiji Kimura, Hironori Kasahara:
Performance of Static and Dynamic Task Scheduling for Real-Time Engine Control System on Embedded Multicore Processor. LCPC 2019: 1-14 - [c39]Yu Omori, Keiji Kimura:
Performance Evaluation on NVMM Emulator Employing Fine-Grain Delay Injection. NVMSA 2019: 1-6 - [c38]Tomoya Kashimata, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara:
Cascaded DMA Controller for Speedup of Indirect Memory Access in Irregular Applications. IA3@SC 2019: 71-76 - 2018
- [j10]Keiji Kimura, Hayato Waki:
Minimization of Akaike's information criterion in linear regression analysis via mixed integer nonlinear program. Optim. Methods Softw. 33(3): 633-649 (2018) - [c37]Cristina Seceleanu, Keiji Kimura:
Message from the CAP Organizing Committee. COMPSAC (1) 2018: 667 - 2017
- [j9]Keiji Kimura, Hayato Waki, Masaya Yasuda:
Application of mixed integer quadratic program to shortest vector problems. JSIAM Lett. 9: 65-68 (2017) - [c36]Hironori Kasahara, Keiji Kimura, Boma A. Adhi, Yuhei Hosokawa, Yohei Kishimoto, Masayoshi Mase:
Multicore Cache Coherence Control by a Parallelizing Compiler. COMPSAC (1) 2017: 492-497 - [c35]Boma A. Adhi, Masayoshi Mase, Yuhei Hosokawa, Yohei Kishimoto, Taisuke Onishi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara:
Software Cache Coherent Control by Parallelizing Compiler. LCPC 2017: 17-25 - [p1]Keiji Kimura, Hayato Waki:
A Mixed Integer Quadratic Formulation for the Shortest Vector Problem. CREST Crypto-Math Project 2017: 239-255 - 2016
- [j8]Bui Duc Binh, Tomohiro Hirano, Hiroki Mikami, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara:
Android Video Processing System Combined with Automatically Parallelized and Power Optimized Code by OSCAR Compiler. J. Inf. Process. 24(3): 504-511 (2016) - [c34]Bui Duc Binh, Keiji Kimura:
An Android Systrace Extension for Tracing Wakelocks. CSE/EUC/DCABES 2016: 146-149 - [c33]Keiji Kimura, Hayato Waki:
Mixed Integer Nonlinear Program for Minimization of Akaike's Information Criterion. ICMS 2016: 292-300 - [c32]Kouhei Yamamoto, Tomoya Shirakawa, Yoshitake Oki, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara:
Automatic Local Memory Management for Multicores Having Global Address Space. LCPC 2016: 282-296 - [c31]Lau Phi Tuong, Keiji Kimura:
2-Step Power Scheduling with Adaptive Control Interval for Network Intrusion Detection Systems on Multicores. MCSoC 2016: 69-76 - [c30]Keiji Kimura, Gakuho Taguchi, Hironori Kasahara:
Accelerating Multicore Architecture Simulation Using Application Profile. MCSoC 2016: 177-184 - [c29]Koichiro Yamashita, Takahisa Suzuki, Hongchun Li, Chen Ao, Yi Xu, Jun Tian, Keiji Kimura, Hironori Kasahara:
Architecture Design for the Environmental Monitoring System over the Winter Season. MobiWac 2016: 27-34 - [c28]Jixin Han, Rina Fujino, Ryota Tamura, Mamoru Shimaoka, Hiroki Mikami, Moriyuki Takamura, Sachio Kamiya, Kazuhiko Suzuki, Takahiro Miyajima, Keiji Kimura, Hironori Kasahara:
Reducing parallelizing compilation time by removing redundant analysis. SEPS@SPLASH 2016: 1-9 - [i1]Reem Elkhouly, Keiji Kimura, Ahmed El-Mahdy:
If-Conversion Optimization using Neuro Evolution of Augmenting Topologies. CoRR abs/1603.01112 (2016) - 2015
- [c27]Dan Umeda, Takahiro Suzuki, Hiroki Mikami, Keiji Kimura, Hironori Kasahara:
Multigrain Parallelization for Model-Based Design Applications Using the OSCAR Compiler. LCPC 2015: 125-139 - [c26]Mamoru Shimaoka, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various Cc-NUMA Servers. LCPC 2015: 238-253 - [c25]Daichi Fukui, Mamoru Shimaoka, Hiroki Mikami, Dominic Hillenbrand, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara:
Annotatable systrace: an extended Linux ftrace for tracing a parallelized program. SEPS@SPLASH 2015: 21-25 - 2014
- [c24]Tomohiro Hirano, Hideo Yamamoto, Shuhei Iizuka, Kohei Muto, Takashi Goto, Tamami Wake, Hiroki Mikami, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara:
Evaluation of Automatic Power Reduction with OSCAR Compiler on Intel Haswell and ARM Cortex-A9 Multicores. LCPC 2014: 239-252 - 2013
- [c23]Dominic Hillenbrand, Akihiro Hayashi, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara:
Automatic parallelization, performance predictability and power control for mobile-applications. COOL Chips 2013: 1-3 - [c22]Yohei Kanehagi, Dan Umeda, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara:
Parallelization of automotive engine control software on embedded multi-core processor using OSCAR compiler. COOL Chips 2013: 1-3 - [c21]Hideo Yamamoto, Tomohiro Hirano, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara:
OSCAR Compiler Controlled Multicore Power Reduction on Android Platform. LCPC 2013: 155-168 - [c20]Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara:
Reconciling application power control and operating systems for optimal power and performance. ReCoSoC 2013: 1-8 - [e1]Hironori Kasahara, Keiji Kimura:
Languages and Compilers for Parallel Computing, 25th International Workshop, LCPC 2012, Tokyo, Japan, September 11-13, 2012, Revised Selected Papers. Lecture Notes in Computer Science 7760, Springer 2013, ISBN 978-3-642-37657-3 [contents] - 2012
- [j7]Yasir I. M. Al-Dosary, Keiji Kimura, Hironori Kasahara, Seinosuke Narita:
Enhancing the Performance of a Multiplayer Game by Using a Parallelizing Compiler. Int. J. Intell. Games Simul. 7(1): 14-23 (2012) - [c19]Yasir I. M. Al-Dosary, Keiji Kimura, Hironori Kasahara, Seinosuke Narita:
Enhancing the performance of a multiplayer game by using a parallelizing compiler. CGAMES 2012: 67-75 - 2011
- [j6]Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima:
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. IEICE Trans. Electron. 94-C(4): 663-669 (2011) - [j5]Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara:
A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture. Trans. High Perform. Embed. Archit. Compil. 4: 215-233 (2011) - [c18]Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo:
Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC 2011: 87-88 - [c17]Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, Hironori Kasahara:
Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-Power Multicore. LCPC 2011: 31-45 - 2010
- [c16]Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima:
A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC 2010: 100-101 - [c15]Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara:
Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores. LCPC 2010: 184-198
2000 – 2009
- 2009
- [c14]Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara:
Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. ICPP 2009: 510-517 - [c13]Keiji Kimura, Masayoshi Mase, Hiroki Mikami, Takamichi Miyamoto, Jun Shirako, Hironori Kasahara:
OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers. LCPC 2009: 188-202 - 2008
- [j4]Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Power-Aware Compiler Controllable Chip Multiprocessor. IEICE Trans. Electron. 91-C(4): 432-439 (2008) - [j3]Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. IEEE J. Solid State Circuits 43(4): 902-910 (2008) - [c12]Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Software-cooperative power-efficient heterogeneous multi-core for media processing. ASP-DAC 2008: 736-741 - [c11]Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara:
Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API. ISPA 2008: 600-607 - [c10]Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara:
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. ISSCC 2008: 90-91 - 2007
- [c9]Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Power-Aware Compiler Controllable Chip Multiprocessor. PACT 2007: 427 - [c8]Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara:
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. ISSCC 2007: 100-590 - 2005
- [c7]Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara:
Multigrain parallel processing on compiler cooperative chip multiprocessor. Interaction between Compilers and Computer Architectures 2005: 11-20 - [c6]Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara:
Performance Evaluation of Compiler Controlled Power Saving Scheme. ISHPC 2005: 480-493 - [c5]Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara:
Compiler Control Power Saving Scheme for Multi Core Processors. LCPC 2005: 362-376 - 2004
- [c4]Kazuhisa Ishizaka, Takamichi Miyamoto, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara:
Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers. LCPC 2004: 319-331 - 2003
- [j2]Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara:
Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP. Int. J. Parallel Program. 31(3): 211-223 (2003) - 2002
- [c3]Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara:
Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP. ISHPC 2002: 479-489 - [c2]Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka, Keiji Kimura, Hiroki Kaminaga, Hirofumi Nakano, Kouhei Nagasawa, Akiko Murai, Hiroki Itagaki, Jun Shirako:
Multigrain Automatic Parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler. PARELEC 2002: 105-111
1990 – 1999
- 1993
- [j1]Hajime Yamashina, Susumu Okumura, Keiji Kimura:
Detection of small cracks in the chain of a trolley conveyor with an infrared camera. J. Intell. Manuf. 4(4): 259-267 (1993)
1980 – 1989
- 1988
- [c1]Keiji Kimura, Akihide Demura, Tatsuya Igarashi, Yukio Takeyari:
CD-ROM System Based on the NEWS Workstation. COMPCON 1988: 274-277
Coauthor Index
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