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ORCIDDenis Deschacht
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2010 – 2019
- 2010
[j5]Jean-Etienne Lorival, Denis Deschacht:
Crosstalk pulsewidth calculation. Microelectron. J. 41(8): 474-479 (2010)
2000 – 2009
- 2006
- [j4]Denis Deschacht:
DSM interconnects: importance of inductance effects and corresponding range of length. IEEE Trans. Very Large Scale Integr. Syst. 14(7): 777-779 (2006) - 2005
- [c10]Denis Deschacht, Alain Lopez:
Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing Orientation. VLSI Design 2005: 640-643 - 2004
- [c9]Alain Lopez, Denis Deschacht:
Comparison between Different Data Buses Configurations. ISVLSI 2004: 69-76 - 2002
- [c8]Grégory Servel, Denis Deschacht, Françoise Saliou, Jean-Luc Mattei, Fabrice Huret:
Impact of Low-K on Crosstalk. ISQED 2002: 298-303 - 2001
- [c7]Denis Deschacht, Grégory Servel:
On-chip interconnections: impact of adjacent lines on timing. ASP-DAC 2001: 539-544 - 2000
- [c6]Grégory Servel, Denis Deschacht:
On-chip crosstalk evaluation between adjacent interconnections. ICECS 2000: 827-834 - [c5]Denis Deschacht, Grégory Servel, Fabrice Huret, Erick Paleczny, Patrick Kennis:
Theoretical limits for signal reflections due to inductance for on-chip interconnections. SLIP 2000: 55-60
1990 – 1999
- 1999
- [c4]Grégory Servel, L. B. Kenmei, Fabrice Huret, Erick Paleczny, Patrick Kennis, Denis Deschacht:
Inductance effect for interconnection timing analysis in submicronic circuits. ICECS 1999: 1407-1410 - 1996
- [j3]Denis Deschacht, Christophe Dabrin, Daniel Auvergne:
Delay propagation effect in transistor gates. IEEE J. Solid State Circuits 31(8): 1184-1189 (1996) - 1995
- [c3]Denis Deschacht, Christophe Dabrin:
A new and accurate interconnection delay time evaluation in a general tree-type network. ASP-DAC 1995 - 1993
- [j2]Denis Deschacht, Michel Robert
, Nadine Azémard-Crestani, Daniel Auvergne:
Post-layout timing simulation of CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8): 1170-1177 (1993) - 1991
- [j1]D. Navarro, A. Roy, Michel Robert, Denis Deschacht, Daniel Auvergne:
TVA: A timing verifier with analytic temporal modelling. Microprocessing and Microprogramming 32(1-5): 637-644 (1991) - [c2]Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert:
Formal sizing rules of CMOS circuits. EURO-DAC 1991: 96-100 - 1990
- [c1]Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne:
Path runner: an accurate and fast timing analyser. EURO-DAC 1990: 529-533
Coauthor Index
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