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ORCIDWilliam J. Starke
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2020 – today
- 2021
[j10]William J. Starke
, Brian W. Thompto, Jeffrey Stuecheli, José E. Moreira:
IBM's POWER10 Processor. IEEE Micro 41(2): 7-14 (2021)- [c7]Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose:
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA 2021: 29-42 - 2020
- [c6]William J. Starke, Brian W. Thompto:
IBM's POWER10 Processor. Hot Chips Symposium 2020: 1-43 - [c5]Bülent Abali, Bart Blaner, John J. Reilly, Matthias Klein, Ashutosh Mishra, Craig B. Agricola, Bedri Sendir, Alper Buyuktosunoglu, Christian Jacobi, William J. Starke, Haren Myneni, Charlie Wang:
Data Compression Accelerator on IBM POWER9 and z15 Processors : Industrial Product. ISCA 2020: 1-14
2010 – 2019
- 2019
- [c4]Jeff Stuecheli, Scott Willenborg, William J. Starke:
IBM's Next Generation POWER Processor. Hot Chips Symposium 2019: 1-19 - 2018
- [j9]William J. Starke, J. S. Dodson, Jeffrey Stuecheli, Eric Retter, Brad W. Michael, Stephen J. Powell, James A. Marcella:
IBM POWER9 memory architectures for optimized systems. IBM J. Res. Dev. 62(4/5): 3:1-3:13 (2018) - [j8]Jeffrey Stuecheli, William J. Starke, John D. Irish, L. Baba Arimilli, Daniel M. Dreps, Bart Blaner, Curt Wollbrink, Brian Allison:
IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI. IBM J. Res. Dev. 62(4/5): 8:1-8:8 (2018) - 2017
- [j7]Satish Kumar Sadasivam, Brian W. Thompto, Ronald N. Kalla, William J. Starke:
IBM Power9 Processor Architecture. IEEE Micro 37(2): 40-51 (2017) - 2015
- [j6]Hung Q. Le, Guy L. Guthrie, Derek Williams, Maged M. Michael, Brad Frey, William J. Starke, Cathy May, Rei Odaira, Takuya Nakaike:
Transactional memory support in the IBM POWER8 processor. IBM J. Res. Dev. 59(1) (2015) - [j5]William J. Starke, Jeffrey Stuecheli, David Daly, J. S. Dodson, Florian Auernhammer, Patricia Sagmeister, Guy L. Guthrie, Charles F. Marino, M. S. Siegel, Bart Blaner:
The cache and memory subsystems of the IBM POWER8 processor. IBM J. Res. Dev. 59(1) (2015) - 2014
- [c3]Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor:
The POWER8TM processor: Designed for big data, analytics, and cloud environments. ICICDT 2014: 1-4 - 2011
- [j4]Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban:
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. IEEE J. Solid State Circuits 46(1): 145-161 (2011) - 2010
- [j3]Ronald N. Kalla, Balaram Sinharoy, William J. Starke, Michael S. Floyd:
Power7: IBM's Next-Generation Server Processor. IEEE Micro 30(2): 7-15 (2010) - [c2]Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, Roland Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott A. Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban:
The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor. ISSCC 2010: 102-103
2000 – 2009
- 2009
- [c1]William J. Starke:
POWER7: IBM's next generation, balanced POWER server chip. Hot Chips Symposium 2009: 1-32 - 2007
- [j2]Hung Q. Le, William J. Starke, J. Stephen Fields, Francis P. O'Connell, Dung Q. Nguyen, Bruce J. Ronchetti, Wolfram Sauer, Eric M. Schwarz, Michael T. Vaden:
IBM POWER6 microarchitecture. IBM J. Res. Dev. 51(6): 639-662 (2007)
1990 – 1999
- 1996
- [j1]David R. Kaeli, O. Richard LaMaire, Peter P. Hennet, William W. White, William J. Starke:
Real-Time Trace Generation. Int. J. Comput. Simul. 6(1): 53- (1996)
Coauthor Index
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