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ORCIDDeepak Mathaikutty
Person information
- affiliation: Intel, USA
- affiliation (former): Virginia Tech, Blacksburg, Virginia, USA
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2020 – today
- 2024
[c34]Shamik Kundu
, Soumendu Kumar Ghosh, Arnab Raha, Deepak A. Mathaikutty:
SwiSS: Switchable Single-Sided Sparsity-based DNN Accelerators. ISLPED 2024: 1-6- [c33]Shamik Kundu, Arnab Raha, Deepak A. Mathaikutty, Kanad Basu:
RASH: Reliable Deep Learning Acceleration using Sparsity-based Hardware. ISQED 2024: 1 - [c32]Soumendu Kumar Ghosh, Shamik Kundu, Arnab Raha, Deepak A. Mathaikutty, Vijay Raghunathan:
HARVEST: Towards Efficient Sparse DNN Accelerators using Programmable Thresholds. VLSID 2024: 228-234 - [i2]Arnab Raha, Deepak A. Mathaikutty, Soumendu Kumar Ghosh, Shamik Kundu:
FlexNN: A Dataflow-aware Flexible Deep Learning Accelerator for Energy-Efficient Edge Devices. CoRR abs/2403.09026 (2024) - 2023
- [c31]Ming Lei, Mahib Rahman, Deepak Mathaikutty, Ignacio Alvarez:
Wireless-Assisted Automatic Online Spatial Calibration based on 5G TSN for Sensor Fusion. ICSPCC 2023: 1-6 - [i1]Charles Qi, Yi Wang, Hui Wang, Yang Lu, Shiva Shankar Subramanian, Finola Cahill, Conall Tuohy, Victor Li, Xu Qian, Darren Crews, Ling Wang, Shivaji Roy, Andrea Deidda, Martin Power, Niall Hanrahan, Rick Richmond, Umer Cheema, Arnab Raha, Alessandro Palla, Gary Baugh, Deepak Mathaikutty:
VPU-EM: An Event-based Modeling Framework to Evaluate NPU Performance and Power Efficiency at Scale. CoRR abs/2303.10271 (2023) - 2022
- [c30]Steven Hsu, Amit Agarwal, Mark A. Anders, Arnab Raha, Raymond Sung, Deepak Mathaikutty, Ram Krishnamurthy, James W. Tschanz, Vivek De:
2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators. VLSI Technology and Circuits 2022: 22-23 - 2021
- [c29]Arnab Raha, Soumendu Kumar Ghosh, Debabrata Mohapatra, Deepak A. Mathaikutty, Raymond Sung, Cormac Brick, Vijay Raghunathan:
Special Session: Approximate TinyML Systems: Full System Approximations for Extreme Energy-Efficiency in Intelligent Edge Devices. ICCD 2021: 13-16 - [c28]Arnab Raha, Sang Kyun Kim, Deepak Mathaikutty, Guruguhanathan Venkataramanan, Debabrata Mohapatra, Raymond Sung, Cormac Brick, Gautham N. Chinya:
Design Considerations for Edge Neural Network Accelerators: An Industry Perspective. VLSID 2021: 328-333
2010 – 2019
- 2019
- [j13]Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - 2018
- [j12]Mike Davies, Narayan Srinivasa, Tsung-Han Lin, Gautham N. Chinya, Yongqiang Cao, Sri Harsha Choday, Georgios D. Dimou, Prasad Joshi, Nabil Imam, Shweta Jain, Yuyun Liao, Chit-Kwan Lin, Andrew Lines, Ruokun Liu, Deepak Mathaikutty, Steven McCoy, Arnab Paul, Jonathan Tse, Guruguhanathan Venkataramanan, Yi-Hsin Weng, Andreas Wild, Yoonseok Yang, Hong Wang:
Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. IEEE Micro 38(1): 82-99 (2018) - [c27]Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40
2000 – 2009
- 2009
- [b2]Deepak Mathaikutty, Sandeep Kumar Shukla:
Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design. Artech House 2009, ISBN 978-1-59693-424-5, pp. I-XXI, 1-287 - [j11]Alberto L. Sangiovanni-Vincentelli, Sandeep K. Shukla, Janos Sztipanovits, Guang Yang, Deepak Mathaikutty:
Metamodeling: An Emerging Representation Paradigm for System-Level Design. IEEE Des. Test Comput. 26(3): 54-69 (2009) - [j10]Sumit Ahuja, Deepak Mathaikutty, Avinash Lakshminarayana, Sandeep K. Shukla:
SCoPE: Statistical Regression Based Power Models for Co-Processors Power Estimation. J. Low Power Electron. 5(4): 407-415 (2009) - [c26]Sumit Ahuja, Deepak Mathaikutty, Gaurav Singh, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar:
Power estimation methodology for a high-level synthesis framework. ISQED 2009: 541-546 - [c25]Sumit Ahuja, Deepak Mathaikutty, Avinash Lakshminarayana, Sandeep K. Shukla:
Accurate power estimation of hardware co-processors using system level simulation. SoCC 2009: 399-402 - 2008
- [j9]Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch:
SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system. Des. Autom. Embed. Syst. 12(1-2): 1-30 (2008) - [j8]Deepak Mathaikutty, Sandeep K. Shukla:
Mining metadata for composability of IPs from SystemC IP library. Des. Autom. Embed. Syst. 12(1-2): 63-94 (2008) - [j7]Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja:
MMV: A Metamodeling Based Microprocessor Validation Environment. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 339-352 (2008) - [j6]Deepak Mathaikutty, Sandeep K. Shukla:
MCF: A Metamodeling-Based Component Composition Framework - Composing SystemC IPs for Executable System Models. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 792-805 (2008) - [j5]Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
A Trace-Based Framework for Verifiable GALS Composition of IPs. IEEE Trans. Very Large Scale Integr. Syst. 16(9): 1176-1186 (2008) - [c24]Syed Suhaib, Bijoy Antony Jose, Sandeep K. Shukla, Deepak Mathaikutty:
Formal Transformation of a KPN Specification to a GALS Implementation. FDL 2008: 84-89 - [c23]Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla:
Applying Verification Collaterals for Accurate Power Estimation. MTV 2008: 61-66 - 2007
- [b1]Deepak Mathaikutty:
Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design. Virginia Tech, Blacksburg, VA, USA, 2007 - [j4]Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch:
EWD: A metamodeling driven customizable multi-MoC system modeling framework. ACM Trans. Design Autom. Electr. Syst. 12(3): 33:1-33:43 (2007) - [c22]Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara, David J. Lilja, Ajit Dingankar:
Design fault directed test generation for microprocessor validation. DATE 2007: 761-766 - [c21]Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla:
A Metamodeling based Framework for Architectural Modeling and Simulator Generation. FDL 2007: 210-218 - [c20]Deepak Mathaikutty, Sumit Ahuja, Ajit Dingankar, Sandeep K. Shukla:
Model-driven test generation for system level validation. HLDVT 2007: 83-90 - [c19]Deepak Mathaikutty, Sandeep K. Shukla:
Type Inference for IP Composition. MEMOCODE 2007: 61-70 - [c18]Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla, Ajit Dingankar:
Assertion-Based Modal Power Estimation. MTV 2007: 3-7 - [c17]Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja:
Model Based Test Generation for Microprocessor Architecture Validation. VLSI Design 2007: 465-472 - [c16]Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
Dataflow Architectures for GALS. FMGALS@MEMOCODE 2007: 33-50 - 2006
- [j3]Syed Suhaib, Deepak Mathaikutty, David Berner, Sandeep K. Shukla:
Validating Families of Latency Insensitive Protocols. IEEE Trans. Computers 55(11): 1391-1401 (2006) - [j2]Hiren D. Patel, Deepak Mathaikutty, David Berner, Sandeep K. Shukla:
CARH: service-oriented architecture for validating system-level designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8): 1458-1474 (2006) - [c15]Deepak Mathaikutty, Sandeep K. Shukla:
Mining Metadata for Composability of IPs from SystemC IP Library. FDL 2006: 143-151 - [c14]Deepak Mathaikutty, Sandeep K. Shukla:
MCF: A Metamodeling-based Visual Component Composition Framework. FDL 2006: 367-375 - [c13]Ajit Dingankar, Deepak Mathaikutty, Sreekumar V. Kodakara, Sandeep K. Shukla, David J. Lilja:
MMV: Metamodeling Based Microprocessor Valiation Environment. HLDVT 2006: 143-148 - [c12]Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, Jean-Pierre Talpin:
Polychronous Methodology For System Design: A True Concurrency Approach. HLDVT 2006: 211-214 - [c11]Deepak Mathaikutty, Sandeep K. Shukla:
SoC Design Space Exploration through Automated IP Selection from SystemC IP Library. SoCC 2006: 109-110 - [c10]Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
A Trace Based Framework for Validation of SoC Designs with GALS Systems. SoCC 2006: 247-250 - 2005
- [j1]Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner:
XFM: An incremental methodology for developing formal models. ACM Trans. Design Autom. Electr. Syst. 10(4): 589-609 (2005) - [c9]Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch:
Modelling Environment for Heterogeneous Systems based on MoCs. FDL 2005: 291-303 - [c8]David Berner, Jean-Pierre Talpin, Hiren D. Patel, Deepak Mathaikutty, Sandeep K. Shukla:
SystemCXML: An Exstensible SystemC Front end Using XML. FDL 2005: 405-409 - [c7]Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner:
Validating families of latency insensitive protocols. HLDVT 2005: 127-134 - [c6]David Berner, Hiren D. Patel, Deepak Mathaikutty, Sandeep K. Shukla:
Automated Extraction of Structural Information from SystemC-based IP for Validation. MTV 2005: 99-104 - [c5]Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
System Level Design Methodology for System On Chips using Multi-Threaded Graphs. SoCC 2005: 133-136 - [c4]Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner, Jean-Pierre Talpin:
A Functional Programming Framework for Latency Insensitive Protocol Validation. FMGALS@MEMOCODE 2005: 169-188 - 2004
- [c3]Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla:
A Functional Programming Framework of Heterogeneous Model of Computation for System Design. FDL 2004: 586-598 - [c2]Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
Effects of property ordering in an incremental formal modeling methodology. HLDVT 2004: 89-94 - [c1]Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner:
Extreme Formal Modeling (XFM) for Hardware Models. MTV 2004: 30-35
Coauthor Index
aka: Sandeep Kumar Shukla
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