"A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 ..."

Timothy O. Dickson et al. (2016)

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DOI: 10.1109/JSSC.2016.2550499

access: closed

type: Journal Article

metadata version: 2020-08-30

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Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman:
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. IEEE J. Solid State Circuits 51(8): 1744-1755 (2016)

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