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- Wafer-level packaging (WLP) is a process where packaging components are attached to an integrated circuit (IC) before the wafer – on which the IC is fabricated – is diced. In WSP, the top and bottom layers of the packaging and the solder bumps are attached to the integrated circuits while they are still in the wafer. This process differs from a conventional process, in which the wafer is sliced into individual circuits (dice) before the packaging components are attached. WLP is essentially a true chip-scale package (CSP) technology, since the resulting package is practically of the same size as the die. Wafer-level packaging allows integration of wafer fab, packaging, test, and burn-in at wafer level in order to streamline the manufacturing process undergone by a device from silicon start to customer shipment. There is no single industry-standard method of wafer-level packaging at present. A major application area of WLPs are smartphones due to the size constraints. For example, the Apple iPhone 5 has at least eleven different WLPs, the Samsung Galaxy S3 has six WLPs and the HTC One X has seven. Functions provided WLPs in smartphones include sensors, power management, wireless, etc. In fact, it has recently been rumored that the iPhone 7 will use fan-out wafer-level packaging technology in order to achieve a thinner and lighter model. Wafer-level chip scale packaging (WL-CSP) is the smallest package currently available on the market and is produced by OSAT (Outsourced Semiconductor Assembly and Test) companies, such as Advanced Semiconductor Engineering (ASE). A WL-CSP or WLCSP package is just a bare die with a redistribution layer (RDL, interposer or I/O pitch) to rearrange the pins or contacts on the die so that they can be big enough and have sufficient spacing so that they can be handled just like a ball grid array (BGA) package. There are two kinds of wafer level packaging: fan-in and fan-out. Fan-in WLCSP packages have an interposer that is the same size as that of the die, where as fan-out WLCSP packages have an interposer that is larger than the die, similar to conventional BGA packages, the difference being that the interposer is built directly atop the die, instead of the die being attached to it and reflowed using the flip chip method. This is also true in fan-in WLSCP packages. In both cases, the die with its interposer may be covered in encapsulating material such as epoxy. In February 2015, it was discovered that a WL-CSP chip in the Raspberry Pi 2 had issues with xenon flashes (or any other bright flashes of longwave light), inducing the photoelectric effect within the chip. Thus, careful consideration concerning exposure to extremely bright light will need to be given with wafer-level packaging. (en)
- ウエハーレベルCSP (英: wafer level chip size package) とは、半導体部品のパッケージ形式のひとつであり、ボンディング・ワイヤーによる内部配線を行なわず、半導体の一部が露出したままの、ほぼ最小となる半導体パッケージであり、広義のフリップチップである。プリント基板上に単体の高集積度半導体を表面実装する時に小さな占有面積で済ませられる。最近では、FOWLPと区別するためにFIWLP（英: fan in wafer level package）とも呼ばれる。 「CSP」（英: chip size package）と云う名前の通り、半導体のダイとも呼ばれるベアチップ大のパッケージであり、「ウエハーレベル」とは、外部端子や封止樹脂といった通常はベアチップへ行なう加工処理をウエハーからチップを切り出す前のウエハーの段階で済ませる事を意味している。 (ja)
- Wafer-Level Packaging (WLP) indica una tecnologia di packaging dei circuiti integrati a livello di wafer. Essenzialmente è una soluzione che porta ad ottenere un componente che ha circa la stessa dimensione del die di silicio di partenza. (it)
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- ウエハーレベルCSP (英: wafer level chip size package) とは、半導体部品のパッケージ形式のひとつであり、ボンディング・ワイヤーによる内部配線を行なわず、半導体の一部が露出したままの、ほぼ最小となる半導体パッケージであり、広義のフリップチップである。プリント基板上に単体の高集積度半導体を表面実装する時に小さな占有面積で済ませられる。最近では、FOWLPと区別するためにFIWLP（英: fan in wafer level package）とも呼ばれる。 「CSP」（英: chip size package）と云う名前の通り、半導体のダイとも呼ばれるベアチップ大のパッケージであり、「ウエハーレベル」とは、外部端子や封止樹脂といった通常はベアチップへ行なう加工処理をウエハーからチップを切り出す前のウエハーの段階で済ませる事を意味している。 (ja)
- Wafer-Level Packaging (WLP) indica una tecnologia di packaging dei circuiti integrati a livello di wafer. Essenzialmente è una soluzione che porta ad ottenere un componente che ha circa la stessa dimensione del die di silicio di partenza. (it)
- Wafer-level packaging (WLP) is a process where packaging components are attached to an integrated circuit (IC) before the wafer – on which the IC is fabricated – is diced. In WSP, the top and bottom layers of the packaging and the solder bumps are attached to the integrated circuits while they are still in the wafer. This process differs from a conventional process, in which the wafer is sliced into individual circuits (dice) before the packaging components are attached. (en)
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- Wafer-level packaging (it)
- ウエハーレベルCSP (ja)
- Wafer-level packaging (en)
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