2007 Volume 2 Issue 3 Pages 695-703
We present very wide dynamic range (WDR) CMOS image sensor that integrates improved high-speed column-parallel cyclic ADCs. The proposed signal readout technique of extremely short accumulation (ESA) enables the dynamic range to be expanded to a very high illumination region. Including the ESA signals, a total of four different accumulation time signals are read out in one frame period using a burst readout technique. To achieve the high-speed and high-quality signal readout required for multiple exposure signals, column parallel high-speed A/D converters are integrated at the upper and lower sides of the pixel arrays. This improved cyclic ADC, with reduced random noise, better linearity and offset deviation, expands the dynamic range in the low illumination region. The resulting dynamic range is maximally 153 dB. The improved 12-bit cyclic ADC has a differential non-linearity (DNL) of ±0.3 LSB.
