An RRAM-based building block for reprogrammable non-uniform sampling ADCs

2.1 Memristor modelling

A memristor’s characteristic hysteresis curve is depicted in Figure 2 [14, 15]. This curve can be generated by applying a DC signal including the devices V _set and V _reset thresholds.

Figure 2:

Memristor’s I–V cycles hysteresis loop [14].

An early device model has been provided by Biolek et al. [16], which is mathematically similar to [5]. The model was rather simplistic, accepting only one state variable. It has been constructed as follows: The oxygen atoms doping method in TiO₂ thin films provides two zones with differing resistances in series with the film [16]. The doped zone (TiO₂ − x) has lower resistance and better conductivity, while the region which is not doped has higher resistance with lower conductivity. When the bias voltage is removed, the oxygen vacancies do not shift, and the region between doped and un-doped areas of the memristor’s boundary remains in place [8, 17]. This is displayed by a component consisting of two resistors arranged in series (R _ON, R _OFF where, R _ON < R _OFF). w represents the state variable describing each resistor’s relative doped or undoped part (see Figure 3). Doped areas have an oxygen deficit (TiO₂ − x) and serve as R _ON, whereas undoped areas act as R _OFF [8].

Figure 3:

Memristor model based on linear ion drift titanium dioxide (HP’s) [8].

In the following years more sophisticated models have been developed. Ding et al. provided an HSPICE Macro design for the resistive random access memory with CuxO technology (ReRAM) [18]. Pickett et al. released a more sophisticated model for the TiOx device which included nonlinear dynamics [19]. This has subsequently been implemented in SPICE [20]. Menzel et al. adapted this model to describe the electrochemical metallization memory cells [21]. Gao et al. have found that the observed switching behaviors of metal–oxide based RRAM can be employed to quantitatively investigate and expect the resistive switching aspects [22]. Jiang et al. have proposed the Stanford PKU model [23], which has been adapted to reflect the RRAM devices fabricated at IHP by Reuben et al. [24]. Subsequently, we chose to use it for our investigation

2.2 Non-uniform sampling

Henry Landau invented nonuniform sampling in 1967. This aspect of the theory of sampling deals with the Nyquist-Shannon sampling theorem’s results [25]. The Shannon sampling theory for nonuniform sampling states that when an average sampling rate meets the Nyquist condition, a band-constrained signal can be rebuilt from such samples. Several hardware implementations based on this theory have been realized and the mathematical theory of nonuniform sampling thoroughly researched and recognized [26]. Later non-uniform sampling has also been used to describe non-equally distributed quantization thresholds as depicted in Figure 1. Within this paper, we will propose an efficient implementation using RRAM devices. Table 1 shows typical values obtained through nonuniform sampling. The corresponding signals obtained from the ADC interface are quantized. A range that generates the same digital signals exists among the analog input signals.

2.3 ADC design

Analog signals are converted into digital signals by using Analog-to-Digital Converters (ADCs) for digital signal processors in electronic devices [27]. The ADCs working principle is shown in Figure 4. The Analog signal is first sampled via a circuit (sample and hold) and changed into a discrete-time signal. The sample and hold circuit output is then quantized yielding an approximate quantization level [27, 28]. The quantization level is then encoded into a binary number. The encoded binary number becomes the output of the ADC. The rudimentary operation of the comparator lies within comparing two analog signals and outputting a 0 or 1, depending on whether input a is above or below input b. In recent times, dynamic comparators have found widespread use in reducing energy consumption and increasing the analog-to-digital signal conversion rate [29]. There are inverters in dynamic comparators that are effective at producing positive feedback. Such mechanisms can transform smaller voltage differences into more significant digital output levels. A schematic of the comparator is part of Figure 5. V _IP is the voltage supplied at the positive terminal of the input of the comparator, and V _IN is the negative voltage to the negative terminal [29, 30]. Suppose V _IP, is higher than V _IN in that case, the comparator outputs a binary value of 1 and 0 and vice versa.

Figure 4:

Operation principle of an ADC [28].

Figure 5:

Schematic symbol of a comparator [30].

The gain of a comparator can be written as [31]:

where ΔV is the input voltage change V _IP–V _IN. V _OH and V _OL are defined as the high and low-level output voltage of the comparator.

The comparator’s propagation delay can be expressed as follows (t _rp and t _fp, respectively, represent the rising and falling propagation delays) [31]:

There are different types of comparators, namely, static, static latched, dynamic, and double-tail dynamic comparators. Within this work we will focus on the static and dynamic comparators.

2.3.1 Static comparators

A static comparator is a basic device that compares two signals (V _IP and V _IN) based on input and reference signal threshold detection. Two differential input transistors (Nla and N1b), a current mirror load (N2a and N2b), and a current source (I _SS) make up the traditional static comparator as depicted in Figure 6a. The input signals (V _IP and V _IN) are continuously compared without being timed, regulated, or activated by any clock signals [32]. The function of a static comparator can be compared to that of an operational amplifier with compensation. A drawback of the static comparator is that it suffers from overshoots and undershoots. The circuit of the static comparator is elementary, but since it is always energized when in operation it tends to consume more power, especially at high switching speeds [32].

Figure 6:

Schematics of the static comparator (a) [32] and dynamic comparator (b) [32, 33].

3.1 RRAM-based comparator

3.1.1 Novel modified CMOS comparator design

We have depicted our proposed comparator structure in Figure 7, which is a modified two-stage CMOS comparator with the primary goal of designing a low-power, low-delay, and high-speed comparator. It consists of a differential amplifier, input stage, and an inverter output stage. The advantage of a two-stage CMOS comparator is that the circuit requires the minimum number of transistors, ultimately resulting in reduced area consumption. The initial phase is a differential amplifier (N1, N2, N8, N5), the middle is a common-source amplifier (N4, N7), and the final is an inverter stage (N9, N10, N11, N12). The biasing circuit stage of the amplifier is accomplished with transistors (N4, N7, N6, and N3). The differential pair is connected to the two analog input voltages, V _IP, and V _IN. To enhance the gain of the first stage and decrease the input offset voltage, we increased the widths of the input differential pair, N1-N2. To decrease the parasitic capacitance at the N7 gate and, consequently, the propagation delay, the area of the common-source transistor was decreased. A CMOS inverter is used in the third stage, improving the comparator and adding a small amount of gain. All the other transistors act as for switching operations. The supply voltage in this circuit is 1V, while the input bias current is designed to be 50 μA. In Table 3, the dimensions of the transistors in the proposed comparator structure are presented. The circuit is designed with appropriate W/L ratios to obtain better performances in terms of delay and power. Compared to conventional architectures, the comparator power consumption and delay have improved. The key benefit of this type of comparator is that no power is wasted from the supply when the comparator is not in use. This comparator controls the leakage current on the device. It is the main advantage of this comparator, and its performance is excellent (delay) compared to those covered in refs. [35, 40, 41].

Figure 7:

Modified comparator schematic.

3.1.3 Proposed RRAM based comparator

In this section, we introduce the proposed memristor-based comparator with hysteresis, as shown in Figure 8. The application of the CMOS comparator part has been explained in the previous section. Table 2 shows the set of parameters fed to the Memristor model to simulate the behavior of the IHP’s 130 nm technology RRAM cells [44]. The circuit configuration uses a voltage divider which is used to set up an upper threshold voltage (V _H ) to transition below a lower threshold voltage (V _L ). The comparator input signal is applied to the inverting input. The memristor network comprising N ₁, N ₂, the voltage divider, and N ₃ – the hysteresis level, as used in this circuit has been preprogrammed to set the hysteresis at the desired value [13]. If the supply voltage causes the output to reach 1V memristor N ₃ is set in parallel with memristor N ₁, raising threshold voltage node B [13, 45].

Figure 8:

RRAM based comparator.

Table 2:

RRAM model parameters as fitted by [24].

go = 5e-10	Vo = 0.27 V	I0 = 0.0003
vo = 0.8 m/s	β = 5.2	α = 2.1
gapini = 1.5e-10	T o = 300 K	γ = 22
gapmax = 1.5e-10	t ox = 6 nm	I o = 0.003
Ea = 0.6 eV	R th = 1500 K/W	γ reset = 15.3 nm

Table 3:

Transistor sizes/part specifictions in the circuit shown in Figure 7.

Part	Width/length	Part	Width/length
N1	0.15 μ/0.13 μ	N8	0.8 μ/0.13 μ
N2	0.15 μ/0.13 μ	N9	0.8 μ/0.13 μ
N3	0.15 μ/0.13 μ	N10	0.8 μ/0.13 μ
N4	0.15 μ/0.13 μ	N11	0.8 μ/0.13 μ
N5	0.15 μ/0.13 μ	N12	0.8 μ/0.13 μ
N6	0.15 μ/0.13 μ	I dc	50 mA
N7	0.15 μ/0.13 μ	C, C L	20 pf

This concept and the following equations have been proposed by others [13, 46], our contribution lies within adapting this to a given CMOS process and a specific RRAM device.

(12) V H = N 2 N 2 + N 1 N 3 N 1 + N 3 . V d d

(13) V H = N 2 N 3 + N 1 N 2 N 1 N 3 + N 2 N 3 + N 1 N 2 . V d d

Similarly, when the supply voltage causes the output to reach 0 V, N ₃ is set in parallel with N ₂, thus reducing the current to memristor N ₂ and the threshold voltage V _L [13, 45].

(14) V L = N 2 N 3 N 2 + N 3 N 1 + N 2 N 3 N 2 + N 3 . V d d

(15) V L = N 2 N 3 N 1 N 3 + N 2 N 3 + N 1 N 2 . V d d

A transition happens when the input voltage is below V _L . The following hysteresis voltage equations are derived from Equations (13) and (15) [13, 45].

(16) V H − V L = N 2 N 2 + N 1 N 3 N 1 + N 3 . V d d

(17) V H − V L = N 1 N 2 N 1 N 3 + N 2 N 3 + N 1 N 2 . V d d

(18) V d d − V H = V d d − ( N 3 N 2 + N 1 N 2 N 1 N 3 + N 2 N 3 + N 1 N 2 ) . V d d

(19) V d d − V H = N 1 N 3 N 1 N 3 + N 2 N 3 + N 1 N 2 . V d d

The resistance of the memristors N ₁, N ₂ and N ₃ should be chosen to be very high in order to minimize the current consumption of this circuit. Equations (12) and (14) show the equations for setting the threshold voltages. We obtain the following equations from Equations (13), (15) and (17)–(15) and (19)(15) and (17)–(19)(15) and (17)–(19) [13, 45].

(20) N 1 N 3 = V H − V L V L

(21) N 1 N 2 = V d d − V H V L

The hysteresis threshold voltages (V _H and V _L ) are described in Equations (20) and (21), respectively.

3.2 Non-uniform sampling ADC and model parameters

We can use the comparator shown earlier to implement a non-uniform ADC or a sensor evaluation circuit by stacking multiple of these blocks and having them switch at non-uniformly distributed voltages. We will demonstrate the reprogrammability within the next section.

We have used the Stanford PKU memristor model parameters as fitted by Reuben et al. [24] and as depicted in Table 2.

4.1 Comparator design

In this section, we will evaluate the proposed design as ported to the 130 nm process. We use Cadence Virtuoso to achieve the depicted simulation results. All simulations are performed considering 1V of supply voltage at T = 27 °C operating temperature. We used an input clock of 10 MHz with a rise and fall time of 50 ps each. The transient analysis of the proposed comparator is shown in Figure 9a. In this situation, the difference between the two inputs is 5 mv. Using the concepts described earlier the total power consumption for the proposed circuit is 8.64 μW. Figures 10 and 11 depict Monte-Carlo simulations (2000 samples) for both power consumption and delay; The total power consumption is 847.364 mw and the standard deviation is 6.188 mw. As one can see the average delay seems to be 51.63 ps, with a standard deviation of 1.31. The dynamic power consumption variation is shown in Figure 9b. The simulation results in noise performance are shown in Figure 9c, showing the effects of input-referred noise, output noise, and phase noise margin, respectively, for the proposed comparator. The graph plot shows the relationship between Frequency (Hz) and V/sqrt referred noise (V/Hz). The merging technique, on the other hand, has been used in preamplifier transistors to increase speed and decrease the delay. The achieved specifications of the implemented comparator circuit are shown in Table 4. A comparison of the proposed comparator with designs proposed in literature is presented in Table 5. The proposed technique seems to be promising regarding delay; The power consumption is not directly comparable since this circuit is highly optimized for the specified application. The next Section will illustrate that the circuit uses way less power when integrated into the RRAM circuit.

Figure 9:

Results: transient analysis (a), corresponding power consumption (b) and noise response (c) of our design.

Figure 10:

Monte Carlo simulation result for delay.

Figure 11:

Monte Carlo simulation result for power consumption.

4.2 Comparator RRAM optimizations

In this section we show the effectiveness of our proposed comparator design for the usage with RRAM devices. As discussed, the proposed RRAM comparator design can preserve its pre-programmed state, acting similarly to a conventional resistor. Figure 12 depicts the simulation verifying the threshold voltages. The input is an ideal triangle waveform. The memristor N ₃ sets the hysteresis level. When the output is at a logic high (1V), N ₃ is in parallel with N ₁. This drives more current into N ₂, raising the threshold voltage (V _H ) to 504.77 mv. The input signal needs to be below V _H = 504.77 mv to cause the output to transition to logic low (OV). When the output is at logic low (OV), N ₃ is in parallel with N ₂. This reduces the current into N ₂, reducing the threshold voltage to 495.07 mv. The input signal needs to increase until V _L = 495.07 mv to cause the output to transition to logic low (0 V). This helps avoiding glitches when the input is slightly above or beyond the desired threshold. Figure 13 depicts the output of the comparator showing a single transition in spite of the noisy triangular waveform signal at its input. V _H and V _L are set to 504.77 and 495.07 mv, respectively. The output of the memristor-based comparator hysteresis ranges from 504.77 mv to 495.07 mv. The simulation results in output noise performance are shown in Figure 14a and b. These show the effects of input-referred noise and phase noise margin, respectively, for the proposed memristor-based comparator. The graph plots also show the difference between Frequency (Hz) and V/sqrt referred noise (V/Hz). Figure 14c shows Monte-Carlo simulations (1200 samples) for power consumption of the proposed memristor-based comparator for changes in process and mismatch operations. The total power consumption is approximately 84.69 μw with a small standard derivation of 6.2 μw. Table 6 shows the simulated parameters of the proposed RRAM comparator.

Figure 12:

Simulation results: comparator behaviour without noise applied to its input.

Figure 13:

Simulation results: comparator behaviour when applying noise to its input.

Figure 14:

Output noise response (a), input and phase noise response (b), and Montecarlo simulation regarding the power consumption of the proposed comparator (c).

4.3 Non-uniform ADC embedding RRAMs

We have programmed the memristor to modify the threshold of the comparator. Since the memristors current state is modelled using the gap model variable using the employed model we use this variable to depict the current state of the device. This is equivalent to the w/d ratio depicted in Figure 3, resulting in different device resistances. The effect of different gaps on the threshold of the comparator is depicted in Figure 15. As one can see programming the RRAM device to a given gap state leads to a different threshold. Subsequently this yields a comparator with programmable threshold. Future work should investigate how device variations impact this block.

Figure 15:

Simulation results: programming the RRAM device to different resistances/gaps (individual colors) leads to different threshold behaviour.

The programming circuit does not need to be part of the design, it can be connected externally in case a readjustment of the threshold is required. Additionally, multiple of these blocks can be combined to form a larger ADC block which is highly optimized towards the required thresholds.