IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration
Xiaoge Zhu, Danyu Wu, Lei Zhou, Chonghe Ma, Dandan Wang, Jian Luan, Yinkun Huang, Jin Wu, Xinyu Liu
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Keywords: analog-to-digital converter (ADC), successive approximation register (SAR), segmented prequantize and bypass, alternating comparison, asynchronous timing, background offset calibration
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2017 Volume 14 Issue 11 Pages 20170329

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Abstract

An 8-b single-channel successive approximation register (SAR) analog-to-digital converter (ADC) fabricated in 55 nm CMOS is proposed. With segmented prequantize and bypass digital-to-analog converter (DAC), the unnecessary switching of high weight capacitors are avoided. Two alternating comparators are utilized to reset the comparators completely without the sacrifice of conversion speed. A novel simple and low power background offset calibration technique is implemented. Operating at 325 MS/s, this ADC consumes 6 mW from 1.2 V supply, achieves SNDR of 43.6 dB and SFDR of 59.1 dB with 11-MHz input while occupying 0.011 mm2.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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