A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs

Widiant; Masaki HASHIZUME; Shohei SUENAGA; Hiroyuki YOTSUYANAGI; Akira ONO; Shyue-Kung LU; Zvi ROTH

doi:10.1587/transinf.2015EDP7273

Regular Section

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs

Widiant, Masaki HASHIZUME, Shohei SUENAGA, Hiroyuki YOTSUYANAGI, Akira ONO, Shyue-Kung LU, Zvi ROTH

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Keywords: electrical test, built-in test circuit, open defect, interconnect test, design for testability

JOURNAL FREE ACCESS

2016 Volume E99.D Issue 11 Pages 2723-2733

DOI https://doi.org/10.1587/transinf.2015EDP7273

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Abstract

In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this paper, the test circuit is evaluated by SPICE simulation and by experiments with a prototyping IC. The experimental results reveal that a hard open defect is detectable by the test method in addition to a resistive open defect and a capacitive open one at a test speed of 400 kHz.

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