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SMP-SIM: An SMP-based discrete-event execution-driven performance simulator

Lin Yufei (State Key Laboratory of High Performance Computing National University of Defense Technology, Changsha, China)
Xu Xinhai (State Key Laboratory of High Performance Computing National University of Defense Technology, Changsha, China)
Tang Yuhua (State Key Laboratory of High Performance Computing National University of Defense Technology, Changsha, China)
Zhang Xin (State Key Laboratory of High Performance Computing National University of Defense Technology, Changsha, China)
Guo Xiaowei (State Key Laboratory of High Performance Computing National University of Defense Technology, Changsha, China)

Designing and implementing a large-scale parallel system can be time-consuming and costly. It is therefore desirable to enable system developers to predict the performance of a parallel system at its design phase so that they can evaluate design alternatives to better meet performance requirements. Before the target machine is completely built, the developers can always build an symmetric multi-processor (SMP) for evaluation purposes. In this paper, we introduce an SMP-based discrete-event execution-driven performance simulation method for message passing interface (MPI) programs and describe the design and implementation of a simulator called SMP-SIM. As the processes share the same memory space in an SMP, SMP-SIM manages the events globally at the granularity of central processing units (CPUs). Furthermore, by re-implementing core MPI point-to-point communication primitives, SMP-SIM handles the communication virtually and sequential computation actually. Our experimental results show that SMP-SIM is highly accurate and scalable, resulting in errors of less than 7.60% for both SMP and SMP-Cluster target machines.

Keywords: simulator, SMP, MPI, performance prediction