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Volume: 32 | Article ID: art00015
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CIS Band Noise Prediction Methodology Using Co-Simulation of Camera Module
Euncheol Lee
Hyunsu Jun
Wonho Choi
Kihyun Kwon
Jihyung Lim
Seung-hak Lee
JoonSeo Yim
  DOI :  10.2352/ISSN.2470-1173.2020.7.ISS-328  Published Online :  January 2020
Abstract

This paper describes a CMOS image sensor (CIS) horizontal band noise reduction methodology considering on-chip and offchip camera module PCB design parameters. The horizontal band noise is a crucial issue for high quality camera of modern smartphone applications. This paper discusses CIS horizontal band noise mechanism and proposes the solution by optimization of design factors in CIS and camera module. Analog ground impedance value and bias voltage condition of pixel array transfer gate have been found to be effective optimization parameters. Through the real experimental data, we proved that proposed solution is instrumental in reducing the horizontal band noise.

Journal Title : Electronic Imaging
Publisher Name : Society for Imaging Science and Technology
Publisher Location : 7003 Kilworth Lane, Springfield, VA 22151 USA
Subject Areas :
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 DOI 10.2352/ISSN.2470-1173.2020.7.ISS-328
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  Cite this article 

Euncheol Lee, Hyunsu Jun, Wonho Choi, Kihyun Kwon, Jihyung Lim, Seung-hak Lee, JoonSeo Yim, "CIS Band Noise Prediction Methodology Using Co-Simulation of Camera Module"  in Proc. IS&T Int’l. Symp. on Electronic Imaging: Imaging Sensors and Systems,  2020,  pp 328-1 - 328-5,  https://doi.org/10.2352/ISSN.2470-1173.2020.7.ISS-328

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Copyright © Society for Imaging Science and Technology 2020
72010604
Electronic Imaging
2470-1173
Society for Imaging Science and Technology
7003 Kilworth Lane, Springfield, VA 22151 USA
10.2352/ISSN.2470-1173.2020.7.ISS-328
2470-1173(20200126)2020:7L.3281;1-
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Articles
CIS Band Noise Prediction Methodology Using Co-Simulation of Camera Module
LeeEuncheol
JunHyunsu
ChoiWonho
KwonKihyun
LimJihyung
LeeSeung-hak
YimJoonSeo
26012020
2020
7
328-1
328-5
2020
This paper describes a CMOS image sensor (CIS) horizontal band noise reduction methodology considering on-chip and offchip camera module PCB design parameters. The horizontal band noise is a crucial issue for high quality camera of modern smartphone applications. This paper discusses CIS horizontal band noise mechanism and proposes the solution by optimization of design factors in CIS and camera module. Analog ground impedance value and bias voltage condition of pixel array transfer gate have been found to be effective optimization parameters. Through the real experimental data, we proved that proposed solution is instrumental in reducing the horizontal band noise.
NoiseHorizontal band noiseSimulationCamera ModuleModelingBand noiseMethodology