FET drain voltage spike in push-pull converter

Question

I have returned to my 150W inverter simulation and have a new problem I can't decipher. This is the design:

It runs, it allegedly has good efficiency, and it creates a stable 180V output voltage. I've included a leakage inductance of 198nH on each primary winding to simulate stored energy in the transformer windings. I'm getting ringing on the drains which I expect, and I've added an RC snubber to reduce them. However, at the point of turn-off for the mosfets there is an enormous drain voltage spike up to 100V. It might be higher, but the Vds breakdown is 100V and I suspect the spike is even higher but the models are simply clamping it there.

I have experimented with diodes across drain-source, freewheeling diodes across drain-Vin, but the former does nothing and the latter severely distorts the switching waveform. When I check the primary input waveform of the transformer after the leakage it does not have these spikes:

I'm not sure how else to dissipate this stored leakage energy without interfering with operation. Since it happens at turn-off I wonder if there is a better drive scheme I can be doing? The whole idea of simulation was to identify issues that could destroy components but I'm not sure how to reduce this spike. Any help is appreciated.

Answer 1

While a snubber might work, it is not very precise and therefore needs to be overdesigned.

The general way to do this is to control (reduce) the strength of the gate drive. This can be difficult because there is a tradeoff with dead time control and with gate lift-up.

A zener diode across the D-S of each FET will work, but it needs to handle the peak current. Alternatively a zener (+ series diode) from D-G will allow the FET to handle the current. You might need to increase the 10 Ω gate R to keep the zener currents within reason.

Answer 2

One idea is to make the primary resonant by adding a capacitor between the drains. Another is to add a 50V transient voltage suppressor between the drains.

Answer 3

First RC snub the output diodes this will waste power. Aim up your parts for low Q damping the resonance. Then turn off snub the mosfets wasting more power. Next do some energy recovery to get most of the power back.

Answer 4

I'll try to help by showing a simulation that is a bit easier to understand. I added some snubbers which seem to help reduce the transients without sapping too much power. It shows an efficiency of about 96% which is probably unrealistic, although most components have realistic ESR and other parameters.