Merge branch 'analogdevicesinc:main' into master

docs/projects/ad469x_fmc/index.rst

@@ -51,6 +51,26 @@ The data path and clock domains are depicted in the below diagram:
    :align: center
    :alt: AD469X_FMC block diagram
 
+Configuration modes
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The SPI_4WIRE configuration parameter defines if CNV signal is linked to PWM or
+to SPI_CS to enable interfacing with a single 4-wire SPI port. By default it is
+set to 0. Depending on the required pin functionality, some hardware
+modifications need to be done on the board and/or ``make`` command:
+
+In case we link CNV signal to PWM:
+
+.. code-block::
+
+   make SPI_4WIRE=0
+
+In case we link CNV signal to SPI_CS:
+
+.. code-block::
+
+   make SPI_4WIRE=1
+
 CPU/Memory interconnects addresses
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -128,6 +148,14 @@ The Software GPIO number is calculated as follows:
      - INOUT
      - 32
      - 86
+   * - gpio[33]
+     - IN
+     - 33
+     - 87
+
+BSY_ALT_GP0 pin can be configured to function as a general-purpose input/output
+(GPIO), the threshold detection alert indicator, the busy indicator, or the
+second serial data output in dual-sdo MODE
 
 Interrupts
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -156,7 +184,18 @@ the HDL repository, and then build the project as follows:
    :linenos:
 
    user@analog:~$ cd hdl/projects/ad469x_fmc/zed
-   user@analog:~/hdl/projects/ad469x_fmc/zed$ make
+   user@analog:~/hdl/projects/ad469x_fmc/zed$ make SPI_4WIRE=0
+
+The result of the build, if parameters were used, will be in a folder named
+by the configuration used:
+
+if the following command was run
+
+``SPI_4WIRE=0``
+
+then the folder name will be:
+
+``SPI4WIRE0``
 
 A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
 

library/spi_engine/spi_engine_execution/spi_engine_execution_constr.ttcl

@@ -30,6 +30,7 @@ set_property ASYNC_REG true [get_cells -hier {*last_sdi_bit_m_reg[1]}]
 set_false_path -to [get_cells -hier -filter {name =~ *last_sdi_bit_m_reg[0]* && IS_SEQUENTIAL}]
 
 # SDI shift registers are reset asynchronously after a negative edge of CSN - define the reset line as a false path
-set_false_path -to [get_pins -hierarchical -filter {NAME=~*g_echo_sclk_miso_latch.*.data_sdi_shift_reg[*]/CLR}]
+set_false_path -to [get_pins -hierarchical -filter {NAME=~*g_echo_sclk_miso_latch.*.data_sdi_shift_reg[*]/C*}]
+set_false_path -to [get_pins -hierarchical -filter {NAME=~*g_echo_sclk_miso_latch.*.sdi_data_latch_reg[*]/CE}]
 
 <: } :>

library/spi_engine/spi_engine_offload/spi_engine_offload_constr.ttcl

@@ -8,28 +8,9 @@
 <: setFileName [ttcl_add $ComponentName "_constr"] :>
 <: setFileExtension ".xdc" :>
 <: setFileProcessingOrder late :>
-<: set async_spi_clk [getBooleanValue "ASYNC_SPI_CLK"] :>
-
-<: if { $async_spi_clk } { :>
-
-set_property ASYNC_REG TRUE \
-  [get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
-  [get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
-
-set_false_path -quiet \
-  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_out/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
-set_false_path -quiet \
-  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_in/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
-
-set_false_path -quiet \
-  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
-
-set_false_path -quiet \
-  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enable/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
-
-set_false_path -quiet \
-  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enabled/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
 
+<: set async_trigger [getBooleanValue "ASYNC_TRIG"] :>
+<: if { $async_trigger } { :>
 set_false_path -quiet \
   -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_trigger/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
 

library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl

@@ -15,7 +15,7 @@ adi_ip_files spi_engine_offload [list \
 ]
 
 adi_ip_properties_lite spi_engine_offload
-adi_ip_ttcl axi_spi_engine "spi_engine_offload_constr.ttcl"
+adi_ip_ttcl spi_engine_offload "spi_engine_offload_constr.ttcl"
 
 set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload} [ipx::current_core]
 

projects/ad469x_fmc/Readme.md

@@ -9,3 +9,12 @@ Here are some pointers to help you:
   * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad469x
   * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad469x
   * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all
+# Building, Generating Bit Files
+
+How to use over-writable parameter from the environment:
+```
+hdl/projects/ad469x_fmc/zed> make SPI_4WIRE=0
+```
+SPI_4WIRE - Defines if CNV signal is linked to PWM or to SPI_CS
+* 0 - CNV signal is linked to PWM
+* 1 - CNV signal is linked to SPI_CS

projects/ad469x_fmc/common/ad469x_bd.tcl

@@ -3,6 +3,11 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
+# system level parameter
+
+set SPI_4WIRE $ad_project_params(SPI_4WIRE)
+puts "build parameter: SPI_4WIRE: $SPI_4WIRE"
+
 create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad469x_spi
 create_bd_port -dir O ad469x_spi_cnv
 create_bd_port -dir I ad469x_spi_busy

projects/ad469x_fmc/zed/system_constr.xdc

@@ -4,14 +4,14 @@
 ###############################################################################
 
 # ad4696_fmc SPI interface
-set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdi]       ; ## D08  FMC_LA01_CC_P  IO_L14P_T2_SRCC_34
-set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdo]       ; ## H07  FMC_LA02_P     IO_L20P_T3_34
-set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sclk]      ; ## D09  FMC_LA01_CC_N  IO_L14N_T2_SRCC_34
-set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cs]        ; ## G06  FMC_LA00_CC_P  IO_L13P_T2_MRCC_34
-set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cnv]       ; ## G07  FMC_LA00_CC_N  IO_L13N_T2_MRCC_34
+set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad469x_spi_sdi];  ## D08  FMC_LA01_CC_P  IO_L14P_T2_SRCC_34
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad469x_spi_sdo];  ## H07  FMC_LA02_P     IO_L20P_T3_34
+set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad469x_spi_sclk]; ## D09  FMC_LA01_CC_N  IO_L14N_T2_SRCC_34
+set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad469x_spi_cs];   ## G06  FMC_LA00_CC_P  IO_L13P_T2_MRCC_34
+set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cnv];           ## G07  FMC_LA00_CC_N  IO_L13N_T2_MRCC_34
 
-set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad469x_resetn]        ; ## H10  FMC_LA04_P     IO_L15P_T2_DQS_34
-set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad469x_busy_alt_gp0]  ; ## H08  FMC_LA02_N     IO_L20N_T3_34
+set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad469x_resetn];            ## H10  FMC_LA04_P     IO_L15P_T2_DQS_34
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad469x_busy_alt_gp0];      ## H08  FMC_LA02_N     IO_L20N_T3_34
 
 # rename auto-generated clock for SPIEngine to spi_clk - 160MHz
 # NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk

projects/ad469x_fmc/zed/system_project.tcl

@@ -7,7 +7,12 @@ source ../../../scripts/adi_env.tcl
 source ../../scripts/adi_project_xilinx.tcl
 source ../../scripts/adi_board.tcl
 
-adi_project ad469x_fmc_zed
+# Parameter description
+
+# SPI_4WIRE - For 0 CNV is linked to PWM. For 1 CNV is linked to SPI_CS
+
+adi_project ad469x_fmc_zed 0 [list \
+  SPI_4WIRE [get_env_param SPI_4WIRE 0]]
 
 adi_project_files ad469x_fmc_zed [list \
     "../../../library/common/ad_iobuf.v" \

projects/ad469x_fmc/zed/system_top.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -35,8 +35,9 @@
 
 `timescale 1ns/100ps
 
-module system_top (
-
+module system_top #(
+  parameter SPI_4WIRE = 0
+) (
   inout   [14:0]  ddr_addr,
   inout   [ 2:0]  ddr_ba,
   inout           ddr_cas_n,
@@ -107,9 +108,17 @@ module system_top (
   wire    [ 1:0]  iic_mux_sda_o_s;
   wire            iic_mux_sda_t_s;
 
-  // instantiations
+  wire            ad469x_spi_cnv_s;
+  wire            ad469x_spi_cs_s;
+
+  // instantiation
+
+  assign gpio_i[63:34] = 30'b0;
+
+  assign ad469x_spi_cnv = (SPI_4WIRE == 0) ? ad469x_spi_cnv_s : ad469x_spi_cs_s;
+  assign ad469x_spi_cs = ad469x_spi_cs_s;
 
-  assign gpio_i[63:33] = 31'b0;
+  assign gpio_i[33] = ad469x_busy_alt_gp0;
 
   ad_iobuf #(
     .DATA_WIDTH(1)
@@ -207,10 +216,10 @@ module system_top (
     .ad469x_spi_sdo (ad469x_spi_sdo),
     .ad469x_spi_sdo_t (),
     .ad469x_spi_sdi (ad469x_spi_sdi),
-    .ad469x_spi_cs (ad469x_spi_cs),
+    .ad469x_spi_cs (ad469x_spi_cs_s),
     .ad469x_spi_sclk (ad469x_spi_sclk),
     .ad469x_spi_busy(ad469x_busy_alt_gp0),
-    .ad469x_spi_cnv(ad469x_spi_cnv),
+    .ad469x_spi_cnv(ad469x_spi_cnv_s),
     .otg_vbusoc (otg_vbusoc),
     .spdif (spdif));
 

projects/adrv9009zu11eg/adrv2crr_fmcxmwbr1/system_project.tcl

@@ -17,12 +17,12 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 #   How to use over-writable parameters from the environment:
 #
 #    e.g.
-#      make ADI_PRODUCTION = 1
+#      make ADI_PRODUCTION = 0
 #
 #    ADI_PRODUCTION  - Defines the interface type (XMICROWAVE or FMCXMWBR1)
 #
-# LEGEND: 0 - XMICROWAVE - uses all the spi lines and gpios
-#         1 - FMCXMWBR1 - used for production testing
+# LEGEND: 0 - FMCXMWBR1 - used for production testing
+#         1 - XMICROWAVE - uses all the spi lines and gpios
 #
 ##-----------------------------------------------------------------------------
 
@@ -56,11 +56,11 @@ adi_project_files adrv9009zu11eg_fmcxmwbr1 [list \
 switch $intf {
   0 {
     adi_project_files adrv9009zu11eg_fmcxmwbr1 [list \
-      "system_top_xmicrowave.v" ]
+      "system_top_fmcxmwbr1.v" ]
   }
   1 {
     adi_project_files adrv9009zu11eg_fmcxmwbr1 [list \
-      "system_top_fmcxmwbr1.v" ]
+      "system_top_xmicrowave.v" ]
   }
 }