rustc_target: Add more RISC-V vector-related features and use zvl*b target features in vector ABI check #138742
+91
−5
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Currently, we have only unstable
v
target feature, but RISC-V have more vector-related extensions. The first commit of this PR adds them to unstableriscv_target_feature
.unaligned-vector-mem
: Has reasonably performant unaligned vectorunaligned-scalar-mem
target feature, but for vector instructions.zvfh
: Vector Extension for Half-Precision Floating-Pointzvfhmin
andzfhmin
zvfhmin
: Vector Extension for Minimal Half-Precision Floating-Pointzve32f
zve32x
,zve32f
,zve64x
,zve64f
,zve64d
: Vector Extensions for Embedded Processorszve32x
implieszvl32b
zve32f
implieszve32x
andf
zve64x
implieszve32x
andzvl64b
zve64f
implieszve32f
andzve64x
zve64d
implieszve64f
andd
v
implieszve64d
zvl*b
: Minimum Vector Length Standard Extensionszvl{N}b
implieszvl{N>>1}b
v
implieszvl128b
zvkb
: Vector Bit-manipulation used in Cryptographyzve32x
zvbb
: Vector basic bit-manipulation instructionszvkb
zvbc
: Vector Carryless Multiplicationzve64x
zvkg
: Vector GCM instructions for Cryptographyzve32x
zvkned
: Vector AES Encryption & Decryption (Single Round)zve32x
zvknha
: Vector SHA-2 (SHA-256 only))zve32x
zvknhb
: Vector SHA-2 (SHA-256 and SHA-512)zve64x
zvknha
, but doesn't imply that feature at least in LLVMzvksed
: SM4 Block Cipher Instructionszve32x
zvksh
: SM3 Hash Function Instructionszve32x
zvkt
: Vector Data-Independent Execution Latencyzkt
.zvkn
: Shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'zkn
.zvknc
: Shorthand for 'Zvkn' and 'Zvbc'zvkng
: shorthand for 'Zvkn' and 'Zvkg'zvks
: shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'zks
.zvksc
: shorthand for 'Zvks' and 'Zvbc'zvksg
: shorthand for 'Zvks' and 'Zvkg'Also, our vector ABI check wants
zvl*b
target features, the second commit of this PR updates vector ABI check to use them.rust/compiler/rustc_target/src/target_features.rs
Lines 707 to 708 in 4e2b096
r? @Amanieu
@rustbot label +O-riscv +A-target-feature