In this paper, we present a low-power receiver that supports high data rates over bandwidth-limited and coupled links. The receiver employs a half-rate 2-tap speculative DFE architecture with a far-end cross-talk (FEXT) cancellation technique. Figure 25.6.1 shows the top-level architecture of the DFE receiver. Conventionally, analog taps of the equalizer are implemented using current mode summers, thus the power consumption of the DFE increases proportion ally with the number of taps. In the proposed architecture, a switched-capacitor S/H is employed to sample the input signal and combine it with the feedback coefficients at the front-end of the receiver, as shown in Fig. 25.6.2 (S/H/summer). In this design, the switched-capacitor network is modified to support two taps of DFE without any signal loss. This technique can be further extended to realize more number of taps. The extra power due to sampling capacitors, switches and voltage-mode DACs is very small.