An H. 264/AVC decoder with 4/spl times/4-block level pipeline

TA Lin, SZ Wang, TM Liu, CY Lee - 2005 IEEE International …, 2005 - ieeexplore.ieee.org
4/spl times/4-block level pipelining architecture with instantaneous switching scheme and
optimal decoding … AVC video decoders, which adopt macroblock level pipelines, our proposed …

Architecture design of H. 264/AVC decoder with hybrid task pipelining for high definition videos

TW Chen, YW Huang, TC Chen… - … on Circuits and …, 2005 - ieeexplore.ieee.org
… pipelining, and frame-level pipelining. Previous designs of video decoders are usually
based on MB pipeline scheme [2]. In H.264, 4×4-block is the smallest element of the prediction …

An efficient pipeline architecture for deblocking filter in H. 264/AVC

CM Chen, CH Chen - IEICE TRANSACTIONS on Information and …, 2007 - search.ieice.org
… to be very time consuming in the decoder of this new video coding standard. … 4×4 block
edges of a picture, except for the edges at the boundary of the picture. Therefore, most of the 4×4

Methods for power/throughput/area optimization of H. 264/AVC decoding

K Xu, TM Liu, JI Guo, CS Choy - Journal of Signal Processing Systems, 2010 - Springer
… The cycle time for a single stage in the 4 × 4 block pipeline … the pipeline needs to be
synchronized every 4 × 4 block. Assuming a 4:2:0 chrominance format, the total time for decoding a …

Block-pipelining cache for motion compensation in high definition H. 264/AVC video decoder

X Chen, P Liu, J Zhu, D Zhou… - 2009 IEEE International …, 2009 - ieeexplore.ieee.org
… Basic idea of such strategy is to hide external memory latency with a welldesigned pipeline.
To explain the pipeline, we first divide the processing of each basic block in cache into four …

Hardware architecture design of an H. 264/AVC video codec

TC Chen, CJ Lian, LG Chen - Proceedings of the 2006 Asia and South …, 2006 - dl.acm.org
… AVC, not only the pipeline structure but also efficient memory hierarchy is required. The …
scheme including 4×4-block-level pipelining, MB-level pipelining, and frame-level pipelining. …

Implementation of H. 264/AVC baseline profile decoder for mobile video applications

SH Lee, JH Park, SW Kim, S Kim - 2005 12th IEEE …, 2005 - ieeexplore.ieee.org
… baseline profile decoder based on an SOC platform design methodology. The overall decoding
… We minimize the number ofbus accesses and use macroblock level pipeline processing …

Design and Implementation of H. 264/AVC Decoder

KB Lee - Mobile Multimedia Broadcasting Standards …, 2009 - Springer
… The bottom horizontal edge of this 4 ×4 block will be processed when its below … each
pipeline stage and to solve pipeline data and structure hazards [26, 80]. For multisymbol decoding

A 0.7-v 1.8-mw H. 264/AVC 720p video decoder

V Sze, DF Finchelstein, ME Sinangil… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
… a hybrid 4 4 block/macroblock pipeline scheme. In this work, a 4 4 block pipelining scheme
the 4 4 block level, DVFS allows the decoder to address the varying workload at the frame …

A power-efficient and self-adaptive prediction engine for H. 264/AVC decoding

K Xu, CS Choy - IEEE Transactions on very large scale …, 2008 - ieeexplore.ieee.org
4 block level pipeline. Based on the different prediction requirements, the prediction pipeline
4 level pipeline requires the calculation of each 4 4 block in double-z order instead of …