A spacer-type self-aligned double pattering (SADP) is a pitch-splitting sidewall image method that is a major option for sub-30nm device node manufacturing due to its lower overlay sensitivity and better process window compared to other double patterning processes, such as litho-etch-litho-etch (LELE). SADP is in production use for 1D patterns in NAND Flash memory applications but applying SADP to 2D random logic patterns is challenging. In this paper, we describe the first layout decomposition methods of SADP lithography for complex 2D layouts. The favored type of SADP for complex logic interconnects is a two mask approach using a core (mandrel) mask and a trim mask. This paper describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in SADP process. We evaluate our technique on 22nm node industrial standard cells and logic designs. Experimental results show that our proposed layout decomposition for SADP effectively decomposes many challenging 2D layouts.