User profiles for Shih-Lien Lu
Shih-Lien Lu (Linus)Washington State University Verified email at wsu.edu Cited by 9523 |
Speeding up processing with approximation circuits
SL Lu - Computer, 2004 - ieeexplore.ieee.org
Current microprocessors employ a global timing reference to synchronize data transfer. A
synchronous system must know the maximum time needed to compute a function, but a circuit …
synchronous system must know the maximum time needed to compute a function, but a circuit …
Trading off cache capacity for reliability to enable low voltage operation
One of the most effective techniques to reduce a processor’s power consumption is to
reduce supply voltage. However, reducing voltage in the context of manufacturing-induced …
reduce supply voltage. However, reducing voltage in the context of manufacturing-induced …
[BOOK][B] The electronics handbook
…, R Kasturi, R Kubichek, G Lakhani, F Long, SL Lu… - 2018 - taylorfrancis.com
During the ten years since the appearance of the groundbreaking, bestselling first edition of
The Electronics Handbook, the field has grown and changed tremendously. With a focus on …
The Electronics Handbook, the field has grown and changed tremendously. With a focus on …
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
Large last-level caches (L 3 Cs) are frequently used to bridge the performance and power
gap between processor and memory. Although traditional processors implement caches as …
gap between processor and memory. Although traditional processors implement caches as …
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM)
caches. eDRAM is significantly denser than traditional SRAMs, but must be …
caches. eDRAM is significantly denser than traditional SRAMs, but must be …
Energy-efficient cache design using variable-strength error-correcting codes
Voltage scaling is one of the most effective mechanisms to improve microprocessors' energy
efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin, …
efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin, …
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power
consumption. However, the increased severity of manufacturing-induced parameter variations …
consumption. However, the increased severity of manufacturing-induced parameter variations …
[PDF][PDF] STTRAM SCALING AND RETENTION FAILURE.
In this article, we focus on the solutions in the second category, that is, relaxing the nonvolatility
condition to allow lower bound on D. Although there have been an extensive number of …
condition to allow lower bound on D. Although there have been an extensive number of …
Improving DRAM latency with dynamic asymmetric subarray
The evolution of DRAM technology has been driven by capacity and bandwidth during the
last decade. In contrast, DRAM access latency stays relatively constant and is trending to …
last decade. In contrast, DRAM access latency stays relatively constant and is trending to …
RAMP: Research accelerator for multiple processors
… Shih-Lien Lu has a BS in electrical engineering and computer sciences from the University
of California, Berkeley, and an MS and a PhD, both in computer science and engineering, …
of California, Berkeley, and an MS and a PhD, both in computer science and engineering, …