User profiles for Shih-Lien Lu

Shih-Lien Lu (Linus)

Washington State University
Verified email at wsu.edu
Cited by 9523

Speeding up processing with approximation circuits

SL Lu - Computer, 2004 - ieeexplore.ieee.org
Current microprocessors employ a global timing reference to synchronize data transfer. A
synchronous system must know the maximum time needed to compute a function, but a circuit …

Trading off cache capacity for reliability to enable low voltage operation

…, AR Alameldeen, Z Chishti, M Khellah, SL Lu - ACM SIGARCH …, 2008 - dl.acm.org
One of the most effective techniques to reduce a processor’s power consumption is to
reduce supply voltage. However, reducing voltage in the context of manufacturing-induced …

[BOOK][B] The electronics handbook

…, R Kasturi, R Kubichek, G Lakhani, F Long, SL Lu… - 2018 - taylorfrancis.com
During the ten years since the appearance of the groundbreaking, bestselling first edition of
The Electronics Handbook, the field has grown and changed tremendously. With a focus on …

Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM

MT Chang, P Rosenfeld, SL Lu… - 2013 IEEE 19th …, 2013 - ieeexplore.ieee.org
Large last-level caches (L 3 Cs) are frequently used to bridge the performance and power
gap between processor and memory. Although traditional processors implement caches as …

Reducing cache power with low-cost, multi-bit error-correcting codes

…, Z Chishti, W Wu, D Somasekhar, S Lu - Proceedings of the 37th …, 2010 - dl.acm.org
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM)
caches. eDRAM is significantly denser than traditional SRAMs, but must be …

Energy-efficient cache design using variable-strength error-correcting codes

…, Z Chishti, W Wu, C Wilkerson, SL Lu - ACM SIGARCH …, 2011 - dl.acm.org
Voltage scaling is one of the most effective mechanisms to improve microprocessors' energy
efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin, …

Improving cache lifetime reliability at ultra-low voltages

…, AR Alameldeen, C Wilkerson, W Wu, SL Lu - Proceedings of the 42nd …, 2009 - dl.acm.org
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power
consumption. However, the increased severity of manufacturing-induced parameter variations …

[PDF][PDF] STTRAM SCALING AND RETENTION FAILURE.

H Naeimi, C Augustine, A Raychowdhury, SL Lu… - intel technology …, 2013 - intel.com
In this article, we focus on the solutions in the second category, that is, relaxing the nonvolatility
condition to allow lower bound on D. Although there have been an extensive number of …

Improving DRAM latency with dynamic asymmetric subarray

SL Lu, YC Lin, CL Yang - … of the 48th International Symposium on …, 2015 - dl.acm.org
The evolution of DRAM technology has been driven by capacity and bandwidth during the
last decade. In contrast, DRAM access latency stays relatively constant and is trending to …

RAMP: Research accelerator for multiple processors

J Wawrzynek, D Patterson, M Oskin, SL Lu… - IEEE micro, 2007 - ieeexplore.ieee.org
Shih-Lien Lu has a BS in electrical engineering and computer sciences from the University
of California, Berkeley, and an MS and a PhD, both in computer science and engineering, …