Experiment No.: 02 Experiment Name: Objective

EXPERIMENT No.: 02 EXPERIMENT NAME: SPICE simulations of logic gates.
OBJECTIVE:
The objectives of this experiment are: (a). To simulate CMOS NAND and NOR logic gates using SPICE and compare their performance. (b). Sizing the transistors for symmetrical NAND and NOR gates, that is, ensuring identical rise and fall times. (c). To simulate a 6-transistor CMOS inverter that provides sharper Voltage Transfer Characteristics.
INTRODUCTION: CMOS technology uses to construct logical gates such as Inverter, NOR and NAND gate. MOS transistor is not faster than the BJT but it take less power than BJT and large no MOSs circuit can be fabricate in a small place but it is almost impossible for BJT. NAND, NOR those logic gates can be constructed by CMOS. CMOS consists of 1 nMOS and 1 pMOS. pMOS transistor are used as pull up transistor and nMOS are uses as pull down. In this experiment we simulate NAND, NOR and 6-Transis Inverter gate for DC and transient analysis to examine the characteristics for those circuits.
2-Input NAND GATE:
Logic-Lavel of Input VA
Logic-Lavel of Input VB
State MPU1
of State MPU2
of State MPD1
of State MPD2
of
Logic-Level of Gate Output
0 0 1 1
0 1 0 1
On On Off Off
On Off On Off
Off Off On On
Off On Off On
1 1 1 0
Examining the truth table we can say this circuit is working as 2-Input NAND gate. For equal rise time and fall time we consider the symmetric inverter as a reference which we examine at Lab1. So for the transistor sizing we take w=13m and l=3m for pMOS and w=4m and l=3m for nMOS. SPICE code is given in the next page.
CODES: *CMOS 2-INPUT NAND GATE vdd 1 0 5 vA 3 0 pulse(0 5 0.3ns 0.3ns 0.3ns 10ns 20ns) vB 4 0 pulse(0 5 0.3ns 0.3ns 0.3ns 20ns 40ns) mpu1 2 3 1 1 penh w=13u l=3u mpu2 2 4 1 1 penh w=13u l=3u mpd1 2 3 5 5 nenh w=8u l=3u mpd2 5 4 0 0 nenh w=8u l=3u .model nenh nmos level=2 vto=0.85 +kp=30e-6 tox=470e-10 nsub=38e14 +ld=0.6e-6 u0=624 uexp=0.055 vmax=20e4 +neff=9.8 delta=2.0 +cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33 +pb=0.81 cgdo=4.0e-11 cgso=4.0e-11 cgbo=2.0e-11 .model penh pmos level=2 vto=-0.85 +kp=12e-6 tox=470e-10 nsub=8.7e14 +ld=0.5e-6 u0=200 uexp=0.18 vmax=12e4 +neff=4.0 delta=2.0 +cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 +pb=0.7 cgdo=4.0e-11 cgso=4.0e-11 cgbo=2.0e-11 cl 2 0 50f .tran 1ns 80ns .probe .end
GRAPH:
V B
VA
Vou t
2-Input NOR GATE:
Logic-Lavel of Input VA
Logic-Lavel of Input VB
State MPU1
of State MPU2
of State MPD1
of State MPD2
of
Logic-Level of Gate Output
0 0 1 1
0 1 0 1
On On Off Off
On Off On Off
Off Off On On
Off On Off On
1 0 0 0
Examining the truth table we can say this circuit is working as 2-Input NOR gate. For equal rise time and fall time we consider the symmetric inverter as a reference which we examine at Lab1. So for the transistor sizing we take w=13m and l=3m for pMOS and w=4m and l=3m for nMOS. SPICE code is given in the next page.
CODES: *CMOS 2-INPUT NOR GATE mpu1 2 5 1 1 penh w=13u l=3u mpu2 3 4 2 2 penh w=13u l=3u mpd1 3 5 0 0 nenh w=4u l=3u mpd2 3 4 0 0 nenh w=4u l=3u VA 5 0 pulse(0 5 0.3ns 0.3ns 0.3ns 10ns 20ns) VB 4 0 pulse(0 5 0.3ns 0.3ns 0.3ns 20ns 40ns) vdd 1 0 5 .model nenh nmos level=2 vto=.85 kp=30e-6 tox=470e-10 nsub=38e14 +ld=0.6e-6 uo=624 uexp=0.055 vmax=20e4 neff=9.8 delta=2.0 + cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33 pb=0.81 .model penh pmos level=2 vto=-.85 kp=12e-6 tox=470e-10 nsub=8.7e14 +ld=0.5e-6 uo=200 uexp=0.18 vmax=12e4 neff=4.0 delta=2.0 + cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 pb=0.7 cl 3 0 50ff .tran 1ns 80ns .probe .end
GRAPH:
VB
Vou t
6-TRANSISTOR INVERTER:
CODES: *TRANSISTOR CMOS INVERTER vdd 1 0 5 vin 5 0 pulse(0 5 0us 0.5us 0.5us 10us 20us) mpu1 2 5 1 1 penh w=13u l=3u mpu2 3 5 2 2 penh w=13u l=3u mpu3 0 3 2 2 penh w=13u l=3u mpd1 3 5 4 4 nenh w=4u l=3u mpd2 4 5 0 0 nenh w=4u l=3u mpd3 1 3 4 4 nenh w=4u l=3u .model nenh nmos level=2 vto=0.85 +kp=30e-6 tox=470e-10 nsub=38e14 +ld=0.6e-6 u0=624 uexp=0.055 vmax=20e4 +neff=9.8 delta=2.0 +cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33 +pb=0.81 cgdo=4.0e-11 cgso=4.0e-11 cgbo=2.0e-11 .model penh pmos level=2 vto=-0.85 +kp=12e-6 tox=470e-10 nsub=8.7e14 +ld=0.5e-6 u0=200 uexp=0.18 vmax=12e4 +neff=4.0 delta=2.0 +cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 +pb=0.7 cgdo=4.0e-11 cgso=4.0e-11 cgbo=2.0e-11 cl 3 0 100ff
.tran 1us 80us .dc vin 0 5 0.1 .probe .end
GRAPH:
Vi
Vou
Ids
Vou t Vin
FIG-1:- Voltage Transfer Characteristics (Vout vs. Vin) and Ids vs. Vin (6-Transistor Inverter)
Id
Vou Vi
FIG-2:- Voltage Transfer Characteristics (Vout vs. Vin) and Ids vs. Vin (Typical Inverter)
Comparing both FIG-1 and FIG-2 we can see that the 6-Transistor Inverter is faster than the Typical Inverter. The transition from logic 1(5V) to logic 0 (0V) of 6-Transistor Inverter is faster than the Typical Symmetric Inverter. Again from the Ids vs. Vin curve we can see that Ids current flows for a short time for 6-Transistor Inverter and it is less than 3A, in other hand Ids flows for a long time for Typical Symmetric Inverter and it is nearly 70A. So, the power dissipation of 6-Transistor Inverter is lesser than Typical Symmetric Inverter. Discussion: We simulated CMOS NAND and CMOS NOR gate. To make the rise time and fall time of Vout of NAND and NOR gate, we consider symmetrical inverter as reference. For that reason we put w=13m for pMOS and w=3m for nMOS. Generally the w of the pMOS is three times greater than the w of the nMOS to make the circuit symmetric. This is occurred because the mobility of the hole is not as fast as electron. Lastly we simulate dc and transient analysis of a 6-Transistor Inverter and we observe that Typical Inverter is slower than the 6-transistor Inverter and Typical 2-Transistor takes much power than the other Inverter.

Experiment No.: 02 Experiment Name: Objective

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Experiment No.: 02 Experiment Name: Objective

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EXPERIMENT No.: 02 EXPERIMENT NAME: SPICE simulations of logic gates.

2-Input NAND GATE:

Logic-Level of Gate Output

2-Input NOR GATE:

Logic-Level of Gate Output

.tran 1us 80us .dc vin 0 5 0.1 .probe .end

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