Contents:

Introduction
Block Diagram and Pin Description of the 8051
Registers
Memory mapping in 8051
Stack in the 8051
I/O Port Programming
Timer
Interrupt
 Why do we need to learn
Microprocessors/controllers?
 The microprocessor is the core of
computer systems.
 Nowadays many communication, digital
entertainment, portable devices, are
controlled by them.
 A designer should know what types of
components he needs, ways to reduce
production costs and product reliable.
 Different aspects of a
microprocessor/controller

 Hardware :Interface to the real world

 Software :order how to deal with inputs

 The necessary tools for a
microprocessor/controller
 CPU: Central Processing Unit
 I/O: Input /Output
 Bus: Address bus & Data bus
 Memory: RAM & ROM
 Timer
 Interrupt
 Serial Port
 Parallel Port
 Microprocessors:
General-purpose microprocessor
 CPU for Computers
 No RAM, ROM, I/O on CPU chip itself
 Example ： Intel’s x86, Motorola’s 680x0

Many chips on mother’s board

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus

General-Purpose Microprocessor System

 Microcontroller :
 A smaller computer
 On-chip RAM, ROM, I/O ports...
 Example ： Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X

CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller
Microprocessor vs. Microcontroller
Microprocessor Microcontroller
 CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
 designer can decide on the • fix amount of on-chip ROM,
amount of ROM, RAM and RAM, I/O ports
I/O ports. • for applications in which cost,
 expansive power and space are critical
 versatility • single-purpose
 general-purpose
 Embedded System

 Embedded system means the processor is embedded into that

application.
 An embedded product uses a microprocessor or microcontroller to do
one task only.
 In an embedded system, there is only one application software that is
typically burned into ROM.
 Example ： printer, keyboard, video game player
 Three criteria in Choosing a Microcontroller

1. meeting the computing needs of the task efficiently and cost

effectively
• speed, the amount of ROM and RAM, the number of I/O ports
and timers, size, packaging, power consumption
• easy to upgrade
• cost per unit
1. availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator,
technical support
1. wide availability and reliable sources of the microcontrollers.
 Block Diagram
External interrupts
On-chip Timer/Counter

Interrupt ROM for

On-chip Timer 1 Counter
Control program
code RAM Timer 0 Inputs

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/Data
Pin Description of the 8051
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0
P1.2 3 38 P
) 0.1(AD1)
P1.3 4 8051 37 P0.2(AD2
P
P1.4 5 36 ) 0.3(AD3)
P1.5 6 (8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14
(T1)P3.5 15 26 )P2.5(A13
(WR)P3.6 16 25 P
) 2.4(A12
(RD)P3.7 17 24 )P2.3(A11
XTAL2 18 23 P ) 2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8) 
 Pins of 8051 （ 1/4 ）

 Vcc （ pin 40 ）：
– Vcc provides supply voltage to the chip.
– The voltage source is +5V.
 GND （ pin 20 ）： ground
 XTAL1 and XTAL2 （ pins 19,18 ）
 Figure (a). XTAL Connection to 8051

 Using a quartz crystal oscillator

 We can observe the frequency on the XTAL2 pin.

C2
XTAL2
30pF

C1
XTAL1
30pF

GND


 Pins of 8051 （ 2/4 ）

 RST （ pin 9 ）： reset

– It is an input pin and is active high （ normally low ） .
 The high pulse must be high at least 2 machine cycles.
– It is a power-on reset.
 Upon applying a high pulse to RST, the
microcontroller will reset and all values in registers
will be lost.
 Reset values of some 8051 registers 
 Figure (b). Power-On RESET Circuit
Vcc

10 uF 31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST


 Pins of 8051 （ 3/4 ）

 /EA （ pin 31 ）： external access

– There is no on-chip ROM in 8031 and 8032 .
– The /EA pin is connected to GND to indicate the code is
stored externally.
– /PSEN ＆ ALE are used for external ROM.
– For 8051, /EA pin is connected to Vcc.
– “/” means active low.
 /PSEN （ pin 29 ）： program store enable
– This is an output pin and is connected to the OE pin of the
ROM.
 Pins of 8051 （ 4/4 ）

 ALE （ pin 30 ）： address latch enable

– It is an output pin and is active high.
– 8051 port 0 provides both address and data.
– The ALE pin is used for de-multiplexing the address
and data by connecting to the G pin of the 74LS373
latch.
 I/O port pins
– The four ports P0, P1, P2, and P3.
– Each port uses 8 pins.
– All I/O pins are bi-directional.
 Pins of I/O Port

 The 8051 has four I/O ports

– Port 0 （ pins 32-39 ）： P0 （ P0.0 ～ P0.7 ）
– Port 1 （ pins 1-8 ） ： P1 （ P1.0 ～ P1.7 ）
– Port 2 （ pins 21-28 ）： P2 （ P2.0 ～ P2.7 ）
– Port 3 （ pins 10-17 ）： P3 （ P3.0 ～ P3.7 ）
– Each port has 8 pins.
 Named P0.X （ X=0,1,...,7 ） , P1.X, P2.X, P3.X
 Ex ： P0.0 is the bit 0 （ LSB ） of P0
 Ex ： P0.7 is the bit 7 （ MSB ） of P0
 These 8 bits form a byte.
 Each port can be used as input or output (bi-direction).

 Hardware Structure of I/O Pin
 Each pin of I/O ports
– Internal CPU bus ： communicate with CPU
– A D latch store the value of this pin
 D latch is controlled by “Write to latch”
– Write to latch ＝ 1 ： write data into the D latch
– 2 Tri-state buffer ：
 TB1: controlled by “Read pin”
– Read pin ＝ 1 ： really read the data present at the pin
 TB2: controlled by “Read latch”
– Read latch ＝ 1 ： read value from internal latch
– A transistor M1 gate
 Gate=0: open
 Gate=1: close
D Latch:
 A Pin of Port 1

Read latch Vcc

TB2
Load(L1)

Internal CPU D Q P1.X

bus P1.X pin

Write to latch Clk Q M1

TB1
Read pin P0.x
8051 IC
 Writing “1” to Output Pin P1.X

Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
D Q 1 P1.X
Internal CPU
bus P1.X pin
0 output 1
Write to latch Clk Q M1

TB1
Read pin

8051 IC
 Writing “0” to Output Pin P1.X

Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 0 to the pin ground
D Q 0 P1.X
Internal CPU
bus P1.X pin
1 output 0
Write to latch Clk Q M1

TB1
Read pin

8051 IC
 Reading “High” at Input Pin

Read latch Vcc 2. MOV A,P1

TB2 external pin=High
1. write a 1 to the pin MOV Load(L1)
P1,#0FFH

1 1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC
 Reading “Low” at Input Pin

Read latch Vcc 2. MOV A,P1

TB2
1. write a 1 to the pin Load(L1) external pin=Low
MOV P1,#0FFH
1 0 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC
 Other Pins
 P1, P2, and P3 have internal pull-up resisters.
– P1, P2, and P3 are not open drain.
 P0 has no internal pull-up resistors and does not
connects to Vcc inside the 8051.
– P0 is open drain.
– Compare the figures of P1.X and P0.X. 
 However, for a programmer, it is the same to program
P0, P1, P2 and P3.
 All the ports upon RESET are configured as output.
 A Pin of Port 0

Read latch
TB2

Internal CPU D Q P0.X

bus P1.X pin

Write to latch Clk Q M1

TB1
Read pin P1.x

8051 IC
Port 0 with Pull-Up Resistors

Vcc
10 K

P0.0
DS5000 P0.1

Port 0
P0.2
8751 P0.3
8951 P0.4
P0.5
P0.6
P0.7
Port 3 Alternate Functions
P3 Bit Function Pin

P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17 
 RESET Value of Some 8051 Registers:

Register Reset Value

PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000
RAM are all zero.

 Registers
A

R0
DPTR DPH DPL
R1

R2 PC PC
R3

R4 Some 8051 16-bit Register

R5

R6

R7

Some 8-bitt Registers of

the 8051
 Memory mapping in 8051

 ROM memory map in 8051 family

4k 8k 32k
0000H 0000H 0000H

0FFFH
DS5000-32

1FFFH
8751
AT89C51
8752
AT89C52 7FFFH

from Atmel Corporation

from Dallas Semiconductor
 RAM memory space allocation in the 8051

7FH

Scratch pad RAM

30H

2FH
Bit-Addressable RAM

20H
1FH Register Bank 3
18H
17H
Register Bank 2
10H
0FH Stack) Register Bank 1)
08H
07H
Register Bank 0
00H
 Stack in the 8051
 The register used to access 7FH
the stack is called SP (stack
Scratch pad RAM
pointer) register.
30H

 The stack pointer in the 8051 2FH

Bit-Addressable RAM
is only 8 bits wide, which 20H
means that it can take value 1FH Register Bank 3
00 to FFH. When 8051 18H
17H
powered up, the SP register 10H
Register Bank 2

contains value 07. 0FH Stack) Register Bank 1)

08H
07H
Register Bank 0
00H
Timer :
 TMOD Register:

 Gate : When set, timer only runs while INT(0,1) is

high.
 C/T : Counter/Timer select bit.
 M1 : Mode bit 1.
 M0 : Mode bit 0.
 TCON Register:

 TF1: Timer 1 overflow flag.

 TR1: Timer 1 run control bit.
 TF0: Timer 0 overflag.
 TR0: Timer 0 run control bit.
 IE1: External interrupt 1 edge flag.
 IT1: External interrupt 1 type flag.
 IE0: External interrupt 0 edge flag.
 IT0: External interrupt 0 type flag.
Interrupt :
Interrupt Enable Register :

 EA : Global enable/disable.
 --- : Undefined.
 ET2 :Enable Timer 2 interrupt.
 ES :Enable Serial port interrupt.
 ET1 :Enable Timer 1 interrupt.
 EX1 :Enable External 1 interrupt.
 ET0 : Enable Timer 0 interrupt.
 EX0 : Enable External 0 interrupt.