Chapter 6 Basic Input and

Output interface
 Objective
 The operation of buffered input ports
 The operation of latched output ports
 I/O addressing space
 The design of full and partial I/O address
decoders
 Basic I/O instruction
 Basic data transfer mode
 Key terms
• I/O
• Peripheral equipment 外部设备
• Electric level 电平
• Mismatch 不匹配
• Buffer 缓冲器
• Latch 锁存器
• Decoder 译码器
• DMA 存储器直接存取
• Interrupt 中断
• Memory-mapped 存储器映像
• Mechatronics 机电一体化
• Polling 查询
 6.1 Introduction
• I/O devices are used to
bring data into CPU
from an external device Microprocessor
such as keyboard or to
send data from CPU to
an external device such
as printer I/O devices Memory
• I/O instructions
• I/O design
 Necessity of I/O interface
• Multiplicity in peripherals

• Great differences b/t CPU and

peripherals in working principle,
driving mode, information type and
running speed.

• Peripherals could not directly link to

CPU.
 Problems of switch information
• Data transmission speed’s inconsistency

• Signal level’s mismatching

• Signal format’s mismatching

• Timing’s mismatching
I/O interface circuit:
medium circuits to link peripherals and CPU
 I/O interface circuit
• Programmable interface chip, I/O bus
slots
– Assistant data transfer
– Control logical unit

I/O I/O
CPU Interface
Device
Circuit
6.2 Function of Interface circuits
• 1. Buffer and Latch: Solve the problem of
inconsistency speed.
• 2. Transform information and data:
Convert format and logic level
• 3. Address decoding
• 4. Timing control
 6.3 Basic I/O Interface Chips
• Basic Input and Output Interfaces
– A. The basic input device is a set of three-
state buffers.
– B. The basic output device is a set of data
latches.
• Buffered Input chip
– 74LS244, 74LS245
• Latched Output Port
– 74LS373
 74LS244
• Two 4-bit buffers
INPUT OUTPUT

1G 1A 1Y
L L L
L H H
H X Z

INPUT OUTPUT

2G 2A 2Y
L L L
L H H
H X Z
 74LS245
• Bidirectional bus transceiver

ENABLE DIRECTION OPERATION

CONTROL

G DIR
L L B Data to A Bus
L H A Data to B bus
H X Isolation
 Example
• DEN: Data Enable
• DT/R: Data transmit/receive
 74LS373

OC: Output control

C: Clock

INPUTS OUTPUT
OC C D Q
L H H H
L H L L
L L x Q0
H x x Z
Example
 Review
• Necessity of I/O interface

• Basic I/O chips

– 74LS244
– 74LS245
– 74LS373
 6.4 Basic I/O operation
• I/O space to access ports
– Bring data into CPU
– Send data from CPU

• Addressing the I/O port

– Memory mapped
– I/O mapped
 Memory mapped
FFFFF
• I/O registers act like read-
write RAM Memory
• Advantages:
Memory
– No programming difference
between I/O data transfer and Space
memory data transfer I/O
– Wide range of instructions 00000
and addressing mode
• Disadvantages:
– Reduces the number of
memory locations available
Example circuit
 I/O mapped mode(I/O isolated)
• Special I/O control line FFFFFH
• Separate memory space for
I/O ports
• Different I/O instructions for I/O Memory
operations FFFFH
• Advantages: I/O
– Save the memory locations 0
available
• Disadvantages:
– I/O instructions are limited
– Additional control lines needed,
so complex
6.4.3 Basic I/O instructions
IN/OUT ---Transfer data between an I/O and micro
processor’s accumulator

Mnemonic Meaning Format Operation

IN Input direct IN Acc, port (Acc ） (Port)
Input indirect(variable) IN Acc, DX (Acc ） ((DX))
OUT Output direct OUT port, Acc (Port ） (Acc)
Output indirect(variable) OUT DX, Acc ((DX))(Acc)

Acc=AX or AL

Difference between direct and indirect:

Method for specifying address
Direct: address of I/O is indicated directly, 8-bit, so 256 I/O
Indirect: address is in DX, 16-bit,so 64K I/O
I/O address
Fixed port: address on A7-A0 while A15-A8 a
re zero.
Variable port: address on A15-A0. 16-bit I/O
address in DX.

The 00H-FFH can be accessed by both ports,

but 0000H-FFFFH only by variable port.
 Examples
• Input instructions
IN AL,05H ;input the data in byte size
MOV DX, 21H
IN AL,DX ;input the data in byte size
IN AX,21H ;input the data in word size
MOV DX, 21H
IN AX,DX ;input the data in word size
• Output instructions
OUT 21H,AL ;output the data in byte size
MOV DX, 21H
OUT DX,AL ;output the data in byte size
OUT 21H,AX ;output the data in word size
MOV DX,21H
OUT DX,AX ;output the data in word size
 6.5 Data transfer format and mode
• Byte size: one bus cycle
• Word size: two bus cycle

• Three ways of exchanging data between

CPU and I/O
– Polling routine mode
– Interrupt mode
– Direct memory Access (DMA) mode
6.5.1 Polling routine mode
 1) Polling input port
8 bit
8D
mov dx,8000h Buffer
； let DX pointD to
～ status
D port
Latch 0
status:
Input in al,dx ； read status 7
port
Device test al,01h ； test service-request bit IOR
+5V 1；bitif D0=0, continue8001H
jz status polling
RQ Buffer D0
inc dx D ； else D0=1, Decode
ready to read A0 ～ A15
in al,dx ； read the data from 8000HI/O port
STB
IOR
 2) Polling output port
8 bit
mov dx,8000h ； Let DX point D0 to
～ status
D7 port
Latch
status: in al,dx +5V ； read status port
Output Q al,80h
test D ； test status bit D7
Device IOW
jnz status
R ； if D7 ＝ 1 ， continue polling
1 bit 8001H
inc dx ； otherwise D7 ＝ 0 ， ready, DX
ACK Buffer
point D7 Decode A0 ～ A15
to I/O port
mov al,buf ； move buf to AL 8000H
out dx,al ； move the data to Output port IOR
6.5.2 Interrupt mode
 6.5.3 DMA mode
• The DMA I/O technique provides direct
access to the memory while the
microprocessor is temporarily disabled.

• This allows data to be transferred between

memory and the I/O device at a rate that is
limited by the speed of the memory
component in the system or the DMA
controller.
 DMA Operation procedure
⑴ CPU initialize the DMA controller (DMAC)
⑵ CPU release the bus and give it to DMAC
⑶ DMA transfer
– DMA read memory ： Memory → I/O device
– DMA write memory ： Memory ← I/O device
⑷ Increase or decrease address, and judge whether it
finishes or not
MEM

cpu I/O
BUS

DMAC
 Flowchart of DMA
HLDA

Send the address of memory

Transfer data Modify the address

End ？

END
 Basic DMA operation
• A. Two control signals are used to request and a
cknowledge a DMA transfer.
• HOLD : input of microprocessor, request a DMA
action
• HLDA : output of microprocessor, acknowledge t
he DMA action.

• HOLD=1------DMA request------a few clocks, by s

uspending the execution of the program and by
placing its AB, DB and CB at high-impedance st
ates.
 Basic DMA operation
• B. Priority:
(highest) Reset , DMA, NMI/INTR (lower)

• HOLD: sampled in the middle of any clocki

ng cycle and take effect any time during the
operation of any instruction.

• Interrupts only take effect at the end of an i

nstruction
 Basic DMA operation
• C. DMA normally occurs between an I/O device and
memory without the use of the microprocessor.

– A DMA read transfers data from the memory to th

e I/O device.

– A DMA write transfers data from and I/O device t

o memory.
• In both operations, the memory and I/O are controll
ed simultaneously, and this is why the system conta
ins separate memory and I/O control signals.
 Basic DMA operation
– A DMA read causes both the MRDC and IOW
C signals to simultaneously activate.

– A DMA write causes both the MWTC and IOR

C signals to simultaneously activate.
6.6 Application of Basic I/O interface
• Binary counter
• Sine wave generator
• Traffic light port
• Stepper motor
• Robot port
 Summary
• Two basic I/O instructions
– IN, INSB or INSW
– OUT, OUTSB or OUTSW
• Two I/O address mode
– Memory-mapped
– Isolated I/O (I/O mapped)
• Three data transfer mode
– Polling routine
– Interrupt
– DMA
 Assignments
• 1. To which register are data input to by
the 16 bit IN instruction?
• 2. Contrast a memory-mapped I/O with an
isolated I/O. (Differences, advantages,
disadvantages…)
• 3. Give the summary of three data transfer
mode: polling service mode, interrupt
mode and DMA mode.