- Free download as PDF File (.pdf), Text File (.txt) or read online for free. The SN54/74LS280 is a 9-bit universal parity generator and checker that can generate either odd or even parity outputs. It has buffered inputs to reduce the drive requirements and can be cascaded to expand the word length. This device improves upon the LS180 by allowing it to be substituted without any changes to functionality.">
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9-Bit Odd/Even Parity Generators/Checkers SN54/74LS280: Low Power Schottky

The SN54/74LS280 is a 9-bit universal parity generator and checker that can generate either odd or even parity outputs. It has buffered inputs to reduce the drive requirements and can be cascaded to expand the word length. This device improves upon the LS180 by allowing it to be substituted without any changes to functionality.

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district19
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50 views2 pages

9-Bit Odd/Even Parity Generators/Checkers SN54/74LS280: Low Power Schottky

The SN54/74LS280 is a 9-bit universal parity generator and checker that can generate either odd or even parity outputs. It has buffered inputs to reduce the drive requirements and can be cascaded to expand the word length. This device improves upon the LS180 by allowing it to be substituted without any changes to functionality.

Uploaded by

district19
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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SN54/74LS280 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

The SN54 / 74LS280 is a Universal 9-Bit Parity Generator / Checker. It features odd / even outputs to facilitate either odd or even parity. By cascading, the word length is easily expanded. The LS280 is designed without the expander input implementation, but the corresponding function is provided by an input at Pin 4 and the absence of any connection at Pin 3. This design permits the LS280 to be substituted for the LS180 which results in improved performance. The LS280 has buffered inputs to lower the drive requirements to one LS unit load.

9-BIT ODD / EVEN PARITY GENERATORS/ CHECKERS


LOW POWER SCHOTTKY

Generates Either Odd or Even Parity for Nine Data Lines Typical Data-to-Output Delay of only 33 ns Cascadable for n-Bits Can Be Used To Upgrade Systems Using MSI Parity Circuits Typical Power Dissipation = 80 mW
INPUTS VCC 14 F 13 F G H 1 G 2 H 3 NC I E 12 E D 11 D C 10 C B 9 B A A 8

J SUFFIX CERAMIC CASE 632-08


14 1

14 1

N SUFFIX PLASTIC CASE 646-06

EVEN ODD

4 5 6 7 GND I INPUT EVEN ODD OUTPUTS

14 1

D SUFFIX SOIC CASE 751A-02

INPUTS

ORDERING INFORMATION FUNCTION TABLE


NUMBER OF INPUTS A THRU 1 THAT ARE HIGH 0, 2, 4, 6, 8 1, 3, 5, 7, 9
H = HIGH Level, L = LOW Level

OUTPUTS EVEN H L ODD L H

SN54LSXXXJ SN74LSXXXN SN74LSXXXD

Ceramic Plastic SOIC

GUARANTEED OPERATING RANGES


Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 0.4 4.0 8.0 Unit V C mA mA

FAST AND LS TTL DATA 5-1

SN54/74LS280
FUNCTIONAL BLOCK DIAGRAM
A (8) B (9) (5) EVEN

C (10)

D E F

(11) (12) (13) (6) ODD

G H

(1) (2)

I (4)

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)


Limits S b l Symbol VIH VIL VIK VOH P Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current 20 0.4 100 27 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 0.65 3.5 0.8 1.5 V V Min 2.0 0.7 V Typ Max U i Unit V T Test C Conditions di i Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input p LOW Voltage g for All Inputs VCC = MIN, IIN = 18 mA VCC = MIN, , IOH = MAX, , VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)


Limits S b l Symbol tPLH tPHL tPLH tPHL P Parameter Propagation Delay, Data to Output EVEN Propagation Delay, Data to Output ODD Min Typ 33 29 23 31 Max 50 45 35 50 U i Unit ns CL = 15 pF ns T Test C Conditions di i

FAST AND LS TTL DATA 5-2

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