Chapter 3 Data processing Circuit

Course Learning Outcomes, CLO

CLO 4:

explain correctly the application of data processing circuits in digital systems.

SUMMARY
DATA PROCESSING CIRCUITS
Encoder, Decoder, BCD to Seven Segment Display Decoder, Multiplexer Demultiplexer.
School of Electrical Engineering 3

Decoder

Decoder: a multiple input, multiple output logic circuit which converts coded input into coded output from n input line to a maximum of 2n unique output lines. activates an output that corresponds to a binary number on the input. Only one output is active for any given input

Decoder

The basic function is to detect the presence of a specified combination of bits (code) on its inputs and to indicate the presence of that code by a specified output level In other word, decoder circuit look at its inputs, determine which binary number present there, and activates the output that correspond to that numbers; all other outputs remain inactive Some decoder do not utilize the 2n possible input codes for example BCD to decimal decoder and Seven segment decoder

2-to-4 Decoder (Active HIGH)

a) Logic symbol c) Boolean expression d) Logic diagram

O0 = AB
O0 A B

2-to-4 Decoder

O1 O2 O3

O1 = AB O2 = AB O3 = AB

O0

O1 O2

b) Truth table

O3
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2-to-4 Decoder (Active LOW)

a) Logic symbol
A B 21 20 2 to 4 Decoder O0 B O1 O2 O3 A 21 20 2 to 4 Decoder O0 O1 O2 O3

O0

O1 O2 O3

b) Truth table

c) Boolean expression

O0 A B O1 AB O2 A B O3 AB
A B
d) Logic diagram

2-to-4 Decoder with active LOW enable input

a) Logic symbol b) Truth table

d) Logic diagram c) Boolean expression

D0 en AB , D2 enAB D1 en AB , D3 enAB
Enable input used to control the operation of the decoderActive mode is 0- active low
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The 74x139 Dual 2-to-4 Decoder

a) Logic symbol

Truth table for one-half of a 74x139 dual 2-to-4 decoder Inputs Outputs

G
1 0 0 0 0

B
X 0 0 1 1

A
X 0 1 0 1

Y3 Y2 Y1 Y0
1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1

b) Logic diagram
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3 to 8 Binary Decoder (active HIGH)

a) Logic symbol
F0 X Y Z F1 F2 F3 F4 F5 F6 F7

c) Logic diagram & Boolean Expression

F0 = x'y'z' F1 = x'y'z F2 = x'yz' F3 = x'yz F4 = xy'z'

3-to-8 Decoder

b) Truth table

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

z F0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0

F1 0 1 0 0 0 0 0 0

F2 0 0 1 0 0 0 0 0

F3 0 0 0 1 0 0 0 0

F4 0 0 0 0 1 0 0 0

F5 0 0 0 0 0 1 0 0

F6 0 0 0 0 0 0 1 0

F7 0 0 0 0 0 0 0 1

F5 = xy'z F6 = xyz'

F7 = xyz

z
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The 74x138 3-to-8 Decoder

a) Logic symbol

(b) Logic diagram.

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The 74x138 3-to-8 Decoder

(c) Function table

(b) Block Diagram

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The 74x138 3-to-8 Decoder

It has three enable inputs, G1, G2A, G2B , all of which must be asserted for the selected output to be asserted.

The equation for the output signal Y5:

Y 5 G1G 2 AG 2 BC B A
Active-low

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Exercise

Design a decoder listing below a) BCD to decimal decoder b) 4 to 16 decoder

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Seven Segment Display

Used for displaying information in a form that can be understood by user or operator. Information can be in alphanumeric (numbers and letters). Seven segment configuration which its arrangement uses LED for each segment. two ways of arrangement common anode and common cathode. Each arrangement needs different driver/ decoder to drive each segment of seven segment display.

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BCD-to-7 Segment Decoder / Driver

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FILL IN THE TRUTH FOR ACTIVE LOW BCD TO 7 SEGMENT DECODER

A
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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Decoder applications

Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n decoder (active HIGH) with m OR gates to generate a minterms OR gate forms the sum The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate Suitable when a circuit has many outputs, and each output function is expressed with few minterms. It can also use AND gates and n-to-2n decoder to generate a Maxterm function.

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Decoder applications (full adder)

a) Truth table b) Minterm Expression

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

z 0 1 0 1 0 1 0 1

C S 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1

Example: Full adder S(x, y, z) = S (1,2,4,7) C(x, y, z) = S (3,5,6,7)

3-to-8 0 Decoder 1

x
y z

S2

S1
S0

2 3 4 5 6 7

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Decoder applications example

f1(x2,x1,x0) = M(0,1,3,5) and f2(x2,x1,x0) = M(1,3,6,7) (a) Using output or-gates. (b) Using output nor-gates.

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Decoder applications example

Application Example

f1(x2,x1,x0) = Sm(0,2,6,7) and f2(x2,x1,x0) = Sm(3,5,6,7) (a) Using output and-gates. (b) Using output nand-gates.

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Encoder

An encoder is a combinational logic circuit that essentially performs a reverse of decoder function Number of input lines is larger than output lines Decoder VS Encoder

Decoder

Encoder

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Encoder

Only one of input lines is activated at a given time and produces an N-bit output code depending on which input is active. For example octal to binary encoder: if input 4 is active, the output code should be 100 with 1 is MSB bit.

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Octal to Binary Encoder

a) Logic Symbol b) Truth table

Inputs
I0 I1 I2 I3 I4 I5 I6 I7

Outputs
4

I
22 21 20

I 0 1 0 0 0 0 0 0

I 0 0 1 0 0 0 0 0

I 0 0 0 1 0 0 0 0

I 0 0 0 0 1 0 0 0

I 0 0 0 0 0 1 0 0

I 0 0 0 0 0 0 1 0

I 0 0 0 0 0 0 0 1

y2 y1 y0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

1 0 0 0 0 0 0 0

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Octal to Binary Encoder

d) Logic diagram c) Boolean Expression

I0 I1 I2 I3 I4 y 2 = I4 + I 5 + I6 + I7

I5
I6 I7

y1 = I2 + I3 + I6 + I7

y 0 = I1 + I 3 + I5 + I7

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Decimal to BCD Priority Encoder

The priority function means that the encoder will produce a BCD output corresponding to the highest-order decimal digit input that is active and will ignore any other actives input

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Multiplexer

A multiplexer is a device that allows digitals information from several sources to be routed onto a single line for transmission over that line to a common destination The basic multiplexer has several data-input line and a single output line has data select inputs, which permit digital data on any one of the inputs to be switched to the output line also known as data selector

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Multiplexer

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2 - to - 1 Multiplexer
a) Logic Symbol d) Logic Circuit
I0 2 input z Mux I1 s

b) Truth Table

c) Boolean Expression

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4 - to - 1 Multiplexer
a) Logic Symbol d) Logic diagram

I0 I1 4 input z I2 Mux I3
S1 S0

b) Truth Table

c) Boolean Expression

z S1 S0 I 0 S1S0 I1 S1 S0 I 2 S1S0 I 3
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The 74ALS151 8 inputs Multiplexer

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Multiplexer Application

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Logic design using Mux

Example - 3 variable function using 8-to1 line Multiplexer

Case1- number of input is equal to number of select lines Design procedure Connect inputs to selected lines Identify the decimal number corresponding to each minterm in the expression Connect logic 1 level to input lines corresponding to these numbers Connect logic 0 level to the others

f(x,y,z) = Sm(0,2,3,5)
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Logic design using Mux

Case

2: Number of inputs is higher than number of select lines Design procedure

Reduce

the number of inputs to the number of select lines by inspection k-map

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Logic design using Mux

Example implement f(x,y,z) = Sm(0,2,3,5) using 4 input mux
a) k-map b) Boolean Exp c) implementation

S1S0

xy

0 1 0 0 0

1 0 1 0 1

I0 00 I1 01 I3 11 I2 10

I0 z I1 I 3 z I2 0

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Logic design using Mux (Exercise)

Realize the f(a,b,c,d) = Sm(0,2,3,5,8,9,11,12,14,15) Using a)8 input Mux b)4 input Mux

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Demultiplexer (Demux)

Basically reverses the multiplexing function Takes data from one line and distributes them to a given numbers of output lines. Demultiplexer also known as a data distributor. Decoders can also be used as a demultiplexers.

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Figure (a): 1-line-to-4-line demultiplexer

Figure (a) shows a 1-line-to-4-line demultiplexer circuit. The data input lines goes to all of the AND gates. The two data lines only one gate at a time, and the data appearing on the data-input line will pass through the selected gated to the associated data output line.
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Example: The serial data input waveform (data in) and data selectors input (s0 and s1) are shown in figure (b). Determine the data output waveforms on D0 through D3 for the demultiplexer in figure (a).

Solution:

Figure (b)

Notice that the select lines go through a binary sequence so that each successive input bit is routed to D0, D1, D2 and D3 in sequence as shown by the output waveforms in figure (b).
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