1.

General description
The 74LVC08A provides four 2-input AND gates.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with J EDEC standard:
J ESD8-7A (1.65 V to 1.95 V)
J ESD8-5A (2.3 V to 2.7 V)
J ESD8-C/J ESD36 (2.7 V to 3.6 V)
ESD protection:
HBM J ESD22-A114F exceeds 2000 V
MM J ESD22-A115-B exceeds 200 V
CDM J ESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information

74LVC08A
Quad 2-input AND gate
Rev. 6 16 December 2011 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC08AD 40 C to +125 C SO14 plastic small outline package; 14leads;
body width 3.9 mm
SOT108-1
74LVC08ADB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LVC08APW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LVC08ABQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
SOT762-1
74LVC08A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 16 December 2011 2 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate
4. Functional diagram

5. Pinning information
5.1 Pinning

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one gate
mna222
1A
1B
1Y
2
1
3
2A
2B
2Y
5
4
6
3A
3B
3Y
10
9
8
4A
4B
4Y
13
12
11
mna223
3
&
&
&
&
2
1
6
5
4
8
10
9
11
13
12
mna221
A
B
Y
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There
is no electrical or mechanical requirement to solder
this pad. However, if it is soldered, the solder land
should remain floating or be connected to GND.
Fig 4. Pin configuration SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14
74LVC08A
1A V
CC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y
001aac945
1
2
3
4
5
6
7 8
10
9
12
11
14
13
001aac946
74LVC08A
GND
(1)
Transparent top view
2Y 3A
2B 3B
2A 4Y
1Y 4A
1B 4B
G
N
D
3
Y
1
A
V
C
C
6 9
5 10
4 11
3 12
2 13
78
1
1
4
terminal 1
index area
74LVC08A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 16 December 2011 3 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate
5.2 Pin description

6. Functional description

[1] H =HIGH voltage level; L =LOW voltage level; X =dont care
7. Limiting values

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO14 packages: above 70 C derate linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.
Table 2. Pin description
Symbol Pin Description
1A to 4A 1, 4, 9, 12 data output
1B to 4B 2, 5, 10, 13 data input
1Y to 4Y 3, 6, 8,11 data input
GND 7 ground (0 V)
V
CC
14 supply voltage
Table 3. Function selection
[1]
Input Output
nA nB nY
L X L
X L L
H H H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +6.5 V
I
IK
input clamping current V
I
<0 V 50 - mA
V
I
input voltage
[1]
0.5 +6.5 V
I
OK
output clamping current V
O
>V
CC
or V
O
<0 V - 50 mA
V
O
output voltage output HIGH or LOW-state
[2]
0.5 V
CC
+0.5 V
I
O
output current V
O
=0 V to V
CC
- 50 mA
I
CC
supply current - 100 mA
I
GND
ground current 100 - mA
P
tot
total power dissipation T
amb
= 40 C to +125 C
[3]
- 500 mW
T
stg
storage temperature 65 +150 C
74LVC08A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 16 December 2011 4 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate
8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage 1.65 - 3.6 V
functional 1.2 - - V
V
I
input voltage 0 - 5.5 V
V
O
output voltage output HIGH or LOW-state 0 - V
CC
V
T
amb
ambient temperature 40 - +125 C
At/AV input transition rise and fall rate V
CC
=1.65 V to 2.7 V 0 - 20 ns/V
V
CC
=2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
V
IH
HIGH-level
input voltage
V
CC
=1.2 V 1.08 - - 1.08 - V
V
CC
=1.65 V to 1.95 V 0.65 V
CC
- - 0.65 V
CC
- V
V
CC
=2.3 V to 2.7 V 1.7 - - 1.7 - V
V
CC
=2.7 V to 3.6 V 2.0 - - 2.0 - V
V
IL
LOW-level
input voltage
V
CC
=1.2 V - - 0.12 - 0.12 V
V
CC
=1.65 V to 1.95 V - - 0.35 V
CC
- 0.35 V
CC
V
V
CC
=2.3 V to 2.7 V - - 0.7 - 0.7 V
V
CC
=2.7 V to 3.6 V - - 0.8 - 0.8 V
V
OH
HIGH-level
output
voltage
V
I
=V
IH
or V
IL
I
O
=100 A;
V
CC
=1.65 V to 3.6 V
V
CC
0.2 - - V
CC
0.3 - V
I
O
=4 mA; V
CC
=1.65 V 1.2 - - 1.05 - V
I
O
=8 mA; V
CC
=2.3 V 1.8 - - 1.65 - V
I
O
=12 mA; V
CC
=2.7 V 2.2 - - 2.05 - V
I
O
=18 mA; V
CC
=3.0 V 2.4 - - 2.25 - V
I
O
=24 mA; V
CC
=3.0 V 2.2 - - 2.0 - V
V
OL
LOW-level
output
voltage
V
I
=V
IH
or V
IL
I
O
=100 A;
V
CC
=1.65 V to 3.6 V
- - 0.2 - 0.3 V
I
O
=4 mA; V
CC
=1.65 V - - 0.45 - 0.65 V
I
O
=8 mA; V
CC
=2.3V - - 0.6 - 0.8 V
I
O
=12 mA; V
CC
=2.7 V - - 0.4 - 0.6 V
I
O
=24 mA; V
CC
=3.0 V - - 0.55 - 0.8 V
I
I
input leakage
current
V
CC
=3.6 V; V
I
=5.5 Vor GND - 0.1 5 - 20 A
74LVC08A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 16 December 2011 5 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate
[1] All typical values are measured at V
CC
=3.3 V (unless stated otherwise) and T
amb
=25 C.
10. Dynamic characteristics

[1] Typical values are measured at T
amb
=25 C and V
CC
=1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N +E(C
L
V
CC
2
f
o
) where:
f
i
=input frequency in MHz, f
o
=output frequency in MHz
C
L
=output load capacitance in pF
V
CC
=supply voltage in Volts
N = number of inputs switching
E(C
L
V
CC
2
f
o
) =sum of the outputs.
I
CC
supply
current
V
CC
=3.6 V; V
I
=V
CC
or GND;
I
O
=0 A
- 0.1 10 - 40 A
AI
CC
additional
supply
current
per input pin;
V
CC
=2.7 V to 3.6 V;
V
I
=V
CC
0.6 V; I
O
=0 A
- 5 500 - 5000 A
C
I
input
capacitance
V
CC
=0 V to 3.6 V;
V
I
=GNDto V
CC
- 4.0 - - - pF
Table 6. Static characteristics continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation delay nA, nB to nY; see Figure 6
[2]
V
CC
=1.2 V - 11.0 - - - ns
V
CC
=1.65 V to 1.95 V 0.5 4.2 9.0 0.5 10.4 ns
V
CC
=2.3 V to 2.7 V 1.0 2.5 6.9 1.0 8.0 ns
V
CC
=2.7 V 1.5 2.5 4.8 1.5 5.6 ns
V
CC
=3.0 V to 3.6 V 1.0 2.3 4.1 1.0 4.8 ns
t
sk(o)
output skew time V
CC
=3.0 V to 3.6 V
[3]
- - 1.0 - 1.5 ns
C
PD
power dissipation
capacitance
per gate; V
I
=GNDto V
CC
[4]
V
CC
=1.65 V to 1.95 V - 4.4 - pF
V
CC
=2.3 V to 2.7 V - 7.7 - - - pF
V
CC
=3.0 V to 3.6 V - 10.5 - - - pF
74LVC08A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 16 December 2011 6 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate
11. AC waveforms



V
M
=1.5 V at V
CC
> 2.7 V
V
M
=0.5 V
CC
at V
CC
<2.7 V
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 6. The input nA, nB to output nY propagation delays
mna224
nA, nB input
nY output
t
PLH
t
PHL
GND
V
I
V
M
V
M
V
OH
V
OL
Test data is given in Table 8. Definitions for test circuit:
R
L
=Load resistance
C
L
=Load capacitance including jig and probe capacitance
R
T
=Termination resistance should be equal to output impedance Z
o
of the pulse generator
Fig 7. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aaf615
V
CC
V
I
V
O
DUT
C
L
R
T
R
L
PULSE
GENERATOR
74LVC08A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 16 December 2011 7 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate
Table 8. Test data
Supply voltage Input Load
V
I
t
r
, t
f
C
L
R
L
1.2 V V
CC
s 2 ns 30 pF 1 kO
1.65 V to 1.95 V V
CC
s 2 ns 30 pF 1 kO
2.3 V to 2.7 V V
CC
s 2 ns 30 pF 500 O
2.7 V 2.7 V s 2.5 ns 50 pF 500 O
3.0 V to 3.6 V 2.7 V s 2.5 ns 50 pF 500 O
74LVC08A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 16 December 2011 8 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate
12. Package outline

Fig 8. Package outline SOT108-1 (SO14)
UNIT
A
max.
A
1
A
2
A
3
b
p
c D
(1)
E
(1) (1)
e H
E
L L
p
Q Z y w v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
w M

A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M A
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.35
0.34
0.16
0.15
0.05
1.05
0.041
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74LVC08A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 16 December 2011 9 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate

Fig 9. Package outline SOT337-1 (SSOP14)
UNIT A
1
A
2
A
3
b
p
c D
(1)
E
(1)
e H
E
L L
p
Q Z y w v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65 1.25 0.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1
99-12-27
03-02-19
(1)
w M
b
p
D
H
E
E
Z
e
c
v M A
X
A
y
1 7
14 8

A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
A
max.
2
74LVC08A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 16 December 2011 10 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate

Fig 10. Package outline SOT402-1 (TSSOP14)
UNIT A
1
A
2
A
3
b
p
c D
(1)
E
(2) (1)
e H
E
L L
p
Q Z y w v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.72
0.38
8
0
o
o
0.13 0.1 0.2 1
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153
99-12-27
03-02-18
w M
b
p
D
Z
e
0.25
1 7
14 8

A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M A
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
74LVC08A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 16 December 2011 11 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate

Fig 11. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.5 1
A
1
E
h
b UNIT y e
0.2
c
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
3.1
2.9
D
h
1.65
1.35
y
1
2.6
2.4
1.15
0.85
e
1
2
0.30
0.18
0.05
0.00
0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - - - - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A
(1)
max.
A
A
1
c
detail X
y y
1 C e
L
E
h
D
h
e
e
1
b
2 6
13 9
8
7 1
14
X
D
E
C
B A
02-10-17
03-01-27
terminal 1
index area
A C
C
B v M
w M
E
(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D
(1)
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Product data sheet Rev. 6 16 December 2011 12 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate
13. Abbreviations

14. Revision history

Table 9. Abbreviations
Acronym Description
CDM Charged Device Model
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC08A v.6 20111216 Product data sheet 74LVC08A v.5
Modifications: The format of this document has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges.
74LVC08A v.5 20030224 Product specification - 74LVC08A v.4
74LVC08A v.4 20021030 Product specification - 74LVC08A v.3
74LVC08A v.3 20020308 Product specification - 74LVC08A v.2
74LVC08A v.2 19970630 Product specification - 74LVC08A v.1
74LVC08A v.1 19970630 Product specification - -
74LVC08A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 16 December 2011 13 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate
15. Legal information
15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term short data sheet is explained in section Definitions.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customers own risk.
Applications Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customers sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customers applications and
products planned, as well as for the planned application and use of
customers third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customers applications or products, or the application or use by customers
third party customer(s). Customer is responsible for doing all necessary
testing for the customers applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customers third party
customer(s). NXP does not accept any liability in this respect.
Limiting values Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customers general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
74LVC08A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 16 December 2011 14 of 15
NXP Semiconductors 74LVC08A
Quad 2-input AND gate
Non-automotive qualified products Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors specifications such use shall be solely at customers
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors
standard warranty and NXP Semiconductors product specifications.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors 74LVC08A
Quad 2-input AND gate
NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 16 December 2011
Document identifier: 74LVC08A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics . . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16 Contact information. . . . . . . . . . . . . . . . . . . . . 14
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15