74AHC08 74AHCT08: 1. General Description
74AHC08 74AHCT08: 1. General Description
74AHC08 74AHCT08: 1. General Description
1. General description
The 74AHC08; 74AHCT08 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard JESD7-A.
2. Features
■ Balanced propagation delays
■ All inputs have a Schmitt-trigger action
■ Inputs accepts voltages higher than VCC
■ For 74AHC08 only: operates with CMOS input levels
■ For 74AHCT08 only: operates with TTL input levels
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC08D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; SOT108-1
74AHCT08D body width 3.9 mm
74AHC08PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1
74AHCT08PW body width 4.4 mm
74AHC08BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1
74AHCT08BQ thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
NXP Semiconductors 74AHC08; 74AHCT08
Quad 2-input AND gate
4. Functional diagram
1
& 3
2
1 1A
1Y 3
2 1B 4
& 6
4 2A
2Y 6 5
5 2B A
9 3A Y
3Y 8 9
10 3B & 8
10 B
12 4A mna221
4Y 11
13 4B
12
& 11
mna222
13
mna223
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
5. Pinning information
5.1 Pinning
14 VCC
terminal 1
1A
1B 2 13 4B 1B 2 13 4B
1Y 3 12 4A 1Y 3 12 4A
2A 4 08 11 4Y
2A 4 08 11 4Y
2B 5 GND(1) 10 3B
2B 5 10 3B
2Y 6 9 3A
7
2Y 6 9 3A
GND
3Y
GND 7 8 3Y 001aac946
6. Functional description
Table 3. Function selection[1]
Input Output
nA nB nY
L X L
X L L
H H H
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7.0 V
VI input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V [1] −20 - mA
IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] - ±20 mA
IO output current VO = −0.5 V to (VCC + 0.5 V) - ±25 mA
ICC supply current - 75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 °C.
[3] Ptot derates linearly with 5.5 mW/K above 60 °C.
[4] Ptot derates linearly with 4.5 mW/K above 60 °C.
9. Static characteristics
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
For type 74AHC08
VIH HIGH-level VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
input voltage VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
input voltage VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level VI = VIH or VIL
output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.4 - V
IO = −8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.7 - V
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
11. Waveforms
VI
nA, nB input VM
GND
t PHL t PLH
VOH
nY output VM
VOL
mna224
tW
VI
90 %
negative
pulse VM VM
10 %
0V
tf tr
tr tf
VI
90 %
positive
pulse VM VM
10 %
0V
tW
VCC VCC
VI VO RL S1
PULSE
DUT open
GENERATOR
RT CL
001aad983
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
D E A
X
y HE v M A
14 8
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 7 L
e w M detail X
bp
0 2.5 5 mm
scale
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
99-12-27
SOT108-1 076E06 MS-012
03-02-19
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
D E A
X
y HE v M A
14 8
Q
A2 (A 3)
A
A1
pin 1 index
θ
Lp
L
1 7
detail X
w M
e bp
0 2.5 5 mm
scale
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
99-12-27
SOT402-1 MO-153
03-02-18
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1
D B A
A
A1
E c
terminal 1 detail X
index area
terminal 1 e1 C
index area
e b v M C A B y1 C y
w M C
2 6
1 7
Eh e
14 8
13 9
Dh
X
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
A(1)
UNIT
max.
A1 b c D (1) Dh E (1) Eh e e1 L v w y y1
13. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
LSTTL Low-power Schottky Transistor-Transistor Logic
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
CDM Charged Device Model
TTL Transistor-Transistor Logic
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16 Contact information. . . . . . . . . . . . . . . . . . . . . 13
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.