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Sync Async Reset

Synchronous resets sample the reset signal only on the clock edge, treating reset like other inputs to the state machine, while asynchronous resets have priority over all other signals and can occur with or without a clock. Synchronous resets make the circuit completely synchronous but require a clock and may need pulse stretching or buffer pipelining, while asynchronous resets do not need a clock but the reset line is sensitive to glitches and the reset deassertion must occur within a clock cycle for all flip-flops. Both reset methods require careful routing of the large reset tree due to the capacitive load of resetting all flip-flops.

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38 views6 pages

Sync Async Reset

Synchronous resets sample the reset signal only on the clock edge, treating reset like other inputs to the state machine, while asynchronous resets have priority over all other signals and can occur with or without a clock. Synchronous resets make the circuit completely synchronous but require a clock and may need pulse stretching or buffer pipelining, while asynchronous resets do not need a clock but the reset line is sensitive to glitches and the reset deassertion must occur within a clock cycle for all flip-flops. Both reset methods require careful routing of the large reset tree due to the capacitive load of resetting all flip-flops.

Uploaded by

brk_318
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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Asynchronous versus Synchronous Resets

Reset is needed for:

forcing the ASIC into a sane state for simulation

initializing hardware, as circuits have no way to self-initialize

Reset is usually applied at the beginning of time for simulation

Reset is usually applied at power-up for real hardware

Reset may be applied during operation by watchdog circuits


Synchronous Resets

Reset is sampled only on the clock edge

Reset applied as any other input to the state machine


Synchronous Resets

Sync reset advantages

The ip-op is less complex, thus smaller in area

Circuit is completely synchronous

Synchronous resets provide ltering for the reset line

Sync reset disadvantages

Combinatorial logic grows and may cancel out the benet

Reset buer tree may have to be pipelined to keep all resets occurring
within the same clock cycle

May need to pulse stretch reset so its is wide enough to be seen at a


clock rising edge

Requires a clock to be present if reset is to occur

If internal tri-state buers are present, separate asynchronous reset


may still be required

Reset signal may take the fastest path to ip-ops


Asynchronous Resets

Asynchronous reset advantages

Reset has priority over any other signal

Reset occurs with or without clock present

Data paths are always clear of reset signals

No coercion of synthesis tool needed for correct synthesis

Asynchronous reset disadvantages

Reset deassertion to all ip-ops must occur in less than a clock cycle.

Reset line is sensitive to glitches at any time


Asynchronous Resets

Asynchronous reset synchronization circuit

Synchronization circuit required with asynchronous reset

Circuit will provide asynchronous reset and synchronous deassertion


Asynchronous Resets

Reset tree

Routing and buering of the reset tree almost as critical as the clock
tree

Reset goes to every ip-op, possibly 100s of thousands

Capacitive load is very large

Reset deassertion must happen within 1 clock cycle and allow time
for reset recovery time

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