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    Asynchronous Vs Synchronous Reset VLSI Interview Topics 1674364028 PDF

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    Aathith Saiprasad
    This document discusses asynchronous and synchronous resets. Asynchronous resets have priority over other signals and occur with or without a clock, but reset deassertion must occur within a clock cycle. Synchronous resets are sampled only on clock edges and make the circuit completely synchronous. Asynchronous resets are preferred for ASICs while synchronous resets have smaller area but more complex logic. Resets are needed to initialize hardware but FPGAs initialize during configuration while ASICs require explicit resets.

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    Asynchronous Vs Synchronous Reset VLSI Interview Topics 1674364028 PDF

    Uploaded by

    Aathith Saiprasad
    92 views9 pages
    This document discusses asynchronous and synchronous resets. Asynchronous resets have priority over other signals and occur with or without a clock, but reset deassertion must occur within a clock cycle. Synchronous resets are sampled only on clock edges and make the circuit completely synchronous. Asynchronous resets are preferred for ASICs while synchronous resets have smaller area but more complex logic. Resets are needed to initialize hardware but FPGAs initialize during configuration while ASICs require explicit resets.

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    This document discusses asynchronous and synchronous resets. Asynchronous resets have priority over other signals and occur with or without a clock, but reset deassertion must occur within a clock cycle. Synchronous resets are sampled only on clock edges and make the circuit completely synchronous. Asynchronous resets are preferred for ASICs while synchronous resets have smaller area but more complex logic. Resets are needed to initialize hardware but FPGAs initialize during configuration while ASICs require explicit resets.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    92 views9 pages

    Asynchronous Vs Synchronous Reset VLSI Interview Topics 1674364028 PDF

    Uploaded by

    Aathith Saiprasad
    This document discusses asynchronous and synchronous resets. Asynchronous resets have priority over other signals and occur with or without a clock, but reset deassertion must occur within a clock cycle. Synchronous resets are sampled only on clock edges and make the circuit completely synchronous. Asynchronous resets are preferred for ASICs while synchronous resets have smaller area but more complex logic. Resets are needed to initialize hardware but FPGAs initialize during configuration while ASICs require explicit resets.

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    Asynchronous versus Synchronous Resets

    I Reset is needed for:


    I forcing the ASIC into a sane state for simulation
    I initializing hardware, as circuits have no way to self-initialize
    I Reset is usually applied at the beginning of time for simulation
    I Reset is usually applied at power-up for real hardware
    I Reset may be applied during operation by watchdog circuits
    Synchronous Resets

    I Reset is sampled only on the clock edge


    I Reset applied as any other input to the state machine
    Synchronous Resets

    I Sync reset advantages


    I The flip-flop is less complex, thus smaller in area
    I Circuit is completely synchronous
    I Synchronous resets provide filtering for the reset line

    I Sync reset disadvantages


    I Combinatorial logic grows and may cancel out the benefit
    I Reset buffer tree may have to be pipelined to keep all resets occurring
    within the same clock cycle
    I May need to pulse stretch reset so its is wide enough to be seen at a
    clock rising edge
    I Requires a clock to be present if reset is to occur
    I If internal tri-state buffers are present, separate asynchronous reset
    may still be required
    I Reset signal may take the fastest path to flip-flops

    www.vlsiforall.com
    Asynchronous Resets
    I Asynchronous reset advantages
    I Reset has priority over any other signal
    I Reset occurs with or without clock present
    I Data paths are always clear of reset signals
    I No coercion of synthesis tool needed for correct synthesis
    I Asynchronous reset disadvantages
    I Reset deassertion to all flip-flops must occur in less than a clock cycle.
    I Reset line is sensitive to glitches at any time

    www.vlsiforall.com
    Asynchronous Resets

    I Asynchronous reset synchronization circuit


    I Synchronization circuit required with asynchronous reset
    I Circuit will provide asynchronous reset and synchronous deassertion

    Whatsapp Us :
    9643070368
    Asynchronous Resets
    I Reset tree
    VLSI FOR ALL
    I Routing and buffering of the reset tree almost as critical as the clock
    tree
    I Reset goes to every flip-flop, possibly 100’s of thousands
    I Capacitive load is very large
    I Reset deassertion must happen within 1 clock cycle and allow time
    for reset recovery time
    Resetting FPGAs

    I FPGAs are initialized during configuration: all FFs, and memory


    I ASICs must have an explicit reset to achieve initialization
    I What happens here in both environments?
    %lecture_verilog/beamer/example_code/init_ffs.sv
    module init_ffs (
    input clk,
    output q_out_b,
    input d_in
    );
    logic q_out = ’0; //initalize flip flop
    always_ff @ (posedge clk)
    q_out <= d_in;
    assign q_out_b = q_out; //assign output
    endmodule

    I FPGA: FFs are initialized in hardware and simulation


    I Hardware FFs get initialized by configuration
    I Initialization statement resets simulation FFs
    www.vlsiforall.com
    Resetting FPGAs

    I What happens here in both environments? (cont.)


    module init_ffs (
    input clk,
    output q_out_b,
    input d_in
    );
    logic q_out = ’0; //initalize flip flop
    always_ff @ (posedge clk)
    q_out <= d_in;
    assign q_out_b = q_out; //assign output
    endmodule

    I ASIC: Synopsis design compiler says:


    Warning: init_ffs.sv:8: The ’declaration initial assignment’
    construct is not supported. It will be ignored. (VER-104)
    Resetting FPGAs

    I Places for providing explicit reset


    I High availability application requiring hot reset
    I If clock drops out, need hard reset after PLL gets lock
    I Comm channel: if it drops out, how do you reset the hardware?
    I User push button reset
    I Partial configuration will require reset of new logic
    I IP (esp from ASIC sources) may require it
    I Migration to ASIC from FPGA
    I Reset not needed for some logic (pipelines)
    I Reset is always needed for any logic with feedback

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