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Vlsi Cad Laboratory: Layout and Characterization of NAND Gate

This document outlines a project to design and characterize a 3-input NAND gate using Tanner Tools CAD software. The tasks involve drawing the circuit schematics for the gate using S-Edit, simulating it to verify functionality, creating the transistor layout while following design rules, performing design rule and layout versus schematic checks, extracting the layout and simulating it with a load capacitance to characterize the gate's delay characteristics including rise time, fall time, and propagation delays. The goal is for students to gain experience with VLSI design from schematic capture to transistor layout and characterization of timing performance.

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AhmadSyazwan
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26 views2 pages

Vlsi Cad Laboratory: Layout and Characterization of NAND Gate

This document outlines a project to design and characterize a 3-input NAND gate using Tanner Tools CAD software. The tasks involve drawing the circuit schematics for the gate using S-Edit, simulating it to verify functionality, creating the transistor layout while following design rules, performing design rule and layout versus schematic checks, extracting the layout and simulating it with a load capacitance to characterize the gate's delay characteristics including rise time, fall time, and propagation delays. The goal is for students to gain experience with VLSI design from schematic capture to transistor layout and characterization of timing performance.

Uploaded by

AhmadSyazwan
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
Download as doc, pdf, or txt
Download as doc, pdf, or txt
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Fakulti:

FAKULTI KEJURUTERAAN ELEKTRIK


Semakan
Tarikh Keluaran
Pindaan Terakhir
No. Prosedur

Nama Matapelajaran :
Kod Matapelajaran :

:1
: 2003
: 2003
: PK-UTM-FKE-(0)-10

SEE 4722
FAKULTI KEJURUTERAAN ELEKTRIK
UNIVERSITI TEKNOLOGI MALAYSIA
KAMPUS SKUDAI
JOHOR

VLSI CAD LABORATORY


Layout and characterization of NAND gate

Disediakan oleh
Nama
Tandatangan
Cop

:
: Nasir Shaikh Husin
:
:

Disahkan oleh
Nama
Tandatangan
Cop

: Ketua Jabatan
: PM Dr. Ahmad Zuri Shaameri
:
:

Tarikh

: Julai 2007

Tarikh

Project Introduction:
VLSI design involves drawing of transistor layout. Knowledge on how to design transistor layout is
very crucial for VLSI designers. In this project, you are required to do layout of a simple gate. You
must also characterize your layout by providing delay characteristics through simulation. You are
required to use Tanner Tools CAD software in this project.
Project tasks:
Design a 3-input NAND gate. Draw circuit schematics and layout for your logic gate. Choose transistor
sizes to conform to TSMC 0.25 m fabrication process. Make sure your layout is free from any design
rule violations and the layout represents the circuit schematic correctly. Then, get accurate rise time,
fall time, and propagation delays by extracting parasitic capacitances from the layout and simulating
the gate with T-Spice.
Tasks that you must do:
Draw the circuit schematics for the gate using S-Edit. Specify your transistor dimension.
Simulate the gate and verify correct functionality. Test all possible inputs.
Create layout for the gate. You must follow SCN5M_SUBM design rules.
Perform a Design Rules Check (DRC) on the layout.
Perform a Layout Versus Schematic (LVS) on the layout.
Extract your layout and simulate the netlist to verify correct functionality. Ensure all possible input
combinations are accounted for.
Repeat the simulation but this time by adding a reasonable load capacitance at the output.
Characterize your gate in terms of rise time, fall time, t pHL and tpLH propagation delays, and power
dissipation.

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