COURSE: ELECTRONICS AND COMMUNICATION ENGINEERING

SUBJECT CODE:4040531
QP CODE:517
4040531-VERY LARGE SCALE INTEGRATION-ANSWER KEY
PART-A
1.Draw the OR gate using CMOS?

2. Define Routing. Mention its types.

Routing in VLSI is making physical connections between signal pins using metal layers. Following
Clock Tree Synthesis (CTS) and optimization, the routing step determines the exact pathways
for interconnecting standard cells, macros, and I/O pin
Types of Routing
Clock nets and Power/Ground nets.
3.Write the syntax for IF statement.
If (x<10) then
a:=b;
End if;
4.Write the syntax for variable declaration statement.
Variable VARIABLE_Name : VARIABLE_TYPE(;=VALUE);
5.Draw the block diagram and truth table for 1 to 4 demultiplexer.
 TRUTH TABLE

6.Draw the circuit diagram and truth table for full adder.

7.Draw the diagram for 3-bit up counter.

8.Draw the diagram for Johnson counter.

9.Write short notes on PLA.

• The PLA is much more versatile than the PROM or the PAL,since both its AND gate
array and its OR-gate array are fusible-linked and thus programmable.
• It is also more complicated to utilize since the number of fusible links is doubled.
10.What is ASIC?

• An application specific integrated circuit(ASIC) is an integrated circuit customized for a

particular use.
• ASICs are non-standard integrated circuits constructed for one specific purpose only.
• The overall design of ASIC can be made into one integrated circuit and the number of
additional circuits can be reduced.

PART-B
11.(a) Draw the NOT gate using CMOS and explain.
The input is connected to the gate terminal of the two transistors, and the output is
connected to both drain terminals. Applying +V (logic 1) to the input (Vi), transistor Q2 is
“on,” and transistor Q1 remains “off.” Under this condition, the output voltage (Vo) is
close to 0 V (logic 0).
(b) Explain the steps involved in VLSI design process.

VLSI Design Flow

VLSI design Flow

The VLSI design cycle starts with a formal specification of a VLSI chip, follows a series of steps,
and eventually produces a packaged chip. A typical design cycle may be represented by the flow
chart shown in Figure. Our emphasis is on the physical design step of the VLSI design cycle.
However, to gain a global perspective, we briefly outline all the steps of the VLSI design cycle.

1.System Specification:

• The first step of any design process is to lay down the specifications of the system. System
specification is a high level representation of the system. The factors to be considered in this
process include: performance, functionality, and physical dimensions (size of the die (chip)). The
fabrication technology and design techniques are also considered.
• The specification of a system is a compromise between market requirements, technology
and economical viability. The end results are specifications for the size, speed, power, and
functionality of the VLSI system.
.

Architectural Design:

• The basic architecture of the system is designed in this step. This includes, such decisions
as RISC (Reduced Instruction Set Computer) versus CISC (Complex Instruction Set Computer),
number of ALUs, Floating Point units, number and structure of pipelines, and size of caches
among others.
• The outcome of architectural design is a Micro-Architectural Specification (MAS). While
MAS is a textual (English like) description, architects can accurately predict the performance,
power and die size of the design based on such a description.

3. Behavioral or Functional Design:

• In this step, main functional units of the system are identified. This also identifies the
interconnect requirements between the units. The area, power, and other parameters of each
unit are estimated.
• The behavioral aspects of the system are considered without implementation specific
information. For example, it may specify that a multiplication is required, but exactly in which
mode such multiplication may be executed is not specified. We may use a variety of
multiplication hardware depending on the speed and word size requirements. The key idea is to
specify behavior, in terms of input, output and timing of each unit, without specifying its internal
structure.
• The outcome of functional design is usually a timing diagram or other relationships
between units. This information leads to improvement of the overall design process and
reduction of the complexity of subsequent phases. Functional or behavioral design provides quick
emulation of the system and allows fast debugging of the full system. Behavioral design is largely
a manual step with little or no automation help available.
. Logic Design:

• In this step the control flow, word widths, register allocation, arithmetic operations, and
logic operations of the design that represent the functional design are derived and tested.
• This description is called Register Transfer Level (RTL) description. RTL is expressed in a
Hardware Description Language (HDL), such as VHDL or Verilog. This description can be used in
simulation and verification. This description consists of Boolean expressions and timing
information. The Boolean expressions are minimized to achieve the smallest logic design which
conforms to the functional design. This logic design of the system is simulated and tested to verify
its correctness. In some special cases, logic design can be automated using high level
synthesis tools. These tools produce a RTL description from a behavioral description of the
design.

5. Circuit Design:

• The purpose of circuit design is to develop a circuit representation based on the logic
design. The Boolean expressions are converted into a circuit representation by taking into
consideration the speed and power requirements of the original design. Circuit Simulation is used
to verify the correctness and timing of each component.
• The circuit design is usually expressed in a detailed circuit diagram. This diagram shows
the circuit elements (cells, macros, gates, transistors) and interconnection between these
elements. This representation is also called a netlist. Tools used to manually enter such
description are called schematic capture tools. In many cases, a netlist can be created
automatically from logic (RTL) description by using logic synthesis tools.

6. Physical Design:
• In this step the circuit representation (or netlist) is converted into a geometric
representation. As stated earlier, this geometric representation of a circuit is called
a layout. Layout is created by converting each logic component (cells, macros, gates, transistors)
into a geometric representation (specific shapes in multiple layers), which perform the intended
logic function of the corresponding component. Connections between different components are
also expressed as geometric patterns typically lines in multiple layers.
• The exact details of the layout also depend on design rules, which are guidelines based
on the limitations of the fabrication process and the electrical properties of the fabrication
materials. Physical design is a very complex process and therefore it is usually broken down into
various sub-steps. Various verification and validation checks are performed on the layout during
physical design.
• In many cases, physical design can be completely or partially automated and layout can
be generated directly from netlist by Layout Synthesis tools. Layout synthesis tools, while fast, do
have an area and performance penalty, which limit their use to some designs. Manual layout,
while slow and manually intensive, does have better area and performance as compared to
synthesized layout. However this advantage may dissipate as larger and larger designs may
undermine human capability to comprehend and obtain globally optimized solutions.
Fabrication:
• After layout and verification, the design is ready for fabrication. Since layout data is
typically sent to fabrication on a tape, the event of release of data is called Tape
Out. Layout data is converted (or fractured) into photo-lithographic masks, one for each
layer. Masks identify spaces on the wafer, where certain materials need to be deposited,
diffused or even removed. Silicon crystals are grown and sliced to produce wafers.
Extremely small dimensions of VLSI devices require that the wafers be polished to near
perfection. The fabrication process consists of several steps involving deposition, and
diffusion of various materials on the wafer. During each step one mask is used. Several
dozen masks may be used to complete the fabrication process.
• A large wafer is 20 cm (8 inch) in diameter and can be used to produce hundreds of chips,
depending of the size of the chip. Before the chip is mass produced, a prototype is made
and tested. Industry is rapidly moving towards a 30 cm (12 inch) wafer allowing even more
chips per wafer leading to lower cost per chip.

8. Packaging, Testing and Debugging:

• Finally, the wafer is fabricated and diced into individual chips in a fabrication facility. Each
chip is then packaged and tested to ensure that it meets all the design specifications and
that it functions properly. Chips used in Printed Circuit Boards (PCBs) are packaged in Dual
In-line Package (DIP), Pin Grid Array (PGA), Ball Grid Array (BGA), and Quad Flat Package
(QFP). Chips used in Multi-Chip Modules (MCM) are not packaged, since MCMs use bare
or naked chips.

12.(a) Write a VHDL code for Logic gates NAND,XOR.

VHDL CODE FOR NAND GATE :
Library ieee ;
Use ieee.std_logic_1164 all ;
Entity nandGate is
Port (A, B : in std_logic ;
F : out std_logic) ;
end nand Gate
architecture func of nandGate is
begin
F < = A nand B ;
end func ;
VHDL CODE FOR XOR GATE :
Library ieee ;
Use ieee.std_logic_1164 all ;

entity XOR2 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end XOR2;

architecture Behavioral of XOR2 is

begin
process(A,B)
begin
if((A='0') and (B='1')) then
C<='1';
elsif((A='1') and (B='0')) then
C<='1';
else
C<='0';
end if;
end process;
end Behavioral;

(b)Write the syntax for ‘if elseif else’ statement.Explain with an example.

if <condition> then
elsif <condition> then
else
end if;

The elsif and else are optional, and elsif may be used multiple times. The <condition> can be a
boolean true or false, or it can be an expression which evaluates to true or false.
Example expression which is true if MyCounter is less than 10:

MyCounter < 10
entity T08_IfTb is
end entity;

architecture sim of T08_IfTb is

signal CountUp : integer := 0;

signal CountDown : integer := 10;

begin

process is
begin

CountUp <= CountUp + 1;

CountDown <= CountDown - 1;
wait for 10 ns;

end process;

process is
begin

if CountUp > CountDown then

report "CountUp is larger";
elsif CountUp < CountDown then
report "CountDown is larger";
else
report "They are equal";
end if;

wait on CountUp, CountDown;

end process;

end architecture;
The output to the simulator console when we press

13.(a)Write a VHDL program for half subtractor with diagram.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity half_sub is

port( A, B : in std_logic;

DIFF, Borrow : out std_logic);

end entity;

architecture dataflow of half_sub is

begin

DIFF <= A xor B;

Borrow <= (not A) and B;

end architecture;

(b)Write a VHDL program for four-bit arithmetic subtractor in structural model

4 Bit Subtractor Design using Structural Modeling Style.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity subtractor_4bit is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
borrow : out STD_LOGIC;
diff : out STD_LOGIC_VECTOR(3 downto 0)
);
end subtractor_4bit;
architecture subtractor_4bit_arc of subtractor_4bit is

Component fa is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC );
end component;

signal s : std_logic_vector (2 downto 0);

signal l : std_logic_vector (3 downto 0);

begin

l <= not b;

u0 : fa port map (a(0),l(0),'1',diff(0),s(0));

u1 : fa port map (a(1),l(1),s(0),diff(1),s(1));
u2 : fa port map (a(2),l(2),s(1),diff(2),s(2));
ue : fa port map (a(3),l(3),s(2),diff(3),borrow);

end subtractor_4bit_arc;

14.(a)Draw the block diagram, circuit diagram and truth table for JK flipflop and explain.
The JK flip flop work as a T-type toggle flip flop when both of its inputs are set to 1. The JK flip
flop is an improved clocked SR flip flop. But it still suffers from the "race" problem. This problem
occurs when the state of the output Q is changed before the clock input's timing pulse has time
to go "Off".
(b) Explain ring counter with diagram.
A ring counter is a type of counter composed of flip-flops connected into a shift register, with
the output of the last flip-flop fed to the input of the first, making a "circular" or "ring"
structure.
A ring counter is a type of counter composed of flip-flops connected into a shift register, with
the output of the last flip-flop fed to the input of the first, making a "circular" or "ring"
structure.
There are two types of ring counters:

• A straight ring counter, also known as a one-hot counter, connects the output of the last
shift register to the first shift register input and circulates a single one (or zero) bit around
the ring.
• A twisted ring counter, also called switch-tail ring counter, walking ring counter, Johnson
counter, or Möbius counter, connects the complement of the output of the last shift
register to the input of the first register and circulates a stream of ones followed by zeros
around the ring.
Four-bit ring-counter sequences

Straight ring counter Johnson counter

State Q0 Q1 Q2 Q3 State Q0 Q1 Q2 Q3

0 1 0 0 0 0 0 0 0 0

1 0 1 0 0 1 1 0 0 0

2 0 0 1 0 2 1 1 0 0

3 0 0 0 1 3 1 1 1 0

0 1 0 0 0 4 1 1 1 1

1 0 1 0 0 5 0 1 1 1

2 0 0 1 0 6 0 0 1 1

3 0 0 0 1 7 0 0 0 1

0 1 0 0 0 0 0 0 0 0
15.(a) Explain PAL with example.
PROGRAMMABLE ARRAY LOGIC (PAL) In a PLA both the AND and OR planes are programmable.
The programmable switches presented two difficulties for manufacturers of these devices; (i)
They were hard to fabricate correctly and (ii) they reduced the speed performance of circuits
implemented in PLAs. These drawbacks led to the development of a similar device in which the
AND plane is programmable, but the OR plane is fixed. Such a chip is known as a Programmable
Array Logic (PAL) device. Because they are simpler to manufacture, and thus less expensive
than PLAs, and offer better performance. PALs have become popular in practical applications
X1 X2 X3

An example of a PAL with three inputs, four product terms and two outputs is given in figure
5.9. The product terms P1 and P2 are hardwired to one OR gate, and P3 and P4 are hardwired
to the other OR gate. The PAL is shown programmed to realize the two logic functions f1 =
x1x2x3 + x1x2x3 and f2= x1x2 + x1x2x3. In comparison to the PLA in figure 5.3, the PAL offers
less flexibility The PLA allows up to four product terms per OR gate, whereas the OR gates in the
PAL have only two inputs. To compensate for the reduced flexibility, PALs are manufactured in
a range of sizes, with various numbers of inputs and outputs, and different numbers of inputs
to the OR gates. So far we have assumed that the OR gates in a PAL, as in a PLA, connect
directly to the output pins of the chip. In many PALs extra circuitry is added at the output of
each OR gate to provide additional flexibility. It is customary to use the term macro cell to refer
to the OR gate combined with the extra circuitry. An example for the flexibility that may be
provided in a macro cell is given in Figure 5.10. The symbol labeled flip-flop represents a
memory element. It stores the value produced by the OR gate output at a particular point in
time and can hold that value as indefinite. The flip-flop is controlled by the signal called clock.
When clock makes a transition from logic value 0 to 1, flip-flop stores the value at its D input at
that time and this value appears at the flip-flop’s Q output. Flip-flops are used for implementing
many types of logic circuits. Fig. No: 5.10 2-to-1 multiplexer

a 2-to-1 multiplexer selects as an output from the PAL either the ORgate output or the flip-flop
output. The multiplexer’s select line can be programmed to be either 0 or 1. Figure no. 5.8
shows another logic gate, called a tri-state buffer, connected between the multiplexer and the
PAL output. Finally, the multiplexer’s output is “feed back” to the AND plane in the PAL. This
feedback connection allows the logic function produced by the multiplexer to be used internally
in the PAL. This allows the implementation of circuits that have multiple stages or levels, of
logic gates.