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    Due Date: 10/07/15 1. Write The VHDL Text For The 2-Bit Magnitude Comparator Shown Below

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    NonFicReader
    The document contains 4 sections describing VHDL code implementations: 1. A 2-bit magnitude comparator that outputs 1 if inputs A and B are equal, else 0. 2. A 2-bit full adder using BIT types with inputs A, B, carry in and outputs sum and carry out. 3. A 2-bit full adder using INTEGER types with inputs A, B as integers 0-3, output sum as integer 0-7. 4. A 4-state 8-bit ALU that performs different operations on inputs A and B based on 2-bit control signals S1 and S0, and outputs the result Y.

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    Due Date: 10/07/15 1. Write The VHDL Text For The 2-Bit Magnitude Comparator Shown Below

    Uploaded by

    NonFicReader
    25 views3 pages
    The document contains 4 sections describing VHDL code implementations: 1. A 2-bit magnitude comparator that outputs 1 if inputs A and B are equal, else 0. 2. A 2-bit full adder using BIT types with inputs A, B, carry in and outputs sum and carry out. 3. A 2-bit full adder using INTEGER types with inputs A, B as integers 0-3, output sum as integer 0-7. 4. A 4-state 8-bit ALU that performs different operations on inputs A and B based on 2-bit control signals S1 and S0, and outputs the result Y.

    Original Description:

    Simple VHDL Programs

    Original Title

    HW05

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    © © All Rights Reserved

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    The document contains 4 sections describing VHDL code implementations: 1. A 2-bit magnitude comparator that outputs 1 if inputs A and B are equal, else 0. 2. A 2-bit full adder using BIT types with inputs A, B, carry in and outputs sum and carry out. 3. A 2-bit full adder using INTEGER types with inputs A, B as integers 0-3, output sum as integer 0-7. 4. A 4-state 8-bit ALU that performs different operations on inputs A and B based on 2-bit control signals S1 and S0, and outputs the result Y.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    25 views3 pages

    Due Date: 10/07/15 1. Write The VHDL Text For The 2-Bit Magnitude Comparator Shown Below

    Uploaded by

    NonFicReader
    The document contains 4 sections describing VHDL code implementations: 1. A 2-bit magnitude comparator that outputs 1 if inputs A and B are equal, else 0. 2. A 2-bit full adder using BIT types with inputs A, B, carry in and outputs sum and carry out. 3. A 2-bit full adder using INTEGER types with inputs A, B as integers 0-3, output sum as integer 0-7. 4. A 4-state 8-bit ALU that performs different operations on inputs A and B based on 2-bit control signals S1 and S0, and outputs the result Y.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    1.

    Due Date: 10/07/15


    Write the VHDL text for the 2-bit magnitude comparator shown below.

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    Comparator
    A0
    A1

    0
    AEQB

    B0
    A

    B1
    1

    entity comparator_2bit is
    port(
    A : in STD_LOGIC_VECTOR(1 downto 0);
    B : in STD_LOGIC_VECTOR(1 downto 0);
    AEQB : out STD_LOGIC
    );
    end comparator_2bit;
    architecture comparator_2bit_arc of comparator_2bit is
    begin
    AEQB <= '1' when (A=B) else 0;
    end comparator_2bit_arc;

    2.

    Write the VHDL text file for a 2-bit full-adder using BIT types.
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    entity Full_Adder is port ( A,B:in BIT_VECTOR (1 downto 0);
    CI : in BIT;
    SUM : out BIT_VECTOR (1 downto 0);
    CO : out BIT );
    end Full_Adder;

    architecture Full_Adder_Arch of Full_Adder is


    signal TMP_CO : BIT;
    begin
    SUM(0)<=A(0) xor B(0) xor CI;
    SUM(1)<=A(1) xor B(1) xor TMP_CO;
    TMP_CO<=(A(0) and B(0)) or (B(0) and CI) or (A(0) and CI);
    CO<=(A(1) and B(1)) or (B(1) and TMP_CO) or (A(1) and TMP_CO);
    end Full_Adder_Arch;

    3.

    Due Date: 10/07/15


    Write the VHDL text file for a 2-bit full-adder using INTEGER types.

    use IEEE.STD_LOGIC_1164.all;
    use IEEE.STD_LOGIC_ARITH.all;
    use IEEE.STD_LOGIC_UNSIGNED.all;
    entity Adder is port (A,B : in INTEGER range 0 to 3;
    SUM : out INTEGER range 0 to 7;
    end Adder;
    architecture Adder_Arch of Adder is
    begin
    SUM <= A + B;
    - - most significant bit of SUM is carry out
    end Adder_Arch;

    Due Date: 10/07/15

    4.

    Develop the VHDL text file for a 4 state, 8-bit arithmetic and logic unit (ALU). The
    ALU inputs 2 8-bit numbers (A and B) and output an 8-bit result (Y) as shown in the

    table. (2 points).
    S1

    S0

    A+B

    AB

    Not A

    use IEEE.STD_LOGIC_1164.all;
    use IEEE.STD_LOGIC_ARITH.all;
    use IEEE.STD_LOGIC_UNSIGNED.all;
    entity ALU is port(A,B: in STD_LOGIC_VECTOR (7 downto 0);
    S: in STD_LOGIC_VECTOR (1 downto 0);
    Y: out STD_LOGIC_VECTOR (7 downto 0)
    );
    end ALU;
    architecture ALU_Arch of ALU is
    begin process begin
    case(S)
    when 00"=>Y<="00000000";
    when "01"=>Y<= A + B;
    when 10"=>Y<= A - B;
    when others => Y<= not A;
    end case;
    end process;
    end ALU_Arch;

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