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    1 (A) The Logic Expression For The Circuit Is A (BC+D) 1 (B) 2 2

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    Suvendra Sahoo
    The document discusses transistor sizing for logic gates and the calculation of propagation delays. It provides schematics and calculations for an inverter, NAND gate, and NOR gate. It compares the logical effort of NAND and NOR gates and provides formulas for calculating the logical effort of k-input NAND and NOR gates. Dynamic logic is noted to have higher toggle rates and power consumption than static logic.

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    1 (A) The Logic Expression For The Circuit Is A (BC+D) 1 (B) 2 2

    Uploaded by

    Suvendra Sahoo
    20 views7 pages
    The document discusses transistor sizing for logic gates and the calculation of propagation delays. It provides schematics and calculations for an inverter, NAND gate, and NOR gate. It compares the logical effort of NAND and NOR gates and provides formulas for calculating the logical effort of k-input NAND and NOR gates. Dynamic logic is noted to have higher toggle rates and power consumption than static logic.

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    The document discusses transistor sizing for logic gates and the calculation of propagation delays. It provides schematics and calculations for an inverter, NAND gate, and NOR gate. It compares the logical effort of NAND and NOR gates and provides formulas for calculating the logical effort of k-input NAND and NOR gates. Dynamic logic is noted to have higher toggle rates and power consumption than static logic.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    20 views7 pages

    1 (A) The Logic Expression For The Circuit Is A (BC+D) 1 (B) 2 2

    Uploaded by

    Suvendra Sahoo
    The document discusses transistor sizing for logic gates and the calculation of propagation delays. It provides schematics and calculations for an inverter, NAND gate, and NOR gate. It compares the logical effort of NAND and NOR gates and provides formulas for calculating the logical effort of k-input NAND and NOR gates. Dynamic logic is noted to have higher toggle rates and power consumption than static logic.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 7

    1(a) The logic expression for the circuit is

    A(BC+D)
    1(b)
    2
    2
    2

    2
    3
    3
    3
    3

    The above figure is the sizing of the transistor widths to give the same effective rise and
    fall resistances as a unit inverter
    1(c)

    Layout

    1(d) Area =5 track 6 track


    40

    48

    =1920

    1(e ) Resistance across pmos transistor B and C is R/4 and capacitance is 8C


    Resistance across pmos transistor D is R/4

    and capacitance is 8C

    Resistance across pmos Transistor A is R/2 and capacitance is 4C


    Resistance across nmos transistor B and C is R/4 and capacitance is 4C
    Resistance across nmos transistor D is R/4 and capacitance is 4C
    Resistance across nmos Transistor A is R/2 and capacitance is 2C

    1(f) Elmore worst case rising propagation delay=(5+4h)RC


    Here h=3
    1(g)

    Elmore worst case falling propagation delay


    (7+4h)RC
    h=3

    2 (a) Schematic of CMOS inverter

    2 (b)

    Here tpd() = RC
    Where R : Equivalent resistance

    C : Load capacitance

    2 (c) NAND gate

    NOR Gate

    Wp=3
    Wmin
    Wp=3Wmin

    2Wmin

    2Wmin

    2(d) For NOR gate


    To obtain the same pullup drive, transistors four units wide are required, since two of them in
    series must be equivalent to one transistor two units wide in the inverter. Summing the input

    capacitance on one input, we find that the NOR gate has logical effort, g = 5/3. This is larger than
    the logical effort of the NAND gate because pullup transistors are less effective at generating
    output current than pulldown transistors. Were the two types of transistors similar, i.e., = 1, both

    4
    1

    For NAND gate


    The input capacitance of one input signal is the sum of the width of the pulldown transistor and
    the pullup transistor, or 2+2 = 4. The input capacitance of the inverter with identical output drive
    is Cinv = 1+2 = 3. the logical effort per input of the 2-input NAND gate is therefore g = 4=3. both
    inputs of the NAND gate have identical logical efforts. C.

    2
    2

    2(e) i) Dynamic logic is difficult to design


    ii) It has higher toggle rate than static

    iii) So overall power consumption is larger compare to static. So it is less used.


    2) (f) Logical effort of k-input NOR gate
    for 2 input NAND gate g = (2+2)/ (1+2) = 4/3.
    For 3 input NAND gate, g = (3+2)/ (1+2) =5/3
    For k input NAND gate g=(k+2)/(1+2)
    Logical effort of k-input NOR gate
    For 2 input NOR gate g = (1+4)/ (1+2) = 5/3
    For k input NOR gate, g = (2k+1)/3

    Different types of verification approach


    What are

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