VLSI MODULE-3

Jayalakshmi.N
DELAY:
• Introduction, Transient response,
• RC delay model, Linear delay model,
• Logical efforts of paths.(4.1 to 4.5 of Text2)
Combinational Circuit Design:
• Introduction
• Circuit families(9.1 to 9.2 of Text2)
• Suppose the transistors obey the long-channel
models. The current depends on whether N1 is
in the linear or saturation regime.
• we find the differential equation governing VB
Plot the response of the inverter to a step input and determine the
propagation delay. Assume that the nMOS transistor width is
1μm and the output capacitance is 20 fF. Use the following
longchannel model parameter values for a 65-nm process: L = 50 nm,
VDD = 1.0 V, Vt = 0.3 V, tox = 10.5 Å, μ = 80 cm2/V · s.
In a real circuit, the input comes from another gate with a
nonzero rise/fall time.
This input can be approximated as a ramp with the same
rise/fall time.
Assuming Vtn + |Vtp| < VDD, the ramp response includes
three phases, as shown in Table 4.1.
3-input NAND gate shows capacitances.
 TRANSIENT RESPONSE
• Now, consider applying the RC model to estimate the step
response of the first-order system shown in Figure
• This system is a good model of an inverter sized for equal rise
and fall delays.
• The system has a transfer function
The factor of ln 2 = 0.69 is cumbersome. The effective
resistance R is an empirical parameter anyway, so it is
preferable to incorporate the factor of ln 2 to define a new
effective resistance R ‘= R ln 2.
Now the propagation delay is simply R’C. For the sake of
convenience, we usually drop the prime symbols and just
write
tpd = RC
The transfer function is
EQ (4.12) is so complicated that it defeats the purpose of
simplifying a CMOS circuit into an equivalent RC
network.
ELMORE DELAY
The Elmore delay model [Elmore48] estimates the delay
from a source switching to one of the leaf nodes changing
as the sum over each node i of the capacitance Ci on the
node, multiplied by the effective resistance Ris on the
shared path from the source to the node and the leaf.
Compute the Elmore delay for Vout in the 2nd order RC
system from below figure

Solution: Elmore delay is

Estimate tpd for a unit inverter driving m identical unit
inverters.

Elmore delay is tpd = (3 + 3m)RC.

If a unit transistor has R = 10 k and C = 0.1 fF in a 65 nm
process, compute the delay, in picoseconds, of the inverter
in Figure 4.14 with a fanout of h = 4

the delay is (3 + 3h)(1 ps) = 15 ps.

Layout dependance of capacitance
In a good layout, diffusion nodes are shared wherever
possible to reduce the diffusion capacitance.
LAYOUT STYLES:
LINEAR DELAY MODEL
• The RC delay model showed that delay is a linear
function of the fanout of a gate.
• In general, the normalized delay of a gate can be
expressed in units of 𝜏
d=f+p
• p is the parasitic delay inherent to the gate when no
load is attached. f is the effort delay or stage effort that
depends on the complexity and fanout of the gate:
f = gh
• The complexity is represented by the logical effort. An
inverter is defined to have a logical effort of 1.
• More complex gates have greater logical efforts,
indicating that they take longer to drive a given fanout.
• For example, the logical effort of the 3-input NAND
gate from the previous example is 5/3. A gate driving h
identical copies of itself is said to have a fanout or
electrical effort of h.
• If the load does not contain identical copies of the gate,
the electrical effort can be computed as
h=cout/cin
LOGICAL EFFORT
• Logical effort of a gate is defined as the ratio of the
input capacitance of the gate to the input capacitance of
an inverter that can deliver the same output current.
• Logical effort can be measured in simulation from
delay vs. fanout plots as the ratio of the slope of the
delay of the gate to the slope of the delay of an inverter.
• Below figure shows inverter, 3-input NAND, and 3-
input NOR gates with transistor widths chosen to
achieve unit resistance, assuming pMOS transistors
have twice the resistance of nMOS transistors.5 The
inverter presents three units of input capacitance .
PARASITIC DELAY
• The parasitic delay of a gate is the delay of the
gate when it drives zero load. It can be estimated
with RC delay models.
• A crude method good for hand calculations is to
count only diffusion capacitance on the output
node.
• The inverter has three units of diffusion
capacitance on the output, so the parasitic delay is
3RC = Y.
DELAY IN LOGIC GATE
1. Use the linear delay model to estimate the delay of the fanout-of-4
(FO4) inverter from Example 4.6. Assume the inverter is constructed
in a 65 nm process with 𝜏= 3 ps.

SOLUTION: The logical effort of the inverter is g = 1, by

definition. The electrical effort is 4 because the load is
four gates of equal size. The parasitic delay of an inverter
is pinv ~ 1. The total delay is d = gh + p = 1 × 4 + 1 = 5 in
normalized terms, or tpd = 15 ps in absolute terms.
2. A ring oscillator is constructed from an odd number of
inverters, as shown in Figure 4.24. Estimate the frequency of
an N-stage ring oscillator.

Solution: The logical effort of the inverter is g = 1, by definition. The

electrical effort of each inverter is also 1 because it drives a single identical
load. The parasitic delay is also 1. The delay of each stage is d = gh + p = 1 × 1
+ 1 = 2. An N-stage ring oscillator has a period of 2N stage delays because a
value must propagate twice around the ring to regain the original polarity.
Therefore, the period is T = 2 × 2N. The frequency is the reciprocal of the
period, 1/4N. A 31-stage ring oscillator in a 65 nm process has a frequency of
1/(4 × 31 × 3 ps)= 2.7GHZ
DRIVE
• A good standard cell library contains multiple sizes of
each common gate.
• The sizes are typically labeled with their drive.
• For example, a unit inverter may be called inv_1x. An
inverter of eight times unit size is called inv_8x. A 2-
input NAND that delivers the same current as the
inverter is called nand2_1x.
• It is often more intuitive to characterize gates by their
drive, x, rather than their input capacitance. If we
redefine a unit inverter to have one unit of input
capacitance, then the drive of an arbitrary gate is
 x=Cin/g
Delay can be expressed in terms of drive as
D=Cout/x +p
Logical efforts of paths
• The method of Logical Effort [Sutherland99]
provides a simple method “on the back of an
envelope” to choose the best topology and number
of stages of logic for a function
• Based on the linear delay model, it allows the
designer to quickly estimate the best number of
stages for a path, the minimum possible delay for the
given topology, and the gate sizes that achieve this
delay.
Delay in multistage logic networks:
• Figure shows the logical and electrical efforts of each
stage in a multistage path as a function of the sizes of
each stage.
• The path of interest (the only path in this case) is
marked with the dashed blue line. Observe that logical
effort is independent of size, while electrical effort
depends on sizes.
• This section develops some metrics for the path as a
whole that are independent of sizing decision.
We must introduce a new kind of effort to account for
branching between stages of a path. This branching effort
b is the ratio of the total capacitance seen by a stage to the
capacitance on the path; in Figure 4.30 it is (15 + 15)/15 =
2
3-STAGE PATH
Estimate the minimum delay of the path from A to B in Figure
4.30 and choose transistor sizes to achieve this delay. The initial
NAND2 gate may present a load of 8λ of transistor width on the
input and the output load is equivalent to 45λ of transistor width.
Calculate
1. Logical effort G
2. Electrical effort H
3. Branching effort B
4. Path effort F
5. Best stage effort
6. Parasitic delay P
7. Delay
Solution:
• The path logical effort is G = (4/3) × (5/3) × (5/3) =
100/ 27.
• The path electrical effort is H = 45/8.
• The path branching effort is B = 3 × 2 = 6.
• The path effort is F = GBH = 125.
• As there are three stages, the best stage effort is f=5
• The path parasitic delay is P = 2 + 3 + 2 = 7. Hence,
the minimum path delay is D = 3 × 5 + 7 = 22 in units
of , 𝜏
• The gate sizes are computed with the capacitance
transformation from EQ (4.41) working backward
along the path: y = 45 × (5/3)/5 = 15.
• x = (15 + 15) × (5/3)/5 = 10.
• We verify that the initial 2-input NAND gate has the
specified size of (10 + 10 + 10) × (4/3)/5 = 8.
• For example, a 2-input NOR gate should have a 4:1 P/N
ratio. If the total input capacitance is 15, the pMOS
width must be 12 and the nMOS width must be 3 to
achieve that ratio.
• We can also check that our delay was achieved. The
NAND2 gate delay is d1 = g1h1 + p1 = (4/3) × (10 +
10 + 10)/8 + 2 = 7.
• The NAND3 gate delay is d2 = g2h2 + p2 = (5/3) × (15
+ 15)/10 + 3 = 8.
• The NOR2 gate delay is d3 = g3h3 + p3 = (5/3) × 45/15
+ 2 = 7. Hence, the path delay is 22.
• In a 65 nm process with 𝜏= 3 ps, the delay is 66 ps.
CHOOSING BEST NUMBER OF STAGES
• Given a specific circuit topology, we now know
how to estimate delay and choose gate sizes.
• However, there are many different topologies that
implement a particular logic function.
• Logical Effort tells us that NANDs are better than
NORs and that gates with few inputs are better than
gates with many.
• Logic designers sometimes estimate delay by
counting the number of stages of logic, assuming
each stage has a constant “gate delay.”
Example:
A control unit generates a signal from a unit-sized inverter. The
signal must drive unit-sized loads in each bitslice of a 64-bit
datapath. The designer can add inverters to buffer the signal to
drive the large load. Assuming polarity of the signal does not
matter, what is the best number of inverters to add and what
delay can be achieved?
Solution:
Figure shows the cases of adding 0, 1, 2, or 3 inverters. The
path electrical effort is H = 64. The path logical effort is G = 1,
independent of the number of inverters. Thus, the path effort is
F = 64. The inverter sizes are chosen to achieve equal stage
effort. The total delay is
• The logic block shown in Figure has n1 stages and a
path effort of F. Consider adding N – n1 inverters to the
end to bring the path to N stages.

• The delay of the new path is

• Differentiating with respect to N and setting to 0 allows
us to solve for the best number of stages, which we will
call N.

• A path achieves least delay by using stages.

Example
• Ben Bitdiddle is designing a decoder for a register file
in the Motoroil 68W86, an embedded processor for
automotive applications. Help ben design the decoder
for a register file.
Decoder specifications
• 16-word register file
• 32-bit words Each register bit presents a load of three
unit-sized transistors on the word line.
• True and complementary versions of the address bits
A[3:0] are available
• Each address input can drive 10 unit-sized transistors.
• Ben needs to decide
How many stages to use
How large should each gate be
How fast can decoder operate
Number of stages
• Decoder effort is mainly electrical and branching
Electrical effort: H=32*3/10=9.6
Branching effort: B=8
• If we neglect logical effort (assume G=1)
Path effort: F=GBH=76.8
Number of stages N=log4F=3.1
• Try a 3-stage design
3-stage decoder design
• logical effort of G = 1 × (6/3) × 1 = 2
• path effort is F = (2)(8)(9.6) = 154.
• Stage effort is =5.36
• Gate sizes z = 96 × 1/5.36 = 18
y = 18 × 2 /5.36 = 6.7.
• The delay is 3 × 5.36 + 1 + 4 + 1 = 22.1.
Summary of Logical effort
Limitations of Logical effort
• Logical Effort does not account for interconnect.
• Logical Effort explains how to design a critical path for
maximum speed, but not how to design an entire circuit
for minimum area or power
• Paths with nonuniform branching or reconvergent
fanout are difficult to analyze
• The linear delay model fails to capture the effect of
input slope.
COMBINATIONAL CIRCUIT DESIGN
STATIC CMOS
• Designers accustomed to AND and OR functions must
learn to think in terms of NAND and NOR to take
advantage of static CMOS.
• Compound gates are particularly useful to perform
complex functions with relatively low logical effort.
Processes with multiple threshold voltages, multiple
flavors of gates can be constructed with different
speed/leakage powers and trade-offs.
Bubble pushing
CMOS stages are inherently inverting, so AND and OR
functions must be built from NAND and NOR gates.
DeMorgan’s law helps with this conversion.