210

ACTIVE FILTERS

ACTIVE FILTERS
An electrical filter may be defined as a transducer for separating waves on the basis of their frequencies (1). There are
numerous everyday uses for such devices ranging from the
filter that allows one to select a particular radio station, to
the circuit that detects brainwaves, to resonant cavities that
operate at microwave frequencies. Indeed, filters are needed
for operation across the electromagnetic spectrum. Furthermore, they are required to perform frequency selection to satisfy various specialized approximating functions, not necessarily confined to the conventional low-pass, bandpass, highpass, and band-stop forms.
However, the purpose of this article is to focus on a particular category of filter, the active filter, whose evolution over
the past 40 years has been heavily influenced by advances in
microelectronic circuit fabrication. The earliest active filters
were motivated by the need to overcome significant limitations of inductorcapacitor (LC) passive filters, namely:
1. In the audio band, inductors are bulky and prone to
pick up.
2. Resistorcapacitor (RC) filter structures offer a limited
range of responses and are subject to substantial passband attenuation.
By contrast, active RC structures can realize (theoretically) lossless filter characteristics in miniaturized form. Passive and active filter properties are summarized in Table 1.
A disadvantage of the active filter is its need for a power
supply and the incorporation of one or more active elements,
usually operational amplifiers. As a result, highly selective
filters need careful design so as to avoid instability. However,
as active filter design has matured, a small number of highly
reliable topologies have evolved that provide solid performance across a variety of fabrication technologies.
The earliest active filters used discrete components and
were based upon direct synthesis of RC sections with appropriately embedded active devices such as the negative impedance converter (2). Second-order sections were then cascaded
to form higher order structures.
Subsequently, a catalog of building blocks was developed
by Sallen and Key (3), which led to a much broader interest
in active filters. This was due in no small part to removal of
the need for classical synthesis expertise.
However, widespread use of active filters was still inhibited by concerns over sensitivity, particularly when compared
to the passband performance of passive filters. This was overcome by the simulation of the floating inductor (4) and the
widespread availability of operational amplifiers whose high-

Table 1. Comparison of Active and Passive Filter Properties

Audio Band Filters
LC
Bulky
Lossy (low Q)
Stable (absolutely)
Transmission loss

Active RC
Small
Lossless (high Q)
Stability depends upon design
Capable of transmission gain

quality performance and low cost resulted in a fundamental

change in design philosophy.
Designers, previously cost-constrained to single-amplifier
second-order sections, were now able to consider multiamplifier sections whose performance and multipurpose functions
made commercial production a viable proposition. In particular, the state variable topology (5) formed the basis for a universal filter yielding all basic filtering functions from a single structure.
Inductor replacement and direct simulation techniques
such as the leapfrog approach (6) offered low-sensitivity analogs of classical LC filters. The difficulty in tuning these devices was simplified enormously by the introduction of computer-controlled laser trimming using hybrid microelectronics
technology. Indeed, by the mid-1970s, sophisticated fifth-order elliptic characteristic filters were in large-scale production
within the Bell System (7).
Thus, over a period of 20 years (19541974), active filter
designers had come to rely upon a relatively small number of
basic building blocks to form second-order sections, or were
basing higher-order designs on analogs of LC structures. Although many realizations used discrete components, largerscale production of thick and thin film hybrid microelectronic
structures was quite common.
The advent of switched-capacitor filters in 1979 (8) overcame the need to laser trim resistors and yielded the first
fully integrated active filters. While truly a sampled-data
technique, the use of sufficiently high clock frequencies meant
that active filters could be used up to 100 kHz, far higher
than by conventional analog techniques. Subsequent developments have led to metal-oxide semiconductor field-effect transistor-capacitor (MOSFET-C) and operational transconductance amplifier-capacitor (OTA-C) filters (9) which yield
authentic analog performance at frequencies exceeding 1
MHz.
The following sections will concentrate on a few fundamental filter design techniques that form the basis for modern
active filter design. The Sallen and Key, multiple loop feedback, and state variable structures have stood the test of time
and have proven to be as effective in discrete component realizations as they have in MOSFET-C structures. They all form
higher-order filters when cascaded with similar sections. Finally, the leapfrog design and direct replacement techniques
are discussed as examples of direct higher-order filter synthesis.
SECOND-ORDER STRUCTURES
The fundamental building blocks for active RC filters are second-order structures which can readily be cascaded to realize
higher-order approximating functions described by the general voltage transfer function:



z
s2 +
s + z2
Vo
Qz

=H
p
Vi
s2 +
s + p2
Qp

(1)

where z, Qz and p, Qp refer to the zero and pole frequency

and Q, respectively. All-pole functions (low-pass, bandpass,
high-pass) occur when only one of the numerator terms (s0,

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

ACTIVE FILTERS

211

G2
3
1

G1

2
RC
network

V1

V1

V3

Figure 1. Sallen and Key structure consisting of a controlled source

and an RC network. Appropriate choice of the RC network yields all
basic forms of second-order transfer functions.

s1, or s2) is present. A notch occurs when the s1 term disappears in the numerator. We will not discuss the more general
case (10) that arises when all numerator terms are present
simultaneously.
The topologies that follow are suitable for design using discrete, hybrid, or fully monolithic fabrication. Furthermore,
they have stood the test of time for ease of design, tuning
simplicity, and relatively low cost.

Sallen and Key originally proposed (3) a family of all-pole filters based upon the circuit shown in Fig. 1, for which
Ky21
V3
=
V1
y22 + Ky23

(2)

By appropriate choice of the passive RC network, it is possible

to realize all forms of basic filter. However, because the creation of a band-stop (notch) section requires the use of twin T
networks, which are inherently difficult to tune, we confine
our discussion to the realization of all-pole functions.

Table 2. Sallen and Key Realizations

a

RC Structure

Voltage Transfer Function

3
1

G2

G1

C2

G2 G1 + G2 KG2
s2 + s
+

C2
C1
C2

3
G1
2

2
C1

C2

s2

G2

G1
1

G2

C1

2
C2

s2 + s

C1

G1

2
C2

G2

KG2
C2

G2 G1 + G2
+
C2
C1

3
4

G1G2
+
C1C2

Ks 2
G2 G2 G1
G1G2
+s
+
+
(1 K ) +
C2 C1 C1
C1C2

3
3

KG1G2
C1C2

C1

G1G2
+ (1 K )
C1C2

KG1
(1 K )C1

s
G1 G2 G2
s2 +
+
+
(1 K ) C1 C1 C2

K > 0 for circuits 1 and 2, K < 0 for circuits 3 and 4.

G1G2
+
(1 K )C1C2

C1

G3

V3

Figure 2. Sallen and Key second-order bandpass filter using positive-gain controlled source.

Table 2 illustrates four topologies and the resulting voltage

transfer function when that RC structure is used in the circuit of Fig. 1. Thus, it is seen that low-pass and high-pass
sections can be achieved with a positive-gain controlled
source, whereas the two bandpass sections require a negativegain controlled source (11).
Although not included in the original catalog, the five-element bandpass circuit of Fig. 2, which utilizes a positive-gain
controlled source, is now generally incorporated under the
Sallen and Key banner. In this case:

Sallen and Key

Circuit
No.

C2

V3
=
V1

KG1
C1


G (G +G2 )
G
(G
G
(1
K)
+G
2
1
3)
s2 +
+
+ 3 s+ 3 1
C1
C1
C1
C1C2
s

(3)

Design is most commonly restricted to the positive-gain

controlled source realizations, despite the inherent positive
feedback used to enhance Qp. In general, if realizations are
restricted to Qp 10, the advantages of the lower component
spread in this design outweigh the stability considerations.
Design is relatively straightforward and proceeds by coefficient matching.
Example 1. For our example, we design a second-order lowpass Chebyshev filter having 0.5 dB passband ripple and a
passband gain of 20 dB. From the standard tables (1215),
the normalized transfer function is
H
V3
= 2
V1
s + 1.426s + 1.516

(4)

A passband gain of 20 dB is equivalent to an absolute gain of

10, so that H 15.16. By matching the low-pass expression
from Table 2 and the coefficients of Eq. (4), we obtain

KG1 G2
= 15.16
C1C2
G1 G2
= 1.516
C1C2
G2
G + G2
KG2
+ 1

= 1.426
C2
C1
C2

(5a)
(5b)
(5c)

Thus, K 10 [from Eqs. (5a) and (5c)]. The remaining two

equations contain four unknowns, indicating freedom of
choice for two of the elements. Such freedom of choice is a
characteristic of the coefficient-matching technique. For convenience, set C1 C2 IF, since this is highly desirable in

212

ACTIVE FILTERS
Table 3. MFB Structure and Voltage Transfer Functions
Filter Type

Network

Voltage Transfer Function

3
1

2
RC
network

C5

G4

(a) Low-pass

V1

G1

V3

G3
C2

G5

C4

Figure 3. Multiple feedback (MFB) structure consisting of an operational amplifier and an RC network. Appropriate choice of the RC
network yields all basic forms of second-order transfer functions.

(b) High-pass

C1

C3
G2

C4

(c) Bandpass

many practical realizations. As a result,

G1 G2 = 1.516

(6a)

G1 8G2 = 1.426

(6b)

The only solution yielding positive values is G1 4.268 S and

G2 0.355 S. Impedance and frequency denormalization can
be applied, depending upon specific design requirements.
Realization of the basic low-pass Sallen and Key filter has
been widely discussed in the literature (11). Popular alternatives to the C1 C2 IF used above are as follows:
1. Setting C1 C2 C, G1 G3 G, and K 3 (1/Q)
2. Setting K 1 (thereby eliminating two gain-setting resistors), G1 nG3 and C1 mC2
3. Setting K 2 (for equal-valued gain-setting resistors),
C1 C2 C and G3 Q2G1
Multiple Feedback Structure
The multiple feedback (MFB) structure (16) is derived from
the general feedback configuration of Fig. 3, in which the active element is an ideal operational amplifier.
The most common realization of the RC network is shown
in Fig. 4, which yields the MFB transfer function
Y1Y3
V3
=
V1
Y5 (Y1 + Y2 + Y3 + Y4 ) + Y3Y4

(7)

G1

C3
G2

G1G3
s 2C2C5 + sC5(G1 + G3 + G4) + G3G4

s 2C1C3
s 2C3C4 + sG5(C1 + C3 + C4) + G2G5

G5

sG1C3
s 2C3C4 + sG5(C3 + C4) + G5(G1 + G2)

stable, negtive-feedback circuit. Specific realizations of the

all-pole functions are shown in Table 3.
As for Sallen and Key sections, design proceeds by coefficient matching. A widely used design set is illustrated in Table 4, for which both bandpass and high-pass circuits use
equal-valued capacitors. No such solution is possible for the
low-pass circuit, though an equal-valued resistor pair is possible.
Although highly stable, the MFB structure has a pole Q
dependent upon the square root of component ratios. Thus,
for a Qp of n, the maximum component spread will be proportional to n2. As a result, the MFB arrangement is best suited
to modest values of Qp, typically not greater than 10.
Modified Multiple-Loop Feedback Structure
In positive-feedback topologies such as the Sallen and Key,
Qp is enhanced by subtracting a term from the damping (s1)
coefficient in the denominator. By contrast, in negative-feedback topologies such as the MFB, high values of Qp are obtained at the expense of large spreads in element values. The
two techniques are combined in the modified multiple-loop

The basic all-pole functions can be realized by single-element

replacement of the admittances Y1 Y5, yielding a highly
Table 4. Element Values for MFB Realizations (H is the
Numerator Constant in Each Case)

Element Value
Bandpass

Y1

Y4

Y3

Y5

High-pass

G1 H

C1 H

G2 2p Qp H

G2 p(2 H)Qp

C3 1

C3 1

H
p
Qp(22p H)
C2
2p
G 3 p

C4 C 3

C4 C 3

G4 G 3

Y2

Figure 4. Three-terminal, double-ladder structure for use in MFB

sections.

Low-pass

G5

p
2Qp

G5

p
Qp(2 H)

G1

C5

2p
Qp(22p H)

ACTIVE FILTERS

C4
G1

G5

C3
Vi

Vo

Gb

Ga

Figure 5. Modified multiple-loop feedback (MMFB) structure due to

Deliyannis which yields a second-order bandpass function. By judicious use of positive feedback, this circuit reduces the large component spreads which are characteristic of the MFB structure while
yielding greater stability margin than the Sallen and Key arrangement.

213

versatility and ease of tuning. The advent of the operational

amplifier eliminated earlier cost concerns, and the ability to
realize relatively high-Q sections remains an attractive consideration. However, it is the ability of the circuit to yield all
basic forms of second-order sections by appropriate choice of
output terminal that has made it so popular for commercial
manufacture (19). Custom filters are readily fabricated by appropriate interconnection of terminals, yielding the universal
filter terminology of several vendors. In particular, highly reliable notch filters are possible through the addition of a summing amplifier to the basic three-amplifier array.
The circuit shown in Fig. 7 is an example of a state-variable section and can be recognized as an analog computer realization of a second-order differential equation. It is more
commonly referred to as the Huelsman-Kerwin-Newcomb
(HKN) filter (5). In the frequency domain it is capable of yielding a variety of voltage transfer functions, according to the
particular output connections used. Assuming ideal operational amplifiers, the specific transfer functions are as follows:

feedback (MMFB) circuit (17) of Fig. 5, for which

1. The low-pass response with

Vo
sC3 G1 (1 + k)
= 2
Vi
s C3C4 + s{G5 (C3 + C4 ) kC3 G1 } + G1 G5

(8)

where k Gb /Ga, and the Q-enhancement term signifies the

presence of positive feedback.
Design of this bandpass circuit proceeds by coefficient
matching, although the reader is advised to adopt the stepby-step procedure developed by Huelsman (11).
A generalization of the MMFB circuit, yielding a fully biquadratic transfer ratio has been developed by Friend et al.
(18), as shown in Fig. 6. This arrangement was used extensively in the Bell System where the benefits of computer-controlled (deterministic) laser trimming techniques and largescale manufacture were utilized. Although this resulted in
quite exacting realizations using tantalum thin-film technology, the structure is less suited to discrete component realizations. An ordered design process based upon coefficient
matching is presented elsewhere by Huelsman (15).

V1
=
Vi

R2 [R3 + R10 ]
R3 [R1 + R2 ]



R2 [R3 + R10 ]
V2
D(s)
= R9C2 s
Vi
R3 [R1 + R2 ]

R (R + R10 )
V3
C C R R s2
= 2 3
Vi
R3 (R1 + R2 ) 1 2 8 9

R4


D(s)

C1

R6

(9c)

where



R1 (R3 + R10 )
R
C2 R9 s + 10
R3 (R1 + R2 )
R3

A general biquadratic function may be obtained by combining the various outputs via a summing network, as shown in
Fig. 8. The composite voltage transfer function then becomes

R (R + R3 )R5 (R6 + R7 )
Vo
= 2 10
Vi
(R1 + R2 )R3 (R4 + R5 )R7

[R4 + R5 ]R6

R9C2 s +
C1C2 R8 R9 s +
R [R + R7 ]


 5 6

R1 [R3 + R10 ]

C1C2 R8 R9 s2 +
C2 R9 s +

R3 [R1 + R2 ]

R2

(9b)

3. The high-pass response with

State Variable Structure

C2

(9a)

2. The bandpass response with

D(s) = C1C2 R8 R9 s2 +
Based upon analog computer design techniques, the state
variable (SV) structure (5) assumed popularity because of its


D(s)

R4
R5
R10
R3

(10)

Rc

Now consider the design of a low-pass response

Vi

Rb
R5

R7

Vo

RD

Figure 6. The Friend biquad which generalizes the MMFB structure

of Fig. 5 so as to yield biquadratic filters.

T (s) =

H
s2 + (p s/Qp ) + p2

(11)

It is clear from Eqs. 9(a) and (10) that there is considerable

flexibility in the design since there are nine passive components and only three specified variables in Eq. (11).

214

ACTIVE FILTERS

V3 (high-pass)
R10

C1

C2

R3
R9

Vi

R8

+
R1

Vi
(low-pass)

R2

Figure 7. State variable filter capable of yielding

a variety of all-pole second-order transfer functions.

V2
(bandpass)

The design equations are thus


R10
p =
R3 R8 R9C1C2

R10
C1C2 R8 R9
R3

Qp = 
R1 (R3 + R10 )
R9C2
R3 (R1 + R2 )

R2 (R3 + R10 )
H=
R3 (R1 + R2 )C1C2 R8 R9

Setting C IF and R8 R9 R yields the following simplified equations

(12a)

1
R2


R
1
Qp =
1+ 2
2
R
2p =

(12b)

(14c)

Therefore, the design equations are

Selecting C1 C2 C and R1 R3 R10 R gives

2R2
H=
(R + R2 )C2 R8 R9

(14b)

2R2 /R

H= 
R
1 + 2 R2
R

(12c)

p = (R8 R9C2 )1/2


(R + R2 ) R8
Qp =
2R
R9

(14a)

(13a)

R =

1
p

(15a)

(13b)

R2
+ 2Qp 1
R

(15b)

(13c)

The gain constant, H, is fixed as [2 (1/Qp)]p2.

R10

C1
V3

C2
V2

R3
R9

Vin

+
R1

R8

V1

R2

R6
R7

Vout
+
Figure 8. Composite state variable structure.
The addition of an output summing network to
the arrangement of Fig. 7 yields fully biquadratic transfer functions.

R4
R5

ACTIVE FILTERS

Example 2. Here we design a state-variable filter satisfying

the following normalized elliptic function characteristic having a notch at 1.4 kHz.

T (s) =

H(s2 + z2 )
s2 + 1.438664
=

2
p
s + 0.314166s + 1.167222
s2 +
s + p2
Qp

(16)

Thus, z 1.199, p 1.08038, and Qp 3.4389.

Realization requires the use of the summing network to
combine the low-pass and high-pass outputs. Since no bandpass component is required, the left-hand end of resistor R7
(Fig. 8) should be grounded.
Now consider the realization of the low-pass section. Set
R C 1 and Eqs. 15(a) and (b) to give the normalized
component values as

C1 = C2 = 1F
R = R8 = R9 = 0.926
R = 1

so that R1 = R3 = R10 = 1
and R2 = 5.878

2 1.4 103
= 7.351 103
1.199

Assume that available capacitors have a value of 6800 pF.

Then, the impedance denormalization factor is evaluated as
Zn =

HIGHER-ORDER REALIZATIONS
Higher-order filters may be designed by cascading second-order structures of the form described in the previous section.
Odd-order functions are accommodated by the addition of a
single-pole section or, if combined with a low-Q pole-pair, by
the addition of a third-order section. The section types (Sallen
and Key, MFB, MMFB, SV) may be mixed in a realization so
that the SV is used for higher Q and notch functions. Particular care must be taken with the selection of pole-zero pairs
and the ordering of sections due to considerations of dynamic
range. A fuller discussion of these features is described elsewhere (2022).
The major advantage of the cascade approach is the ability
to independently tune each pole pair. This is offset to some
degree by the higher sensitivity to component changes and
the care needed to properly order the sections and pair the
poles and zeroes. A widely used alternative bases designs on
the passive LC prototype whose passband sensitivity is minimal. The most common approaches are described below.
Inductor Replacement

The gain constant, H, has the value 1.995. The frequency

denormalization factor, n, is
n =

1
= 20 k
6800 1012 7.351 103

As indicated above, it is highly desirable to base active RC

filter designs upon passive LC prototypes because of the resulting low passband sensitivity. An added advantage results
from the availability of tabulated LC designs (1215), which
obviate the need for sophisticated synthesis techniques. Thus,
for a given standard approximating function, the LC prototype may be established with the aid of design tables.
The resulting inductors may be replaced by means of an
appropriately terminated generalized impedance converter
(GIC). The ideal GIC is shown in Fig. 9, for which

Therefore, the denormalized values are

C1
R1
R8
R2

= C2 = 6800 pF

= R3 = R10 = 20 k

= R9 = 18.7 k
standard 1% values

= 118 k

1.709R5 (R6 + R7 )
Vo
=
Vin
R7 (R4 + R5 )

s2

s2 + 1.1672(R4/R5 )
+ 0.314179s + 1.1672

a11
= k(s)ZL
a22
a
1
Z
= 22 =
a11
k(s) L

Z11 =

(18a)

Z22

(18b)

if a12 a21 0.

The high-pass and low-pass outputs may now be combined

to yield the desired transfer function of Eq. (16). Thus, by
substituting normalized element values into Eq. (10)


215

GIC
[a]

(17)

The location of z is obtained by appropriate choice of the resistor ratio, R4 /R5. Hence,

Z11ZL
(a)

R4
= 1.2326
R5
Choosing R5 20 k gives R4 24.65 k. The dc gain of
the filter is determined by appropriate choice of R6 /R7. If these
resistors are set equal at 20 k, the resulting dc gain is
5.52 dB.
The filter may be tuned by means of the R4 to R5 ratio to
locate the notch accurately. In practice, this may be observed
by closing a Lissajous pattern on an oscilloscope. The frequency at which this occurs will be z.

ZL

1
GIC
[a]

ZL
1

2
Z22ZL
(b)

Figure 9. Generalized impedance converter (GIC). (a) Load at terminal 2. (b) Load at terminal 1.

216

ACTIVE FILTERS

C1

L1

C2

L2

L3

L4

Z2

Z3

(a)

2
Z1

C3

Z4

C1

R
ZL

C2

C3

ZL

R
R2

R1

R3

R4

Figure 10. Antoniou GICthe most widely used realization of this

important circuit element.

(b)

The most commonly used realization of the GIC, from Antoniou (23), is shown in Fig. 10. In this case
k(s) =

Z1 Z3
Z2 Z4

Figure 11. High-pass filter realization using direct inductor replacement. (a) Passive prototype. (b) Active realization using resistor-terminated GICs to realize the grounded inductors.

(19)
capacitor, because


Z22 

Thus, if we select
Z1 = Z3 = Z4 = R and Z2 =

1
sC

we obtain k(s) sk. If ZL R1, then

Z11 = sk R1
and we have simulated a grounded inductor whose Q value
far exceeds that of a conventional coil. Indeed, audio band Q
factors of the order of 1000 are readily obtained if high-quality capacitors are used in the GIC.
Grounded inductor simulation is readily applicable to the
realization of high-pass filters, as illustrated in Fig. 11. Note
that a dot ( ) is used to denote terminal 1 of the GIC, because
it is a directional device having a conversion factor k(s) from
terminal 1, and 1/k(s) from terminal 2.
The simulation of a floating inductor requires the use of
two GICs, as shown in Fig. 12. However, the simulation of
structures containing several floating inductors can become
undesirable due to the excessive number of active blocks.
Frequency-dependent Negative Resistance
Depending upon the choice of impedances Z1 Z4, the GIC of
Fig. 10 may be used to provide conversion factors of sn, where
n 1, 2. If one internal port impedance is capacitive and
the other three are resistive, the conversion factor is ks in
one direction and 1/ks in the other. Use of two internal capacitors yields ks2 and 1/ks2, respectively. Using the first
combination of elements and a capacitor at port 1 produces a
port 2 impedance given by Z22 (1/s2)D, where D is frequency
invariant. At real frequencies, this represents a second-order

=
s= j

1
2 D

(20)

However, the term frequency-dependent negative resistance

(FDNR) has achieved universal adoption. D is in units of
(farad)2 ohms and is represented by the symbol shown in
Fig. 13.
A synthesis technique incorporating FDNRs (24) overcomes the need for floating inductor simulation in LC prototypes. If the admittances in a network are scaled by a factor
s, neither the voltage nor current transfer ratios are affected,
because they are formed from ratios of impedance or admittance parameters. However, scaling does affect the network
elements as follows:
Admittance Y(s) becomes sY(s) (transformed admittance)
Capacitor sC becomes s2C (FDNR)
Inductor 1/sL becomes 1/L (resistor)
Resistor 1/R becomes s/R (capacitor)
Inductors are thus eliminated and a new, but topologically
equivalent, network is formed.
Example 3. In this example, we realize a doubly terminated
low-pass filter having a fourth-order Butterworth characteris-

kR
ks

ks

Figure 12. GIC realization of a floating inductor.

ACTIVE FILTERS

Z=

s 2D

for which, for example, RA may be set at 100 so as to avoid

loading the capacitor.
Denormalization of the circuit is straightforward, noting
that an FDNR of normalized value Dn, is denormalized using
the expression

(a)

D=

ks2
k

(b)

ks
C

kC

(c)
Figure 13. FDNR symbol and realization. (a) Symbol for FDNR of
value D. (b) Realization of FDNR by resistively-terminated GIC. (c)
Realization of FDNR by capacitively-terminated GIC.

tic. From design tables, we obtain the LC prototype of Fig.

14(a). Transformation yields the so-called DCR network of
Fig. 14(b). If biasing problems are encountered due to the
presence of floating capacitors, they may be overcome by the
addition of shunt resistors, RA and RB, as shown in Fig. 14(c).
In order to preserve the passband loss of the original network,
these resistors are arranged to yield a dc gain of 0.5. Hence,

0.7654 H

1.8478 H
1

1.8478 F

0.7654 F
(a)

1F

0.7654

1.8478
1F

1.8478 F2

0.7654 F2
(b)

RA
0.7654

1.8478

1.8478 F2

0.7654 F2

Dn
Zn n2

(21)

The FDNR approach is most effective when all inductors

are floating. In more complex arrangements, floating FDNRs
result whenever a floating capacitor is present in the original
prototype. Since the replacement of each floating FDNR requires the use of two GICs, the alternative of partial transformation (25,26) is preferred.
The technique is illustrated in Fig. 15, for which the composite transmission matrix [a] for the three-section cascade
is given as

a12 k2

 a11
a12

1 1

k1
1 0

a11
n
(22)

k
s
[a ] =
=
1
1

0 k 2 sn
n
0

a
k
k
a
s
a
n
22
2
1
21
22
k1 s
a21
k1
Hence, for matched GICs (k1 k2), we see that [a] [a].
The technique is illustrated in Fig. 16(a)(c) for a bandpass section. Using direct FDNR realization of Fig. 16(b)
would require a total of five GICs. The partial transformation
of Fig. 16(c) reduces the requirement to three GICs. Clearly,
the savings are more dramatic for higher-order realizations.
Leapfrog Realization

RB
= 0.5
RA + 0.7654 + 1.8478
1

217

The leapfrog technique (6) was introduced over 40 years ago

and represents the first of several multiloop feedback simulation methods (2729). Its simplicity and elegance derives
from a one-to-one relationship between passive reactances in
a ladder structure and integrators in the leapfrog model.
The technique is particularly well suited to the realization
of low-pass responses, which are the most difficult to realize
by direct replacement methods. Although the presence of multiple feedback loops can render tuning difficult, the close
matching of capacitor ratios and the similarity of the active
blocks rendered this approach ideal for the realization of
switched-capacitor filters (SCF). Indeed, SCF technology revitalized interest in the leapfrog approach.
Consider the output sections of the low-pass LC filter of
Fig. 17(a). The relationships between the various voltages
and currents are shown in Eqs. 23

i1 = sC1 RV 0

(23a)

i2 = i1 + i0

(23b)

sL1
i
R 2
V3 = V2 + V0

(23d)

i3 = sC2 RV 3

(23e)

(c)

i4 = i3 + i2

(23f )

Figure 14. FDNR realization of low-pass filter. (a) LC prototype of

fourth-order Butterworth filter. (b) DCR network derived from (a). (c)
Resistive shunts added for biasing purposes.

sL2
i
V4 =
R 4
V5 = V4 + V3

V2 =

1F

RB
1F

(23c)

(23g)
(23h)

218

ACTIVE FILTERS

[a]

k1a21

Figure 15. The use of two GICs to yield an embedded network equivalence which eliminates the need
to realize floating FDNRs.

Co

Lo

L2

L1

1
2
3
4
5
6
7
8

C1

B
Ro

R2

R1

D2

B
(b)

Co

Ro

C2

R2

R1

k1sn
a22

k2sn

= sT 1 0
= 1 + 0
= sT 2 2
= 3 + 0
= sT 3 4
= 5 + 4
= sT 4 6
= 7 + 6

(24a)
(24b)
(24c)
(24d)
(24e)
(24f )
(24g)
(24h)

Thus, for every current and voltage in Eqs. (23ah), there is

a corresponding quantity i in Eqs. (24ah). Furthermore, if
corresponding factors such as C1R1 and T1, L1 /R and T2 are
set equal, the two systems have full equivalence.
As a result, LC low-pass structures may be simulated
by a straightforward process, as illustrated in Fig. 18. More
detailed discussions of this approach, including its extension
beyond the low pass are presented elsewhere (14, Ch. 10).
As an analog of a passive LC filter, the leapfrog structure
provides a low sensitivity structure, and one which is inherently stable.

D1

sn

Thus, working from output to input, we have alternating processes of differentiation and addition. Now, consider the
multifeedback integrator structure of Fig. 17(b), for which

C2

(a)

Do

a12

a11

k1sn

D1

INTEGRATED FILTERS

(c)
Figure 16. Partial transformation to eliminate floating FDNRs. (a)
LC bandpass section. (b) DCR realization of (a). (c) Partial transformation of (a) by embedding the section AABB between two GICs.

As indicated previously, the earliest active filters were fabricated using discrete components and, eventually, operational
amplifiers. The selection of high-quality capacitors and lowtolerance, high-performance resistors is crucial to the ultimate quality of the filter (20). Finally, the circuit must be
tuned by the adjustment of one or more trimmer pots.

V4
L2/ R

V2
i4

i3

i2

C2

V5

i0

L1/ R

V3

i1
C1

V0

(a)

Figure 17. Basic equivalence of LC and leapfrog

structures. (a) LC prototype. (b) Multifeedback integrator structure.

1/ sT

1/ sT

(b)

1/ sT

1/ sT

ACTIVE FILTERS

The advent of laser trimming, combined with thick and

thin film hybrid microelectronic processing, not only led to
larger-scale production but allowed for much more precise
adjustment of resistors. Coupled with numerically controlled
resistor adjustment, hybrid microelectronics fabrication led
to more widespread use of active filters. However, the quest
for ever-smaller structures, and for higher cut-off frequencies ultimately led to fully integrated filters. Several major
technical problems inhibited the fabrication of fully integrated filters:

219

Fully integrated filters have been developed using the

MOSFET-C (32) technique, which is based upon monolithic
operational amplifiers, capacitors, and MOS (metal oxide
semiconductor) transistors. The latter are biased in their
ohmic region to yield tunable resistors. The technique allows
the designer to take advantage of well-tried RC active filter
design methods but is restricted in frequency by the operational amplifiers and the nonlinear nature of the simulated
resistance.
Further limitations occur due to integrated circuit parasitics and switching noise resulting from the tuning circuitry.
These problems can be overcome by using fully balanced differential circuits so that parasitic effects appear as common
mode signals. Fully balanced circuits are usually derived from
their single-ended counterparts, and are based upon welltried structures such as those described in earlier sections. A
useful general rule (9) for converting from single-ended to a
balanced circuit is presented below:

1. The relatively low bulk resistance of silicon, which

meant that large values of resistance required an unduly large volume.
2. The relatively low dielectric constant of silicon which
resulted in excessively large capacitor plate area.
3. The inability to trim passive elements.
Active-R filters (3031) which utilize the single-pole rolloff model of an operational amplifier provide an effective capacitance for simple, high cut-off filters. However, the need to
accurately determine the roll-off properties of each amplifier
renders this approach inefficient in the absence of sophisticated on-chip self-tuning circuitry (9).
Switched-capacitor filters were the first fully-integrated
structures. Although they are strictly sampled-data systems,
they simulate an analog system if the clock frequency is much
higher than the cut-off frequency. Although a more detailed
description of SCFs is presented in SWITCHED CAPACITOR NETWORKS, two of their advantages are worthy of note at this time:

Identify ground node(s) in the single-ended circuit.

Mirror the circuit at ground, duplicating all elements,
and divide the gain of all active devices by two.
Change the sign of the gain of all mirrored active devices
and merge so that any resulting pair with inverting-noninverting gains becomes one balanced differential inputdifferential output device.
Realize any devices whose sole effect in the original circuit is a sign inversion by a simple crossing of wires.
The conversion process for a state variable filter is shown
in Fig. 19(ab), while Fig. 19(c) shows the MOSFET-C realization in which the resistors of Fig. 19(b) have been replaced
by MOSFET-simulated resistors.
By contrast, fully integrated active filters based upon the
operational transconductance amplifier (OTA) (3334) are

1. The filters are fully integrated.

2. Performance depends upon the ratio of relatively small
capacitors and an accurate clock to establish circuit
time constants with high precision.

Vi

V0

(a)

Vi

T5

T4

T3

T2

(b)
Figure 18. Leapfrog realization of low-pass LC filter. (a) Fifth-order LC filter. (b) Leapfrog realization of (a).

T1

Vo

220

ACTIVE FILTERS

R4
R2
R
R1

C1

C2

R3

Vi

+
Vo

(a)
R4
C1
R2

C2
R3

R1
V i+

R1

V i

R3

V o+
Vo

C2

R2
R4

C1
(b)

R4
R2
C1

C2

R1

R3

V i+

V i

+
R3

R1
C1

V o+
Vo

C2

R2
R4
(c)
Figure 19. Realization of MOSFET-C state variable filter. (a) Original active RC version using
single-ended amplifiers. (b) Fully differential, active-RC version. (c) MOSFET-C version with
MOSFETs R1 . . . R4 replacing equivalent resistors of (b).

ACTIVE FILTERS

gm

I0

I1
+

simpler to design and have a much wider frequency range.

This has led to OTA-C structures capable of accurate operation at frequencies beyond 100 MHz (35).
The OTA is a high-gain voltage-controlled current source,
which is relatively easy to fabricate using CMOS or complementary bipolar technology. Some basic properties of the OTA
are as follows:
1. High gain-bandwidth product that yields filters with
higher operating frequencies than those using conventional operational amplifiers.
2. Can be electronically tuned to modify its transconductance.
3. Infinite input impedance and infinite output impedance.

V1

Figure 20. Circuit symbol for the operational transconductance amplifier (OTA).

(25)

where gm is the transconductance, a typical value being 500

A/V. gm can be controlled by Ic such that:
gm = KIc

(26)

where Ic is in microamps and a typical value of K is 15. Of

particular importance, Eq. (26) is valid over a wide range,
perhaps as much as six decades for Ic, that is, 0.001 to 1000
A. In addition, the gain-bandwidth is also proportional to
Ic and may extend to hundreds of megahertz. This will be
limited by input and output parasitics.
An OTA-C filter structure depends upon the ability of the
OTA to simulate large values of resistance. Hence, in conjunction with relatively small values of capacitance, it is possible
to set the appropriate filter time constants without undue use
of silicon real estate.
Resistance can be simulated by the circuits shown in Figs.
21(a,b). For the grounded resistance,

Req

Req

(a)
I1

Req

I2

V1

V2

V1

V2

(b)
Figure 21. Resistance simulation using OTAs. (a) Grounded resistor.
(b) Floating resistor.

from which:

  
I1
gm1
=
I2
gm2

The circuit symbol for the OTA is shown in Fig. 20, for
which
I0 = gm (V + V )

I0

V+

221

gm1
gm2

 
V1
V2

(29)

For matched devices, gm1 gm2, and Eq. (29) represents a

floating resistor of value 1/gm. Various building blocks can
now be developed, forming the basis for simulation of structures such as the state variable. For example, the simple
summer shown in Fig. 22(a) yields
V0 =

gm1
g
V + m2 V
gm3 1 gm3 2

(30)

+
1

V1

V2

V0

(a)

I1 = I0 = gm (0 V ) = gmV1
+

Hence,

2
+

Req

V
1
= 1 =
I1
gm

(27)

V+

V0

Thus, if gm 105S, Req 100 k.

For the floating resistance of Fig. 21(b):
(b)

I1 = gm1 (V2 V1 )

(28a)

I2 = gm2 (V1 V2 )

(28b)

Figure 22. OTA filter building blocks. (a) Summer. (b) Damped integrator.

222

ACTIVE FILTERS

Bandpass
Low-pass

6. F. E. Girling and E. F. Good, Active filters, Wireless World, 76:

341345, 445450, 1970. The leapfrog method was first described
by the same authors in RRE Memo No. 1177, September, 1955.
7. R. A. Friedenson et al., RC active filters for the D3 channel bank
filter, Bell Syst. Tech. J., 54 (3): 507529, 1975.
8. R. W. Brodersen, P. R. Gray, and D. A. Hodges, MOS switchedcapacitor filters, Proc. IEEE, 67: 6175, 1979.
9. R. Schaumann, M. S. Ghausi, and K. R. Laker, Design of Analog
Filters, Englewood Cliffs, NJ: Prentice-Hall, 1990.
10. R. W. Daniels, Approximation Methods for Electronic Filter Design, New York: McGraw-Hill, 1974.

5. W. J. Kerwin, L. P. Huelsman, and R. W. Newcomb, State-variable synthesis for insensitive integrated circuit transfer functions, IEEE Journal, SC-2: 8792, 1967.

4
+

Figure 23. OTA circuit yielding both bandpass and low-pass secondorder transfer functions.

11. P. Bowron and F. W. Stephenson, Active Filters for Communications and Instrumentation, London: McGraw-Hill, 1979.
12. A. I. Zverev, Handbook of Filter Synthesis, New York: Wiley, 1967.
13. E. Christian and E. Eisenman, Filter Design Tables and Graphs,
New York: Wiley, 1966.

whereas the circuit of Fig. 22(b) realizes a damped integrator,

for which
V0 =

gm1
(V + V )
sC + gm2

(31)

Furthermore, by setting gm2 0 (eliminating the second OTA),

Eq. (31) reduces to that of an undamped integrator.
Other biquads, not based directly on earlier topologies,
may also be realized. For example, the biquad of Fig. 23 may
be analyzed to yield a bandpass output of

Vbp
Vi

=
s2 +

s(gm1 /C1 )

gm2
g g
s + m3 m4
C2
C1C2

(32)

SUMMARY
RC active filters have reached a degree of maturity that could
not have been envisaged when they were first conceived over
40 years ago. The successive introductions of operational amplifiers, laser trimming, hybrid microelectronic fabrication,
and, finally, fully integrated filters have all helped advance
the state of the art. However, the thread linking all of these
technological advances has been the retention of a small number of topologies and techniques that have been proven to
yield reliable filters for large-scale practical applications.
These structures have formed the basis for discussion in this
article. By no means do they represent all the possibilities,
but they do form a solid basis upon which further study may
be based.
BIBLIOGRAPHY
1. F. Jay (ed.), IEEE Standard Dictionary of Electrical and Electronic
Terms, 4th ed., New York: IEEE Press, 1988.
2. J. G. Linvill, RC active filters, Proc. IRE, 12: 555564, 1954.
3. R. P. Sallen and E. L. Key, A practical method of designing RC
active filters, IRE Trans., CT-2: 7485, 1955.
4. A. G. J. Holt and J. R. Taylor, Method of replacing ungrounded
inductances by grounded gyrators, Electron. Lett., 1 (4): 105,
1965.

14. F. W. Stephenson (ed.), RC Active Filter Design Handbook, New

York: Wiley, 1985.
15. L. P. Huelsman, Active and Passive Analog Filter DesignAn
Introduction, New York: McGraw-Hill, 1993.
16. F. W. Stephenson, Single-amplifier multiple-feedback filters, in
W-K. Chen, (ed.), The Circuits and Filters Handbook, New York:
CRC Press/IEEE Press, 1995.
17. T. Deliyannis, High-Q factor circuit with reduced sensitivity,
Electron. Lett., 4 (26): 577579, 1968.
18. J. J. Friend, C. A. Harris, and D. Hilberman, STAR: an active
biquadratic filter section, IEEE Trans. Circuits Syst., CAS-22:
115121, 1975.
19. L. P. Huelsman and P. E. Allen, Introduction to the Theory and
Design of Active Filters, New York: McGraw-Hill, 1980.
20. F. W. Stephenson and W. B. Kuhn, Higher-order filters, in J. T.
Taylor and Q. Huang (eds.), CRC Handbook of Electrical Filters,
New York: CRC Press, 1997, pp. 119139.
21. G. S. Moschytz, A second-order pole-zero pair selection for nthorder minimum sensitivity networks, IEEE Trans., CT-17 (4):
527534, 1970.
22. M. S. Ghausi and K. R. Laker, Modern Filter Design, Englewood
Cliffs, NJ: Prentice-Hall, 1981.
23. A. Antoniou, Realization of gyrators using operational amplifiers
and their use in RC-active network synthesis, Proc. IEEE, 116
(11): 18381850, 1969.
24. L. T. Bruton, Network transfer functions using the concept of
frequency-dependent negative resistance, IEEE Trans., CT-16:
406408, 1969.
25. A. W. Keen and J. L. Glover, Active RC equivalents of RCL networks by similarity transformation, Electron. Lett. 7 (11): 288
290, 1971.
26. L. T. Bruton and A. B. Haase, Sensitivity of generalized immittance converter-embedded ladder structures, IEEE Trans., CAS21 (2): 245250, 1974.
27. G. Hurtig, The primary resonator block technique of filter synthesis, Proc. IEEE International Filter Symposium, Santa Monica,
CA, April 1972, p. 84, [US Patent 3,720,881, March, 1973].
28. K. R. Laker and M. S. Ghausi, Synthesis of low-sensitivity
multiloop feedback active RC filter, IEEE Trans., CAS-21 (2):
252259, 1974.
29. J. Tow, Design and evaluation of shifted-companion form of active filters, Bell Syst. Tech. J., 54 (3): 545568, 1975.
30. J. R. Brand and R. Schaumann, Active R filters: Review of theory
and practice, IEEE J., ECS-2 (4): 89101, 1978.

ACTIVE PERCEPTION
31. A. S. Sedra and P. O. Brackett, Filter Theory and Design: Active
and Passive, Portland OR: Matrix, 1978.
32. Y. Tsividis, M. Banu, and J. Khoury, Continuous-Time MOSFETC Filters in VLSI, IEEE Trans., CAS-33: 112540, 1986.
33. Y. P. Tsividis and J. O. Voorman (eds.), Integrated ContinuousTime Filters, Piscataway, NJ: IEEE Press, 1993.
34. R. L. Geiger and E. Sanchez-Sinencio, Active filter design using
operational transconductance amplifiers: A tutorial, IEEE Circ.
Dev. Mag., CDM-1: 2032, 1985.
35. M. Atarodi and J. Choma, Jr., A 7.2 GHz bipolar operational
transconductance amplifier for fully integrated OTA-C filters, J.
Analog Integ. Circ. Signal Process., 6 (3): 243253, 1994.

F. WILLIAM STEPHENSON
Virginia Polytechnic Institute and
State University

ACTIVE FILTERS. See ANALOG FILTERS; CASCADE NETWORKS.

ACTIVE NETWORK SYNTHESIS. See CURRENT CONVEYORS.

223

ADAPTIVE FILTERS

Now consider the expectation of Eq. (37):

For stable convergence each term in Eq. (45) must be less

than one, so we must have

w (n + 1)] = E[w
w (n)] + 2E[d(n)xx(n)]
E[w

(38)

w (n)]
2E[xx (n)xx (n)T ]E[w

We have assumed that the lter weights are uncorrelated

with the input signal. This is not strictly satised, because
the weights depend on x(n); but we can assume that has
small values because it is associated with a slow trajectory.
So, subtracting the optimum solution from both sides of Eq.
(38), and substituting the autocorrelation matrix R and crosscorrelation vector p, we get

0<<

Next, dening
w (n + 1)] R1 p
(n + 1) = E[w

(40)

from Eq. (39) we obtain

(n + 1) = (I 2R) (n)

(41)

This process is equivalent to translation of coordinates. Next,

we dene R in terms of an orthogonal transformation (7):
R = K T QK

max

(46)

max/min

(47)

So, from the point of view of convergence speed, the ideal

value of the eigenvalue spread is unity; the larger the value,
the slower will be the nal convergence. It can be shown (3)
that the eigenvalues of the autocorrelation matrix are
bounded by the maximum and minimum values of the power
spectral density of the input.
It is therefore concluded that the optimum signal for fastest convergence of the LMS algorithm is white noise, and that
any form of coloring in the signal will increase the convergence time. This dependence of convergence on the spectral
characteristics of the input signal is a major problem with the
LMS algorithm, as discussed in Ref. 6.

(42)

where Q is a diagonal matrix consisting of the eigenvalues

(0, 1, . . ., N) of the correlation matrix R, and K is the unitary matrix consisting of the eigenvectors associated with
these eigenvalues.
Substituting Eq. (42) in Eq. (41), we have

(n + 1) = (I 2K T QK) (n)

(43)

= K T (I 2Q)K (n)
Multiplying both sides of the Eq. (43) by K and dening
v (n + 1) = K (n + 1)

LMS-Based Algorithms
The Normalized LMS Algorithm. The normalized LMS
(NLMS) algorithm is a variation of the ordinary LMS algorithm. Its objective is to overcome the gradient noise amplication problem. This problem is due to the fact that in the
standard LMS, the correction e(n)x(n) is directly proportional to the input vector x(n). Therefore, when x(n) is large,
the LMS algorithm amplies the noise.
Consider the LMS algorithm dened by
w (n + 1) = w (n) + 2e(n)xx (n)

(44)

v (n)
= (I 2Q)v
we may rewrite Eq. (44) in matrix form as

(48)

Now consider the difference between the optimum vector w*

and the current weight vector w(n):
v (n) = w w (n)

v0 (n)
v (n)

..

.
vN1 (n)

(1 21 )n

where max is the largest eigenvalue of the correlation matrix

R, though this is not a sufcient condition for stability under
all signal conditions. The nal convergence rate of the algorithm is determined by the value of the smallest eigenvalue.
An important characteristic of the input signal is therefore
the eigenvalue spread or disparity, dened as

w (n + 1)] R1 p = E[w
w (n)] R1 p + 2R{R1 p E[w
w (n)]}
E[w
(39)

259

(49)

Assume that the reference signal and the error signal are

(1 22 )n
..
.

(1 2N )n

v0 (0)
v (0)

..

.
vN1 (0)

d(n) = w Tx (n)

(50)

e(n) = d(n) w (n)Tx (n)

(51)

Substituting Eq. (50) in Eq. (51), we obtain

e(n) = w Tx (n) w (n)Tx (n)

w T w (n)T ]xx (n)
= [w

(52)

= v (n)xx (n)
T

(45)

We decompose v(n) into its rectangular components

v (n) = v o (n) + v p (n)

(53)

260

ADAPTIVE FILTERS

Therefore, the NLMS algorithm given by Eq. (64) is equivalent to the LMS algorithm if

vp(n1)
vp(n)

2 =
vp(n)

NLMS Algorithm

Parameters :
where vo(n) and vp(n) are the orthogonal component and the
parallel component of v(n) with respect to the input vector.
This implies
v p (n) = Cxx (n)

Initialization :
Computation :

(54)

where C is a constant. Then substituting Eq. (53) and Eq. (54)

in Eq. (52), we get
v o (n) + v p (n)]Tx (n)
e(n) = [v

(55)

v o (n) + Cxx (n)]Tx (n)

e(n) = [v

(56)

Because vo(n) is orthogonal to x(n), the scalar multiplication

is
v Tox (n) = 0

(57)

Then solving for C from Eqs. (56) and (57) yields

e(n)
x T (n)xx (n)

(58)

and
v p (n) =

e(n)xx (n)
x T (n)xx (n)

(59)

The target now is to make v(n) as orthogonal as possible to

x(n) in each iteration, as shown in Fig. 13. The above mentioned can be done by setting
v p (n)
v (n + 1) = v (n) v

(60)

Finally, substituting Eq. (49) and Eq. (59), we get

w w (n + 1) = w w (n)
w (n + 1) = w (n) +

(66)

x(n)

vp(n)

Figure 13. Geometric interpretation of the NLMS algorithm.

C=

x T (n)xx (n)

e(n)xx (n)
x T (n)xx (n)

e(n)xx (n)
x T (n)xx (n)

(61)

w (n + 1) = w (n) + e(n)xx (n)

Time-Variant LMS Algorithms. In the classical LMS algorithm there is a tradeoff between validity of the nal solution
and convergence speed. Therefore its use is limited for several
practical applications, because a small error in the coefcient
vector requires a small convergence factor, whereas a high
convergence rate requires a large convergence factor.
The search for an optimal solution to the problem of obtaining high convergence rate and small error in the nal
solution has been an arduous in recent years. Various algorithms have been reported in which time-variable convergence coefcients are used. These coefcients are chosen so
as to meet both requirements: high convergence rate and low
MSE. Interested readers may refer to Refs. 914.
Recursive Least-Squares Algorithm
The recursive least-squares (RLS) algorithm is required for
rapidly tracking adaptive lters when neither the referencesignal nor the input-signal characteristics can be controlled.
An important feature of the RLS algorithm is that it utilizes
information contained in the input data, extending back to
the instant of time when the algorithm is initiated. The resulting convergence is therefore typically an order of magnitude faster than for the ordinary LMS algorithm.
In this algorithm the mean squared value of the error signal is directly minimized by a matrix inversion. Consider the
FIR lter output

(62)

where, in order to reach the target, must satisfy (9)

0<<2

(63)

w (n + 1) = w (n) + e(n)xx (n)

(64)

M = lter order
= step size
Set w (0) = 0
For n = 0, 1, 2, . . ., compute
y(n) = w (n)Tx (n)
e(n) = d(n) y(n)

= T
x (n)xx (n)

y(n) = w Tx (n)

(67)

where x(n) is the input vector given by x(n) [x(n), x(n 1,

. . ., x(n M 1)]T and w is the weight vector. The optimum
weight vector is computed in such a way that the mean
squared error, E[e2(n)] is minimized, where

In this way
e(n) = d(n) y(n) = d(n) w Tx (n)

(68)

E[e (n)] = E[{d(n) w x (n)} ]

(69)

where

= T
x (n)xx (n)

(65)

To minimize E[e2(n)], we can use the orthogonality principle

in the estimation of the minimum. That is, we select the
weight vector in such a way that the output error is orthogo-

ADAPTIVE FILTERS

nal to the input vector. Then from Eqs. (67) and (68), we obtain

Next, for convenience of computation, let

Q(n) = R1 (n)

w}] = 0
E[xx (n){d(n) x (n)w
T

261

(82)

(70)
and

Then
w] = E[d(n)xx (n)]
E[xx (n)xxT (n)w

K(n) =

(71)

Assuming that the weight vector is not correlated with the

input vector, we obtain
w = E[d(n)xx (n)]
E[xx (n)xxT (n)]w

p (n) =

n


nk d(k)xx (k)

w (n) =

(73)

p (n 1) +
w (n) = Q(n 1)p

(74)

k=0

p (n) =

n1


nk d(k)xx (k) + d(n)xx (n)

k=0

n1


(75)

nk1

d(k)xx (k) + d(n)xx (n)

R(n) = R(n 1) + x (n)xx T (n)

(85)

1
d(n)K(n)xxT (n)Q(n 1)xx (n)

1
w (n) = w (n 1) + d(n)Q(n 1)xx (n)

w (n 1)
Q(n 1)xx (n)xxT (n)w

+ x T (n)Q(n 1)xx (n)

1 d(n)Q(n 1)xx (n)xxT (n)Q(n 1)xx (n)

+ x T (n)Q(n 1)xx (n)

(86)

Q(n 1)xx (n)

1
+ x T (n)Q(n 1)xx (n)
[d(n) + d(n)xxT (n)Q(n 1)xx (n)

w (n) = w (n 1) +

(87)

w (n 1) d(n)xxT (n)Q(n 1)xx (n)]

xxT (n)w

(76)

where is the forgetting factor. In a similar way, we can obtain

(84)

1
d(n)Q(n 1)xx (n)

p (n 1)
K(n)xx T (n)Q(n 1)p

k=0

p (n 1) + d(n)xx(n)
p (n) = p

1
[Q(n 1) K(n)xx T (n)Q(n 1)]

p (n 1) + d(n)xx(n)]
[p

(72)

where R and p are the autocorrelation matrix of the input

signal and the correlation vector between the reference signal d(n) and input signal x(n), respectively. Next, assuming
ergodicity, p can be estimated in real time as

(83)

Then from Eq. (81) we have

which can be rewritten as

w=p
Rw

R1 (n 1)xx (n)
+ x T (n)R1 (n 1)xx (n)

Q(n 1)xx (n)

1
+ x T (n)Q(n 1)xx (n)
w(n 1)]
[d(n) x T (n)w

w (n) = w (n 1) +

(88)

(77)
Finally, we have

Then, multiplying Eq. (73) by R1 and substituting Eq. (76)

and Eq. (77), we get
p (n 1) + d(n)xx (n)]
w = [R(n 1) + x (n)xxT (n)]1 [p

(78)

w (n) = w (n 1) + K(n)(n)
where

Next, according to the matrix inversion lemma

(A + BCD)

=A

B(DA

B +C

1 1

K(n) =
DA

1 1
R (n 1)

1 1
R (n 1)xx (n)

1 T
x (n)R1 (n 1)xx (n) + 1

1 1

(n) = d(n) w T (n 1)xx (n)

x T (n)R1 (n 1)

(91)

Then Eq. (89) can be written as

w (n) = w (n 1) + Q(n)(n)xx(n)

(n 1)

1
R (n 1)xx (n)xx (n)R
w (n) =
R1 (n 1)

[ + x T (n)R1 (n 1)xx (n)]

p (n 1) + d(n)xx(n)]
[p
xT

(90)

and (n) is the a priori estimation error, based on the old

least-square estimate of the weights vector that was made at
time n 1, and dened by

p (n 1) + d(n)xx (n)]
[p
1

Q(n 1)xx (n)

+ x T (n)Q(n 1)xx (n)

(79)

with A R(n 1), B x(n), C 1, and D xT(n), we

obtain

w (n) =

(89)

(80)

(81)

(92)

where Q(n) is given by

Q(n) =

Q(n 1)

Q(n 1)xxT (n)Q(n 1)

+ x T (n)Q(n 1)xx (n)

(93)

262

ADAPTIVE FILTERS
3. S. Haykin, Adaptive Filter Theory, 3rd ed., Upper Saddle River,
NJ: Prentice-Hall, 1996.

The applicability of the RLS algorithm requires that it initialize the recursion of Q(n) by choosing a starting value
Q(0) to ensure the nonsingularity of the correlation matrix
R(n) (3).

4. B. Friedlander, Lattice lters for adaptive processing, Proc.

IEEE, 70: 829867, 1982.

RLS Algorithm

5. J. J. Shynk, Adaptive IIR ltering, IEEE ASSP Mag., 6 (2): 4

21, 1989.

Initialization :
Computation :

Set Q(0)
w (0) = 0
For n = 1, 2, . . ., compute
K(n) =

Q(n 1)xx (n)

+ x T (n)Q(n 1)xx (n)

(n) = d(n) w T (n 1)xx (n)

w (n) = w (n 1) + K(n)(n)
w (n + 1) = w (n) + e(n)xx (n)
Q(n) = R1 (n)
IMPLEMENTATIONS OF ADAPTIVE FILTERS
In the last few years many adaptive lter architectures have
been proposed, for reducing the convergence rate without increasing the computational cost signicantly. The digital implementations of adaptive lters are the most widely used.
They yield good performance in terms of adaptivity, but consume considerable area and power. Several implementations
achieve power reduction by dynamically minimizing the order
of the digital lter (15) or employing parallelism and pipelining (16). On the other hand, high-speed and low-power applications require both parallelism and reduced complexity (17).
Is well known that analog lters offer advantages of small
area, low power, and higher-frequency operation over their
digital counterparts, because analog signal-processing operations are normally much more efcient than digital ones.
Moreover, since continuous-time adaptive lters do not need
analog-to-digital conversion, it is possible to prevent quantization-related problems.
Gradient descent adaptive learning algorithms are commonly used for analog adaptive learning circuits because of
their simplicity of implementation. The LMS algorithm is often used to implement adaptive circuits. The basic elements
used for implementing the LMS algorithm are delay elements
(which are implemented with all-pass rst-order sections),
multipliers (based on a square law), and integrators. The
techniques utilized to implement these circuits are discretetime approaches, as discussed in Refs. 18 to 21, and continuous-time implementations (22,23,24).
Several proposed techniques involve the implementation of
the RLS algorithm, which is known to have very low sensitivity to additive noise. However, a direct analog implementation of the RLS algorithm would require a considerable effort.
To overcome this problem, several techniques have been proposed, such as structures based on Hopeld neural networks
(23,25,26,27).
BIBLIOGRAPHY
1. S. U. H. Qureshi, Adaptive equalization, Proc. IEEE, 73: 1349
1387, 1985.
2. J. Makhoul, Linear prediction: A tutorial review, Proc. IEEE, 63:
561580, 1975.

6. P. Hughes, S. F. A. Ip, and J. Cook, Adaptive ltersa review of

techniques, BT Technol. J., 10 (1): 2848, 1992.
7. B. Widrow and S. Stern, Adaptive Signal Processing, Englewood
Cliffs, NJ: Prentice-Hall, 1985.
8. B. Widrow and M. E. Hoff, Jr., Adaptive switching circuits, IRE
WESCON Conv. Rec., part 4, 1960, pp. 96104.
9. J. Nagumo and A. Noda, A learning method for system identication, IEEE Trans. Autom. Control, AC-12: 282287, 1967.
10. R. H. Kwong and E. W. Johnston, A variable step size LMS algorithm, IEEE Trans. Signal Process., 40: 16331642, 1992.
11. I. Nakanishi and Y. Fukui, A new adaptive convergence factor
with constant damping parameter, IEICE Trans. Fundam. Electron. Commun. Comput. Sci., E78-A (6): 649655, 1995.
12. T. Aboulnasr and K. Mayas, A robust variable step size LMStype algorithm: Analysis and simulations, IEEE Trans. Signal
Process., 45: 631639, 1997.
13. F. Casco et al., A variable step size (VSS-CC) NLMS algorithm,
IEICE Trans. Fundam., E78-A (8): 10041009, 1995.
14. M. Nakano et al., A time varying step size normalized LMS algorithm for adaptive echo canceler structures, IEICE Trans. Fundam., E78-A (2): 254258, 1995.
15. J. T. Ludwig, S. H. Nawab, and A. P. Chandrakasan, Low-power
digital ltering using approximate processing, IEEE J. Solid
State Circuits, 31: 395400, 1996.
16. C. S. H. Wong et al., A 50 MHz eight-tap adaptive equalizer for
partial-response channels, IEEE J. Solid State Circuits, 30: 228
234, 1995.
17. R. A. Hawley et al., Design techniques for silicon compiler implementations of high-speed FIR digital lters, IEEE J. Solid State
Circuits, 31: 656667, 1996.
18. M. H. White et al., Charge-coupled device (CCD) adaptive discrete analog signal processing, IEEE J. Solid State Circuits, 14:
132147, 1979.
19. T. Enomoto et al., Monolithic analog adaptive equalizer integrated circuit for wide-band digital communications networks,
IEEE J. Solid State Circuits, 17: 10451054, 1982.
20. F. J. Kub and E. W. Justh, Analog CMOS implementation of high
frequency least-mean square error learning circuit, IEEE J. Solid
State Circuits, 30: 13911398, 1995.
21. Y. L. Cheung and A. Buchwald, A sampled-data switched-current
analog 16-tap FIR lter with digitally programmable coefcients
in 0.8 m CMOS, Int. Solid-State Circuits Conf., February 1997.
22. J. Ramirez-Angulo and A. Daz-Sanchez, Low voltage programmable FIR lters using voltage follower and analog multipliers,
Proc. IEEE Int. Symp. Circuits Syst., Chicago, May 1993.
23. G. Espinosa F.-V. et al., Ecualizador adaptivo BiCMOS de tiempo
continuo, utilizando una red neuronal de Hopeld, CONIELECOMP97, UDLA, Puebla, Mexico, 1997.
24. L. Ortz-Balbuena et al., A continuous time adaptive lter structure, IEEE Int. Conf. Acoust., Speech Signal Process., Detroit,
1995, pp. 10611064.
25. M. Nakano et al., A continuous time equalizer structure using
Hopeld neural networks, Proc. IASTED Int. Conf. Signal Image
Process., Orlando, FL, November 1996, pp. 168172.
26. G. Espinosa F.-V., A. Daz-Mendez, and F. Maloberti, A 3.3 V
CMOS equalizer using Hopeld neural network, 4th IEEE Int.
Conf. Electron., Circuits, Syst., ICECS97, Cairo, 1997.

ADAPTIVE RADAR
27. M. Nakano-Miyatake and H. Perez-Meana, Analog adaptive ltering based on a modied Hopeld network, IEICE Trans. Fundam., E80-A: 22452252, 1997.
Reading List
M. L. Honig and D. G. Messerschmitt, Adaptive Filters: Structures,
Algorithms, and Applications, Norwell, MA: Kluwer, 1988.
B. Mulgrew and C. F. N. Cowan, Adaptive Filters and Equalisers,
Norwell, MA: Kluwer, 1988.
S. Proakis et al., Advanced Signal Processing, Singapore: Macmillan.

GUILLERMO ESPINOSA FLORES

VERDAD
JOSE ALEJANDRO DIAZ MENDEZ
National Institute for Research in
Astrophysics, Optics and
Electronics

263

ALL-PASS FILTERS
NETWORKS, ALL-PASS
FILTERS, ALL-PASS
PHASE EQUALIZERS
All-pass lters are often included in the catalog of classical
lter types. A listing of types of classical lters reads as
follows: low-pass, high-pass, bandpass, band-stop, and allpass lters. The transfer functions (see Transfer functions) of all of these lters can be expressed as real, rational functions of the Laplace transform variable s (see
Laplace transforms). That is, these transfer functions
can be expressed as the ratio of two polynomials in s which
have real coefcients. All of the types of lters listed have
frequency-selective magnitude characteristics except for
the all-pass lter. That is, in the sinusoidal steady state,
a low-pass lter passes low-frequency sinusoids relatively
well and attenuates high-frequency sinusoids. Similarly, a
bandpass lter in sinusoidal steady state passes sinusoids
having frequencies that are within the lters passband
relatively well and attenuates sinusoids having frequencies lying outside this band. It should be kept in mind that
all of the lters on the list modify the phase of applied
sinusoids (see Filtering theory). Figure 1 shows idealized
representations of the magnitude characteristics of classical lters for comparison.
However, the all-pass lter is the only lter on the list
having a magnitude characteristic that is not frequency
selective; in the sinusoidal steady state, an all-pass lter
passes sinusoids having any frequency. The lter does not
change the amplitude of the input sinusoid or it changes
the amplitudes of input sinusoids by the same amount no
matter the frequency. An all-pass lter modies only the
phase, and this is the property that is found useful in signal
processing.
Only the transfer function of the all-pass lter, expressed as a rational function of s must have zeros (loss
poles) in the right-half s plane (RHP). The poles and zeros
of the transfer function are mirror images with respect to
the origin. The transfer functions of the other lters are
usually minimum phase transfer functions, meaning that
the zeros of these transfer functions are located in the lefthalf s plane (LHP) or on the imaginary axis but not in the
open RHP. As a result of these properties, the transfer function of an all-pass lter, TAP (s), can be expressed as a gain
factor H times a ratio of polynomials in which the numerator polynomial can be constructed from the denominator
polynomial by replacing s by s thereby creating zeros that
are images of the poles. H can be positive or negative.
The primary application of all-pass lters is in phase
equalization of lters having frequency-selective magnitude characteristics. A frequency-selective lter usually realizes an optimum approximation to ideal magnitude characteristics. For example, a Butterworth low-pass lter ap-

proximates the ideal brick-wall low-pass magnitude characteristic [see Fig. 1(a)] in a maximally at manner. An
ideal lter also has linear phase in the passband in order
to avoid phase distortion. But the Butterworth lter does
not have linear phase. So an all-pass lter is designed to
be connected in cascade with the Butterworth lter in order to linearize its phase characteristic. This application is
discussed in greater detail later in this article.
Another application of all-pass lters is creation of delay
for a variety of signal-processing tasks. A signal-processing
system may have several branches, and, depending on the
application, it may be important to make the delay in each
branch approximately equal. This can be done with allpass lters. On the other hand, a signal processing task
may require delaying one signal relative to another. Again,
an all-pass lter can be used to provide the delay. This
application is also discussed in greater detail in this article.
PROPERTIES OF ALL-PASS FILTERS
The transfer function of an all-pass lter, TAP (s), has the
form

where the constant H is the gain factor, which can be positive or negative, and D(s) is a real polynomial of s. Thus, a
rst-order all-pass lter transfer function, denoted by TAP1 ,
with a pole on the negative real axis at s = a is given by

and a second-order transfer function, denoted as TAP2 , with

complex poles described by undamped natural frequency
(or natural mode frequency) 0 and Q ( < Q < for
complex poles in the open LHP) is given by

Of course, an all-pass transfer function can be created that

has two real-axis poles as would be obtained by cascading two buffered rst-order transfer functions, but all-pass
transfer functions with complex poles are the most useful
for phase equalization of lters.
To show that the magnitude characteristic is constant
for all frequencies for all-pass transfer functions of any order, we rst obtain from Eq. (1)

where indicates the conjugate. Then from Eq. (4), we obtain

This result is also shown graphically in Fig. 2 for the case

of a second-order all-pass transfer function with complex
poles. An arbitrary point P has been selected on the j axis,
and we see that the lengths of the vectors from the poles to

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Phase Equalizers

Figure 1. Idealized magnitude characteristics of classical lters. (a) Low-pass lter. (b) High-pass
lter. (c) Bandpass lter. (d) Band-stop lter. (e) All-pass lter.

Figure 2. A pole-zero plot for a second-order all-pass transfer

function with complex poles is shown. An arbitrary point on the
j axis, denoted as P, has been selected. The lengths of the vectors
from the poles to point P are the same as the corresponding lengths
of the vectors from the zeros to point P

the point are the same as the lengths of the vectors from
the zeros to point P. Thus, the magnitude characteristic is
determined only by H and is not a function of frequency.
The phase, however, is a function of frequency. Denoting
the phase of the all-pass transfer function as AP , selecting
H to be positive for convenience, and denoting the phase of
D(j) as D , we can write:

The all-pass transfer function produces phase lag, see 1.

If H is negative, then an additional phase of radians is
introduced. Figure 3 shows the phase plots obtained for
the rst-order transfer function in Eq. (2) with a = 1 and

Figure 3. Phase plots for the rst-order all-pass transfer function of Eq. (2) with a zero at s = 1 and for second-order transfer
functions of Eq. (3) with 0 = 1 and Q = , 1, 2, and 4. H is positive
for all the transfer functions.

for the second-order transfer function in Eq. (3) with 0 =

1 and Q values equal to , 1, 2, and 4. H is positive for
all the transfer functions. Upon examination of the plots
generated by the second-order transfer functions, it is seen
that for Q = , there is no point of inection. For certain
higher values of Q, there is a point of inection. The point
of inection is obtained by differentiating the expression
for phase two times with respect to , equating the result
to zero, and solving for a positive . The result is

Thus, for Qs greater than 0.578, there is a point of inection

in the phase plot.
The negative of the derivative of phase with respect to
is the group delay, denoted as (). Group delay is also

Phase Equalizers

termed envelope delay or merely delay, and its units are

seconds. Oftentimes, designers prefer working with delay
rather than phase because delay can be expressed as a rational function of . The expression for phase involves a
transcendental function tan1 ( ). For example, the phase
of the second-order transfer function with positive H, 0 =
1 and Q = 2 (see Eq. 3) is

Rewriting Eq. (11), we obtain

where it is seen that each sinusoid in vo (t) is delayed by the

same amount, namely k seconds. The output voltage has
been delayed by k seconds, but there is no phase distortion.
However, suppose the phase of the system is given by =
k3 , a nonlinear phase characteristic. With the input signal given by Eq. (10) and, as before, assuming that |T(j)|
= |T(2j)| = 1, we obtain

However, the delay is given by

which is a rational function of resulting from the derivative of the arctangent function. Figure 4 depicts the delays corresponding to the phase plots given in Fig. 3. For
Q greater than 0.578, the plots of delay exhibit peaks. For
Q2 > , the peaks occur at
0 = 1.

From Eq. (13), it is seen that the sinusoids are delayed by

different amounts of time. The nonlinear phase characteristic has resulted in phase distortion. Although the human
ear is relatively insensitive to phase changes (3), applications such as control and instrumentation can be greatly
impaired by phase distortion. To illustrate this important
point further, assume that a signal vi (t) is applied to three
different hypothetical ampliers. The signal vi (t) is composed of two sinusoids and is given by

PHASE DISTORTION
At steady state, a linear, time-invariant network affects
only the amplitude and phase of an applied sinusoid to
produce an output sinusoid. The output sinusoid has the
same frequency as the input sinusoid. If the input signal is composed of two sine waves of different frequencies,
then, depending on the network, the output signal could
be changed in amplitude or in phase or both. For example, suppose the network is a low-pass lter and that the
input signal consists of two sinusoids with different frequencies, but both frequencies lie within the passband. In
this case, the network should pass the signal to the output with minimum distortion. Since the frequencies of the
sine waves that make up the input signal lie within the
passband, very little amplitude distortion is encountered.
However, the result can be severely phase distorted. If no
phase distortion is to be produced, then the phase characteristic in the passband of the network must be linear and,
hence, have the form k + 0 , where k is the magnitude of
the slope of the phase characteristic and 0 is the phase at
= 0. Furthermore, if 0 is neither 0 nor a multiple of 2
radians, then a distortion known as phase-intercept distortion results. In the following, phase-intercept distortion is
not considered. The interested reader is referred to Ref. 2
for further information on phase-intercept distortion.
To illustrate the effects that a system with linear phase
has on an input signal, let an input signal v(t), given by

One sinusoid has twice the frequency of the other sinusoid.

One amplier is perfectly ideal and has a gain G1 = 10 with
no phase shift. The second amplier has a gain magnitude
equal to 10 and has a linear phase shift given by = .
Thus, its transfer function can be expressed as

The third amplier also has a gain magnitude equal to 10,

but it has a nonlinear phase characteristic given by =
3 . Thus, its transfer function is given by

Figure 5 depicts the output of the rst amplier. Since

the amplier is perfectly ideal, the output is exactly 10vi .
Figure 6 shows the output of the second amplier, and it is
seen that the waveform at the output of the amplier with
linear phase is the same as shown in Fig. 5 except that the
waveform in Fig. 6 has been delayed by 1 s. Delay of the
entire waveform does not constitute phase distortion. On
the other hand, the output of the amplier with nonlinear
phase, shown in Fig. 7, is clearly distorted. For example, its
peak-to-peak value is more than 12% larger than it should
be. In the next section, we examine the use of a secondorder all-pass lter to linearize the phase of nth-order lowpass lters.
PHASE EQUALIZATON

be applied to a network with transfer function T(s). Assume

the phase of the system is given by () = k, where k is
a positive constant, and assume that |T(j)| = |T(2j)| =
1. In Eq. (10), A1 and A2 are the peak amplitudes of the
two sinusoids that make up v(t). The output signal can be
written as

Phase equalization is the term used to describe compensation employed with a lter or a system to remedy phase
distortion. The goal is to achieve linear phase (at time
delay), and the compensator is labeled a phase equalizer.
In this section, we derive the specications for a secondorder all-pass lter that can be used to linearize the phase
of most all-pole low-pass lters. The technique can also be

Phase Equalizers

Figure 4. Delay plots for the all-pass transfer

functions listed in Fig. 3. The plot for Q = has
the largest delay near the origin.

Figure 5. Output voltage of perfectly ideal

amplier with input voltage given by Eq. (14).
The amplier has a gain equal to 10 with no
phase shift.

Figure 6. Output voltage of amplier with linear phase characteristic. The output voltage is
delayed 1 s in comparison to the output voltage
shown in Fig. 5.

Phase Equalizers

Figure 7. Output voltage of amplier with nonlinear phase characteristic with input voltage
given by Eq. (14). The effects of phase distortion
are easily seen when this waveform is compared
with those in Figs. 5 and 6.

Figure 8. Cascade connection of a second-order low-pass lter

with a second-order all-pass lter. It is assumed there is no loading
between the two lters.

The use of a program that is capable of performing symbolic

algebra is recommended to obtain the Maclaurin series for
L . The results are

extended to other phase-equalization tasks. We begin the

derivation by linearizing the phase of a second-order lowpass lter having a transfer function given by
Equation (20) can be used also to write the series for the
phase of the all-pass lter directly. Then, forming = L +
A and truncating the results after the term containing 7
we obtain
Figure 8 depicts the cascade connection of this low-pass
lter with a second-order all-pass lter with transfer function TAP (s). The form of the transfer function of the all-pass
lter is given by Eq. (3), but for the purposes of this derivation, let us designate its undamped natural frequency as
A and its Q as QA . The overall phase of the cascade circuit is () = L () + A () where L and A are the phase
contributed by the low-pass lter and the all-pass lter, respectively. We wish to make () approximate linear phase
in the Maclaurin sense (1). Since is an odd function of ,
the Maclaurin series for has the form

where K1 is the rst derivative of () with respect to with

the result evaluated at = 0, and K3 is proportional to the
third derivative evaluated at = 0, and so on. Therefore, we
want to choose A and QA to make K3 and K5 equal to zero
in Eq. (18). Then K7 7 will be the lowest order undesired
term in the series for ().
The phase L contributed by the second-order low-pass
lter can be expressed as

The next step is to set the coefcients of 3 and 5 equal to

zero in Eq. (21). Thus, we must satisfy the equations

Introduce parameters a and b to represent the left sides of

Eqs. 22a and 22b, respectively. That is, let

Phase Equalizers

Thus, we have two equations, Eqs. 22a and 22b, that involve
a, b, QA , and A . Upon eliminating A , we obtain a twelfthorder equation for QA given by

is given by

k is positive, and TE (s) is the remaining portion of the overall transfer function and is of even order. We have assumed
that the odd order of To (s) arises because of the existence
of one real axis pole, the usual case. All other poles of To (s)
occur in complex conjugate pairs. Denoting the phase of
T1 (j) as 1 (), we write
where

For a given second-order low-pass transfer function, d can

be found from Eqs. 23a, and 23b. Then a positive solution
for QA is sought from Equation (24). Finally, A is obtained
from

If we consider the case of linearizing the phase given in

Eq. (30) with a second-order all-pass transfer function, we
obtain

and the terms given in Eq. (31) are added to the expressions
for the parameters a and b for higher order odd transfer
functions.
Note that a positive result must be found both for QA from
Eq. (24) and for A from Eq. (26) in order to obtain a solution.
Although only a second-order low-pass lter transfer
function was utilized to derive Eqs. 24 and 26, these two
equations are used for the nth order all-pole case as well
because only the parameters a, b, and d need to be modied. For example, suppose we wish to linearize the phase
of a normalized fourth-order Butterworth lter, denoted as
B4 (s), with a second-order all-pass lter. The transfer function B4 (s) is given by

where 1 = 2 = 1, Q1 = 0.541196, and Q2 = 1.306563. The

parameters a and b become

Calculating d from Eq. (25) and employing Eqs. 24 and 26,

we obtain QA = 0.5434 and A = 1.0955. If the normalized
Butterworth transfer function is to be frequency scaled to
a practical frequency, then the all-pass transfer function
must be frequency scaled by the same amount.
Phase equalization has been applied only to transfer
functions of even order in the derivation and the example.
To apply phase equalization to an odd-order lter, we must
determine the additional factor to add to each parameter a
and b. An odd-order, all-pole, low-pass lter transfer function To (s) can be expressed as To (s) = T1 (s)TE (s) where T1 (s)

Table 1 provides the values for QA and A needed to

linearize the phase of low-pass Butterworth lters with a
3.01-dB variation in the passband and the phase of 1-dB
ripple Chebyshev low-pass lters. Note that no solution
exists for the second-order Butterworth lter. As an application of Table 1, we nd the step responses of two normalized fth-order Butterworth lters. One lter has a secondorder all-pass connected in cascade in order to linearize its
phase, and the other does not. The transfer function B5 (s)
is given by

In Fig. 9, the step response of B5 (s) has less delay, and the
step response of B5 (s)TAP2 (s) with QA and A obtained from

Phase Equalizers

Figure 10. Essential components of a slope-polarity detector.

Figure 9. Step responses of fth-order Butterworth low-pass lters with and without phase equalization. The step response of the
lter with phase equalization exhibits preshoot and has greater
delay.

Table 1 has greater delay due to the presence of the all-pass

lter. However, it is seen from Fig. 9 that the response for
the phase-equalized lter more nearly approximates the
step response of an ideal low-pass lter with delay because
the response of an ideal lter should begin ringing before it
rises to the upper amplitude level. In other words, it should
exhibit preshoot.
Oftentimes, the design of lters having frequencyselective magnitude characteristics other than low-pass is
accomplished by applying Cauer transformations to a lowpass prototype transfer function. Unfortunately, the Cauer
transformations do not preserve the phase characteristics
of the low-pass transfer function. Thus, if a Cauer low-pass
to bandpass transformation is applied to a low-pass lter
transfer function that has approximately linear phase, the
resulting bandpass lter transfer function cannot be expected to have linear phase, especially if the bandwidth of
the bandpass lter is relatively wide. An approach to linearizing the phase of lters other than low-pass lters is to
make use of a computer program that plots delay resulting
from the cascading of a specied magnitude-selective lter
with one or more all-pass lters. Using Eq. (7) and Figure
4 as guides, the peaks of the time delays of the all-pass lters can be placed to achieve approximately linear overall
phase.
AN APPLICATION OF DELAY
An all-pass lter can be combined with a comparator to obtain a slope-polarity detector circuit (4). The basic arrangement of the all-pass lter and the comparator is shown in
Fig. 10. An LM311 comparator works well in this circuit,
and a rst-order all-pass lter can be used for input signals
that are composed of sinusoids that do not differ greatly in
frequency. To understand the behavior of this circuit, suppose vi (t) = Asin(t), where A is positive and represents the
peak value of the sine wave. The output voltage of the allpass lter is vA (t) = Asin(t-t1 ), where t1 is the delay in
seconds caused by the lter. Figure 11 depicts vi (t), vA (t),
and the output voltage of the comparator vo (t), for A = 4 V
and = 2(100) rad/s. The output terminal of the comparator has a pull-up resistor connected to 5 V. Ideally, when the

slope of vi (t) is positive, vo (t) is high, and vo (t) is low when

the slope of vi (t) is negative. Actually, the circuits output
changes state at a time which is slightly past the time at
which vi (t) changes slope. It is at this later time that the
delayed input to the comparator, vA (t), causes the polarity
of the voltage (vi (t) vA (t)) between the leads of the comparator to change. The need for an all-pass lter in this
application is clear because the amplitude of the input signal must not be changed by the delaying circuit no matter
the frequencies present in the input signal. A rst-order
all-pass lter is ordinarily adequate for the task. The pole
and zero can be set far from the origin, and their placement
is not overly critical. Too little delay results in insufcient
overdrive for the comparator. Too much delay increases the
error in the time at which the comparator changes state because the polarity of the voltage between the leads of the
comparator does not change soon enough after the slope
of vi (t) changes. For the example illustrated in Fig. 11 involving a simple sine wave, the amplitudes of the input
and delayed sine waves are equal at a time closest to zero
denoted by tE and given by

The voltage difference, denoted as VE , between the peak of

the input sine wave and the level at which the input and
delayed sine waves are equal is given by

If, for example, the delay provided by the all-pass lter is

0.5 ms for the 100-Hz input sine wave, then the input sine
wave will have decreased by approximately 50 mV from its
peak value before the comparator begins to change state.
This circuit works well at steady state for input signals
that do not contain signicant high-frequency components.
Thus, it works reasonably well if the input signal is a triangular waveform, but it does not work well with square
waves.
A SYNTHESIS APPLICATION
First-order all-pass lters can be utilized to realize lters
with magnitude-selective characteristics. For example, the
circuit shown in Fig. 12, which is based on (5) and (6), realizes a bandpass lter transfer function by using a rstorder all-pass circuit in a feedback loop. The overall trans-

Phase Equalizers

Figure 12. Second-order bandpass lter realized by incorporating a rst-order all-pass lter in a feedback path.

Figure 11. Input voltage vi (t), delayed input voltage vA (t), and
comparator output voltage vo (t) for the slope-polarity detector
shown in Figure 10 when the input voltage is a sine wave.

fer function of the circuit is

Figure 13. Passive circuit that can be used to realize a rst-order

all-pass lter. Only one capacitor is needed.

ALL-PASS CIRCUIT REALIZATIONS

Voltage-mode Realizations

where K1 is the gain factor associated with the transfer

function of the rst-order all-pass lter. If C1 R1 = CR, K1
= 1, and R2 = R3 , then Eq. (35) reduces to the transfer
function of a standard second-order bandpass lter given
by

The Q and 0 of the poles in Eq. (36) are

Although the circuit requires the matching of elements and

several operational ampliers, including, possibly, a buffer
at the input, it demonstrates that all-pass lters can be
employed in the realization of lters having frequencyselective magnitude characteristics.

In this section, we examine a variety of circuits used to

realize all-pass transfer functions for which the input and
output variables of interest are voltage. Inductorless circuits for rst-order all-pass lters can be realized using
the bridge circuit shown in Fig. 13. The transfer function
of this circuit is given by

If R1 = R2 , then Eq. (38) reduces to the transfer function of

an all-pass lter (7). However, the requirement that R1 =
R2 results in a gain factor equal to , which is small in
magnitude. Also, a common ground does not exist between
the input and output ports of the circuit.
The bridge circuit shown in Fig. 14, which can be redrawn as a symmetrical lattice, can realize rst-order allpass transfer functions with a gain factor equal to 1. The
transfer function of this circuit is

If ZB = R and ZA = 1/(sC), a rst-order all-pass transfer

function is obtained. If inductors are allowed in the circuit,
then the circuit in Fig. 14 can realize higher order all-pass

Phase Equalizers

Figure 14. Passive circuit that can be used to realize rst-order

all-pass lters with gain factor equal to 1. Two capacitors are
needed. If inductors are allowed, this circuit can realize higher
order all-pass transfer functions with complex poles.

transfer functions. For example, suppose a circuit is needed

to realize a third-order all-pass transfer function TAP3 (s)
given by

where p(s) and q(s) are the numerator and denominator polynomials, respectively. The denominator polynomial
q(s) can be expressed as the sum of its even part, m(s), and
its odd part, n(s). Thus, q(s) = m(s) + n(s). If the roots of q(s)
are conned to the open LHP, then the ratios n/m and m/n
meet the necessary and sufcient conditions to be an LC
driving point impedance (8). Thus, if the numerator and denominator of the transfer function in Eq. (40) are divided
by m(s), we obtain

By comparing the result in Eq. (41) with Eq. (39), it is seen

that ZA = 1  and the box labeled ZB in Fig. 14 consists of
the series connection of a 1 Henry inductor and an LC tank
circuit that resonates at 1 rad/s. However, the resulting
circuit requires six reactive elements and does not have a
common ground between the input and output ports, and
these properties may preclude the use of bridge circuit allpass networks in some applications.
Single transistor rst-order all-pass transfer function
realizations have been described by several authors. The
interested reader may refer to Refs. 9 and 10 for additional information. Inductorless second-order realizations
are also described in Refs. 9 and 10 but the poles and zeros
of the transfer functions are conned to the real axis. Rubin
and Even extended the results in Ref. 9 to include higher
order all-pass transfer functions with complex poles, but
inductors are employed (11).
Figure 15 shows two rst-order all-pass circuits based
on operational ampliers (op-amps) (12, 13, also see Active
lters). The transfer functions are given by Ta = (Z2
kR1 )/(Z2 + R1 ) and Tb = (kZ1 + R2 )/(Z1 + R2 ). Thus, if
Z2 in Fig. 15(a) or if Z1 in Fig. 15(b) are selected to be the
impedances of capacitors and k = 1, then rst-order all-pass
circuits are realized. The circuit in Fig. 15(a) can be used

Figure 15. Single op-amp active realizations of rst-order allpass lters. (a) First-order all-pass circuit with gain factor equal
to +1. (b) First-order circuit with gain factor equal to 1.

to realize the all-pass circuits used in Figs. 10 and 12. Both

circuits in Fig. 15 can be modied to realize second-order
inductorless all-pass transfer functions, but the poles and
zeros are conned to the real axis. Resistor R1 in Fig. 15(a)
and resistor R2 in Fig. 15(b) are replaced by RC impedances
Z1 and Z2 , respectively. The circuit in Fig. 15(a) is clearly
related to the all-pass circuit shown in Fig. 13. An op-amp
has been employed so that the input and output voltages
have a common point of reference.
The realization of inductorless second-order all-pass circuits with complex poles can be achieved with the circuits
shown in Fig. 16. These circuits are minimal in the number of capacitors required. If the op-amps are ideal in the
sense of having innite gain-bandwidth product, then both
circuits have the same transfer function, namely,

where

In order to obtain an all-pass transfer function, we must

impose the requirement

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Phase Equalizers

Figure 17. Second-order all-pass circuit realization based on a

bandpass lter circuit with negative gain factor.

a second-order all-pass can be realized by summing the

output of the bandpass lter with the input signal. Figure
17 shows an all-pass realization using this scheme that is
based on the bandpass lter described earlier in this article. The transfer function is

Figure 16. Op-amp circuits for the realization of inductorless

second-order all-pass lters with complex poles. (a) Circuit useful in low Q applications in which a light load must be driven. (b)
Circuit employed in higher Q applications, but it requires a buffer
if a load must be driven.

If Eq. (44) is satised, then Eq. (42) becomes

where

Although both circuits have the same transfer function

when the op-amp is ideal, there are differences in the circuits. The circuit in Fig. 16(a) can drive light loads without an output buffer (14), whereas the circuit in Fig. 16(b)
requires a buffer for such loads (15). However, it can be
shown that when the nite op-amp gain-bandwidth product is taken into account, the circuit in Fig. 16(b) is better
suited for the realization of all-pass transfer functions with
poles having a Q greater than about ve. Since the Qs required for phase equalization of low-pass lters are usually
quite low, the circuit in Fig. 16(a) is a good choice for that
application.
If the requirement for a minimum number of capacitors is relaxed, then many inductorless active circuits are
available that can realize second-order all-pass transfer
functions with complex poles. The interested reader is invited to consult Ref. 16. In fact, if a second-order bandpass
circuit is available which has a negative gain factor, then

where 0 and Q are given in Eq. (37). To obtain an all-pass

lter, RX and RY must satisfy

It is seen that this same scheme is employed in the allpass lter circuit depicted in Fig. 16(b). If a second-order
band-pass lter is available that has a positive gain factor, then a second-order all-pass lter can be obtained by
interchanging input and ground (17).
Operational transconductance ampliers (OTAs) can
also be used to obtain active circuit realizations of voltagemode all-pass lters. These active devices are approximations to differential-input voltage-controlled current
sources (18, 19) and ideally have innite input and output impedances. Figure 18 shows circuit congurations for
a rst-order and a second-order all-pass lter. If the OTAs
are ideal, the transfer function for the rst-order lter is

where gm1 and gm2 are the transconductances of OTA1 and

OTA2, respectively. The transconductance is controlled by
a control current that is applied to a terminal (not shown)
of the OTA. Ideally, the transconductance is constant for
a constant control current. If the control currents for the
OTAs in Fig. 18(a) are adjusted so that gm1 = gm2 , then a
rst-order all-pass lter is obtained. The transfer function
for the circuit shown in Fig. 18(b) is

To obtain a second-order all-pass circuit, the transconductances in Fig. 18(b) must satisfy

Phase Equalizers

11

Figure 19. Current-mode all-pass circuits. (a) First-order. (b)

Second-order.

Figure 18. Operational transconductance amplier (OTA) allpass lter realizations. (a) First-order all-pass circuit. (b) Secondorder all-pass circuit.

and gm4 = gm5 . For realizing integrated circuit versions of

lters (see Analog processing circuits), OTAs are particularly suited, because they are relatively simple in structure, and they can operate at higher frequencies than, say,
voltage-mode op-amps. However, OTAs depart from ideal
in many aspects, of which the chief aspects are nite input
and output impedances, a frequency-dependent transconductance, and a limited range of input signal that is allowed
for linear operation. The input and output impedances also
are dependent on the control current (18, 19). The nonideal characteristics of OTAs must be taken into account
in the design of most circuits if accurate results are to be
obtained.
Voltage-mode all-pass lters can also be constructed using current-feedback op-amps (CFOAs). Soliman (20) provides several useful realizations.
Current-mode Realizations
All-pass lters in which the input and output variables
of interest are currents are called current-mode circuits.
If, in addition, the variables of interest throughout the
circuit are currents, then the current is a fully currentmode circuit. Active, fully current-mode circuits are of interest because they offer a larger bandwidth if properly
designed than do active voltage-mode circuits (21). Pas-

sive current-mode all-pass lters are easily obtained from

passive voltage-mode lters because the networks are reciprocal. Thus, if the output port of the voltage-mode circuit is excited by a current source and if the input port of
the voltage-mode circuit is shorted with the output current
owing through this short, then the current transfer function of the resulting circuit is the same as the voltage-mode
transfer function of the original circuit. However, the input
and output currents do not have a common ground. Active
current-mode all-pass lters with a common ground can be
obtained from voltage-mode lters that incorporate a voltage amplier by using the adjoint network concept (22). For
example, the application of the adjoint network concept to
the rst-order voltage-mode all-pass circuit in Figure 15(b)
results in the fully current-mode all-pass circuit shown in
Fig. 19(a). This rst-order all-pass lter employs a secondgeneration, positive current conveyor (CCII+) as the active
device (see Current conveyors). The transfer function of
the circuit is

If Z1 is chosen as (1/(sC), then a rst-order current-mode

all-pass lter is obtained. Although the all-pass lter in
Fig. 19(a) uses the minimum number of passive elements,
the capacitor is not counted as a grounded capacitor (a capacitor in which one lead of the capacitor has its own connection to ground), because it is connected to ground only
through the output lead. If this circuit is cascaded with
another circuit, the output lead may be connected to a virtual ground, and in this case, the capacitor would not be
a physically grounded one. Other rst-order all-pass realizations that incorporate one (grounded) capacitor and use
one CCII have been given (23), although they employ four
resistors. These realizations are easily cascaded.
A second-order all-pass lter that uses only one CCII is
shown in Fig. 19(b). This circuit can realize complex poles

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Phase Equalizers

and uses the minimum number of capacitors (23). Note that

no feedback elements are connected to the output terminal
z of the current conveyor, and so this all-pass realization
can be easily cascaded to achieve higher order realizations.
Either a positive or a negative current conveyor can be
employed. The transfer function of the circuit is given by

where a and b are identied in Fig. 19(b) and k is

The plus sign is chosen if a CCII+ is used, and the minus

sign is chosen if a CCII is utilized.
To realize an all-pass transfer function, the elements
must also satisfy

Minimum passive sensitivities are obtained with C1 = C2 ,

but the spread of element values can be reduced for larger
Qs by choosing C2 larger than C1 .
CCIIs are simpler to construct than rst-generation current conveyors (CCIs), and so are much more widely used.
However, a second-order all-pass lter with complex poles
can be realized using a single CCI (24). This circuit uses
the minimum number of capacitors, and both capacitors
are grounded.
MINIMUM PHASE AND ALL-PASS FILTERS
We say that a real, rational, stable transfer function in s
is a minimum phase transfer function if all its zeros are
conned to the closed LHP. No zeros are allowed in the
RHP. On the other hand, a nonminimum phase transfer
is one that has one or more zeros in the RHP. An all-pass
transfer function is nonminimum phase. Figure 20 depicts
pole-zero diagrams for minimum phase [Figs. 20(a) and (c)]
and nonminimum phase [Figs. 20(b) and (d)] transfer functions. To convert the diagram in Fig. 20(a) to a diagram corresponding to a nonminimum phase transfer function with
the same magnitude characteristic, we reect the zeros in
Fig. 20(a) through the origin. Thus, z3 = z1 and z4 = z2 in
Fig. 20(b). The corresponding transfer functions have the
same magnitude characteristics because the lengths of the
vectors from the zeros z1 and z2 to an arbitrary point P on
the j axis in Fig. 20(a) are the same as the lengths of the
vectors from the zeros z3 and z4 to P in Fig. 20(b). However, considering the order of the transfer functions (third
order) and that both have the same magnitude characteristic, there is more phase lag associated with the pole-zero
diagram in Fig. 20(b) than with Fig. 20(a).
In Figs. 20(c) and 20(d), a pair of complex poles, labeled
p1 and p2 , has been reected into the RHP as zeros labeled
z1 and z2 , where z1 = p1 and z2 = p2 . The phase characteristics of the corresponding transfer functions are the

Figure 20. Transfer function pole-zero plots. (a) and (c) Plots for
minimum phase transfer functions. (b) and (d) Plots for nonminimum phase transfer functions. The transfer functions corresponding to the plots in (a) and (b) have the same magnitude characteristics but differ in phase characteristics. The transfer functions
corresponding to the plots in (c) and (d) have the same phase characteristics but differ in magnitude characteristics.

same, but the magnitude characteristics differ. Still, the

second-order transfer function corresponding to Fig. 20(d)
is a nonminimum phase one. Note that it has the same
phase as the fourth-order transfer function corresponding
to Fig. 20(c).
A nonminimum phase transfer function can be expressed as the product of a minimum phase transfer function and an all-pass transfer function. For example, suppose we have the transfer function
T (s) =

(s 1)[(s 3)2 + 1]
[(s + 1)2 + 1][(s + 2)2 + 1]

By multiplying T(s) by

and regrouping the factors, we obtain

where TMP (s) is a minimum phase transfer function and

TAP (s) denotes an all-pass transfer function.
For sinusoidal steady state analysis applications, a minimum phase transfer function T(s) can be expressed in the
form

where () is the attenuation function in nepers and ()

is the negative of the phase function in radians. These
two functions are not independent but are related by the

Phase Equalizers

Hilbert transforms given by

13

maximally at at = 0.
DIGITAL ALL-PASS FILTERS

where  is a dummy variable and (0) is the value of the

attenuation function at zero frequency (25). Equations 55a
and 55b show that if () is specied for all , then ()
is also specied over all for a minimum phase transfer
function. Thus, () and () cannot be specied independently. Even if () is specied over only part of the j axis
and () is specied over the remaining parts, then T(j)
is determined over the whole axis.
However, attenuation and phase are independent of
each other in the case of nonminimum phase transfer functions. This is the reason that nonminimum phase transfer
functions usually are used to meet simultaneous attenuation and phase specications (26). Nevertheless, all-pole
low-pass minimum phase transfer functions can serve as
useful prototypes for all-pass lters (27). An all-pole lter
has a transfer function given by

where we take the gain factor H to be positive for convenience, and m(s) and n(s) are the even and odd parts of
the denominator polynomial q(s), respectively. The phase
of this low-pass lter is given by

An all-pass transfer function constructed from this lowpass transfer function has the form

Digital lters can be classed into two categories: nite impulse response (FIR) lters and innite impulse response
(IIR) lters (see Digital lters). The FIR lters can be
designed with perfectly linear phase. However, in general,
stable, realizable IIR lters cannot achieve perfectly linear
phase. Although IIR lters can be designed to approximate
given magnitude and phase requirements, a popular approach to digital lter design is to base a design on continuous time lter approximations and transform the result
to digital lter form. Then the phase is linearized (equalized) using cascaded digital all-pass lters. This approach
is a practical one (among several practical approaches) if
the order of the all-pass lter required is reasonable (28).
To devise a rst-order, real, stable, all-pass transfer
function, we place a zero outside the unit circle in the z
plane on the real axis at z = (1/r1 ) corresponding to a pole
at z = r1 , |r1 | < 1. The resulting transfer function is given
by

or

Evaluating H(z) in Eq. (68) for z = ejT , where T is the sampling interval, we obtain

and has a phase characteristic that can be expressed as

Thus, the phase and delay characteristics are the same

as for the low-pass prototype transfer function except for
the factor of two. Suppose that the low-pass prototype is
a Bessel lter transfer function. Then an all-pass transfer
function can be devised that also has maximally at delay
at = 0 and which has, ideally, a lossless magnitude characteristic. For example, the third-order Bessel lter transfer
function is

Thus, the corresponding all-pass transfer function is

The Bessel lter produces a 1-s delay, and the all-pass lter generates a 2-s delay, but the delay in both cases is

The numerator of the term in parentheses in Eq. (69) is the

conjugate of the term in the denominator. Thus, the magnitude of the term in parentheses is one. Also, the magnitude
of ejT is one. As a result, we have |H(ejT )| = 1/|r1 |. The
phase, denoted as (), for r1 assumed to be positive is obtained from Eq. (69) as

Since the magnitude characteristic is a constant over frequency and yet the phase characteristic changes as a function of frequency as can be seen from Eq. (70), the transfer
function in Eq. (67) is an all-pass one.
A second-order, real, stable all-pass transfer function
with complex poles can be devised in a manner similar to
that used for the rst-order transfer function. For a complex pole at z = rej , 0 < < , we must have another pole
at z = rej if the transfer function is to be real. We take
r positive for convenience and r < 1 for stability. Thus, for
each pair of complex poles given by z = rej , we place a pair

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Phase Equalizers

Figure 21. Poles and zeros of a digital third-order all-pass lter

transfer function.

of complex zeros outside the unit circle at z = (1/r)ej . The

resulting transfer function is given by

which can be rearranged into

The magnitude characteristic is easily obtained by evaluating H(z) in Eq. (72) for z = ejT . The result is |H(ejT )| =
1/r2 , and the phase is given by

A pattern is indicated by Eqs. 68 and 72 for higher order,

real, stable all-pass transfer functions. Let N be the order
of the all-pass transfer function, and let the poles be inside
the unit circle and occur in conjugate pairs if complex. That
is, each complex pole pair is described by

Figure 22. Plots of the rst function to the right of the equal sign
in Eq. (70) for values of r = 0.2, 0.4, 0.6, 0.75, and 0.8.

The delay of an IIR digital lter can be made more at

by connecting all-pass lters in cascade. The coefcients
required for the all-pass lters as well as the number of
all-pass lters needed are best determined by a cut-and-try
process using a computer program that plots delay characteristics interactively and quickly. However, an aid for delay equalization can be established. For this purpose, let
in the transfer function for a second-order all-pass transfer
function in Eq. (71) be expressed in terms of the sampling
interval T as = T. Then the normalized time delay characteristic can be obtained from d/d applied to Eq. (73).
Thus, we have

where 0 m N/2 and 0 < ri < 1. Then the transfer function is given by

where k is given by

and all the coefcients ai in Eq. (75) are real. The magnitude characteristic of the transfer function in Eq. (75)
evaluated for z = ejT is 1/|k|. Figure 21 shows a pole-zero
plot on the z plane for an all-pass transfer function with a
real pole at z = r1 and two conjugate complex poles at z =
r2 ej . The transfer function is real and stable.

Equation (77) expresses the normalized delay as the sum

of two functions. Let us examine the rst function to the
right of the equal sign. Its maximum value is (1 + r)/(1
r), which occurs at = in T . Since the delay characteristics obtained from cascaded all-pass lters
are described by a sum of functions of this type, a convenient design aid (29) is obtained by plotting this function
for several values of r. These plots are shown in Fig. 22. The
frequency axis has been normalized to ( )/s , where s
is the sampling frequency given by s = 2/T.
As an illustration of the concept, we apply delay equalization to a bandpass lter transfer function (8) given by

Phase Equalizers

15

Figure 24. Digital all-pass lter realizations. (a) First-order realization. (b) Second-order realization.

Figure 23. Equalizing the delay characteristic of a bandpass lter in the neighborhood of its center frequency with a second-order
all-pass lter.

This lter has its center frequency at = s /4 and has a

bandwidth described by 0.2s 0.3s . The normalized delay characteristic of the bandpass lter is denoted
by BP /T and is shown in Fig. 23. It is clear that this characteristic would benet by the addition of a delay lump from
a second-order all-pass lter located at = s /4 with r =
0.7. That is, a second-order all-pass lter is utilized with
normalized delay characteristic given by Eq. (77) with
= s /4 and r = 0.7. The normalized delay characteristic of
the all-pass lter is labeled AP /T in Fig. 23. The resulting
overall normalized delay characteristic, denoted by o /T, is
also shown, and it is seen that the result is atter in the
neighborhood of the center frequency at the expense of the
characteristic at the edges of the bandpass lter passband.
Additional all-pass delay lumps can be employed to correct
the delay at the band edges.
First- and second-order digital all-pass lters can be realized using the structures shown in Fig. 24. Figure 24(a)
shows a realization for a rst-order lter that employs only
one delay (30). Its transfer function is

where X and Y are the input and output variables, respectively, and a1 is the coefcient of a multiplier. The structure
in Fig. 24(b) can be used to realize second-order all-pass
transfer functions. Its transfer function is given by

Both structures in Fig. 24 are minimal in the number of

delays required. Higher order all-pass lters can be constructed by cascading rst- and second-order realizations.
There are many other structures that can be used to realize rst- and second-order all-pass lters; an extensive
catalog of such structures is given in Ref. 30, and a discussion of the effects of multiplication roundoff and hardware
requirements is provided.

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Phase Equalizers

BIBLIOGRAPHY
1. A. Budak Active and Passive Network Analysis and Synthesis,
Boston: Houghton Mifin, 1974; reprinted Prospect Heights,
IL: Waveland Press, 1991.
2. H. J. Blinchikoff A. I. Zverev Filtering in the Time and Frequency Domains, New York: Wiley, 1976; reprinted Malabar,
FL: Robert E. Krieger, 1987.
3. M. S. Ghausi K. R. Laker Modern Filter Design, Englewood
Cliffs, NJ: Prentice-Hall, 1981.
4. P. Klemp Phase shifter yields slope-polarity detection, EDN,
41 (6): 92, 94, 96, 1996.
5. D. J. Comer J. E. McDermid Inductorless bandpass characteristics using all-pass networks, IEEE Trans. Circuit Theory,
CT-15 (4), 501503, 1968.
6. D. T. Comer D. J. Comer J. R. Gonzalez A high-frequency integrable bandpass lter conguration, IEEE Trans. Circuits
Syst. II, Analog Digit. Signal Process., 44 (10): 856860, 1997.
7. A. Budak Circuit Theory Fundamentals and Applications, 2nd
ed, Englewood Cliffs, NJ: Prentice-Hall, 1987.
8. H. Lam Analog and Digital Filters, Englewood Cliffs, NJ:
Prentice-Hall, 1979.
9. P. Aronhime A one-transistor all-pass network, Proc. IEEE,
55: 445446, 1967.
10. H. J. Orchard Active all-pass networks with constant resistance, IEEE Trans. Circuit Theory, CT-20: 177179, 1973.
11. H. Rubin R. K. Even Single-transistor all-pass networks,
IEEE Trans. Circuit Theory, CT-20: 2430, 1973.
12. R. Genin Realization of an all-pass transfer function using
operational ampliers, Proc. IEEE, 56: 17461747, 1968.
13. P. Aronhime A. Budak An operational amplier all-pass network, Proc. IEEE, 57: 16771678, 1969.
14. T. Deliyannis RC active allpass sections, Electron. Lett., 5 (3):
5960, 1969.
15. A. Budak P. Aronhime Frequency limitations on an operational amplier realization of all-pass transfer functions with
complex poles, Proc. IEEE, 58: 11371138, 1970.
16. G. S. Moschytz A general all-pass network based on Sallen-Key
circuit, IEEE Trans. Circuit Theory, CT-19: 392394, 1972.
17. D. Hilberman Input and ground as complements in active lters, IEEE Trans. Circuit Theory, CT-20: 540547, 1973.
18. R. Schauman M. S. Ghausi K. R. Laker Design of Analog Filters, Englewood Cliffs, NJ: Prentice-Hall, 1990.
19. P. Aronhime Applications of operational ampliers. InJ. C.
Whitaker (ed.), The Electronics Handbook, 2nd Ed. Boca Raton, FL: CRC Press, 2005.
20. A. M. Soliman Applications of the current feedback operational ampliers, Analog Integr. Circuits Signal Process., 11:
265302, 1996.
21. C. ToumazouF. J. LidgeyD. G. Haigh eds., Analogue IC Design:
The Current-Mode Approach, London: Peter Peregrinus, 1990.
22. G. W. Roberts A. S. Sedra All current-mode frequency selective
circuits, Electron. Lett., 25 (12): 759761, 1989.
23. A. M. Soliman Generation of current conveyor-based all-pass
lters from op amp-based circuits, IEEE Trans. Circuits Syst.
II, Analog Digit. Signal Process., 44: 324330, 1997.
24. P. Aronhime D. Nelson J. Zurada C. Adams Realization of
current-mode complex pole all-pass networks using a single
current conveyor. In Proceedings of the International Symposium on Circuits and Systems, vol.4, 1990, pp. 31933196.

25. C. S. Lindquist Active Network Design, Long Beach, CA: Steward & Sons, 1977.
26. A. S. Sedra P. O. Brackett Filter Theory and Design: Active and
Passive, Portland: Matrix Publishers, 1978.
27. L. P. Huelsman Active and Passive Analog Filter Design, New
York: McGraw-Hill, 1993.
28. L. R. Rabiner B. Gold Theory and Application of Digital Signal
Processing, Englewood Cliffs, NJ: Prentice-Hall, 1975.
29. S. A. Tretter Introduction to Discrete-Time Signal Processing,
New York: Wiley, 1976.
30. S. K. Mitra K. Hirano Digital all-pass networks, IEEE Trans.
Circuits Syst. CAS-21: 688700, 1974.

Reading List
W.-K. Chen ed., The Circuits and Filters Handbook, Boca Raton,
FL: CRC Press, 1995.
A. B. Williams F. J. Taylor Electronic Filter Design Handbook, New
York: McGraw-Hill, 1995.

PETER ARONHIME
University of Louisville, 10
Eastern Parkway, Louisville,
KY, 40292

446

ANALOG COMPUTER CIRCUITS

VI

V0 = K(VP VI )
+

VP
(a)
+15

VI

V0 = K(VP VI )

VP
15
(b)
Figure 1. Operational amplifier symbol. (a) Operational amplifier.
(b) Operational amplifier with power supply voltages attached.

and transistors) connected to process analog signals (as opposed to digital signals) which are conceptually modeled as
continuous functions of time. Analog computers have limited
bounds namely, Emax and Emin. Since the early 1960s, analog
computers have used solid state components, and the signal
range is typically 10 V. The operational amplifiers are usually made in integrated circuit form. They may be supplied as
separate modules, mounted on a circuit board, or a part of a
larger integrated circuit. We are here primarily interested in
the operation of such electronic systems to solve ordinary differential equations, although operational amplifiers are often
used in the design of signal filtering circuits and in the design
of interface signal-conditioning subsystems to go between
real-world signals from a wide variety of transducers and subsequently to digital signal processing systems used for data
logging and analysis.
A typical ideal operational amplifier model is shown in Fig.
1. The ideal model has an inputoutput description
V0 = K(VP VI ),

V1

where K  1

K1

V2

K2

Vn

Kn

V0

(a)
K1
K2

V0

Kn

(b)

V1

ANALOG COMPUTER CIRCUITS

The term analog computer usually refers to an electronic circuit consisting of operational amplifiers, resistors, and capacitors along with additional electronic components (e.g., diodes

K1

V2

K2

Vn

Kn

V0
(c)

Figure 2. Conventional operational amplifier circuit block symbols.

(a) Summerinverter. (b) Inverting summerintegrator. (c) Older
symbol for inverting summerintegrator.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

ANALOG COMPUTER CIRCUITS

V1
V2

R1
R2

Basic inputoutput relations for the circuit in Fig. 3(c) are

R1

V1

R2

V2

V0 = RF

RF
Vn

Zini = Ri

V0

V0

Ki =

RF
Ri

Ki =

(a)

For Fig. 3(d):

V0 = (1 + RF /Ri )V

ZF
Ri

Example. Consider the mechanical system of Fig. 4(a). A

simple force balance equation gives

(b)

RF
R1
V2

RF

F + MX DX KX = 0

Vn
Rn

Vo

Vin
(c)

f =0

with initial conditions X(0) and X(0) or

Vo

V2

R1

RF

R2

(V /R) i = 1, 2, . . ., n

= RF (V1 /R1 + V2 /R2 + )

Rn

Vn

n

i=1

Rn

447

or
X = (K/M)X + (D/M)X + (F/M)

(d)

Figure 3. Operational amplifier circuits. (a) Summerinverter. (b)

Inverting summerintegrator. (c) Basic summerinverter circuit. (d)
Basic noninverting circuit.

More information on operational amplifiers is available in

Refs. 1 and 2.
Primary operational amplifier circuits for analog computing are integrating and summing circuits. Figure 2(a) shows
the block diagram for a summerinverter. Figure 2(b) shows
a summerinverting integrator. A skilled analog computer
programmer learns to cleverly program his or her collection
of summers and integrators to implement an electronic model
which solves a set of ordinary differential equations (ODEs)

Let M 5 kg, D 0.1 Ns/m, and K 1.0 m/N; then

X = (0.2)X + 0.02X + 0.2F)
The operational amplifier circuit of Fig. 4(b) shows a basic
analog computer model for this system. F(t) may be a voltage
generated by a variety of signal sourcesfor example, function generator types of variable-frequency sine-square wave
generators, recorded signal sources, and so on. Often we may
not want a real model of this system but will want to scale
or denormalize the circuit to get a repetitive display (e.g., on
an oscilloscope). We can slow down a simulation by making
the capacitors larger, or we can speed it up by making them
smaller by the same time scale factor.

F (t) = a0 X + a1 X + a2 X +

;;;
;

OPERATIONAL AMPLIFIER CIRCUITS

Figure 3 shows corresponding operational amplifier circuits.

As indicated in Chapter 1 of Ref. 1, the ideal operational
amplifier has a very high open loop gain and input impedance
and a relatively low output impedance.

Spring

M
mass

For precise signal processing, one often uses nonlinear operational amplifier circuits. Important nonlinear operations include:

5R

5R
+

F(t)

+
50R

Friction

(a)

(b)

Figure 4. Spring-mass system. (a) Mechanical system. (b) Operational amplifier analog computer model. R 106 , C 106 F.

448

ANALOG COMPUTER CIRCUITS

R1

eg

V1

5R
Nonlinear
network

+15 V

R2
V2

V0 = f ( in )

eg 0

RA
1500

D1
Vin

i1 + i2 + in = 0

Figure 5. General nonlinear operational amplifier circuit configuration.

RB
500
RF

R1
5 k

V0
p

+
On

i V

On i > 0
Off

Off i < 0

K=

n
(a)

(b)

(c)

RD
1500

RF
R1

15 V

(d)

Figure 6. Pn junction diode. (a) Diode symbol; (b) demon-with-aswitch model; (c) diode ON or forward biased (d) diode OFF or reverse biased.

iE

VE

RC
500

D2

Figure 9. Operational amplifier circuit for a limiter amplifier.

V0

iC

VC

Emitter

No RF

Collector

5
RF /R1
With RF

VEB

VCB

RI C

V1

FI E

iB

F
F 1
F
1
1 F

VB
Base

Figure 7. Npn bipolar junction transistor model (BJT). F is forward

biased current gain.

V1

V0

Figure 10. Direct-current transfer characteristic for circuit in Fig. 9.

V1
V0

ER
V0

V0

L+

K
V1

ER

V1

L
Figure 11. Comparator block symbol. ER is reference voltage.
Figure 8. Limiter operator.

ANALOG COMPUTER CIRCUITS

VI

Clamp or
5R
feedback
limiter

449

V0

V1

VV
V0 = 1 2
10

VP

V0

(a)

+
RA

ER

V2 > 0

RB

R2
R1

V0

V0

(a)
+

V0

V0 =

10R2 V1
R1 V2

(b)

V+
Eh

Figure 13. Block symbols: (a) Multiplier. (b) Divider.

V1
E RR 1
R2
(b)
V0

V0
With hysteresis
V+

V+
0

Squegging
(c)

(d)

Figure 12. Comparator behavior. (a) General circuit diagram. (b) Direct-current transfer characteristic. (c) squegging (i.e., no hysteresis). (d) Comparator behavior with hysteresis.

used in instrumentation systems to prevent signal overloads.

One amplifier actually provides an inverting limiter.
The one-amplifier limiter or comparator circuit of Fig. 9
actually provides the transfer characteristic of Fig. 10. The
resistance string RA RD sets the limiting levels.
Without RF, the circuit of Fig. 9 provides a comparator,
which may operate with a reference voltage ER, (Figs. 11 and
12).
Useful comparator circuits should have some hysteresis
Eh to prevent an ambiguous chattering or squegging at the
comparator switch point (just as a household thermostat provides hysteresis with a small magnet associated with its contacts). Figure 12 shows a one-amplifier (inverting) comparator. The hysteresis is established by the network RA RB,
which yields
Eh = RB (V+ )/(RA + RB )

Limiters (Figs. 8 to 10)

Comparators (Figs. 11 and 12)
Multipliers and dividers (Fig. 13)
Waveform generators (Figs. 14 and 15)
Circuits based upon these types of operations may be extended to circuits that precisely measure absolute value, amplitude, peak value, and logarithmic operations. (Another way
of making a multiplier is by the use of antilog or exponentiation operators.) A variety of other waveform generators, including triangle waveform and very low-frequency oscillators
(function generators) and frequency modulation (FM) oscillators, may be implemented. Detailed discussions of nonlinear
operators appear in Refs. 1 and 2.
Figure 5 shows a general diagram for nonlinear operational amplifier circuits. The operational amplifier forces the
current at the inverting terminal or summing junction voltage to be zero.
Figure 6 shows a demon with a switch model of a junction diode. When the diode is on, the forward drop is not
really zero but may be as much as 0.5 V. The bipolar junction
transistor (BJT) (Fig. 7) provides a more flexible active device
for nonlinear circuit design. The limiter operator (Fig. 8) is

Analog multipliers and dividers are designed in a variety of

ways (Fig. 13). A popular method uses loggingantilogging
circuits (see Ref. 1). Sinusoidal waveform generators may be
implemented using the block diagrams of Figs. 14 and 15. The
circuit of Fig. 14 generates sine waves by implementing the
solution of an undamped second-order ODE. The block dia-

Soft amplitude
included limiter
w0

Inverting
integrator
w0

V0

w0
1
V0
<< 1
Figure 14. Sinusoidal waveform generator.

450

ANALOG COMPUTERS

VT

Inverting
integrator

V1
Bistable

Figure 15. Function generator block diagram for generating low-frequency triangle and square waves.

gram of Fig. 15 shows a diagram of the function generator

type of circuit to generate square and triangle waveforms (see
Ref. 1).
BIBLIOGRAPHY
1. J. V. Wait, L. P. Huelsman, and G. A. Korn, Introduction to Operational Amplifier Theory and Applications, New York: McGrawHill, 1992.
2. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, New York: McGraw-Hill, 1988.
Reading List
Analog Devices, Designers References Manuals, Norwood, MA.
Burr-Brown Corp., Integrated Circuits Data Books, Tucson, AZ.
F. H. Mitchell, Jr. and F. H. Mitchell, Sr., Introduction to Electronics
Design, Englewood Cliffs, NJ: Prentice-Hall, 1988.
R. J. Smith and R. C. Dorf, Circuits, Devices and Systems, 5th ed.,
New York: Wiley, 1992.
Texas Instruments, Linear Circuits, Dallas, TX.

JOHN V. WAIT

ANALOG COMPUTERS
Computing devices capable of mapping inputs to outputs
without human intervention and of providing numerical solutions to complex problems have been available in various
forms for over 150 years. In many of the early devices, information was represented in mechanical form, as in the mechanical calculators that became invaluable for business data
processing in the first half of the twentieth century. Others
employed electric representations, as in the network analyzers that played an important role in a wide variety of engineering applications during same period.
The utilization of electronic circuits as components of automatic computers was made possible by developments and inventions stimulated by military requirements during World
War II, particularly in the United States and Great Britain.
One class of these computers was primarily developed as part
of the Manhattan Project to help solve the complex partial
differential equations that characterize various physical processes in atomic bombs. These represented extensions of me-

chanical calculators, but were vastly more powerful in their

ability to do arithmetic. A second class of computing techniques was developed to help in the performance of integral
and differential calculus as required for the simulation of dynamic mechanical and electromechanical systems, such as
ships and aircraft, and for a wide variety of control tasks.
The members of the first category became known as digital
computers, while the second class was termed analog computers and devices.
The years immediately following World War II saw the
rapid extension of electronic computers to new application
areas and the formation of industrial enterprises to commercialize them. For a variety of reasons, analog computing devices emerged from military projects more ready for immediate general application than did digital computers, and in the
late 1940s a number of companies were formed to market
products specifically designed for the solution of the systems
of nonlinear ordinary differential equations characterizing dynamic systems. These computers were termed electronic differential analyzers (EDAs), and they became so widely used
in the 1950s that the term analog computer became largely
synonymous with EDA.
As digital computers evolved during the same period, they
gradually began to be used in competition with analog computers. Until well into the 1970s, however, digital computers
tended to be less cost effective than analog computers in the
specialized simulation application, and they were too slow to
permit real-time operation. EDAs had their heydays in the
1970s as free-standing simulators or in concert with digital
computers in hybrid computer systems. Companies such as
Electronic Associates, Inc., Comcor, Inc., Applied Dynamics,
Inc., and a number of others in the United States, Germany,
and Japan grew to large size and maintained an important
position in the military and industrial marketplace. In the
meantime companies such as IBM, Control Data Corporation,
Digital Equipment Corporation, and many others developed
more and more powerful simulation hardware and software.
By the end of the 1970s, the balance began to shift in favor
of digital simulation, and gradually the market for EDAs
evaporated. It disappeared almost completely in the 1990s.
By then, all the tasks formerly performed by electronic analog
computers in the simulation of dynamic systems were handled more effectively by digital computing systems. In other
application areas, however, analog devices thrived as specialpurpose components embedded in a wide variety of systems.
The requirements for these analog devices in communication
and control systems and in a myriad of military, industrial,
and commercial projects has grown almost continuously, and
many prosperous companies throughout the world specialize
in their manufacture.
In this article, the evolution analog computing devices is
first briefly reviewed, including a discussion of the electrical
network analyzers and mechanical differential analyzers that
were important before World War II. Next, a survey of the
EDAs that became popular during the 1960s and 1970s is presented. Finally, the rise and eventual decline of hybrid
(analog/digital) computers in the 1980s and early 1990s is
considered. Further details may be found in Refs. 15.
ANALOG AND DIGITAL PROCESSING
Modern science and engineering are based upon a quantitative description of the physical universe. A variety of so-called

ANALOG COMPUTERS

physical variables is measured, and inferences are drawn

from the results of these measurements. In this connection,
it is necessary first to distinguish between independent and
dependent variables. In most system analyses, time and space
constitute the independent variables. That is, measurements
are distinguished from each other and ordered according to
the location in the timespace continuum at which the measurements were made. The measured quantities are the dependent variables, and they may be expressed as functions of
time and/or space. Some familiar dependent variables include
voltage, displacement, velocity, pressure, temperature, stress,
and force. The measurement of these variables requires the
selection of appropriate instruments, along with a decision as
to the manner in which the measurements are to be recorded
and utilized. There are two major ways in which a dependent
variable is treated by instrumentation and data processing
systems: analog and digital. These are defined as follows:
1. A dependent variable is said to be an analog variable if
it can assume any value between two limits.
2. A dependent variable is said to be a digital variable if
its magnitude is limited or restricted to certain specified
values or levels.
It should be recognized that this distinction does not apply to
the domains of the independent variables. Thus analog computers or simulators may maintain the time and the space
variables in continuous form, or they may restrict their attention to discretely spaced points in the time and space domains.
The decision as to whether to process data in analog or
digital form has far-reaching consequences on the organization of the computer system and its cost, upon the accuracy
of the computations, and upon their speed. In order to place
the discussion of analog signal processing in its proper perspective, these considerations are briefly summarized.
A basic distinction between analog and digital data processing is that digital computations are usually performed sequentially or serially, while analog computations are performed simultaneously or in parallel. Digital data processing
generally requires reference to data and programmed instructions stored in a memory unit. For technical reasons, there
exists a bottleneck at the entrance to this memory, so that
only one item (or a very small number of items) of information
can be read into or read out of the memory at any particular
instant of time. Therefore, only one arithmetic operation can
be performed at a time. This implies that data processing consists of a sequence of arithmetic operations. For example, if
10 numbers are to be added, 10 successive additions are performed. No additional equipment is needed if 100 additions
are required instead.
By contrast, an analog processor generally does not require
a memory, which must be time-shared among the various
mathematical operations. Rather, a separate electronic unit
or black box is supplied for each mathematical operation. If
a computation requires 10 additions, 10 analog operational
units must be provided and interconnected; and all of these
units operate simultaneously. If the number of required additions is increased to 100, the amount of electronic equipment
necessary is multiplied by a factor of 10. The hardware structure and the cost of an analog data processing system is
therefore determined by the types and numbers of specific

451

mathematical operations which are to be performed. The

structure of a digital processing system, on the other hand,
includes standardized memory, control, and arithmetic units
and is more or less independent of the types of computations
that are to be performed.
The accuracy of a computation performed by a digital processor is determined by the number of bits employed to represent data. For example, if two numbers are to be multiplied
in a digital processing system in which numbers are represented by 32 binary digits, the result of the multiplication
must be rounded up or down to the nearest least significant
bit. There is, therefore, a chance of a roundoff error corresponding to one-half of the least significant bit. In an analog
processor, data are not discretized, and roundoff errors are
therefore not incurred. Instead, the accuracy is limited and
error is introduced by the nonideal functioning of the operational units used to carry out the computationsthat is, by
the quality of its components. If two variables are to be added
electrically, they are each applied as continuous voltages to
an adder unit. The output voltage of the adder then corresponds to the sum of the two variables. The accuracy of this
addition operation is limited by the quality (tolerance) of the
electronic components making up the adder and by the precision with which the output voltage can be measured and recorded. In the performance of linear mathematical operations
(such as addition, subtraction, and multiplication by a constant), relative errors are usually larger than 0.01% of full
scale; in the case of nonlinear operations, the best available
electronic units are subject to relative errors of 0.1%.
The speed with which a sequential digital computation can
be performed is determined by the complexity of the computations. The larger the number of arithmetic operations that
must be performed, the longer the time required. One hundred additions require nearly 10 times as much computing
time as 10 additions. By contrast, in analog data processing,
the time required for computations is independent of problem
complexity. One hundred additions require precisely the same
time as 10 additions; approximately 10 times as much hardware is required, however. The speed with which a mathematical operation can be performed using an analog unit is
determined by the characteristics of its electronic components
as well as by the characteristics of the measuring or output
devices.
In most modern systems utilizing analog processing, only
the operational units actually required for the specific task at
hand are provided. These are interconnected in a permanent
or semipermanent fashion for a specific application. By contrast, the so-called general-purpose analog computers or
EDAs, which have by now almost completely disappeared,
were fashioned by assembling a variety of operational units
and permitting the user sufficient flexibility to interconnect
them as required for the solution of differential equations.
Since the analog methods described in this article were applied almost exclusively to the implementation of mathematical models of real-world systems and to the experimentation
with these models, the terms analog computer and analog
simulator gradually became synonymous and are used in this
way in this article.
CLASSIFICATION OF ANALOG METHODS
The various devices and methods comprising the general area
of analog computers and simulators are best classified ac-

452

ANALOG COMPUTERS

cording to their basic principles of operation. The systems

falling into the resulting categories are subdivided, in turn,
according to the type of physical variables which constitute
the continuous data within the computer.
One major class of analog devices depends for its operation
upon the existence of a direct physical analogy between the
analog and the prototype system being simulated. Such an
analogy is recognized by comparing the characteristic equations describing the dynamic or static behavior of the two systems. An analogy is said to exist if the governing, characteristic equations are similar in form, term by term. For every
element in the original system, there must be present in the
analog system an element having mathematically similar
propertiesthat is, an element having a similar excitation/
response relationship. Furthermore, the analog elements
must be joined or interconnected in a similar fashion. Members of this category of analog devices are termed direct analogs. Direct analogs may be of either the continuous (distributed) or the discrete variety.
Continuous direct analog simulators make use of distributed elements such as sheets or solids, made of an electrically
conductive material, so that every spatial point in the analog
corresponds to a specific point in the system being simulated.
The conductive sheets and electrolytic tanks described below
fall into that category. Stretched membrane models, in which
soap films or thin rubbers sheets are supported by a mechanical framework, were also used for a time to simulated fields
governed by Laplaces and Poissons equations. Hydrodynamic models, termed fluid mappers, as well as direct analog
simulators utilizing thermal fields, electrochemical diffusion
phenomena, polarized light, and electrostatic fields, have also
been successfully used for that purpose.
Discrete direct analog simulators employ lumped physical
elements, such as electrical resistors and capacitors, in which
case the behavior of the system being simulated is obtained
only for the points in the system that correspond to the junctions in the electrical circuit. Networks of electrical resistors,
resistancecapacitance networks, and inductancecapacitance networks have all been widely used to simulate fields
governed by elliptic, parabolic, hyperbolic, and biharmonic
partial differential equations.
The other major class of analog simulation systems includes mathematical rather than physical analogs. The behavior of the system under study is first characterized by a

set of algebraic or differential equations. An assemblage of

analog computing units or elements, each capable of performing some specific mathematical operation, such as addition, multiplication or integration, is provided, and these
units are interconnected so as to generate numerical solutions
of the problem. Such computing systems are termed indirect
analog computers. Prior to World War II, powerful indirect
analogs for the solution of differential equations were fashioned from mechanical components and termed mechanical
differential analyzers. Electronic differential analyzers were
introduced after World War II and became very important
tools in the design of aerospace systems, control systems, and
chemical process controllers in the United States, western
Europe, Japan, and the Soviet Union.
An important distinction between direct and indirect analogs involves the significance of the physical variables within
the computer. In a direct analog, an analog variable has the
same significance everywhere within the analog system. For
example, in the electrical analog simulation of a mechanical
system, voltage everywhere in the analog may represent velocity. The time derivative of the analog voltage would then
represent acceleration. In an indirect analog, on the other
hand, a transient voltage at some junction in the analog may
represent acceleration; this voltage is then applied to an integrator unit, and the transient voltage at the output of the
integrator would represent velocity.
The general classification of analog methods is illustrated
diagrammatically in Fig. 1. It should be emphasized that continuous and discrete direct analog simulators played a very
significant role before World War II. By 1980 they had all
been virtually completely eclipsed by digital simulation methods. Indirect analog computers enjoyed wide use in the 1960s,
1970s, and 1980s; but by the early 1990s, they too had largely
been replaced by digital computers.
DIRECT ANALOG SIMULATORS
Examples of Continuous Direct Analog Simulators
One of the fundamental equations characterizing distributed
parameter systems in a wide variety of areas of physics is
Laplaces equation,
2 = 0

(1)

Analog computer and simulators

Direct

Electrical

Indirect

Mechanical

Electronic

One-Shot

Figure 1. Classification of analog simulation methods and analog computers.

Conductive paper
Stretched membrane
Eletrolytic tank
Massspring system
Resistance network
Fluid mapper
R-C network
L-C network
L-C transformer network

EAI-PACE
Comcor
Applied Dynamics
Beckman EASE
etc.

Mechanical

Repetitive
Philbric
GPS

Mechanical
differential
analyzer

ANALOG COMPUTERS

453

and Poissons equation

2 = K

(2)
Direct-current
oscillograph

Conductive sheet

Equation (1) arises, for example, in the study of the steadystate temperature distribution in a flat plate, subject to heat
sources or sinks at its boundaries. Lets apply a direct analog
simulation method to such a problem:
1. A sheet made of an electrically conductive material having the same geometrical shape as the field under study
is fashioned in the laboratory.
2. The boundary conditions of the original field are simulated in the analog system by appropriate voltage and
current sources. For example, if one boundary of the
sheet is specified to have a temperature of 100C, and
another boundary a temperature of 0C, voltage sources
100 V and 0 V in magnitude might be applied to the
corresponding locations in the analog.
3. By means of suitable sensing equipment, such as a voltmeter or an oscilloscope, lines of equal voltage in the
conductive medium are detected and recorded.
4. The voltage distribution measured in the analog then
constitutes the solution to the problem.
Over the years, the suitability of many different conductive
materials was investigated so as to devise practical analog
simulators. One technique widely used in the 1960s and
1970s involved the utilization of Teledeltos Paper developed
and marketed by the Western Union Telegraph Company as
a recording medium for telegrams and graphic chart instruments. This paper is formed by adding carbon black, a conductive material, to paper pulp in the pulp-beating stage of
the paper-manufacturing process. This results in a high-quality paper with a fairly uniform dispersion of carbon. Because
of its wide use, the paper was quite inexpensive and wellsuited for rough and dirty simulation applications. A typical
setup of this type is shown in Fig. 2(a). At times, lines of equal
potential were drawn directly on the conductive paper, using
a ball point pen, as illustrated in Fig. 2(b). In that case, the
potentiometer is set to the voltage corresponding to the equipotential line to be sketched, and the probe is moved over the
paper in such a manner that the deflection of the microameter
remains zero. When a complete equipotential line has been
drawn, the potentiometer is set to a different voltage, and the
process is repeated until the equipotential lines of the entire
field have been plotted.
For greater accuracy, an electrically conductive liquid was
used in place of the resistance paper. Such so-called electrolytic tank analog simulators, shown in Fig. 3, were employed
to simulate fields governed by Laplaces equation and were
used as follows:
1. A large container (the tank), open at the top is filled
with a suitable weak saline solution (the electrolyte).
2. A scale model of the boundary configuration of the twodimensional field under study, or a conformal transformation thereof, is immersed in the container. Boundaries which are equipotential surfaces are made of
metal, while streamline boundaries are fashioned from
an insulating material.

Probe

Silver
electrode

Silver
electrode
(a)

Potentiometer P

Microammeter

Probe

Silver
electrode

Silver
electrode

Teledeltos
(b)
Figure 2. (a) Simple conductive sheet analog simulator for modeling
fields governed by Laplaces equation in two dimensions. (b) Potentiometer plotting arrangement for drawing equipotential lines directly
on the conductive paper.

3. Alternating-current (ac) voltage sources of appropriate

magnitudes are applied to all equipotential boundaries.
4. The voltage distribution along the surface of the electrolyte is measured and recorded. Lines of constant voltage
within the analog then correspond directly to the equipotential lines of the system being simulated.
If a field governed by Laplaces equation in three dimensions
was to be simulated, the sensing probe could be extended into

Power supply

Null
indicator
Plotter

Probe
Electrolyte

Potentiometer

Tank
Electrodes
Figure 3. Typical conductive liquid analog simulation system (electrolytic tank) for modeling fields governed by Laplaces equation.

454

ANALOG COMPUTERS

3
5
R3
2
Figure 4. Typical nodes of resistance
capacitance networks used to simulated
fields governed by the heat-transfer or diffusion equations. Networks may contain
thousands of such node elements. (a) One
dimension, (b) two dimensions, (c) three
space dimensions.

R2

R1

R2

R1

R2

R1

R6
C0

C0

C0

R4

(b)

Examples of Discrete Direct Analog Simulators

Electrical network simulators are based on finite difference or
finite element approximations of one-, two-, or three-dimensional partial differential equations. By far the most widely
used discrete direct analog simulators were the resistance/
capacitance networks for the simulation of fields governed by
the diffusion equation,

(3)

in one, two, and three Cartesian coordinates. In this approach, the derivatives with respect to the space variables are
replaced by finite differences, while the time variable is kept
in continuous form, as

1 0

+ 2 20
=k 0

x2

x
t
1 0
2 0
3 0
4 0 0
+
+
+
=k

x2

x2

y2

y2
t
2 0
3 0
4 0
1 0
+
+
+

x2

x2

y2

y2

+ 5 20 + 6 20
=k 0

z
t

(4a)
(4b)

R4

4
(a)

the liquid and a three-dimensional record of the potential distribution within the tank obtained. Great care was taken to
achieve highly accurate modeling and sensing devices, so that
relative solution errors could be kept below 0.01%. Throughout the first half of the twentieth century and until the advent
of digital simulators in the 1980s, electrolytic tanks remained
the premier method for the accurate mapping of potential
fields (see Ref. 1).

2 = k

R3

R5

(c)

Other network simulators for the simulation of fields characterized by partial differential equations included one-, two-,
and three-dimensional networks of resistors. These served to
model fields governed by elliptic partial differential equations
such as Eqs. (1) and (2). Networks of inductors and capacitors
were occasionally used to simulate fields governed by the
wave equation, particularly in the design of electromagnetic
systems such as waveguides and cavity resonators.
One very sophisticated and elaborate network computer
was designed at Caltech and by Computer Engineering Associates for the simulation elastic beam problems governed by
the biharmonic partial differential equations,

4 = 0

(5a)

2
4 = k 2
t

(5b)

In addition to inductors and capacitors, this simulator included high-quality transformers in every network node element. Figure 5 illustrates the simulation of the vibration of a
cantilever beam using this approach. Similar networks were
used to simulate the deflection of two-dimensional systems
such as elastic plates. Another network analyzer including resistors, reactors and transformers was marketed by General
Electric and used for the simulation of electric power distribution networks. More details are provided in Ref. 1.
INDIRECT ANALOG SIMULATORS
Mechanical Differential Analyzers

(4c)

Electrical networks are then fashioned from resistors and capacitors, with typical nodes as shown in Fig. 4, where the
magnitudes of the circuit elements are determined by the local magnitudes of the parameters in the field being simulated.
Networks of this type proved extremely useful in the study of
transient heat transfer (so-called thermal analyzers) and of
the flow of fluids in porous media as in aquifers and oil reservoirs. In a number of instances, such networks contained
many thousands of node elements, as well as sophisticated
electronic circuitry for the application of boundary and initial conditions.

The possibility of obtaining computer solutions of ordinary

differential equations by successive mechanical integrations
was first suggested by Lord Kelvin in 1876. No successful
machines using this method appear to have been constructed until researchers at MIT, under the leadership of
Vannevar Bush, constructed a series of these computers,
termed mechanical differential analyzers, in the 1930s. In
the 1940s, General Electric marketed several such analog
machines, and others were subsequently constructed and
installed at a number of locations in Western Europe and
in the Soviet Union.
In mechanical differential analyzers, all dependent problem variables are represented by the rotations of as many as
100 parallel shafts, rather than by voltages as in electronic

;;

ANALOG COMPUTERS

S1
2

M0

x
1

x
5

(a)

m1 x S1 1 m2 x S2 1 m3 x S3 1 m4 x S4 1
2

M1

M2

M3

1
2 m5 x

M4

S5

M5

z=
(EI)0
x

455

(EI)1
x

(EI)2
x

(EI)3
x

(EI)4
x

x+ y
2
(a)

4m

3n

4n

5n

6n

7n

8n

9n

Input
Figure 5. Network for the simulation of the vibrations of an elastic
cantilever beam, governed by the biharmonic equation, which is
fourth-order in x and second order in time. (a) Schematic of the beam
including five finite difference or finite element sections. (b) Network
containing inductors, capacitors and a transformer at each node. (See
Refs. 1 and 2.)

10n

(b)

dz =

1
y dx
a

(6)

6m

12m

4m

differential analyzers. These shafts are interconnected and

driven by mechanical units that accept one or more shaft rotations as inputs, and they drive another shaft the rotation of
which provides the output corresponding to the desired functional inputoutput relationship.
The addition of two dependent variables, x and y, is accomplished with the aid of differential gears, as shown in Fig.
6(a). Multiplication by a constant is readily achieved by coupling two shafts by gears. By selecting appropriate gear ratios, one turn of one shaft can be translated into a desired
multiple or fraction of a turn of the second shaft. This is illustrated in Fig. 6(b).
Integration of a dependent variable with respect to another
dependent variable or with respect to an independent variable can be carried out using a disk-and-wheel integrator as
shown schematically in Fig. 6(c). The turns of the disk, called
the turntable, represents the differential variable x to a suitable scale factor. The distance of the wheel centerplane from
the axis of the turntable represents the integrand, y, again to
some suitable scale factor. These are the two inputs to the
integrator. The turns of the integrating wheel represent the
value z of the integral to a scale factor determined by the two
input scale factors and the actual structural details of the
unit. This is the output of the integrator.
A rotation of the disk through an infinitesimal fraction of
a turn, dx, causes the wheel to turn through a correspondingly small part of a turn, dz. For a wheel of radius a, we
obtain

10n

Splined coutershaft

Output

(b)

(b)
Figure 6. Mechanical computing elements employed in mechanical
differential analyzers. (a) Differential gear for producing a shaft rotation z which is proportional to the sum of rotations x and y. (b) Multiplication of the rotation of a shaft using step-up or step-down gear
ratios. (c) Disk-wheel integrator for generating the integral z of wheel
displacements y with respect to wheel displacement x of the disk.

456

;;

ANALOG COMPUTERS

D
Motor

During a finite time interval, the x turntable will turn

through a finite number of revolutions, and the distance y
will vary, ranging through positive (on one side of center) to
negative (on the other side of center) values as called for by
the problem. The total number of turns registered by the integrating wheel will then be


y dx

Amplifier

Figure 7. Polarized-light servomechanism for torque amplification in a wheel

disk integrator.

1
z=
a

(7)

x0

Adequate operation of the integrator requires that the wheel

roll with negligible slip, even as the rotation z is transmitted
mechanically to other shafts. This calls for torque amplification, and a variety of ingenious mechanism were introduced
for that purpose. The polarized light servomechanism for
torque amplification is shown schematically in Fig. 7. The integrating wheel, A, consists of a polarizing disk with a steel
rim and a steel hub. The direction of optical polarization is
shown by the direction of the crosshatch lines on the wheel.
The follow-up system consists of a pair of similar polarizing
disks B and C on the motor-driven output shaft D. The two
disks are mounted with their planes of polarization at right
angles to each other. Two beams of light pass through polarizer A and are polarized in the same direction. One light beam
passes through polarizer B, while the other passes through
polarizer C. The light beams are picked off by separate phototubes, which are connected through an amplifier to a splitfield series motor. Any difference in light intensity striking
the two phototubes will cause the motor to turn. This will
cause the output shaft D to assume an orientation with respect to wheel A so that the plane of polarization of wheel A
bisects the right angle between the two planes of polarization
of disks B and C. The output shaft D is thus constrained to
follow the motions of the integrating wheel, with only the
light beams as the coupling medium between them.
Note that the shafts representing the variables x and y can
be driven by the outputs of other integrators or by a separate
motor. For example, the turntable can be driven by a motor
at constant speed. In that case, integration with respect to
time is achieved. Multiplication of two dependent variables x
and y can be effected by connecting two integrators as shown
in Fig. 8, resulting in an output:


xy = x dy + y dx
(8)
In Fig. 8, conventional symbols are used to represent the integrators, adder, and shafts. The initial values of the product is

taken into account by providing suitable initial settings of the

two integrator wheels. Note that this equation would be much
more difficult to implement using an electronic analog computer, since electronic integrators are limited to integrating
with respect to time.
To illustrate the application of the mechanical differential
analyzer, consider first the almost-trivially simple problem of
finding the area under a curve. Specifically, a curve y f(x)
is shown plotted on a sheet of paper fastened to an input table I in Fig. 9(a). The curve starts at some value, x1, of the
independent variable x and ends at some other value x2. The
curve

z=

x1

y dx

(9)

x1

is to be plotted on the output table O. The differential equation corresponding to Eq. (9) is
dz
=y
dx

(10)

where y is given as a plotted function of x. The mechanical

differential analyzer system for generating this solution is
shown in detail in Fig. 9(a) and schematically in Fig. 9(b).
The variable y displaces the integrating wheel when the hand

z = xy

+
y
x

y dx

x dx

Figure 8. Schematic diagram showing the multiplication of two dependent variables x and y by implementing the formula for integration by parts, Eq. (8).

;;
;;
;
;
;;;;;;;;;
;;
;;
I

ANALOG COMPUTERS

457

x2 x

x1

Motor

(a)

x
z

Figure 9. Mechanical differential analyzer method for generating the area under a specified curve. (a) Detailed figure,
(b) schematic diagram.

(b)

crank on the input table is turned manually to keep a peephole on the given curve, while the x lead screw shifts the
peephole horizontally via the independent variable motor
drive. The motor also turns the integrator disk D. The integrator wheel W operates through a torque-amplifying coupling C to drive the vertical lead screw on the output table
O. A nut on this lead screw carries a pen P which traces the

curve z f(x), as a nut on the horizontal lead screw traverses

the x range.
Consider now a simple second-order differential equation
of the form
M

d2y
dy
+ ky = 0
+b
dx2
dx

(11)

458

ANALOG COMPUTERS

where M, b, and k are specified constants, and initial values

of y and dy/dx are also given. The solution process is

b

d2y
=
dx2
 x
dy
=
dx
0
 x
y=
0

k
dy
+
y
M dx M
d2y

dx + y(0)
dx2
dy
dx + y(0)
dx

(12a)
(12b)
(12c)

Assume that it is desired to plot y and dy/dx as functions of

x and that dy/dx is also required as a function of y and also
as a function of the second derivative of y with respect to x.
The mechanical differential analyzer implementation is
shown schematically in Fig. 10. All variable shafts are shown
as horizontal lines. Adders and the gear trains interconnecting the various shafts are shown at one end. Connections
from the various shafts are carried over to the integrators and
output tables by cross shafts. In a similar manner, systems of
simultaneous nonlinear differential equations with variable
coefficients can be solved.
Major mechanical differential analyzer facilities included
20 or more integrators and a substantial number of input and
output tables. Using high-precision mechanical components,
they were capable of solving complex engineering problems to
a higher accuracy than were the electronic differential analyzers that eventually replaced them. At the time they were,
however, very costly to construct and to maintain, and they
occupied an inordinate amount of space. Additional details
are discussed in Ref. 2.
Electronic Differential Analyzers (EDAs)
Electronic analog computers were first developed for military
applications during World War II. Subsequently, numerous
manufacturers entered into competition to provide progressively larger, more accurate, and more flexible general-purpose computers. The design of the electronic computer units
and the programming of EDAs is considered in detail in other
articles in this encyclopedia. General-purpose electronic dif-

ferential analyzers became available in installations ranging

from a modest 10 operational amplifiers to well over 2000 operational amplifiers. The accuracies of these computers in
solving nonlinear equations ranged from 2% of full scale for
relatively low-cost devices to better than 0.1% for the most
elegant models.
Very early in the development of electronic analog computers, it became apparent that there exist two distinct philosophies or approaches to the application of these devices. In one
class of analog computers, the time necessary to obtain a solution varies from approximately 10 s to several minutes. The
initial conditions and driving functions are applied at an instant of time corresponding to t 0, and continuous graphical
outputs are generated from selected points in the computer
system. This type of EDA is termed a long-time or one-shot
analog computer. The other class of differential analyzers operates on a greatly speeded-up time scale, so that solutions of
problems are obtained in several milliseconds. In that case,
the problem run is repeated automatically several times per
second, and the result of the computation is displayed on a
cathode-ray oscilloscope. Members of this second class are
termed repetitive or high-speed analog computers. While both
approaches had their enthusiastic adherents, the long-time
computer assumed a preponderant position by a wide margin,
in terms of both (a) the number of companies engaged in its
production and (b) the number of computers actually in use.
Almost all commercial long-time installations are designed around a centrally located patch-bay housed in a control console. Wires leading to the inputs and outputs of all
computer units and components are brought out to an array
of several hundred or even thousands of patch-tips. Removable problem boards, made of an insulating material, are machined to fit precisely over these tips in such a manner that
a clearly identified hole in the problem board lies directly over
each patch-tip. Most of the programming and connecting of
the computer can then be accomplished by means of patchcords interconnecting the various holes in the problem board.
Usually a considerable number of problem boards are available with each computer. Problems can be programmed on
these boards, which can be stored for subsequent experimen-

x
y

y
dy/dx

dy/dx

d 2y
dx2

dy/dx

k
y
M d 2y
dx2
b dy

M dx
y

dy/dx
x

Figure 10. Mechanical differential analyzer schematic for the solution of the second-order differential equation, Eq. (11).

dy
dx
dx

d 2y
dx
dx2

k
M

b
M

ANALOG COMPUTERS

Digital-analog
converters

459

Analog-hold
circuits

Demultiplexer
Demultiplexer

Buffer

Timing
and
control
unit

Digital data
processor

Analog
system
Recorders

Printer,
tape units
Analog-digital
converter
Buffer
(digital-hold)

Multiplexer

tal work while the computer is being employed to solve an

entirely different problem. In that manner, the computer installation is not tied-up by a single problem. A considerable
effort has been expended in optimizing the design of problem
boards to facilitate their use. Even so, the programming of
reasonably complex problems results in a veritable maze of
plug-in wires, a factor which not infrequently leads to errors
and makes debugging very difficult. To help alleviate this situation, most manufacturers introduced color-coded plug-in
connectors and multicolored problem boards, as well as special problem-check circuitry.
In addition to the patch-bay, the control console generally
includes the principal operating relays or solid-state switches
for resetting initial conditions and for commencing computer
runs, as well as potentiometers and amplifier overload indicators. One set of solid-state switches facilitates the connection
of direct-current (dc) power supplies to the outputs of all integrators for the setting of specified initial conditions. At the
start of the computer run, at t 0, all of these switches open
simultaneously, and at the same instant of time, other
switches connect the specified driving functions into the circuit. To repeat the computer run, the control switch is moved
from the compute to the reset position, and the identical
initial conditions are again applied. Frequently a control unit
includes a hold setting. In this position, all integrator capacitors are disconnected from the input resistors, so that they
are forced to maintain whatever charge they possess at the
instant the control switch is turned to the hold position. The
voltages at various points in the circuit can then be examined
at leisure.
The rest of the components are mounted in standard racks
in such a manner that the computer facility can readily be
expanded by purchasing and installing additional racks of
equipment. Precision resistors and capacitors are used
throughout; and in the more refined high-accuracy installations, all resistors and capacitors actually taking part in the
computing operation are kept in a temperature-controlled

Figure 11. Major components of a hybrid

(analog/digital) computer system of the type
widely used in the aerospace industry in the
1970s and 1980s for the design of systems
and for the training of pilots and astronauts.

oven so as to minimize drift errors. All computers have variable dc power supplies for the application of initial conditions
to the integrators and for the generation of excitations. The
output devices are generally mounted separately and may include direct-writing oscillographs for relatively high-speed recording, servo-driven recorders, and digital voltmeters. In addition, most analog facilities possess a number of multipliers,
resolvers for the generation of trigonometric functions, arbitrary function generators, Gaussian noise generators, and
time-delay units for simulating transport lags. Further details are presented in Refs. 3 and 5.
Hybrid (Analog/Digital) Computers
When relatively low-cost, on-line digital computers became
available in the late 1960s and 1970s, so-called hybrid computers became popular. Analog and digital computer units
were interconnected, using analogdigital and digitalanalog
converters, while a single control unit controlled all computers comprising the system. In such a hybrid computer, the
computing tasks were divided among the analog and digital
units, taking advantage of the greater speed of the analog
computer and the greater accuracy of the digital computer.
For example, in simulating a space vehicle, the guidance
equations were solved digitally, while the vehicle dynamics
were implemented on the analog computer. Such a hybrid
computer system is shown in Fig. 11. Further details are to
be found in Ref. 4.
Throughout the 1970s and well into the 1980s, hybrid computers played a crucial role in the development of many military and civilian aerospace systems, including guided missiles, aircraft and space vehicles, and so on, as well as in
training pilots and astronauts. By 1990, however, the development of minicomputers and microprocessors had reached a
level of performance that permitted all tasks formerly assigned to the analog computer to be performed digitally at
adequate speed and greatly reduced cost. This effectively

460

ANALOG FILTERS

spelled the end of hybrid computers as a tool for engineering

design and simulation.
BIBLIOGRAPHY
1. W. J. Karplus, Analog Simulation: Solution of Field Problems, New
York: McGraw-Hill, 1958.
2. W. J. Karplus and W. W. Soroka, Analog Methods: Computation
and Simulation, New York: McGraw-Hill, 1959.
3. R. Tomovic and W. J. Karplus, High-Speed Analog Computers, New
York: Wiley, 1962.
4. G. A. Bekey and W. J. Karplus, Hybrid Computation, New York:
Wiley, 1968.
5. A. S. Jackson, Analog Computation, New York: McGraw-Hill,
1960.

WALTER J. KARPLUS
University of California at Los
Angeles

494

ANALOG PROCESSING CIRCUITS

+
V

+
V+

Vout

Figure 1. General analog signal processing circuit.

In recent years, the trend to smaller and cheaper electronic

systems has resulted in mixed-mode integrated systems
where both digital and analog signal processing circuits are
manufactured in the same chip (3).
Analog signal processing circuits can be divided in two categories: linear and nonlinear circuits. Among linear circuits
for signal processing are filters (4) which use amplifiers,
adders, and integrators. High-frequency signal processing is
an area where analog circuits are the main signal processors.
For nonlinear analog signal processing, the most important circuits are data converters, where comparators are
widely used, as well as adders and integrators. Instrumentation and control (5) are also areas that use analog signal processing circuits intensively, for example, to measure ac signals or to control positioning motors.
This article is divided into two parts. The first part covers
linear circuits, such as adders and integrators, and circuits
that use them, such as filters. The second part covers nonlinear circuits, such as comparators, limiters, log and antilog
amplifiers, and their applications. Because most analog signal
processing circuits use operational amplifiers, a brief section
on op-amps is included.
OPERATIONAL AMPLIFIERS
An operational amplifier (op-amp), shown in Fig. 1, is a threeterminal device that has a high-input impedance Zin, a low
output impedance Zo, and a very high gain A (6). For an ideal
op-amp, these quantities are

Zin
Zo = 0

(1)

A
The op-amp inputoutput relationship is given by
Vout = A(V+ V )

ANALOG PROCESSING CIRCUITS

Analog signal processing is still the primary mode of signal
processing in many applications, despite the tremendous development in digital signal processing circuitry. For example,
at high frequencies signal processing is implemented with
very simple analog circuits. Very low-power applications are
also realized with analog circuitry. In addition, even in systems using digital signal processing, it is necessary to include
some form of analog signal processing and data conversion as
an interface for analog systems (1,2).

(2)

The input terminal with a plus sign is called the noninverting

input, and the input terminal with a minus sign is called the
inverting input.

+
V

+
+
V+

A(V+ V)

Vout

Figure 2. Operational amplifier characteristics.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

ANALOG PROCESSING CIRCUITS

Iout

IF

Rin

gm(V+ V)

+
V+

RF

Iin

Vin

495

+
Vout

Figure 3. Operational amplifier macromodel.

(a)

The op-amp variables are shown in Fig. 1. In addition to

Eqs. (1) and (2), the very high input impedance forces
I+ = I = 0

Vin

(3)

A macromodel for an ideal op-amp, where A , is given in

Fig. 2. Note that Zo 0, and Zin . Furthermore, because
Vout is finite when A , (V V) must be very small. That
is,
V+ = V

(4)

Another type of op-amp that has the macromodel shown in

Fig. 3, also has a high input impedance, but it has as the
output variable an output current given by (6)
Iout = gm (V+ V )

gm = gm (Ibias )

(6)

Because the gain factor for this op-amp is the transconductance gm, this op-amp is called an operational trasconductance
amplifier (OTA). The symbol for an OTA is shown in Fig. 4.
Usually, the OTA has a higher operating frequency than the
conventional voltage mode op-amp and thus, it is usually
found in high-frequency circuits.

LINEAR CIRCUITS FOR SIGNAL PROCESSING

The simplest circuit in linear signal processing is the inverting amplifier (2) shown in Fig. 5(a). Because no current
flows into the inverting input of the op-amp, by Kirchhoff s

Figure 5. Inverting amplifier. (a) Circuit; (b) block, diagram.

current law
Iin + IF = 0

+
V+

Iout

Iin =

Vin
Rin

(8)

iF =

Vout
RF

(9)

and

Thus,
V
Vin
+ out = 0
Rin
RF

(10)

which can be rewritten as

Vout =

RF
V
Rin in

(11)

Thus, the output voltage is given by the product of the input

voltage and the inverting amplifier gain RF /Rin. Figure 5(b)
shows a block diagram for the inverting amplifier. An inverting unity gain amplifier is obtained by making Rin
RF R as shown in Fig. 6. Now let us consider the circuit

+
Vin

(7)

In addition, because V 0 due to the infinite op-amp gain,

IF

Rin

Vout

(b)

(5)

Note that now the output impedance is infinite because the

output element is a current source. The value of the transconductance gm is a function of the bias current Ibias. Thus,

RF
Rin

K=

Rin

Iin

+
Vout

Ibias

Figure 4. OTA macromodel.

Figure 6. Inverting adder. (a) Circuit; (b) block diagram.

496

ANALOG PROCESSING CIRCUITS

K1 =

RF
R1

K2 =

RF
R2

K3 =

RF
R3

V1
R1
V1
R2

V2

RF

V2
R3

V3

V3

Vo

Vo

+
Rn
Vn

Vn
Kn =

Figure 7. Two input inverting adder. (a)

Circuit; (b) block diagram.

(a)

shown in Fig. 7 (8). The currents ik are

V1
R1
V
I2 = 2
R2
..
.

I1 =

(12a)

EXAMPLE 1. Figure 8(a) shows a two-input inverting adder.

The output voltage is given by

(12b)

and
Vo
RF

10 k
10 k
V
V
5 k 1
1 k 2

(17)

Thus,

(13)

Vo = 2V1 10V2

Furthermore, because no current flows into the inverting input, by Kirchhoff s current law
I1 + I2 + + In + IF = 0

(14)

V
Vn
Vo
V1
+ 2 + +
+
=0
R1
R2
Rn
RF

(15)

A more general inverting adder (2) is shown in Fig. 9.

Here each impedance Zi is given by the T-circuit in Fig.
10. The input short circuit impedances at nodes 1 and 2
are given by

Zsc (s) =

Solving for Vo,

R
R
R
Vo = F V1 F V2 F Vn
R1
R2
Rn

(18)

A block diagram is shown in Fig. 8(b).

Thus,


V1 (s) 
I2 (s) V

=
2 (s)=0


V2 (s) 
I1 (s) V

1 (s)=0

(19)

Z (s)Z2 (s) + Z2 (s)Z3 (s) + Z1 (s)Z3 (s)

= 1
Z2 (s)

(16)

5 k

10 k

V1

V1

1 k

V2

Vo
+

Figure 8. General inverting adder.

(b)

Thus, we have obtained an inverting adder. Each input is amplified by the factor RF /Ri. A block diagram for the inverting
adder is shown in Fig. 7(b).

Vo =

IF =

RF
Rn

(a)

V2

10

(b)

Vo

ANALOG PROCESSING CIRCUITS

10 k

Zo(s)

10 k

R2 = ?

Z1(s)

V1(s)

10 k

V1

Vo(s)
V2(s)

Z2(s)

Vn(s)

Zn(s)

497

Vo = 100 V1

Figure 11. Noninverting amplifier.

and

Figure 9. Tee network.

I2 =
As with the inverting adder, Kirchhoff s current law at node
Vg gives
Vn (s) Vo (s)
V1 (s) V2 (s)
+
+ +
+
=0
Z1 (s) Z2 (s)
Zn (s) Zo (s)

(20)

Zo (s)
Zo (s)
Zo (s)
V1 (s)
V2 (s)
V (s)
Z1 (s)
Z2 (s)
Zn (s) N

(21)

V
I1 = 1
R1

(22)

V1

Z3

V
Vo V1
= 1
R2
R1

(25)

R1 + R2
V1

R1 R 
= 1 + 2 V1
R1

(26)

Vo =

We readily see that the amplification factor for the noninverting amplifier is always greater than unity.
EXAMPLE 3. If we desire to design a noninverting amplifier
with a gain of 3, we can choose R2 2 k and R1 1 k.
Thus,
R2
2 k
=3
=1+
R1
1 k

(27)

The final circuit is shown in Fig. 13.

I2
Z1

(24)

Solving for Vo,

1+
I1

I2 = I1
Thus,

EXAMPLE 2. We want the circuit shown in Fig. 11 to have

an inverting gain of 100. By solving Eq. (19) with R1 R3
10 k, R2 102.04 .
A noninverting amplifier is shown in Fig. 12. Because the
op-amp forces the inverting input voltage to be equal to the
noninverting input voltage, the currents I1 and I2 are given
by

(23)

Using Kirchhoff s current law at the inverting input node,

Solving for Vo,

Vo (s) =

Vo V1
R2

V2

R2
Z2

I2
R1
I1

Figure 10. Amplifier with a gain of 100.

Vo(s)
V1(s)

Figure 12. Noninverting amplifier with a gain of three.

498

ANALOG PROCESSING CIRCUITS

2 k

1 k

Vo(s)

V1(s)

V1(s)

Vo(s)
+

Figure 15. Differential amplifier.

Figure 13. General noninverting amplifier.

A general inverting amplifier is shown in Fig. 14. Similarly to the noninverting amplifier, the output voltage is given
by



Z (s)
V (s)
Vo (s) = 1 + 2
Z1 (s) 1

(28)
Vo =

As before, the gain is noninverting and greater than unity. If

Z2(s) 0 (short circuit), the circuit equation is
Vo (s) = V1 (s)

(29)

that is, we have a unity gain amplifier. Note that Z1(s) has no
effect and can be deleted (an open circuit.) The resulting circuit, shown in Fig. 15 is also called a voltage follower because the output voltage follows the input voltage. Now let
us consider the circuit (9) in Fig. 16. Voltage V is given
by
V+ =

R3
V
R2 + R3 2

Thus, we see that the circuit takes the difference of the input
voltages. Therefore, this circuit is called a differential amplifier. By choosing Ro R3 and R1 R2, we can write Eq. (33)
as

which gives the input voltage difference amplified by the factor Ro /R1.
EXAMPLE 4. It is desired to find an amplifier whose output
voltage is given by
Vo = 10(V2 V1 )

R1

Ro
R1
V +
V
Ro + R1 1 Ro + R1 2

V1

Ro

(31)

Vo
+

Because the op-amp forces both voltages V and V to be

equal,
Ro
R1
R3
V =
V +
V
R2 + R3 2
Ro + R1 1 Ro + R1 2

(34)

(30)

Using superposition, voltage V is given by

V =

Ro
(V V1 )
R1 2

R2

R3

V2
V+

(32)

(a)

Solving for Vo,

Vo =

R3 (Ro + R1 )
Ro
V
V
R1 (R2 + R3 ) 2 R1 1

(33)

R1
V1

Ro

Vo
Z1(s)

Z2(s)

R1

Vo(s)
V1(s)

Figure 14. Voltage follower.

R0

V2
V+
(b)
Figure 16. Differential amplifier with a gain of 10.

ANALOG PROCESSING CIRCUITS

1 k

499

Defining impedances ZA(s) and ZB(s) by

10 k

V1

1
=
ZA (s)

m

1
1
1
+
+
ZIS (s) i=1 ZIi (s) Zo (s)


(37)

Vo
+
1 k

and

10 k

1
=
ZB (s)

V2

n

1
1
+
ZNS (s) k=1 ZNk (s)


(38)

and because for an ideal op-amp,

Figure 17. General inverting and noninverting amplifier.

VA = VB
By choosing Ro R3 10 k and R1 R2 1 k in Fig. 16,
we obtain the desired output voltage. The final circuit realization is shown in Fig. 17.
A differential amplifier (2) can be extended to the general
combined inverting and noninverting amplifier shown in Fig.
18. Kirchhoff s current law at nodes A and B gives

VA

1
1
1
1
+
+ +
+
ZIS (s) ZI1 (s)
ZIm (s) Zo (s)
=

from Eqs. (35)(39) we can write

(35)

 
n
VNk (s)
1
1
1
+
+ +
=
ZNS (s) ZN1 (s)
ZNn (s)
Z (s)
k=1 Nk

(40)

n

VNk (s)
VB
=
ZB (s) k=1 ZNk (s)

(41)

Finally, from Eqs. (40) and (41) together with Eq. (39), we can
write
m

VB
Vo
VIi (s)
=
+
Zo (s)
Z
(s)
Z
Ii
A (s)
i=1

and
VB

m
Vo (s) 
VA
VIi (s)
=
+
ZA (s)
Zo (s) i=1 ZIi (s)

and

m
Vo (s) 
VIi (s)
+
Zo (s) i=1 ZIi (s)

(36)

V (s)
+ I2
+VI1(s)

ZI2(s)

GIi (s) =

ZI1(s)

Zo(s)

VA

V (s)
+ N2

V (s)
+ Nn

ZN2(s)

ZNn(s)

(44)

GNk (s) =

ZB (s) Zo (s)
ZA (s) ZNk (s)

(45)

The values of ZIS(s) and ZNS(s) can be picked such that

ZA(s) ZB(s), so that the noninverting gains are given by
GNk (s) =

....
......

Zo (s)
ZIi (s)

ZN1(s)

....

V (s)
+ N1

....

(43)

and each noninverting input has a gain given by

Vo(s)
VB

This equation allows us to design combined inverting and

noninverting adders. Each inverting input has a gain

ZIS(s)

....

....

ZIm(s)

...

V (s)
+ Im

(42)

Solving for Vo,

n
m
VNk (s) 
VNi (s)
ZB (s) 

Vo (s) = Zo (s)
ZA (s) k=1 ZNk (s) i=1 ZIi (s)

(39)

ZNS(s)

Figure 18. Inverting and noninverting adder.

Zo (s)
ZNk (s)

(46)

EXAMPLE 5. Consider the circuit in Fig. 19(a). Suppose we

want
V0 = 2VN1 + 3VN2 4VI1 2VI2

500

ANALOG PROCESSING CIRCUITS

RIS
RI1

Ro

50 k

VI1

100 k

VI1
RI2

VN1

50 k

VI2

VI2
Vo

+
RN1

VN2

Vo

VI1

RNs

VN1

50 k

20 k

VI2

VN1
RN2

+2
+3
2

Vo

33.3 k

VN2

VN2
(a)

(c)

(b)

Figure 19. Inverting and noninverting amplifier. (a) Schematic circuit; (b) block diagram.

We start by picking Ro 100 k. We set RA RB by a proper

choice of RIS and RNS (usually this can be done by making any
one infinite.) From our desired output

GN1 = 2

From Eqs. (37) and (38)

RA = RIS RI1 RI2 R0 = RIS 20 k
RB = RNS RN1 RN2 = RNS 25 k
By setting RIS ,

GN2 = 3

RA = 20 k

GI1 = 2
GI2 = 2

Then, the value that makes RA RB is

RNS = 100 k

From Eq. (46) for the noninverting gains

RN1

The final circuit is shown in Fig. 19(b), and a block diagram

is shown in Fig. 19(c).

Ro
100 k
=
=
= 50 k
GN1
2

INTEGRATORS

and
RN2 =

Integrators are basic building blocks in analog signal processing (10). For example, state variable filters such as the
KHN (11) and TowThomas (12) filters are based on integrators within a loop. The most popular integrator circuit is
the inverting Miller integrator depicted in Fig. 20. For an
ideal op-amp, its transfer function is given by

Ro
100 k
= 33.3 k
=
GN2
3

and for the inverting gains

RI1 =

Ro
100 k
=
= 50 k
GI1
2

1
Vout
=
Vin
sRC

and
RI2

(47)

As can be seen, this integrator has its pole at the origin.

Another widely used integrator circuit is the inverting
lossy integrator shown in Fig. 21. Its transfer function is

Ro
100 k
= 50 k
=
=
GI2
2

R2
C

C
R1

R
Vin

Vin

Vout
+

Figure 20. Miller inverting integrator.

Vout
+

Figure 21. Lossy inverting integrator.

ANALOG PROCESSING CIRCUITS

V+

+
V

Vin
+

Vout

1
R1 C
1
s+
R2 C

(48)

From this transfer function we see that a pole is located on

the negative real axis at
1
s=
R2 C

(49)

Now if we take into account the finite op-amp gain A0, routine
circuit analysis gives the inverting Miller integrator transfer
function as
Vout
A0
=
Vin
1 + (1 + A0 )sRC

(50)

Note that the pole shifts from the origin to a location on the
negative real axis given by
1
(1 + A0 )RC

of these dc errors, the integrator output consists of two components, namely, the integrator signal term and an error
term. Thus, now Vout is given by


1
1
Vout (t) =
Vin (t) dt +
Vos (t) dt
RC
RC

(52)
1
ID (t) dt + VDS
+
C
An option for high-frequency applications is using an operational transconductance amplifier (OTA). Because Iout
gm(V V) in an OTA, by loading the OTA with a capacitor,
as shown in Fig. 22, we obtain (13)
Vout =

Vout
=
Vin

(53)

gm
C
1
s+
RC

(54)

We can also realize a lossy integrator by producing a resistor

with the OTA, as shown in Fig. 25. In this case the transfer
function achieved is given by

gm
Vout
C
=
gm
Vin
s+
C

Vout

(55)

If we require realizing Eq. 55 with different numerator and

denominator coefficients, then we can use an additional OTA
to produce the resistor, as shown in Fig. 26. The resulting

gm (V+ V )
Iout
=
sC
sC

If any one of the input voltages is zero, we obtain either an

inverting or a noninverting integrator, as shown in Fig. 23 for
an inverting integrator. Note that OTA-based integrators are
open loop integrators. We can realize a lossy integrator with
the circuit in Fig. 24. In this case the transfer function is
given by

(51)

Because A0 is very large, this pole is very close to the origin

but on the negative real axis. Thus, the Miller integrator for
very high frequencies behaves like a lossy integrator.
Other sources of error in the inverting Miller integrator
are the op-amp dc offset voltage and bias current (8). Because

Vout

Figure 24. OTA-based lossy integrator with external resistor.

given by

Vin

Figure 22. OTA based integrator.

s=

Vout
=
Vin

501

(a)

Vin

+
C

Vout

Vin

Vout

(b)
Figure 23. (a) Non-inverting integrator. (b) Inverting integrator.

Figure 25. OTA-based lossy integrator without external resistor.

The OTA feedback realizes the resistor.

502

ANALOG PROCESSING CIRCUITS

NONLINEAR ANALOG SIGNAL PROCESSING CIRCUITS

Vin

+
gm1

gm2

The general form of a nonlinear analog signal processing circuit (2) is shown in Fig. 29, where f is a nonlinear function of
the current IN. In Fig. 29, the output voltage is given by

Vout

Vout = f (IN )

Figure 26. OTA-based lossy integrator with different coefficients.

(57)

Because no current flows into the inverting input of the opamp

IN = I1 I2

transfer function is given by

gm1
Vout
C
=
g
Vin
s + m2
C

(56)

(58)

and, because the inverting input voltage is zero due to the

infinite gain
I1 =

Vin1
R1

(59a)

I2 =

Vin2
R2

(59b)

There are some advantages when using OTAs in integrators:

and
1. The operating frequency range is greatly increased.
2. The dynamic range is also increased because now we
have a current as the output variable for the operational amplifier.
3. Modern OTAs require lower supply voltages.
EXAMPLE 6. As an application of integrators, let us consider
the circuit shown in Fig. 27. This circuit is known as a state
variable filter, or KHN filter (11), after its inventors. As can
be seen, this circuit is formed by two Miller inverting integrators and an inverting and noninverting adder. The transfer function is given by



1 + R6 /R5 s

VBP (s)
1 + R3 /R4 R1C1
=
s
R6 /R5
1 + R6 /R5
V1 (s)
s2 +
+
R1C1 1 + R4 /R3
R1 R2C1C2

Thus,
Vout = f

Vin1 Vin2

R1
R2


(60)

COMPARATORS

The first op-amp realizes the adder and the last two op-amps
realize the integrators.

A comparator is a circuit that has the transfer characteristic

shown in Fig. 30. Here we have a comparison level ER. The
function of this circuit is to compare the input voltage Vin with
the reference voltage ER and decide which one is larger. The
ideal comparator is described by

Vin > ER
L+
Vout = 0
(61)
Vin = ER

L
Vin < ER

EXAMPLE 7. Another very popular filter realization is the

TowThomas filter (12). This filter is shown in Fig. 28(a). It
consists of a lossy integrator followed by a noninverting integrator. The noninverting integrator is formed by a Miller inverting integrator cascaded with a unity inverting amplifier.
An alternative realization of this filter using OTAs is shown
in Fig. 28(b).

This function is plotted in Fig. 31.

Now let us consider the circuit shown in Fig. 32. The function f() is realized by a zener diode [see Fig. 33(a)] for which
an ideal description is given by

IN < 0
Ez
f (iN ) =
(62)
0
IN > 0

R5

C1

R3
+
V1

Figure 27. KHN biquad filter.

R6

R1

C2

+
+

R4

R2
+
VBP

ANALOG PROCESSING CIRCUITS

503

C2

C1
RQ

Rin

+
V1

R1

VBP

+
+

(a)

+
gm1
+
V1

VBP

gm2
+
C2

C1

Figure 28. TowThomas biquad filter.

(a) With voltage mode op-amps; (b) with
OTAs.

(b)

Vout

R1

I1

IN

L+

Vin1
R2
Vin2

I2

ER

Vin

Vout = (In)
+

Figure 31. Transfer characteristic for a comparator.

Figure 29. General nonlinear signal processing circuit. F is a nonlinear function.

R1
Vin

Clamp

R2

Vout
+

VREF

RB

Vin
Vout

RA

ER
Figure 30. Block diagram for a comparator circuit.

Figure 32. Comparator circuit.

504

ANALOG PROCESSING CIRCUITS

IN

Vout

Forward
biased

IN
+
vD

EZ

VREF R1
R2

vD

Vin

Reversed
biased

(a)

EZ

(b)

Figure 33. Zener diode. (a) Symbol and variables; (b) I-V characteristic.

as shown in Fig. 33(a). For our circuit,

Vin
R1

(63)

VREF
R2

(64)

I1 =
and
I2 =
The current IN is given by
IN =
Thus,
Vout = f

Vin VREF

R1
R2

Vin VREF

R1
R2

(65)

Figure 35. Transfer characteristic for the comparator from Fig. 32

with the zener diode reversed.

that is, the circuit compares the input voltage Vin with the
reference voltage VREFR1 /R2. If Vin is either smaller or
greater than VREFR1 /R2, then Vout is chosen according to Eq.
(62). Thus the circuit is a comparator. Its transfer characteristic is shown in Fig. 34. This is equal to the comparator characteristic from Fig. 31 with a sign reversal. By reversing the
diode, we get the characteristic shown in Fig. 35. Figure 36
shows a bipolar comparator using a double-anode zener diode.
Using two zener diodes with different zener voltages we obtain different output voltages.
A related circuit is the limiter whose function is shown in
Fig. 37. A limiter is realized by adding resistive feedback to a
comparator, as shown in Fig. 38(a). The circuit acts as a voltage amplifier with gain RF /Rin as long as the output voltage
is between Ez2 and Ez1. When this condition does not hold,
then the output is clamped either to Ez1 for positive output
voltage or to Ez2 when the output voltage is negative. Thus,
the two zener diodes act as a level clamp or feedback limiter

(66)

Using Eq. (62) in Eq. (66),

Vout =

E z

Vin

R1
R2
R
Vin > VREF 1
R2
Vin < VREF

Rin

Vout
+

(67)

(a)

Vout

Vout
EZ

VREF R1
R2

Vin

Vin

(b)
Figure 34. Transfer characteristic for the comparator from Fig. 32.

Figure 36. Comparator using double-anode zener diodes. (a) Circuit;

(b) transfer characteristic.

ANALOG PROCESSING CIRCUITS

Vin

Vout

Figure 37. Block diagram for a limiter circuit.

whose purpose is to limit output level excursions but otherwise do not affect the inverting amplifier behavior. This characteristic is shown in Fig. 38(b).
Let us consider the circuit in Fig. 39(a). There are two combinations of possible diode states.
1. D1 ON, D2 OFF. If Vin is sufficiently positive, Vout will be
sufficiently negative and eventually e1 reaches 0 V, and
D1 turns on. Node e1 acts as a virtual ground, and the
output voltage is given by [see Fig. 39(c)]
Vout =

E 1 RB
RA

(68)

2. D1 OFF, D2 ON. This state is reached when Vin is negative. Then Vout becomes positive, e2 is eventually 0 V,
and D2 turns ON. Similar to state 1, the equivalent circuit is shown in Fig. 39(d), and Vout is given by
Vout = +

E 2 RD
RC

(69)

3. The transfer characteristic is shown in Fig. 39(b). The

slopes in the limiting region are given as follows:
For state 1,
dVout
R
= B
dVin
RA

(70)

characteristics. This comparator is called a soft comparator

because there is rounding in the corners and nonzero
slopes.
A hard comparator, where the clamp levels are well controlled, is shown in Fig. 40. The input-output transfer characteristic for the comparator is shown in Fig. 41. Here the diodes are substituted by transistors. The operation is similar
to the comparator from Fig. 39, but the slopes are reduced by
the transistors s (2).

Suppression of Leakage Currents and Stray Capacitances

If the design calls for a precision comparator where the clamp
levels are to be as accurate as possible, then we have to suppress leakage currents from the diodes D1 and D2 in the clamp
circuit which tend to create an offset error similar to an opamp offset current. In addition, the use of low resistance values helps to improve circuit speed and reduces the effects of
offset currents and parasitic capacitances. The comparator of
Fig. 39 is improved in Fig. 42 with extra diodes D3 and D4
and resistor R5 to suppress leakage currents and establish
precision comparator levels (2).

HYSTERESIS
A comparator is improved by adding positive feedback to create a hysteresis loop. Hysteresis is usually added to a comparator to give some noise immunity. Figure 43 shows an
example (2) where hysteresis adds noise immunity to a
comparator. Let us consider the circuit shown in Fig. 44
which is a comparator with positive feedback added. Without the positive feedback, a fast amplifier presents a positive oscillation at the output [see Fig. 43(a).] If the amount
of positive feedback is small, the amount of hysteresis in
Fig. 45 is given by

and for state 2,

EH =
dVout
R
= D
dVin
RC

RA E W
RA + E W

(72)

(71)

As can be seen the slopes are nonzero. In addition there

is rounding in the corners because of the nonideal diode

D1

505

D2

And, usually, EH is small, on the order of 10 mV to 20 mV.

Figure 43(b) shows how noise immunity has been added to
the comparator.

Vout
E Z1

RF

Vin
Rin

Vout
+

(a)

E Z2

(b)

RF
Rin

Vin

Figure 38. Limiter circuit. (a) Schematic

circuit; (b) transfer characteristic.

506

ANALOG PROCESSING CIRCUITS

+E1 > 0

RA

Vout

D1

E 2R C
RD

e1
Rin

RB

vin

Vout

Vin

+
RC

D2

E 1R B
RA

RD

E2 < 0
(a)

(b)

+E1 > 0

RA
RB

RA
E1

Rin
e1

RB

Vin
Vout

Vout

+
RC

RD

E2 < 0
(c)

(d)

Figure 39. Improved comparator. (a) Schematic circuit; (b) transfer characteristic; (c) equivalent
circuit for state 1; (d) equivalent circuit for state 2.

A more accurate circuit is shown in Fig. 46. The dimensions of the hysteresis loop are given by

R E
L+ = 2 P
R1
R E
L = 3 N
R4
R R E
S+ = 3 6 P
R4 R7

and
S =

(73a)

R2 R6 E N
R1 R7

(73d)

The hysteresis loop is shown in Fig. 47.

(73b)

LOGARITHMIC AMPLIFIERS

(73c)

Logarithmic amplifiers, simply called log amplifiers (8), are

extensively used to produce multipliers and signal compres-

ANALOG PROCESSING CIRCUITS

and

+E1

IC = I1 =

RA

D1

507

Vin
R1

(77)

then
Q1
Rin

V0 =

RB

RF

kT Vin
ln
q
RIS

(78)

Vin

Vout
+
RC

Q2

D2

RD

E2 < 0
Figure 40. Transistor-based improved comparator.

sors. Figure 48 shows a basic log amplifier circuit. Note that

the transistor collector is connected to the virtual ground
node. Because the base is also grounded, the transistor voltagecurrent relationship is
IC = aIS (e

qV0 / kT

1)

Thus, we obtain an output voltage proportional to the logarithm of the input voltage. The only constraint is that Vin 0.
External compensation is usually needed (2) for frequency
stability. This compensation can be achieved with a capacitor
CC in parallel with the feedback element which in our case is
the transistor. Unfortunately, this solution lowers the gain as
the operating frequency increases. To compensate for this, we
add a series resistor rC in series with the emitter, placing a
limit on the negative feedback resistance through the transistor. This scheme is shown in Fig. 49. Values for CC and rC are
best determined empirically because parasitic effects play a
large role but they are usually in the range of 100 pF for CC
and 1 k for rC. Note that Eq. 78 for the log amplifier is temperature-sensitive. Furthermore, IS is also temperature-dependent. A solution for this problem is provided by the circuit
shown in Fig. 50. Resistor RTC has a positive temperature coefficient. It can be shown that

Vout = 1 +

R2
RTC

 kT
q

ln

Vin
VREF

(79)

(74)

Where kT/q 25 mV at 25C. Equation 74 can be rewritten

as
V0 =

kT
ln
q

I0
+1
aIS

+E1 > 0

(75)
D3

Also, because 1

RA

I0

1
aIS

D1

(76)
R

RB

D4

RC
2R 1

Vout
Slope

Vin

Rin

E 2R C
RD

+
Rin

Vin

E 1R B
RC
Slope

RB
1R 1

Figure 41. Transfer characteristic for the comparator from Fig. 40.

RC

D2
VREF

Vout

RD

E2 < 0
Figure 42. Scheme to reduce leakage currents and stray capacitance.

508

ANALOG PROCESSING CIRCUITS

Vin

Vout

ER

E R1

t
E R2
(a)

Vin

Vout

ER

E R1

Figure 43. Noise immunity in comparator circuits. (a) Comparator without positive feedback;
(b) comparator with positive feedback. The noise
immunity is evident.

E R2
(b)

Note that as T increases, the factor kT/q also increases, but

because RTC has a positive temperature coefficient, the first
factor in Eq. 79 decreases. By properly matching temperature
coefficients and resistor values, negligible variation of Vout
with temperature is achieved.

R1
Vin

Antilog Amplifiers
A basic antilog amplifier (8) is shown in Fig. 51. Because

Vout = 1 +

R2
RTC

 kT
q

ln

Vin
VREF

Vout

Clamp

R2

Vout

EH

VREF

RB

Vin

EW

RA
VREF R1
R2
Figure 44. Comparator with added positive feedback to provide hysteresis and noise immunity.

Figure 45. Hysteresis loop for the comparator in Fig. 43.

(80)

ANALOG PROCESSING CIRCUITS

+E1

509

Q1

D3
R1
D4
Vin

D1

CC

Rin

R6

R5

R2

Vin

A1

Vout

Vout

R1

Q2

R3

D2
R4

rC

CC

Rin

RTC

E2

R7

A2

VREF

Figure 46. Improved circuit with hysteresis loop.

Figure 50. Improved temperature-insensitive logarithmic amplifier.
Includes compensation circuit.
Vout

IC

L+

IR

Vin
RF

Q1
S

S+

Vout

Vin

Figure 51. Antilog amplifier.

Q1

Figure 47. Hysteresis loop for the circuit in Fig. 46.

Q1

rC

Rin

Vin

R1

Vout

CC
Vout

+
Q2

Figure 48. Logarithmic amplifier.

Rin
Vin
Q1

RTC
rC

CC

R1

CC

Rin
Vin

Vout
+

Figure 49. Logarithmic amplifier with compensation.

VREF

Figure 52. Improved antilog amplifier.

510

ANALOG-TO-DIGITAL CONVERSION

Vin1

k1 ln Vin1

Log
amp

+
Figure 53. Multiplier circuit realized
with log and antilog amplifiers.

Vin2

Log
amp

(81)

This is equivalent of saying that Vout is the antilog of Vin. This

circuit has the same drawbacks as the log amplifier for stability and temperature dependence. A better circuit is shown in
Fig. 52 which includes the compensation circuit (2).
It can be shown that



RTC
q
Vout = VREF exp Vin
(82)
kT R2 + RTC
EXAMPLE 8. The most popular application of log and antilog
amplifiers is in the realization of multipliers. Figure 53 shows
a block diagram of such a multiplier. Each input is fed into a
log amp. Then, the logs of the inputs are summed. Recall that
the sum of the logarithms is the logarithm of the product.
Finally, the antilog amp outputs this product. Then the output has the form
Vout = K Vin1 Vin2

Antilog
amp

k4 Vin1 Vin2

k2 ln Vin2

For Vout, assuming 1 and IC /IS 1, we obtain

Vout = RIS e qVin /kT

k3(ln Vin1 + ln Vin2)

(83)

3. F. Dielacher, Design aspects for mixed analog-digital circuits, in

W. Sansen, J. H. Huijsing, and R. J. Van de Plassche, (eds.), Analog Circuit Design, Mixed A/D Circuit Design, Sensor Interface
Circuits and Communication Circuits, Dordrecht: Kluwer, 1994.
4. L. P. Huelsman, Active and Passive Analog Filter Design, New
York: McGraw-Hill, 1993.
5. S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Converters, New York: IEEE Press, 1996.
6. G. E. Tobey, J. G. Graeme, and L. P. Huelsman, Operational Amplifiers, New York: McGraw-Hill, 1971.
7. J. Silva-Martnez, M. S. J. Steyaert, and W. C. Sansen, A largesignal very low distortion transconductor for high-frequency continuous-time filters, IEEE J. Solid State Circuits, SC-27: 1843
1853, 1992.
8. J. M. Jacob, Applications and Design with Analog Integrated Circuits, Reston, VA: Reston, 1982.
9. I. M. Faulkenberry, An Introduction to Operational Amplifiers
with Linear IC Applications, New York: Wiley, 1992.
10. A. S. Sedra and P. O. Bracket, Filter Theory and Design: Active
and Passive, Portland, OR: Matrix, 1978.
11. W. J. Kerwin, L. P. Huelsman, and R. W. Newcomb, State-variable synthesis for insensitive integrated circuit transfer functions, IEEE J. Solid-State Circuits, SC-2: 8792, 1967.

where K is a constant that depends upon the circuit parameters. The only limitation in the circuit is that the input signal
and reference voltage must have the same polarity for each
log amplifier. Thus, our multiplier is a one-quadrant multiplier.

12. L. C. Thomas, The Biquad: Part I-Some practical design considerations, IEEE Trans. Circuit Theory, CT-18: 350357, 1971.

Other useful applications of multipliers are frequency doublers, amplitude modulation, phase detection, oscillators, and
automatic gain control (9).

15. J. G. Graeme, Applications of Operational Amplifiers, Third Generation Techniques, New York: McGraw-Hill, 1973.

CONCLUDING REMARKS

17. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, New York: McGraw-Hill, 1998.

We have presented circuits for analog signal processing. The

circuits are all based on operational amplifiers. Although the
most commonly used op-amp is the conventional voltage mode
op-amp, simply called op-amp, we have also included the operational transconductance amplifier (OTA) usually found in
high-frequency integrated circuits. The circuits presented are
those currently used in analog signal processing, and in many
cases they are off-the-shelf parts.
BIBLIOGRAPHY
1. C. Tomazou, J. B. Hughes, and N. C. Battersby, Switched-Currents, An Analogue Technique for Digital Technology, London: Peregrinus, 1993.
2. J. V. Wait, L. P. Huelsman, and G. A. Korn, Introduction to Operational Amplifier Theory and Applications, 2nd ed., New York:
McGraw-Hill, 1992.

13. D. Johns and K. Martin, Analog Integrated Circuit Design, New

York: Wiley, 1997.
14. B. Nauta, Analog CMOS Filters for Very High Frequencies, Dordrecht: Kluwer, 1993.

16. A. Barna and D. I. Porat, Operational Amplifiers, New York: Wiley, 1989.

DAVID BAEZ-LOPEZ
University of the Americas-Puebla
National Institute for Astrophysics,
Optics, and Electronics

510

ANALOG-TO-DIGITAL CONVERSION

ANALOG-TO-DIGITAL CONVERSION
Analog-to-digital (A/D) converters (ADCs) constitute the key
interface function between analog signals in the physical
world and digital signal processing systems. The importance
of integrated ADCs has grown enormously in recent years, in
line with the increasing importance of mixed analog-digital
VLSI systems. Indeed, with the powerful digital signal processing engines available today the fidelity and accuracy of
digitally processed analog signals is fundamentally limited by
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

ANALOG-TO-DIGITAL CONVERSION

Vin

ADC

.
.
.

511

Quantization error

b1
b2
b3

LSB

bN

Vref

1 LSB
Vin
Figure 1. Symbol of an ADC.

LSB

the performance of ADCs rather than by any meaningful digital circuitry limitation. Moreover, given the continuing need
to achieve higher integration functionality at minimum cost
and with minimum energy consumption, the design of ADCs
is becoming increasingly tailor-made to specific applications
rather than, as not long ago, being considered as general purpose components (1). As a result, a wide variety of ADC architectures and circuit design techniques has emerged in recent
years, ranging from low to high conversion frequency as well
as from high to low conversion resolution. The most relevant
of such conversion architectures and circuit design techniques
are described in this article.

FUNDAMENTAL ASPECTS OF A/D CONVERTERS

Figure 3. Quantization error produced by an ADC when the input

signal is a ramp.

where Vref is the reference voltage of the converter and

n=

Vref
2N

(3)

Quantization Noise. Even assuming that the conversion

characteristic of an ADC is ideal, the quantization process
produces a quantization error signal that is a function of the
conversion resolution. This is often called the quantization
noise of the converter (2). Figure 3 illustrates the shape of
such a quantization error signal when the input signal is a
ramp. Assuming that the maximum quantization error is uniformly distributed between LSB/2 and LSB/2, then it can
be shown that the total quantization noise power can be expressed as
PQ =

(1)

LSB2
12

(4)

In most practical cases the quantization noise power is

uniformly distributed in the Nyquist frequency band from dc
to Fs /2, as depicted in Fig. 4, such that the corresponding
power spectral density SQ2 ( f) is expressed as

Digital output
111
110

(2)

represents the output digital code. The difference between

two consecutive quantization levels is usually designated the
least significant bit (LSB) of the converter. From Eq. (1) this
is given by
LSB =

Ideal Conversion Characteristic. An ADC is usually represented by the symbol indicated in Fig. 1, where the number
of bits N of the output digital word indicates the conversion
resolution. The conversion characteristic of an ADC is obtained by determining the transition voltages (VT)n of the input analog signal that produce a change of the output digital
code. The time interval between two consecutive input samples indicates the sampling period Ts. The conversion frequency is Fs 1/Ts.
Figure 2 illustrates a portion of the ideal conversion characteristic of an ADC. The analog input transition voltages are
defined by
VT n

2i1 bi

i=1

Conversion Between Analog and Digital Samples

V
= ref
n
2N

N


S2Q ( f ) =

LSB

LSB2
12

2
Fs


(5)

101
100
S Q( f )

011
010
LSB
12

001
000

VT1 VT 2 VT3 VT4 VT 5 VT6 VT7 Vref Vin

Figure 2. Ideal conversion characteristic of an ADC.

2
Fs
0

Fs /2

Figure 4. Uniform power spectral density of the quantization noise.

512

ANALOG-TO-DIGITAL CONVERSION

For any given frequency band within the Nyquist band, that
is, from dc to f c Fs /2, the total noise power is given by

fc
0

LSB 1

12 Fs /2

2
df =

LSB2
12

2 fc
Fs


(6)

Digital output
111

1 - Offset error

110

2 - Full-scale error

101

Equation (6) indicates two possible solutions for reducing

the quantization noise of a converted signal at a given frequency. One solution is to reduce the converter LSB by increasing its resolution N, whereas the alternative solution
corresponds to having a conversion frequency much higher
than the signal being converted. This is called oversampling
and the factor of oversampling the signal would be defined by
(Fs /2)
OSR =
fc

(7)

Increasing the resolution of an ADC gives a reduction of the

noise power of approximately 6 dB per added bit of resolution.
As this would be guaranteed over the full Nyquist range, such
type of converters are called Nyquist converters. In the socalled oversampling converters, a further reduction of the
quantization noise power is obtained by oversampling the signal with respect to the Nyquist frequency; it yields an additional gain of approximately 3 dB per octave of oversampling.
Dynamic Range of a Quantized Signal. The dynamic range
of a quantized signal is commonly determined with respect to
a sinusoidal waveform between 0 and Vref , whose power is
2
Vref
/8. Thus, from Eq. (4), the resulting signal-to-noise (SNR)
ratio of the quantized signal will be given by




2
/8
Vref
Pin
= 10 log
(8)
SNR(dB) = 10 log
PQ
LSB2 /12
From Eq. (3) this results in


3 2N
2
= (6.02N + 1.76) dB
SNR(dB) = 10 log
2

(9)

For example, the conversion of an analog sine waveform using

a 10-bit ADC will lead to a digital sine waveform with an
SNR of approximately 61.8 dB.
Conversion Codes. When an ADC operates with only positive (or negative) signals its output is normally a natural binary code. There are many cases, however, when the ADC
has to operate with both positive and negative signals, thus
resulting in the need to produce both positive and negative
output digital codes. Two of the most popular of such codes
are the sign magnitude code and the 2s complement code.
In the sign magnitude code, negative and positive digital
numbers are represented by the same code except for the
most significant bit (MSB): for positive codes MSB 0,
whereas for negative codes MSB 1. For example, the signmagnitude representation for 7 is 0111, whereas for 7 it is
1111.
In the 2s complement code, positive codes are represented
as natural binary codes with MSB 0. The negative codes
are obtained from the equivalent positive number by first
complementing all the bits and then adding 1 LSB. For exam-

100
011
010
001
000

1
0

VT1 VT 2 VT3 VT4 VT 5 VT6 VT7 Vref Vin

Figure 5. Illustrating offset, full scale and gain errors of an ADC.

ple, for the representation of 7 we obtain first 0111 (corresponding to the positive number 7), then we obtain 1000
(corresponding to the complement of all bits of 0111) and finally we obtain code 1001 (adding 1 LSB to 1000). An important advantage of the 2s complement code is that the addition
of both positive and negative numbers is made by straightforward addition and no extra computations are needed. For example, 0111 (number 7) added to 1001 (number 7) gives
0000 (of course the carry bit is neglected).
ADC Limitations and Performance Parameters
Offset, Full Scale and Gain Errors. Figure 5 represents both
the ideal and actual conversion characteristics of a 3-bit ADC
(3). The former is represented by the broken line that unites
the white dots corresponding to the ideal input transition
voltages between all digital codes in the absence of conversion
errors, whereas the latter is represented by the full line that
unites all black dots corresponding to the actual analog transition voltages between all digital codes. On the lower extreme of the conversion characteristic, the offset error corre1 represents the difference between the actual
sponding to
and ideal input voltage that produces a transition of one LSB
from the output digital code 0. On the upper extreme of the
conversion characteristic, the full-scale error corresponding to
2 represents the difference between the actual and ideal in
put voltages that produce the transition of the output to the
full scale digital code. The gain error of the ADC corresponds
to the difference between the ideal slope of the conversion
characteristic and its actual value.
Differential and Integral Nonlinearity. The differential nonlinearity (DNL) in the ADC expresses the deviation of the difference between the actual input transition voltages Va(n)
and Va(n 1) that produce any two consecutive output digital
codes from the difference voltage corresponding to one LSB.
Such LSB must be determined through a linear characteristic
with the same offset and full-scale errors. This gives a measure of the linearity of operation for small incremental signals
and can be expressed by
DNL(n) =

Va (n + 1) Va (n)
1
LSB

(10)

ANALOG-TO-DIGITAL CONVERSION

for any digital code between n 1 and n 2N 2. The normal specification for the DNL of the ADC is (1/2) LSB. It
should also be mentioned that when the DNL is larger than
1 LSB a phenomenon of nonmonotonicity occurs whereby the
output digital code decreases with an increase of the analog
input signal.
By contrast with the DNL, the integral nonlinearity (INL)
in the ADC gives a measure of the linearity of operation for
large signals, as it expresses the deviation between the actual
input transition voltages obtained for a given digital code and
the corresponding ideal transition voltages assuming a linear
characteristic with the same offset and full-scale errors. For
any digital code from n 1 to n 2N 1, this can be defined
as

INL(n) =

Va (n) Va (1)
(n 1)
LSB

513

Ideally sampled signal

Sampling with jitter noise

Ts
t

(a)

(11)

n
(b)

and relates to the DNL through the equation

INL(n) =

n1


DNL(i)

Figure 7. Illustrating the effect of sampling jitter. (a) Sampled sine

waveform. (b) Jitter related error signal.

(12)

i=1

The normal specification for the INL of an ADC is also (1/

2) LSB. Figure 6 illustrates the preceding definitions of the
DNL and INL of an ADC.

Sampling Jitter. An important dynamic error that affects

the performance of an ADC, especially for high-frequency operation, is due to the timing uncertainty of the sampling instants that produce the input analog samples for conversion
(4). Because of this error, commonly called sampling jitter, the
actual sequence of analog samples is not equally spaced in
time but rather varies with respect to the nominal ideal sam-

111

INL

101

1
2N+1 f

(13)

where f is the frequency of the input signal. For example, for

a 10-bit ADC at 1 MHz this corresponds to a maximum timing
uncertainty of 310 ps.
Effective Number of Bits. A global parameter that summarizes the performance behavior of an ADC is the effective
number of bits (ENOB) expressed as
SINADdB 1.76
6.02

(14)

where the parameter SINADdB (signal-to-noise-plus-distortion

ratio) represents the combined effect of quantization and harmonic distortion due to the various sources of nonlinearity of
the converter. An example of the graphical evolution of the
ENOB is given in Fig. 8, for an ADC with Fs 40 MHz conversion frequency, showing that the effective number of bits
of the converter decreases as the signal-to-noise-plus-distortion ratio decreases for higher frequencies of input analog
signal.

110

DNL

011
LSB
010
001

ts <

ENOB =

Digital output

100

pling instants, as illustrated in Fig. 7(a). For a fixed conversion frequency, it is easily seen that the resulting signal error,
represented in Fig. 7(b), increases as the frequency of the input analog signal increases. It can be shown that in order to
obtain an error signal smaller than the LSB of the converter
the sampling jitter must be such that

LSB

Vref

000
VT1 VT 2 VT3 VT4 VT 5 VT6 VT7 (ideal transitions) Vin
VT1

VT 2 VT3 VT4 VT 5 VT6 VT7 (actual transitions)

Figure 6. Integral nonlinearity (INL) and differential nonlinearity

(DNL) of an ADC.

NYQUIST ANALOG-TO-DIGITAL CONVERTERS

From the standpoint of the conversion frequency, we can classify ADCs into three main groups. Serial converters are the
slowest of all because each bit of the output digital word is
usually determined in a number of clock cycles that rises proportionally to the equivalent bit weight. For example, for the

514

ANALOG-TO-DIGITAL CONVERSION

10.0
60

9.5
9.0

56

8.5

52

8.0

SINAD (dB)

Effective number of bits

Fs = 40 MHz

48

7.5

trated in Fig. 9(a), comprising an active-RC integrator with

multiplexed input, a comparator and a digital counter and
control logic. Figure 9(b) illustrates the time-domain waveforms typically produced in the converter during a complete
conversion cycle. At the beginning of the conversion cycle the
capacitor around the feedback loop of the opamp is reset to
zero. Then, the integrator input is connected to the input signal terminal to generate the first integration ramp that is
carried out during a fixed time interval T1 controlled by the
digital counter. Thus, for a clock period of Ts the opamp output voltage reached after the first integration ramp is

44
7.0
100 k 200 k

500 k

1M

2M

5M

10 M

Vx =

20 M

N1 Ts
(Vin )
RC

(15)

Input signal frequency (Hz)

Figure 8. Evolution of the effective number of bits of an ADC as a
function of the frequency of the input signal.

LSB this may take only one clock cycle, but for the most significant bit this may take as long as 2N clock cycles. By contrast with their low speed, serial processing converters offer
the highest resolution of all the converters described in this
section. They are therefore particularly useful to interface
slowly varying signals for very high precision signal processing as required, for example, in instrumentation and biomedical applications.
Following the serial converters in the speed scale is the
group of algorithmic ADCs. Here, conversion takes place in a
number of clock cycles that is typically proportional to the
conversion resolution. Hence, depending on the actual frequency limitations of the constituting building blocks, conversion frequencies of a few megahertz can be achieved without
too much difficulty in modern complementary metal oxide
semiconductor (CMOS) technology. Algorithmic ADCs constitute a versatile group of converters that can meet a wide
range of specifications in terms of the conversion frequency
as well as resolution. A particular type of ADC based on the
successive approximation algorithm constitutes an industry
workhorse for a large variety of applications.
The fastest group of converters is based on parallel processing techniques that allow a full conversion period to be
performed in only one or, at most, a few (e.g., 2) clock cycles.
One-clock cycle (flash) ADCs in modern CMOS technology can
reach conversion frequencies above 100 MHz but their resolution is limited to no more than 8-bits. An increasingly popular
group of parallel ADCs is based on pipeline architectures that
can perform a full conversion period in only two clock cycles,
although there is an initial latency period that depends on
the total number of stages of the pipe. Pipeline converters
with optimized silicon and power dissipation are in great demand for video processing applications for the consumer
market.

where N1 is the fixed number of clock cycles counted during

T1. Next, the input terminal is switched to the reference voltage terminal and a second integration ramp is generated
whose slope is the negative of the first integration ramp. This
is carried out until the comparator detects that the output
voltage of the amplifier crosses zero and thereby stops the
digital counter. The duration of this second integration ramp,
T2 N2Ts, varies as the voltage at the output of the amplifier
at the end of the first integration ramp is larger or smaller.
This is determined from
0 = Vx +

N2 Ts
V
RC ref

(16)

Vin
R

Vref

Vx

Counter
and logic

bN
b1

(a)
Vx
Vin3
Phase (II)
(Constant slope)

Phase (I)

Vin2
Vin1
Time

Constant T1
Varying T2 for
three inputs

Serial Processing ADCs

Double-Ramp Integration. One of the best known architectures for serial processing analog-digital conversion is illus-

(b)
Figure 9. Serial processing ADC with double-ramp integration. (a)
Typical circuit realization. (b) Waveforms.

ANALOG-TO-DIGITAL CONVERSION

where Vref (Ci /Cf ) Vx 0 and n is the output of the counter

(digital integrator). This implies

Reset
Vin

Vout

Reset

+
CKc

(1)

U/D

b
Counter

Vref


n = 2N

Control
logic

b+1

515

Data out (N )

Figure 10. Conceptual block diagram of an incremental ADC.

Vin
Vref


+

(19)

where the residual error is 0 1. Thus, n is an N-bit

digital representation of the sampled input voltage, with a
quantization error 1 LSB.
As in the double-ramp integrator, the conversion characteristic expressed by Eq. (19) is independent of the capacitance ratio and, hence, resolutions of the order of 16-bits and
above can also be achieved without too much difficulty. Of
course this will be possible only for very low frequency of conversion due to the serial processing nature of the converter.

and which, combined with Eq. (15), yields

Vin =

N2
V
N1 ref

Algorithmic A/D Converters

(17)

Hence, the variable time interval of the second integration

ramp (expressed in terms of the counted number of clock cycles) is a measure of the value of the analog input signal integrated during the first integration ramp.
Because the conversion function Eq. (17) is independent of
the passive circuit elements it allows very high conversion
resolutions to be achieved, although at rather low conversion
frequencies. Such high-resolution and low-speed conversion
characteristics render double-ramp ADCs particularly suitable for applications in telemetry, instrumentation, and measurements.
Incremental Converters. Another type of serial processing
ADC is based on the so-called incremental converter (5,6). Its
conceptual block diagram is illustrated in Fig. 10 where, as
before, the processing core of the converter is formed by an
integrator and a comparator. The control logic and digital
counter provide the additional digital processing functions required for conversion. The main difference with respect to the
previous double-ramp converter lies in the fact that the integration variable is now formed by the difference between the
sampled input signal and an analog signal determined as a
function of the output voltage of the comparator.
A switched-capacitor implementation of the processing
core of an incremental ADC is shown in Fig. 11(a). It is assumed that during a full conversion cycle the sampled input
signal of the converter is held constant. For simplicity of the
following discussions it is further assumed that the input
sampled and held signal is positive. At the beginning of the
conversion cycle, the integrating capacitor is reset by closing
switch SR. In each subsequent conversion step switches S1,
S3, S4, and S5 are controlled in such a way as to produce an
incremental variation of Vx (Ci /Cf )Vin at the output voltage of the opamp. Then, whenever Vx reaches zero, a fraction
of the reference voltage, actually (Ci /Cf )Vref , is subtracted from
the output using switches S2, S3, S4 and S5, and the digital
counter is advanced by 1. The typical waveform observed at
the output of the opamp is depicted in Fig. 11(b). At the end
of 2N conversion steps the output voltage becomes
C
C
Vx = 2 Vin i n Vref i
Cf
Cf
N

(18)

Next in the scale of conversion frequency is the group of algorithmic ADCs where the number of clock cycles needed for
conversion is directly, rather than exponentially, proportional
to the conversion resolution. Two types of algorithmic ADCs
will be described. The first is based on the classical successive
approximation algorithm and constitutes the industry workhorse for a large variety of applications. The second is based
on a cyclic divide-by-two and subtract algorithm whose circuit
implementations can be made more compact than in the case
of the successive approximation ADC.

Vin

S1

Vref

S2

SR
Ci

S5

Cf

Latched
comparator

S3

GND

Vx

S4

To
control
logic

(a)

Vx

VRef Ci/C2
1

2n integration cycles
(b)
Figure 11. Switched-capacitor incremental ADC. (a) Circuit diagram
and (b) Typical output waveform.

516

ANALOG-TO-DIGITAL CONVERSION

Vref

11xx

1110
1101

110x
1xxx

1100
1011

101x
10xx

xxxx

01xx

Vin

1000

0xxx

0100
0011

001x
00xx

0010
0001

000x

Comparator

S/H

Figure 13. Block diagram of a successive approximation ADC.

0110
0101

010x

0111
011x

D/A

1010
1001

100x

(MSB)

Successive
approximation
register

1111
111x

0000

(LSB)

Figure 12. Illustrating the successive approximation algorithm for

analog-to-digital conversion.

Vx = Vin +

Vref
2

(20)

at the negative terminal of the open loop opamp. If this is

negative, then the output voltage indicates the equivalent
logic value 1; otherwise it indicates the equivalent logic value
0. In the former case, the MSB is set to 1 and the corresponding branch remains connected to the reference voltage.

2N 1C 2N 2C

2C

C Vx

Vo
+

.
..
..

Vin
1

.
..
..

1
2
Vref

.
..
..

Successive Approximation ADC. The successive approximation ADC is based on the algorithm schematically represented
in Fig. 12, for an example of 4-bits conversion. The equivalent
analog weights of the digital bits are Vref /2, for bit b4 (the
MSB), Vref /4 for bit b3, Vref /8 for bit b2, and finally Vref /16 for
the LSB (bit b1). The execution of the algorithm is done from
the MSB to the LSB during a number of clock cycles equal to
the resolution of conversion. At the beginning of the conversion, the input signal is compared with the analog weight of
the MSB and the result is either b4 1 or b4 0, depending
on whether the signal is above or below Vref /2. If the result is
1, then the analog weight of the MSB is subtracted from the
input signal; otherwise the input signal remains unchanged.
In the next phase, the available analog signal is compared
with the analog weight of bit b3 and the result is either b3
1 or b3 0, depending on whether the signal is above or below Vref /4. If the result is 1, then the analog weight of bit b3
is subtracted from the analog signal; otherwise the signal remains unchanged. Similar operations are carried-out in two
more steps until the LSB is resolved.
Figure 13 represents a possible conceptual block diagram
for the implementation of the forementioned successive approximation algorithm. The input sample-and-hold block provides the analog sampled signal for conversion. The digitalto-analog converter generates the equivalent analog values of
the digital words containing the bits that are sequentially resolved, from the MSB to the LSB. The comparator acts as
the decision element that indicates to the digital successive
approximation register how the input analog signal is being
approximated by the reconstructed analog values.
There are various possible circuit solutions for the implementation of the block diagram in Fig. 13, some employing
digital-to-analog converters with resistive division and some

employing digital-to-analog converters with capacitive division (1). The latter is one of the most popular forms of implementation, especially for CMOS technology, as it uses a capacitor array that can also provide the additional functions of
sample-and-hold and subtraction needed in the conversion algorithm.
Figure 14 illustrates the implementation of a successive
approximation ADC using an array of switched binaryweighted capacitors. During the execution of one conversion
cycle the circuit is sequentially reconfigured as illustrated in
Fig. 15. First, as seen in Fig. 15(a), the opamp is connected in
a unity-gain feedback configuration while the capacitors are
connected to the input terminal. Because of the virtual
ground created at the negative terminal of the opamp the input voltage signal is sampled onto the top plate of the capacitors. In the next phase, shown in Fig. 15(b), the most significant capacitor is connected to the reference voltage and, as a
result, a process of charge redistribution between this and the
remaining capacitors takes place, yielding a new voltage expressed by

bN

bN1

b2

b1

Successive approximation register

Figure 14. Switched-capacitor implementation of a successive approximation ADC.

ANALOG-TO-DIGITAL CONVERSION

2N 1C 2N 2C

2C

517

Vin

C Vx

...
..

1
2

Vin

S/H

2X

Vx

+
bi

Vref

(a)

2N 1C 2N 2C

2C

Vx

...
..

bN
+

Vref

Figure 16. Conceptual block diagram of a multiply-by-two cyclic

ADC.

(b)

to meet a wide range of conversion specifications, from a few

kilohertz to the megahertz range.
2N1C 2N 2C

2C

Vx

..
...

Vref

+
bN = 1 bN1 = 1

b2 = 0 b1 = 0
(c)

Figure 15. Sequence of configurations of the SC successive approximation ADC during one cycle of the conversion algorithm.

In the latter case, the MSB is set to 0 and the corresponding

branch is connected back to ground. In this case, there will be
a further charge redistribution in the array such that the
original input voltage appears again at the negative terminal
of the opamp. After all bits have been tested by similar sequences of charge redistribution and comparison, the connection of the capacitors either to ground or to the reference voltage will reflect the final configuration of the converted output
digital word, as seen in Fig. 15(c).
In the preceding SC successive approximation ADC the accuracy of conversion is limited both by capacitance mismatch
errors and by the input referred offset voltage of the opamp.
Capacitance matching accuracy can be maximized by adopting careful layout designs of the capacitor arrays properly
sized, whereas the input-referred offset of the opamp can be
virtually eliminated by means of auto-zero techniques. Thus,
untrimmed conversion resolutions of up to 9 to 10 bits can be
comfortably achieved by SC successive approximation ADCs.
For higher resolutions it is mandatory to employ calibration
techniques which can extend the inherent matching accuracy
of integrated capacitor-arrays well above the inherent technology-dependent 10-bit level.
Regarding the speed of conversion, there are two main limitations imposed on the operation of the SC successive approximation ADC in Fig. 14. One is due to the speed of the
comparator, whereas the other results from the RC time constants associated with each SC branch because of the equivalent on-resistance of the switches. In most cases such time
constants can be properly controlled by sizing accordingly
both the transistor aspect ratios and the input capacitors and
hence the speed of conversion becomes limited essentially by
the speed of the comparator. This allows the design of SC
successive approximation ADCs in modern CMOS technology

Cyclic ADC. Another type of algorithmic ADC is illustrated

in the conceptual diagram shown in Fig. 16, comprising an
input sample-and-hold, a two-fold gain amplifier, a comparator, and an adder (7). In the sampling phase, the input multiplexer is initially connected to the input terminal. Next, the
input signal is multiplied by two and compared with Vref to
resolve the most significant bit. Depending on the result, a
residual signal will be fedback to the input of the circuit for
further processing (thus the designation of cyclic conversion).
If Vin Vref , then MSB 1 and the generated residual signal
will be (2Vin Vref ). If, on the contrary, Vin Vref , then
MSB 0 and the residual signal will be simply the signal
2Vin. The residual signal will be again multiplied by two and
compared with Vref to resolve the second most significant bit
and again generate a new residue. This cycle repeats as many
times as the number of bits to be resolved and, hence, the
conversion time is directly proportional to the resolution of
the converter.
A possible SC implementation of a cyclic ADC is shown in
Fig. 17. The first opamp samples the input signal in the first
conversion cycle, and the residue signal in the remaining conversion cycles. The second opamp performs the combined
functions of amplification by two of the recycling residue and
addition. The 1-bit digital-to-analog conversion function is
performed by the switched capacitor that can be connected
either to Vref or ground. The number of components and capacitance spread is independent of the conversion resolution and,

Vin
C

2C

Vx

bi
+

Vref
Figure 17. Switched-capacitor realization of a cyclic ADC.

ANALOG-TO-DIGITAL CONVERSION

put of the comparators is encoded into an N-bit twos-complement binary code and then latched.
One circuit solution that is particularly suitable for integrated circuit implementation in CMOS technology is shown
in Fig. 19. Here, the multilevel reference voltage generator is
formed by a resistor-string with direct connection of the output voltage taps to the inputs of a bank of latched comparators. Each of the latched comparators in the converter employs input offset voltage compensation by auto-zero. Slight
modifications of this architecture can also be considered if a
specialized sample-and-hold circuit is employed, rather than
the distributed scheme already mentioned here.
With only one clock cycle per conversion period, the flash
ADC gives the fastest possible time of conversion. However,
because of the very large number of resistances and especially
comparators needed (proportional to 2N), this type of converters usually occupies a very large area for implementation and
burns a significant amount of power. In practice, they are
therefore limited to conversion resolutions of no more than 8bits. In order to overcome such limitations and still achieve
high speed of conversion, two alternative types of parallel processing ADCs are described next, namely the subranging and
the two-step flash converters.

Vin

VT

S/H

VT

2N1

+
VT

.
.
.
D

+
VT

Thermometer to binary encoder

2N

Multilevel reference voltage generator

VT

.
.
.
D

bN

b3
b2
b1

Figure 18. Typical block diagram of a flash ADC.

hence, the converter can be very compact even for medium to

high resolution.
Parallel Processing ADCs (8)
Flash ADC. The block diagram of a flash ADC is represented in Fig. 18 (9). It comprises an input sample-and-hold
circuit, a multilevel reference voltage generator with output
taps directly connected to the inputs of a bank of comparators
and, finally, some digital circuits for latching and encoding
the output voltages of the comparators. The input voltage is
sampled and held and then compared simultaneously with
2N 1 voltages (for a resolution of N-bit) of the reference
voltage generator. The resulting thermometer code at the out-

Vref +

Vin

Vref

.. 2
.
1

..
.

R
Figure 19. The CMOS implementation of
a flash ADC.

..
.

N 1

voltage taps

Subranging ADC. The conceptual block diagram of the subranging ADC is illustrated in Fig. 20 and which comprises,
besides the input sample-and-hold, two flash-like converters,
one with N1-bits and the other with N2-bits, connected by a
digital-to-analog conversion block (10). The resulting digital
codes of both flash converters are combined to form the converted output digital word of the converter. After input signal
sampling, the operation of the subranging converter is performed in two phases, namely a coarse conversion phase
where typically the N1 most significant bits are determined,
and a fine conversion phase where the remaining N2 least significant bits are obtained.
The behavior of the subranging converter in both the
coarse and fine conversion phases is identical to the behavior
of the flash, although the set of voltages to which the input
voltage is compared is different from one phase to the other,

.. 2
.
1

..
..
.

..
..
.

..
..
.

..
..
.

2
1

2
1

Thermometer to binary encoder

518

bN

b3
b2
b1

ANALOG-TO-DIGITAL CONVERSION

Vin

Sample and
hold

VT

VT

VT

(i) 2 N2

N2-bits

VT

N1-bits

.
.
.

bN

2+2

bN

bN

2 +1

.
.
.

.
.
.

bN

b2 b1

2N

2 N1

VT

bN

D/A converter

D/A converter

(i + 1) 2 N2

N1-bits flash quantizer

VT

N2-bits flash quantizer

N1-bits flash quantizer

G=

N1-bits

ra

2N

2N

VT

res
_

bN

2+2

bN

2 +1

N2-bits

bN

.
.
.

N2-bits flash quantizer

Sample and
hold

VT

519

b2 b1

Figure 22. Conceptual block diagram of a two-step flash ADC.

Figure 20. Conceptual block diagram of a subranging ADC.

as seen in Fig. 21. In the coarse conversion phase the input

voltage is compared with a set of 2N/2 1 voltages spanning
the whole input signal range, and the resulting MSBs indicate the specific conversion interval that encompasses the
sampled input voltage. Then, in the fine conversion phase the
selected conversion interval is segmented into a further
2N/2 1 voltages in order to determine the remaining LSBs.
In subranging ADCs the required number of comparators
and resistors is only proportional to 2N/2 rather than to 2N as
in the case of the pure flash ADC. Therefore subranging

1st Step
MSBs
VT

2nd Step
LSBs

16

11
VT

12

10

VT

18

VT
12
VT
11
VT
10
VT
9
VT

11
10
01
00

01
VT

00
VT

Figure 21. Illustrating the two quantization phases in a subranging ADC.

ADCs offer an attractive solution for the integrated implementation of high-speed ADCs with 8-bits resolution and
above.
Two-Step Flash ADC. The conceptual block diagram of a
two-step flash ADC is shown in Fig. 22, comprising two flash
quantizers, one with N1-bits and the other with N2-bits, a digital-to-analog converter (DAC) and also a gain block that amplifies the difference between the input analog signal and the
partially reconstructed analog signal obtained at the output
of the DAC (11,12). The conversion cycle is divided into a sampling phase, a coarse conversion phase, and a phase for the
amplification of the residue and its fine conversion. After
sampling, the input voltage is applied to the input of the N1bits coarse quantizer to determine the MSBs that are latched
into a digital register. Afterwards, the converted digital code
is reconstructed back to an analog voltage by means of the
DAC. This voltage is then subtracted from the input voltage
signal to form the residue signal of the converter. This, in
turn, is amplified by the gain block G 2N1 and then applied
to the N2-bits fine quantizer to determine the LSBs of the
converter. The final output digital code is obtained by combining the MSBs of the first quantization phase together with
the LSBs of the second quantization. The accuracy of the amplified residue signal generated internally in the two-step
flash ADC is a key factor to determine the overall linearity of
the converter. Under ideal circuit conditions it evolves between two consecutive digital codes as illustrated in Fig. 23,
where the slope of the characteristic is defined by the amplification factor of the gain block.
A circuit implementation of the two-step flash ADC that is
particularly suitable for integration in CMOS technology is
shown in Fig. 24. The multiplying DAC uses an array of
switched capacitors and an opamp, whereas the flash quan-

520

ANALOG-TO-DIGITAL CONVERSION

pled voltage. A residue amplified by 2N/2 is then generated at

the output of the amplifier. This is again applied to the flash
to determine the remaining N/2 LSBs.

Residue (in LSB of the

1st conversion)

+1/2

1/2
VT

VT

VT

2 N2

VT

(2N1 1) 2N2

2N

Vin

Figure 23. Amplified residue signal internally generated in the twostep flash converter under ideal circuit components characteristics.

tizer is identical to the one presented in Fig. 19 because it

first samples the voltages generated by the resistor-string
into the input capacitors (Ci), and then compares them with
the input voltage. It is possible to realize both the coarse and
fine conversions by the same flash. The operation of this particular configuration is as follows. The input voltage is sampled in the top plates of the capacitor array, while the input
capacitors of the flash sample the corresponding voltages generated in the resistor-string. In the next phase, the whole
array is connected as the feedback of the opamp, thus holding
at its output the sampled voltage. This output is next applied
to the input of the flash to determine the N/2 MSBs. In the
next phase, the resolved bits are applied to the DAC to subtract the reconstructed analog voltage from the original sam-

Vref +

Vin

..
. .
..
R

..
.

..
..
.

..
..
.

..
.

..
.

Vref

..
.

C1

..
..
.

..
..
.

C0

Vref

Vref

..
..
.

..
.

2 N11
rows

2 N2 1
rows

Vref

Thermometer to
binary encoder
bN

1
Q

..
. .
..

1
D

C2

1
D

CF

..
.

..
..
.

..
.

+
R

C N11

1
D

Vref +

Vin

Vref +

Digital Error Correction. Because of unavoidable circuit impairments associated with practical integrated circuit realizations, the quantization window determined by the first flash
quantizer in both the subranging and two-step flash ADCs is
determined with a maximum error of 1/2 LSB of its nominal
resolution, rather than with an ideal 0 LSB error. When this
error is passed on to the second quantization phase it may
overflow the quantization range of the flash and thus produce
errors in the overall conversion characteristic.
To correct for such errors the flash quantizer may be augmented beyond its nominal resolution, for example by 1/2
LSB on the upper boundary of the quantization window and
by 1/2 LSB on the lower boundary of the quantization window, such that the additional resolved bit can be subsequently used for digital code correction. This technique is illustrated in Fig. 25. The quantization zone A corresponds to
the original comparators in the center of the flash quantizer,
zone B corresponds to the additional lower comparators and
zone C corresponds to the additional upper comparators.
When the MSB flash quantizer determines correctly the
quantization zone A, as in Fig. 25(a), the output digital code
is obtained directly from the outputs of the comparators.
When the flash quantizer resolves instead a code within zone
B, as shown in Fig. 25(b), the output digital code of the previous quantization will be corrected by 1. Finally, when the
flash quantizer resolves a code within zone C, as illustrated
in Fig. 25(c), the output digital code of the previous quantization will be corrected by 1.

b N2 + 1
Figure 24. The CMOS implementation of a two-step flash ADC.

Thermometer to
binary encoder
b N2

b1

MSBs

.
.
.

FLG

.
.
.

1011

;
;
;
;
;
;

LBSs

ANALOG-TO-DIGITAL CONVERSION

Digital error correction

1 0111

1 0000
0 1111

MSBs LBSs FLG

Vin

Vin

1010

0 1000

0 0000
1 1111

1010

1000 0 = no error

1010

1000 final result

1001

.
.
.

1 1000

.
.
.

(a)

MSBs

.
.
.

FLG

.
.
.

1101

LBSs

Digital error correction

1 0111

1 0000
0 1111

MSBs LBSs FLG

;
;
;
;
;
;
A

1011

1011

1100 1 = error

0 0000
1 1111
Vin

Vin
1010

.
.
.

MSBs

.
.
.

1 1100

1010

1100 final result

1 1000

.
.
.

FLG

1010

LBSs

Digital error correction

1 0111

Vin

Vin

1 0010
1 0000
0 1111

MSBs LBSs FLG

1001

1001

0011 1 = error

+ 1

0 0000
1 1111

1010

0011 final result

1000

.
.
.

.
.
.

Pipeline A/D Converters

Architecture and Operation. Pipelined ADCs constitute a
type of parallel processing converters that have gained popularity in a variety of high-speed conversion applications due
to the cost/benefit they can achieve over the subranging and
two-step flash converters (13,14). The conceptual block diagram of a pipeline ADC is shown in Fig. 26(a), for an example
with five pipelined stages, and the associated timing diagram
is given in Fig. 26(b). During the first phase of the first clock
cycle, the input stage samples the input signal and executes
the first quantization. Then, in the second phase the residue
is generated, amplified, and transmitted to the second stage
of the pipeline for further processing. In subsequent clock cycles similar operations of sampling, quantization, and residue
generation are again carried out in the first stage. Meanwhile, in the second stage, these operations are performed in
opposite phases. Input sampling and quantization are performed when the first stage is amplifying the residue,
whereas residue amplification and transmission to the next
stage are performed when the first stage is receiving a new
input sample. In parallel with this form of horizontal propagation of the signal (actually, the signal residues), the digital
words quantized in each stage and in each clock cycle are
propagated vertically through digital registers, as seen in Fig.
26(a), such that at the end of five clock cycles they are all
available at the output of the converter to produce the converted digital word. Then, after this latency period, which is
needed to fill all the vertical digital registers, there will be
one converted digital word every clock cycle.
The maximum resolution achieved with such an architecture is limited mainly by thermal noise, the nonlinearity of
the MDACs produced by capacitor mismatches and also by
the residue amplification error that is due to the amplifier
nonidealities. The error from the flash quantizer can be digitally corrected if kept within 1/2 LSB of the nominal resolution of the quantizer and redundancy is used for digital error correction.
Time-Interleaved Converters

(b)

.
.
.

521

1 1000

(c)

Figure 25. Illustrating the digital error correction technique in an

ADC.

An extended concept for parallel processing conversion is

based on the use of the type of time-interleaved architectures
illustrated in Fig. 27(a) (15,16). These are formed by M paralleled channels whose operation is multiplexed in time, as illustrated in the timing diagram depicted in Fig. 27(b). Each
channel in a time-interleaved converter can be formed by any
of the types of ADCs previously described. At any given clock
cycle, the input and output multiplexers connect only one
ADC channel between the input and output terminals, so that
one converted digital word is delivered at the output and a
new sample of the input signal is taken for conversion. In the
next clock cycles the same operation is sequentially repeated
with the remaining ADC channels while the first channel carries out the signal conversion; everything should be completed
only after the M channels have been served by the multiplexers. Thus, for a given conversion frequency Fs of the ADCs
the time-interleaved operation allows to achieve an overall
conversion frequency of MFs.
A variation of the basic time-interleaved ADC architecture
based on a quadrature-mirror filter (QMF) bank is indicated
in Fig. 28 (17). At the input there is an analysis filter bank,
typically realized in switched-capacitor form, whereas the
output filter bank is a digital network. In this approach the

522

ANALOG-TO-DIGITAL CONVERSION

In
S/H

MDAC

MDAC

MDAC

MDAC

FLASH

FLASH

FLASH

FLASH

3b

3b

3b

FLASH
4b

3b

Clk
12b Out
Digital error correction logic
(a)
1

Cycle
Stage 1

Sampling and
quantization

Stage 2

.
.
.

.
.
.

Residue
amplification

Sampling and
quantization

Residue
amplification

Sampling and
quantization

Residue
amplification

Sampling and
quantization

Residue
amplification

Sampling and
quantization

Residue
amplification

Sampling and
Residue
Sampling and
quantization amplification (5) quantization

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

Sampling and
quantization

Stage 5

Sampling and
quantization

.
.
.

.
.
.

Sampling and
quantization

q[x(2)]

Digital
output

Residue
amplification

q[x(2)]

5 cycles latency
(b)
Figure 26. (a) Conceptual block diagram of a five-stage pipelined ADC. (b) Illustration of the
timing of the pipe operation and latency of the converter.

input signal is first decomposed into a number of contiguous

frequency bands (subbands) so that a specific ADC (subconverter) can be assigned to each subband signal. Due to the
synthesis filters the linearity performance due to mismatches
among the subconverters is substantially reduced. Similarly,
the jitter problem that arises in the basic time-interleaved
converter due to uneven sample timing, especially for highfrequency input signals, is also reduced by the filtering and
downconversion stage. Besides, this type of QMF-based converter also incorporates the advantages of subband coding
such that by appropriately specifying the resolution of the
subconverters throughout the respective subbands the quantization noise can be separately controlled in each band, and
the shape of the reconstruction error spectrum can be controlled as a function of the frequency.
Theoretically, the overall resolution of a QMF-based ADC
depends solely on the resolution of the subconverters used. If

successive approximation subconverters are used, then substantial savings in die area can be obtained when compared
to flash converters.

OVERSAMPLING CONVERTERS
The common characteristic of all the converters already described herein concerns the uniform power spectral density of
the quantization noise in the Nyquist band, that is, the frequency range from dc to half the conversion frequency. Hence,
their designation of Nyquist converters. In order to achieve
high SNR, Nyquist converters must have a correspondingly
high conversion resolution, which, in turn, requires very high
matching accuracy from the constituting elements responsible
for the scaling operations in the converter. This can be
achieved without too much difficulty for conversion resolu-

ANALOG-TO-DIGITAL CONVERSION

A/D 1

in

out

523

N @ Fs

@ Fs
A/D 2

in

out

N @ Fs

@ Fs

.
.
.

.
.
.

.
.
.

N
@ MFs

@ MFs
A/D M 1

in

out

@ Fs
A/D M

in

N @ Fs

out

N @ Fs

@ Fs
(a)

n MT
A/D 1

(n+1)MT
V(nM)

V [(n+1)M ]

n MT+T

V(nM+1)

A/D 2

.
.
.

.
.
.

n MT+(M2)T

A/D M1

.
.
.

V(nM+M2)
n MT+(M1)T

V(n M+ M1)

A/D M

Ts
T = Ts / M

(b)

tions up to about 10-bits. For conversion resolutions above 10bits self-calibration techniques should be employed to extend
the matching accuracy of the elements above the inherent accuracy provided by the technology.
Because of the increased difficulty of designing self-calibrated converters alternative techniques have been sought to
achieve equivalent high-resolution conversion within the limits of matching accuracy that can be achieved with a given
technology. Such conversion techniques are based on shaping
the quantization noise of an oversampled signal, that is,
where its sampling frequency is much higher than the Nyquist frequency, such that the resulting power spectral density is significantly reduced within the frequency band of interest and increases outside such a band. Hence, the resulting
converters are commonly known as oversampling converters.
The notion of using such artificially high sampling rates
and simple single-bit quantization to represent analog signals
has been of interest ever since the introduction of delta modulation. However, the oversampling technique alone would re-

Figure 27. (a) Conceptual block diagram

of a time-interleaved ADC and (b) illustration of its time multiplexed operation.

quire sampling frequencies too high to be of much practical

use. Subsequent developments introduced the methods of
negative feedback, noise shaping and higher-order modulators (18). These improvements allowed the practical implementation of very high resolution converters at the expense
of an increase in complexity of the digital filters that are
needed to extract the baseband signal from the high speed
bit-stream produced by the modulator (19). Because these can
be implemented rather efficiently by modern CMOS technology, oversampling converters have been making inroads in
mixed-signal analog-digital integrated circuits for high performance applications. The sections that follow describe the
basic concepts and most relevant implementation techniques
of oversampling ADCs.
Quantization Noise with Oversampling and Shaping
To reduce the in-band noise power of an oversampled quantized signal beyond the value obtained for the uniform noise

524

ANALOG-TO-DIGITAL CONVERSION

Analysis
filter bank

Downsamplers

Synthesis
filter bank

Upsamplers

H0 (z)

ADC

F0 (z)

H1(z)

ADC

F1(z)

H2(z)

ADC

F2(z)

Analog
input

Digital

..
.

output

.
.
.

.
.
.

HN1(z)
Figure 28. Block diagram of a time-interleaved ADC based on a quadrature-mirror
filter (QMF) bank.

Quantization noise

..
.

FN1(z)

Analog

distribution, a specific noise shaping function should be performed, as illustrated in Fig. 29. A portion of the quantization
noise is now pushed into higher frequencies, thereby improving the equivalent bit-resolution in the signal bandwidth of
interest while keeping the oversampling ratio constant. Such
shaping effect can be obtained by means of the circuit shown
in Fig. 30 for an example in which an integrator is used to
produce a first-order noise shaping. Its operation can be intuitively understood from the theory of closed loop systems. Because in the baseband the integrator has a very large gain,
the overall transfer characteristic is determined by the feedback branch and any nonlinearity in the feed-forward branch
is attenuated by the large loop gain. The feedback branch consists of a digital-to-analog converter and the overall resolution will be determined solely by the linearity of this component.
An interesting case is when only two quantization levels
are used, that is, one-bit resolution. This is called a single-bit
first-order sigma-delta () modulator and is represented by
the circuit diagram shown in Fig. 31. It comprises an integrator for the filter function, a comparator with latch for the
1-bit quantizing function, and a switch to either Vref or
Vref that realizes the 1-bit digital-to-analog conversion providing the reconstruction of signal prior to the subtraction

Digital

from the incoming signal at the input of the modulator. Because of its simplicity and use of 1-bit converters the system
becomes very robust and precise. In particular, the implementation of the 1-bit DAC renders such a structure inherently
linear, possibly yielding only offset and gain errors. Thus, the
modulator offers the potential for high resolution conversion without the need for accurate components.
Analysis of First- and Second-Order Modulators
Due to the highly nonlinear element in the loop, the exact
analysis of a modulator is not simple to do and any form
of analytical solution is too complex to be of much practical
use. Therefore, a simplified linearized model of the modulator
is used in which the comparator is replaced by an additive
noise source. Although this approximation allows prediction
of some important aspects of the modulator behavior, such as
noise level and spectrum, it must be nevertheless carefully
interpreted because it assumes a set of conditions not thoroughly satisfied in most applications.
First-Order Modulator
Linearized Model. Referring to the circuit in Fig. 31, the
corresponding linearized model of the modulator is represented in Fig. 32, where the integrator is modeled by a discrete-time function and the quantizer is modeled as a unity
gain block with an additive noise source VQ. It can be readily
obtained that the transfer function for the input signal is
given by

Fs

Baseband

ADC

.
.
.

Input

Integrator

A/D

Output

Quantization noise shaped

Baseband
Figure 29. Effect of shaping the quantization noise.

Fs

D/A
Figure 30. Oversampling and noise-shaping modulator.

ANALOG-TO-DIGITAL CONVERSION

S(z) =

Vout (z)
= z1
Vin (z)

1
1 z 1

(21)
Input

whereas the transfer function relative to the quantization

noise source is given by

V (z)

= 1 z1
Q(z) = out
VQ (z)

(22)


Q( f ) = 2 sin

f
Fs

PQ =

LSB2
12



(23)

1
Fs /2




2
f
2 sin
df
Fs

(24)

where, as previously indicated, LSB represents the quantizer

step size.
Considering that the signal band of interest is highly
oversampled, that is, ( fc /Fs) 1, the total in-band noise power
can be expressed as follows:

PQ =

LSB2
12



2
3



1
OSR

3
(25)

as a function of the quantization step and oversampling ratio

of the modulator. Hence, for a sine waveform with maximum
peak value of (2N 1)(LSB/2) it results in a signal-to-noise
ratio given by





3
3 N
3
(2 1)2 + 10 log
(26)
SNR = 10 log
OSR
2
2
and which, for a 1-bit quantizer (N 1), can also be expressed
as
SNR(dB) = 9 log2 (OSR) 3.41

(27)

Fs

Input +

Output
+

Integrator

Delay

Delay
Integrator

VQ
Quantizer

Thus, while the input is unaffected throughout the modulator

processing chain (apart from the delay term), the quantization noise VQ is filtered by a high-pass function with notch
frequency at dc.
Signal-to-Noise Ratio. For the circuit considered above with
the noise related transfer function given by Eq. (23), the total
quantization noise power in a frequency band from dc to f c
can be calculated from
fc

Output
+

Figure 32. Linearized model of the first-order modulator.

to yield the frequency response

525

Comparator

Latch

+Vref
Vref
Figure 31. Schematic diagram of the first-order modulator.

From the preceding expression it is now clear that each octave of the oversampling ratio leads to a 9 dB improvement
of the SNR, which corresponds to an equivalent increase of
1.5 bit of the conversion resolution.
One important aspect in the type of oversampling modulator considered above, and that is not predicted by the approximated linearized model, is the appearance of limit cycles for
certain input waveforms (20). The reason is that the quantization noise becomes highly correlated with the input. Then,
the assumption that the quantization noise spectrum is white
is no longer valid. Actually, the quantization noise is concentrated in discrete frequency bands that, when falling in the
baseband, produce noise tones much above the noise level predicted by Eq. (25). This effect can be attenuated by introducing a high frequency dither signal superimposed on the input
signal, thereby creating sufficient disturbance so as to destroy
the tones. However, the addition of this dither signal reduces
the dynamic range of the modulator and complicates the
design.
Second-Order Modulator. By adding another integrator
in the forward loop, a stronger reduction of low-frequency
quantization noise is possible for the same oversampling ratio. Furthermore, due to the additional integrator the quantization noise becomes a more complex function of the circuit
parameters and it is, therefore, less correlated with the input.
Thus, a second-order modulator will be much less prone to
enter in limit cycle conditions than its first-order counterpart
and the corresponding noise tone power is very small. In applications where the input signal is sufficiently busy so as to
completely randomize the quantization noise there is no need
to add a dither signal. Figure 33 shows the schematic diagram of such a second-order oversampling modulator. The inner second feedback loop has been added to ensure operation
stability.
Two of the most common implementations of second-order
modulators are represented by their linearized discrete-time
models illustrated in Fig. 34. The first one, represented in
Fig. 34(a), employs two delay-free integrators whereas the
other one, represented in Fig. 34(b), employs a delayed integrator in the first stage and a different coefficient in the inner
loop. The latter implementation allows more design flexibility
due to the relaxed timing requirements, and smaller voltage
swings on the integrator outputs (21).
From the linearized models represented in the preceding
illustration (Fig. 34), it is readily seen that the signal is
merely affected by a delay term corresponding to one clock
period, in the case of the delay-free integrators, and two clock
periods in the other case. Both forms of implementation produce the same noise shaping effect determined by a high-pass

526

ANALOG-TO-DIGITAL CONVERSION

Fs

Input

Output
+

Integrator

Integrator

Comparator

Latch

+Vref /2
Figure 33. Schematic diagram of a second-order modulator with two feedback loops for operation stability.

Vref /2

transfer function expressed as

and which for a single-bit quantizer yields

Q(z) = (1 z1 )2

(28)

SNR(dB) = 15 log2 (OSR) 11.14

(31)

yielding the frequency response


2
f
Q( f ) = 2 sin
Fs

(29)

It can be appreciated that while at low frequencies the quantization noise will be strongly attenuated due to the secondorder noise shaping the high-frequency portion of the spectrum will be substantially amplified, as is illustrated in Fig.
35.
Following a similar procedure as for the first-order modulator, it can be shown that in both forms of implementation
the resulting quantization noise power at the output, in a frequency band from dc to f c Fs /2OSR, is given by the approximate expression
Q
=

LSB2 4
60

1
OSR

5
(30)

Therefore, each doubling of the oversampling ratio provides a

15 dB increase in the SNR, which gives an equivalent resolution increase of 2.5 bits.
Figure 36 compares the SNR characteristics obtained for
oversampling modulators with first- and second-order filtering as well as for oversampling modulators with no noise
shaping function (zero-order). For example, in order to
achieve an equivalent 12 bit of resolution with a second-order
oversampling modulator a signal-to-noise ratio of 74 dB must
be obtained. In practical application designs, in order to allow
for secondary sources of noise such as thermal noise in the
input stage and degradation of noise shaping due to imperfect
components, a margin of approximately 6 dB should be added.
From Fig. 36 we can see that for obtaining SNR 80 dB
such a second-order modulator would need an OSR of only 65,
whereas a first-order modulator would required a much
higher OSR of 600.

1
1 z1

1
1 z1

Input
+

Delay

Output

Delay

VQ

Delay

Integrator-1

Integrator-2

Quantizer

(a)
z1
1 z1

1
1 z1

Input
+

Delay

Delay

VQ

Delay

Figure 34. Linearized equivalent circuits

of second-order modulators for two of
the most popular implementations.

Integrator-1

Integrator-2
(b)

Quantizer

Output

ANALOG-TO-DIGITAL CONVERSION

Spectral density

16

High-speed clock

12

Nyquist
clock

Second order

Analog
input

8
First order

Baseband

Quantization noise
0

527

Analog
modulator

Digital
filter

Register

Digital
output

Figure 37. Block diagram of a complete oversampled ADC system,

including an analog modulator and a digital decimator.

0.5
Frequency (normalized to Fs = 1)

Figure 35. Shaping functions of the output quantization noise for

the case of first- and second-order modulators.

System Aspects of Oversampling ADCs

Signal-to-noise ratio (dB)

The general architecture of a complete ADC based on

oversampling techniques is represented in Fig. 37. Besides
the analog modulator clocked at a high (oversampled) frequency, the system includes a digital filter, also clocked at the
oversampling frequency, and an output register clocked at the
lower Nyquist frequency. The combined digital filter and output register with different clock rates perform the so-called
decimation function of the converter, which purpose is to remove the high-frequency noise components produced by the
shaping effect of the modulator.
Figure 38 depicts several time-domain waveforms and corresponding signal spectra that illustrate the operation of the
complete oversampling ADC. It is assumed that an input signal band limited from dc to f c Fs is sampled at the highfrequency clock, as seen in Fig. 38(a). Next, the 1-bit quantized bit stream at the output of the modulator contains basically the baseband information from dc to f c and a large
amount of out-of-band quantization noise above f c. The corresponding time-domain waveform and frequency spectrum are
depicted in Fig. 38(b). The out-of-band quantization noise is
then removed by means of the digital filter and which, at the
same time, increases the length of the digital signal from 1
bit to the full N-bits resolution of the converter. The resulting
spectrum is shown in Fig. 38(c). Finally, the output sampling
rate is reduced by means of an M-fold down sampler in order
to obtain to the required output conversion frequency and
thus yields the periodic (digital) spectrum illustrated in Fig.

140
120
100
80
60
40
20
0
20

Second order
First order
No noise shaping
1

10
100
Oversampling ratio

1000

Figure 36. The SNR characteristics of oversampling modulators

with zero-order (no noise shaping), first-order, and second-order noise
shaping as functions of the oversampling ratio.

38(d). This last stage of the processing chain is called decimation.

The design of a complete oversampling ADC based on the
preceding system architecture involves the selection of key
design parameters for both the analog modulator and the digital decimator, bearing in mind the interaction between them.
For the analog modulator, on the one hand, the parameters
of concern are the order of the filtering function and the number of quantized bits. On the other hand, the relevant design
parameters for the digital decimator are the oversampling ratio, the word length at both the output of the analog modulator and at the output of the system, and the required level of
attenuation of the out-of-band noise. Next, we shall discuss
more advanced architecture options for designing oversampled ADCs.
Higher-Order Modulators. The oversampling ratio required
to meet a specific level of performance may be decreased below that needed in a first-order modulator by increasing
the order of the modulator. Higher-order noise shaping can
be accomplished by including a higher order filter, such as
additional integrators, in the forward path of the modulator.
However, higher-order modulators require careful attention
to the placement of appropriate zeros in the transfer function
of the analog filter (22,23). Moreover, when a higher-order
modulator is driven by a large input, the two level quantizer
is overloaded, causing an increase in the quantization noise.
The increased quantization noise is amplified by the analog
filter, leading to instability in the form of large, uncontrollable, low-frequency oscillations. Thus, third- and higher-order
modulators based on the use of a single two-level quantizer
are potentially unstable and may require circuitry to reset the
integrators when large signals are detected in the integrator
outputs (24).
Cascaded Modulators. The danger of having saturating
limit cycles in high-order modulators can be avoided by cascading a number of first- and second-order modulators to
produce the effect of high-order prediction. One such architecture is represented in Fig. 39 showing a cascade of two firstorder modulators. In this arrangement the second modulator takes at the input the quantization error of the first stage
while the outputs of both modulators are combined together.
In the combined output signal the first-stage quantization error is removed, thus leaving only the error corresponding to
the second modulator stage. The technique can generally be
extended to more than two stages and to both first- and second-order modulators.
The forgoing type of cascade architectures, called MultistAge noise SHaping (MASH) gives the advantage of achiev-

528

ANALOG-TO-DIGITAL CONVERSION

Out-of-band components

t
Fs/2

fc
(a)

Quantization noise

t
Fs/2

fc
(b)

fc

Fs/2
(c)

t
fc

Fs/2

Fs/M
(d)

Figure 38. Time-domain waveforms and signal spectra throughout the processing chain of an
oversampling ADC. (a) Sampled input analog signal. (b) Digital bitstream signal. (c) Digitally
filtered signal. (d) Decimated digital signal.

1
1 z1

First stage
Output
+

Input
+

VQ1

Delay
Integrator-1

Quantizer-1

+
1
1 z1
+

Second stage

1 z1

Delay
Figure 39. Second-order noise shaping
by cascading two first-order modulators.

Integrator-2

VQ2

Delay

Quantizer-2

Differentiator

ANALOG-TO-DIGITAL CONVERSION

MFs

4Fs

Fs

2Fs

FIR Filter
FIR
halfband
LPF

Sinc2
LPF

FIR
halfband
LPF

Figure 40. A two-stage architecture for designing the digital decimator using only FIR filter sections.

ing high-order noise shaping functions using inherently stable modulator stages (2528). Rather than regarding the
MASH architecture as a method of obtaining high-order circuits, it is usually more correct to regard it as a means of
enhancing the performance of the first modulator in the cascade. For example, a modulator composed of a second-order
sigma-delta circuit followed by a first-order circuit has attractive properties. Unfortunately, however, these modulators are
sensitive to the opamp finite dc gain as well as to mismatches
among the circuit parameter values. Their resolution is usually determined by how well individual modulators are
matched. Specifically, in switched-capacitor implementations,
cascaded modulators require close capacitance matching, high
opamp dc gain, and nearly complete settling of the integrator outputs.
Despite their attractive features, which allow lower
oversampling ratios and, therefore, higher conversion rate for
a given modulator operating speed, sophisticated modulator
architectures such as the ones discussed above do not necessarily ease the performance required on the overall circuit.
For example, a larger percentage of the thermal noise introduced by the sampling switches in switched capacitor integrators falls in the baseband. To maintain the dynamic range,
the capacitors must be increased accordingly. This implies
proportionally higher-load capacitances on the operational
amplifiers in the integrators. Also, the complexity of the antialiasing filter that precedes the modulator and the decimator
filter following it are increased. Their attenuation specifications are tighter because the sampling rate is lower with respect to the baseband.
N-Bit Quantizer. As previously discussed, the advantage of
single-bit modulators is that the linearity of the feedback
DAC is inherently ideal, besides being extremely simple for
implementation. Single-bit modulators, however, also have
the disadvantage of a large amount of quantization noise,
which may easily cause saturation and lead to potential instability conditions. Multibit quantizers, by contrast, generally
provide improved stability conditions of the modulators,

especially in the case of higher order modulators, as well as

minimization of the occurrence of idle tones. However, modulators based on a quantizer with more than two levels place
stringent linearity demands on the DAC in the feedback loop
and generally require sophisticated linearization techniques
(2932).
Decimation Filter. The output of the modulator represents
the input signal together with its spurious out-of-band components, quantization noise, and noise or interference that may
have entered the analog circuits. As already discussed, the
digital filter in the general architecture of Fig. 36 serves to
attenuate all out-of-band energy, so that the signal may be
resampled at the Nyquist rate without being corrupted with
the folded-back components of the high frequency noise.
Fairly simple digital filters would suffice to remove only
quantization noise because it rises slowly, for example at 12
dB per octave for the case of a second-order modulation. By
contrast, highly selective filters are usually needed to remove
the out-of-band components of the input. Such filters are
rather expensive when operated at high sample rates. Therefore, in practice, the decimator filter is usually implemented
in two stages, as seen in Fig. 40. First, there is a decimator
with output at four times the Nyquist rate and which is designed predominantly to remove the quantization noise component that is dominant at high frequencies. The secondstage filter resamples the signal at the Nyquist rate and
defines the baseband cut-off characteristics. Typically this is
the most complex and larger circuit and should be carefully
designed to suit the application.
A convenient filter for the first stage of decimation is based
on the Sinc function expressed as


Sinck =

Fs

Fs

Fs/M

Fs/M

z1

z1

z1

z1

z1

1
(1 z1)3

Fs/M

1 1 zM
M 1 z1

k
(32)

where M is the decimation factor and k is the order of the

filter. This filter is very easy to implement as it requires no
multipliers. It has the advantage of having zeros at the multiples of the output sample frequency, which remove the noise
components that would otherwise be aliased into the baseband with the decimation operation (3335). The order of this
filter should be equal to the modulator order plus one in order
to suppress the high frequency quantization noise adequately.
Eventually, the order of the decimating filter can be made
equal to that of the modulator, in order to reduce the implementation complexity. However, this results in some degradation of the overall signal-to-noise ratio. A typical architecture
for the implementation of a third-order Sinc filter is illustrated in Fig. 41.

Fs
+

529

Fs/M
+

(1 zM )3

Figure 41. Typical architecture of a third-order Sinc filter for digital decimation.

z1

530

ANALOG-TO-DIGITAL CONVERSION

BIBLIOGRAPHY
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9. T. Kumamoto et al., An 8-bit high-speed CMOS A/D converter,
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13281338, 1990.
12. B. Razavi and B. A. Wooley, A 12-b 5-Msample/s two-step CMOS
A/D converter, IEEE J. Solid-State Circuits, 27: 16671678, 1992.
13. S. H. Lewis and P. R. Gray, A pipelined 5-Msample/s 9-bit analog-to-digital converter, IEEE J. Solid-State Circuits, SC-22: 954
961, 1987.
14. B. Song, M. F. Tompset, and K. R. Lakshmikumar, A 12-bit 1Msample/s capacitor error-averaging pipelined A/D converter,
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23. D. R. Welland et al., A stereo 16-bit delta-sigma A/D converter

for digital audio, J. Audio Eng. Soc., 37 (6): 476486, 1989.
24. S. Mohsen Moussavi and B. H. Leung, High-order single-stage
single-bit oversampling A/D converter stabilized with local feedback loops, IEEE Trans. Circuits Syst.-II: Analog Digital Signal
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25. Y. Matsuya et al., A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping, IEEE J. Solid-State
Circuits, SC 22: 921929, 1987.
26. M. Rebeschini et al., A 16-bit 160-kHz CMOS A/D converter using sigma-delta modulation, IEEE J. Solid-State Circuits, 25:
431440, 1990.
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modulator for 12-b 2-MHz A/D conversion, IEEE J. Solid-State
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fourth-order A/D converter in BiCMOS technology, IEEE J.
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in sigma delta modulators, Int. Conf. Acoustics, Speech, Signal
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filter for decimation and interpolation, IEEE J. Solid-State Circuits, 29: 679687, 1994.

JOSE EPIFANIO DA FRANCA

CARLOS AZEREDO LEME
JOA O CALADO VITAL

15. W. C. Black, Jr. and D. A. Hodges, Time interleaved converter

arrays, IEEE J. Solid-State Circuits, SC-15: 10221029, 1980.

Instituto Superior Tecnico

16. C. S. G. Conroy, D. W. Cline, and P. R. Gray, An 8-b 85-MS/s

parallel pipeline A/D converter in 1m CMOS, IEEE J. SolidState Circuits, 28: 447454, 1993.
17. J. Franca, A. Petraglia, and S. Mitra, Multirate analog-digital
systems for signal processing and conversion, Proc. IEEE, 85:
242262, 1997.

ANALYSIS AND DESIGN ALGORITHMS FOR CONTROL SYSTEMS. See SOFTWARE FOR CONTROL SYSTEM

18. S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data

Converters, Theory, Design and Simulation, New York: IEEE
Press, 1997.

ANALYSIS, CEPSTRAL OF SPEECH. See CEPSTRAL

19. J. C. Candy, A use of double integration in sigma delta modulation, IEEE Trans. Commun., COM-33: 249258, 1985.
20. J. C. Candy and O. J. Benjamin, The structure of quantization
noise from sigma-delta modulation, IEEE Trans. Commun.,
COM-29: 13151323, 1981.
21. B. E. Boser and B. A. Wooley, The design of sigma-delta modulation analog-to-digital converters, IEEE J. Solid-State Circuits, 23:
12981308, 1988.
22. K. S. Chao et al., A higher order topology for interpolative modulators for oversampling A/D converters, IEEE Trans. Circuits
Syst., 37: 309318, 1990.

ANALYSIS AND DESIGN, SINGULAR VALUE DECOMPOSITION.

ANALYSIS OF SPEECH.

ANALYSIS, COST. See COST ANALYSIS.

ANALYSIS, COST-BENEFIT. See COST-BENEFIT ANALYSIS.
ANALYSIS, INTERVAL, FOR CIRCUITS. See INTERVAL
ANALYSIS FOR CIRCUITS.

ANALYSIS, NETWORK. See NETWORK ANALYSIS USING

LINEARIZATION.

ANALYSIS, OF CIRCUITS IN THE FREQUENCY DOMAIN. See FREQUENCY-DOMAIN CIRCUIT ANALYSIS.

ANALYSIS OF FAILURE MODES AND EFFECTS.
See FAILURE MODES AND EFFECTS ANALYSIS.

ANTENNA ACCESSORIES

ANALYSIS OF MICROWAVE AND MILLIMETERWAVE STRUCTURES. See SPECTRAL-DOMAIN ANALYSIS.

ANALYSIS OF RELIABILITY DATA. See STATISTICAL
ANALYSIS OF RELIABILITY DATA.

ANALYSIS,
CUITS.
ANALYSIS,
ANALYSIS,

QUALITATIVE OR DYNAMIC CIRSee QUALITATIVE ANALYSIS OF DYNAMIC CIRCUITS.

SENSITIVITY. See SENSITIVITY ANALYSIS.

SPEECH. See SPEECH ANALYSIS; SPEECH

PROCESSING

ANALYSIS, SYSTEMS. See SYSTEMS ANALYSIS.

ANALYSIS, TRANSIENT. See TRANSIENT ANALYSIS.
ANALYZER, POWER SYSTEM. See POWER SYSTEM MEASUREMENT.

ANIMATION, COMPUTER. See COMPUTER ANIMATION.

ANNUNCIATORS. See ALARM SYSTEMS.

531

716

ASYNCHRONOUS CIRCUITS

ASYNCHRONOUS CIRCUITS
Digital Very Large Scale Integration (VLSI) circuits are usually classified into synchronous and asynchronous circuits.
Synchronous circuits are generally controlled by global synchronization signals provided by a clock. Asynchronous circuits, on the other hand, do not use such global synchronization signals. Between these extremes there are various
hybrids. Digital circuits in todays commercial products are
almost exclusively synchronous. Despite this big difference in
popularity, there are a number of reasons why asynchronous
circuits are of interest.
In this article, we present a brief overview of asynchronous
circuits. First we address some of the motivations for designing asynchronous circuits. Then, we discuss different classes
of asynchronous circuits and briefly explain some asynchronous design methodologies. Finally, we present an asynchronous design in detail.
MOTIVATIONS FOR ASYNCHRONOUS CIRCUITS
Throughout the years researchers have had a number of reasons for studying and building asynchronous circuits. Some of
the often mentioned advantages of asynchronous circuits are
speed, low energy dissipation, modular design, immunity to
metastable behavior, freedom from clock skew, and low generation of and low susceptibility to electromagnetic interference. We elaborate here on some of these potentials and indicate when they have been demonstrated through comparative
case studies.
Speed
Speed has always been a motivation for designing asynchronous circuits. The main reasoning behind this advantage is
that synchronous circuits exhibit worst-case behavior,
whereas asynchronous circuits exhibit average-case behavior.
The speed of a synchronous circuit is governed by its clock
frequency. The clock period should be large enough to accommodate the worst-case propagation delay in the critical path
of the circuit, the maximum clock skew, and a safety factor
due to fluctuations in the chip fabrication process, operating
temperature, and supply voltage. Thus, synchronous circuits
exhibit worst-case performance, in spite of the fact that the
worst-case propagation in many circuits, particularly arithmetic units, may be much longer than the average-case propagation.
Many asynchronous circuits are controlled by local communications and are based on the principle of initiating a computation, waiting for its completion, and then initiating the next
one. When a computation has completed early, the next computation can start early. For this reason, the speed of asynchronous circuits equipped with completion-detection mechanisms depend on the computation time of the data being
processed, not the worst-case timing. Accordingly, such asynchronous circuits exhibit average-case performance. An example of an asynchronous circuit where the average-case potential is nicely exploited is reported in (1), an asynchronous
divider that is twice as fast as its synchronous counterpart.
Nevertheless, to date, there are few concrete examples demonstrating that the average-case performance of asynchronous circuits is higher than that of synchronous circuits perJ. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

ASYNCHRONOUS CIRCUITS

forming similar functions. The reason is that the average-case

performance advantage is often counterbalanced by the overhead in control circuitry and completion-detection mechanisms.
Besides demonstrating the average-case potential, there
are case studies in which the speed of an asynchronous design
is compared to the speed of a corresponding synchronous version. Molnar et al. report a case study (2) of an asynchronous
FIFO that is every bit as fast as any synchronous FIFO using
the same data latches. Furthermore, the asynchronous FIFO
has the additional benefit that it operates under local control
and is easily expandable. At the end of this article, we give
an example of a FIFO with a different control circuit.
Immunity to Metastable Behavior
Any circuit with a number of stable states also has metastable states. When such a circuit gets into a metastable state,
it can remain there for an indefinite period of time before resolving into a stable state (3,4). Metastable behavior occurs,
for example, in circuit primitives that realize mutual exclusion between processes, called arbiters, and components that
synchronize independent signals of a system, called synchronizers. Although the probability that metastable behavior
lasts longer than period t decreases exponentially with t, it is
possible that metastable behavior in a synchronous circuit
lasts longer than one clock period. Consequently, when metastable behavior occurs in a synchronous circuit, erroneous
data may be sampled at the time of the clock pulses. An asynchronous circuit deals gracefully with metastable behavior by
simply delaying the computation until the metastable behavior has disappeared and the element has resolved into a stable state.
Modularity
Modularity in design is an advantage exploited by many asynchronous design styles. The basic idea is that an asynchronous system is composed of functional modules communicating along well-defined interfaces. Composing asynchronous
systems is simply a matter of connecting the proper modules
with matching interfacial specifications. The interfacial specifications describe only the sequences of events that can take
place and do not specify any restrictions on the timing of
these events. This characteristic reduces the design time and
complexity of an asynchronous circuit, because the designer
does not have to worry about the delays incurred in individual
modules or the delays inserted by connection wires. Designers
of synchronous circuits, on the other hand, often pay considerable attention to satisfying the detailed interfacial timing
specifications.
Besides ease of composability, modular design also has the
potential for better technology migration, ease of incremental
improvement, and reuse of modules (5). Here the idea is that
an asynchronous system adapts itself more easily to advances
in technology. The obsolete parts of an asynchronous system
can be replaced with new parts to improve system performance. Synchronous systems cannot take advantage of new
parts as easily, because they must be operated with the old
clock frequency or other modules must be redesigned to operate at the new clock frequency.
One of the earliest projects that exploited modularity in
designing asynchronous circuits is the Macromodules project

717

(6). Another example where modular design is demonstrated

is the TANGRAM compiler developed at Philips Research
Laboratories (7).
Low Power
Due to rapid growth in the use of portable equipment and the
trend in high-performance processors towards unmanageable
power dissipation, energy efficiency has become crucial in
VLSI design. Asynchronous circuits are attractive for energyefficient designs, mainly because the clock is eliminated. In
systems with a global clock, all of the latches and registers
operate and consume dynamic energy during each clock pulse,
in spite of the fact that many of these latches and registers
may not have new data to store. There is no such waste of
energy in asynchronous circuits, because computations are
initiated only when necessary.
Two notable examples that demonstrated the potential of
asynchronous circuits in energy-efficient design are the work
done at Philips Research Laboratories and at Manchester
University. The Philips group designed a fully asynchronous
digital compact-cassette (DCC) error detector which consumed 80% less energy than a similar synchronous version
(8). The AMULET group at Manchester University successfully implemented an asynchronous version of the ARM microprocessor, one of the most energy-efficient synchronous microprocessors. The asynchronous version achieved a power
dissipation comparable to the fourth generation of ARM,
around 150 mW (9), in a similar technology.
Recently, power management techniques are being used in
synchronous systems to turn the clock on and off conditionally. However, these techniques are only worthwhile implementing at the level of functional units or higher. Besides,
the components that monitor the environment for switching
the clock continue dissipating energy.
It is also worth mentioning that, unlike synchronous circuits, most asynchronous circuits do not waste energy on hazards, which are spurious changes in a signal. Asynchronous
circuits are essentially designed to be hazard-free. Hazards
can be responsible for up to 40% of energy loss in synchronous
circuits (10).
Freedom from Clock Skew
Because asynchronous circuits generally do not have clocks
they do not have many of the problems associated with clocks.
One such problem is clock skew, the technical term for the
maximum difference in clock arrival time at different parts of
a circuit. In synchronous circuits, it is crucial that all modules
operating with a common clock receive this signal simultaneously, that is, within a tolerable period of time. Minimizing
clock skew is a difficult problem for large circuits. Various
techniques have been proposed to control clock skew, but generally they are expensive in terms of silicon area and energy
dissipation. For instance, the clock distribution network of
the DEC Alpha, a 200 MHz microprocessor at a 3.3 V supply,
occupies 10% of the chip area and uses 40% of the total chip
power consumption (11). Although asynchronous circuits do
not have clock skew problems, they have their own set of
problems in minimizing the overhead needed for synchronization among the parts.

718

ASYNCHRONOUS CIRCUITS

MODELS AND METHODOLOGIES

There are many models and methodologies for analyzing and
designing asynchronous circuits. Asynchronous circuits can
be categorized by the following criteria: signaling protocol and
data encoding, underlying delay model, mode of operation,
and formalism for specifying and designing circuits. This section presents an informal explanation of these criteria.

Request
S
e
n
d
e
r

n
Data

Acknowledge

R
e
c
e
i
v
e
r

(a) Bundled data convention

Signaling Protocols and Data Encodings

Modules in an asynchronous circuit communicate data with
some signaling protocol consisting of request and acknowledgment signals. There are two common signaling protocols for
communicating data between a sender and a receiver, the
four-phase and the two-phase protocol. In addition to the signaling protocol, there are different ways to encode data. The
most common encodings are single-rail and dual-rail encoding. We explain the two signaling protocols first and then discuss the data encodings.
If the sender and receiver communicate through a twophase signaling protocol, then each communication cycle has
two distinct phases. The first phase consists of a request initiated by the sender. The second phase consists of an acknowledgment by the receiver. The request and acknowledgment
signals are often implemented by voltage transitions on separate wires. No distinction is made between the directions of
voltage transitions. Both rising and falling transitions denote
a signaling event.
The four-phase signaling protocol consists of four phases, a
request followed by an acknowledgment, followed by a second
request, and finally a second acknowledgment. If the request
and acknowledgment are implemented by voltage transitions,
then at the end of every four phases, the signaling wires return to the same voltage levels as at the start of the four
phases. Because the initial voltage is usually zero, this type
of signaling is also called return-to-zero signaling. Other
names for two-phase and four-phase signaling are two-cycle
and four-cycle signaling, respectively, or transition and level
signaling, respectively.
Both signaling protocols are used with single and dual-rail
data encodings. In single-rail data encoding each bit is encoded with one wire, whereas in dual-rail encoding, each bit
is encoded with two wires.
In single-rail encoding, the value of the bit is represented
by the voltage on the data wire. When communicating n data
bits with a single-rail encoding during periods where the data
wires are guaranteed to remain stable, we say that the data
are valid. During periods where the data wires are possibly
changing, we say the data are invalid. A two-phase or fourphase signaling protocol is used to tell the receiver when data
are valid or invalid. The sender informs the receiver about
the validity of the data through the request signal, and the
receiver, in turn, informs the sender of the receipt of the data
through the acknowledgment signal. Therefore, to communicate n bits of data, a total number of (n 2) wires are necessary between the sender and the receiver. The connection pattern for single-rail encoding and two or four-phase signaling
is depicted in Fig. 1(a).
Figure 2(a) shows the sequence of events in a two-phase
signaling protocol. The events include the times when the
data become valid and invalid. The transparent bars indicate
the periods when data are valid. During the other periods,

S
e
n
d
e
r

2n
Data

Acknowledge

R
e
c
e
i
v
e
r

(b) Dual-rail data encoding

Figure 1. Two different data communication schemes.

data are invalid. Notice that a request signal occurs only after
data become valid. This is an important timing restriction associated with these communication protocols, namely, the request signal that indicates that data are valid should always
arrive at the receiver after all data wires have attained their
proper value. The restriction is referred to as the bundling
constraint. For this reason the communication protocol is often called the bundled data protocol. Figure 2(b) shows a sequence of events in a four-phase protocol and single-rail data
encoding. Other sequences are also applicable for the fourphase protocol.
The dual-rail encoding scheme uses two wires for every
data bit. There are several dual-rail encoding schemes. All
combine the data encoding and signaling protocol. There is no
explicit request signal, and the dual-rail encoding schemes all
require (2n 1) wires as illustrated in Fig. 1(b). In four-phase
signaling, there are several encodings that are used to transmit a data bit. The most common encoding has the following
meaning for the four states in which each pair of wires can
be, 00 reset, 10 valid 0, 01 valid 1, and 11 is an unused
state. Every pair of wires has to go through the reset state
before becoming valid again. In the first phase of the fourphase signaling protocol, every pair of wires leaves the reset
state for a valid 0 or 1 state. The receiver detects the arrival
of a new set of valid data when all pairs of wires have left the
reset state. This detection replaces an explicit request signal.
The second phase consists of an acknowledgment to inform
the sender that data has been consumed. The third phase consists of the reset of all pairs of wires to the reset state, and
the fourth phase is the reset of the acknowledgment.
In a two-phase signaling protocol, a different dual-rail encoding is used. An example of an encoding is as follows. Each
pair of wires has one wire associated with a 0 and one wire
associated with a 1. A transition on the wire associated with
0 represents the communication of a 0, whereas a transition
on the other wire represents a communication of a 1. Thus, a
transition on one wire of each pair signals the arrival of a
new bit value. A transition on both wires is not allowed. In
the first phase of the two-phase signaling protocol every pair
of wires communicates a 0 or a 1. The second phase is an
acknowledgment sent by the receiver.
Of all data encodings and signaling protocols, the most
popular are the single-rail encoding and four-phase signaling
protocol. The main advantages of these protocols are the
small number of connecting wires and the simplicity of the
encoding, which allows using conventional techniques for implementing data operations. The disadvantage of these protocols are the bundling constraints that must be satisfied and
the extra energy and time wasted in the additional two
phases compared with two-phase signaling. Dual-rail data en-

ASYNCHRONOUS CIRCUITS

Request

719

Request

Data

Data

Acknowledge

Acknowledge

One cycle

One cycle

(a)

(b)

Figure 2. Data transfer in (a) two-phase signaling and (b) four-phase signaling.

codings are used to communicate data in asynchronous circuits free of any timing constraints. Dual-rail encodings, however, are expensive in practice, because of the many
interconnecting wires, the extra circuitry to detect completion
of a transfer, and the difficulty in data processing.
Delay Models
An important characteristic distinguishing different asynchronous circuit styles is the delay model on which they are
based. For each circuit primitive, gate or wire, a delay model
stipulates the sort of delay it imposes and the range of the
delays. Delay models are needed to analyze all possible behavior of a circuit for various correctness conditions, like the
absence of hazards.
A circuit is composed of gates and interconnecting wires,
all of which impose delays on the signals propagating through
them. The delay models are categorized into two classes, pure
delay models and inertial delay models. In a pure delay
model, the delay associated with a circuit component produces only a time shift in the voltage transitions. In reality,
a circuit component may shift the signals and also filter out
pulses of small width. Such a delay model is called an inertial
delay model. Both classes of delay models have several ranges
for the delay shifts. We distinguish the zero-delay, fixed-delay,
bounded-delay, and unbounded-delay models. In the zero-delay model, the values of the delays are zero. In the fixed-delay
model, the values of the delays are constant, whereas in the
bounded-delay model the values of the delays vary within a
bounded range. The unbounded-delay model does not impose
any restriction on the value of the delays except that they
cannot be infinite. Sometimes two different delay models are
assumed for the wires and the gates in an asynchronous circuit. For example, the operation of a class of asynchronous
circuits is based on the zero-delay model for wires and the
unbounded-delay model for gates. Formal definitions of the
various delay models are given in (12).
A concept closely related to the delay model of a circuit is
its mode of operation. The mode of operation characterizes the
interaction between a circuit and its environment. Classical
asynchronous circuits operate in the fundamental mode
(13,14), which assumes that the environment changes only
one input signal and waits until the circuit reaches a stable
state. Then the environment is allowed to apply the next
change to one of the input signals. Many modern asynchronous circuits operate in the input-output mode. In contrast to
the fundamental mode, the input-output mode allows input

changes immediately after receiving an appropriate response

to a previous input change, even if the entire circuit has not
yet stabilized. The fundamental mode was introduced in the
1960s to simplify analyzing and designing gate circuits with
Boolean algebra. The input-output mode evolved in the eighties from event-based formalisms to describe modular design
methods that abstracted from the internal operation of a
circuit.
Formalisms
Just as in any other design discipline, designers of asynchronous circuits use various formalisms to master the complexities in designing and analyzing their artifacts. The formalisms used in asynchronous circuit design are categorized into
two classes, formalisms based on Boolean algebra and formalisms based on sequences of events. Most design methodologies in asynchronous circuits use some mixture of both formalisms.
The design of many asynchronous circuits is based on Boolean algebra or its derivative switching theory. Such circuits
often use the fundamental mode of operation, the boundeddelay model, and have, as primitive elements, gates that correspond to the basic logic functions, like AND, OR, and inversion. These formalisms are convenient for implementing logic
functions, analyzing circuits for the presence of hazards, and
synthesizing fundamental-mode circuits (12,14).
Event-based formalisms deal with sequences of events
rather than binary logic variables. Circuits designed with an
event-based formalism operate in the input-output mode, under an unbounded-delay model, and have, as primitive elements, the JOIN, the TOGGLE, and the MERGE, for example.
Event-based formalisms are particularly convenient for designing asynchronous circuits when a high degree of concurrency is involved. Several tools have been generated for automatically verifying asynchronous circuits with event-based
formalisms (15,16). Examples of event-based formalisms are
trace theory (1719), DI algebra (20), Petri nets, and signal
transition graphs (21,22).

DESIGN TECHNIQUES
This section introduces the most popular types of asynchronous circuits and briefly describes some of their design techniques.

720

ASYNCHRONOUS CIRCUITS

TYPES OF ASYNCHRONOUS CIRCUITS

There are special types of asynchronous circuits for which formal and informal specifications have been given. Here are
brief informal descriptions of some of them in a historical
context.
There are two types of logic circuits, combinational and sequential. The output of a combinational circuit depends only
on the current inputs, whereas the output of a sequential circuit depends on the previous sequence of inputs. With this
definition of a sequential circuit, almost all asynchronous circuit styles fall into this category. However, the term asynchronous-sequential circuits or machines generally refers to
those asynchronous circuits based on finite-state machines
similar to those in synchronous sequential circuits (14,23).
Muller was the first to rigorously formalize a special type
of circuit for which he coined the name speed-independent circuit. An account of this formalization is given in (24,25). Informally, a speed-independent circuit is a network of gates
that satisfies its specification irrespective of any gate delays.
From a design discipline that was developed as part of the
Macromodules project (6) at Washington University in St.
Louis, the concept of another type of asynchronous circuits
evolved, which was given the name delay-insensitive circuit,
that is, a network of modules that satisfies its specification
irrespective of any element and wire delays. It was realized
that proper formalization of this concept was needed to specify and design such circuits in a well-defined manner. Such a
formalization was given by Udding (26).
Another name frequently used in designing asynchronous
circuits is self-timed systems. This name was introduced by
Seitz (27). A self-timed system is described recursively as either a self-timed element or a legal connection of self-timed
systems. The idea is that self-timed elements can be implemented with their own timing discipline, and some may even
have synchronous implementations. In other words, the elements keep time to themselves. In composing self-timed systems from self-timed elements, however, no reference to the
timing of events is made. Only the sequence of events is relevant.
Some have found that the unbounded gate-and-wire delay
assumption, on which the concept of a delay-insensitive circuit is based, is too restrictive in practice. For example, the
unbounded gate-and-wire delay assumption implies that a
signal sent to multiple recipients by a fork incurs a different
unbounded delay for each of the recipients. In (28) it is proposed to relax this delay assumption slightly by using isochronic forks. An isochronic fork is a fork whose difference in
the delays of its branches is negligible compared with the delays in the element to which it is connected. A delay-insensitive circuit that uses isochronic forks is called a quasi-delayinsensitive circuit (17,28). Although isochronic forks give more
design freedom in exchange for less delay insensitivity, care
has to be taken with their implementation (29).
Asynchronous-Sequential Machines
The design of asynchronous-sequential, finite-state machines
was initiated with the pioneering work of Huffman (23). He
proposed a structure similar to that of synchronous-sequential circuits consisting of a combinational logic circuit, inputs,
outputs, and state variables (14). Huffman circuits, however,

store the state variables in feedback loops containing delay

elements, instead of in latches or flip-flops, as synchronoussequential circuits do. The design procedure begins with creating a flow table and reducing it through some state minimization technique. After a state assignment, the procedure
obtains the Boolean expressions and implements them in
combinational logic with the aid of a logic minimization program. To guarantee a hazard-free operation, Huffman circuits
adopt the restrictive single-input-change fundamental mode,
that is, the environment changes only one input and waits
until the circuit becomes stable before changing another input. This requirement substantially degrades the circuit performance. Hollaar realized this fact and introduced a new
structure in which the fundamental mode assumption is relaxed (30). In his implementation, the state variables are
stored in NAND latches, so that inputs are allowed to change
earlier than the fundamental mode allows. Although Hollaars method improves the performance, it suffers from the
danger of producing hazards. Besides, neither technique is
adequate for designing concurrent systems. Models and algorithms for analyzing asynchronous-sequential circuits have
been developed by Brzozowski and Seger (12).
The quest for more concurrency, better performance, and
hazard-free operation, resulted in the formulation of a new
generation of asynchronous-sequential circuits known as
burst-mode machines (31,32). A burst-mode circuit does not
react until the environment performs a number of input
changes called an input burst. The environment, in turn, is
not allowed to introduce the next input burst until the circuit
produces a number of outputs called an output burst. A state
graph is used to specify the transitions caused by the input
and output bursts. Two synthesis methods have been proposed and automated for implementing burst-mode circuits.
The first method employs a locally generated clock to avoid
some hazards (33). The second method uses three-dimensional flow tables and is based on Huffman circuits (34). One
limitation of burst mode circuits is that they restrict concurrency within a burst.
Speed-Independent Circuits and STG Synthesis
Speed-independent circuits are usually designed by a form of
Petri nets (35). A popular version of Petri nets, signal-transition graphs (STG), was introduced by Chu. He also developed
a synthesis technique for transforming STGs into speed-independent circuits (21). Chus work was extended by Meng, who
produced an STG-based tool for synthesizing speed-independent circuits from high-level specifications (36). In this technique, a circuit is composed of computational and interconnecting blocks. Computational blocks range from a simple
shifter module to more complicated ones, such as ALUs,
RAMs, and ROMs. Interconnecting blocks synchronize the
operation of computational blocks by producing appropriate
control signals. Computational blocks generate completion
signals after their output data becomes valid. The interconnecting blocks use the completion signals to generate fourphase handshake protocols.
Delay-Insensitive Circuits and Compilation
Several researchers have proposed techniques for designing
delay-insensitive circuits. Ebergen (37) has developed a synthesis method based on the formalism of trace theory. The

ASYNCHRONOUS CIRCUITS

WIRE

IWIRE

a
c

JOIN
b
a
MERGE

TOGGLE

b
c

Figure 3. Some primitives in event-based designs.

method consists of specifying a component by a program and

then transforming this program into a delay-insensitive network of basic elements (18).
Martin proposes a method (28) that starts with the specification of an asynchronous circuit in a high-level programming language similar to Hoares Communicating Sequential
Processes (CSP) (38). An asynchronous circuit is specified as
a group of processes communicating over channels. After various transformations, the program is mapped into a network
of gates. This method led to the design of an asynchronous
microprocessor (39) in 1989. Martins method yields quasidelay-insensitive circuits.
Van Berkel (17) designed a compiler based on a high-level
language called Tangram. A Tangram program also specifies
a set of processes communicating over channels. A Tangram
program is first translated into a handshake circuit. Then
these handshake circuits are mapped into various target architectures, depending on the data-encoding techniques or
standard-cell libraries used. The translation is syntax-directed, which means that every operation occurring in a Tangram program corresponds to a primitive in the translated
handshake circuit. This property is exploited by various tools
that quickly estimate the area, performance, and energy dissipation of the final design by analyzing the Tangram program. Van Berkels method also yields quasi-delay-insensitive circuits.
Other translation methods from a CSP-like language to a
(quasi-) delay-insensitive circuit are in (40,41).

The simplest primitive is the WIRE, a two-terminal element

that produces an output event on its output terminal b after
every input event on its input terminal a. Input and output
events in a WIRE must alternate. An input event a must be
followed by an output event b before another event a occurs.
A WIRE is physically realizable with a wire, and events are
implemented by voltage transitions. An initialized WIRE, or
IWIRE, is very similar to a WIRE, except that it starts by producing an output event b instead of accepting an input event
a. After this, its behavior exactly resembles that of a WIRE.
The primitive for synchronization is the JOIN, also called
the RENDEZVOUS (6). A JOIN has two inputs a and b and one
output c. The JOIN performs the AND operation of two events
a and b. It produces an output event c only after both of its
inputs, a and b, receive an event. The inputs can change
again after an output is produced. A JOIN can be implemented
by a Muller C-element, explained in the next section.
The MERGE component performs the OR operation of two
events. If a MERGE component receives an event on either of
its inputs, a or b, it produces an output event c. After an input
event, there must be an output event. Successive input events
are not allowed. A MERGE is implemented by a XOR gate.
The TOGGLE has a single input a and two outputs b and c.
After an event on input a, an event occurs on output b. The
next event on a results in a transition on output c. An input
event must be followed by an output event before another input event can occur. Thus, output events alternate or toggle
after each input event. The dot in the TOGGLE schematic indicates the output which produces the first event.
The Muller C-Element
The Muller C-element is named for its inventor D. E. Muller
(24). Traditionally, its logical behavior is described as follows.
If both inputs are 0 (1), then the output becomes 0 (1). Otherwise the output remains the same. For the proper operation
of the C-element, it is also assumed that, once both inputs
become 0 (1), they do not change again until the output
changes. A state diagram is given in Figure 4. The behavior
of the output c of the C-element is expressed in terms of the
inputs a and b and the previous state of the output c by the
following Boolean function:
c = [c (a + b)] + (a b)

(1)

The C-element is used to implement the JOIN, which has a

slightly more restrictive environment behavior in the sense
that an input is not allowed to change twice in succession. A

AN ASYNCHRONOUS DESIGN EXAMPLE

In this section we present a typical asynchronous design, a
micropipeline (5). The circuit uses single-rail encoding with
the two-phase signaling protocol to communicate data between stages of the pipeline. The control circuit for the pipeline is a delay-insensitive circuit. First we present the primitives for the control circuit, then we present the latches that
store the data, and finally we present the complete design.

100

011
b

a
000

110
b

a
c

111

001
b

a
010

a
101

The Control Primitives

Figure 3 shows a few simple primitives used in event-based
design styles. The schematic symbol for each primitive is depicted opposite its name.

721

(c)
Figure 4. State diagram of the C-element.

722

ASYNCHRONOUS CIRCUITS

VDD
VDD

a
a

P1

P2

P3

P4

P1

P2

P5

c
N2

N1

N4

P4

P6
c

N2

N6
N3

N5

P3

P5

P6

N4

N3

N6

N5

a
a

c
N1

(b)

(a)

Figure 5. Two CMOS implementations of the C-element: (a) conventional and (b) symmetric.

state graph for the JOIN is produced by replacing the bidirectional arcs by unidirectional arcs.
There are many implementations of the C-element. We
have given two popular CMOS implementations in Figure 5.
Implementation (a) is a conventional pull-up, pull-down implementation suggested by Sutherland (5). Implementation
(b) is suggested by Van Berkel (29). Each implementation has
its own characteristics. Implementation (b) is the best choice
for speed and energy efficiency (42). There are many variations of the C-element and other elements that are convenient
for the design of asynchronous circuits. For some of these
variations and their uses, in particular the asymmetric C-element, see Ref. 28.
Storage Primitives
Two event-controlled latches due to Sutherland (5) are depicted in Figure 6. Their operation is managed through two
input control signals, capture and pass, labeled c and p, respectively. They also have two output control signals, capture
done, cd, and pass done, pd. The input data is labeled D, and
the output data is labeled Q. Implementation (a) is composed

of three so-called double-throw switches. Implementation (b)

includes a MERGE, a TOGGLE, and a level-controlled latch consisting of a double-throw switch and an inverter.
A double-throw switch is schematically represented by an
inverter and a switching tail. The tail toggles between two
positions based on the logic value of a controlling signal. A
double-throw switch, in fact, is a two-input multiplexer that
produces an inverted version of its selected input. A CMOS
implementation of the double-throw switch is shown in Figure 7 (5). The position of the switch corresponds to the state
where c is low.
An event-controlled latch can assume two states, transparent and opaque. In the transparent state no data is latched,
but the output replicates the input, because a path of two
inverting stages exists between the input and the output. In
the opaque state, this path is disconnected so that the input
data may change without affecting the output. The current
data at the output, however, is latched. Implementations in
Figs. 6(a) and 6(b) are both shown in their initial transparent
states. The capture and pass signals in an event-controlled
latch always alternate. Upon a transition on c, the latch cap-

p
M

D
D

Figure 6. Two event-driven latch implementations.

pd

cd
(a)

pd

cd
(b)

ASYNCHRONOUS CIRCUITS

VDD

c
x

y
c

Figure 7. A CMOS implementation of a double-throw switch.

tures the current input data and becomes opaque. The following transition on cd is an acknowledgment to the data provider that the current data is captured and that the input
data can be changed safely. A subsequent transition on p returns the latch to its transparent state to pass the next data
to its output. The p signal is acknowledged by a transition on
pd. Notice that in implementation (a) of Fig. 6 signals cd and
pd are merely delayed and possibly amplified versions of c
and p, respectively.
A group of event-controlled latches, similar to implementation (a) of Fig. 6, can be connected, sharing a capture wire
and a pass wire, to form an event-controlled register of arbitrary data width. Implementation (b) of Fig. 6 can be generalized similarly into a register by inserting additional level-controlled latches between the MERGE and the TOGGLE. A
comparison of different micropipeline latches is reported in
(43) and later in (44).
Pipelining
Pipelining is a powerful technique for constructing high-performance processors. Micropipelines are elegant asynchro-

Rin

r2

a1

pd

cd

nous circuits that have gained much attention in the asynchronous community. Many VLSI circuits based on
micropipelines have been successfully fabricated. The AMULET microprocessor (9) is one example. Although there are
many asynchronous implementations of micropipelines, we
only show an asynchronous implementation based on twophase signaling and data bundling, as given in Ref. 5. For
other implementations of pipelines involving four-phase signaling, the reader is referred to Ref. 45.
The simplest form of a micropipeline is a First-In-FirstOut (FIFO) buffer. A four-stage FIFO is shown in Figure 8. It
has a control circuit composed solely of interconnected JOINs
and a data path of event-controlled registers. The control signals are indicated by dashed lines. The thick arrows show the
direction of data flow. Data is implemented with single-rail
encoding, and the data path is as wide as the registers can
accommodate. Adjacent stages of the FIFO communicate
through a two-phase, bundled-data signaling protocol. This
means that a request arrives at the next stage only when the
data for that stage becomes valid. A bubble at the input of a
JOIN is a shorthand for a JOIN with an IWIRE on that input. It
implies that, initially, an event has already occurred on the
input with the bubble, and the JOIN produces an output event
immediately upon receiving an event on the other input.
Initially, all control wires of the FIFO are at a low voltage
and the data in the registers are not valid. The FIFO is activated by a rising transition on Rin, which indicates that input
data is valid. Subsequently, the first-stage JOIN produces a
rising output transition. This signal is a request to the firststage register to capture the data and become opaque. After
capturing the data, the register produces a rising transition
on its cd output terminal. This causes a transition on Ain and
a transition on r1, which is a request to the second stage of
the FIFO. Meanwhile, the data has proceeded to the secondstage register and has arrived there before the transition on
r1 occurs. If the environment does not send any new data, the
first stage remains idle, and the data and the request signals
propagate further to the right. Notice that each time the data
is captured by a stage, an acknowledgment is sent back to the
previous stage which causes its latch to become transparent
again. When the data has propagated to the last register, it

Rout

a3

723

pd

cd

p
Dout

Din

Reg
cd

Ain

Reg

r1

pd

a2

Reg
cd

Reg

r3

pd

Aout

Figure 8. A four-stage micropipeline

FIFO structure.

ASYNCHRONOUS CIRCUITS

Ain

Delay

is stored and a request signal Rout is forwarded to the consumer of the FIFO. At this point, all control signals are at a
high voltage except for Aout. If the data is not removed out of
the FIFO, that is, Aout remains at low voltage, the next data
coming from the producer advances only up to the third-stage
register, because the fourth-stage JOIN cannot produce an output. Finally, Aout also becomes high when the consumer acknowledges receipt of the data. Further data storage and removal follows the same pattern. The operation of each JOIN is
interpreted as follows. If the previous stage has sent a request
for data capture and the present stage is empty, then send a
signal to capture the data in the present stage.
The FIFO is modified easily to include data processing. A
four-stage micropipeline, in its general form, is illustrated in
Figure 9. Now the data path consists of alternately positioned
event-driven registers and combinational logic circuits. The
event-driven registers store the input and output data of the
combinational circuits, and the combinational circuits perform the necessary data processing. To satisfy the databundling constraint, delay elements are occasionally required
to slow down the propagation of the request signals. A delay
element must at least match the delay through its corresponding combinational logic circuit, either by some completion detection mechanism or by inserting a worst-case delay.
A micropipeline FIFO is flexible in the number of data
items it buffers. There is no restriction on the rate at which
data enter or exit the micropipeline, except for the delays imposed by the circuit elements. That is why this FIFO and micropipelines generally are termed elastic. In contrast, in an
ordinary synchronous pipeline, the rates at which data enter
and exit the pipeline are the same, dictated by the external
clock signal. A micropipeline is also flexible in the amount of
energy it dissipates, which is proportional to the number of
data movements. A clocked pipeline, however, continuously
dissipates energy as if all stages of pipeline capture and pass
data all the time. Another attractive feature of a micropipeline is that it automatically shuts off when there is no activity. A clocked pipeline, on the other hand, requires a special
clock management mechanism to implement this feature.
This sensing mechanism, however, constantly consumes energy because it should never go idle.

Reg
c

r1

pd

pd

Reg
cd

a2

cd
Logic

cd

Delay

Logic

pd

Reg
cd

Figure 9. A general four-stage micropipeline structure.

Rout

a3

Delay

c
Din

r2

a1

Delay

Reg
c

r3

p
Logic

Rin

Logic

724

Dout

pd

Aout

CONCLUDING REMARKS
We have touched only on a few topics relevant to asynchronous circuits and omitted many others. Among the topics
omitted are the important areas of verifying, testing, and analyzing the performance of asynchronous circuits. We hope,
however, that within the scope of these pages we have provided enough information for further reading. For more information on asynchronous circuits, see (12, 46, or 47). A comprehensive bibliography of asynchronous circuits is in (48).
Up-to-date information on research in asynchronous circuit
design is at (49).
The authors wish to thank Bill Coates for his generous
criticisms of a previous draft of this article.

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for the DCC player, IEEE J. Solid-State Circuits, 29: 1429
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ASYNCHRONOUS CIRCUITS
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clocked asynchronous state machines, Proc. Int. Conf. Comput.Aided Des. (ICCAD), Los Alamitos: IEEE Computer Society Press,
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34. K. Y. Yun and D. L. Dill, Automatic synthesis of 3-D asynchronous state machines, Proc. Int. Conf. Comput.-Aided Des. (ICCAD), Los Alamitos: IEEE Computer Society Press, 1992, pp.
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35. J. L. Peterson, Petri nets, Computing Surveys, 9: 223252, 1977.
36. T. H.Y. Meng, R. W. Brodersen, and D. G. Messerschmitt, Automatic synthesis of asynchronous circuits from high-level specifications, IEEE Trans. Comput.-Aided Des., 8: 11851205, 1989.
37. J. C. Ebergen, Translating Programs into Delay-Insensitive Circuits, vol. 56 CWI Tract., Amsterdam: Centre for Mathematics
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40. E. Brunvand and R. F. Sproull, Translating concurrent programs
into delay-insensitive circuits. Proc. Int. Conf. Comput.-Aided Des.
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262265.
41. S. Weber, B. Bloom, and G. Brown, Compiling joy to silicon, T.
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VLSI Parallel Syst., Cambridge: MIT Press, 1992, pp. 7998.
42. M. Shams, J. Ebergen, and M. Elmasry, A comparison of CMOS
implementations of an asynchronous circuits primitive: the C-element, Int. Symp. Low Power Electron. Des., Digest of Technical
Papers, New York: ACM Press, 1996, pp. 9396.
43. P. Day and J. V. Woods, Investigation into micropipeline latch
design styles, IEEE Trans. VLSI Syst., 3: 264272, 1995.
44. K. Y. Yun, P. A. Beerel, and J. Arceo, High-performance asynchronous pipeline circuits, Proc. Int. Symp. Advanced Res. Asynchronous Circuits Syst., Los Alamitos: IEEE Computer Society
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45. S. B. Furber and P. Day, Four-phase micropipeline latch control
circuits, IEEE Trans. VLSI Syst., 4: 247253, 1996.
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(eds.), Asynchronous Digital Cricuit Design. Workshops in Computing, Berlin: Springer-Verlag, 1995, pp. 149.
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Proc. IEEE, 83: 6993, 1995.
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49. The Asynchronous Logic Homepage. Uniform Resource Locator
(URL) http://www.cs.man.ac.uk/amulet/async/.

MAITHAM SHAMS
University of Waterloo

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103128, 1992.

JO C. EBERGEN

30. L. A. Hollaar, Direct implementation of asynchronous control

units, IEEE Trans. Comput., C-31: 11331141, 1982.

MOHAMED I. ELMASRY

Sun Microsystems Laboratories

University of Waterloo

ASYNCHRONOUS SEQUENTIAL LOGIC

In sequential logic (see Sequential Circuits), output is a
function of current input and the state stored in the system. In synchronous sequential logic circuits, time is quantized, making all actions and state changes take place at
discrete intervals of time, determined by a regular source
of pulses called a clock. For the other more general class,
called asynchronous sequential circuits (ASCs), timing information is introduced without the use of a global clock;
thus, events in signals and changes in states take place at
any time. The use of ASCs may often bring some advantages when implementing digital control and processing
structures. Such advantages come from the decentralization of the timing control in the operation of the system,
with self-synchronization taking place at a local level.
This article introduces most of the fundamental issues
related to ASCs: comparison with synchronous circuits and
potential advantages of ASCs, major specication and design techniques, different implementation architectures,
and performance characteristics.
An ASC can be simply dened as a sequential circuit
whose internal states change only in response to changes
in its inputs, with no common timing reference (see Ref. 1
for a complete introduction). While the reader can easily
understand how a privileged signalcalled the clockcan
control the change of the state in a synchronous sequential
circuit, the way to ensure correct operation in an ASC is not
so clear. Thus, it is necessary to establish more precisely
the operational procedure of the ASC, establishing suppositions about the delay models of components and interconnections in the system. Negligible, bounded, arbitrary,
or unbounded delay models in gates and interconnections
can be considered.
A simple ASC model is the Huffman circuit (Fig. 1),
which is basically composed of a combinatorial circuit and
a set of feedback lines, with a bounded (or zero) delay model
for interconnections. For a Huffman ASC to work properly
(hazard- and race-free operation), the input signals can
only change once the internal state has been correctly settled (operation under fundamental mode and single-input
change). There are some other operation modes, such as
inputoutput, multiple, or unrestricted input change, with
different constrains. A special operation mode, called burst
mode operation, allows operation in the fundamental mode
but on bursts of inputs rather than single inputs. For additional information, see Reading List.

Figure 1. Huffman Circuit. Delay elements can be explicitly

placed or being simply the delay in feedback lines.

More generally, an ASC is called speed-independent

when it operates correctly (hazard-free) for any nite delay
in gates. A subset of these circuits generates a completion
signal indicating that its operation has nished. For correct behavior, changes in input signals are only allowed
when a completion signal is activated. More restrictive is
the delay-insensitive ASC, which works correctly for any
nite delay in gates and interconnections. An intermediate category is the quasi-delay-insensitive ASC, which is
a delay-insensitive ASC that considers isochronic forks. In
this type of ASC, delay in interconnections is arbitrary except in forks, where the two branches have similar delays.

SELF-TIMED APPROACH
A self-timed circuit, also called a handshake circuit, is
an ASC that is self-synchronized with its environment
through a handshaking protocol (see Ref. 2 for a complete
introduction). The behavior of components and elements in
a self-timed system is conducted by events in their terminal ports: The beginning of the operation of the system is
caused by a specic event in an input signal (request), and
the end of the operation is indicated to the outside by another event in an output signal (acknowledgment). Thus,
the time required to perform the computation or processing
is determined by internal delays of gates and interconnections inside the circuit, corresponding to the time elapsed
between the request and the acknowledgment events. A
precedence relation exists between such events, in that
initiation must take place prior to nishing, indicating a
sequence of events.
A self-timed system can be dened either as (1) a selftimed circuit itself, or (2) a correct connection of self-timed
circuits. Such a correct connection incorporates the restrictions in the communication between such elements, imposed by the handshaking protocol. In a simplied model,
the handshaking protocol is veried by specic signals
called protocol signals. In such signals at least two events
are necessary to describe the self-timed operation (request
and acknowledgment), and these events must alternate.
Figure 2(a) shows a so-called two-phase, or no-return-tozero (NRZ), handshaking protocol characterized by the
events that occur at the edges of protocol signals. Thus,
logic circuits operating under this protocol should be edgetriggered. On the other hand, Fig. 2(b) displays a so-called
four-phase, or return-to-zero (RZ), handshaking protocol,
which is level-sensitive. Systems incorporating such protocols will present different performance: The two-phase protocol is faster and, since it has less transitions, consumes
less power. However, the four-phase protocol is easier to implement because it operates with less-costly level-sensitive
hardware.
Potential advantages in the use of the self-timed approach are based on its higher efciency in computing data,
especially in those cases where processing time is strongly
data-dependent; self-timed ASCs operate on an averagecase basis, while synchronous circuits operate on a worstcase basis.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Asynchronous Sequential Logic

Figure 2. Handshaking protocol: (a) 2-phase or edge-sensitive;

(b) 4-phase or level-sensitive.

GLOBALLY ASYNCHRONOUS LOCALLY

SYNCHRONOUS APPROACH
A promising method between pure synchronous and selftimed circuits is the Globally Asynchronous Locally Synchronous (GALS) approach. Although the background for
this technique was set in 1984 (3), recently has received
a lot of attention because it offers advantages from both
the synchronous and asynchronous domains. In GALS systems, the components are synchronous modules operating
at their own clock speed, which allows the proven synchronous design methodologies to be used. The interface
between the synchronous components is made with selftimed circuitry, generating the local clock signal under a
request-acknowledgement basis. The main advantages in
using the GALS technique are the elimination of problems
related to the usage of a global clock (see next section)
and the possibility of using classical synchronous cores,
methodologies and CAD tools. The main drawback is the
metastability problem when interacting synchronous and
asynchronous signals, being this problem faced with design
solutions (4).
LIMITATIONS OF SYNCHRONOUS CIRCUITS
Most of the problems and limitations of synchronous circuits stem from the existence of a global clock signal. The
main problems are crosstalk noise and, especially, clockskew and synchronization faults.
Clock-Skew Problems
In synchronous circuits, the clock signal must arrive
simultaneously at the memory elements to avoid race
problems. However, generating and distributing highfrequency clocks inside very large-scale (VLSI) integrated
circuits (ICs) is a very difcult and expensive task, so that
eliminating clock skew often limits system performance (5
7). Clock skew appears because the clock paths suffer different delays, causing synchronization failures in the sys-

tem. The nature of clock skew is unpredictable for two main

reasons: rst, at a logic level, the designer cannot prevent
the placement of memory elements in the layout, and second, the variations in the delays depend on various factors,
such as operation temperature and technological process
deviations. Thus, the designer cannot ensure clock-skewfree operation.
Figure 3 shows an example of the pernicious effects of
clock skew. The correct operation requires that the rst
bistable store its input datum D1 , while the second bistable
stores Q1 . However, if the delay in the clock signal is greater
than the delay in the datum line (
2 >
1 + propagation
delay of rst bistable), D1 may be stored instead in the
second bistable, so that the Q1 value is lost.
This problem is nowadays aggravated because, with current technologies, delays in interconnection paths are becoming comparable to delays in gates. Classical solutions
to this problem, such as (1) routing of clock signals in the
opposite direction to data ow and (2) use of nonoverlapping clocks, limit the overall performance of the system.
The most effective solutions, such as identical buffering in
each clock path or routing clock signals through H-tree networks, are much more expensive in design time and cost
(57). Parameters that should be taken into account in generating and distributing clock signals are routing layers,
clock network shape, clock generators, rise and fall times,
and capacitive and resistive load in lines.
Synchronization Problems
Synchronization problems can have various causes, but
the primary cause is metastable operation in bistables.
The probability of failure increases with the complexity
and operation speed of the system. In synchronous operation, some timing restrictions in bistables, concerning
hold time, setup time, and pulse width, must be observed.
Due to asynchronous interactionsa delay between data
and clock signals, for instancethat cause a violation in
such restrictions, a bistable may enter its metastable state,
showing in its output an undetermined logic state for an
indenite time. If such output acts as the input of two parallel bistables, these may read different logic values upon
the arrival of the next clock edge. In such a case, a system
error occurs as a consequence of a synchronization fault.
In view of these problems, it is of interest to consider the
design of ASCs, which provide solutions in that (1) ASCs do
not need a global clock to synchronize the operation of the
circuit, and (2) the handshaking protocol imposes restrictions on changes in the inputs of the memory elements.
DESCRIPTION AND REPRESENTATION TECHNIQUES
OF ASYNCHRONOUS SEQUENTIAL CIRCUITS
Flow diagram and tables are the classic ways of describing
ASC (1). States are stored in the feedback loops or in asynchronous latches. Correct operation is ensured with the assumption of operation in the fundamental mode and with
single-input change. Once the ow table has been generated or obtained, minimization and assignment processes
generate an asynchronous implementation, which should
be race- and hazard-free.

Asynchronous Sequential Logic

Figure 3. Illustrative example of negative effects of clock skew. Datum in Q1

can be lost if delay in clock line is higher
than delay in datum line plus propagation delay in rst bistable.

Figure 4. State table (a) and STG (b) corresponding to an

asynchronous pipeline interface (c), working under a 4-phase
handshaking protocol, and implemented with two two-input Celements (d).

The characteristic of ASCs by which changes in inputs

directly bring about changes in states and outputs makes
graph-based descriptions suitable. Such representations
easily describe precedence relations between events in signals and allow for parallelism, decisions, and conict between processes as well. An important, but not unique,
graph-based description is the signal transition graph
(STG), an interpreted Petri net. Basically, STGs are formed
by placessignal transitions, labeled + for rise transitions
andfor fall transitionsand by arcs connecting places. If
the STG satises some criteria of good behavior (liveness,
safety, persistence, semimodularity, etc.), it may represent
a hazard-free ASC (5). Other techniques based on Petri nets
are change diagrams and I nets.
Figure 4 shows the table- and graph-based description
and a possible implementation of a pipeline interface operating under a four-phase handshaking protocol. Rin performs a request from block A, acknowledged by Aout and
transmitted to block B through the Rout signal, depending
on the value of Ain , which indicates if B is ready to accept
data. All signals are considered active high.
Starting from an initial state (Rout Aout = 0 0) with no request stored, activation of a request (R+
in ) leads the system

to the state (Rout Aout = 0 1), indicating that the request

has been acknowledged and considered. Only when Ain is
disabled (A
in ), indicating that the following cell is idle, does
the system go to the state (Rout Aout = 11), transferring the
request from the present to the next stage. Disabling the
input request (R
in ) forces the falling of the acknowledge
signal (A
),
leading
the system to the state (Rout Aout =
out
10), from which the system is returned to the initial state
by disabling Ain .
The proposed race-free implementation uses as a memory cell a C-Muller element: a bistable that stores its input
values when they are coincident. The characteristics of this
bistable (i.e., the fact that it performs the AND operation
on events) make it the recommended memory element for
self-timed implementations, as suggested by Meng (8) and
Martin (9).
Peculiarities of ASCs exclude classic synthesis tools
used for synchronous sequential circuits. Different
methodologies have been presented, which are focused on
graph- and state-based descriptions. Also, VLSI programming and sintax-driven translation has recently received
attention (911).
Synthesis tools using state representation (ow diagrams and tables) are oriented toward the implementation of race-free tables by using techniques of state minimization and efcient assignment. For instance, so-called
single-transition table (STT) state assignments provide
race-free VLSI circuits (see Reading List).
Synthesis tools using graph representations (STG or
Petri nets) utilize as input an original graph that contains
the desired behavior. This graph is transformed by using
different techniques in such a way that the transformed
graph veries some properties of good behavior, such as
liveness, safety, or semimodularity. Some algorithms generate a state diagram and a hazard-free circuit is synthesized. The transformation of the original graph into the
modied one takes place but adding arcs (causal relations)
and signals in such a way that the transformed graph veries the above-mentioned properties, and the resulting circuit is hazard-free (see Reading List).
VLSI programming allows the description of typical
asynchronous VLSI processes such as concurrence and parallelism between processes. Synthesis tools based on VLSI
programming, as for instance TANGRAM (10), BALSA
(11) or the one used in (9), directly translate a high-level
description into hardware through connections between
handshake signals and circuits.

Asynchronous Sequential Logic

ARCHITECTURES OF ASYNCHRONOUS SEQUENTIAL

CIRCUITS
The main parameter that characterizes the architecture
of ASCs is the way that the self-synchronization is performed. In self-timed ASCs, the timing control is carried
out by data themselves, assisted by specic protocol
handshakesignals. The way that this information is included depends on the data encoding and on the relationship between data and handshake signals. There are
two main data signaling schemes used in self-timed ASCs:
dual- and single-rail codication.
Dual-Rail Codication
Using dual-rail code, also called self-synchronizing or
delay-insensitive code, allows the inclusion of information
about the validity of data by including redundancy of information. A simple code uses two signal bits (xt and xf )
per data bit (x). Thus, we can express four possible values:
when both xt and xf are inactive (low level, for instance),
an empty or spacer state is dened, indicating that data
are not valid. When either xt or xf is active (high level, for
instance), the data are valid (true or false, respectively).
By denition, xt and xf cannot be simultaneously active.
Figure 5 presents a waveform diagram showing the synchronization scheme using dual-rail data, working with a
four-phase handshaking protocol. Only one transition per
bit takes place per operation cycle, while valid data and
spacers are forced to alternate. Delay-insensitive operation
may be ensured, since delay in interconnections would only
bring about additional delays in transitions, but events occur in the right sequence.
Single-Rail Codication
This approach, also called bundled data, uses a specic
handshake signal to validate data, in such a way that only
one signal per data bit is needed. However, synchronization
between the validation signal and data signal is required
to ensure correct operation; thus, delay-insensitive operation is not guaranteed. To validate the output data of an
ASC, it is necessary to generate a completion signal once
the operation of the circuit is nished. This completion signal can be used as a request signal for other ASCs. The
two most widely accepted mechanisms for generating completion signals are based on the use of matched delays and
the use of differential circuits as computation or processing
elements.
Matched Delays. This technique (2, 12) generates a completion signal by using a delay element that matches the
worst-case delay of the combinational logic (Fig. 6). When
the request is activated, input data are valid. Since the
combinational logic takes less time to process data than
the propagation time of the delay element, once the completion signal is activated, the output data are necessarily
valid. This scheme has the advantage of simplicity, but its
operation is always performed considering the worst-case
delay. Furthermore, the correct calculation of propagation
delays and implementation of delay elements requires exhaustive timing simulations (see Delay circuits).

Differential Circuits. Using differential circuits as

computation or processing blocks provides an efcient way of generating completion signals (8). These
circuits, which are well suited for complementary
metaloxidesemiconductor (CMOS) implementations,
generate both the true and the complemented outputs.
However, dual-coded inputs are needed. Conversion of
single-rail to dual-rail data can be performed at a local
level. The generic schematic and waveform diagrams are
shown in Fig. 7. In the precharge phase, outputs take the
same value, while in the evaluation phase, the logic function is performed and the two outputs take complemented
values. A simple logic gate detecting the complemented
values can generate the completion signal. The main
advantage is the adaptability to new operation conditions,
but at the cost of expensive hardware resources.
Figure 8 shows an example of bundled-data architecture using differential circuits to generate completion signals. Synchronous memory elements (D ip-ops) are locally clocked by protocol signals (not shown in the gure)
in such a way that data must be stored and stable while
they are being processed. Single- to dual-rail data conversion takes place in the memory elements. Interconnection
circuits are implemented with two C elements, as we can
see in the ASC shown in Fig. 4. The Rout signal acts as a
request signal for the differential circuit, while the completion signal is the Rin signal for the following interconnection circuit.
MACROMODULE-BASED CIRCUITS
Most current handshake circuits combine some of the
above-mentioned characteristics: two- or four-phase handshaking protocol, matched delays or differential circuits,
and single-rail or dual-rail codication. A common characteristic is their modularity, in the sense that we can interconnect several modules that work under the same handshaking protocol and codication schemes to build a complex self-timed ASC. Thus, an efcient approach to the development of handshake circuits is the use of a library of
macromodules that, correctly interconnected, can perform
any desired functionality.
With respect to interconnections between macromodules, although they can be used to design delay-insensitive
control modules, their implementation is not delayinsensitive or even speed-independent.
Micropipelines
A very important macromodule-based approach, called micropipelines, was presented by Sutherland (12). It uses a
two-phase handshaking protocol, single-rail codication,
and matched delays, and its basic architecture is shown in
Fig. 9. For the data path, it uses data passcapture latches
to store data in events of protocol signals. For control, it
uses a library of event-sensitive macromodules, shown in
Fig. 10. The XOR gate and the C element perform the OR
and AND operation of events, respectively. The toggle cell
transfers an event from its input to its two outputs alternately, starting with the dotted output. The select block
allows a Boolean to direct the input event to the true or

Asynchronous Sequential Logic

Figure 5. Speed-independent buffer as example of a dual-rail

scheme for data signaling. A 4-phase handshaking protocol has
been used. Empty (E) and Valid Data values are forced to alternate.

Figure 6. Bundled-data scheme using matched delays to generate complete signal.
1 (
2 ) matches the worst case delay of
C1 (C2 ). Data signals must be validated by handshake signals.

Figure 7. (a) Logic schematic of a generic differential logic block.

LOAD block sets the precharge values and the differential tree
generates both the true and the complemented logic output. (b)
Waveform diagram showing how precharge and evaluation phases
alternate.

false output. The call block allows two independent, mutually exclusive processes to share a common subprocess.
The arbiter cell grants a common resource to only one of
the elements that requested it. The mutually exclusive element (MUTEX) ensures that the resource can never be
used simultaneously by the two elements that requested
it.

Control and Data Handshake Circuits

One of the main approaches to the design of ASCs uses
VLSI programming for direct translation of high-level descriptions into hardware (911). Control and data handshake circuits are the result of compiling the behavior description. A handshake circuit is a (quasi) delayinsensitive network of components connected by communication channels. A control handshake circuit communicates with other components through request/acknowledge
signaling through the channels. Data handshake circuits
also include data signaling. Following heuristic or systematic techniques, you can design more complex components
based on simple handshake circuits.

As an example of an ASC built with handshake circuits

(taken from Ref. 10), Fig. 11 shows the high-level description, symbol, and handshake-based implementation of oneand two-stage rst-in, rst-out (FIFO) memories. There is
a direct translation from language (forever do) into a handshake circuit (repeater block, marked with ; and with
a possible implementation is shown in Fig. 12). Blocks
marked ; are sequencers, which complete handshaking
from the ASCs input to its outputs alternatively. The T
and x blocks, called transferrers and handshake latches, respectively, are data handshake blocks, capable of transferring and storing data signals according to the handshake
protocol. An open circle a block indicates that the request
acts as input and the acknowledge as output (passive port),
while a lled circle indicates an output request and input
acknowledge (active port).
For the one-stage FIFO in Fig. 11 (see Fig. 4 for the
same basic functionality), the statement (a?x0; b!x1) indicates that input a is loaded in variable x, which can be read
through the b port. The action of the sequencer makes it
possible for data to be written before being read, verifying the handshaking protocol. The two-stage FIFO is built

Asynchronous Sequential Logic

Figure 8. Example of bundled-data architecture using differential circuits as computation blocks.

The generation of complete signals is quite straightforward by using a logic gate. A 4-phase handshaking protocol is used.

Figure 9. Micropipelined single-rail data architecture. The data path is implemented with combinatory logic to perform the logic function and PassCapture latches to store data. Control manages
protocol signals and write/read operation in latches. Matched delays are used for completing handshaking protocol (see reference 12 for more complex examples).

with two cascaded one-stage FIFOs operating in parallel; it

is marked with the symbol  in the specication (Fig. 11).
The nal circuit can be synthesized by substituting each
handshake component for its schematic and layout.

DISCUSSION OF CHARACTERISTICS AND

PERFORMANCES
Current state-of-the art ASCs are more complex and, in
general, more difcult to design than their synchronous
counterparts. Many advantages of ASCs over synchronous
circuits have been claimed, such as automatic adaptation to physical properties, better accommodation to asynchronous external inputs, better technology migration po-

tential, more timing reliability, lower noise and electromagnetic emission, and higher modularity. However, the
most prominent advantages of ASCs come from their special ability to exploit data dependence in operation time
and their lower power consumption. Thus, there are some
applications where ASCs can be recommended, such as digital signal processing and low-power applications. Some
emergent applications are in the eld of thermally-aware
circuits, secure systems as smart cards, and the implementation of bio-inspired articial vision systems, based on
the asynchronous address-event-representation communication scheme. Advanced aspects, such as testability or verication, are still under development.

Asynchronous Sequential Logic

Figure 10. Event-sensitive macromodule library and a possible CMOS implementation of each cell.

Figure 11. High-level description, symbol and module implementation of 1-stage and 2-stage FIFO memories.

To show the data dependence, let us consider (Fig. 13)

a ripple carry adder (see Summing circuits), where the
time needed to perform the operation depends on the input
words (2). The best cases correspond to direct generation of
output carry of all cell bits, and this occurs when the added

bits have the same value (ai , bi , ci1 ) = (1, 1, x) or (0, 0, x),
giving as output carry 1 and 0, respectively, regardless of
the value of the input carry. The worst case is given by the
propagation of carry throughout the whole chain, whereby
each cell needs the output carry of the previous cell to n-

Asynchronous Sequential Logic

Figure 12. A possible implementation of a Repeater block. Its

functionality is summarized as follows: a requests b (ar+ ); b is indefinitely executed (br+ bk+ br bk ); a is released (ak+ ). A 4-phase
handshaking protocol is supposed.

Figure 13. Ripple carry adder as an example (taken from reference 2) showing the dependence of processing time with input
data. The operation performed by each full adder is ci = ai bi + ai
ci1 + bi ci1 ; si = ai xor bi xor ci1 . If an bn = 1 1, then cn = 1; if an
bn = 0 1, then cn = an1 bn1 + an1 cn1 + bn1 cn1 , depending
recursively on the previous carry.

ish its processing. An input vector such as (ai , bi , ci1 ) = (1,

0, x) will create such a situation. This example shows how
the data themselves lead to very different time processing. While synchronous circuits must take into account the
worst-case operation, ASC can operate on the average case.

Figure 14. Representation of the power consumption vs operations performed. In the synchronous case, there is power consumption even if there are no data to compute. In a self-timed ASC, for
relatively low input data rate, consumption is lower.

occur in areas involved in the current computation. Moreover, problems related to the generation of clocks are minimized. Figure 14 shows a generic representation of power
consumption versus operations performed. Because a clock
consumes power when the circuit is idle, depending on the
input data rate, the ASC consumes less power. A good example of an ASC exhibiting less power consumption than
its synchronous counterpart is found in Ref. 13.
There are some interesting approaches combining the
advantages of the synchronous and the asynchronous style.
These structures are locally clocked and are based on the
generation of a local clock that ensures correct operation
of the circuit under asynchronous inputs. The most important are those based on burst-mode operation, metastableinsensitive Q-modules, and stoppable clocks (10).

BIBLIOGRAPHY
Operation Speed
At a circuit level, ASCs show more tolerance for physical
variations, such as deviation in the technological process
and variations in supply voltage and temperature. This is
mainly due to the action of the handshake and the generation of completion signals (indicating when the operation has been nished) and to their working at the maximum speed possible. At an algorithmic or architectural
level, ASCs ability to operate on an average case is helpful, especially when the worst and average cases are very
different; and they are not limited by the slowest processing block (2, 8). However, verication of the handshaking
protocol requires two processes: (1) monitoring the state,
and (2) wait or go operation. Thus a tradeoff exists between the two approaches.
Power Consumption
In synchronous circuits, clock lines have to be toggled and
circuit nodes charged and discharged even in unused parts
or when the circuit is idle and there are no data to compute.
Also, the generation of good clock signals (vertical edges)
consumes a lot of power in each transition. Although ASCs
often require more signal transitions in a given computation than do synchronous circuits, these transitions usually

1. S. H. Unger, Asynchronous Sequential Switching Circuits.,

New York: Wiley-Interscience, 1969.
2. C. L. Seitz, System timing, inC. A. Mead andL. Conway (eds.),
Introduction to VLSI Systems. Reading, MA: Addison-Wesley
Pubs., 1980.
3. D. M. Chapiro, Globally-asynchronous locally-synchronous,
PhD thesis, Stanford University, 1984.
4. D. Sokolov and A. Yakovlev, Clockless Circuits and System
Synthesis, IEE Proc. Computers and Digital Techniques, 152
(3): 298316, 2005.
5. H. B. Bakoglu, Circuits, Interconnections and Packaging for
VLSI. Reading, MA: Addison-Wesley Pubs., 1990.
6. J. M. Rabaey, Digital Integrated Circuits. A Design Perspective.
Englewood Cliffs, NJ: Prentice-Hall, 1996.
7. E. G.Friedman, Clock Distribution Networks in Synchronous
Digital Integrated Circuits, Proceedings of the IEEE, 89 (5):
665692, 2001.
8. T. H. Y. Meng, Synchronization Design for Digital Systems.
Norwell, MA: Kluwer Academic Pubs., 1991.
9. A. J. Martin, Compiling communicating processes into delayinsensitive VLSI circuits. Distributed Computing, 1 (4):
226234, 1986.
10. K. van Berkel, Handshake Circuits: an Asynchronous Architecture for VLSI Programming. Cambridge University Press,
1993.

Asynchronous Sequential Logic

11. A.
Bardsley,The
BALSA
Asynchronous
Synthesis
Systems
web
pages:
http://www.cs.manchester.ac.uk/apt/projects/tools/balsa/
12. I. E. Sutherland, Micropipelines. Commun. of the ACM, 32 (6):
720738, 1989.
13. K. van Berkel, R. Burgess, J. Kessels, M. Roncken, F. Schalij,
and A. Peeters, Asynchronous circuits for a low power: A DCC
error corrector. IEEE Design and Test of Computers, 11 (2):
2232, 1994.

Reading List
Most classical textbooks dedicated to digital logic design discuss
asynchronous sequential logic. A summary of them is as follows:

A. E. A. Almaini, Electronic Logic Systems. Englewood Cliffs, NJ:

Prentice-Hall, 1994, chap. 5.
E. J. McCluskey, Logic Design Principles. Englewood Cliffs, NJ:
Prentice-Hall, 1986, chap. 9.
F. J. Hill and G. R. Peterson, Computer Aided Logical Design with
Emphasis on VLSI. New York: John Wiley & Sons, 1993, chap.
14.
R. F. Tinder, Digital Engineering Design: A Modern Approach. Englewood Cliffs, NJ: Prentice-Hall 1991, chap. 6.
S. H. Unger, The Essence of Logic Circuits. 2nd ed., Piscataway,
NJ: IEEE Press, 1997, chap. 6.

ANTONIO J. ACOSTA-JIMENEZ

MANUEL J. BELLIDO-DIAZ
ANGEL BARRIGA-BARROS

University of Seville, Seville,

Spain

ATTENUATORS
Attenuators allow a known source of power to be reduced
by a predetermined factor usually expressed as decibels.
Attenuators are linear, passive or active networks or devices that attenuate electrical or microwave signals, such
as voltages or currents, and hence power in a system by
a predetermined ratio. The most commonly used method
in attenuators is placing resistors at the center of an electric eld, which induces a current resulting in ohmic loss. A
great advantage of attenuators is that since it is made from
non-inductive resistors, they are able to change a source or
load, which might be reactive, into one which is precisely
known and resistive. This power reduction is achieved by
the attenuator without introducing distortion. Attenuators
are used in a wide variety of applications and can satisfy almost any requirement where a reduction in power is
needed. Attenuators are used to extend the dynamic range
of devices such as power meters and ampliers, reduce signal levels to detectors, match circuits and are used daily in
lab applications to aid in product design. Attenuators are
also used to balance out transmission lines that otherwise
would have unequal signal levels. Attenuation is usually
expressed as the ratio of input power (Pin ) to output power
(Pout ), in decibels (dB), as

Figure 1 illustrates this concept. The relation between

Np and dB is,

Here the load and source are matched to the characteristic

impedance. The decibels are converted to the attenuation
ratio as follows: Pin /Pout = log1 10 dB/10 or Vin /Vout = log1 10
dB/20.
APPLICATION
There are many instances when it is necessary to reduce
the value or level of electrical or microwave signals, such
as voltages and currents by a xed or variable amount to
allow for the rest of the system to work properly. Attenuators are used for this purpose. For example, in turning
down the volume on a radio, stereo CD player or IPod, we
make use of a variable attenuator to reduce the signal. Almost all electronic instruments use attenuators to allow
for the measurement of a wide range of voltage and current values, such as voltmeters, oscilloscopes, and other
electronic instruments. Thus, the various applications in
which attenuators are used include the following:

To reduce signal levels to prevent overloading

To match source and load impedances to reduce their
interaction

This is derived from the standard denition of attenuation

in Nepers (Np), as

where is attenuation constant, Np/m, and x is the distance between the voltages of interest, E1 and E2 .

To measure loss or gain of two-port devices

To provide isolation between circuit components, or
circuits or instruments so as to reduce interaction
among them

To extend the dynamic range of equipment and prevent burn-out or overloading equipment
TYPES
There are various types of attenuators based on the nature
of circuit elements used, type of conguration, and kind of
adjustment. They are as follows:

Passive and active attenuators

Absorptive and reective attenuators

Fixed and variable attenuators
Figure 1a

Concept and denition of attenuation.

Figure 1b Alternative representation.

A xed attenuator is used when the attenuation is constant. Variable attenuators have varying attenuation, using varying resistances for instance. The variability can be
in steps or continuous, obtained either manually or programmably. There are also electronically variable attenuators. They are reversible, except in special cases, such as
a high-power attenuator. They are linear, resistive, or reactive, and are normally symmetrical in impedance. They
include waveguide, coaxial, and strip lines, as well as calibrated and uncalibrated versions. Figures 2, 3, and 4 show
xed, manual step, and continuously variable commercial
attenuators.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Attenuators

HP 84904L programmable step attenuator, direct current (dc) to 40 GHz, 0 dB to 11 dB, 1 dB steps
HP 84906K programmable step attenuator, dc to 26.5
GHz, 0 dB to 90 dB, 10 dB steps
HP 84904L programmable step attenuator, dc to 40
GHz, 0 dB to 70 dB, 10 dB steps
HP 8495B manual step attenuator, dc to 18 GHz, 0 dB
to 70 dB, 10 dB steps
HP 355F programmable step attenuator, dc to 1 GHz, 0
dB to 120 dB, 10 dB steps
HP 8493A Coaxial xed attenuator, dc to 12.4 GHz

Figure 2. Fixed coaxial attenuator. (Courtesy of Weinschel

Associates.)

Based on their utility, military attenuators are classied

as:
Class I
Class II

Class III
Class VI

For use as a primary standard

For use as a secondary standard, and in
lab and precision test equipment
Awith lumped-constant or distributed shunt and series elements
Bwith lossy-line pads
For use in general eld equipment
For use in equipment where precision
and stability are secondary considerations

Typical mil specications for xed coaxial attenuators

are as follows:

Figure 3. Manual step attenuator. (Courtesy of Weinschel

Associates.)

Mil-A-3933/1: Attenuators, xed, coaxial line, dc to 3

GHz, class IIA, low power
Mil-A-3933/2: Attenuators, xed, coaxial line, 1 GHz to
4 GHz, class IIB, medium power
Mil-A-3933/10: Attenuators, xed, coaxial line, dc to 18
GHz, class III, medium power
Mil-A-3933/26: Attenuators, xed, coaxial line, 0.4 GHz
to 18 GHz, class IV low power
SPECIFICATIONS

Figure 4. Continuously variable attenuator. (Courtesy of Weinschel Associates.)

Based on their usage, IEEE Std 474 classies them as

Class I
Class II
Class III
Class VI

Standard
Precision
General purpose
Utility

Typical commercial attenuators are listed below:

WA 1 (0 GHz to 12.4 GHz), WA 2 (0 GHz to 3 GHz),
coaxial, xed attenuators: 1 dB to 60 dB; 5 W av./1
kW PK
WA 115A manual step attenuators: 0 GHz to 18 GHz, 0
dB to 9 dB, 1 dB steps
VA/02/100 continuously variable attenuators, resistive,
0 GHz to 2 GHz, 5 W av./0.5 kW PK

To specify an attenuator, the purpose of the attenuator

should be known. Attenuators are used to provide protection, reduce power, and extend the dynamic range of the
test equipment. In choosing an attenuator, the frequency
range of operation should be considered since the accuracy
depends on the frequency. Attenuation involves placing resistive material to absorb the signals electric eld. This
means, there will always be some reection. So, attenuators must be designed to minimize reection. This is quantied in terms of voltage standing wave ratio (VSWR). Another factor to be considered is the insertion loss, which is
the ratio of power levels with and without the component
insertion. If it is a variable step attenuator, the step size is
to be known. Thus, the parameters available in the specs
are as follows:
dB rating
VSWR
Accuracy
Power rating

Attenuators

Step size (if variable)

Frequency band
Degree of stability (measured by the change in attenuation due to temperature, humidity, frequency, and
power level variations)
Characteristic impedance of attenuator
Repeatability
Life
Degree of resolution (difference between actual attenuation and measured value)
The denitions of various parameters used in selecting attenuators are given below.
Electrical Parameters and Denitions (From
MIL-HDBK-216)
Attenuation A general transmission term used to indicate a decrease in signal magnitude. This decrease
in power is commonly expressed in decibels (dB) as:

Deviation of Attenuation from Normal Difference in actual attenuation from the nominal value at 23 C and
an input power of 10 mW at a specied reference frequency or frequency range. When used in a frequency
range, it involves the frequency sensitivity.
Frequency Sensitivity This is the peak-to-peak variation in the loss of the attenuator through the specied frequency range.
Frequency Range Range of frequency over which the
accuracy of attenuator is specied.
Insertion Loss Amount of power loss due to the insertion
of the attenuator in the transmission system. It is
expressed as a ratio of the power delivered to that
part of the system following the attenuator, before
and after the insertion.

Characteristic Insertion Loss This is the insertion loss

in a transmission line or waveguide that is reectionless in both directions from the inserted attenuator.
Power-Handling Capabilities Maximum power that can
be applied to the attenuator under specied conditions and durations without producing a permanent
change in the performance characteristics that would
be outside of specication limits.
Power Sensitivity This is the temporary variation in
attenuation (dB/W) under steady-state conditions
when the input power is varied from 10 mW to maximum input power.
Stability of Attenuation Capability of attenuator to retain its parameters when subjected to various environmental conditions.
Operating Temperature Range Temperature range the
attenuator can be operated with maximum input
power.
Temperature Sensitivity Temperature variation in attenuation [dB/(dB C)] over the operating range.
Input VSWR This is the level of reected signal created at the attenuator input when the output is terminated with a load with the same characteristic
impedance as the source.
Output VSWR This is the level of reected signal created at the attenuator output when the input is terminated with a load with the same characteristic
impedance as the source.
PASSIVE ATTENUATORS
Resistance Networks for Attenuators
Typically T, Pi, or L designs are used for attenuators.
Figure 5 shows four commonly used symmetrical (input
and output resistors of equal value) congurations. The
formulas for the resistance values in ohms for these pads
when the characteristic resistance R0 = 1  are given below. If R0 is other than 1 , multiply each of the resistance

Figure 5. Symmetrical pads with matched impedances. (a) T pad. (b) Pi pad. (c) Bridged T pad. (d) Balanced pad.

Attenuators

Figure 6. Unsymmetrical matching L attenuator.

values (a, b, c, 1/a, 1/b, and 1/c) by R0 , where

Simple wirewound resistors are used in audio applications. Nonreactive wirewound resistors, such as mica card,
Aryton-Perry winding, woven resistors are used for high
frequencies. For coaxial applications (over 26.5 GHz), thinlm resistors are used. For higher frequencies, distributive
resistive lms, such as nichrome alloy lm, on a high quality ceramic substrate, such as alumina or sapphire, is used.
An unsymmetrical pad is shown in Figure 6, and the formulas for this pad are

Typical values for the pads in Figure 5 are shown in

Table 1, and those of Figure 6 are shown in Table 2.
For a broad-band match between impedances R1 and R2 ,
use the minimum loss L pad (Figure 6).

Figure 7. Denition of characteristic insertion loss. (a) Original

setup without attenuator. (b) Original setup with attenuator between source and load.

Figure 8. T attenuator conguration.

Power Dissipation within a T Pad

Table 3 lists values of power dissipation within a T pad.
The values are for an input of 1 W; for other input powers,
multiply the values by the input power.
INSERTION LOSS
An attenuator is used to introduce attenuation between a
source and a load. Due to the introduction of the attenuator, there is change in the current. This loss is designated
as insertion loss, which depends on the conguration. Usually, the load and source impedances are matched. Figure
7 illustrates this concept. If IL0 is the load current without
the attenuator pad, and IL is the current with the attenuator pad, then the ratio IL /IL0 is called the insertion loss,
one of the parameters of the attenuates. Figure 7(a) shows
the source and load connected without an attenuator, and
Figure 7(b) shows the same system with an attenuator.
(The quantities, IL , Rin , and Rout depend on the attenuator
conguration.) The quantities insertion loss (IL ), input resistance (Rin ), and output resistance (Rout ) depend on the

Figure 9. Pi attenuator conguration.

attenuator conguration. The value of each of the three resistors of the T (Figure 8) and Pi (Figure 9) attenuators can
be chosen independently of others. This enables the threedesign criteria of input resistance, output resistance, and
insertion loss to be met. In many situations, the only function of the pad is to provide matching between source and
load; and although attenuation will be introduced, this may
not be a critical design parameter. This allows a simpler
type of pad to be designed, requiring only two resistors; it
is known as an L pad.

Attenuators

Table 1. Resistance Values for Attenuator Pads When R0 = 1 a

dBb

1/b

1/a

1/c

0.100
0.006
86.853
0.012
173.710
0.012
86.356
0.200
0.012
43.424
0.023
86.859
0.023
42.930
0.300
0.017
28.947
0.034
57.910
0.035
28.455
0.400
0.023
21.707
0.046
43.438
0.047
21.219
0.500
0.029
17.362
0.058
34.753
0.059
16.877
0.600
0.034
14.465
0.069
28.965
0.072
13.982
0.700
0.040
12.395
0.081
24.830
0.084
11.915
0.800
0.046
10.842
0.092
21.730
0.096
10.365
0.900
0.052
9.634
0.104
19.319
0.109
9.160
1.000
0.057
8.667
0.115
17.391
0.122
8.195
2.000
0.115
4.305
0.232
8.724
0.259
3.862
3.000
0.171
2.838
0.352
5.848
0.412
2.424
4.000
0.226
2.097
0.477
4.419
0.584
1.710
5.000
0.280
1.645
0.608
3.570
0.778
1.285
6.000
0.332
1.339
0.747
3.010
0.995
1.005
7.000
0.382
1.116
0.896
2.614
1.239
0.807
8.000
0.430
0.946
1.057
2.323
1.512
0.661
9.000
0.476
0.812
1.232
2.100
1.818
0.550
10.000
0.519
70.273c
1.423
1.925
2.162
46.248c
c
4.950
1.222
9.000
11.111c
20.000
0.818
20.202
15.796
1.065
30.623
3265.500c
30.000
0.939
6330.900c
40.000
0.980
2000.200c
49.995
1.020
99.000
1010.100c
158.110
1.006
315.230
317.230c
50.000
0.994
632.460c
500.000
1.002
999.000
100.100c
60.000
0.998
200.000c
70.000
0.999
63.246c
1581.100
1.006
3161.300
31.633c
5000.000
1.000
9999.000
10.001c
80.000
1.000
20.000c
15.811
1.000
31.622
3.163c
90.000
1.000
6.3246c
50.000
1.000
99.999
1.000c
100.000
1.000
2.000c
a If R = 1 , multiply all values by R . (From Ref. data for Radio Engineers, 1985.)
0
0
b For other decibel values, use formulas in text.
c These values have been multiplied by 103 .

1/a

0.006
0.012
0.017
0.023
0.029
0.034
0.040
0.046
0.052
0.058
0.115
0.171
0.226
0.280
0.332
0.382
0.430
0.476
0.519
0.818
0.939
0.980
0.994
0.998
0.999
1.000
1.000
1.000

173.710
86.859
57.910
43.438
34.753
28.965
24.830
21.730
19.319
17.391
8.724
5.848
4.419
3.570
3.010
2.614
2.323
2.100
1.925
1.222
1.065
1.020
1.006
1.002
1.001
1.000
1.000
1.000

Table 2. Resistance Values and Attenuation for L Pada

R1 /R2

dB

20.00
19.49
1.03
18.92
16.00
15.49
1.03
17.92
12.00
11.49
1.04
16.63
10.00
9.49
1.05
15.79
8.00
7.48
1.07
14.77
6.00
5.48
1.10
13.42
5.00
4.47
1.12
12.54
4.00
3.47
1.16
11.44
3.00
2.45
1.22
9.96
2.40
1.83
1.31
8.73
2.00
1.41
1.41
7.66
1.60
0.98
1.63
6.19
1.20
0.49
2.45
3.77
1.00
0.00

0.00
a For R = 1  and R > R . If R = 1 , multiply values by R . For ratios not in the table, use the formulas in the text. (From Ref. data for
2
1
2
2
2
Radio Engineers, 1985.)
Examples of use of table:
If R1 = 50  and R2 = 25 , then R1 /R2 = 2.0, and j = k = 1.414 25  = 35.35 .
If R1 /R2 = 1.0, minimum loss = 0 dB.
For R1 /R2 = 2.0, the insertion loss with the use of j and k for matching is 7.66 dB above that for R1 /R2 = 0

Attenuators

Table 3. Power Dissipation in T Pada

dB

Watts, Input Series Resistor

Watts, Shunt Resistor

Watts, Output Series Resistor

0.100
0.006
0.011
0.006
0.300
0.017
0.033
0.016
0.500
0.029
0.954
0.025
0.700
0.040
0.074
0.034
0.900
0.052
0.093
0.042
1.00
0.058
0.102
0.046
1.200
0.069
0.120
0.052
1.400
0.080
0.114
0.058
1.600
0.092
0.152
0.064
1.800
0.103
0.167
0.068
2.000
0.114
0.181
0.072
2.200
0.126
0.195
0.076
2.400
0.137
0.208
0.079
2.600
0.149
0.220
0.082
2.800
0.160
0.232
0.084
3.000
0.171
0.242
0.086
3.200
0.182
0.252
0.087
3.400
0.193
0.260
0.088
3.600
0.204
0.270
0.089
3.800
0.215
0.278
0.090
4.000
0.226
0.285
0.090
5.000
0.280
0.314
0.088
6.000
0.332
0.332
0.083
7.000
0.382
0.341
0.076
8.000
0.430
0.343
0.068
9.000
0.476
0.338
0.060
10.000
0.519
0.328
0.052
12.000
0.598
0.300
0.038
14.000
0.667
0.266
0.027
16.000
0.726
0.230
0.018
18.000
0.776
0.200
0.012
20.000
0.818
0.163
0.010
30.000
0.938
0.059
0.001
40.000
0.980
0.020
0.000
a For 1 W input and matched termination. If input = 1 W, multiply values by P . (From Ref. data for Radio Engineers, 1985.)
in

Table 4. Resistors R1 and R2 values for various Attenuators (assuming Z0 = 50 )

dB

Tee
R1

R2

Pi
R1

0
1
2
3
5
7
8
10
15
20
30
40
50
100

0.0
2.9
5.7
8.5
14.0
19.1
21.5
26.0
34.9
40.9
46.9
49.0
49.7
50.0

open
433.3
215.2
141.9
82.2
55.8
47.3
35.1
18.4
10.1
3.2
1.0
0.3
0.0

open
869.5
436.2
292.4
178.5
130.7
116.1
96.2
71.6
61.1
53.3
51.0
50.3
50.0

R2
0.0
5.8
11.6
17.6
30.4
44.8
52.8
71.2
136.1
247.5
789.8
2499.8
7905.6
open

Bridged Tee
R1

R2

Reection
R1

R2

0.0
6.1
12.9
20.6
38.9
61.9
75.6
108.1
231.2
450.0
1531.1
4950.0
15761.4
open

open
409.8
193.1
121.2
64.2
40.4
33.1
23.1
10.8
5.6
1.6
0.5
0.2
0.0

0.0
2.9
5.7
8.5
14.0
19.1
21.5
26.0
34.9
40.9
46.9
49.0
49.7
50.0

open
869.5
436.2
292.4
178.5
130.7
116.1
96.2
71.6
61.1
53.3
51.0
50.3
50.0

Attenuators

and

and

Example: (T Attenuator) A T-type attenuator is required to provide 3 0 dB insertion loss and to match
50  input and output. Find the resistor values.

using the following equation:

Figure 10. L attenuator conguration. (a) Rs < RI . (b) Rs > RI .

Figure 10 shows an L attenuator, which can be derived

from either a T or a pi attenuator, simply by removing one
of the resistors. As shown, different congurations are required depending on whether RS > RL or RS < RL .

using the following equation:

Check:
T Attenuator Insertion Loss
The T attenuator contains resistors R1 , R2 , and R3 ; these
form a T conguration, as shown in Figure 6. Insertion
loss is usually measured in dB, dened as IL (dB) = 20
log IL or |20 log IL |, the amount of attenuation required.
The insertion loss IL is given as

The Pi Attenuator Insertion Loss. Figure 9 shows a Pi

attenuator formed by resistors Ra , Rb , and Rc . The insertion
loss and conductances Gin and Gout are given by

The input and the output of resistances of the attenuator

are given by

and

In many cases, the attenuator has also to match the load

and the source impedance. In this case, R1 = R2 = R and
Rin = Rout = R0 . Thus,

and the insertion loss is given by

where G = 1/R; i.e., GL = 1/RL and so on.

The same Pi attenuator can be realized using a T attenuator with R1 , R2 , and R3 values using the Y transformation, as

Attenuators

shows that for RS > RL , we have

Table 5. Attenuator Input Power Reduction
% Input Power attenuated = (1-10dB/10 ) 100%
dB

dB

1
2
3
4
5
6
7
8
9
10
11

20.57
36.90
49.88
60.19
68.38
74.88
80.05
84.15
87.41
90.00
92.06

12
13
14
15
16
17
18
19
20
30
40

93.70
94.98
96.02
96.84
97.58
98.00
98.42
98.74
99.00
99.90
99.99

Table 6. HPND-4165 PIN Diode Specications

Parameter
HPND-4165 Test Conditions
High-resistance limit, RH
11001660 
10 A
Low-resistance limit RL
1624 
1 mA
Maximum difference in
resistance versus bias slope x
0.04
10 A and 1 mA

The selection between Pi and T is based on the value of

resistors that can be used in practice. With matching source
and load impedances, the values of the pi attenuator are

and

from which it can be shown that

and

and when we put R2 = 0, the insertion loss is calculated as

Example Design an L attenuator to match a 300 source

to a 50 load and determine insertion loss. Here RS > RL
using the following equation:

Using the following Equation:

and

Example: (Pi Attenuator) Repeat the above problem

using a Pi attenuator:
For Rs < Rl , we have

and
Using the following equation:

and
Using the following equation:
and

The L Attenuator Insertion Loss. An L attenuator can be

derived from a T or a Pi attenuator by removing one resistor. As shown in Figure 10, two congurations are obtained
depending upon RS > RL or RS < RL . Simple circuit theory

The corresponding insertion loss is

Attenuators

Attenuation (dB)
2
4
6
8
10
12
14
22

Attenuation (dB)
2
4
6
8
10
12
14
22

Table 7. Attenuator Resistor Values for Different Levels of Attenuation

R1 ()
R2 ()
5.73
11.31
16.61
21.53
25.97
29.92
33.37
42.64

215.24
104.83
66.93
47.31
35.14
26.81
20.78
7.99

Table 8. -Attenuator Resistor Values for Different Levels of Attenuation

R1 ()
R2 ()
436
221
150.5
116.14
96.25
83.54
74.93
58.63

11.61
23.85
37.35
52.84
71.15
93.25
120.31
312.90

Example Design an L attenuator to match 50 source to

75 load and determine the insertion loss.
RS < RL , using the following equation:

using the following equation:

Frequency:
Attenuation:
Accuracy:

VSWR:
Input power:
Connectors:
Length:
Diameter:
Weight:
Power sensitivity:
Temperature stability
<0.0004 dB/dB C

0 GHz to 3 GHz
50 dB
0.10 dB (dc)
0.15 dB (0 GHz to 2 GHz)
0.13 dB (0 GHz to 3 GHz)
1.15 (0 GHz to 1 GHz)
1.20 (1 GHz to 3 GHz)
1 W av., 1 kW PK at 30 to 70 C
Type N; St. St.; m, f
68 mm (2.7 in.)
210 mm (0.83 in.)
100 g (3.6 oz)
<0.005 dB/dB W; bidirectional in power

Applications

using the following equation:

Fixed attenuators are used in numerous applications. In

general, they can be classied into two distinct categories:
1. Reduction in signal level
2. Impedance matching of a source and a load
Those in the rst category are used in the following situations:

Operation of a detector in its square-law range for

most efcient operations.

FIXED ATTENUATORS
Fixed attenuators, commonly known as pads, reduce the
input signal power by a xed amount, such as 3 dB, 10
dB, and 50 dB. For example, an input signal of 10 dBm
(10 mW) passing through a 3 dB xed attenuator will exit
with a power of 10 dBm 3 dB = 7 dBm (5 mW). Figure 2
shows a xed coaxial commercial attenuator. A typical data
sheet for a xed coaxial attenuator is as follows (courtesy
of Weinschel Associates).

Testing of devices in their small signal range.

Reduction of a high-power signal to a level compatible
with sensitive power measuring equipment, such as
power sensors and thermistor mounts.
Those in the second category are used in the following situations:

Reduction of signal variations as a function of frequency. The variations here are caused by a high

10

Attenuators

Types
Based on construction, they are available in coaxial, waveguide, and strip line congurations. The various types are:
1.
2.
3.
4.
5.
6.

Figure 11. T/Pi xed attenuator conguration. (a) T section. (b)

Pi section.

VSWR. The attenuator provides a reduction in these

variations and a better match.

Reduction in frequency pulling (changing the source
frequency by changing the load) of solid-state sources
by high reection loads.

Figure 12. T/Pi xed attenuator construction.

Waveguide vane
Rotary vane (xed)
Directional coupler
T or Pi
Lossy line
Distributed resistive lm

Coaxial Fixed Attenuators. T or Pi congurations are

most commonly used both at low and high frequencies. At
low frequencies, normal wirewound resistors are used. At
high frequencies, thin lm resistors are used. Figures 11
and 12 show T and Pi xed attenuators. Thin-lm resistors designed for microwave frequencies are used, in place
of carbon resistors. These resistors employ a nichrome alloy
lm on a high-quality ceramic substrate to ensure a rmly
bonded lm with low-temperature coefcients. This type of
construction makes the resistors extremely stable at high
frequencies. The skin effect of these resistors is excellent,
used extensively the microwave applications.
The T and Pi conguration is obtained by placing the
resistors in series on the center conductor and in shunt,
contacting both the center and outer conductor. Thus, the
T conguration with one shunt anked by two series resistors and the Pi conguration with one series anked by
two shunt resistors can be fabricated. The series resistors
in the T and Pi conguration have less than 1 W capacity,
thereby severely limiting the use at high-power applications, unless an elaborate heat sinking is provided. Power
attenuators usually have huge sinks to handle high-power
applications.

Attenuators

11

Figure 15. Fixed single-mode, ber optic attenuator.

Figure 13. Fixed resistive card attenuator conguration.

Figure 14. Fixed RF attenuator.

Resistive Card Attenuator. In a xed dissipative,

waveguide-type resistive card attenuator, the card is
bonded in place (Figure 13). It is tapered at both ends
to maintain a low-input and low-output VSWR over the
useful waveguide band. Maximum attenuation per length
is obtained when the card is parallel to the E eld and
at the center, where the TE10 mode is maximum. The
conductivity and the dimensions of the card are adjusted,
by trial and error, to obtain the desired attenuation, which
is a function of frequency. The attenuation increases with
increase in frequency. In power applications, ceramic-type
absorbing materials are used instead of a resistive card.

Environmentally stable over temperature, humidity,

and vibration
High performance and low polarization dependent loss
(PDL)
Simple plug-in style enables rapid deployment
Wavelength independent: 1310/1550nm
The specications of a commercial, ber-optic, xed,
single-mode attenuator is given below. Figure 15 shows a
typical sample.
Technology Type
Attenuation, dB
Return Loss, dB
Attenuation accuracy
Operating Temperature, C

Doped Fiber
110, 15, 20
>50, typically 55
0.5 for 1-5 dB; 10% for > 6 dB
40 to 75

VARIABLE ATTENUATORS

RF Fixed Attenuators

Variable attenuators have a range, such as 0 dB to 20 dB,

0 dB to 100 dB, and so on. The variation can be continuous
or in steps, obtained manually or programmably.

Figure 14 shows a commercial RF xed attenuator whose

specications are shown below:

Step Attenuators

Average Power, W
Peak Power, W
Attenuation, dB
Frequency, GHz
VSWR
Tolerance, dB

5
125
1, 6, 10, 20, 30
DC-4, 4-6
1.15:1, 1.20:1
0.30, 0.50, 0.75

Fixed Fiber optic Attenuators

Fiber optic attenuators are engineered and manufactured
with continuous light absorbing metal-ion doped ber.
Metal-ion ber optic attenuators offer better feed-back
reection and noise performance than other attenuators
based on spliced ber, air-gap or offset-ber designs. The
salient features of these attenuators are:

A series of xed attenuators are mechanically arranged

to offer discrete step variation. The xed attenuators are
arranged in a rotatable drum or in a slab for switching between contacts. This arrangement provides discrete values
of attenuation in each position and a high reliability factor. The step size can be 0.1 dB, 1 dB, or 10 dB. Stationary
coaxial contacts provide the input and output of the device. These are used in applications requiring broadband
atness with low VSWR and satisfactory resettability over
ranges from 0 to 120 dB. Their application range is dc to
18 GHz.
Figure 3 shows a commercial manual step attenuator.
A typical data sheet looks as follows:
Manual Step Attenuators
Figure 3 shows manual step attenuator. A typical data
sheet looks as follows:

Frequency:
Attenuation:
Step size:
VSWR:
Connectors:
Height:
Depth:
Width:

0 to 4, 0 to 8, 0 to 12.4, 0 to 18 GHz
0 to 9, 0 to 60, 0 to 69
1 dB, 10 dB, 1 dB, respectively, for the above range
1.20, 1.25, 1.40, 1.50 for the above frequency range 1.25, 1.30, 1.45, 1.60 for the above frequency range
N/SMA; St. St.
83 mm (3.3 in.)
79 mm (3.1 in.) (excludes shaft and knob)
65, 65, 118 mm (2.6, 2.6, 4.7 in.) for the above three attenuation ranges

12

Attenuators

Continuously Variable Attenuators

Digital Step Attenuator

Figure 4 shows a continuously variable attenuator. Typical

specs are:

50, RF digital step attenuators are available with the following specications. Fig. 17 shows a functional schematic
diagram.

Frequency:
Connectors:
Zero loss:
Attenuation:

1 GHz to 18 GHz, 1 W av./1 kW PK

St. St., M, F; type N, SMA
typically 0.5 dB to 1 dB
0 to 9, 0 to 60, 0 to 69 dB

The various types of continuously variable attenuators

are:
Lossy wall
Moveable vane (Flap)
Rotary vane
Variable coupler
Absorptive type
Coaxial resistive lm
Variable T
Waveguide below cutoff (Piston)
Variable Fiber Optic attenuator
The specications of a commercial, variable, ber-optic,
single- and multi-mode attenuator is given below.
Back-Reection
Attenuation Range
Resolution
Wavelength
Fiber type
Temperature Range, C

> 30 dB, >50 dB, >60 dB

2 to 80 dB
0.01 dB up to 10 dB, 0.1 dB up to 30 dB
4001625 nm
Single mode, multimode
35 to 70

Number of Bits
Range, dB
Frequency, GHz
Programming Interfaces
Insertion Loss, dB
Return Loss (DC 2.2 GHz)

Programmable Attenuators
These are rapid switching attenuators with high accuracy
and repeatability, useful for remote and computerized
applications. Switching speeds can be as low as 30 ns.
Two varieties of the programmable attenuators are the
step-controlled and voltage-controlled types. The attenuation is varied by controlling the electrical signal applied
to the attenuator. These signals can be in the form of
either a biasing current or binary digit. The biasing can be
pulses, square waves, or sine waves. A typical data sheet
for coaxial programmable step attenuator is as follows:
Frequency:
Attenuation:
Maximum VSWR:

Insertion loss:

Digital Attenuators
Digital attenuators provide more than one step in attenuation. It depends on number of bits, LSB, attenuation range
and power rating. Fig. 16 shows the functional schematic
of a commercial, 5-bit, 15.5 dB, DC-GHz, digital attenuator that can be used for broadband communication system
applications which require accurate, fast and low power devices. This is made of patented silicon On Insulator (SIO)
CMOS manufacturing technology, which provides the performance of GaAs with the economy and integration capabilities of conventional CMOS.

Figure 16. Bit digital attenuator.

6
0.5 dB steps to 31.5
DC to 4.0 GHz
Flexible, serial and parallel
1.5
20 dB

Repeatability:
Power rating average:
Peak:
Maximum pulse width:
Life:
Solenoid
Voltage:
Speed:
Power:
RF connectors:
Shipping weight:

dc to 40 GHz
0 dB to 11 dB, in steps of 1 dB
1.3 GHz to 12.4 GHz
1.7 GHz to 34 GHz
1.8 GHz to 40 GHz
0.8 dB + 0.04 GHz
0 dB setting
0.03 dB
1W
50 W
10 s
5 million cycles per section minimum
20 V to 30 V
<20 ms
2.7 W
2.4 mm, F
291 g (10.3 oz)

Attenuators

13

Figure 17. Digital step attenuator.

Solid State Programmable Attenuators

Solid state programmable attenuators operating from 30
MHz to 3 GHz are introduced in the market. They have
low insertion loss and high switching speed. Specications
for two types are given below.
Frequency Range
Impedance, 
Attenuation
Attenuation Steps, dB
VSWR
Accuracy
1, 2, 4, 8 dB
1, 2, 4, 8 dB
16, 32, 64 dB
Insertion Loss
RF Input power
Switching Speed
Operating Temperature
Programming

Model 1
30 MHz to 3 GHz
50
0 to 127 in 1 dB steps
1, 2, 4, 8, 16, 32 and 64
1.6:1 max

Model 2
400-2000 MHz
50
0 to 127 in 1 dB steps
1, 2, 4, 8, 16, 32 and 64

0.3 dB to 2 GHz
0.4 dB to 2 GHz
0.5 dB or 3% (whichever is higher)

0.25 dB for 1, 2, 4, 8 dB
0.35 for 16 and 32 dB
0.50 dB for 64 dB
Max error 0.5 dB or 2%
5 dB max t@ 1 GHz
7 dB max t@ 2 GHz
+10 dB

6 dB max to 2000 MHz

8 dB max to 3000 MHz
15 dBm operating
30 dBm no damage
20 s max
0 to 70 C
TTL low for thru path
TTL high for attenuation

2 s
0 to 70 C
TTL low for 0 setting
TTL high for pad setting

Lossy Wall Attenuator

Moveable Vane (Flap) Attenuator

Figure 18 shows lossy wall variable attenuator. It consists of a glass vane coated with a lossy material, such as
aquadag or carbon. For maximum attenuation the vane is
placed in the center of the guides wide dimension, where
the electric eld intensity is the maximum. A drive mechanism with a dial then shifts the vane away from the center
so that the degree of attenuation is varied. This needs calibration by a precise attenuator. To match the attenuator to
the waveguide, the vane can be tapered at each end; usually a taper of g/2 provides an adequate match. Thus, it
is frequency sensitive and the glass dielectric introduces
appreciable phase shift.
Attenuation may also be obtained by inserting a resistive element through a shutter. The plane of the element
lies in the distribution of the electric eld across the wide
dimension of the waveguide and the result is a degree of
attenuation, which increases with the depth of insertion.
However, due to the discontinuity, there is reection of
energy.

Figure 19 shows a waveguide variable, dissipative attenuator. The card enters the waveguide through the slot in the
broad wall, thereby intercepting and absorbing a portion of
the TE10 wave. The card penetration, and hence the attenuation, is controlled by means of the hinge arrangement
to obtain variable attenuation. The ratings are typically
30 dB and widely used in microwave equipment. However,
the attenuation is frequency sensitive and the phase of the
output signal is a function of card penetration and hence
attenuation. This may result in nulling when the attenuator is part of a bridge network. Since it is not simple to
calculate the loss in dB, this type of attenuator has to be
calibrated against a superior standard. To overcome these
drawbacks, a rotary vane attenuator is used.
Rotary Vane Attenuator
The rotary vane attenuator is a direct reading precision
attenuator which obeys a simple mathematical law, A =
20 log cos2 = 40 log cos dB. As such, it is frequency
independent, which is very attractive criterion for an attenuator. A functional diagram illustrates the operating

14

Attenuators

Figure 18. Lossy wall attenuator conguration. (a) Minimum attenuator. (b) Maximum attenuator.

When all the strips are aligned, the electric eld of the
applied wave is normal to the strips and hence no current
ows in the attenuation strips and therefore no attenuation occurs. In a position where the central attenuation
strip is rotated by an angle , the electric eld of the applied wave can be resolved into two orthogonally polarized
modes; one perpendicular and one parallel to the resistive
card. That portion which is parallel to the resistive slab
will be absorbed, whereas the portion, which is polarized
perpendicular to the slab, will be transmitted.
Variable Coupler Attenuator
Figure 19. Movable vane (ap) variable attenuator conguration.

principle of this attenuator. It consists of three sections

of waveguide in tandem as shown (Figure 20). A rectangular to circular waveguide transition containing a horizontal attenuator strip is connected to a rotatable circular
waveguide containing an attenuator strip. This in turn is
connected to a circular to rectangular waveguide transition
containing a horizontal attenuator strip.
The incoming TE10 mode is transformed into the TE11
mode in the circular waveguide by the rectangular to circular waveguide transition with negligible reections. The
polarization of the TE11 mode is such that the e eld is
perpendicular to the thin resistive card in the transition
section. As such, this resistive card has a negligible effect
on the TE11 mode. Since the resistive card in the center can
be rotated, its orientation relative to the electric eld of the
incoming TE11 mode can be varied so that the amount by
which this mode is attenuated is adjustable.

These are basically directional couplers where the attenuation is varied by mechanically changing the coupling between two sections. This is accomplished by varying the
spacing between coupled lines. These attenuators have a
large range, high power handling capability, and retain calibration over a range of ambient conditions. They have a
higher insertion loss at lower frequencies (Figure 21).
Absorptive Attenuator
Figure 22 shows an absorptive variable attenuator. Attenuation is obtained by using a lossy dielectric material. The
TEM electric eld is concentrated in the vicinity of the center strip of the stripline. When the absorbing material is inserted in the high eld region, a portion of the TEM wave is
intercepted and absorbed by the lossy dielectric. Thus, the
attenuation increases. Since the characteristic impedance
of the stripline changes with the dielectric material insertion, the SWR tends to increase as the attenuation increases. To minimize this, the ends of the lossy material
are tapered to provide a smooth impedance transformation into and out of the lossy section. SWR values of >1.5

Attenuators

15

Figure 20. Rotary vane attenuator conguration.

Figure 23. Coaxial resistive lm attenuator conguration.

Figure 21. Variable coupler attenuator conguration.

Figure 24. Variable T attenuator.

Figure 22. Absorptive-type variable attenuator conguration.

are possible over a limited frequency range. In general, the

SWR deteriorates at low frequencies. The attenuation increases with increasing frequency for a xed setting. This
is another disadvantage, since this makes the calibration a
cumbersome procedure. Compensation techniques are occasionally used to reduce this variation with frequency.
Coaxial Resistive Film Attenuator
Figure 23 shows a coaxial resistive lm attenuator. In this
conguration, if r is the RF resistance per unit length, by
adjusting the length l, the series resistance R = rl of the
center conductor is changed; thus, the attenuation is variable. If I is the conduction current on the center conductor,
the voltage drop is V = RI = Irl. If Ei is the input voltage,
then the output voltage is E0 = Ei rlI and the attenuation
is

Figure 25. Coaxial variable cutoff attenuator conguration.

Variable T
The variable T attenuator is the same as the xed attenuator except that the resistors are variable (Figure 24). All
the three resistors are variable simultaneously to give good
input/output VSWR.
Waveguide Below Cutoff or Piston Attenuator
The simple principle of cutoff below frequency is used in
the piston or the cutoff attenuator. The cylindrical waveguide used is operating at a frequency below cutoff. For high
power applications, a coaxial conguration is used. A simple waveguide cutoff attenuator is shown in Figure 25. A
metal tube, acting as a waveguide, has loops arranged at
each end to couple from the coaxial lines into and out of
the waveguide. One of the loops is mounted on a movable
plunger or hollow piston so that the distance between the

16

Attenuators

Figure 26. (a) Standard variable piston attenuator and (bd) calibration curves. (b) Typical VSWR
versus frequency of SPA-2 attenuator with frequency. (c) Typical variation of insertion loss of SPA-2
attenuator with frequency in a 50- system. (d) Deviation versus indicated incremental insertion.
Typical deviation from linearity for the model SPA-2 operating frequency is 30.0 MHz.

Figure 28. CDMA handset transmit application.

loops is variable. The input coupling loop converts the incoming TEM wave into the TE11 mode in the circular guide,
while the output loop converts the attenuated TE11 mode
back to TEM. The attenuator can be matched by adding Z0
resistors. The attenuation is given as:
Figure 27. Laser piston attenuator. (Courtesy of Weinschel Associates.)

Attenuators

17

By choosing the diameter such that c < o , and hence

f/fc < 1, the above equation reduces to

This was obtained from

Figure 29. Functional block diagram of a digital cellular phone,

using variable attenuators.

Figure 30. Pin diode high-frequency equivalent circuit.

Figure 31. Typical RF resistance versus dc bias current for

HPND-4165.

(If oc = 10 cm, and o is much greater (10 times or more

(in this case, 1 m or more)), the attenuation increases 5.45
dB per cm of outward movement of the plunger.)
The sliding cylindrical conductors allow length l to be
varied, which varies the attenuation, since attenuation
A = l, where is the attenuation constant due to the cutoff
effect, and l is the length of the circular guide. The cutoff
wavelength is, c = 1.706D, where D is the diameter of the
waveguide. Thus the attenuation is:

or

The attenuation is independent of frequency; it depends

only on the physical dimensions and hence can be accurately controlled by maintaining tight tolerances on the
length and diameter of the circular guide. With A linearly
proportional to l, the cutoff attenuator is easily calibrated
and hence particularly useful as a precision variable attenuator.
The cutoff attenuator is one of the most widely used precision variable attenuators in coaxial measurement equipment. This is a reective-type attenuator, since the waveguide is essentially dissipationless. The signal is reected
rather than absorbed. For higher attenuation (>10 dB),
the SWR at both ports is very high (>30). This can cause
problems in certain applications.
This type of attenuator is very useful, but has the disadvantage of high insertion loss. Due to cutoff nature,
the insertion loss is high, up to 15 dB to 20 dB. If this
loss is overcome, piston attenuators are one of the most

Figure 32. Series pin RF attenuator or switch. (a) Complete circuit. (b) Idealized RF equivalent circuit.

18

Attenuators

Figure 33. Shunt pin RF attenuator or switch. (a) Complete circuit. (b) Idealized RF equivalent circuit.

Figure 34. Constant impedance pin diode attenuators. (a) Pi attenuator. (b) Bridged T attenuator. (c) T attenuator. (d) Resistive line
attenuator.

Figure 35. Fixed Pi attenuator.

Attenuators

accurate attenuators available. Values of 0.001 dB/10 dB

of attenuation over a 60 dB range are common. A good input/output match is obtained using inductive loops within
the waveguides. Excellent matching is obtained over the
entire range of attenuation due to inductive loop coupling.
Figure 26 shows a commercially available standard variable piston attenuator and the various calibration curves.
It contains an accurately dimensioned tube acting as a circular waveguide, below cutoff TE11 mode. Typical specications are (Courtesy of Weinschel Associates):
Frequency:
Mode:
Range:
VSWR:
Connectors:
Accuracy:

Resolution:

30 MHz
TE11 cutoff
0 dB to 120 dB
12.5 dB zero insertion loss
1.2 max in 50  system
Type-N, panel mounted
0.01 dB from 0 dB to 15 dB
0.005 db/10 dB from 15 dB to 100 dB
0.01 dB/10 dB from 100 dB to 120 dB
0.001 dB direct reading digital indicator

Laser Piston Attenuator. Figure 27 shows a laser piston

attenuator. The heart of this instrument is a precise
stainless steel circular waveguide, operated in the TE11
cutoff mode. Laser light, traveling between two antennas
in the center of the circular waveguide, measures directly
the changes in actual separation of the two antennas along
the same path as the TE11 mode propagates. The laser
signal is converted to attenuation in dB and corrected
for skin effect, the refractive index of air, and changes
due to temperature of the waveguide and pressure. The
specications are (Courtesy of Weinschel Associates):
Operating frequency:
Waveguide mode:
Incremental attenuation range:
Min insertion loss:
Resolution:
Attenuation readout:
Connectors:
VSWR (input and output):
Accuracy:
Weight:
Accessories:

19

tor for leveling and amplitude modulating a RF signal.

These attenuators provide local oscillator, IF, and RF
signal level control throughout communications, measurement, and control circuits. One example is the reduction
in the output of a receive mixer in a Code-Division Multiple Access (CDMA) base station prior to the IF amplier.
Also, to provide one step of transmit level control with little degradation of the noise gure (NF), it could be used in
a CDMA handset transmit chain between the mixer (upconverter) and the bandpass lter (Figure 28). Since the
attenuator is purely passive, it produces no additive noise
and the NF is essentially its insertion loss. Even in the
attenuator mode, the effect on the noise gure would be
minimal.
In Personal Communication Service (PCS) systems, the
base stations may be fed from multiple picocells that are
physically separated from it by up to 100 feet or more of
coaxial cable. The signal levels coming into the base station will vary depending on the cable length and individual transponder power. It is desirable to keep the signals
at uniform levels coming into the base station; to do so,
it may be necessary to attenuate the stronger signals. An
attenuator can be easily inserted for this purpose.
The upper end of a receivers linear dynamic range is
determined by the largest signal it can handle without being overdriven and producing unacceptable levels of distortion caused by device nonlinearities. Inserting an attenu-

Dual frequency 1.25 MHz + 0.05 MHz and 30.0 MHz + 0.1 MHz
TE11 , below cut-off
100 dB
10 dB nominal
0.0001 dB for  dB, 0.002 dB for total loss
Front panel 7 digit LED or remotely via IEEE bus
Type N jacks
1.2 max at 1.25 and 30 MHz in 50  system
0.001 dB/10 dB + 0.0005 dB between 15 and 115 dB total loss
Net: 77 kg (170 lb); shipping: 145 kg (320 lb)
Power supply, controller, calibration tape, two power cables, one
22 wire power cable, Instruction and Maintenance manual

ACTIVE ATTENUATORS
PIN Diode Attenuators
The normal diode junction consists of a p-type material
brought together with an n-type material to form the familiar PN junction. The PIN diode is distinguished from
the normal PN junction type by an area called an intrinsic
region sandwiched between the p+ doped and n+ doped silicon layers. This intrinsic layer has almost no doping and
thus has a very large resistance. When a variable dc control voltage forward biases the PIN diode, the dc bias or
control current causes it to behave as almost a pure resistance at RF frequencies, with a resistance value that can
be varied over a range of 1  to 10 K. As the bias current
is increased, the diode resistance decreases. This relation
makes the PIN diode ideally suited as a variable attenua-

ator before a low noise amplier (LNA) in the presence of

strong, in-band signals produces better reception by preventing them from overdriving the receivers front end.
This effectively shifts the dynamic range upward by the
amount of attenuation. It must be remembered that when
inserted into the system, the attenuator will also present
a load and a source impedance to the previous and succeeding stages, respectively, hence the importance of the
attenuator impedance match.
RF variable attenuators are used to control the transmitting and receiving signal power levels to prevent
strongweak adjacent signals from seriously degrading the
bit error rate (BER) of digital mobile communication systems, such as TDMA or CDMA. Figure 29 shows the basic
RF functional block diagram of a typical digital cellular
phone system, where variable attenuators are required.

20

Attenuators

Characteristics of the Pin Diode

The approximate high frequency equivalent circuit of a PIN
diode is shown in Figure 30. Here, RI is the effective resistance of the intrinsic (I) layer, given by

where IDC is the dc bias current in mA, and k and x are

device-dependent empirical constants. Although shown as
a variable, this resistance is constant with respect to the RF
signal. The high frequency resistance function is plotted in
Figure 31 for the Hewlett Packard HPND-4165 diode. For
a specic diode design, the exponent X is usually a constant. For the HPND-4165, X is typically 0.92. The constant k and therefore, RI , however, are highly dependent
on the fabrication and process control and its value can
vary by as much as 3:1 from diode to diode. For analog applications, such as a variable attenuator, where repeatable
attenuation with bias current is desired, the variation of
RI must be controlled. The HPND-4165 is precisely controlled in manufacturing, and resistance values at specic
bias points are specied and the slope of resistance versus
bias matched with narrow limits. The specication limits
of these parameters are shown in Table 4.
Applications
The PIN diode is ideally suited to switch and attenuate
RF signals. Since the PIN diode is a RF variable resistor,
the logical application is that of a variable attenuator. This
attenuator may be either a step or a continuously variable
type. Two of the simplest circuits are the series and shunt
attenuators shown in Figures 32 and 33.
Attenuation in the series PIN circuit is decreased (more
power appears at the output) as the RF resistance of the
diode is reduced. This resistance is reduced by increasing
the forward bias control current on the diode. The opposite occurs for the shunt conguration. The attenuation in
the shunt circuit is decreased when the RF resistance of
the diode increases because less power is absorbed in the
diode and more appears at the output. If the control bias is
switched rapidly between high and low (zero) values, then
the circuit acts simply as a switch. When used as a switch,
the attenuation that exists when the switch is on is called
insertion loss. The attenuation provided when the switch
is off is called isolation. If the diode is a pure resistance,
the attenuation for the series and shunt circuit can be calculated as

where Z0 = RG = RL = circuit, generator, and load resistance, respectively. In reviewing these equations, it is seen
that the attenuation is not a function of frequency but only
a ratio of circuit and diode resistances, which is a great advantage. As the bias on the diode is varied, the load resistance experienced by the source also varies. These circuits
are generally referred to as reective attenuators because
they operate on the principle of reections.

Many RF systems require that the impedance at both

RF ports remain essentially constant at the design value
Z0 . Four such circuits and their PIN diode counterparts are
shown in Figure 34. All four circuits operate on the principle of absorbing the undesired RF signal power in the PIN
diodes. In circuits (a), (b), and (c), the control current variation through each diode is arranged in such a way that the
impedance at both RF ports remain essentially constant at
the characteristic impedance (Z0 ) of the system while the
attenuation can be varied over a range of less than 1 dB to
greater than 20 dB. In circuit (d), the input impedance is
kept constant by using a distributed structure with a large
number of diodes. The impedance variation of each diode
is also shaped so that the diodes in the center of the structure vary more than those near the ports. The resulting
tapered impedance structure results in an essentially constant impedance at the ports, while the overall attenuation
can be varied up to a range of 40 dB to 80 dB, depending
on the length of the structure.
PIN diode Pi attenuator in Figure 30(a) is often selected
when designing a variable attenuator. The basic Pi xed
attenuator is shown, along with its design equations, in
Figure 35. Shunt resistors R1 and the series resistor R3
are set to achieve a desired value of attenuation, while simultaneously providing an input and output impedance
which matches the characteristic impedance Z0 of the
system.
Three PIN diodes can be used as shown in Figure 36 to
replace the xed resistors of the Pi circuit to create a variable attenuator. The attenuator provides good performance
over the frequency range of 10 MHz to over 500 MHz. However, the use of three diodes as the three variable resistors
in a Pi attenuator results in a complex unsymmetrical bias
network. If resistor R3 is replaced by two diodes, as shown
in Figure 37, the resulting attenuator is symmetrical and
the bias network is signicantly simplied. V+ is a xed
voltage, and Vc is the variable control voltage, which controls the attenuation of the network. The only drawback to
using two series diodes in place of one is the slight increase
in insertion loss. Resistors R1 and R2 serve as bias returns
for series diodes D2 and D3 . Resistors R3 and R4 are chosen to match the specic characteristics of the PIN diodes
used. Properly selected, they will provide the correct split
of bias current between series and shunt diodes required to
maintain a good impedance match over the entire dynamic
range of attenuation.
The PIN diode variable attenuator is an excellent circuit used to set the power level of an RF signal from a voltage control; used widely in commercial applications, such
as cellular telephones, PCN (personal communication networks), wireless LANs (local area networks), and portable
radios.
GaAs NMESFET Attenuator
The GaAs N-semiconductor metal semiconductor eld effect transistor (NMESFET) is used in microwave attenuator designs. The metalsemiconductor FET (MESFET) is
a eld effect transistor that operates on the principle that
the gate-to-source voltage controls the drain current. The
MESFET is a device extension of a JFET, where the gate

Attenuators

Figure 36. Three-diode Pi attenuator.

Figure 37. Wideband four-diode  attenuator.

Figure 38. MESFET T attenuator.

21

22

Attenuators

Figure 39. MESFET Pi attenuator.

structure is a Schottky MN (metalN semiconductor) junction.

In GaAs NMESFET attenuator designs, the devices are
operated either in the linear region where the device is
modeled as a voltage variable resistor or they operate as
an on/off switch in conjunction with thin-lm nichrome resistors to provide appropriate levels of attenutation. The
channel resistance of the GaAs NMESFET is known to follow the classical theory for a FET in the linear region of
operation. With the FET biased in the linear region, the
resistance varies inversely to the gate voltage as shown
below:

where Vg = gate bias voltage (V), Vp = pinch-off voltage

(V), and Rdso = channel resistance () with Vg = 0 V.
As the gate voltage approaches the pinch-off voltage, the
resistance becomes very high (relative to 50 ). Conversely,
as the gate voltage approaches zero, so does the channel resistance. For each attenuator conguration, two independent gate bias voltages are used; one to control the series
MESFETs and one to control the shunt MESFETs. The T
attenuator conguration is shown in Figure 38, with one
voltage controlling the series resistance arms, and another
the shunt resistance arm. Table 5 gives the resistor values
of the series and shunt resistances in a Z0 = 50  system.
The channel resistances of the MESFETs are matched as
closely as possible for these resistances. A matched condition at the input and output port to Z0 occurs when,

The resulting matched attenuation is

The Pi attenuator conguration is shown in Figure 39, with

one voltage controlling the shunt resistance arms, and another the series resistance arm. Table 6 gives the values
of the series and shunt resistances for different levels of
attenuation in a Z0 = 50  system. Shunt resistor R1 and
series resistor R2 provide and input and output impedance
which matches the characteristic impedance Z0 = 50  of
the system, while setting the desired level of attenuation.

The design equations are:

where K is the input to output voltage ratio.

GaAs NMESFET digital attenuators allow a specic
value of attenuation to be selected via a digital n bit programming word. In these designs, the NMESFET operates as an on/off switch and is used in conjunction with
nichrome thin-lm resistors to provide the desired level
of attenuation. Figure 40 shows the circuit congurations
used for individual attenuator bits. The switched bridged
T attenuator consists of the classical bridged T attenuator
with a shunt and series FET. These two FETs are switched
on or off to switch between the two states. The attenuation
in dB is given by

where Z2 0 = R1 R2 .
The performance is determined by the FET characteristics in the on and off states and the realizability limit on
required resistance values and their associated parasitics.
The switched T or Pi attenuators are similar in principle
to the switched bridged T attenuator except for the circuit
topology. These attenuators are normally used for high attenuation values. To obtain smaller values of attenuation,
the thin-lm resistors are replaced with appropriate channel resistances.
There are GaAs NMESFET digital RF attenuators on
the market with excellent performance, in both step and
continuously variable types. The variable or programmable
class allows a specic value of attenuation to be selected
from an overall range via an N-bit programming word.
They are more exible than step attenuators, as they allow any amount of attenuation to be set, but the cost is
greater circuit complexity. Both types have a bypass state
when no attenuation is selected, and the attenuation is just
the insertion loss of the device. An example of each type is
presented.
The RF Microdevices RF 2420 is a multistage monolithic variable or programmable attenuator which has as

Attenuators

23

Figure 40. GaAs digital attenuator circuit congurations.

Figure 42. Functional schematic of RF 2420 (one attenuator

section).

Figure 41. RF 2420 functional block diagram.

attenuation programmability over a 44 dB range in 2 dB

steps. The attenuation is set by ve bits of digital data. A
functional block diagram of the RF 2420 is shown in Figure 41. It consists of ve cascaded, dc-coupled attenuator
sections, each with its own logic translator. The logic translator converts the one-bit control signal, which uses logic
levels approximating standard TTL logic, to the voltage levels required to switch the attenuator stage FETS. The RF
input and output signal lines are biased at approximately
VDD , and therefore external dc blocking capacitors are required. An external VDD bypass capacitor is also required.
A functional schematic of the RF portion of one attenuator section is shown in Figure 42. A MESFET bridges
the series resistor in a resistive Pi attenuator, and two
more MESFETs are connected as a double-pole singlethrow (DPST) RF switch connecting the shunt branches
of the Pi attenuator to RF ground. In the bypass state, the
bridge MESFET is in its high conductance state, and the
DPST switch is open, so that the Pi-attenuator is effectively removed from the circuit. When the attenuator bit
is selected, the bridge MESFET is put into its low conductance state or cutoff state and the shunt FETs are put
into their on state, so that the Pi-attenuator is connected
into the RF series path. This attenuator has only moderate

variation across a broad band of operation from 100 MHz

to 950 MHz, as illustrated in Figure 43.
Furthermore, the attenuation varies smoothly and consistently with attenuator switch settings. Other features
of the device are single 3 V to 6 V supply operation, and
4 dB insertion loss, and the input and output have a low
VSWR 50  match. All these features make the RF 2420 an
excellent component for communications systems that require RF transmit power control by digital means. Typical
applications are in dual mode IS-54/55 compatible cellular transceivers and TETRA systems. Figure 44 shows the
complete schematic details of the RF 2420 being employed
in a typical RF/IF switching attenuator application.
The RF Microdevice RF 2421 is a GaAs MESFET
switched step attenuator. It has a single-step digitally controlled attenuation of 10 dB. A functional block diagram
of the device is shown in Figure 45. The supply voltage
range required is 2.7 V to 6 V dc. The input and output of
the device have a low voltage standing wave ratio (VSWR)
50  match and the RF output can drive up to +16 dBm. It
has 1.0 dB of insertion loss over the specied 500 MHz to
3 GHz operating frequency range. The resistors are nickel
chromium (nichrome) and provide excellent temperature
stability. The RF ports are reversible, which means the input signal can be applied to either port. The attenuation
control pin has an internal pull-down resistor which causes
the attenuator to be turned off when it is not connected.
Figure 46 illustrates the RF 2421 being used to set the RF
signal level in a communications system.

24

Attenuators

Figure 43. Attenuation and frequency response characteristics of RF 2420 5-bit digital RF
attenuator.

Figure 44. RF 2420 RF/IF switching attenuator schematic.

MOSFET Attenuators

Figure 45. RF 2421 functional block diagram.

Active voltage attenuators have many useful applications

in analog integrated circuit design. Some of the applications are in the feedback loops of nite gain ampliers and
in the input stages of transconductance ampliers. In discrete circuit design, the most popular way to design a nite
gain amplier with precisely controlled gain, high linearity, and low output noise is to use operational amplier and
a voltage attenuator in the feedback loop. Here the voltage
attenuator consists of two resistors connected in series as
shown in the classical noninverting and inverting op amp
gain congurations of Figure 47. Resistor attenuators are

Attenuators

25

Figure 46. RF 2421 single-step 10 dB attenuator application.

Figure 47. Op-amp noninverting (a) and inverting (b) gain congurations.

not useful in integrated circuit design because of their large

areas, low input impedance, large power dissipation, and
parasitic capacitances, and precise resistance values cannot be realized.
Three MOS active voltage attenuator congurations
useful for the realization of nite gain ampliers in monolithic circuits are presented. The attenuators are two
single-input attenuators and a summing attenuator that
has two inputs. These attenuators are simple in structure,
consisting only of MOSFETs. Therefore, they are easy to
fabricate in standard CMOS semiconductor processes. The
attenuation factor is precisely controlled over a wide range
of gains because it ideally depends only on the ratios of the
dimensions of the MOSFETs.
Attenuator I, shown in Figure 48 is an active linear
voltage attenuator consisting of two n-channel MOSFETs
fabricated in a common substrate. The capability to fabricate the MOSFETs in a common substrate has several advantages. First, both n-channel and p-channel attenuators
can be monolithically fabricated in a standard CMOS process. Second, the required area of the attenuator is much
smaller. As seen in Figure 48, the substrate is common for
both MOSFETs and is connected to the source of the bottom transistor M1. The circuit operates as a linear voltage
attenuator when M1 is in the ohmic region and M2 is in
the saturation region.
The operating conditions of the MOS attenuators in this
section are derived as follows: The list of symbols used are:

VI
Vo
VDD
VB
VBB
VTON = VTON1 = VTON2
VT2
V1
V2

ID
W
L
W1 , W2
L1 , L2
K
n
CoX

Input voltage
Output voltage
Drain supply voltage
Bias supply voltage 1
Bias supply voltage 2
Zero bias threshold voltage of
M1 and M2
Threshold voltage of M2 due
to body bias effect
Input voltage 1
Input voltage 2
Body effect parameter
Barrier potential
Drain current
Width of channel
Length of channel
Width of channels 1, 2
Length of channels 1, 2
Device constant, n CoX
Mobility of electron
Gate oxide capacitance per
unit area

The zero bias threshold voltage of both MOSFETs is

VTON1 = VTON2 = VTON . The proper operating conditions will
be met, provided

where

26

Attenuators

Figure 48. (a) Circuit and block diagram of attenuator I consisting of two n-channel MOSFETs, and (b) block diagram of amplier
consisting of an op-amp and attenuator.

Since M1 is operating in the ohmic region and M2 is in the

saturation region, the drain current of each MOSFET is
given by

and

Equating the two drain currents, the relationship between

V1 and Vo is obtained as

Figure 49. Dc transfer characteristic of attenuator I ( =

0.07824).

where

characteristic is 0.07824 at an input quiescent voltage of

3.5 V.
A nite gain amplier consisting of an ideal op amp and
attenuator I in the feedback loop is shown in Figure 48.
Since the op amp is assumed ideal,

If each MOSFET in the attenuator is fabricated in a

separate substrate and the substrate of each MOSFET is
connected to its source ( = 0), the dc transfer characteristic
relating VI and Vo becomes a linear equation:

or

where is the small signal attenuation factor.

In this case, is

Eq. (70) is a special case of Eq. (68), when the bulk effect
term due to is ignored. When the substrate is separate,
the small signal attenuation factor from Eq. (71) is precisely determined by width/length ratios. If the substrate
is common, the relationship between the input and output
is still very linear as given by Eq. (68) even though the
equation appears to be a nonlinear quadratic.
Figure 49 shows the typical dc transfer characteristic of
the attenuator consisting of M1 (12 10 m2 ) and M2 (3
10 m2 ) when the substrate is common ( = 0) and VDD
= 5 V. The dc transfer characteristic exhibits a high degree
of linearity for the input range 2 V to 5 V. The small signal
attenuation factor () which is the slope of the dc transfer

That is, the dc transfer function of the amplier is the inverse function of the dc transfer function of the attenuator
in the feedback loop. Thus, the transfer function between


the input V I and the V o of the amplier is given by Eq. (68)


when Vo is replaced by V I and VI by V o . The small signal
voltage gain

is the reciprocal of the attenuators attenuation factor in

the feedback loop. Figure 50 illustrates the dc transfer
characteristic of the nite gain amplier.
Two slightly different linear inverting voltage attenuator congurations consisting of two n-channel MOSFETs
are shown in Figure 51. These circuits operate as a linear
inverting voltage attenuator when both transistors are in
the saturation region. Assuming the zero bias threshold of
both of the MOSFETs is VTON , the condition will be met,

Attenuators

27

Figure 51. Circuit and block diagrams of linear inverting voltage

attenuators consisting of two n-channel MOSFETs.
Figure 50. Dc transfer characteristic of amplier (AV = 1/ =
12.78).

provided

and

Under this condition, the drain currents of the transistors

are given by:

where

Since the two drain currents are the same for the circuit,
the dc transfer function relating VI and Vo is found by
equating Eqs. (77) and (64):

where

If = 0 in Eq. (80) which corresponds to the case of circuit

(b) in Figure 51 where the substrate is separate, the dc
transfer characteristic reduces to a linear equation,

In this case, the small signal attenuator factor is

which is precisely determined by the width/length ratios

of the MOSFETs. From Eqs. (80) and (68), it is noted that
the output dc operating voltage is controlled by VB , independent of the attenuation factor.
The dc transfer characteristic between VI and Vo calculated from Eq. (80) for the common substrate case, R1 =
0.1149 and VB = 3.993, and the dc transfer characteristics
calculated from Eq. (82) for the separate substrate case, R1
= 0.1 and VB = 3.449 are shown in Figure 4852 for the

Figure 52. Dc transfer characteristics of attenuator II linear inverting voltage attenuators.

range restricted by Eq. (76). The parameter values ( =

0.525 V1/2 , = 0.6 V, and VTON1 = VTON2 = VTON = 0.777 V)
were used in the calculation. The dc transfer function given
by Eq. (80) for the common substrate case appears nonlinear, but the degradation from linearity due to practical
values of is not signicant. The small signal attenuation
factor , the slope of transfer characteristic in Figure 52, is
0.1. The high degree of linearity supports the usefulness
of both congurations in precision attenuator or nite gain
amplier applications.
Figure 53 shows a nite gain amplier with attenuator
II in the feedback loop of an op amp. Assuming the op amp
is ideal,

The transfer function of the amplier is the inverse function of the transfer function of the attenuator in the feedback loop. The dc transfer function of the amplier is given

by Eq. (80) when VI is replaced by V o and Vo is replaced


by V I . If the substrate is separate, VI replaces V o and Vo

replaces V I in Eq. (82); then

where the small signal attenuator factor = R1 .

A summing attenuator is necessary to realize versatile
multiple input nite gain ampliers in integrated circuits.

28

Attenuators

Similarly, it can be shown, that the dc transfer function

between V1 and Vo is obtained as

where
Figure 53. Amplier consisting of op-amp and attenuator II in
the feedback loop.

Figure 54. Circuit and block diagram of summing attenuator.

Figure 54 shows a two-input active linear inverting voltage summing attenuator which consists of two attenuators
cascaded. For the summing attenuator, VBB is used to control the output dc operating voltage and input signals are
designated as V1 and V2 .
As for the inverting attenuator, the summing attenuator works when all the MOSFETs M1M4 are operating in
the saturation region. The dc transfer characteristics are
found by equating the drain currents in the saturation region for each transistor. Assuming the zero bias threshold
voltages for the four MOSFETs are matched at VTON , the
four transistors are in the saturation region provided,

If = 0 in Eqs. (92) and (80), the equations become linear.

This is realized if each transistor is fabricated in a separate
substrate and the substrate of each transistor is connected
to its source. In this case, the attenuation factors are given
by 1 = R1 , and 2 = R2 . Even when = 0, which is the
case when the substrates are common, the transfer characteristics between V1 and Vo and between V2 and Vo are
nearly linear as shown in Figure 57 for practical values of
. In the calculation of Figure 55, = 0.5255 V1/2 , = 0.6 V,
and VTON = 0.777 V were used which are standard for a 2
CMOS process and R1 = 0.1149 and R2 = 0.1290 were set
such that the small signal attenuation factors for V1 and
V2 are both 0.1. The operating points were set by VBB =
5.712 V such that VoQ = 2.5 V (VBQ = 3.993 V) when V1Q =
V2Q = 2.5 V.
Summing and subtracting amplier congurations using the inverting attenuator and the inverting summing
attenuator are shown in Figure 56.
Circuit (a) in Figure 56 functions as a summing amplier and the circuit (b) functions as a subtracting amplier,
with controllable weights. Assuming ideal op amps and attenuators, we obtain

Equating V and V+ , the output is given by

By equating the drain currents of M3 and M4 given by

From Eq. (98), the circuit in Figure 56(a) is a summing

amplier with a wide range of available gain from each
input. Similarly, for the circuit in Figure 56(b), we obtain

and

Equating V+ and V , the output is given by

where

The dc transfer function between V2 and VB is obtained as

where

From Eq. (99), the circuit in Figure 56(b) is a subtracting

amplier with a wide range of available gain for each input.
The active attenuator and the active summing attenuator have many desirable characteristics such as small
size, nearly innite impedance, low power dissipation, and
precisely controllable attenuation ratio with excellent linearity. These attenuators and the nite gain ampliers

Attenuators

29

Figure 55. Dc transfer characteristics of summing attenuator.

Figure 56. (a) Summing amplier. (b) Subtracting amplier.

obtained from these attenuators and op amps will nd increased applications in analog integrated circuits.

Noise
Noise in a communication system can be classied in
2 broad categories, depending on its source. Noise generated by components within a communication system,
such as resistive, extender, and solid-state active devices,
comprise internal noise. The second category, external
noise, results from sources outside a communication system, including atmospheric, man-made, and extraterrestrial sources.
External noise results from the random motion of a
charge carrier in electronic components. The three types
include:
1. Thermal noise: caused by random motion of free electrons in a conductor or semiconductor excited by thermal agitation;
2. Shot noise: caused by random amount of discrete charge
carriers in such devices as thermionic tubes or semiconductors in devices
3. Flicker noise: produced by semiconductors by a mechanism not well understood and is more severe the lower
the frequency.
Atmospheric noise results primarily from spurious radio waves generated by the natural discharges within the
atmosphere associated with thunderstorms. Man-made
noise sources include high voltage power line discharge and
computer-generated noise in electric motors.

Figure 57. Variable attenuator using GaAs MESFET

CONT+/CONT = VDD/GND in attenuation mode and
CONT+/CONT = GND/VDD in through mode.

Other noises include:

Generationrecombination noise: due to free carriers

being generated and recombining in semiconductor
material. They are random and can be treated as a
shot noise process.

Temperature-uctuation noise: the result of the uctuating heat exchange between a small body, such as
a transistor, and its environment due to the uctuations in the radiation and heat conduction processes.

30

Attenuators

Figure 59. Switchable-network attenuator.

Figure 60. Switchable-element attenuator.

Figure 61. Switchable attenuator.

Switchable Attenuators

Figure 58. Microstripslot-line attenuator on a silicon substrate

with an override ferrite slab.

ADDITIONAL TYPES
Figure 57 shows a 4 dB step, 28 dB variable attenuator for
1.9 GHz personal handy phone system transmitter fabricated using silicon bipolar technology with fT of 15 GHz.
The GaAs MESFET variable attenuator is congured with
resistive Pi attenuators and GaAs switches as shown. Step
accuracy within 1.2 dB and total vector modulation error
of less than 4% were realized for 15 dBm output. The
attenuator consumes 21 mA with 2.7 V power supply and
occupies 1.1 mm 0.5 mm. This unit is being developed.
This shows the technology trend.
Figure 58 shows the top view and cross section of a prototype optical microwave attenuator that can be controlled
by illuminating the silicon substrate. The maximum attenuation is 30 dB using laser diode illumination. It is a microstrip line whose substrate consists of silicon and ferrite
slabs. The ferrite slab is overlaid on the microstrip. There
is a slot on the ground plane under the strip. A white light
from a xenon arc lamp with a parabolic mirror is focused
by a lens to the silicon surface through the slot. The intensity of the light is not uniform along the slot direction.
Due to the light, electronhole pairs are induced and the
permittivity and conductivity of the silicon are changed,
which vary the phase and amplitude of the microwave.
With 240 mW optical power illumination, an attenuation in
the range of 17 dB to 26 dB was obtained in the frequency
range from 8 GHz to 12 GHz.

Switchable attenuators allow users to vary the attenuation

for various applications, such as in production, eld, and
bench-top applications. They offer mechanically or electrically controllable attenuation levels. There are two types
of switchable attenuators: (1) switched-network attenuators, and (2) switched element attenuators. In switchednetwork attenuators, PIN diode switches are used to develop two or more paths for changing attenuation values.
Once developed, it can be used to obtain several attenuation values. In switched-element attenuator, the resistive
elements have multiple values. Either a pi pad, a tee pad
or a reection attenuation conguration can be used as the
initial network in which the resistive elements are variable. Typically FETs are used for switching and the set-up
is implemented in MMIC format.
A typical data sheet for one model is shown in Table x
Frequency
dB
Impedance
VSWR
Accuracy
Insertion Loss
Average Power
Peak Power
Connectors

DC-0.5 GHz
0 to 102 by 1 dB
50 
1.2:1 to 0.5 GHz
0.5 dB to 0.03 GHz 1 dB to 0.5 GHz
0.3 dB max to 0.1 GHz 1.5 dB max to 0.5 GHz
0.5 W (25 C)
750 W, 3 s pulse
BNC

Audio Attenuators
Audio attenuators need compact design to reduce noise and
give audio volume controls with accurate attenuation and
tracking (0.05 dB). Resistor network using surface mount
resistors for short signal path and very low inductance and
stray capacitance seem to be successful in achieving the
end results. Shown in Fig. 62 is a surface mount audio attenuator with 24 steps. The series resistor networks consist
of 23 non-inductive, low noise surface mount lm resistors.
The layout of the PC boards and the surface mount resistors reduce the signal path compared to normal leaded resistors. The surface mount lm resistors also have very low

Attenuators

Power, W
Impedance, 
Frequency Range, GHz
Attenuation

Figure 62. Stereo attenuator.

Connection
Max VSWR
4 GHz
8 GHz
18 GHz

Model 1
50
50
DC to 18
3, 6, 10, 20,
30, 4
N

31

Model 2
150
50
DC to 8
3, 6, 10, 20, 30, 4
N M/F
1.20:1
1.30:1

1.35:1

ACKNOWLEDGMENT
The author is grateful to Mr. Grant Richards of ECET
Dept., Purdue University for his help with xed and variable ber optic attenuators.
Figure 63. High power attenuatorModel 1.

BIBLIOGRAPHY
Reading List

Figure 64. High power attenuatorModel 2.

series inductance and very low stray capacitance, allowing

a wide bandwidth.

High Power Attenuators

Shown in Fig. 63 is the group of high power attenuator, a
new addition to commercial, xed attenuators. This model
features a frequency range of DC-18 GHz with an input
power rating of 50 W CW. Standard attenuation values are
3, 6, 10, 20, 30 and 40 dB and the VSWR is rated at 1.35:1 at
18 GHz. A robust mechanical package with stainless steel
Type N connectors is designed to meet the requirements
of MIL-A-3933. Applications include high power amplier
design and test environments as well as defense and radar
requirements.
For applications including high power radar, amplier
test, telecommunication labs and MRI calibration another
new type, high power, xed attenuators were introduced
in the market (Figure 64). This type features a frequency
range of DC-8 GHz with an input power rating of 150 W
CW. Standard attenuation values are 3, 6, 10, 20, 30 and
40 dB and the VSWR is rated at 1.20:1 @ 4 GHz and 1.30:1
@ 8 GHz. The specications of the above two models are
shown below.

F. G. Ananasso A Low Phase Shift Step Attenuator using PIN

Diode Switches, IEEE Trans. Microwave Theory Tech., MTT28 (7): July 1980.
P. S. Bochert FET Attenuator, 0-1 GHz Applied Microwave and
Wireless, Spring 1996.
R. G. Brown et al. Lines, Waves, Ana Antennas, New York: The
Ronald Press Co. 1973.
R. S. Elliot An Introduction to Guided Waves and Microwave Circuits, Englewood Cliffs, NJ: Prentice-Hall, 1993.
Engineering staff of the Microwave Division, Microwave Theory
and Measurements, Hewlett-Packard Co., 1962.
S. C. Harsany Principles of Microwave Technology, Englewood
Cliffs, NJ: Prentice Hall, 1997.
M. R. Haskard Thick Film HybridsManufacture and Design,
New York: Prentice-Hall, 1988.
Hewlett Packard Application Note 1048, A Low-Cost Surface Mount PIN Diode Attenuator, Hewlett Packard Co.,
1996.
Hewlett Packard Application Note 922, Applications of PIN
Diodes, Hewlett Packard Co., 1997.
IEEE Std 474-1973, Specications and Test methods for Fixed and
Variable Attenuators, DC to 40 GHz.
T. Koryu Ishii Microwave Engineering, New York: Harcourt Brace
Jovanovich, Publishers, 1989.
Joon-Yu Kim R. L. Geiger MOS Active Attenuators for Analog ICS
and Their Applications to Finite Gain Ampliers, ProceedingsIEEE International Symposium on Circuits and Systems,
1994.
Joon-Yu Kim R. L. Geiger Performance Characterization of an
Active Attenuator Using Two Cascaded MOSFETS, Proceedings of the 36th Midwest Symposium on Circuits and Systems,
1993.
Joon-Yu Kim R. L. Geiger Characterization of Linear MOS Active
Attenuator and Amplier Elec. Lett., 3 (7): March 30, 1995.
Joon-Yu Kim R. L. Geiger An Inverting MOS Active Attenuator for
Monolithic Applications, Proceedings of the Midwest ElectroTechnology Conference, 1993.

32

Attenuators

T. S. Laverghetta Practical Microwaves, Englewood Cliffs, NJ:

Prentice-Hall, 1996.
R. LaVerne Libbey Video Attenuator using a Multiplier and FET,
A Publication of RCA, New Jersey: 1975.
RF Microdevices, RF 2420 Programmable Attenuator Data Sheet,
1997.
RF & Microwave Test Accessories Catalog, HP, 1997/98.
RF Microdevices Technical Application note TA 0027 Integrated,
Single Step, 10 dB Attenuator for Power Control Applications,
1997.
RF Microdevices, RF 2421 10 dB Switched Attenuator Data Sheet,
1997.
MIL-HDBK-216, Military handbook, R. F. Transmission Lines and
Fittings, Section 14, Attenuators, Nov. 1976.
MIL-A-3933E, Military specication, attenuators, xed, general
specication for 1985.
MIL-A-3933E, Suppl. 1, Military specication, Attenuators, Fixed,
General Specication for 1985.
S. Otaka et al. A 1.9 GHz Si-Bipolar variable Attenuator for PHS
Transmitter, IEEE J. Solid State Circuits, 32 (9): 14241429,
September, 1997
Reference Data for Radio Engineers, 1957, International Telephone and Telegraph Corp., New York.
P. A. Rizzi Microwave EngineeringPassive Circuits, Englewood
Cliffs, NJ: Prentice-Hall, 1988.
D. Roddy Microwave Technology, Englewood Cliffs, NJ: PrenticeHall, 1986.
S. E. Saddow C. H. Lee Scattering Parameter Measurements on
Optoelectronic Attenuator, IEEE MIT-S Digest, 1994.
H. W. Sams Reference Data for Radio Engineers, 7th ed., 1985,
Indianapolis, IN.
G. E. Schafer A. Y. Rumfelt Mismatch Errors in CascadeConnected Variable Attenuators, IRE Trans. Microwave Theory Tech., 1959.
H. Shimasaki S. Matsuda M. Tsutsumi Phase compensation in
an Optically Controlled Microwave attenuator, IEEE MTT-S
Digest, 17031706, 1997.
V. A. Suprynowicz Electrical and Electronics FundamentalsAn
Applied Survey of Electrical Engineering, New York: West Publishing Company, 1987.
A Vector Attenuator for Feedforward Amplier and RF Predistortion Use, Product Feature, Microwave J., Oct. 1997.
Weinschel Associates Catalogue, Attenuators and Terminations,
1998.
R. E. Ziemer W. H. Tranter Principles of Communications
Systems, Modulation, and Noise, New York: Wiley, 1988.
V. F. Valey Modern Microwave Technology, Englewood Cliffs, NJ:
Prentice-Hall, 1987.

Additional Reading List

Attenuators, www.electronics-tutorials.com
www.microwaves101.com/encyclopedia/attenuators.cfm, Aug 28
2006
Rf Fixed attenuators, www.e-meca.com/rf-attenuators.htm, Aug
25 2006
Fiber optic attenuators, www.Telect.com, Aug 25 2006
Fiber optic xed and variable attenuators, www.berdyne.com, sep
2006
High power attenuators, www.Trilithic.com, Aug 28 2006

Digital attenuator, www.psemi.com, Aug 2006

Audio attenuators, www.dact.com, Aug 25 2006
Parallel, digital attenuator, www.mysolservices.com, Sep 04 2006
Switchable attenuators, www.trilithic.com, Sep 04 2006
Solid state programmable attenuators, www.trilithic.com, Sep 04
2006

RAJI SUNDARARAJAN
EDWARD PETERSON
ROBERT NOWLIN
Arizona State University East,
Mesa, AZ
Currently at ECET Dept.,
Purdue University

218

BANDPASS FILTERS

BANDPASS FILTERS
A bandpass filter is an electrical device that passes the spectral components of an electrical signal around a certain frequency f 0 with little or no attenuation, while it mostly rejects
other spectral components (Fig. 1). Bandpass filters are common building blocks of many electronic systems. They find
applications in diverse fields such as communications, audio,
instrumentation, and biomedicine. To illustrate a typical application of a bandpass filter, consider the simultaneous
transmission of n signals in one communications channel using frequency multiplexing techniques. The signals can share
the same channel because their individual frequency spectra
are shifted so that they occupy nonoverlapping regions (or
bands) of the frequency spectrum. Frequency modulation is
used to shift the baseband spectrum of each of the signals
(centered originally at zero frequency or dc) to center frequencies f 01, f 02, . . ., f 0n (Fig. 2). In order to avoid overlapping, the
center frequencies must have a minimum separation of at
least the bandwidth of the signals. Bandpass filters are used
on the receiver side in order to select or filter out only one
of the signals transmitted in the channel. A process called
demodulation is used to shift the spectrum of the selected signal back to baseband (to a zero center frequency).
T( f )
BW

fp1

f0

fp2

Figure 1. Frequency response of ideal bandpass filter.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

BANDPASS FILTERS

219

s-plane

f01

f02

f03

f0n

Figure 4. Polezero plot of second-order bandpass filter.

Figure 2. Spectrum of n signals in a communication channel.

IDEAL BANDPASS FILTERS

Ideally, a bandpass filter is characterized by its center frequency f 0 and its bandwidth BW. The bandwidth is defined in
terms of upper and lower passband edge frequencies f p1 and
f p2, respectively, and given by BW f p2 f p1. Typically, f p1
and f p2 specify frequency points at which the gain decreases
by a factor 2. The frequency response plot of Fig. 1 shows
the gain A as a function of frequency f of an ideal bandpass
filter. An important parameter of a bandpass filter is its selectivity factor SF, which is expressed by SF f 0 /BW. The selectivity is a measure of the filters ability to reject frequencies
outside its passband. It is also a relative measure of the reciprocal bandwidth. Highly selective filters (also denoted narrowband filters) have a bandwidth that constitutes only a
small fraction of f 0. Narrowband filters with large selectivity
factors (e.g., SF 50) are commonly required in communication systems. For ideal bandpass filters, the frequency range
is divided into three regions: the passband region where the
gain is approximately constant ( fp1 f f p2) and the lower
and upper stopbands ( f f p1 and f f p2, respectively), where
the gain is ideally zero or the attenuation or reciprocal gain
is infinite. The ideal bandpass filter has sharp transitions between the passband and the two stopbands.
PRACTICAL BANDPASS FILTERS
The typical frequency response of a practical passband filter
is shown in Fig. 3. It has a relatively constant gain possibly
with fluctuations (ripple) with maximum amplitude Ap within
the passband. The passband edge frequencies f p1 and f p2 are
defined, in this case, as the minimum and maximum frequencies with gain, A Ap. The center frequency f 0 is commonly

T( f )
BW
A

Ap

the center of geometry of the passband edge frequencies: f 0

f p1 f p2. In a practical filter, there is a gradual transition between the passband and the upper and lower stopbands.
Therefore, besides the passband and stopband there are also
two transition bands. Two frequencies f s1 and f s2, each denoted lower and upper stopband edge frequencies, respectively, define the stopbands in a practical bandpass filter.
Stopband regions are characterized by a small gain with maximum value, 1/As, where As is the stopband attenuation. Passband ripple Ap and stopband attenuation As are commonly
specified in a logarithmic unit denoted decibel according to
As (dB) 20 log As. Practical bandpass filters can have monotonic decreasing gain or equal gain fluctuations (ripple) both
within the passband and the stopband.
MATHEMATICAL CHARACTERIZATION
OF A BANDPASS FILTER
The simplest bandpass filter is the second-order filter. It is
characterized by the inputoutput relation or transfer function:
T( f ) =

j BW f
f 20 + j BW f f 2

(1)

This transfer function is a complex function with magnitude

and phase. The magnitude (frequency response) obtained
from Eq. (1) has the form
|T ( f )| =

BW f
( f f 2 )2 + (BW f )2
2
0

(2)

The polezero plot (in the complex frequency plane also

known as the s-plane) of a second-order bandpass filter is
shown in Fig. 4. It has a zero at the origin (shown as a circle)
and two complex conjugate poles (shown as marks). The selectivity is associated with the relative distance of the poles from
the imaginary axis in the s-plane. The distance from the origin to the poles corresponds to the center frequency in radians, 0 2f 0.
BANDPASS FILTER IMPLEMENTATIONS

As

fs1 fp1

f0

fp2 fs2

Figure 3. Practical bandpass filter.

Depending on the center frequency and selectivity, there exist

several possible implementations of bandpass filters. In general, the higher the selectivity and the center frequency, the
more complex the filter becomes. Two very important aspects
are: miniaturization and compatibility with very large scale
integration (VLSI) systems technology. These have dictated

220

BANDPASS FILTERS

R
vOUT
vIN +

vIN +

Figure 5. Second-order RLC bandpass filter.

the evolution of bandpass filters and of most other electronic

circuits. Compatibility refers to the fact that the filter can be
fabricated on a CMOS integrated circuit as a part of a VLSI
system in CMOS technology. This technology allows the fabrication of very complex analog and digital electronic systems
with hundreds of thousands or even millions of transistors on
a single integrated circuit. CMOS compatibility is crucial in
order to reduce manufacturing costs and to increase system
reliability. Automatic tuning and low power consumption are
also important aspects for bandpass filters. Tuning consists
in the process of adjusting the filters response to compensate
for unavoidable fabrication tolerances in the values of the filter elements. These tolerances cause the filters response to
deviate from the ideal (nominal) response. Low power is important for portable equipment like cellular phones and bioimplantable devices.
Passive Filters
For many years, most filters were exclusively implemented as
passive RLC circuits using resistors, inductors, and capacitors
(1). Figure 5 shows an example of a resonant RLC circuit used
as a bandpass filter. This filter is characterized by the transfer function of Eq. (1) with f 0 1/2 1/ LC and BW
1/(CR). The transfer function of this circuit has the polezero
plot shown in Fig. 4. Ceramic filters based on bulk electromechanical resonance phenomena in piezoelectric materials
have been used in the radio frequency range specially for requirements of high selectivity and accurate center frequency.
Inductors have several problems: they have large physical dimensions and cannot be integrated unless their value is very
small; they are temperature dependent; and their value is
subject to large manufacturing tolerances. They also have
poor characteristics at low frequencies, and their value tends
to change with time. RLC passive filters cannot be automatically tuned at the manufacturing stage. Additionally, RLC
and ceramic filters are not compatible with CMOS VLSI technology.

vOUT

Figure 7. Second-order switched-capacitor filter.

RC Active Filters
In the 1960s, RC active filters using operational amplifiers,
capacitors, and resistors led to the implementation of highly
selective low-cost filters without inductors (Fig. 6). These filters are known as RC active filters (2). They constituted the
first step toward filter miniaturization. RC active filters were
mass produced in miniaturized form using thin-film and/or
thick-film technology. These filters still required individual
tuning. This was automatically done using computer-controlled laser beams that burn sections of resistor material to
change the resistance and achieve the desired filter response.
Within a short time, RC active filters replaced most inductorbased filters in the audio frequency range.
Monolithic Analog Filters
In the mid 1980s, RC active filters were replaced by fully integrated switched-capacitor filters (3). These use only switches,
operational amplifiers, and capacitors and can be fabricated
in CMOS VLSI technology (see Fig. 7). Switched-capacitor
filters require no tuning and can operate at center frequencies

+
vIN

+
+

vout

(a)

+
iIN

vIN

vOUT

iout

+
+

Figure 6. Second-order RC active filter.

(b)
Figure 8. Second-order OTA-C bandpass filter: (a) voltage mode implementation; (b) current mode implementation.

BANDPASS FILTERS

x(n)
x(n)

T
a0

T
a0

T
a1

221

T
a1

a2

a2
+

y(n)

+
+

+
+
+

y(n)
+

b2

b1
T

(a)

up to a few hundred kilohertz. Starting in the mid 1970s surface acoustic wave (SAW) filtersanother family of filters
were developed to implement filters for center frequencies
spanning from 10 to several hundred megahertz. These filters
are miniaturized filters that also require no tuning. They are
based on the controlled propagation of electromechanical
waves on the surface of a piezoelectric crystal with very small
dimensions. SAW filters are not compatible with CMOS technology. But because of their excellent performance characteristics and low cost, they are currently being used to implement the intermediate frequency filter of most televisions.
Recently, electronically tunable elements in CMOS technology have allowed the integrated circuit implementation of
active filters for center frequencies up to a few tens of megahertz. These filters are compatible with CMOS VLSI technology. Most of these implementations are based on electronically tunable elements called operational transconductance
amplifiers (transconductors or OTAs) and include on-chip automatic tuning circuitry (4). The tuning circuit continuously
(or periodically) monitors the filters response and electronically adjusts the gain of the OTAs to tune the frequency response of the bandpass filter. This family of filters is known
as OTA-C filters (see Fig. 8). They require no tuning and can
be integrated as part of a VLSI system (5). Figure 8a shows
a conventional voltage mode filter, while Fig. 8b shows a
current mode filter where input, output, and intermediate
variables are represented by electrical currents rather than
voltages as it is done in conventional voltage mode filters
(6). In analog signal processing systems, the range above 100
MHz is still based, to a large exent, on passive RLC filters.
At these frequencies, high-quality, small-dimension inductors
are available. A very recent trend for the implementation of
high-frequency high-selectivity integrated analog filters is
based on microelectromechanical (MEM) structures, which
are based on electromechanical resonance. This approach has
shown potential for the implementation of bandpass filters
operating in the radio frequency range and with very high
selectivity factors similar to those achievable with ceramic
and SAW structures. These MEM-based filters, unlike the
SAW filters, are CMOS VLSI compatible.
Digital Filters
Currently, the availability of low-cost digital circuitry in VLSI
systems has made it convenient to replace many traditional

T
(b)

Figure 9. Second-order digital filters (a)

FIR filter; (b) IIR filters.

analog functions by digital ones and to process signals in the

digital domain rather than in analog form. Successful implementation of digital filters for center frequencies up to a few
megahertz, as stand-alone units or as part of a VLSI system
has recently been achieved. Digital filters are fully integrated
filters that are compatible with CMOS technology and require
no tuning (7). Their characteristics ( f0, BW, or Q) can be easily reprogrammed for many different applications. A digital
filter consists basically in various addition, multiplication,
and delay operations applied to an ordered sequence of numbers that represent the digitized values of a signal. These digitized values are obtained by sampling the signal at regular
time intervals (t T, 2T, 3T, . . .) and transforming the sampled values into binary codes. In digital filters, present values x(n) x(nT) and past values x(n 1) x((n 1)T),
x((n 2) x((n 2)T) . . . of both input and output signals
are processed. The steps performed on these digitized values
lead to an output sequence y(n), y(n 1), y(n 2), . . ., which
can be transformed by means of a digital-to-analog converter
into a filtered output signal y(t). A digital filter is, therefore,
an algorithm or sequence of mathematical steps that relates
input and output sequences by means of multiplication, addition, and delay operations. A digital filter is mathematically
characterized by a difference equation. There are two types of
digital filters: finite impulse response (FIR) filters, where the
current value of the output signal y(n) depends only on the
current and past values of the input signal, and infinite impulse response (IIR) filters, where the current value of the
output signal depends also on past values of the output signal. For example, the difference equation of a second-order
FIR filter is expressed by
y(n) = a0 x(nT ) + a1 x(n 1) + a2 x(n 2)

(3)

while the difference equation of a second-order IIR digital filter has the form
y(n) = a0 x(n) + a1 x(n 1) + a2 x(n 2)
b1 y(n 1) b2 y(n 2)

(4)

where a0, a1, a2, b1, and b2 are multiplying coefficients; x(n)
and y(n), stand for x(t nT) and y(t nT), are the current
values of the input and output signals; and x(n 1), x(n

222

BAND-STOP FILTERS

2), y(n 1), and y(n 2) correspond to the two previous values of the input and output signals, respectively. The values
of the multiplying coefficients and the sampling frequency,
f s 1/T, determine the selectivity and center frequency of the
digital filter and can be easily reprogrammed. Figures 9(a, b)
illustrate the block diagram of second-order FIR and IIR filters, respectively.
High-speed digital filters can be implemented using special-purpose VLSI hardware in the form of digital signal processors (6) or as relatively low-speed filters using software in
general-purpose digital systems such as computers or microprocessors.
BIBLIOGRAPHY
1. A. B. Williams and F. J. Taylor, Electronic Filter Design Handbook:
LC Active and Digital Filters, New York: McGraw-Hill, 1988.
2. M. E. Van Valkenburg, Analog Filter Design, Forth Worth, TX:
Holt, Reinhart and Winston, 1982.
3. R. Schaumann, M. S. Ghausi, and K. R. Laker, Design of Analog
Filters: Passive, Active RC and Switched Capacitors, Englewood
Cliffs, NJ: Prentice-Hall, 1990.
4. J. Silva-Martinez, M. Steyaert, and W. Sansen, High Performance
CMOS Continuous-time Filters, Norwell, MA: Kluwer Academic
Publishers, 1995.
5. Y. P. Tsividis and J. O. Voorman, Integrated Continuous Time Filters: Principles Design and Applications, Piscataway NJ: IEEE
Press, 1992.
6. J. Ramirez-Angulo, E. Sanchez-Sinencio, and M. Robinson, Current mode continuous time filters: two design approaches. IEEE
Trans. Circuits Syst., 39: 337341, 1992.
7. R. Higgins, Digital Signal Processing in VLSI, Englewood Cliffs,
NJ: Prentice-Hall, 1990.

JAIME RAMIREZ-ANGULO
New Mexico State University

BAND-REJECT FILTERS. See BAND-STOP FILTERS.

BAND-STOP FILTERS

Atternuation (dB)

222

As

Ap
1
Normalized frequency

Figure 2. Normalized low-pass requirements.

at least As dB. In the passbands (below f 1 Hz and above f 2

Hz), the maximum attenuation is Ap dB. The bands from f 1
to f 3 and from f 4 to f 2 are called the transition bands. The
filter requirement is said to be geometrically symmetrical if
f 1 f 2 f 3 f 4.
An approach to designing a circuit (a band-stop filter) with
a frequency response that satisfies the band-stop requirements shown in Fig. 1 is described below. It consists of two
steps: the approximation of the requirements by a transfer
function, and the synthesis of the transfer function.
In the approximation part of the design process, it is desirable to find a transfer function with a frequency response that
satisfies the band-stop requirements. To find that transfer
function, first convert the band-stop requirements into the
normalized low-pass requirements. For the case that the
band-stop requirements are symmetrical, the corresponding
normalized low-pass requirements are shown in Fig. 2. The
normalized passband frequency Fp 1 and the passband attenuation is Ap dB. The normalized stopband frequency is
Fs =

f2 f1
f4 f3

and the stopband attenuation is As dB.

With such low-pass requirements, we can obtain the corresponding low-pass transfer function TLP(s). (See LOW-PASS FILTERS for more information about how to obtain the transfer
function.) The band-stop filter transfer function TBS(s) is obtained by making the transformation

BAND-STOP FILTERS
A band-stop filter (also known as band-reject, band-elimination, or notch filter) suppresses a band of frequencies of a signal, leaving intact the low- and high-frequency bands. A
band-stop filter specification can be expressed as shown in
Fig. 1. In the stopband from f 3 Hz to f 4 Hz, the attenuation is

TBS (s) =

TLP (s)

s= 2 Bs
s + (2 f ) 2
0

where B is the bandwidth of the band-stop filter defined as

Atternuation (dB)

B = 2 ( f 2 f 1 )
As

and f 0 is the center frequency of the band-stop requirement

defined as
f0 =

Ap

f1 f2 =

f3 f4

Ap
f1

f3

f4

f2

Frequency (Hz)
Figure 1. Band-stop filter specification.

To use this method when the requirement is not symmetrical, for the case that f 1 f 2 f 3 f 4, we form a more stringent
requirement by either decreasing f 2 or increasing f 4, so that
the symmetrical condition is met. The band-stop transfer
function that satisfies the new requirements must also satisfy

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

BATCH PROCESSING IN COMPUTERS

the original requirements. In case f 1 f 2 f 3 f 4, we either increase f 1 or decrease f 3 and then apply the same procedure.
A simple example is provided to illustrate this concept. For
the band-stop requirements As 25 dB, Ap 3.01 dB, f 1 1
kHz, f 2 100 kHz, f 3 8 kHz, and f 4 12.5 kHz; the corresponding normalized low-pass requirements are: As 25 dB,
Ap 3.01 dB, Fp 1, and Fs 22. Choosing a single-pole
Butterworth approximation, the low-pass transfer function
for the normalized low-pass requirements is
TLP (s) =

1
s+1

TBS (s) =

1
S+1

S= 2 2 (10010 3110 )s 3
s + (2 10010 ) (2 110 )

which simplifies to
TBS (s) =

Compare with Eq. (1),

R12
,
R11 R21 R31C1C2
1
1
1
+
,
b2 =
b1 =
R31C1
R32C1
R22 R31C1C2

a1 = 0,

s2 + 3.948 109
s2 + 6.220 105 s + 3.948 109

Note that the single-pole low-pass function has been transformed to a two-pole band-stop function. The above band-stop
transfer function is in the so called biquadratic form, which
is an expression of the form
s2 + a 1 + a 2
s2 + b 1 s + b 2

a2 =

Choose C1 C2 1, R12 /R11 K, R31 R32. Solving for the

other values,
R21 =

which meets the stopband requirements easily. The band-stop

transfer function is obtained by the transformation

223

Kb1
,
2a2

R22 =

b1
,
2b2

R31 =

2
b1

The impedance scaling method can be used to scale the values

of R and C into the practical ranges. In general, a higherorder band-stop transfer function can be factorized into a
product of biquadratic functions. Each of the biquadratic
function can be synthesized by using the Bainter or other circuits. By cascading all the circuits together, the band-stop filter is realized.
BIBLIOGRAPHY
1. J. J. Friend et al., STAR, An active filter biquad section, IEEE
Trans. Circuits Syst., CAS-22: 115121, 1975.
2. S. A. Boctor, Single amplifier functionally tunable low-pass notch
filter, IEEE Trans. Circuits Syst., CAS-22: 875881, 1975.

(1)

3. G. Daryanani, Principles of Active Network Synthesis and Design,

New York: Wiley, 1976.

There are a number of ways to synthesize and biquadratic

function as an active network, such as the Friend biquad circuit (1,5), the Boctor circuit (2), and the summing four-amplifier biquad circuit (3,5). The Friend or Boctor circuit uses one
operational amplifier. The summing four-amplifier biquad circuit is much easier to tune. When a1 0, the Bainter circuit
can be used. The Bainter circuit (4) is shown in Fig. 3. For
higher performance circuits, see Ref. 5 for the description of
different band-stop circuit topologies.
The transfer function is

4. J. R. Bainter, Active filter has stable notch and response can be

regulated, Electronics, 115117, Oct. 1975.

R12
s2 +
Vout (s)
R11 R21 R31C1C2

1

=
1
1
Vin (s)
s2 +
+
s+
R31C1
R32C1
R22 R31C1C2

5. G. Moschytz and P. Horn, Active Filter Design Handbook, New

York: Wiley, 1981.

CHIU H. CHOI
University of North Florida

BANDWIDTH EFFICIENCY. See MODULATION ANALYSIS

FORMULA.

BANG-BANG CONTROL. See NONLINEAR CONTROL SYSTEMS, ANALYTICAL METHODS.

BANK BRANCH AUTOMATION. See BRANCH AUTOMATION.

BARCODES, TWO-DIMENSIONAL CODES, AND

SCANNING EQUIPMENT. See MARK SCANNING

R22
R12
R11
Vin

EQUIPMENT.

C2
R21

BARE DIE PRODUCTS. See KNOWN GOOD DIE TECHNOLOGY.

R31
+

C1

R32

Figure 3. Bainter circuit.

Vout

BARIUM TITANATE MAGNETORESISTANCE. See

MAGNETORESISTANCE.

BATCHED I/O. See BATCH PROCESSING IN COMPUTERS.

454

BIPOLAR AND MOS LOGIC CIRCUITS

logic functions, which in turn can be interconnected to achieve

more complex arithmetic or control operations.
BIPOLAR LOGIC CIRCUITS
Bipolar junction transistors (BJTs) along with resistors and
diodes can be used to create electronic circuits that perform
Boolean logic functions. Bipolar refers to transistors that
have two polarities of charge carriers inside: electrons and
holes. These were the first transistors developed commercially, starting in 1949. Junctions of p-type and n-type semiconductors were formed from silicon with small amounts of
impurities to produce the BJT structure. Two types of BJTs
are possible: pnp and npn, which refer to the arrangement
and types of the semiconductor junctions.
Historical Background

BIPOLAR AND MOS LOGIC CIRCUITS

Logic is the science that deals with the principles of reasoning. Reasoning can be either valid or faulty, and a statement
can be either true or false. In electronic circuits, this translates into a device being on or off or an output voltage being
high or low. The work of Claude Shannon, based on the earlier theoretical work of George Boole, established an algebra
of logic. Boolean algebra describes logical operations on binary state variables such as and, or, and exclusive or, as well
as the invert (not) function. Electronic circuits, defined by the
Websters New Collegiate Dictionary, as an assemblage of
electronic components: hookup, implement each of the basic

The first bipolar logic circuits were implementation with discrete transistors on small circuit boards or as hybrids. In
1956, the first integrated circuits (ICs) were designed, which
consisted of resistors, diodes, and bipolar transistors, all interconnected on chip by metal lines. Bipolar logic ICs have
been designed in several styles or families, some of which are
obsolete today. The first logic families were resistor
transistor logic (RTL) and diodetransistor logic (DTL).
Later, as the cost of adding transistors to a circuit became
secondary, the number of active devices (transistors) was increased to replace the resistors and diodes.
Transistortransistor logic (TTL) was introduced in the
early 1960s and was quickly accepted around the world, becoming the most popular logic family. Most mainframe computers of the 1970s were designed based on TTL logic chips,
and only the TTLs density and speed changed significantly
over the course of many years. Later, Schottky barrier diodes
(SBDs) were used to prevent saturation in the bipolar transistors, which reduced power consumption and improved switching speed. Saturation in a BJT describes the condition when
the base-collector junction becomes forward biased and conducts current. Saturated transistors slow down considerably.
TTL used a single 5 V power supply, which became the de
facto standard for logic circuits. Only recently has this begun
to change to 3.3 V. Digital circuits based on TTL are still
widely sold today. TTL held the largest market share until
the early 1980s, when complementary metaloxidesilicon
(CMOS) began to overtake it.
For a period of time in the 1970s, integrated injection logic
(IIL), also known as merged transistor logic, was a successful
logic family. It promised the highest speeds and levels of integration. However, the processing complexity and the inferior
speedpower product, compared to modern emitter-coupled
logic (ECL) designs, have relegated IIL technology to historical interest.
ECL, a derivative of current-mode logic (CML), has been
popular for over two decades. It made its first commercial appearance in 1962, introduced by Motorola as MECL1, and
within a few years was capable of 1 to 2 ns propagation delays. In CML, whose name derives from the current steering
realized by differential amplifiers, the transistors do not saturate by design. ECL logic is fairly dense, since several differential amplifiers are stacked on top of each other and share a
single current source. ECL is used in high-speed computers

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

BIPOLAR AND MOS LOGIC CIRCUITS

Vplus

455

Out
Vplus

High output

R2
Out
R1
In

Q1
0.1 V

Low output
0.75 V

In

(such as the Crays), in instrumentation, and in communications. Typical propagation delays for ECL logic today are less
than 100 ps per gate, and the maximum frequency of operation is greater than 10 GHz.
Nonthreshold logic (NTL) is a relatively new nonsaturating logic family that uses common-emitter (CE) stages with
large emitter resistors to prevent saturation. The layouts of
some NTL designs are very small; others have achieved some
of the highest speed and speedpower records.
Bipolar CMOS (BICMOS) was introduced in the middle
1980s as an optimal technology containing both high-speed
and high-density devices. The current drive of bipolar transistors could be used to drive long metal lines or large capacitances, which metaloxidesilicon (MOS) is poor at doing. On
the other hand, CMOS had made it possible to integrate very
large numbers of logic gates, and memory cells, on a single IC
chip, compared to bipolar.
Another new logic family, called current mirror control
logic (CMCL), is claimed to achieve the highest speedpower
product of any technology. It operates at less than 2 V and is
derived from CML by removing the current sources and replacing them with current mirrors.
Bipolar Logic Circuits Operation
The most fundamental property of logic circuits is that their
transfer characteristics (e.g., voltage transfer function from
input to output) are such that they clamp at the output. Their
gain is high enough so that a minimum input voltage swing
will causes the output to swing fully on or off. This limiting
action allows a large number of logic circuits to function simultaneously, for example in a microprocessor, without suffering any errors. The amount of signal degradation that can
be tolerated at the input of a logic circuit is called its noise
immunity, and it is proportional to the circuit gain.

Figure 1. Simple inverter circuit and voltage transfer

curve.

Figure 1 shows a simple inverter circuit consisting of a

common emitter (CE) transistor with its load resistor R2, and
a current limiting resistor R1 at its input. Also shown is a
simplified voltage transfer curve. When the input voltage increases from zero to the normal on voltage of the base-emitter
junction (Vbe, 0.75 V), the transistor begins to turn on and the
output level begins to drop. The low output voltage will be
reached when the transistor saturates, resulting in a level
close to zero (about 0.1 V or less). This voltage is lower than
what is needed to turn on the next stage, and therefore it is
a logic zero.
A simple RTL circuit is shown in Fig. 2 as well as curves
indicating changes in time at the inputs and the corresponding output change. No limiting resistors are shown for the
inputs A and B, although these are normally necessary; they
serve the secondary purpose of preventing one transistor from
taking all the current coming from the power supply. RTL is
a saturating logic family, and its transistors take longer to
come out of saturation (turn off) than to go into saturation.
Therefore its rising output voltage occurs with more delay
than its falling voltage.
In Fig. 3, we show a two-input DTL nand gate. The input
threshold of this circuit is equal to two diode drops (2Vbe),
since the input voltage goes up one diode and down three diodes. Only when both inputs are above the turn-on threshold
does the output go low, corresponding to the nand function.
The advantage of DTL over RTL is that the inputs do not
draw any current when they are high, because of the reverse
bias at their diodes. The resistor at the base of the output
transistor speeds up its turnoff.

Vplus
Vplus

Vplus

Out

Out
A

B
Out

Out = A Nor B
Figure 2. Resistortransistor logic (RTL) nor gate. Timing waveforms show Boolean relationship.

Figure 3. Diodetransistor logic (DTL) nand gate. Output is high

for all input combinations except A 1 and B 1.

456

BIPOLAR AND MOS LOGIC CIRCUITS

Vplus

GND

R1

R2

R2
Q6

Q4

R1

Q7

Q5
A

R5

Q1
Q2

Out
Q6

Out

Q3

Outn

Q4

BN
VCS

R3

Q2

AN

A
B

Q1

R4

Q5

R4

R5

R3

Q3
VEE
Figure 4. Schottky transistortransistor logic (TTL) nand gate with
totem-pole output and squaring circuit.

CML
ECL

The Schottky TTL nand gate shown in Fig. 4 has similar

operation to the DTL implementation except that the input
diodes have been merged into two emitters at the input transistor. The output stage is composed of a totem-pole configuration driven by a phase-splitter transistor (Q2). The output
is pulled up by a Darlington connect pair. Schottky diodes
connected internally across basecollector junctions prevent
those transistors that might saturate from doing so. The additional two resistors and a transistor circuit connected at the
base of the output transistor (Q3, R3, and R4) are known as a
squaring circuit, and it is used to sharpen the voltage transfer
function. The TTL output levels are particularly troublesome,
since they require driving large capacitive loads and uncontrolled (impedance) transmission lines; they must also source
and sink current in a historically asymmetric way.
IIL circuits are similar to RTL circuits except that all resistors are replaced by pnp current sources, realizing an alltransistor design style. Figure 5 shows that the current
sources are applied to the inputs of transistors and that the
gates consist of the parallel connection of several transistors.

IDC

IDC
IDC

Out

Figure 5. Integrated injection logic (IIL): pnp transistors make up

the current sources. All-transistor design.

Figure 6. Emitter-coupled logic (ECL) and gate with full differential

inputs and outputs. The addition of an emitter follower turns CML
into ECL.

Because CE stages are loaded by current sources, the saturation is light. The pnps are integrated with the npns in a single tub. Multiple emitters on the pnp side further compress
the layout. One shortcoming of IIL was that it required special processes to make npn transistors that could operate upside down, with the collector on top, and also special steps to
make pnp transistors.
ECL/CML circuits are based on the differential amplifier.
Figure 6 shows an ECL and gate consisting of two differential
amplifiers stacked on top of each other. The addition of emitter follower outputs turns a CML circuit into an ECL circuit.
In the figure, the emitter followers are simply loaded by resistors, but current sources are more commonly employed. At
the bottom of the differential amplifiers, transistors Q5 implements a current source that is biased from a common voltage
Vcs. Since the so-called tail current is constant, the amount of
voltage swing developed across load resistors R1 and R2 is
well controlled and saturation prevented. The bases of the differential amplifiers connect to dc levels such that their base
collector junctions do not saturate. There is normally a voltage difference of Vbe (a diode drop) between signals A and AN
and between signals B and BN, so that the emitter of Q1, for
example, makes the collector of Q3 be no lower than the base
of Q3. The and operation is verified by noting that only when
both Q1 and Q3 are on will the current flow into R1, making
the output OUTN low, and OUT high.
Although Fig. 6 shows fully differential inputs and outputs, it is common to use single-ended versions of both. This
requires connecting one side of each differential amplifier to
an appropriate threshold voltage level. These levels are usually generated by the same circuit that provides the bias to
the current sources, and are typically separated from each

BIPOLAR AND MOS LOGIC CIRCUITS

GND

457

Vplus

In

M1
Q1

Q1
D

M2

Q1N

DN

Out

CKN

M3

CK

Q2
M4

VCS

VEE
Figure 7. ECL latch. Outputs latch on CK high.

other by diode drops. The bias circuit is often a bandgap voltage regulator, which is capable of operating with great immunity from temperature and supply voltage variations.
An ECL latch is an interesting circuit that shows some of
the special characteristics of this logic family. Figure 7 shows
that two differential amplifiers are stacked on top of a third,
all three sharing the same current source. When current flows
through the input differential pair, on CKN high, the outputs
Q and QN simply follow the inputs D and DN. When CK selects the current to flow though the differential pair on the
right, it latches to the voltage that was previously presented
at its inputs. This differential pair has its outputs cross-connected to its inputs, and also connected to the collectors of the
input differential pair. The figure also shows emitter followers with constant current source loading.
Figure 8 shows a two-input nonthreshold logic gate. The
NTL transistors do not saturate, since the current demand is
proportional to the input voltage. However, this makes the
transfer function fairly linear, resulting in lower gain and a
soft voltage transfer curve. This is not desirable for logic circuits, but can be alleviated by adding parallel capacitors

Figure 9. Standard BICMOS inverting buffer. All-transistor design

requires no resistors. Bipolar transistors provide high current drive
for large (or unknown) loads.

across the emitter resistors. In NTL the maximum collector

current is predictable, and selected so that the logic voltage
swing does not saturate the next stage. Emitter followers between stages improve interstage loading and the ability to
drive more logic inputs (fanout).
As an example a standard BICMOS inverting buffer,
which can be used to drive large capacitive loads, is shown in
Fig. 9. The two npn transistors in combination can pull up
and pull down larger currents, and faster, than MOS devices
of similar area. The CMOS inverter, M1 and M2, drive the
top npn in opposite phase to the drive presented to the bottom npn. The bottom npn is both buffered and kept out of
saturation by the n-channel MOS (NMOS) device connected
across its base and collectors. The CMOS inverter also drives
a fourth NMOS transistors, M4, that speeds the turnoff of the
bottom bipolar transistor.
An example of a current mirror control logic (CMCL) xor
gate can be seen in Fig. 10. The removal of current sources in

GND

Vplus

AN

QN
B
VREF
Q5

Out

Q6

2 V
QN = A XOR B
Figure 8. Nonthreshold logic (NTL), including speedup capacitor.

Figure 10. Current mirror control logic (CMCL) xor gate.

458

BIPOLAR AND MOS LOGIC CIRCUITS

Table 1.
Parameter
gm /I
1/f
Voffset
Rin
Rb
Switch
Complementary
device
Ft

BJT

MOS

Highest, 1/VT 1/(26 mV)

Best
Very good, exp(Vbe /Vt)
Medium, base current
Yes, limits Fmax
Not ideal
Lateral PNP, 200 MHz

1/(250 mV)
Poor
Poor (surface effects)
Infinite
No
Yes
PMOS, 40% speed

Function of current

Function of Vgs Vt

an ECL circuit allows it to operate from 2 V. As shown, two

levels of logic, corresponding to signals A and AN, and B, are
possible. The differential signals A and AN swing about 0.5 V
and drive the master side of two separate current mirror circuits. When A is high, the current through Q5 is on, while
AN, being low, produces almost no current in Q6. The signal
B is applied against a reference voltage that is regulated
against supply voltage changes.
Comparison of BJT with Other Technologies
At the highest speeds, bipolar logic survives the CMOS onslaught; it also enjoys the advantage of being differential and
semianalog. The reasons why bipolar technology continues to
be so important will become apparent from the comparison
of the advantages and disadvantages of both BJTs and MOS
devices shown in Table 1.
Bipolar transistors have a tremendous (exponential) gain
and high current drive capability, allowing small devices to
develop large gain and to drive loads of considerable size, by
contrast to MOS. In addition, the small offset voltage of bipolar differential pairs is good for logic at small signal swings.
Fully differential signals can have smaller levels, with the
additional benefit of better common-mode signal and noise rejection, resulting in better noise immunity.
Small logic swing (the way to the future for all logic families) can naturally take bipolar logic to lower supply voltages
and higher speeds. Speed and power improve with reduced
voltage swing. In addition, the much lower 1/f frequency corner of BJTs, related to its bulk properties, makes them much
superior in applications where memory effects are detrimental, as in data transmission and test equipment.
Because bipolar logic is built around a lot of the same elements used in analog design (BJTs, resistors, diodes, capacitors, and even inductors), it lends itself nicely to mixed signal
design, combining analog and digital on the same circuit. For
example, some of the key bipolar and BICMOS analog functions, such as analog-to-digital converters, digital-to-analog
converters, phase-locked loops, and disk-drive electronics,
contain a mix of logic circuits.
Concerning GaAs metal semiconductor field effect transistors (MESFETs), all of the above comparisons apply, since
their operation is very similar to that of MOS transistors, except that the higher mobility (at low electric fields) of GaAs
gives it an advantage. GaAs ICs also are manufactured on a
semiinsulating substrate that gives reduced signal loading
and improved crosstalk. However, competing directly with
GaAs logic, SiBJT processes are cheaper, more stable (sta-

tistical corners), better at low temperature, lower in noise for

data transmission (dc-coupled), and nontoxic.
New silicongermanium (SiGe) bipolar technologies are
challenging even the most advanced processes in other materials, since they achieve very high cutoff frequencies (e.g., 75
GHz) and have other improved transistor parameters. Since
1995, the circuit speed performance of SiGe has not only exceeded GaAs MESFETs but almost equaled that of other more
exotic technologies such as HEMT (high electron mobility
transistor) and HBT (heterojunction bipolar transistor). Finally, silicon-on-insulator and higher resistivity substrates
will remove the last obstacle in the competition for the highspeed and mixed-signal markets, namely, the substrates capacitance, loss, and cross-talk.
CMOS LOGIC CIRCUITS
Although bipolar processes are used for many high-speed designs, CMOS has become the dominant technology for most of
todays digital ICs. Lower power and higher integration densities are two reasons for the success of the CMOS process.
Field effect transistors (FETs) were conceived as early as
1925, more than two decades before the invention of the bipolar transistor. However, development of fabrication processes
to support the manufacture of FETs did not occur until the
1960s. The earliest MOS processes were based on single transistor types. The CMOS fabrication process allows both types
of MOSFETs, p-channel and n-channel, to be fabricated together. Schematic symbols for an n-channel MOS transistor
and a p-channel MOS (PMOS) transistor are shown in Fig.
11. Circuits consisting of NMOS and PMOS transistors can
be used to perform boolean logic functions.
Classical CMOS Gates
In order to understand how CMOS logic circuits behave, a
model for the operation of an individual FET is needed. The
simplest model of an NMOS transistor is that of a switch that
closes when the logic level on the gate is high, passing the
logical state on the input to the output. With a low on the
gate, the switch modeling the NMOS transistor is open. For
modeling a PMOS transistor, the switch is open when the
gate is driven with a high and closed when the gate is driven
with a low. Boolean logic functions such as nand, nor, and
invert can be easily implemented by networks of PMOS and
NMOS transistors as shown in Fig. 12.
Series connections of transistors perform a logical and operation, whereas parallel connections perform a logical or operation. For the nand gate in Fig. 12, two NMOS transistors
are in series between the output (y) and ground (the source of
a low logic level). When both x1 and x2 are asserted high, the
output is pulled to ground, thus passing a low voltage level to

Gate

Input

Gate

Output
NMOS

Input

Output
PMOS

Figure 11. MOS transistor schematics. As shown, the input is arbitrarily connected to the transistor source, and the output to the drain.
The gate controls the switch action.

BIPOLAR AND MOS LOGIC CIRCUITS

x1 x2 y
x1

x1

x2

0
0
1
1

y
x2
x

x1

x1

invert

x2

1
0
0
0

x1

Figure 13. Nor truth table and Karnaugh map with groupings for
both the PMOS network and the NMOS network.

0
1
0
1

x2

459

x2

2-input nor

2-input nand

Figure 12. Basic logic gates are constructed by parallel and series
combinations of NMOS and PMOS transistors.

the output. The two PMOS transistors are connected in parallel between the high-voltage supply and the output. When either x1 is low or x2 is low, a path is closed between the high
supply and the output, passing a high voltage level to the
output. The Boolean operation of a nand function is thus performed.
To understand why PMOS transistors are used to pass
high levels to the output while NMOS transistors are used to
pass low levels, the switch model must be modified to take
account of the threshold voltage. The switch modeling an
NMOS transistor is actually closed only when the difference
between the voltage on the gate, Vg, and the voltage on the
source, Vs, is greater than a threshold voltage, Vt. If an NMOS
transistor is used to pass a low level, then Vg is always
greater than Vt and the switch is always closed. If, however,
an NMOS transistor were used to pass a high level, the output would rise until the voltage was Vt less than the gate
voltage, at which point the switch would open and the output
would cease to rise. NMOS transistors will pass good 0s, but
degrade the voltage level of a 1. PMOS transistors, by similar
arguments, pass good 1s, but poor 0s.
The operation of digital CMOS circuits can be described by
Boolean algebra. The normal boolean expression describing
the nand function is given by y x1x2, which conveys that
both x1 and x2 must be high before y 0. An alternative Boolean expression for the nand function is y x1 x2, which
implies that if either x1 or x2 is low, then y 1. Both concepts
are needed to describe the CMOS nand gate fully.
Let y x(0) be read as y is equal to x passing a 0, meaning that when x 1, a 0 is passed to the output. Also, let
y x(1) be y is equal to x passing a 1, meaning that when
x 1, a 1 is passed to the output. The CMOS nand function
can then be fully described by the following expression:
y = x1 x2 (0) + x1 (1) + x2 (1)

(1)

This can be read as y is equal to x1x2 passing a 0 or x1 passing

a 1 or x2 passing a 1. This notation conveys the meaning that
when x1 is high and x2 is high, the output is low, and if either
x1 or x2 is low, the output is high. The first term of Eq. (1)
implies the series connection to ground of two NMOS transistors. The second and third terms imply a parallel connection
of PMOS transistors.
The concept of passing 1s and 0s can be used to derive
other classical CMOS gates. The derivation of the two-input
nor gate will be used as an example. The information in a

truth table describing the logical function of a two-input nor

gate can be entered into a Karnaugh map and the 1s and 0s
can be grouped together as shown in Fig. 13. These groupings
imply that a 1 must be passed to the output under the input
condition x1x2 and that a 0 must be passed to the output when
x1 1 or when x2 1. Using the pass notation introduced,
y = x1 x2 (1) + x1 (0) + x2 (0)

(2)

Equation (2) describes the network of MOS transistors

needed. The first term is a logical and operation. This implies
a series path between the output and the high supply, since
both x1 and x2 must be low to pass a 1 to the output. Since pchannel transistors pass good 1 levels and the switch model
closes when the gate is driven by a low level, a pair of series
PMOS gates are used. The next two terms imply parallel
paths passing 0s when x1 or x2 is high. Parallel n-channel
transistors are therefore used. Figure 12 shows the classical
CMOS nor gate with series PMOS transistors between the
output and the high supply and parallel NMOS transistors
between the output and the low supply.
Digital MOS ICs can be designed using exclusively nand,
nor, and invert gates; however, the cost of an IC is proportional to the size of the die, and this design methodology
might not result in the most economical solution. Several
logic families have been developed to reduce the number of
transistors required to implement a given Boolean logic expression. As an example, the implementation of the Boolean
function described by the truth table in Fig. 14 will be described for several static logic families. Using basic logic
gates, two two-input nand gates and one three-input nand
gate would be needed to implement the design example, requiring a total of 14 transistors.

x1 x2 x3 x4 y
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1

x 1x 2
x 3x 4
00 01 11 10
00

01

11

10

Figure 14. Design example used for comparison of several CMOS

logic families.

460

x1

BIPOLAR AND MOS LOGIC CIRCUITS

x3

x4

x2

x2
y

x1

x1

x2

x2

x2

x2

x3

x4

x3

x4

Complex gate

pseudo-NMOS gate

Figure 15. Complex gate implementation using fully complementary

networks and a pseudo-NMOS approach.

A complex gate with just one node can perform the same
function. Using a Karnaugh map, the required PMOS and
NMOS networks to implement a complex CMOS gate can be
derived in the same manner that the nor gate was derived.
For the Karnaugh map groupings shown in Figure 14,
y = x1 [x2 x3 (0) + x2 x4 (0)] + x1 (1) + x2 x3 (1) + x2 x4 (1)

(3)

Using NMOS transistors to pass 0s and PMOS transistors to

pass 1s, and remembering that a PMOS switch is closed
when driven with a low logic level, we obtain the 10-transistor solution shown on the left in Fig. 15. This reduction in
transistor count motivates cost-conscious circuit designers to
find alternative implementations, especially for logic blocks
that will be placed many times on a digital IC.

resistor representing the enhancement NMOS transistors in

the pulldown path. The value of the resistance of a FET is
inversely proportional to the width of the transistor. The voltage value representing a low logic level could be controlled by
the ratio of the widths of the depletion and enhancement
NMOS transistors. The enhancement NMOS transistors were
sized to be of much smaller resistance than the depletion
transistor setting a low voltage for the low logic level.
This NMOS structure can be imitated in todays CMOS
process, by replacing the depletion pullup transistor with either a PMOS transistor whose gate is tied to a logic low
(pseudo-NMOS), or an NMOS transistor whose gate is driven
with a bias voltage that is greater than the supply voltage
plus Vt (modified pseudo-NMOS). The pseudo-NMOS structure is shown in the right half of Fig. 15 and requires just six
transistors. A modified pseudo-NMOS structure would also
require only six transistors.
There is a cost associated with the pseudo-NMOS approaches. When y 0, a current flows between the supply
voltage and ground. This current flow is minimized by making the pullup resistance just low enough to maintain the desired speed of operation for the circuit, but still represents
enough current to be the reason that CMOS processes replaced the NMOS and PMOS processes of the 1970s. Although entire chip designs have been based on this logic style,
it is normally used in conjunction with dynamic techniques,
which will be discussed in a following section.
Pass Gates
The concept of passing 1s and 0s helps to understand the
operation of static CMOS gates. The limitation of passing only
0s and 1s requires the use of more transistors than necessary
for many Boolean functions. This constraint is lifted for pass
transistor gates. The first grouping, in the Karnaugh map of
Fig. 16, is x1x2, passing the variable x4. The second is x1x2,
passing x3. The resulting equation is
y = x1 [ x2 (x4 ) + x2 (x3 )] + x1 (1)

Pseudo-NMOS Gates
Another alternative approach reaches back into history to reduce the transistor count even further. In the 1970s, MOS
processes were dominantly single-transistor processes. An
NMOS processes had typically two types of n-channel FETs:
an enhancement transistor similar to the NMOS transistor
available in todays CMOS process, and a depletion transistor.
If the gate and source of the depletion device were tied together (self-sourced), the transistor could be modeled as a resistor. The model for the NMOS enhancement transistor also
need to be expanded to include the concept of resistance.
When Vg Vs Vt and the drain voltage Vd is such that
Vd Vs Vg Vs Vt, then the closed switch modeling the
NMOS transistor has the property of resistance.
In the NMOS process, Boolean logic was implemented with
an NMOS network identical to the one shown in Fig. 15,
while the PMOS network was replaced by a single, selfsourced depletion transistor connected to the high supply.
When the input state was such that y 1, the NMOS networks path to ground would be broken and the output would
charge to the high supply through the resistance of the depletion NMOS transistor. When the inputs were such that y
0, then the output would be a voltage division between the
resistor representing the depletion transistor pullup and the

(4)

The four-transistor circuit shown on the right side of Fig. 16

implements the desired function. Since the variables x3 and
x4 can be either 1s or 0s, the voltage level of 1s will be degraded at y and must therefore be restored. One approach for
passing good levels would be to use an NMOS and a PMOS
transistor in parallel (a transmission gate) whenever a variable is passed. The NMOS device would pass a good 0, while
the PMOS transistor would pass a good 1. If transmission
gates were used, seven transistors would be required. The
second approach would be to actively restore the output level
at the output of the pass network.
x 1x 2
x 3x 4
00 01 11 10
00

01

11

10

x2

x3

x2

x1
y

x4

Figure 16. Pass transistor design eliminates the constraint of passing only 1s and 0s.

BIPOLAR AND MOS LOGIC CIRCUITS

CK

461

CK
y

x1
y
x2

x2

x3

x4

CK

Dynamic logic gate

x1

x2

x3

x3

x4

CK

Domino logic gate

The logic of this design example is to perform the function

of a synchronous set and load/hold when used to drive the d
input of a masterslave flip-flop. Since an array of 100 of
these circuits was needed on an actual design and since active
level restoration of the 1 level was inherent in the master
section of the flip-flop, the pass transistor design shown in
Fig. 16 was used, saving 1000 transistors in comparison with
the nand-gate approach.
Dynamic Gates
Unlike static logic, in which there is a path between the output and either the high supply or ground for every input
state, dynamic logic relies on storage of charge on the capacitive load seen at the output to maintain the logic level for
periods of time. The time base for storage is normally established by a clock. The output of dynamic logic is also valid
only during a portion of the charge storage time. A dynamic
logic gate that implements the design example of Fig. 14 is
shown on the left side of Fig. 17. When the clock CK is low, y
is precharged to a 1 level. When the clock transitions high,
the NMOS transistor at the bottom of the NMOS network
evaluates the state of the inputs and conditionally discharges
the output to ground. If there is no path to ground through
the NMOS array, the output remains high. This high voltage
level is stored on the capacitance seen at the output node.
Over time this level will degrade due to parasitic leakage
paths. This leakage establishes a lower limit on the rate of
the clock signal. This limit could be eliminated by adding a
PMOS transistor, like the pseudo-NMOS pullup device of Fig.
15, with a resistance just low enough to overcome the effects
of leakage. A total of seven transistors are required to implement the design example.
There are two design considerations for dynamic logic
gates. The output of the dynamic gate of Fig. 17 is floating or
at a high impedance when storing a high level. The logic level
is stored in the form of charge on the capacitance of the node.
This floating node is susceptible to charge sharing introduced
by crosstalk from adjacent lines. Charge sharing occurs between two physically adjacent conductors due to the parasitic
capacitance formed by the node metals separated by an the
insulating layer. When an adjacent node voltage changes,
charge is coupled through this parasitice capacitance to the
otherwise unrelated node. Charge can be moved off of the

Figure 17. Dynamic logic structures. A

basic precharge evaluate structure (left) is
compared with a domino logic structure.

node by charge sharing, reducing the voltage level of the

stored logic 1. Charge sharing across the gate capacitance of
transistors within the NMOS pulldown structure also can degrade the output 1 level if the inputs transition while clock is
high. The second consideration occurs when one dynamic gate
drives the input of a second dynamic gate. A race exists between when the clock transitions high and the first dynamic
gate evaluates low. This race occurs because both outputs are
precharged high when the clock is low and evaluate when the
clock is high. With the inputs to the NMOS transistors of the
second stage high due to the precharge of the first stage,
the second node begins to fall even though the first stage might
transition low, requiring the second stage to remain high.
Due to the charge sharing and inherent race condition of
dynamic gates, they are not generally used for random logic.
When the NMOS and PMOS arrays for implementing a desired function are large, the effort required to ensure proper
operation is worthwhile. Dynamic logic is often used, for example, to implement the address decode logic of a memory
circuit.
In order to overcome the race condition and external crosstalk susceptability of dynamic logic, the domino logic configuration shown on the right side of Fig. 17 can be used. The
inverter on the output node isolates the high-impedance node
from charge-sharing effects external to the node. Also, since
precharging the internal node to a 1 sets the output to a 0,
no race exists between cascaded stages. The first state evaluates, and if the input transitions, it may cause the second to
transition, and so on in a domino effect. The NMOS network
is simply designed to produce the inverse of the function desired at the output of the inverter.
Future Challenges for CMOS
The new set of constraints presented by todays submicrometer CMOS processes are opening for debate again design
questions long thought answered. MOS processing technologies underwent a evaluation in the past. NMOS, with inherent speed advantages, replaced PMOS as the dominant MOS
technology in the early to mid 1970s. CMOS, with inherent
power advantages, replaced NMOS processes in the late
1970s and early 1980s. The speed and density of the circuits
being designed at that time had risen to the point where
packaging technology could no longer deal with the power lev-

462

BIPOLAR MEMORY CIRCUITS

els generated by NMOS designs. Today we are faced once

again with the same power dilemma. Architecture, logic, circuit, and fabrication techniques are evolving to reduce power
while maintaining or increasing performance. As the submicrometer geometries continue to shrink, previous assumptions about the choice of design methodologies and families
are no longer valid. For instance, the area of a circuit is now
a much stronger function of interconnect than transistor
count. Off-state leakage is no longer negligible and can in the
case of large memory cores actually dominate as the main
component of static power. Switching power, the power associated with charging and discharging capacitive loads, increases with capacitance. This is allowing the design tradeoff
between capacitance and static power to be reevaluated. As
with most engineering disciplines, VLSI logic design will continue to evolve.
BIBLIOGRAPHY
A. R. Alvarez, BICMOS Technology and Applications, Norwell, MA:
Kluwer Academic, 1989.
A. Barna, VHSIC: Technologies and Tradeoffs, New York: Wiley-Interscience, 1981.
M. I. Elmasry, Digital Bipolar Integrated Circuits, New York: WileyInterscience, 1983.
S. H. K. Embabi, A. Bellaouar, and M. I. Elmasry, Digital BICMOS
Integrated Circuit Design, Norwell, MA: Kluwer Academic, 1993.
E. D. Fabricius, Introduction to VLSI Design, New York: McGrawHill, 1990.
L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI
Circuits, Reading, MA: Addison-Wesley, 1985.
L. J. Herbst, Monolithic Integrated Circuits, Oxford: Clarendon
Press, 1985.
Integrated Circuit Engineering Corporation, STATUS 1997, Scottsdale, AZ: ICE, 1997.
K. Kishine, Y. Kobayashi, and H. Ichino, A high-speed, low-power
bipolar digital circuit for Gb/s LSIs: Current mirror control logic,
IEEE J. Solid-State Circuits 32:, 215221, 1997.
P. L. Mathews, Choosing and Using ECL, London: Granada Publishing, 1983.
R. Meyer, Advanced Integrated Circuits for Communications, Course
ECE242 Notes, Berkeley: Univ. of California 1994.
J. M. Rabaey, Digital Integrated Circuits: A Design Perspective, Upper
Saddle River, NJ: Prentice-Hall, 1996.
H. Rein and M. Moller, Design considerations for very-high-speed Sibipolar ICs operating up to 50 Gb/s, IEEE J. Solid-State Circuits,
31: 10761090, 1996.
M. I. Rocchi (ed.), High Speed Digital IC Technologies, Norwood, MA:
Artech House, 1990.
M. Shoji, CMOS Digital Circuit Technology, Englewood Cliffs, NJ:
Prentice-Hall, 1988.
N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design:
A Systems Perspective, 2nd ed. Reading, MA: Addision-Wesley,
1993.
S. Wolf, Silicon Processing for the VLSI Era: Volume 2, Sunset Beach,
CA: Lattice Press, 1990.

GERMAN GUTIERREZ
Silicon Wave, Inc.

STERLING WHITAKER
NASA Institute for Advanced
Microelectronics

BIPOLAR LOGIC CIRCUITS. See BICMOS LOGIC CIRCUITS.

BOOTSTRAP CIRCUITS

BOOTSTRAP CIRCUITS

Vdd

The word bootstrapping is defined in Websters New World College Dictionary (1) as to lift (or raise) oneself by the (or ones
own) bootstraps to achieve success by ones own unaided efforts. A similar phenomenon may occur in some electrical
and electronic circuits. A circuit can sense a voltage change
at one terminal of a two-terminal element and cause an equal
change in the voltage of the other terminal (2). Thus the voltage drop across that element remains almost unchanged. For
example, while terminal a of the device shown in Fig. 1 may
have higher potential than terminal b (by V volts), if the voltage or potential at b is somehow raised, a potential change at
a follows that at node b. This is referred to as bootstrapping
since it is similar to a person trying to lift himself or herself
off the ground by pulling his or her bootstraps. In actual circuits where bootstrapping is used, the voltage across the element may change.
The bootstrapping technique has been used for both digital
and analog circuits. Some examples of each are presented
next.

M1
Cpar

(Va)

M2
(Vo)

Cboot
M3

Input

Cout

(Vin)
Figure 2. Bootstrapped NMOS inverter (4). The bootstrapping is
achieved by Cboot.

Vdd

BOOTSTRAPPING IN DIGITAL CIRCUITS

Bootstrapping has been used in digital circuits (CMOS and
BiCMOS) mainly to increase the voltage swing of the logic
gates. In such circuits, bootstrapping is achieved by using capacitive coupling (3), as in the NMOS bootstrapped inverter
shown in Fig. 2 (4).
In Fig. 2, M1 maintains the voltage of node a at Vdd VT
(where VT is the threshold voltage of the NMOS transistor).
If the input is grounded, M3 is turned off, whereas M2 is
turned on and thus provides current to charge Cout. This
causes the output voltage Vo to rise toward Vdd. If Cboot is ignored temporarily, M2 should turn off as soon as Vo Vdd
2VT. However, due to the capacitor coupling provided by Cboot,
the voltage of the gate of M2 will follow the rising output. In
other words, node a is bootstrapped. Notice that M1 cuts off
once Va exceeds Vdd VT; thus node a can be assumed floating
(isolated from Vdd). This allows the voltage Va to rise above
Vdd until it reaches Vdd VT, and as a result Vo can be pulled
up to Vdd. This is the main advantage of using bootstrapping
in the case of the NMOS inverter. To achieve proper bootstrapping, Cboot must satisfy the following condition (4):
Cboot

531

Mf1
Mp1 Cboot

Vin

Q1

I2

Mb1

Vo

V0
I3

VDD

CL

Mf2
Mp2
I1

Q2
Mb2

Figure 3. A bootstrapped BiCOMOS inverter (5).

2VT
Cpar
Vdd 2VT VOL

a
Boot
strapping
circuit

+
V

Voltage
Va
V

Vb

V
Time

+
VB

Io

+
V

Ro

b
Current source/sink

Figure 1. Bootstrapping in electronic circuits: The bootstrapping circuit forces the voltage at node a to track any voltage changes occurring at node b.

Figure 4. Bootstrapping to increase the output resistance of a current source.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

532

BOUNDARY-SCAN TESTING

I2
Q2
+
VEE2

3. R. E. Joynsan et al., Eliminating threshold losses in MOS circuits

by bootstrapping using varacter coupling, IEEE J. Solid-State
Circuits, SC-7: 217224, 1972.

(va)

+
Q1

+
VBB1

4. L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of

VLSI Circuits, Reading, MA: Addison-Wesley, 1985.

5. S. H. K. Embabi, A. Bellaoucer, and K. I. Islam, A bootstrapped

bipolar CMOS (B2CMOS) logic gate for low voltage applications,
IEEE J. Solid-State Circuits, 30: 4753, 1995.

6. R. L. Gerzer, P. E. Allen, and N. R. Strader, VLSI Design Techniques for Analog and Digital Circuits, New York: McGraw-Hill,
1990.

I1
b (vb)
R

SHERIF H. K. EMBABI
Figure 5. A bipolar bootstrapped current source. Any change in va
will cause a similar change in vb, such that the voltage across Q1
remains constant.

Texas A&M University

BOUNDARIES, SEMICONDUCTOR-INSULATOR.
See SEMICONDUCTOR-INSULATOR BOUNDARIES.
where Cpar is the parasitic capacitor at node a and VOL is the
low logical level of the NMOS inverter. It is important to notice that the bootstrapping due to capacative coupling is valid
for a finite period of time. The charge stored on the boot node
(node a) will leak off as time passes, and the voltage at node
a will drift back to its nominal value Vdd VT; Vo will consequently drift to Vdd 2VT.
Bootstrapping has also been used for BiCMOS digital inverters to force the output logic high levels to approach Vdd
(similar to NMOS). One example of such circuits is shown in
Fig. 3 (5).

BOOTSTRAPPING FOR ANALOG CIRCUITS

Bootstrapping techniques can be effective in analog circuits,
for instance, to increase the output resistance of a current
source (2,6). This can be explained conceptually using Fig. 4.
The bootstrapping circuit senses any change in V (the voltage
of node a) and generates an equal change at node b so that
the voltage across the current source is almost constant. This
implies that the output resistance of the current source remains high. It can be shown that output resistance R0 increases by a factor 1/1 , where is the small signal voltage gain (2) where va is the small signal voltage at node a
and Vb is the small signal voltage at node b. The gain should
ideally be unity so that the output resistance of the current
source is infinite. But in practice it will have a finite value (
1).
Figure 5 shows how the current source, consisting of Q1
and VBB1, is bootstrapped using Q2, VEE2, and R. The voltage
gain from the base of Q2 (node a) to the emitter of Q1 (node b)
is less than but very close to unity. Therefore, node b tracks
node a. Thus the collectoremitter voltage and the collector
current of Q1 remains almost unchanged even though the
voltage at node a may vary. This implies that the output resistance is increased.

BIBLIOGRAPHY
1. Websters New World College Dictionary, 3rd ed., 1997.
2. A. S. Sedra and K. C. Smith, Microelectronics Circuits, Philadelphia: Saunders College Publishing, 1991.

558

BRIDGE CIRCUITS

BRIDGE CIRCUITS
Bridges are the most commonly used circuits in measurement
techniques. They enable accurate static measurements of resistance, capacitance, or inductance. Measurement accuracy
is provided by the null-balance method of output indication,
and by the fact that the bridge circuit configuration allows
comparison of unknown components with precise standard
units. This resulted in development of bridge instruments as
complete units of laboratory equipment. The balance in
bridges is highly sensitive with respect to variations of the
bridge components, and this brought about the widespread
use of bridge configurations in transducer and sensor applications. In addition, the bridge circuits may be found as working circuitry in electric filters where they provide the flexibility inachievable for other filter configurations, in radio
receivers and transmitters where the bridge approach is used
to design stable sinusoidal oscillators, and elsewhere in electronic hardware, where they are met in a wide variety of circuits used for determination of impedance, reactance, frequency, and oscillation period. The number of circuits based
on the bridge configuration is increasing, and this article describes the elements of the general theory of bridge circuits,
and outlines some of their above-mentioned basic applications
with more stress on measurement and transducer ones.
The circuit [Fig. 1(a)] including four arms with impedances, Z1, Z2, Z3, Z4, an element (in applications called balance detector or balance indicator) with impedance Zo, and
a voltage source of value Eg and output impedance Zg is an
example of the so-called bridge circuit. Figure 1(b) shows the
equivalent lattice form of this circuit. This is the simplest
circuit, for which the currents in the impedances cannot be
found using the circuit reduction based on parallel or series
connection of two or more impedances. To find these currents,
one has to write, for example, a system of three loop equations. As a result, this circuit, which is not very complicated,
is frequently used for demonstration of general (1) (mesh,
loop, and nodal analysis) and special methods (2) (wye-delta
transformation) of circuit analysis. The calculation of the current Io in the impedance Zo is a favorite example for demonstration of Thevenin and Norton theorems (1,3).
Most technical applications of this bridge circuit are based
on a simple relationship that exists among the circuit arm

Z1
Z1
Zg

Zo

Eg

(a)

Io

Zg
Z4

Io
Z4

Z2

Z2

Z3

Eg

Z3

(b)

Figure 1. (a) Bridge circuit and (b) its lattice form.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

Zo

BRIDGE CIRCUITS

Zg

Ig

Io

Vg

Eg

559

Zo

Vo

Zin

Eg

(1) (a) (2)

(3)

Io

(2) (b) (1)

(3)

Zout
(a)

(c)

(1)

Eg

(1)

(b)

(2)

(a)
(3)

Io
(2)

(b)
(3)

Figure 2. (a) Bridge circuit as a transmission

system; (b) two-ports with crossed input or output
wires; (c) two subcircuits in a bridge: (d) their parallel-series connection is clearly seen.

(d)

impedances so that the current (or voltage) of the detector

impedance has a zero value. One can easily see that in the
circuits of Fig. 1 the condition Io 0 (or the balance condition) is achieved when

The terms a11, a12, a21, and a22, (called chain parameters) are
the terms of a-parameter matrix. Equations (2) show that the
two-port does not transmit voltages and currents from left to
right if one of the following conditions is satisfied:

Z1 Z3 = Z2 Z4

a11 = a12 = a21 = a22 =

(1)

In measurements, this relationship allows one to calculate

one of the impedances if three others are known. In transducers, it is used in inverse sensethat is, if Io 0 then Eq. (1)
is violated as well. The deflection Io of the current Io from
zero (the value and sign) is used to evaluate the deviation of
Z1, Z2, Z3, Z4 or their combinations from their nominal values
satisfying Eq. (1). If these impedances are dependent on some
physical variables (which are called measurands), then Io
provides information on these physical variables.
The simplicity of Eq. (1) and its independence of Zo and Zg
(which in many applications are not well specified) make the
bridge measurements of physical variables reliable and sensitive. This feature brought about the widespread use of bridge
circuits in instrumentation and, recently, in microsensors.
By analogy, all circuits (of usually simple configurations)
where a certain relationship between the elements results in
a zero current in a given element, or zero voltage between a
given pair of nodes, are called bridge circuits here.

The investigation of the terms g-, y-, z-, and h-matrices (4)
allows one to formulate other specific relationships pertaining
to the balanced bridge circuits. In these circuits, correspondingly, the parameters of other two-port matrices have the values
g21 = 0 y21 = 0

(4)

g12 = 0 y12 = 0

h12 = 0 z12 = 0

(5)

are also, correspondingly, satisfied, and the circuit will not

transmit voltages and currents as well from right to left.
In addition, for reciprocal circuits the following relationship exists among the chain parameters:
|a| = a11 a22 a12 a21 = 1

Let us consider the bridge circuit as a passive two-port connected between the impedances Zo and Zg [Fig. 2(a)] and assume the balance conditions. Investigation of the systems of
parameters applied for two-port description (4) allows one to
formulate some specific relationships pertaining to bridge circuits.
The four terminal quantities for this two-port are related
by the equations

Ig = a21V0 a22 I0

z21 = 0 h21 = 0

From the other side, the bridge is a reciprocal circuit, and if

Eq. (2) is satisfied then the conditions

BRIDGE CIRCUIT BALANCE CONDITIONS

Vg = a11V0 a12 I0

(3)

(2)

(6)

Now let one consider the input and output impedances

Zin =

a11 Z0 + a12
a21 Z0 + a22

Zout =

a22 Zg + a12
a21 Zg + a11

(7)

One easily finds that if Eqs. (6) is valid and one of the conditions of Eq. (3) is satisfied, these impedances are given by one
of the following expressions:
Zin =

a11
a21

Zin =

a12
a22

Zout =

a22
a21

Zout =

a12
a11

(8)

560

BRIDGE CIRCUITS

Hence, the condition of balance indeed is independent of Zo

and Zg (they are not seen from the input and output terminals) if the two-port is a linear one.
The set of conditions of Eqs. (3) and (4) can be used, to some
extent, for synthesis of bridge circuits (5). A bridge circuit can
frequently be represented as a regular connection (4) of k twoports. Then the conditions of Eqs. (3) and (4) are modified into
i=k


(i)
g21
= 0 or

i=1

i=k

1
=0
a(k)
i=1 11

(9)

for parallel-series connection of these two-ports. They are

modified into
i=k


(i)
y21
=0

or

i=1

i=k

1
=0
(k)
a
i=1 12

(i)
z21
= 0 or

i=1

i=k

1
=0
(k)
a
i=1 21

(11)

for series connection of two-ports. Finally, the conditions of

Eqs. (3) and (4) will be modified into
i=k

i=1

(i)
h21
=0

or

i=k

1
=0
(k)
a
i=1 22

Z1 + Z3 +

(10)

for parallel connection of two-ports. Then they will give

i=k


port matrix terms. If the initial two-port is described by a z,

y, h, or g matrix, then only the diagonal terms of these matrices should change their sign.
Many bridge circuits can be represented as a connection of
two two-ports shown in Fig. 2(c), where the bridge output
branch is a wire carrying the current Io. This connection can
be redrawn as shown in Fig. 2(d). Then the condition of bal(a)
g(b)
ance (Io 0) for this circuit can be written as g21
21 or as
(a)
a11
a(b)
.
11
The following three bridges serve as examples. The circuit
of the twin-T bridge [Fig. 3(a)] is a parallel connection of two
(i)
T circuits. The parameter y21
(i 1, 2) for each of these cir(2)
cuits can be easily calculated, and their sum y(1)
21 y21 , in accordance with Eq. (10) gives the balance condition

(12)

for series-parallel connection of two-ports.

Some bridge circuits include a two-port with input or output crossed wires [Fig. 2(b)]. Such a two-port is described by
an a matrix with terms that are negatives of the initial two-

Z1 Z3
Z Z
+ Z4 + Z6 + 4 6 = 0
Z2
Z5

The ordinary bridge can be represented as a series-parallel

connection of two simple two-ports [Fig. 3(b)]. Calculating the
(i)
a22
(i 1, 2) parameters and using Eq. (11), one obtains
Z4
Z1
=
Z1 + Z2
Z4 + Z3

(14)

from which Eq. (1) follows immediately.

The double bridge [Fig. 3(c)] is easily recognized as the connection of two two-ports shown in Fig. 2(c). Equating the pa(2)
rameters a(1)
11 (left part) and a11 (right part), one can find the
balance condition
Z + Z3
Z6 (Z5 + Z7 ) + (Z1 + Z4 )(Z5 + Z6 + Z7 )
= 2
Z6 Z7 + Z4 (Z5 + Z6 + Z7 )
Z3

(15)

for this bridge.

Z1

Z3

Z2

Z2

Z4

Z1

Vo

Z6

Z3
Z4

Z5
(a)

(b)

Z1

Z2

Z5

Z6
Io
Z4
Figure 3. Examples of bridge circuits: (a) twin-T
bridge; (b) simple bridge redrawn as a series-parallel
connection of two two-ports; (c) double bridge.

(13)

Z7

(c)

Z3

Vo

BRIDGE CIRCUITS

Z1 + Z

Z1

Z2

Z1 + Z +

I10

Z2

Zg

Zg

Z4

Z4

Eg

Eg

Z3

e1
+

Z4
Z3

(b)
Z1 + Z

e2
+

(c)
Z1

Z2

e2
+

Z2

Zg

Zo

Zo
Z4

Eg

Zo

Eg

Z3

(a)

I10 Z

Z2

Zg

Zo

561

Figure 4. Calculation of sensitivity in a

simple bridge circuit: (a) initial circuit; (b)
circuit in balance; (c) introduction of compensating source: (d) extraction of external sources in autonomous two-port; (e)
circuit for calculation of current variation.

Z4
Z3

Z3

(d )

(e)

SENSITIVITY

can find that

An important parameter of the bridge circuit is sensitivity. It

is usually calculated for the balanced bridge condition. One
defines the sensitivity of the bridge output (or balanced) current as
Si =

dI0
I
0
dZk
Zk

(16)

where the derivative is determined at the point Io 0, and

the sensitivity of the bridge balanced voltage as
Sv =

dV0
V0

dZk
Zk

(17)

with the derivative determined at Vo 0. Here Zk is the element of the bridge circuit that varies (it is frequently called a
tuning element). The right sides of Eqs. (16) and (17) show
that variations are used for practical calculations of the sensitivities. In addition, Vo Zoio so that
Sv = Z0 Si

(18)

and calculation of only one sensitivity suffices.

The calculation of sensitivity requires a sequence of steps
that can be demonstrated (Fig. 4) using the bridge of Fig. 1(b).
Assume that it is required to find the sensitivity

I10 =

dI0
dZ1

(20)

Let the element Z1 vary, and let its variation be Z (Fig. 4c).
In accordance with the compensation theorem (2,5), the current Io occurring in the element Zo can be calculated if one
introduces in the branch with Z1 Z a compensating voltage
source I10Z, as shown in Fig. 4(c), and consider a circuit (Fig.
4c) that is an active autonomous two-port (5) connected between the impedances Zg and Zo. Then, this active autonomous two-port can be represented by a passive two-port (of
the same structure, in this case) and two equivalent sources,
which appear at the two-port terminals. This step is simply a
generalization of the Thevenin-Norton theorem for two-ports.
If, for example, one decides to use e1 and e2 connected in series
with the two-port terminals [Fig. 4(d)], one can find that
e2

I10 Z3 Z
Z2 + Z3

(21)

(in this calculation it is assumed Z1 Z Z1, and Z1Z3

Z2Z4). As for e1, there is no need of calculating it, because the
bridge two-port in the circuit of Fig. 4(d) is nearly at the balance condition, and the contribution of e1 to the current in Zo
can be neglected. Simultaneously, for the same reason, the
source e2 does not produce any current in the impedance Zg.
Hence, one can calculate the current in Zo using the approximate circuit of Fig. 4(e). One obtains

I0
Si =

Eg Z2
Zg (Z1 + Z2 ) + Z1 (Z2 + Z3 )

(19)

Eg Z2 Z3 Z
[Zg (Z1 + Z2 ) + Z1 (Z2 + Z3 )][Z0 (Z2 + Z3 ) + Z2 (Z3 + Z4 )]
(22)

From Eq. (22) it immediately follows that

of this bridge with respect to variation of the element Z1 [Fig.
4(a)]. First, let us calculate the current I10 through this element in the condition of balance, when Io 0. In this calculation the element Zo can be disconnected [Fig. 4(b)] and one

Si

Eg Z2 Z3
[Zg (Z1 + Z2 ) + Z1 (Z2 + Z3 )][Z0 (Z2 + Z3 ) + Z2 (Z3 + Z4 )]
(23)

562

BRIDGE CIRCUITS
(1)

I 10

(1)

I 10
(1)

(1)

Zg

(1)

Zg
Zo

Eg

Eg

(2)

(2)

(a)

(b)

(c)

(1)

(1)
2

ZT
IT0

ZT

IT0

ZT + Z

Io

Zo

(2)

I10 Z +

(d)

(e)

Figure 5. Calculation of sensitivity in series connection of two two-ports: (a) initial circuit; (b)
circuit in balance; (c) current in tuning element; (d) introduction of compensating source; (e)
extraction of external sources in autonomous two-port and the circuit for calculation of current
variation.

This calculation of sensitivity may be formalized if the

bridge circuit represents a regular connection of two two-ports
(bridge circuits with more than two subcircuits are very rare).
We assume that the tuning branch is located in the first
two-port.
Let us consider as an example the series connection of two
two-ports [Fig. 5(a)]. As a first step we assume the condition
of balance and then disconnect the indicator branch [Fig. 5(b)]
and calculate the input current I(1)
10 . One can see that this current is equal to
(1)
I10

Eg
=
(1) + z (2)
Zg + Z11
11

(27)

where K2 is another transfer coefficient. Consider that the

bridge circuit is nearly balanced, the current I of the detector
may be found from the approximate circuit shown in Fig.
5(e). The result will be
I0

Z0 +

e2
(1)
z22

(2)
+ z22

(28)

Finally, one can find that

(25)

where K1 is a transfer coefficient. Using the compensation

theorem, one introduces in the tuning branch the compensating voltage
ec = IT0 Z

e2 = K2 ec

(24)

The current IT0 in the tuning branch, ZT, may be determined

by considering the first two-port only [Fig. 5(c)] with the output open and the current I(1)
10 applied to its input. For a linear
two-port one can write that
(1)
IT0 = K1 I10

with corresponding inputs. The source e2 can be found as

(26)

(other forms of the compensation theorem may also be used).

For exact calculation of Io one has to preserve the variation
Z of the tuning impedance, as is shown in Fig. 5(d). Yet, to
simplify the results (and assuming that Z is small), this variation is usually omitted. The first two-port now becomes an
autonomous active two-port. It may be represented as a passive two-port having the sources e1 and e2 connected in series

Si

K1 K2 Eg
(1) + z (2) )(Z + z (1) + z (2) )
(Zg + z11
0
11
22
22

(29)

The extension of this approach for other regular connections

of two two-ports does not present any difficulty (5).

APPLICATION OF BRIDGE CIRCUITS FOR

MEASUREMENT OF COMPONENT PARAMETERS
Bridges are commonly used circuits in measurements. They
have high sensitivity and allow accurate measurements of resistance, capacitance, and inductance. Measurement accuracy
is due to the null-balance method of output indication and to
the fact that the bridge circuit configuration conveniently
allows direct comparison of unknown components with precise standard units. Here we outline the basic ideas of such
measurements. They are useful in laboratory environments
and form the basis of commercial equipment designs (6).

BRIDGE CIRCUITS

Dc Bridges
The dc bridges are used for precise measurements of dc resistance. The conventional Wheatstone bridge is shown in Fig.
6(a). It consists of four arms R1 to R4, a zero-center galvanometer G, which serves as a balance detector, a protection shunt
Rp, a battery VB (1.5 to 9 V), and a set of switches S1 to S3.
We assume that the resistor R1 is a resistor whose value is
unknown, the resistor R4 is a standard resistor (usually a
variable decade box providing, for example, 1 steps from 1
to 11,100 ), and the resistors R2 and R3 are ratio-arm resistors that serve to provide multiplication of the standard resistance by convenient values, such as 100, 10, 1, 1/10, and
1/100.
The goal of the operating procedures is to achieve balance,
which is indicated by a zero reading of the galvanometer with
the switches S1 and S2 closed and the switch S3 open. In the
beginning of the procedure, S3 is closed and S1 and S2 are
open. To avoid transient galvanometer overloading, S1 is
closed first. Then S2 is closed, and an approximate balance is
achieved. Only then is switch S3 opened, and the final balance
is achieved. When balanced, the condition R1R3 R2R4 is satisfied, and the unknown resistor value can be found as
R1 =

R2
R
R3 4

(30)

When the measurement procedure is finished the switches

are returned to their initial state in reverse order (i.e., S3 is
closed first, then S2 is opened, and, finally, S1 is opened).
The main sources of measurement errors are the variance
of ratio-arm resistors (the design characteristic), additional
resistance introduced by poor contacts, resistance in the remote wiring of the unknown (the tactics used against these
sources of errors are discussed in Ref. 7), changes in resistance of arms due to self-heating, spurious voltages introduced from the contact of dissimilar metals, and incorrect balance. The well-made bridge can be expected to measure from
about 0.1 to the low megohm range with approximately 1%
accuracy, and for the range 10 to 1 M accuracies of 0.05%
can be expected. A good practice is to make measurements on
a series of extremely accurate and known resistors and to use
the obtained errors as an error guide for measurements with
the closest bridge constants. For measuring very high resistances, the galvanometer should be replaced by a high-impedance device. For measuring very low resistances, one has to
use the double bridge described later.
In measurements of very low resistances, the resistance of
the connector (yoke) between the unknown resistance R1 and

S1

R1

VB

S2
R4

(a)

R3

R7

Ac Bridges
The Wheatstone bridge circuit may also be used for impedance measurements at audio/radio frequencies. The battery is
replaced by a generator of sinusoidal voltage, and a sensitive
headset or oscilloscope is used as the balance detector [Fig.
7(a)]. The arms now may include reactive components, and
when the condition of balance, as in Eq. (1), is satisfied, one
can find the component Z1 from the equality
Z1 =

Z2
Z
Z3 4

(32)

Introducing Zi Ri Xi (i 1, 2, 3, 4) in Eq. (32), one obtains

R1 + jX1 =

R2 + jX2
(R + jX4 ) = A + jB
R3 + jX3 4

(33)

Hence, to measure two quantities R1 and X1, one can use six
parameters to achieve the balance. This results in an enormous number of different bridges (8) adapted for particular
circumstances.
The selection of configurations to be used in a wider range
of applications (6) is dictated by two factors. First, in general,
attainment of balance is a progressive operation requiring
back and forth in-turn improvements in resistive and reactive
balances. For rapid balancing it is desirable that the adjustment of resistive part A be independent of the adjustment
made in the reactance part jB. This cannot always be done.
In the region of balance the detector voltage is
V0 = K(Z1 Z3 Z2 Z4 )

R2

R3

R4
(b)

(31)

(this is easily done in practical designs; see Ref. 6), then, using Eq. (15), one can find that the relationship among R1 to
R4 given by Eq. (30) will be preserved.
The Kelvin bridge allows one to measure the resistances in
the range 1 to 10 with accuracy better than 0.1%, and in
the range 0.1 to 1 better than 1%.

R6

S3
RP

R
R5
= 2
R7
R3

R5

G
VB

the standard resistance R4 may seriously affect accuracy. The

double (Kelvin) bridge [Fig. 6(b)] is devised to circumvent this
difficulty. In this circuit the resistor R6 represents the resistance of this connector, and R5 and R7 are small resistances
of two additional arms. If one chooses

R1

R2

563

Figure 6. (a) Wheatstone and (b) Kelvin bridges.

(34)

564

BRIDGE CIRCUITS

C1
R1

R2

R2

R1

R4

R4

R3

R3

C4
(a)

(b)

L1

L1
R2

R2

R1

R1
D

D
R3

R4

R3

C3

R4
C3

Figure 7. Ac bridges: (a) Wheatstone bridge; (b) ratio-arm

capacitive bridge; (c) Maxwell inductance bridge; (d) Hay
inductance bridge.

(c)

where K may be assumed constant (9). In general, the most

rapid convergence to balance is obtained when the phase
angle between the selected pair of adjustable components in
Eq. (34) is /2 and least rapid when the angle tends to zero.
For example, for the bridge of Fig. 7(b) the balance equations
are
R1 =

R2
R
R3 4

C1 =

R3
C
R2 4

(35)

If R4 and C4 can be adjusted, rapid balancing is obtained. If

R4 and R2 are chosen for adjustment, the convergence can be
very slow (9).
The second important factor is that a standard capacitance
more nearly approaches the ideal no-loss reactance than does
the best wire-wound coil type of inductance. Hence, it is desirable to measure an inductance in terms of capacitance. This
can be obtained in the Maxwell bridge [Fig. 7(c)]. The balance
equations for the Maxwell bridge are
L1 = R2 R4C3

R1 =

R2
R
R3 4

(36)

The Maxwell bridge is mainly applied for measuring coils of

low Q-factors. Indeed, Q1 L1 /R1 C3R3, and a coil with
Q1 10 may require very high values of R3. This limitation
is removed in the Hay bridge [Fig. 7(d)]. The balance equations for the Hay bridge are
R1 =

R2
1
R
R3 4 Q21 + 1

L1 = R2 R4C3

1
Q21 + 1

(37)

where Q1 L1 /R1 1/(C3R3).

One can see that a disadvantage of the last two circuits is
the interaction between reactive and resistive balance, yet the

(d)

desire to have a constant standard capacitor prevails, and

four basic configurations shown in Fig. 7 are used in generalpurpose universal impedance bridges (6).
It is impossible here to give even a brief survey of specialized bridges; yet four configurations deserve to be mentioned.
Figure 8(a) shows the bridge with the voltage source and detector interchanged. This allows one to apply a polarizing
voltage and measure the parameters of electrolytic capacitors.
The battery that supplies this voltage must be shunted by a
bypass capacitor, CB. Figure 8(b) shows a configuration (the
Owen bridge) adapted for incremental inductance measurements. A filter reactor LRF inserted in the bridge measurement circuit minimizes the effect of core-induced harmonics
in determining the balance point (R2 and C3 are used for
balance).
Figure 8(c) shows the Shering bridge, which is also used
for measuring the capacitance and dissipation factor of the
capacitorsespecially at high voltages. The lower part of this
bridge (resistors R4 and R3 and capacitor C3) may be maintained at a relatively low potential, and the adjustment to the
variable elements can therefore be made safely. The balance
equations are
C1 = C2

R3
R4

R1 = R4

C3
C2

(38)

Other useful configurations of ac bridges with a wide range

of application (bridges for measuring mutual inductances) can
be found in Refs. 6 and 9. Some improvements of the measuring techniques (the Wagner ground) are described well in
Ref. 9.
As a consequence in the development of transformers with
very tight magnetic coupling, the ratio arms of some bridges
may be replaced by transformer coils. A transformer can also
be used as a current comparator. An example of a circuit us-

BRIDGE CIRCUITS

ing these two properties of transformers is shown in Fig. 8(d)

(9). Here the generator is connected to the primary winding
of voltage transformer T1, and the secondary windings of T1
are tapped to provide adjustable sections of N1 and N2 turns,
respectively. The primary windings of the current transformer T2 are also tapped to provide sections with adjustable
turns n1 and n2. The secondary of T2 is connected to a detector.
Let Y1 G1 jB1 be the unknown admittance, and Y2
G2 jB2 be a suitable comparison standard. Balance may be
achieved by any suitable combination of adjustments of Y2
and tap positions. The balanced condition corresponds to zero
net flux in the primary of T2. Hence, the condition of balance
is

tutional methods of measurement. In these methods, the

bridge is first balanced with the unknown impedance connected in series or in parallel with a standard component in
one of the bridge arms and then rebalanced with the unknown either short- or open-circuited. The unknown can then
be determined in terms of the changes made in the adjustable
elements, and the accuracy depends on the difference between
the two sets of balance values obtained. Residual errors, such
as stray capacitance and stray magnetic coupling, and any
uncertainty in the absolute values of the fixed bridge components are virtually eliminated. These effects are nearly the
same whether or not the unknown is in the circuit.
APPLICATION OF BRIDGE CIRCUITS IN TRANSDUCERS

n1 I1 = n2 I2

(39)
Bridge circuits are frequently used to configure transducers
that is, the circuits providing information about physical variables (temperature, force, pressure, etc.) capable of changing
the value of one or more components of the bridge. In transducers, one measures the voltage occurring at the detector (or
a current through the detector). The problems that occur in
this case can be demonstrated using the circuit shown in
Fig. 9(a).
In this circuit the resistors R1, R2, R3 are constant and the
resistor R3 R0(1 x) is a linear function of a dimensionless
variable x. One can assume that the detector resistance R0 is
very high, and then find the voltage V0 at the detector terminals. One then has

If the resistance and the flux leakage in the primary windings

of T2 can be neglected and the core flux is zero, the external
ends of the current transformer have the same potential as
the ground line. The voltages V1 and V2 then appear across
Y1 and Y2, respectively, so that I1 Y1V1 and I2 Y2V2. In
addition, the ratio of the induced voltages in the secondary of
T1 is V2 /V1 N2 /N1. Substituting these simple relationships
in Eq. (39) and separating real and imaginary parts, one obtains
G1 =

n2 N2
G
n1 N1 2

B1 =

n2 N2
B
n1 N1 2

(40)

V0 = V

Hence, using suitable combinations of the tappings, a wide

range of multiplying factors are available. For a given set of
standards, this provides a much wider range of measurements than does the conventional ac Wheatstone bridge. This
bridge also allows independent balancing of the conductive
and susceptive components (9).
The degree of accuracy obtained in bridge impedance measurements can be considerably enhanced by adopting substi-

C1

R2

(41)

V0 = V

mx
(m + 1)(m + 1 + x)

(42)

R2

R1 V
B

CC
D

px + (p mn)
(n + p)(m + 1 + x)

where m R2 /R0, n R4 /R0. When the variable x 0, the

circuit should be balanced; this requires that the condition
p mn be satisfied. The voltage at the detector then becomes

L1

CB

R1

565

Cc
D

VB

R4

R3

C4

Cc

R4
LRF

C4

(a)

C3

(b)
I1

C1

V1

C2

Z1

R1
D
R4

R3

C3

N1

n1

N2

n2

V2
Voltage
transformation

(c)

Z2

I2
(d )

Current
transformation

Figure 8. Some special ac bridges: (a) electrolytic capacitor bridge; (b) Owen increment inductance bridge; (d)
transformer bridge.

566

BRIDGE CIRCUITS

I
R1

R2

R0 (1 + x)

Vo
V

Vo

R0
+

Ro
I3

R4

R3 =
R0 (1 + x)

R0

(a)

(b)

I
R0

R0 (1 x)

R0
Figure 9. Resistive transducer bridges: (a) with
one variable resistor; (b) with two variable resistors; (c) with push-pull variable resistors; (d) with
four variable resistors.

mx
(m + 1)2

(43)

The relative error due to nonlinearity, n, may be calculated

as
n =

x
V0i V0
x

=
V0i
m+1+x
m+1

(44)

The reduction of n is a frequent requirement in transducer

applications. In the case being considered this can be
achieved by increasing m and restricting the range of x. This
means that one is trying to establish a constant current
through R3 (assuming that the voltage V is constant) and is
using the bridge measurements for reasonably small x.
Another important parameter of the circuit of Fig. 9(a) is
its sensitivity. Resistor R3 may be considered as the tuning
element of the bridge; in this case its variation for small x is
x R0 x, and in the vicinity of balance one can take V0
V0. Then the voltage sensitivity is
Sv =

V
V0
m
=
R0 x
R0 (m + 1)(m + 1 + x)

(45)

Its maximum value

Svmax =

V
1
R0 (m + 1)2

Vo

(46)

is achieved when m 1. This result shows that in this particular case the condition of maximum sensitivity conflicts with
minimization of nonlinearity error.

R0 (1 x)

R0 (1 + x)

Vo

R0 (1 x)

R0 (1 + x)

(c)

One can see that V0 is a nonlinear function of x. The desired

ideal response would be
V0i = V

R0 (1 + x)

R0 (1 + x)

(d)

However, this situation is not always inevitable. If the current I in the circuit of Fig. 9(a) is constant the detector voltage
will be

mnx
(m + 1)(n + 1) + x



mnx
x
1
IR0
(m + 1)(n + 1)
(m + 1)(n + 1)

V0 = IR0

(47)

The nonlinearity error is

n =

x
(m + 1)(n + 1)

(48)

This error is decreasing for increasing m and n. The sensitivity in this case is
Sv = I

mnx
(m + 1)(n + 1) + x

(49)

and its maximum value, achievable for m , n , is

Svmax = I

(50)

Hence, in this case there is no contradiction between optimization of sensitivity and reduction of nonlinearity. In the passive circuit, though, the condition of constant current I can be
achieved only approximately.
The results of analysis for the bridge with one variable resistor may be represented by Table 1. It allows one to conclude (7) thatto reduce the nonlinearity errorone has to
restrict the measuring range, work with reduced sensitivity,
or consider current source realization in order to use it as a
power supply for the bridge or the variable resistor.
An increase of sensitivity with a simultaneous decrease of
nonlinearity can also be achieved by using two variable resis-

BRIDGE CIRCUITS

567

Table 1. Properties of the Bridge with One Variable Resistor

Supply
Condition

Nonlinear
Error, n

Sensitivity
Sv

Parameters
Required

Approximate
Conditions

Vo
xR0

V constant

V
m
R0 (m 1)(m 1 x)

I constant

I3 constant

I3

mn
mn m n 1 x
m
m1
Si

Maximal
Sensitivity

x
m1

1
V
R0 (m 1)2

m2 1 x, q

R2 R3

x
mn m n 1

m , n , q

R2 R0 , R4 R0

absent

I3

m , q

R2 R0

Io
xR0

V constant

m
V
R 20 (m 1) (m2 )x

x(m2 )
(m 1)

V (1 m)
R0 (1 m)

q m2(q 1), n 0
small x

R4 R0

I constant

mn
I
R0 (n 1) [m(n 1) q]x

x[m(n 1) q]
(n 1)

1
I
R0 (n 1)

q n2 1, m
small x

R2 R0

I3 constant

I
m
R0 (m 1)q

absent

I3 1
R0 q

m
large q

R2 R0 , Rm R0

Note: m R2 /R0 , n R4 /R0 , p R1 /R0 , q Ro /R0 ; R3 R0(1 x); q(m 1) m(n 1); balance requirement p mn.

tors in opposite arms [Fig. 9(b)] or by using resistors undergoing opposite variations in adjacent arms [Fig. 9(c)] or by using
variable resistors in all four arms [Fig. 9(d)]. Table 2 (7) summarizes and compares the results for the output voltage in all
such bridges for the case in which all resistors have the same
initial value of R0. Again, one can see that the bridges powered by a current source (which leads to active circuits) have
more choices for linearization.
The realization (10) of the current source for the powering
bridge usually involves [Fig. 10(a)] a second voltage source
(denoted here as Zener diode voltage, VR) and an operational
amplifier. The bridge current is I VR /RR.
Switching to active circuits, some other alternatives should
be considered. The circuit of Fig. 10(b), which provides a linearly dependent output voltage
V0 = V

x
2

(51)

can be considered as one alternative. The circuit of Fig. 10(b)

requires the bridge to have five accessible terminals. The circuit of Fig. 10(c), with two operational amplifiers, can also be
considered. It provides a linearly dependent output voltage
V0 = V

RG
x
R0

(52)

and amplifies the bridge output signal.

Capacitive and inductive transducers can be used in a variety of ac bridge circuits. Here we discuss only the so-called
Blumlein bridge circuit. It has particular advantages for use
with variable capacitive transducers (11) and is used frequently with inductive transducers as well. The circuit is
shown in Fig. 11(a). Let the detector impedance be Z0 .
Two variable impedances (sensor arms), Z Z and Z Z,
operate in a push-pull fashion. The ratio arms represent a

Table 2. Output Voltage for Bridges with Variable Resistors and Supplied by a Constant Voltage or Current
R1

R2

R3

R4

Constant V

Constant I
IR0

x
4x

R0

R0

R0(1 x)

R0

x
V
2(2 x)

R0(1 x)

R0

R0(1 x)

R0

x
(2 x)

IR0

x
2

R0

R0

R0(1 x)

R0(1 x)

2x
4 x2

IR0

x
2

R0

R0(1 x)

R0(1 x)

R0

x
2

IR0

x
2

R0(1 x)

R0

R0(1 x)

R0

R0(1 x)

R0(1 x)

R0(1 x)

R0(1 x)

Vx

x2
4 x2

IR0
IR0 x

x2
2

568

BRIDGE CIRCUITS

VCC
RB

R1
+

R0

R0

R2

R0 (1 + x)

Vo

A1

R4

A1

Vo

R3
R0

VR

RR

(b)
(a)
R0

RG
R0 (1 + x)

R0

R0

A2

Vo

+
A1

V
+
Figure 10. (a) Current source for bridge powering
and linearized active bridge circuits: (b) with one amplifier and (c) with two amplifiers.

(c)

Z Z
Vo

I1

Z + Z

Vo = 0

(a)

I Z

I1

I Z

Z + Z

I2

Z1

V0

Figure 11. (a) Blumlein bridge and (b) the circuits for calculation of branch currents and (c) current variations; (d)
pseudobridge circuit.

(c)

(b)

I2

V
L

Z Z

(d)

V0

BRIDGE CIRCUITS

transformer with two tightly coupled coils (i.e., L M ). The

bridge is fed by a sinusoidal voltage V.
Analysis of steady state can be done in two stages. When
the sensor arms have equal impedances Z [Fig. 11(b)], one
finds that
I1 = I2 = I =

(54)

2 jL
Z + 2 jL


(55)

This result can be used for evaluation of the Blumlein bridge

sensitivity. For a capacitive sensor, Z 1/iC. Then Z/Z
C/C, and one obtains
V0 = 2V

C
C

22 LC
1 22 LC

(56)

Hence, the sensitivity of the Blumlein bridge with capacitive

sensor arms is a function of frequency. For a stable result one
must choose the parameters so that 22CL 1.
For an inductive sensor Z il. Then Z/Z l/l and
V0 = 2V

l
l

2L
1 + 2L

(57)

This analysis demonstrates that in the Blumlein bridge

one essentially has comparison of currents at zero potential
of the transformer arms. Hence, the capacitive parasitics at
the detector terminals are not important. Using a third output transformer coil (as was the case for the transformer
bridge), one can realize a very sensitive capacitive sensor.
The idea of current comparison is more directly used in
the pseudobridge circuit [Fig. 11(d)], where the difference in
currents of the sensor arms is entering the virtual ground and
produces the output signal
V0 2V

V0
z21Z0
=
Eg
Zg Z0 + Zg z22 + Z0 z11 + |z|

(Z1 + Z4 )(Z2 + Z3 )
Z1 + Z2 + Z3 + Z4
Z2 Z4 Z1 Z3
= z21 =
Z1 + Z2 + Z3 + Z4

z11 =

IZ
Z + 2 jL

Z
Z

T (s) =

(53)

The variation of the detector voltage is

V0 = 2IZ 2ZI = 2V

transfer function of this system is

(59)

where

V
Z

Indeed, in this condition the magnetic flux in the transformer

is zero and the detector voltage and the voltage at each transformer coil are zero. The variations of the impedances may be
represented, in accordance with the compensation theorem
(see the first section of this article), by two voltage sources.
The circuit [Fig. 11(c)] that includes only these two sources
can be used for calculation of current variations. Writing two
loop equations for this circuit, one finds that
I1 = I2 = I =

569

Z1 Z
Z Z

(58)

Pseudobridges are mostly used with capacitive sensors (12).

BRIDGE CIRCUITS IN NETWORK SYNTHESIS
Let us return to the lattice form of the bridge [Fig. 1(b)] and
consider the impedances Z1 to Z4 as a coupling two-port of the
transmission system [Fig. 2(b)]. One then finds that the

z12

z22 =

(Z1 + Z2 )(Z3 + Z4 )
Z1 + Z2 + Z3 + Z4

|z| = z11 z22 z212

One of the main problems of network synthesis is the realization of a transfer function with prescribed zeros. The zeros
of transmission (which are the zeros of the transfer function)
can now be interpreted as the frequencies at which the bridge
is balanced. This result, obtained for the simple bridge, is
valid for all bridge configurations. Hence, the synthesis of
simple rejection filters (such as the twin-T bridge, or T
bridge), the transfer function of which includes two complexconjugate zeros, can be simplified if the balance condition is
used directly for the choice of filter elements.
The control of transmission zeros location becomes especially simple if the lattice is symmetric. For Z2 Z4 Za and
Z1 Z3 Zb, the transmission zeros occur at those values of
s for which the two branch impedances have equal values.
This can be arranged to occur for any value of s; hence, the
locations of the transmission zeros of a lattice are unrestricted and may occur anywhere in the s-plane. For example, if Z1 Z3 R0 and Z2 Z4 R Ls 1/Cs, the transmission zeros are given by the zeros of a polynomial
LCs2 + (R R0 )Cs + 1 = 0

(60)

and are located in the left-half s-plane for R R0, on the jaxis for R R0, and in the right-half s-plane for R R0. If
L 0, one can obtain a zero on the positive real axis.
It can be proved (13) that every symmetric, passive, reciprocal, lumped, and time-invariant two-port has a physically
realizable lattice equivalent. Thus, the lattice is the most
general symmetric two-port. The lattice has an important
role in the modern network synthesis (15) and, in the past,
was a useful tool in the general image parameter theory of
filter design (16).
BRIDGE CIRCUITS IN ELECTRONICS
In this section we describe oscillators, the operation of which
can only be fully understood if the bridge balanced condition
is considered.
Figure 12 shows the Wien bridge [Fig. 12(a)], twin-T bridge
[Fig. 12(b)], and Meachem bridge [Fig. 12(c)] sinusoidal oscillators. The steady-state operation of all three oscillators requires that, at a certain frequency, the condition
AT B ( j) = 1

(61)

be satisfied. Here, TB( j) is the transfer function of the corresponding bridge calculated at s j. The transfer functions
of the Wien bridge and twin-T bridge should be designed so

570

BRIDGE CIRCUITS

C1
R1
+
C4

R2
vo (t)

R1

R3
Avo(t)

C6

+ Avo (t)

+
C4

R3

R4

R5

C2

(a)

vo (t)

(b)
j

C1

j 0

R1

R2

j 0

L1
Figure 12. Sinusoidal oscillators: (a) Wien
bridge; (b) twin-T bridge; (c) Meachem
bridge; and pole-zero diagrams of bridge
transfer functions: (d) Wien and twin-T
bridge; (e) Meachem bridge.

+
R4

vo (t)

(s2 1 s + 02 )
(s + 1 )(s + 2 )

R3
(c)

( j0 ) = 0 or 180

j 0

(d)

S = 0

(63)

(e)


d 
d =

(66)
0

In the vicinity of 0, only the nearest zeros and poles are important, and this stability will be
S 2Qz

(64)

(65)

The first condition in Eq. (65) gives the required amplifier

gain, and the second condition gives the required sign of gain.

(67)

for the Wien-bridge and twin-T oscillators. Here Qz 0 /

(21). For the Meachem bridge oscillator, one has
S 2Qz 2Qp

and the condition of Eq. (61) can be rewritten as

A|TB ( j0 )| = 1

2 1
j 0

(62)

Here, 0 (L1C1), 1 (R2R4 R1R3)/(2L1R3), and 2

(R1 R4)/(2L1). In all cases, 0 is the desirable oscillation frequency.
In the vicinity of the points j0, the transfer function of
the bridge will be
TB ( j0 ) = |TB ( j0 )|e ( j 0 )

A very important oscillator parameter (16) is the indirect

frequency stability, S. It is calculated as

has two complex-conjugate zeros located in the right half of

the s-plane in the vicinity of the points j0 [the result of Eq.
(62) assumes that, for the twin-T bridge, the real zero and
real pole are cancelled]. For the Wien bridge, 0
(R1C1R4C4), 1 [(R2R4 R1R3)/(R1R3R4C4)] 1/(R1C3). For
the twin-T bridge the elements providing desirable zeros location should be chosen using the balance condition of Eq. (13).
The transfer function of the Meachem bridge should be
(s2 1 s + 02 )
TB (s) = K
(s + 2 s + 02 )

that
TB (s) = K

(68)

where Qp 0 /(22). One can see that the achieved indirect

frequency stability is determined by the chosen bridge imbalance [the reactance branch in Meachem bridge oscillator is
usually a crystal, and the location of poles in TB() is determined by the crystal parameters]. The connection between
bridge imbalance and design for frequency stability is well
known for the Wien bridge and Meachem bridge oscillators
(16), however, it is still not clearly understood in the twin-T
bridge oscillator design (17).
The application of the bridge circuits to design of nonsinusoidal oscillators is less known. Using switches in a two-operational amplifier multivibrator, one can obtain control of the
oscillation frequency by detuning a resistive bridge (Fig. 13).

BRIDGE INSTRUMENTS

P1
R1

R2

VCC

5. E. V. Zelyakh, General theory of linear electric networks, Moscow:

Acad. of Sci. USSR, 1951 (in Russian).

v0

6. H. E. Thomas and C. A. Clarke, Handbook of Electronic Instruments and Measurement Techniques, Englewood Cliffs, NJ: Prentice-Hall, 1967.

Ra
Rb

VCC

R3
P2

9. R. G. Meadows, Electric Network Analysis, Harmondsworth, Middlesex, UK: Penguin Books, 1972.
P1

R2

VCC

12. L. Baxter, Capacitive Sensors, New York: IEEE Press, 1997.

13. W. H. Chen, Linear Network Design and Synthesis, New York:
McGraw-Hill, 1964.

v0

VCC

R3

16. K. K. Clarke and D. T. Hess, Communication Circuits: Analysis

and Design, Reading, MA: Addison-Wesley, 1971.

(b)

Figure 13. Bridge-controlled multivibrators: (a) with Schmitt trigger; (b) with comparator.

For normal circuit operation, the bridge should be unbalanced. The oscillation frequency of this circuit is

1
2C

R

R1

R3
R4

17. N. Boutin and A. Clavet, The misunderstood twin-T oscillator,

IEEE Circuits Syst., 2: 813, 1980.
18. J. H. Huizing, G. A. van Rossum, and M. van der Lee, Two wire
bridge-to-frequency converter, IEEE J. Solid-State Circuits, SC22: 343349, 1987.

I. M. FILANOVSKY
University of Alberta, Edmonton
+

(VCC
VCC
)Rb

+ V ) + R (R + R )(V + V )]
[Rb (R3 R2 )(VCC
a
2
3
0
0
CC

(69)

The use of a comparator allows one to eliminate the feedback

resistances of the Schmitt trigger [Fig. 13(b)]. For this circuit,
the oscillation frequency is
f0 =

14. D. F. Tuttle, Electric Networks: Analysis and Synthesis, New York:

McGraw-Hill, 1965.
15. M. B. Reed, Electric Network SynthesisImage Parameter
Method, Englewood Cliffs, NJ: Prentice-Hall, 1955.

P2

f0 =

10. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, New York: McGraw-Hill, 1988.
11. H. K. P. Neubert, Instrument Transducers, Oxford, UK: Clarendon Press, 1975.

R4

7. R. Pallas-Areny and J. G. Webster, Sensor and Signal Conditioning, New York: Wiley, 1991.
8. B. Hague, Alternating Currents Bridge Methods, London: Pitman & Sons, 1938.

(a)

R1

3. E. Brenner and M. Javid, Analysis of Electric Circuits, 2nd ed.,

New York: McGraw-Hill, 1967.
4. S. Seshu and N. Balabanyan, Linear Network Analysis, New
York: Wiley, 1959.

R4

571

1
4CR3

R

R1

R3
R4

(70)

Both circuits are used as bridge-to-frequency converters in

two-wire transducers (18).
CONCLUSION
Bridge circuits form a specialized, yet a wide-ranging, group
of circuits that find application in measurement techniques,
transducers, network synthesis, and electronics.
BIBLIOGRAPHY
1. H. H. Skilling, Electrical Engineering Circuits, New York: Wiley, 1958.
2. R. E. Scott, Linear Circuits, Reading, MA: Addison-Wesley, 1960.

BUTTERWORTH FILTERS

657

G() 20 log10 T( j), the filter gain in dB, or A()

G(), the filter attenuation. () is the filter phase, but we
may advantageously use the group delay () ()/.
Ideal filters should have constant gain and constant group
delay in frequency bands called pass bands and infinite attenuation in frequency bands called stop bands. Real filters only
approximate these characteristics. In general, no attention is
paid to phase when approximating gain characteristics, for
satisfying gain and phase in tandem is a problem that usually
does not admit closed-form solution and requires an iterative
optimization procedure. If phase equalization is necessary,
the usual practice is to perform it later using other circuits.
Classical approximation methods are usually developed for
normalized low-pass filters with a pass band between 0 rad/s
and 1 rad/s, where the attenuation variationthe pass-band
ripplemust not exceed Ap, and with a stop band from s
1 rad/s to infinity, where attenuation must exceed the minimum attenuation in the pass band by at least As.
Other low-pass, high-pass, band-pass, and band-stop filters
can be designed by trivial frequency transformations applied
onto the normalized low-pass-filter prototype, and will not be
discussed here.

HISTORICAL BACKGROUND
The concept of electrical filters was independently developed
by Campbell and Wagner during World War I. These early
electrical wave filters easily accomplished the stop-band requirements, but a reasonably constant gain in the pass band
required heuristically tuning of some filter resistors.
In his seminal work, Butterworth (1) attacked the problem
of designing linear intervalve resonating circuits in such a
way that the overall circuit combined amplification and filtering, matching the desired characteristics in both stop band
and pass band without a tuning procedure. For the normalized low-pass filter, Butterworth proposed a filter factor F,
nowadays corresponding to the filter gain T( j), such that
|T ( j)|2 = 1/(1 + 2n ) = 1/L(2 )

(1)

where n is the filter order. Figure 1 shows T( j) vs. for

n 2, 4, 7, and 10. It is clear that T( j) approaches the
ideal low-pass-filter characteristics when n is increased, satisfying pass-band and stop-band requirements. Moreover, Butterworth cleverly realized that for n even L(2) could be decomposed as a product of n/2 second-order polynomials Pi(),

L(2 ) =

n/2


i=1

BUTTERWORTH FILTERS
Electrical filters made by linear, lumped, and finite components present a real rational transfer function T(s)
Vout(s)/Vin(s). For real frequencies, T( j) T( j)ej(), where
T( j) is the filter linear gain. Alternatively we may use

Pi () =

n/2

[1 + 2 cos(2i 1)/2n + 2 ]

i=1

and showed that (1) the product of conveniently selected pairs

of polynomials comprised a function Li(2) Pi()Pn/2i(),
which could be associated with a second-order filter, and (2)
the product of four polynomials selected as described previously comprised a function Li(2)Lj(2), which could be associated with a fourth-order filter. All components of these loworder filters could be easily calculated, and the filters could
be used as coupling stages between amplifier tubes. For the
first time it was possible to construct a filter amplifier that
required no heuristic tuning (2).

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

658

BUTTERWORTH FILTERS

we verify that jL(2)/j at 0 is zero for j odd and equals

j!aj for j even. For the moment, let us normalize T( j0) 1.
This leads to a0 1 in Eq. (3). For a filter to be of order n,
a2n 2 0 in Eq. (3). From these considerations, to cancel
the maximum number of derivatives of L(2)and consequently those of T( j)at 0, we must choose aj 0 for
j 1 to 2n 1, leading to

1
0.9
0.8

H(j)

0.7
0.6
0.5

L(2 ) = 1 +  2 2n

0.4

0.2

n=4

0.1
0

which is similar to L(2) in Eq. (1) if we choose 1. The

Butterworth approximation is the answer we were looking
for. Two important considerations must be given on this new
parameter .

n=2

0.3

n = 10

n=7

1.5
2
(rad/s)

0.5

2.5

3.5

1. As A(0) 0 and A() is clearly a monotonically increasing function, controls the attenuation variation, or
gain ripple, in the pass band:

Figure 1. Magnitude of the Butterworth transfer function for n 2,

4, 7, and 10.

Ap = A(1) A(0) = 10 log10 (1 +  2 )

Butterworths contribution for approximating and synthesizing filters that are well behaved both in the pass band and
stopband was immediately recognized and still stands for its
historical and didactic merits. Even nowadays, compared with
others, Butterworths approximation is simple, allows simple
and complete analytical treatment, and leads to a simple network synthesis procedure. For these reasons, it is an invaluable tool to give students insight on filter design and to introduce the subject to the novice. From now on, we intend to
present the Butterworth filter with emphasis on this didactic approach.
The Butterworth approximation is an all-pole approximation, that is, its transfer function has the form
T (s) = k0 /D(s)

(2)

and its n transmission zeros are located at infinity.

The Butterworth approximation is sometimes called the
maximally flat approximation, but this denomination, first
used by Landon (3), also includes other approximations. The
idea of the maximally flat gain is to preserve filter gain as
constant as possible around the frequency at which the most
important signal components appear, by zeroing the largest
possible number of derivatives of the gain at that frequency.
The Butterworth approximation is just the all-pole approximation with maximally flat gain at 0.
MAXIMALLY FLAT APPROXIMATION
Let us consider the family of normalized low-pass all-pole filters of order n. We search for the approximation with maximally flat gain at 0. For all-pole approximations, L(2) is
a polynomial in 2. Comparing the polynomial L(2) and its
MacLaurin series

L(2 ) =

i=0

a2i 2i


2n

1 j L(2 ) 
=
j
j! j =0
j=0

(5)

It is interesting to notice that the pass-band ripple is

independent of the filter order n, depending only on .
On the other hand,

SOME COMMENTS ON BUTTERWORTH FILTERS

n


(4)

(3)

As = A(s ) A(0) = 10 log10 (1 +  2 s2n )

(6)

From Eqs. (5) and (6) we verify that the requirements for the pass band and stop band are satisfied if
 (100.1A p 1)1/2

(7)

and
n

log10 [(100.1A s 1)/ 2 ]

2 log10 s

(8)

2. As 22n (1/n)2n, Eq. (4) and consequently the filter

gain may be written as a function of 1/n instead of .
So 1/n is merely a frequency scaling factor that may be
normalized to 1 without loss of generality in the study
of the maximally flat approximation, yielding the original Butterworth approximation given by Eq. (1).
BUTTERWORTH TRANSFER FUNCTION
We are now interested in determining the filter transfer function T(s), which corresponds to Eq. (1). Using the analytical
continuation s/j (or 2 s2)

1
1 
|T ( j)|2 = T (s)T (s)|s= j =
D(s) D(s) s= j
(9)

1 
=
L(s2 ) s 2 = 2
and
L(s2 ) = D(s)D(s) = 1 + (s2 )n = 1 + (1)n s2n
we verify that the roots of L(s2) are the filter poles and their
symmetrical points with respect to the origin. The roots si of

BUTTERWORTH FILTERS

1.5

659

1.5
j

0.5

0.5

0.5

0.5

1.5
12 1 0.8 0.6 0.4 0.2 0

0.2

1.5
12 1 0.8 0.6 0.4 0.2 0

(a)

Figure 2. Butterworth filter poles for (a) n 4 and (b)

n 7.

(b)

L(s2) are

0.2

Table 1 shows the coefficients di and the Qi factors of the

poles of D(s) for n 1 to 7.
si = e j(2i+n1) /2n,

i = 1, 2, . . ., 2n
PHASE AND GROUP DELAY

where j (1). All roots si have unitary modulus and are

equally spaced over the unitary-radius circle. As the filter
must be stable, we take the roots si in the left-half s plane as
the roots pi of D(s) (the poles of the filter), that is,
pi = e j(2i+n1) /2n,

i = 1, 2, . . ., n

For n odd there exists a real pole at s 1; for n even all

poles are complex. Figure 2 shows the filter poles for n 4
and n 7.
Knowledge of the roots of D(s) allows us to calculate its
coefficients di, or to factor D(s) in second-order polynomials
(s2 s/Qi 1) where
Qi =

1
2 cos [(2i + n 1)/2n]

Group delay gives more practical information than phase

characteristics and is easier to calculate. From Eqs. (9) and
(10) we verify that T(s) may be written as the product of firstand second-order functions, and so the group delay is the addition of the group delay of each of these functions. Using

1 T (s)  

() = Ev

T (s) s
s= j
in these low-order functions, where Ev( ) is the even part of
( ), it is easy to show that the group delay is given by
() =

 1
1
1 + 2
+
2
1+
Qi 1 (2 1/Q2i )2 + 4
i

where the first term comes from the first-order term of T(s),
if it exists, and the summation is done over all second-order

for i 1, . . ., n/2 if n is even or i 1, . . ., (n 1)/2 if n is

odd, when a factor s 1 is also added.

D(s) =

n

i=0

d i si =

n/2

(s2 + s/Qi + 1)

i=1

Table 1. Coefficients and Q Factors for the

Butterworth Filters

for n even
(10)

(n1)/2

(s2 + s/Qi + 1) for n odd

(s + 1)
i=1

A curious property is that, as D(s) is real and its roots are

on the unitary-radius circle, its coefficients are symmetrical,
that is, di dni for i 0, . . ., n. Obviously d0 dn 1.

d1

d2

d3

Q1

Q2

Q3

1
2
3
4
5
6
7

1.0000
1.4142
2.0000
2.6131
3.2361
3.8637
4.4940

1.0000
2.0000
3.4142
5.2361
7.4641
10.0978

1.0000
2.6131
5.2361
9.1416
14.5918

0.7071
1.0000
1.3066
1.6180
1.9319
2.2470

0.5412
0.6180
0.7071
0.8019

0.5176
0.5550

660

BUTTERWORTH FILTERS

14

For a given source resistor Rs, P1() reaches its maximum

Pm when Z1( j) matches Rs, that is, at frequencies where
Z1( j) Rs.

12



 V () 2
 Re{Z ( j)}
P1 () =  in
1
Z1 ( j) 

10

() (s)

n = 10
8

Po () =
n=7

Pm =

n=4

n=2

0.5

1.5

(rad/s)
Figure 3. Group delay of Butterworth filters for n 2, 4, 7, and 10.

terms of T(s). The first term monotonically decreases from 1

to 0 as increases. The other terms begin as 1/Qi at 0,
peak to 2Qi at 1 1/8Qi2 1, and then decrease to zero
as further increases. The approximations hold for 4Qi2 1.
The result is that for the cases of interest, with Ap not too
large, say Ap 1 dB, and n not too small, say n 4, the group
delay of Butterworth filters is practically monotonically increasing in the pass band and is easily compensated by simple all-pass filters. Figure 3 shows the group delay for n 2,
4, 7, and 10. Remember that, due to the frequency scaling
used to reduce the pass-band ripple, the pass-band edge corresponds to 1/n 1.
SYNTHESIZING BUTTERWORTH FILTERS
The filter is implemented as a linear network synthesized to
exhibit the desired frequency behavior. Implementation is related to the technology chosen for the filter assemblage. Although progress has brought new technologies for synthesizing and implementing filters, the doubly loaded LC ladder
network with maximum power gain still remains the basis of
most synthesis procedures, due to the its low gain sensitivity
to the network components. This synthesis method is usually
very complex, but the peculiarities of Butterworth equations
allow simplifications that make this filter very adequate to
introduce the doubly loaded LC ladder network synthesis
method to students.
First, we already know a structure to be used with all-pole
filters. As the transmission zeros of a ladder network are the
poles of the series-branch impedances and the shunt-branch
admittances, a possible network topology is shown in Fig. 4
for n odd and even.
If we find a suitable Z1(s), the synthesis problem reduces
to the easy realization of a one-port network with impedance
Z1(s) through the extraction of poles at infinity, alternating
from the residual admittance and impedance (the chop-chop
method) until it remains only a constant, implemented by the
load resistor RL. The final topology will be given by Fig. 4.
As the LC network is lossless, the active power P1() going
into Z1( j) will be dissipated as active power P0() at RL.

|Vout ()|2
RL
|Vin ()|2
4Rs

where Re means the real part of . Butterworth filters

present maximum gain at 0, and at this frequency the
filter must transmit the maximum possible power to the load
RL. At 0 inductors act as short circuits, capacitors as open
circuits, and by inspection of Fig. 4 we verify that Z1( j0)
RL. For maximum power gain at 0 we choose RL Rs.
Still by inspection of Fig. 4, we verify that T( j0) 
. As
d0 1, we must choose k0 
in Eq. (2) and consequently
Eq. (1) becomes
|T ( j)|2 = 1/4L(2 )
We will use here the simple synthesis procedure described
in Ref. 4 and will make use of all simplifications allowed by
the Butterworth approximation. Let us introduce the filter
transducer function H( j) such that
|H( j)|2 =

R
Pm
1
= L
= L(2 ) = 1 + 2n
P1 ()
4Rs |T ( j)|2

measures the power rejection by the filter at frequency . As

Pm P1(), H( j)2 1, and the equality is reached only at
the frequencies of maximum power gain. Let us also introduce
the filter characteristic function K( j) such that
|K( j)|2 = |H( j)|2 1 = 2n

Rs

L2

Vin

C1

Ln 1

C3

Vout

Cn

RL

Z1
(a)
Rs

Vin

L2

C1

Ln

C3

Cn 1

Vout

RL

Z1
(b)
Figure 4. Low-pass all-pole doubly loaded LC ladder network for (a)
n odd and (b) n even.

BUTTERWORTH FILTERS
Table 2. Element Values for the Butterworth Filter
n

A1

A2

A3

A4

1
2
3
4
5
6
7

2.0000
1.4141
1.0000
0.7653
0.6180
0.5176
0.4450

1.4142
2.0000
1.8478
1.6180
1.4142
1.2470

1.0000
1.8478
2.0000
1.9319
1.8019

0.7653
1.6180
1.9319
2.0000

is also a measurement of the power rejection by the filter at

frequency . As H( j)2 1, K( j)2 0, and the equality is
reached only at the frequencies of maximum power gain.
After some algebraic manipulation and using analytical
continuation to obtain
sn
K(s)
=
H(s)
D(s)

4. Obtain the normalized low-pass prototype by frequencyscaling the standard filter, multiplying all reactive elements by 1/n.
5. Invert step 1, that is, denormalize the low-pass prototype obtained in step 4.
CONCLUSIONS
Butterworths paper is the touchstone of modern filter-approximation theory. However, its low selectivity when compared to that of other approximations restricts its use to situations that require low sensitivity at the center of the pass
band and/or a good group delay flatness. Probably the major
importance of Butterworth filter nowadays is for didactic purposes. Its simplicity and complete analytical formulation
make it the best option to introduce filter synthesis to students.
BIBLIOGRAPHY

it is possible to show that

K(s)
D(s) sn
H(s)
= Rs
Z1 (s) = Rs
K(s)
D(s) + sn
1+
H(s)
1

and Z1(s) may be easily synthesized by the chop-chop method,

concluding the synthesis procedure.
For Butterworth filters the number of frequency points
with maximum power transfer is maximum (all concentrated
at the origin). All-pole filters with this characteristic are symmetrical if n is odd and antisymmetrical if n is even, that is,
Ai is equal to An1i for all i, where Ai denotes the numerical
value of either Ci or Li. Table 2 presents the values of Ai for
n 1 to 7 and for Rs RL 1 .
There exists a simple equation that directly provides the
component values, but its deduction is rather complicated.
For Rs RL 1 ,
Ai = 2 sin(2i 1)/2n

661

(11)

For a more complete discussion on the synthesis of Butterworth ladder network design, even with arbitrary resistors
Rs and RL, as well as the historical facts surrounding the discovery of those formulas, the reader is referred to Refs. 5 to 7.
DESIGNING BUTTERWORTH FILTERS
Only few steps are necessary to design a Butterworth filter:
1. Obtain the normalized low-pass filter and its restrictions Ap, As, and s.
2. Determine and n using Eqs. (7) and (8).
3. Synthesize, use tables, or use Eq. (11) to obtain the
standard filter of order n.

1. S. Butterworth, On the theory of filter amplifiers, Wireless Engineer, Vol. 7, pp. 536541, 1930. Reprinted in M. E. Van Valkenburg (ed.), Circuit Theory: Foundations and Classical Contributions, from J. B. Thomas (series ed.), Benchmark Papers in
Electrical Engineering and Computer Science, Pennsylvania: Dowden, Hutchinson & Ross, 1974.
2. V. Belevitch, Summary of the history of circuit theory, Proc. IRE,
50: 848855, 1962. Reprinted as (1).
3. V. D. Landon, Cascade amplifiers with maximal flatness, RCA
Rev., 5: 347362, 1941.
4. G. Daryanani, Principles of Active Network Synthesis and Design,
New York: Wiley, 1976.
5. L. Weinberg, Explicit formulas for Tschebyscheff and Butterworth ladder networks, J. Appl. Phys., 28: 11551160, 1957.
6. H. J. Orchard, Synthesis of ladder networks to give Butterworth
or Chebyshev response in the pass band (review), IRE Trans. Circuit Theory, CT-1 (Dec.): 37, 1954.
7. L. Weinberg and P. Slepian, Takahasis results on Tchebycheff
and Butterworth ladder networks, IRE Trans. Circuit Theory, CT7 (June): 88101, 1960.
8. M. E. Van Valkenburg, Introduction to Modern Network Synthesis.
New York: Wiley, 1960.
9. G. C. Temes and J. W. LaPatra, Circuit Synthesis and Design,
New York: McGraw-Hill, 1977.
10. DeV. S. Humpherys, The Analysis, Design, and Synthesis of Electrical Filters, Englewood Cliffs, NJ: Prentice-Hall, 1970.
11. L. Weinberg, Network Analysis and Synthesis, New York:
McGraw-Hill, 1962.
12. A. S. Sedra and P. O. Brackett, Filter Theory and Design: Active
and Passive, Matrix, 1978.

LUIZ P. CALOBA
MARCELLO L. R. dE CAMPOS
Universidade Federal do Rio de
Janeiro

BUYING COMPUTERS. See COMPUTER SELECTION.

CASCADE NETWORKS

to the higher-order circuit as an additional term.

Cascade design refers to the procedure in which the designer chooses to factor a complex circuit requirement of
order n 2 that is difcult or impossible to realize in its
given form into a number of simpler specications that result in more practical circuits and are more readily implemented. These are then connected in a chain, that is, in a
cascade circuit, to realize the specied requirements. Typically, one factors a required high-order transfer function

Example 1. We now illustrate the decomposition of a

higher-order transfer function into a product of lower-order
transfer functions. The transfer function of a sixth-order
lter, with a normalized frequency parameter, is

To realize this lter as a cascade circuit, the numerator

and denominator are factored by a suitable root-nding
algorithm as follows:
with n m and n > 1, into a number of lower-order functions Tj (s). H(s) in Eq. (1) is a ratio of two polynomials N(s)
and D(s) of degrees 2m and 2n, respectively. We selected,
without loss of generality, the coefcient a2n = 1, because
numerator and denominator can always be divided by a2n .
The realization then connects the functions Tj (s) such that
In this case, n = 3 and the numerator is odd, that is, N(s)
is factored into a product of two second-order factors and
a rst-order factor, and the function is presented as the
product of three terms according to Eq. (2).
that is, the total transfer function is obtained from the
product of lower-order functions. Examples of cascade synthesis extend from the early days of electronics when
RLC circuits were isolated by vacuum-tube ampliers
to the present-day discrete or fully integrated realizations of active lters (RC circuits augmented or isolated
by operational ampliers) and switched-capacitor circuits
where resistors in active lters are replaced by periodically
switched capacitors. Cascade design is used widely not only
for the implementation of magnitude and phase responses
but also for group-delay equalizers. The goal is to realize
H(s) via simpler circuits in an efcient way with low sensitivities to component tolerances. The sensitivity issue will
be addressed below.
In Eq. (1), we have labeled the degrees of the numerator and denominator polynomials N(s) and D(s) as 2m and
2n, respectively, to emphasize the fact that we assume the
degrees to be even. Both N(s) and D(s) can therefore be
factored into the product of second-order pole-zero pairs,
as expressed in the following form:

The notation assumes that both N and D are of degree 2n;

if m < n, the numerator will contain 2(n m) factors of
unity. If the degree of H(s) is odd, the function can always
be factored into the product of even terms as shown in Eq.
(3) and a rst-order factor. First-order sections can easily
be realized by a passive RC network and can be appended

Example 2. This example illustrates how cascading of

lower-order sections enables the realization of an amplier with a large inverting gain, K = 1,000,000. The bandwidth must be at least 5 kHz and the smallest resistor used
should be 1 k
to minimize currents and loading effects.
If one attempts to realize the amplier in the usual way
with a 741-type operational amplier as shown in Fig. 1(a),
a 1000 M
= 1 G
= 109
resistor is required. This resistor is too large to be realized; it is essentially an open
circuit and leaves the operational amplier operating in
an open loop. The bandwidth would be less than 1 Hz.
Because of such processing or technology constraints, it
is convenient, even necessary, to partition the prescribed
gain into several factors, such as K = K1 K2 K3 = (100)
(100) (100), and connect the resulting circuits in cascade [Fig. 1(b)]. In this conguration, the second amplier
picks up the output of the rst one with gain 100 and
multiplies it by a second factor 100, and so on, to realize
K = 1,000,000 as required. Of course, with this large amplication of the factor 106 , the designer must pay careful
attention to avoid signal-level distortion. This issue will not
be addressed here. At the expense of additional circuitry,
cascade design enabled us to realize the specications with
the required gain, bandwidth (it is larger than 8 kHz), and
practical component values. Without the cascade method,
the specications placed such demands on the components
to render the circuit unrealizable.
In a similar manner, high-order active lters described
by a transfer function, H(s), are most frequently designed
as a cascade of low-order circuits. The method results in
lters that can be adjusted (or tuned) easily and have low
sensitivity to component tolerances Ref. 1. In addition, the
design method is completely general, in that transfer func-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Cascade Networks

Figure 1. (a) Proposed operational amplier circuit to realize K = R2 /R1 = 1,000,000. The
circuit is not practical because of the large resistor R2 and because the minimal feedback limits the
bandwidth to very low values; (b) practical realization as a cascade of three ampliers with gain
Ki = 100.

tions of arbitrary form can be realized. Naturally, to keep

the circuits stable, that is, to prevent them from oscillating,
the poles, the roots of D(s), are restricted to the left half of
the complex s plane (0j > 0, 1j > 0). The transmission
zeros, the roots of N(s), however, can be anywhere in the s
plane; their location depends only on the desired response.
An additional advantage is that in cascade design the designer can focus on the low-order sections Tj (s) that are
generally simpler to implement than the high-order function H(s). The low-order sections are then simply connected
in a chain, or cascaded, as shown in Fig. 2. If Tj (s) is dened
as a voltage transfer function,
T j (s) =

Vo j
Vi j

where we assumed that the component x is located in section j, and partial derivatives are used because H is a function of s and of all circuit components. Customarily, both
the transfer function deviation H and the component deviation x are normalized to H and x, respectively, so that
we obtain from Eq. (8) with Eq. (2)

These quantities are the classical sensitivities, dened as

(5)

the total transfer behavior realized by that circuit is derived to be

Vout
Vo1 Vo2 Vo3
Vo(n1) Vout
H(s) =
=
...
(6)
Vin
Vin Vo1 Vo2
Vo(n2) Vo(n1)
= T1 (s)T2 (s) . . . Tn1 (s)Tn (s)
as required by Eq. (2). Equation (7) holds because the connection guarantees that the input voltage of section j is
equal to the output voltage of section j 1, Vij = Vo(j 1) .
SENSITIVITY
The sensitivity of a cascade realization of a transfer function H(s, x) to a component x is calculated via derivatives,

Equation (6) can be rewritten in the form

which means that the percentage error in a function F(x)

caused by a component with tolerance x is computed by
multiplying the percentage error of the component by the
sensitivity. From Eq. (9) we have the important result

which says that in a cascade circuit the sensitivity of the

total transfer function H to a component is equal to the
sensitivity of the section Tj that contains the component.
In contrast to noncascaded implementations, in which the
sensitivity to a component may depend on all poles and
zeros and may become very large Ref. 1, here it depends
only on the pole and zero in section j and is not affected by

Cascade Networks

Figure 2. Cascade realization of a 2nth-order transfer function. The realized transfer function is
the product of the individual function realized by the blocks T1 .

any of the other sections. Equation (12) veries formally

the intuitive expectation that the cascade circuit with good
sensitivity behavior should be built from low-sensitivity
sections.
CASCADING CONDITION
A general condition that must be satised for Eq. (7) to
hold in the simple form shown is that the sections do not
load each other and do not otherwise interact. This condition requires that the output impedance Zout of any section
ideally is zero and its input impedance Zin innite. Figure
3 illustrates this requirement for two sections T1 and T2 ,
dened as
T1 (s) =

Vn1
V1

and

T2 (s) =

Vn2
Vi2

Vn1 and Vn2 are the voltages at the respective internal

nodes n1 and n2 in Fig. 3. The complete sections, realistically modeled to include a nite input impedance Zi (s) and
output impedance Zo (s), are contained in the dashed boxes.
Assuming that V1 is an ideal voltage source so that Zi1 has
no effect and that there is an open circuit at Vo2 so that no
current ows through Zo2 , analysis of the conguration in
Fig. 3, starting from the output, yields
Vo2

T2 (s)Vi2 = T2 (s)

T2 (s)

Zi2 (s)
Vn1
Zi2 (s) + Zo1 (s)

Zi2 (s)
T1 (s)V1
Zi2 (s) + Zo1 (s)

(12)

Thus, the transfer function of the two-section cascade is

H(s) =

Vo2
Zi2 (s)
= T1 (s)T2 (s)
V1
Zi2 (s) + Zo1 (s)

(13)

rather than the simple product T1T2 intended. The problem

is that the current through Zo1 is not zero, that is, section
1 is loaded by section 2. Equation (15) indicates that the
desired result is achieved provided that
|Zi2 ( j)|  |Zo1 ( j)|

(14)

Ideally, Zi2 = and Zo1 = 0. Condition (14) is satised in

the circuit in Fig. 1(b) because the operational amplier
circuits with feedback and a gain of 100 have very small
output resistance (Rout < 50
) compared to the input resistance of the following stage (Rin = 1 k
). The condition
to permit cascading is, therefore, that the input impedance
of the loading section must be much larger than the output
impedance of the driving section so that the voltage divider
factor that multiplies the ideal product T1T2 in Eq. (15) is
as close to unity as possible. The voltage divider ratio is
written on purpose in terms of impedances as functions of
s or j to emphasize that, in practice, the designer needs to

contend with more than a resistor ratio that would multiply T1T2 simply by a frequency-independent constant.
To illustrate this point consider the example of a secondorder low-pass lter being built by cascading two identical
rst-order sections as in Fig. 4. The sections have the transfer function,

The intent is to multiply the transfer functions T1 and T2

so that
Vo2
1
1
H(s) =
= T1 (s)T2 (s) =
V1
sCR + 1 sCR + 1
(16)
1
=
(sCR)2 + 2sCR + 1
However, because of the nite impedances identied in the
gure,
Zi2 = R +

1
sC

and

Zo1 =

1
sC + 1/R

by Eq. (15) the proposed circuit in Fig. 4 realizes the transfer function
1
R+
Vo2
1
sC
2
H(s) =
=(
)
1
R
V1
sCR + 1
(17)
(R +
)+(
)
sC
sCR + 1
2
1
(sCR + 1)
1
=
=
(sCR + 1)2 (sCR)2 + 3sCR + 1
(sCR)2 + 3sCR + 2
The desired performance is completely altered as can be
conrmed by direct analysis. It is seen that the nite
frequency-dependent input and output impedances substantially change the desired transfer function. If cascading must be used but Eq. (16) is not satised, buffering using a voltage follower can be employed as in Fig. 5 so that
no current is drawn from the rst section and the second
section is driven by a nearly ideal voltage source.
To repeat the important condition that must be satised
if two circuits are to be connected in cascade: the trailing
section must not load the leading section. The circuits to be
cascaded can be of low order, high order, active, passive, or
any desired combination; the loading restriction does not
change. For designing high-order active lters, the cascade
connection normally consists of rst- and second-order active building blocks because they can be cascaded directly
with no need of buffering: since active circuits usually have
an operational amplier output as their output terminal,
unbuffered cascading is possible because the operational
amplier output resistance in a feedback network is very
small (see Example 2). On the other hand, as in the example of Fig. 4, it can be expected intuitively that passive
circuits can generally not be connected in cascade without

Cascade Networks

Figure 3. Two-section cascade with nite input and output impedances. The second section loads
the rst one unless its input impedance, Zi2 , is much larger than the output impedance, Zo1 , of the
rst section.

Figure 4. Cascade connection of two rst-order passive lowpass sections with nite input and output impedances. The two
modules interact so that the realized transfer function is not
equal to the product of the two rst-order functions. Isolating
the sections is required as shown in Fig. 5.

Figure 5. Two low-pass modules isolated by an operational amplier. The unity-gain voltage follower isolates the sections performance so that the total transfer function is the product of the two
rst-order modules.

buffering because the condition in Eq. (16) will rarely be

satised.

THE DESIGN APPROACH AND TRADE-OFFS

The problem to be addressed is how the transfer function
of Eq. (1) can be realized in an efcient way with simple
low-order circuits and low sensitivities to component tolerances. As was mentioned, the sensitivity behavior of highorder lter realizations shows Ref. 1 that, in general, it is
not advisable to realize the transfer function H(s) of Eq. (1)
in the so-called direct form, using only one or maybe two
operational ampliers embedded in a high-order passive
RC network. Although it is possible in principle to realize
Eq. (1) in direct form, the resulting circuits are normally
so sensitive to component tolerances that reliable performance cannot be expected in practice. A further disadvantage of the direct synthesis method is the use of a very
large number of passive components to realize a function
of given order.
In the cascade approach, the high-order function H(s)
is factored into functions of second order as indicated in
Eq. (3). The resulting biquadratic functions are realized by
the methods discussed elsewhere in this encyclopedia and
connected in cascade such that their product implements
the prescribed function H(s). The cascade method is used

widely in industry because it is applicable generally, is well

understood, very easy to implement, and efcient in its use
of active devices (as few as one operational amplier per
pole pair). It uses a modular approach and results in lters that for the most part show satisfactory performance
in practice. One of the main advantages of cascade lters
is that they are very easy to tune because each biquadratic
section, referred to as biquad in the literature, is responsible for the realization of only one pole pair and zero pair:
the realizations of the individual critical frequencies of the
lter are decoupled from each other. The disadvantage of
this decoupling is that for lters of high order, say larger
than order eight (n > 4), with stringent requirements and
tight tolerances, cascade designs are often found to be still
too sensitive to component variations in the passband. In
these cases, ladder simulations may lead to more reliable
circuits Ref. 1.
As shown in Eq. (3), the high-order transfer function
H(s) is factored into a product of second-order blocks,

where the denominator is expressed in terms of the usual

lter parameters, the quality factor Q and the pole frequency 0 . We have also introduced a suitably dened gain
constant, kj , for example such that the leading coefcient in

Cascade Networks

the numerator of the gain-scaled transfer function tj (s) is

unity or such that |tj (j0j )| = 1. The sections Tj (s) are quite
arbitrary; for example, they can realize a low-pass function
(2j = 1j = 0), a bandpass function (2j = 0j = 0), a highpass function (1j = 0j = 0), or a pair of nite transmission
zeros on the j axis (1j = 0), as the process does not change.
Because second-order lter sections can be built to realize
arbitrary functions of the form of Eq. (21), cascade design
is very general in permitting the realization of any type of
stable transmission requirement. If we then may assume
that the output impedances of the biquadratic functions
are sufciently small (compared to the input impedances),
all second-order blocks can be connected in cascade, Fig.
2, without causing mutual interactions due to loading, and
the product of the biquadratic functions is realized as required by Eq. (7).
Although this simple process leads in a straightforward
way to a possible cascade design, it leaves several questions
unanswered:
1. Which zero should be assigned to which pole in Eq.
(3) when the biquadratic functions Tj (s) are formed?
Since we have n pole pairs and n zero pairs (counting
zeros at 0 and at ) we can select from n factorial, n!
= 1 2 3 n, possible polezero pairings.
2. In which order should the biquadratic sections in Eq.
(7) be cascaded? Does the cascading sequence make
a difference? For n biquadratic sections, we have n!
possible sequences.
3. How should the gain constants kj in Eq. (21) be chosen to determine the signal level for each biquad? In
other words, what is the optimum gain distribution?
Because the total transfer function is the product of the
biquadratic sections, the selections in steps 13 are quite
arbitrary as far as H(s) is concerned. However, they do determine signicantly the dynamic range, that is, the distance between the maximum possible undistorted signal
and the noise oor: the maximum and minimum signal levels throughout the cascade lter can be shown to depend on
the choices in steps 13. Although the sensitivities to component tolerances are functions of polezero pairing, the
effect usually is not very strong. For a detailed treatment
see Refs. 2 and 3. Also, the selection of polezero pairing
for best sensitivity can be shown to conict often with the
choice necessary for best dynamic range. Since the implementation of the blocks Tj (s) normally makes use of active
devices, such as operational ampliers, depending on the
operating frequency, the maximum undistorted signal voltage that a lter can process is limited either by the power
supply or by the slew rate of the operational ampliers.
The optimal cascading routine to be discussed
(polezero pairing, section ordering) and gain assignment,
is entirely general and does not depend on the transfer
function or its type. It is independent of the actual implementation of the second-order building blocks. The designer may choose any convenient technology and the circuit architecture that seems preferable from the point of
view of sensitivity, numbers and kinds of elements, values
and element value spreads, power consumption, or other

practical considerations.
DYNAMIC RANGE
Since it is the dominant effect of polezero pairing, section
ordering, and gain assignment, we will be concerned here
only with dynamic range issues. To help tackle the problem,
let us label the maximum signal level that can be handled
with no distortion as Vo,max . We assume that it is measured
at the output of the biquadratic sections. This assumption
will always be correct in single-amplier biquadratic sections for which section output and operational amplier
output are the same. In multiamplier biquadratic sections, each operational amplier output must be evaluated
and the maximum operational amplier output voltage in
the biquadratic section must be determined. To avoid overdriving any operational amplier sooner than any other
one inside a biquadratic section, it is intuitively reasonable that any available design freedom in the biquadratic
sections should be chosen such that all operational ampliers see the same signal level. If this is not possible, that
is, if the undistorted output voltage Voi of section i is only
a fraction 1/qi of the maximum internal voltage, with qi >
1, Voi in the following equations must be replaced by qiVoi .
For simplicity, we shall assume in our discussion that the
sections can be designed such that qi = 1.
We must ensure then that the signal level at any section
output, |Voi (j)|, satises
max|Voi ( j)| < Vo,max ,

0 ,

i = 1, . . . n

(19)

Note that this condition must indeed be satised for all

frequencies and not only in the passband because large
signals even outside the passband must not be allowed
to overload and saturate the operational ampliers: when
operational ampliers are overdriven, their operation becomes nonlinear. The circuit, however, may still act as a
lter and remove the higher harmonics that are generated
by the nonlinear operational amplier operation. The problem that arises when saturating the operational ampliers
is, therefore, not so much harmonic distortion of the signal
but changed operating points, intermodulation distortion,
and deviations of the magnitude response Ref. 1.
The lower limit of the useful signal range is set by the
noise oor. If in the passband of a cascade lter the signal at
an internal stage becomes very small, it must be amplied
again to the prescribed output level. From any point in the
cascade of lter stages, say at the output of stage i, signal
and noise are amplied by the same amount, namely,

Consequently, the signal-to-noise ratio will suffer if in the

cascade lter the signal suffers in-band attenuation, that
is, if it is permitted to become very small. The function
H+ i (s), dened in Eq. (23), is referred to as the noise gain
from the output of section i to the lter output. Thus, the
second condition to be satised by the output voltage of any
biquadratic section is
min|Voi ( j)| max

for L U ,

i = 1, . . . n (21)

Cascade Networks

L and U are the lower and upper, respectively, corners of

the passband. In this case we are, of course, only concerned
with signal frequencies in the passband, because in the
stopband the signal-to-noise ratio is of no interest. Note,
however, that for a white noise input the output noise spectrum of a lter section has the same shape as the square
of the transfer function magnitude, which means that the
highest noise response occurs at the pole frequencies with
the highest Q values. Since these are mostly found just beyond the specied corners of the passband they would not
be included in the measurement dened in Eq. (24). Therefore, to avoid decreased dynamic range caused by possibly
large noise peaks at the passband corners, it is advisable to
extend the frequency range beyond the specied passband
corners, L and U , into the transition band to cover the
pole frequencies with the highest Q values.
The steps of polezero pairing, section ordering, and
gain assignment will now be chosen such that the conditions in Eqs. (22) and (24) are satised. It must be emphasized that these steps do not just amount to minor adjustments when designing a cascade lter, but that the cascade
circuit will likely not perform to specications in practice
unless these steps are taken at the design stage.
Pole-Zero Pairing
According to Eqs. (22) and (24), the polezero pairing
should be chosen such that, in a given section, Mi =
max|Voi (j)| is minimized at all frequencies, and mi =
min|Voi (j)| is maximized in the passband. In other words,
using Eq. (21), |ti (j)| should be as at as possible in the
frequency range of interest. Notice that Mi may lie outside
and mi at the edge of the passband, and that the actual
minimum of the magnitude |ti (j)| lies in the stopband and
is of no concern. As the values of Mi and mi change when the
relative positions of the poles and the zeros of ti (s) are altered, the polezero assignment must be chosen such that
the ratio Mi /mi is as close to unity as possible, which means
that for each biquadratic function the measure of atness

should be minimized. The optimal polezero assignment

for the total 2nth-order cascade lter is then the one that
minimizes the maximum value of di :

Algorithms that accomplish this task are available in the

literature Refs. 4 to 7. Even in fairly simple low-order cases
the problem of polezero assignment can be quite computation intensive; it requires substantial software and computer resources.
If the appropriate computing facilities are not available,
a simple solution that provides good suboptimal results is
simply to assign each zero or zero-pair to the closest pole
Refs. 48. On occasion, depending on system requirements,
we may also preassign some polezero pair(s) and leave
them out of the remaining pairing process. For instance, if
the numerator contains a term s2, we may prefer to factor it
into s s instead of s2 1, that is, we may prefer to realize

two second-order bandpass sections instead of a high-pass

and a low-pass section.
Example 3. Determine the optimal pole-zero pairing for
the transfer function of Eq. (5) of Example 1. The transfer
function was

The zeros are located at z1 = 0 and z2 = , z3,4 = j0.5, and at

z5,6 = j1.5, and the poles are at p1.2 = 0.045 j0.9099, p3,4
= 0.1 j1.0, and p5,6 = 0.05 j1.085. According to the
approximate assignment rule just stated, we should pair
(z1,2 , p3,4 ), (z3,4 , p1.2 ), and (z5,6 , p5,6 ). This choice is indicated
in Eq. (28):

Section Ordering
After the pole-zero assignment has been solved, the optimal
ordering sequence must be determined out of the n! possibilities in which the biquadratic sections can be connected
to form the cascade network. For example, for the sixthorder network with three sections in Example 3, there exist six possible ways to cascade the biquadratic functions:

The best sequence is the one that nds the ordering that
maximizes the dynamic range. The procedure is completely
analogous to the earlier discussion where polezero pairs
were chosen to keep the transfer functions of the individual
sections as at as possible. Now the cascade connection is
designed such that the transfer functions

from lter input to the output of the ith intermediate biquadratic section are as at as possible. Hn is, of course,
equal to the total transfer function H. This will help ensure that the maximum signal voltages do not overdrive
the operational ampliers and that, over the passband,
the smallest signal stays well above the noise oor. Consequently, the relationships in Eqs. (22) and (24) must be
satised,
min|Voi ( j)| < Vo,max
min|Voi ( j)| max

for

0
L U

(26)
(27)

where Voi (s) is now the output voltage of the cascade of the
rst i sections when driven by an input signal Vin (s). With
Hi (s) given in Eq. (30), we dene the two measures
Mi

=
=

Voi ( j)
max|Voi ( j)|
= max|
|
|Vin ( j)|
Vin ( j)
max|Hi ( j)| for 0

(28)

Cascade Networks

and
mi

=
=

min|Voi ( j)|
Voi ( j)
= min|
|
|Vin ( j)|
Vin ( j)
min|Hi ( j)| for L U

(29)

and require again that the atness criterion of Eq. (25)

be minimized, now, however, by choice of the cascading sequence,

The optimal sequence is the one that minimizes the maximum number di as prescribed in Eq. (26). Note that we
do not have to consider dn because, with all sections connected in the cascade lter, dn is nothing but a measure
of the prescribed passband variations (the ripple). With
the problem identied, the optimum cascading sequence
can be found in principle by calculating di for all n! sequences and selecting the one that satises Eq. (35). As in
the polezero assignment problem, a brute-force optimization approach involves a considerable amount of computation, and more efcient methods have been developed that
use linear programming techniques, such as the branch
and bound method of Refs. 57, or back track programming Ref. 9. The necessary computer algorithms are described in the literature.
If the required software routines are not available, the
designer must pick a cascading sequence that is based on
experience or intuition. A selection that is often very close
to the optimum is the one that chooses the section sequence
in the order of increasing values of Qi , that is,

so that the section with the attest transfer function magnitude (the lowest Q) comes rst, the next attest one second, and so on. The possible choices are frequently further
limited by other considerations. For example, it is often desirable to have as the rst section in the cascade a low-pass
or a bandpass section so that high-frequency signal components are kept from the ampliers in the lter in order to
minimize slew-rate problems. Similarly, the designer may
wish to employ a high-pass or a bandpass section as the last
section in order to eliminate low-frequency noise, dc offset,
or power-supply ripple from the lter output. In such situations, the optimum sequencing is performed only on the
remaining sections.
The following example illustrates some of the steps discussed.
Example 4. Continue Example 3 to nd the optimal cascading sequence for the three second-order sections. Since
the coefcient of s in the denominators of the second-order
sections of Eq. (28) equals 0i /Qi , and the constant coefcient equals 2 0i , we have

Using Eq. (31) and using the section numbering in Eq. (28),
the optimal ordering is, therefore, T2T1T3 . If instead the design were to emphasize the elimination of high-frequency
signals from the lter and low-frequency noise from the
output, the ordering T2T3T1 ,

would be preferred because the bandpass section, T2 , has

the best high-frequency attenuation, and section T1 provides reasonable attenuation at low frequencies (0.25/0.83
= 0.3 10.4 dB), whereas section T3 has a high-frequency
gain of 1 and amplies low-frequency noise by more than
2.25/1.18 = 1.91 5.6 dB. This suboptimal ordering gives
almost identical results to the optimal one, T2T1T3 , because
Q 1 Q3 .
Gain Assignment
The last step in the realization of a cascade lter is the
assignment of the gain constants. Generally, the selection
is again based on dynamic range concerns with the goal of
keeping the signals below amplier saturation limits and
above the system noise oor. To get a handle on the process, we note that the circuit is linear and all voltages rise
in proportion to Vin . It is clear then that the maximum
undistorted input signal can be processed if we choose the
gain constants such that all internal output voltages Voi , i
= 1, . . . , n 1, are equal in magnitude to the presumably
prescribed magnitude of the output voltage, Von :
max|Voi ( j)| = max|Von ( j)| = max|Vout ( j)|,
i = 1 = 1, . . . n 1
Assuming as before that the output voltage of the biquadratic sections reaches the critical magnitude, this
choice ensures that for a given signal level none of the operational ampliers in the blocks of Fig. 2 is overdriven
sooner than any other one. Note, however, the earlier comments about precautions necessary in multiamplier biquads.
For the analysis it is convenient to use the notation of
Eqs. (2), (21), and (30), that is,

and, for the intermediate transfer functions,

Furthermore, we introduce the constant

such that

Cascade Networks

is the prescribed gain. Similar to the denition of Mn , let us

denote the maxima of the intermediate n 1 gain-scaled
transfer functions by Mi , that is,

To make max|Vo1 (j)| = max|Vout (j)|, we then obtain the

equation k1 M1 = KMn , that is,

Similarly, k1 k2 M2 = KMn , that is, with Eq. (45),

results in max|Vo2 (j)| = max|Vout (j)|. Proceeding in the

same manner yields

Choosing the gain constants as in Eqs. 45, 46, 47 guarantees that all operational ampliers see the same maximum voltage to ensure that the largest possible signal can
be processed without distortion. Note that changing the total gain of the n-section cascade lter affects only K, that
is, k1 . The voltages in all other sections Ti (s), i = 2, . . . , n,
increase or decrease proportionally, but their relative magnitudes stay the same, as determined by ki in Eq. (47).
Example 5. Continue Example 4 to nd the optimal gain
constants for the three second-order sections so that their
maximum output levels are equalized. The specied midband lter gain is 10 dB. Use the section ordering in Eq.
(38).
From Eq. (43), we nd

corresponding to the prescribed gain of 10 dB. The maxima

Mi can be computed as

29 dB rather than 10 dB, it is necessary only to alter the

rst section in the cascade from k1 = 3.16 to

to achieve the new circuit for which dynamic range is still

optimized.
To demonstrate that gain equalization is very important
in cascade realizations, consider the case where equalization is not performed. Had the designer chosen all ki = 1
as in Eq. (38), the output levels would have been 13.9 dB
at Vo1 , 31.9 dB at Vo2 , and 41.3 dB at Vo3 . Quite apart from
the specied gain of 10 dB not being realized, the difference of a factor of 41.3 dB 13.9 dB = 27.4 dB = 23.4 in
operational amplier output voltages would likely result
in gross distortions unless the input voltage is kept very
small.
BIBLIOGRAPHY
1. R. Schaumann M. S. Ghausi K. R. Laker Design of Analog Filters: Passive, Active RC and Switched Capacitor, Englewood
Cliffs, NJ: Prentice Hall, 1990.
2. R. Schaumann and M. A. Van Valkenburg, Design of Active Filters, New York, NY, Oxford University Press, 2001.
3. M. S. Ghausi K. R. Laker Modern Filter Design, Englewood
Cliffs, NJ: Prentice Hall, 1981.
4. G. S. Moschytz Linear Integrated NetworksDesign, New York:
van Nostrand Reinhold, 1975.
5. S. Haln An optimization method for cascaded lters, Bell Syst.
Tech. J., 49: 185190, 1970.
6. S. Haln Simultaneous determination of ordering and amplications of cascaded subsystems, J. Optimiz. Theory Appl., 6:
356360, 1970.
7. E. Luder

Optimization of the dynamic range and the noise distance of RC-active lters by dynamic programming, Int. J. Circuit Theory Appl., 3: 365170, 1975.
8. A. S. Sedra P. O. Brackett Filter Theory and Design: Active and
Passive, Portland, OR: Matrix, 1978.
9. W. M. Snelgrove A. S. Sedra Optimization of dynamic range in
cascade active lters. In Proc. IEEE Int. Symp. Circuit Syst.,
1978, pp. 151155.

ROLF SCHAUMANN
Portland State University,
Portland, OR

by evaluating the functions in Eqs. (43) and (44). With Mi

known, and using Eq. (48), Eqs. (45) and (47) give

that is

These values result in all section outputs being equal to

KM3 = 3.16 times the input voltage level for a uniform gain
of 10 dB. If the designer were to nd out later that system
performance would improve for a different lter gain, say,

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

CELLULAR ARRAYS
History
This section gives a brief overview on cellular array architectures and related computing principles. Cellular
arrays are massively parallel computing structures composed of cells placed on a regular grid. These cells
interact locally, and the array can have both local and global dynamics. Indeed, it can be shown that in
approximating any partial differential equation (PDE), continuous in space and time, one can use a cellular
array as a computing environment, either in software simulation or in analog or digital hardware emulation.
Two cellular array structures will be discussed, in detail: (i) cellular automata (CA)discrete in space, time,
and value, and (ii) cellular nonlinear or neural networks (CNN)discrete in space and continuous in time
and value. It will be shown that there is a biological relevance and motivation behind promoting cellular
architectures as good prototypes for parallel computing. It is discussed how a stored-program analog array
computer can be built, the CNN Universal Machine (CNN-UM), which makes it possible to synthesize novel
spatiotemporal algorithms. Various physical implementations will be discussed, with emphasis on integrated
array sensing and reconfigurable computing, that is, visual microprocessor architectures embedding stored
programmability. Some application potentials will also be highlighted in engineering, biology, chemistry, and
physics.
Historically, research on cellular arrays was initiated by von Neumann (1) in the 1960s, who studied the
homogeneous structure of cellular automata and its evolution as a general framework for modeling complex
structures. Such a structure consists of a set of cells, each one capable of performing only a set of primitive
operations. Depending on the interconnection pattern among the cells and the initial content, the structure
evolves through a sequence of states. With the introduction of CA, von Neumanns primary interest was to
derive a computationally universal cellular space with self-reproducing and self-repair configurations. After
a thorough study, he framed a universal CA with a set of transition rules involving five-neighborhood cells
(a cross-shaped neighborhood of a cell), each having 29 distinct states. The transition function with this
relatively small set of states turned out to be sufficient to achieve a powerful set of elementary operations: local
logical operations, wire-branching, transmission, relative delays, construction, and destruction. Based on these
operations he successfully synthesized various organs (pulser, decoder, coded channel, etc.) and higher-level
functions (e.g., sensing); furthermore, he proposed a universal computer. Following this pioneering work, several
researchers attempted to improve the construction of von Neumanns cellular space (234), and others started
analyzing CA with the tools of abstract algebra, topology, and measure theory (567) with the ambitious goal
of developing a unified theory of cellular models (8910). In this first phase of CA research already a number of
applications were proposed, including parallel language recognition, image processing, and biological modeling.
The new phase of activities in CA research is due to Wolfram (11, 12) in the early 1980s, who pioneered the
investigation of CA as mathematical models for self-organizing statistical systems. He focused on a simplified
structure: a discrete lattice of cells in which each cell has only two possible values (binary cells). The next state of
a cell depends on itself and its two neighbors (three-neighborhood dependency). The cells evolve in discrete time
1

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steps according to some deterministic rule depending only on local neighbors. Thus, he defined a network that
can be built based on a simple storage elements and combinatorial logic. Using polynomial and matrix algebraic
tools, he moved toward in characterizing the state-transition behavior and the global properties of CA. Based on
the statistical properties Wolfram classified the three-neighborhood CA broadly into four major categories (12).
Packard and Wolfram (13) also defined the framework of the two-dimensional CA and characterized its basic
properties. At the same time, others started to characterize CA models in various unrelated fields. Among other
CA-based models for physical systems [e.g., simple crystal growth (14)], probabilistic analysis of CA behavior
[e.g., the Game of Life algorithm (15)] and the architectural research of CA machines [e.g., CAMs (16)] should
be mentioned. With the advent of very large scale integrated (VLSI) technology, a number of specific-purpose
chips were built mainly for test-pattern generation and various cryptographic applications.
Parallel to this second phase of CA investigations another research field (17) also drew the attention
of the scientific community. After almost two decades of relative silence, Hopfields results (18, 19) on global
optimization problems and biological modeling renewed the activity in the neural network (NN) and artificial
intelligence (AI) research. In the next few years various models and architectures were proposed for a broad
class of classification, optimization, and approximation problems (e.g., Refs 202122). However, because all
these structures were densely or fully connected, their implementation posed a major challenge for VLSI
designers and the wiring problems could not be adequately solved.
In the late 1980s a new cellular array architecture and computing principle was proposed by Chua and
Yang (23), called cellular neural/nonlinear networks (CNN), standing at the crossroads of CA and NN research.
CNN inherited the analog (autonomous-nonautonomous) network dynamics from NN and the cellular (locally
connected) structure from CA, and soon it proved to be a powerful paradigm fertilizing research activity in
a number of disciplines. It turned out to be a well-constructed framework for biological modeling especially
modeling vision (24252627282930), simulating or emulating partial differential equations (PDEs) (313233
34), and in various engineering designs (353637383940414243444546474849505152535455).
CNNs are regular, single-layer or multilayer, parallel processing structures with analog nonlinear computing units (base cells). The state value of the individual processors is continuous in time and their connectivity
is local in space. The program of these networks is completely determined by the pattern of the local interactions, the so-called template. The time evolution of the analog transient, driven by the template operator
and the processor dynamics, represents the computation in CNN (results can be defined both in equilibrium or
nonequilibrium states of the network). The standard CNN equation (23) contains only first-order cells placed
on a regular grid and the interconnection pattern is linear. This was soon generalized to higher-order cells,
nonuniform grids, and nonlinear and/or delay-type templates (56, 57).
Completing the base cells of the CNN with local sensors, local data memories, arithmetical and logical
units, furthermore, with global program memories and control units results in the CNN Universal Machine
(CNN-UM) architecture [Roska and Chua (58)]. The CNN-UM is an analogic (analog and logic) supercomputer;
it is universal both in the Turing sense (59) and also as a nonlinear operator (25). Therefore, when designing
CNN processors, it can be used as a general architectural framework. Currently, there exist different physical
implementations of this architecture: mixed-signal VLSI (606162636465666768), emulated digital VLSI (69),
and optical implementation (70).
From hardware design point of view there is another important group of cellular arrays: smart sensors,
among them probably the most important the specific-purpose vision chips, which also appeared in the 1980s
after the pioneering work of Mead (71) and his research group. This line of investigation follows a more
bottom-up approach: cells are constructed in analog VLSI and are connected to perform a certain sensingcomputing task. Though the structures are CNN-like, there is no well-defined system level theory describing
the qualitative properties of these architectures. The emphasis is on sensing combined with a specific type of
computing for data prefiltering, reduction, and estimation of motion, of color-, and of form etc., rather than on
solving a complex task on a reprogrammable cellular architecture.

CELLULAR ARRAYS

This article gives a short overview of various cellular array architectures. First the mathematical description of different coupled cellular structures is presented by putting the emphasis on CA or CNN frameworks
and their relation to PDE-based descriptions. Then various architectures and their biological relevance are
discussed, followed by physical implementations and some state-of-the-art engineering designs. General application areas are also briefly described. Finally, the key concepts are summarized and future trends in cellular
array research and implementations are predicted.

Foundations and Mathematical Descriptions

In this section the mathematical description of CA- and CNN-type cellular arrays is given along with the basic
types of PDEs. It has been proven that all PDEs can be approximated to any desired accuracy by introducing
finite differences (72) (and possibly discrete variables), that is, they can always be mapped to a cellular
structure. Whereas all resulting models are locally connected, they may exhibit a very complicated global
dynamics. Cellular arrays are computationally universal (7, 15, 59) and from an engineering point of view, they
can be considered as dedicated architectures for building a universal parallel computer. The presentation of
this section aims to underline the engineering view that any PDE machine that can be built is likely to be a
cellular array.
PDE Machines as Cellular Arrays: an Engineering Approach. In a continuous space-time approach diffusive and wavelike transport mechanisms in physics can be well characterized by PDEs. A detailed
qualitative and quantitative analysis of these processes usually focuses on space-time evolution of these systems; however, a closed-form solution of the describing equations is available only in fairly simple cases. Then,
one may consider on constructing a universal computer programmed by PDEs and capable of calculating all the
solutions. The major obstacle in building the ideal PDE machinecontinuous in both space and timeis well
explained by quantum mechanics stating that the spectrum of the volume of any physical region is discrete
(73). For instance, even when choosing some gas or fluid as a basic material, there is always a certain microscopic scale at which these substances should be regarded as spatially discrete. On the other hand, treating
them on a macroscopic scale (thus continuous in space), another engineering problem arises: adjusting some
of the (global) physical parameters of this system would mean a very restricted way of programming. As a consequence, it is very likely that this computer would be self-describing, capable of calculating and predicting
only those processes that it actually represents. Are there any better mathematical abstractions for parallel
computing machines in engineering design?
Discretization along all spatial coordinates maps the PDE-based system into a dynamical system described
by ordinary differential equations (ODE). Stated with other words, the PDE is approximated on a fixed grid
looking at its properties at a chosen scale. This leads to a cellular array structure in which each node represents
an analog (continuous state and time) computing device. In this case, it is easier to imagine the corresponding
universal computer composed of cells having a prescribed sphere of influence in a local neighborhood, similar
to the sensory organs and the nervous system of different species in nature. Here, reprogramming would mean
changing the cell types and/or their local interaction (in order to change the local configuration) to realize a
universal computation.
Further simplification is possible by discretizing the ODE system in time and limiting the cell states to a
finite number of states. This fully discretized system, described by ordinary difference-differential equations
(ODDE), is theoretically still capable of reproducing the qualitative properties of the underlying PDE while
possessing structural simplicity that makes it tailor-made for physical implementation. For instance, imagine
a structure of molecules in a chemical substance in which the spin of the electrons is described by discrete
states and the chemical reaction evolves in phases. In this cellular array structure each node represents a
digital (discrete state and time) computing device. Similarly to the analog case, reprogramming would ensure
the construction of possible local configurations and the realization of a universal computation.

CELLULAR ARRAYS

The above-described analog and digital cellular arrays are not only good approximations of various PDEbased dynamical systems, but they can also be considered as universal computers (7, 15, 59). Furthermore,
it has been proven that there are cases in which for a certain cellular array structure (described by ODEs or
local rules) the limiting PDE representation with the same qualitative properties does not even exist (74). This
promotes a provocative view that PDEs are merely idealizations of (or only alternatives to) cellular structures
described by coupled ODEs or local update rules (75, 76).
Systems Described by Partial Differential Equations. In the following, some basic types of PDEs,
which describe continuous space-time systems, will be introduced. Without loss of generality the mathematical
descriptions will be specified in a two-dimensional (2-D) setting. Let us consider a planar signal flow (a spatiotemporal intensity function) I(x,y,t), where (x,y) represent the spatial coordinates and t the time dependence.
Then the nonlinear reaction-diffusion equation is represented by

where g and F stand for nonlinear functions, D and L are scalars. As a special case, assuming no changes in
time (and setting F = 0), one obtains the following Laplace equation

Using the same notation, a simple wave-type equation can be described as

Other types of useful PDEs, developed particularly for 2-D signal (image) processing, can be found in 777879
80.
Equations (1, 2, 3) and their variants are often used to describe diffusion and wave-type transport mechanisms in physics. There is an important common thread in these descriptions: there are no distant interactions
in space-time; from the continuity assumption it follows that only infinitely close particles interact. This
makes it impossible to build a device that exactly corresponds to the above-noted PDEs; however, it provides
the chance to approximate these equations by simple locally connected cellular systems.

Systems Described by Ordinary Differential Equations: Cellular Neural or Nonlinear Network.

Cellular neural or nonlinear networks (CNN) are two- or higher-dimensional arrays defined by simple dynamical systems arranged at the node points of a regular grid (Fig. 1). The state of these systems (cells) is
represented by a real number, the cells interact locally, and their operation is continuous in time. The cell dynamics is described by the following nonlinear ordinary differential equation with delayed-nonlinear intercell

CELLULAR ARRAYS

Fig. 1. A two-dimensional cellular array defined on a square grid. The ijth cell of the array is shaded black; cells that fall
within the sphere of influence of neighborhood radius r = 1 (the nearest neighbors) are gray.

coupling (the extension to higher dimensions is straightforward, allowing similar interlayer interactions):

where xij, uij, and yij are the state, input, and output voltages of the specified CNN cell, respectively. The
notation ij refers to a grid point associated with a cell on the 2-D M N grid, and klN r is a grid point in
the neighborhood within the radius r of the cell ij. A ij,kl represents the delayed nonlinear feedback, Bij,kl the
delayed nonlinear control, and A and B represent finite time delays, respectively. The constant zij is the cell
current, which could also be interpreted as a space-varying threshold. In general, the CNN template, which is
the program of the CNN array, consists of the [A B z] terms (omitting the indices). The output characteristic
f is a sigmoid-type (e.g., piecewise linear) function. Note that the output equation also describes a first-order
dynamical system. The time constant of a (first-order) CNN cell is determined by the linear capacitor (C) and
the linear resistor (R), and it can be expressed as = RC. Without loss of generality R = 1 and C = 1 will be
considered.
Simplifying the interaction types to nondelayed linear operators (A = 0 and B = 0), omitting the dynamics
in the output equation (Cy = 0), and ceasing the space-variant nature of the cell current (zij z) result in the
standard-CNN system [(23), the circuit theoretic model can be seen in Fig. 2]:

CELLULAR ARRAYS

Fig. 2. The circuit theoretic model of a standard CNN cell with voltage-controlled current sources.

Qualitative properties. Major efforts in CNN research have been concentrated on studying 2-D rectangular standard cellular systems described by Eq. (5). Depending on the template values, the associated CNN
might exhibit a very complicated dynamics: stable, oscillatory, and chaotic patterns can also be generated. In
2-D signal (image) processing applications, usually the globally or completely stable CNN behavior is exploited
by creating the analog kernels of a complex algorithm. A comprehensive overview on stable CNNs can be found
in Ref. 81.
PDE versus CNN. The cellular array described by Eq. (4) can be used to approximate Eqs. (1)(2) (3)
to any required precision by introducing finite differences in space. As an example, let us derive the CNN
equation corresponding to a variant of Eq. (1), the linear heat equation [setting F = 0, L = 0 and g(I) = I], by
using a four-neighbor discretization of the Laplacian:

Thus the linear heat (diffusion) equation can be directly mapped onto the CNN array resulting in the
following simple template (choosing D = 1):

Programmed by this template and operating in the central linear region of the output characteristic, the CNN
solves the associated heat equation. Indeed, this PDE machine based on Eq. (5) has already been built as
an analog VLSI circuitry (e.g., Ref. 67). In general, Eq. (4) can be viewed as the mathematical framework for
analog parallel processing cellular arrays, discrete in space but continuous in time.
Systems Described by Local Rules: Cellular Automata. A CA consists of a regular lattice of cells
(see Fig. 1). Each cell takes q possible values, and is updated in discrete time steps according to a local rule 
that depends on the value of the neighboring cells. The value xij of a cell at position i,j in a 2-D CA with a rule
that depends on the neighbors within the radius k,l N r evolves according to

CELLULAR ARRAYS

There are several possible lattices and neighborhood structures for 2-D CAs. For instance, a five-neighbor
square CA (a standard CA) evolves as follows:

In most cases, xij takes binary values and  is a Boolean logic function of the neighboring cell values.
Qualitative properties. A major line of investigations in CA research deals with 1-D and 2-D standard
cellular systems described by Eq. (9). A qualitative characterization orders these CAs into four classes (12):
(i) evolution leads to a homogeneous state, (ii) evolution leads to a set of separated simple stable or periodic
structures, (iii) evolution leads to a chaotic pattern, and (iv) evolution leads to complex localized structures
(capable of universal computation).
PDE versus CA. The cellular array described by Eq. (8) can be used to approximate Eqs. 1, 2, 3 to any
required precision by introducing finite differences in space-time and discretizing the state variable. Taking
again the linear heat equation [derived from Eq. (1)] as an example, one obtains ( t = h)

Observe that in Eq. (10) the local rule  represents the linear combination of the neighboring cell values.
The state value Iij is quantized and in order to approximate properly the original PDE it should take multiple
discrete values.
CNN versus CA. Equation (10) is a fairly general CA model; however, it can also be viewed as a simple
discrete-time CNN model with no input (82). This also clarifies some important differences when comparing the
CA and CNN frameworks. The CA represents autonomous discrete-valued lattice dynamical systems, while the
CNN can be regarded as a general description of analog-valued nonautonomous cellular dynamical systems.
The standard framework of both the CA and CNN research is the mathematical description that closely
describes the core of the first hardware implementations. Note that a simple algorithm running on a CNN
hardware (67) can exactly emulate a binary CA with Boolean logic update rules (13).
Remarks. Any numerical integration formula solving (approximating) a PDE (and an associated CNN)
in the binary universe can be regarded as a general CA model although with multiple discrete states and
complicated local update rules. In general, Eq. (8) can be viewed as the mathematical framework for autonomous
digital parallel processing cellular arrays, discrete in space-time. A general nonautonomous nonlinear model
could be described by the discrete time version of Eq. (4), the discrete-time CNN equation [(82), DTCNN].

Architectures and Biological Relevance

Different CA and CNN architectures. Based on the preceding generic definition of the CNN [Eq. (4)]
and CA [Eq. (8)], several types of cellular arrays can be generated. They can be classified according to the
types of the grid, the processor (cell), the interaction (template or update rule), and the mode of operation.
Thus, building the core of a massively parallel computer based on cellular array architecture, the following key
points should be addressed in detail:
(1) Grid types Cellular arrays are usually defined on a spatially discrete square (rectangular) grid, however,
hexagonal and triangular arrangements can also be considered (Fig. 3(ac)). These grids are the only

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Fig. 3. The most common and two special grid types of cellular architectures. Regular contiguous tessellations of the
plane based on congruent polygons are shown in the top row: (a) rectangular, (b), triangular, and (c) hexagonal lattices. In
the bottom row two special grid types are given that belong to the ornamental group. All grid types (b)(e) could be mapped
to a rectangular grid (a) with periodic space-variant interconnections.

regular contiguous tessellations of the plane based on congruent polygons alone. Other grid types can
also be created based on nonregular congruent polygons or from a regular vertex grid through discrete
geometrical transformations: rotations and translations [ornamental groups, Fig. 3(de)]. A great number
of these grids can be mapped on a typical eight-neighbor rectangular structure with periodic space-variant
connections (83). Multiple and varying grid sizes (e.g., coarse and fine grids, and logarithmically changing
size) may be useful in simulating adaptive biological systems (e.g., retina, lateral geniculate nucleus (LGN),
or magno-parvo pathways in the cortex).
(2) Cell (processor) types and boundary cell types Cellular arrays can be built from linear or nonlinear, first- or
higher-order cells. A linear or small-signal operation (as a special case) is achievable through piecewise
linear output characteristics. A highly nonlinear dynamic behavior (typical CNN models) is attainable
through a sigmoid, Gaussian, or inverse-Gaussian type output characteristics. Cells can include additional
local analog and/or logical memories for storing intermediate processing results. A cell might perform
local logic operations (typical CA models) or a combined analogic (analog and logic) computation (extended
CNN models). The cells of an array can be uniform or nonuniform (regularly or slightly varying). In some
processing tasks two or three cell types in a regular grid might be very useful, for example, in color image
processing. Since in any physical implementation only a finite array can be built, a boundary condition
should be exactly defined. Creating boundary cells that are not involved in the cooperative computation
(virtual cells) can satisfy this requirement. The most important boundary cell specifications are as follows:
(i) In the fixed (Dirichlet) type, constant values are assigned to all boundary cells. (ii) In the zero-flux
(Neumann) type, boundary cells are made to follow cells that are on the same side of the array. (iii) In the

CELLULAR ARRAYS

periodic (toroidal) type, boundary cells are made to track the values of cells from the opposite side of the
array.
(3) Neighborhood size and interaction types The interaction type (the biological synapse) between the grid
cells represents the program of a cellular array. Depending on whether these interaction types are fixed
or programmable, the array can be regarded as a specific-purpose (see previous section on CA and smartsensor implementations) or a reconfigurable (see previous section on the CNN-UM and its implementations)
parallel array architecture. The nearest neighborhood is the most common sphere of influence in the intercell
communication for both CA and CNN models (either the cross-shaped fourfold-connected or the star-shaped
eightfold-connected neighborhoods); however, larger neighborhood sizes can also be considered (typically
in biological modeling or when creating adaptive artificial systems). The interaction types can be linear or
nonlinear memoryless functions [e.g., a typical CA update rule corresponding to Eq. (8)] of one, two, or more
variables. Delayed nonlinear [e.g., a typical CNN template corresponding to Eq. (4)] and dynamic (lumped)
interactions are more general connection types. By breaking the symmetry or isotropy and moreover varying
the nature of the interconnections in space and/or in time, an extremely rich collection of further templates
(or local update rules) can be created.
(4) Modes of the operation The mode of operation can be continuous (general CNN models) or discrete time
(general DTCNN and CA models). In the case of a discrete-time procedure the update mechanism can be
synchronous or asynchronous. The computation can be analog, logic, or analogic (see also item 2) and can be
executed either in local mode or in propagating mode (on a decoupled or coupled array, respectively). Besides
the usual fixed-point operational mode (equilibrium computing), transient (nonequilibrium computing),
oscillating, chaotic, and general stochastic modes can also be used.

The CNN Universal Machine: An Analogic Stored Program Cellular Array Computer. A cellular architecture that includes the main properties listed and discussed in the previous subsection is the
CNN Universal Machine [CNN-UM (58)] The CNN-UM makes it possible to combine efficiently analog array
operations with local logic. Because the reprogramming time is approximately equal to the settling time of a
nonpropagating analog operation, it is capable of executing complex analogic (analog and logic) algorithms. To
ensure programmability, a global programming unit was added to the array and for an efficient reuse of intermediate results, each computing cell was extended by local memories. In addition to local storage, every cell
might be equipped with local sensors and additional circuitry to perform cellwise analog and logical operations.
The architecture of the CNN-UM is shown in Fig. 4.
The CNN-UM is built around the dynamic computing core of a simple CNN. An image can be acquired
through the sensory input [e.g., optical sensor (OPT)]. Local memories store analog [local analog memory
(LAM)] and logic [local logical memory (LLM)] values in each cell. A local analog output unit (LAOU) and
a local logic unit (LLU) perform cellwise analog and logic operations on the stored values. The output is
always transferred to one of the local memories. The local communication and control unit (LCCU) ensures
the communication between the extended cell and the central programming unit of the machine, the global
analogic programming unit (GAPU). The GAPU has four functional blocks. The analog program register (APR)
stores the analog program instructions, the CNN templates. In the case of linear templates, for connectivity r
= 1, a set of 19 real numbers has to be stored (this number is even less for both linear and nonlinear templates
assuming spatial symmetry and isotropy). All other units within the GAPU are logic registers containing the
control codes for operating the cell array. The local program register (LPR) contains control sequences for the
individual cells LLU, and the switch configuration register (SCR) stores the codes to initiate the different switch
configurations when accessing different functional units (e.g., whether to run a linear or nonlinear template).
The global analogic control unit (GACU) stores the instruction sequence of the main (analogic) program. The
GACU also controls the timing, sequence of instructions and data transfers on the chip and synchronizes the
communication with any external controlling device.

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Fig. 4. The architecture of the CNN Universal Machine, the stored program analogic array supercomputer.

Synthesizing an analogic algorithm running on the CNN-UM, the designer should decompose the solution
to a sequence of analog and logical operations. A limited number of intermediate results can be locally stored
and combined. Some of these outputs can be used as a bias map (space-variant bias) or fixed-state map
(space-variant mask) in the next operation by adding spatial adaptivity to the algorithms without introducing
complicated intercell couplings. Either a linear or a nonlinear template defines analog operations. The output
can be defined both in fixed and nonfixed states of the network (equilibrium and nonequilibrium computing),
depending on the control of the transient length. It can be assumed that elementary logical (NOT, AND, OR, etc.)
and arithmetical (ADD, SUB) operations are implemented and can be used at the cell level between LLM and
LAM locations, respectively. In addition, data transfer and conversion can be performed between LAMs and
LLMs.
Biological Relevance. Earlier it was explained why cellular arrays can be viewed as efficient PDE machines in simulating physics. Here, some key observations made in biologybased on morphological, pharmacological, and physiological measurementswill be recalled that underline the biological relevance of cellular
architectures and also the analogic operational mode of array computing.
At the neuronal level, it is instructive that many complex neural functions are performed without spikes,
and in many visual functions (e.g., within the retina of the vertebrates) 2-D layers of locally connected neurons
perform some tasks that combine both spikeless (analog) and spike-type (logic) processing as well (84). Cellular
arrays are also natural models for topographic maps of biological sensory systems (84). At the neural systems
level, recent physiological discoveries have shown that complex visual tasks are solved by using several different
projections of the same image stored retinotopically in different parts of the brain (cortex) as a multiscreen
theater (85). Finally, at the cognitive systems level, the evidence of functional cerebral hemispheric asymmetry
of the brain (86) provides a strong motivation for formulating the cellular computing model as a nonlinear
analogic (dual) computing structure (87) and justifies a novel approach to computational complexity (88).

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11

Physical Implementation
In this section a brief overview on the main physical implementation trends of cellular arrays will be given. The
emphasis will be put on those reconfigurable cellular architectures that interact with the physical world, that
is, where on-chip sensing and flexible computing are integrated. For these engineering prototypes CA models
cannot be considered as a general framework. The unifying paradigm is rather a CNN-type general model with
locally connected analog computing sensors arranged on a regular rectangular grid. Specific purpose vision
chips (smart sensors) make up a very important class of these architectures, in which sensing is combined
with a specific functionality. These chips are special-purpose nonprogrammable (only tunable) information
sensing devices. Programmable single-chip visual microprocessors can be considered as a more general class
developed within the CNN framework. The general architecture of these reconfigurable devices (CNN-UM)
has been described in the previous section and lead to efficient optoelectronic prototypes. Throughout the
section the phrase visual sensing should be understood in a very broad sense: it rather describes a general 2-D
sampling of any physical property of the environment (e.g., color, temperature, pressure, smell) than only the
2-D representation of the light intensity within the visible spectrum.
CA implementations. The CA theory evolved in parallel with the advance of digital technology that
implemented noncellular architectures and used sequential computing principles for decades. Though the
theory of autonomous cellular automata machines (CAMs) was well developed in the 1980s, single-chip largescale 2-D prototypes had not been fabricated. The CA framework was used in parallel supercomputer [e.g.,
the Connection Machine (89)] and massively parallel processor design [MPP (90)], furthermore in specific
cryptographic and test hardware synthesis. However, this framework was not widely used in engineering
designs integrating array sensing and computing.
Specic-Purpose vision Chips: Smart Sensors. Carver Mead, who first introduced the idea of
neuromorphic engineering using VLSI technologies in the 1980s, pioneered the research field of smart sensors
(71, 91, 92). The main idea was to integrate the photodetecting elements with the processing circuits on the
same chip and perform sensor information processing without redundant and unnecessary data acquisition
(smart sensing). The smart-sensor concept implies a low-level interaction between the sensors and processors; therefore, modular camera-processor combinations do not belong to this class. During the last decade the
sensors that have been embedded into these devices were almost exclusively photodetecting elements; however, recently other types have also been designed in cellular array architectures (e.g., high-resolution tactile
sensors).
Specific-purpose vision chips are optimized for certain functionality, for the quality of processing, instead
of the acquired image quality aimed by high-resolution and precision cameras. The advantage of vision chips
lies in their very high processing speed, large (usually adaptively controlled) dynamic range, small size, and low
power dissipation compared to camera-processor combinations. At the current stage, it is a drawback that most
of these devices are fully custom designed (time consuming, costly, and error prone) and that the implemented
algorithms should account for the hardly controllable inaccuracies of analog VLSI systems. Furthermore, none
of the vision chips are of general purpose, i.e., they could be parameter tunable within certain limits but
are not programmable to perform different vision tasks. This property is particularly undesirable during the
development and test phase of a vision system.
The main technologies used in vision chip fabrication are complementary metal-oxide semiconductor
(CMOS), charge-coupled device (CCD), bimetal CMOS (BiCMOS), and GaAs (MES-FET and HEMT), though
CMOS was exclusively used in the majority of the designs. Vision chips can be classified (93) into spatial (e.g.
94,95), spatiotemporal (e.g., 969798), and optical neurochip (e.g., Ref 99) groups.
Programmable Visual Microprocessors (CNNM-UM chips). Specific-purpose vision chips are nonprogrammable cellular architectures. Since they implement only a specific functionality they require a top level
system for complex information processing. Similarly, all fully connected neural network chip realizations have
a common feature: they implement a single instruction only; thus the weight matrix is fixed when processing

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some input. Reprogramming (i.e., changing the weight matrix) is possible for some devices but takes longer
time (by orders of magnitudes) than the computation itself.
These observations motivated the design of the CNN-UM (58), a stored program nonlinear array computer.
The CNN-UM can also be viewed as a visual microprocessor especially when it is built with a focal plane
sensory array. Different analog VLSI implementations of CNN-UM chips and a comparison of their performance
characteristics can be found in Table 1. The first fully working implementation that can run analogic algorithms
is the 1995 mixed-signal version (it has an optical input) from Seville (62). This chip, embedded into the CNN
prototyping system (100), was used in various experiments validating CNN templates and algorithms. The
most promising is certainly the latest version of these implementations fabricated in 1998 (67) (see the last
column). It has a 64 64 CNN array with optical input, and in addition to the features shown in Table 1 it
allows the use of fixed-state map techniques, global logical lines, and ARAMs (analog random access memory)
(66) during the algorithm synthesis. This prototype already paves the road toward industrial applications.
There is always a gap between the system level design and chip implementations. Trying to synthesize
powerful algorithms that can keep up with the state-of-the art methods of signal-processing disciplines, the
engineer at the system level always faces the problem of hardware limitations and has to simplify the methodologies used. On the other hand, a VLSI designer would like to know the priority of the requirements motivated
by different applications. At the current stage, the need for higher-order (complex) cells, nonlinear interactions,
larger neighborhood size, and space-variant programming contradicts the requirement of higher resolution.
Designing the future generation of CNN-UM chips the cell area versus functionality trade-off will always be
one of the main issues with which to cope.

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13

Fig. 5. Spatial edge (middle row) and spatiotemporal motion (bottom row) detection output from a retinotopic computation executed on a CNN-UM chip (input is shown in the top row). Simply reprogramming the array can test different
biological retina models.

Applications
In this section some applications based on cellular array architectures will be highlighted. Since these areas are very diverse the objective of this summary is only to show how various disciplines can profit from
having a programmable (reconfigurable) visual microprocessor equipped with both analog and logical computing capabilities. It is stressed that the algorithmic flexibility connecting biology, physics, and chemistry
on these cellular architectures also fertilizes the engineering designs targeting industrial and other real-life
applications. Experimental results based on existing prototypes (63, 67) will also be demonstrated.
Biological Modeling: Revealing Adaptation and Plasticity. Cellular architectures have been extensively used in various biological modeling experiments (e.g., 242526272829) but probably retina modeling
is the only interdisciplinary research field that has significantly influenced the engineering designs. For instance, most specific-purpose vision chips aim to reproduce some well-defined functionality (e.g., spatial edge
detection or spatiotemporal motion detection) of this front end of biological visual systems.
The retina is said to be the approachable part of the brain (101) and indeed, currently a large number
of morphological observations, pharmacological, and physiological measurements are at hand helping us to
understand the cells, synapses, and circuitry of this tiny neural processing layer. It is certainly due to its
enormous complexity and emerging computational capability that even nowadays the neural code sent to the
cortex is not fully understood. Vision chip design exploits the information learned about the structure and
some functionality of the retina, but usually there are radical differences comparing biological and silicon
retinas at the cell and synaptic levels. Also, the observed measured functional richness, the adaptation and
plasticity properties in the retina assume, in engineering terms, a very flexible re-programmability that is not
incorporated into these smart sensor architectures.
Theoretical research and implementation in the CNN field have evolved into a closer interaction with
retinal modeling experiments (25). Due to this fact the latest CNNU-UM chip (67) is capable of computing both
the spatial edge and spatiotemporal motion features of an image sequence (Fig. 5). Other functionality can
also be easily tested, i.e., simply by reprogramming this architecture, one can generate hypotheses on various
retinal models.
Retina modeling also motivated a new direction in CNN chip designs trading resolution for so-called
complex cells (higher-order cells with more complicated synapses) that can also be interpreted as having
multilayer CNN structures with simple cells (102). Just taking a glance at a simplified outer-retina model

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Fig. 6. A three-layer base model of the outer plexiform layer (OPL) in the retina. Each biological cell layer is mapped onto
a CNN layer that consists of first- or second-order (two mutually coupled first-order) cells. Some pathways and connections
are also indicated that still represent a controversial issue in neurobiology.

[(28), Fig. 6] that requires at least a three-layer cellular architecture, it is easy to understand why the physical
implementation of cellular arrays has made only the first steps toward a real neuromorphic and programmable
visual microprocessor.
Programmable Physics: Diffusion and Wave Models. The PDE-related diffusion-type CNN template derived earlier could be used to emulate a diffusion mechanism on a CNN-UM chip (67). Starting from
an arbitrary initial condition (a gray-scale image) the linear heat diffusion results in a progressively low-passfiltered version of the original image [Fig. 7(a)]. Changing the value of the central term in the feedback matrix
(a0 = 3) and the bias value (z = 2.75) a nonlinear trigger-wave propagation can also be generated from an
arbitrary initial patch [Fig. 7(b)]. As it can be seen the direction of the propagation is reversible (it depends on
the sign of the bias value). These two simple cases, based on first-order cells, demonstrate how physics can be
easily programmed on a cellular architecture. More complicated wave phenomena can also be generated based
on second-order cells as shown in Fig. 7(c)(f) (see further examples in 38 and 45).
Programmable Chemistry: Self-Assembly in Chemical Substances. There are several classes
of CNN templates (404142) capable of simulating self-assembly in chemical substances. In the following
experiments it will be shown how checkers, patches, stripes, and various combination of these spatial patterns
can be formed from random initial conditions on a CNN-UM chip (67) programmed by these templates (Fig. 8).

Cellular Computing in Engineering Designs. In this subsection the image-flow processing capabilities of cellular architectures will be discussed. It is demonstrated how a cellular computer vision system builds
on the instructions derived during biological, physical and chemical modeling experiments. This is a radically
different approach to synthesizing a computer vision algorithm compared to traditional methods since it is
based on programmable receptive fields, transport mechanisms (diffusion and waves), and self-organization
phenomena.
A cellular computing system is capable of multidimensional information processing. The data can be
acquired either in the focal plane (through the on-chip sensors integrated with the cells of the system) or
transferred from other array sensor devices (e.g., a CCD camera). In this subsection two such engineering
designs based on cellular architectures and analogic cellular computing will also be shortly presented. In these
prototypes the flexibility of a recently designed CNN-UM chip (67) and hardware-software environment (100)
is exploited building a focal-plane and an online video-flow processing application.
Cellular Computer Vision. The architectures and physical implementation of cellular systems were
discussed in previous sections. Here, some key operators and the algorithmic aspects of cellular computing will

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15

Fig. 7. Programmable physics on a cellular architecture based on first-order and second-order cells: (a) snapshots of a
controlled diffusion process, (b) snapshots of a reversed trigger-wave propagation, (c) initial patches for wave generation,
(d) traveling waves, (e) autowaves, (f) spiral waves.

be addressed. Figures 9, 10, 11 illustrate how biological, physical, and chemical models can be interpreted as
meaningful operators in image processing.
In Fig. 9 programmable receptive fields (edge and corner detection), wave-type computation (reconstruction and connected component detection) and spatial logic (XOR) is used to build up the analogic algorithm
solving an object classification problem. In this simple example [Fig. 9(a)] isolated objects that have no corners
should be identified marking the horizontal and vertical object extension (coordinates) along the image edges
[Fig. 9(gh)]. The task is solved combining analog operations (either with local or global dynamics) with spatial
logic relying on a programmable cellular architecture with local memories.
Various filters can be constructed based on diffusion-type computation as illustrated in Fig. 10. Observe
in Fig. 10(b) the low-pass filtered and in Fig. 10(c) the band-pass filtered output of the test image given in Fig.
10(a). Self-organizing phenomena can also be exploited in image processing. By creating a halftone version
of a gray-scale image, an adaptive pattern-creating feature helps us to obtain a visually pleasing binary
representation of the original image as shown in Fig. 10(d).
The global dynamics of locally connected cellular arrays is a key property in building powerful image flow
processing algorithms. Operators derived from transport mechanisms allow us to combine controlled diffusion

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Fig. 8. Programmable chemistry on a cellular architecture pattern-creating self-organization phenomena: (b) checkers,
(c) patches, and (d) stripes formed from a random initial condition (a). A colorful combination of the basic motifs can also
be generated (e)(g).

Fig. 9. Programmable receptive fields, wave-type computation, and spatial logic in analogic cellular image processing.
The example demonstrates the intermediate steps of an analogic algorithm: (a) original image; (b) result of edge detection;
(c) result of corner detection; (d) objects reconstructed from corners; (e) isolated object without corners obtained through
spatial logic; (f) edge of the detected object; (g) vertical extension of the detected object; (h) horizontal extension of the
detected object.

and waves within the analogic algorithmic framework and make it possible to solve sophisticated detectionreconstruction problems. Such an example is shown in Fig. 11, tracking the contour of the left ventricle where
diffusion-type filters were used in noise suppression and trigger waves in boundary detection.
Focal-plane Object Classication. Ultrahigh frame-rate (exceeding 10,000 frame/s) image processing is
an unsolved problem with current digital systems of affordable price and size. Both the limited computational

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17

Fig. 10. Diffusion-type computation and self-organization in analogic cellular image processing. (a) Original image; (b) the
output of a blurring low-pass filter realized through controlled diffusion mechanism; (c) the output of an edge enhancing
band-pass filter realized through diffusion mechanism and spatial arithmetics; (d) halftone (binary representation of a
gray-scale image) output obtained through adaptive pattern creating self-organization.

Fig. 11. Using transport (diffusion and wave) mechanisms in analogic cellular image processing. Top row: snapshots of the
human heart on an echocardiography sequence. The image-flow shows the spatiotemporal deformation of the left ventricle
(the largest heart chamber). Bottom row: detected contour of the left ventricle calculated by an analogic cellular algorithm. Diffusion-type filters were used in noise suppression and trigger-waves in boundary detection. The spatiotemporal
consistency was ensured through inter-frame spatial logic operations.

power and the I/O bottleneck (when the image is transferred from the sensor to the processor) represent major
obstacles in digital systems.
Cellular neural or nonlinear network (CNN) technology offers a parallel and analogic (combined analog
and logic) approach to these problems. If a CNN chip is used as a focal-plane array, even a zero computational
load requirement is achievable (the processing is limited by the image acquisition only). The chip (63) acts
as a focal-plane visual microprocessor: it acquires image frames parallel through the optical input, transfers
them to the processor elements, and performs the analysis also in parallel. In 20 s, approximately five analog
operations (CNN templates) and ten local logic operations can be completed. This makes it possible that even a
complex morphological decision can be performed on-chip within two subsequent frames at a 50,000 frames/s
operational speed.
The experimental setup of the focal-plane classification system is shown in Fig. 12(a). The CNN platform
that carries the chip is mounted on the back panel of a camera (only the optics is used, no shutter is required).
On a rotating disk different images are posted and during the experiment these images are projected onto the
chip through the lens system of the camera [see the images acquired by the on-chip sensor in Fig. 12(b)].
In the experiment objects are classified based on their local morphological features by a complex analogical
algorithm. In Fig. 13 the major subroutines of the algorithm are shown along with their measured on-chip time
performance (no transfer and display time included). This demonstration proves that the current CNN system

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Fig. 12. The ultra high-speed focal-plane array processor system: (a) the experimental setup, (b) the objects silhouettes
captured by the 20 22 CNN-UM chip.

Fig. 13. The flow chart of the object classification algorithm and the measured time performance on the 20 22 CNN-UM
chip. A binary-morphology-based analogic cellular algorithm ensures rotation and translation invariant detection.

is able to classify six different flying objects (hot-air balloons and airplanes) based on their silhouettes lowresolution projections on the chips optical sensors at a speed of approximately 10,000 frames/s.
Online Video-ow Processing. In the last few years particle detection and classification in fluid flows
have received considerable interest among the applications requiring image processing at ultrahigh frame rates.
For instance, a sensory module capable of identifying the density of debris particles in the oil flow of various
engines would enable a cost-effective online monitoring of these systems (e.g., condition-based monitoring of
jet engines).
In these applications the CNN chip can be used either as a focal-plane array processor or a video-flow
processing visual microprocessor. In the latter case recent feasibility studies and experiments indicate that in
a demonstration, the prototype system detection and classification of the particles can be performed online on
a 64 64 CNN chip (67).

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19

Fig. 14. The online video-flow processing system: (a) the experimental setup, (b) a typical image frame acquired by the
CCD camera, (c) identified marble superimposed onto the original image, (d) identified bubbles superimposed onto the
original image.

Fig. 15. The flow chart of the bubble-marble classification algorithm with the time requirement of the algorithm subroutines on a 64 64 CNN-UM chip. The analogic algorithm is based on binary morphology and diffusion-type operators.

Figure 14(a) shows the experimental setup of the online video-flow demonstration. In a water tank
containing bubbles and marbles, a fast turbulent flow is generated. The task is to detect and separate the
marbles from air bubbles in each acquired image. A typical image acquired by the CCD camera can be seen in
Fig. 14(b), a detected marble in Fig. 14(c), and the identified bubbles in Fig. 14(d).
The algorithm consists of the following processing stages: (i) adaptive thresholding, in which all objects
are detected in the image field through a spatially adaptive thresholding, (ii) morphological prefiltering, in
which objects are compared to prototype objects to filter out single bubbles and bubble groups, also to classify
the remaining objects into different particle groups, (iii) object classification, such that in the last stage objects
are classified based on their size and morphology (and a simple statistics is calculated for different object
groups).
The on-chip time performance of the subroutines of the algorithm is summarized in Fig. 15 (no transfer
and display time included). The demonstration proves that with the current CNN system a morphology-based
complex algorithm can be executed during an online video-flow processing.

Summary
Various cellular array architectures that have been proposed for massively parallel computing were discussed.
It has been argued that though the physical laws are often described by PDEs, the abstract engineering
computing machine is rather a cellular structure that is discrete in space, continuous or discrete in time, and
is based on analog/discrete computing devices (processors).

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It has been shown that though historically rooted from cellular automata (and fully connected neural
networks) current implementation trends and biological modeling results justify the intensive research efforts on the field of cellular nonlinear/neural networks. This is especially true when both array sensing and
computing are to be addressed within a unified framework. It has been stressed that in order to have a reconfigurable cellular computing array, stored programmability is a key issue in architecture design targeting
various application areas in engineering, biology, chemistry and physics.

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CSABA REKECZKY
ROSKA
TAMAS
Computer and Automation Institute of
the Hungarian Academy of Sciences
any

and Peter Pazm

Catholic
University

CHEBYSHEV FILTERS

267

processing, where the signal is processed by a linear system

that changes the amplitudes and phases of these components,
but not their frequencies. In a simple form, this processing
can be used to let pass or to reject selected frequency bands,
ideally with no attenuation at the passbands and infinite attenuation at the stopbands. This article discusses a class of
approximations to this kind of ideal filter, known as an Chebyshev filter. It starts with a discussion on a technique for
the derivation of optimal magnitude filters, then discusses the
direct and inverse Chebyshev approximations for the ideal
filtering operator, ending with comments on extensions of the
technique. Tables with example filters are included.
The magnitude approximation problem in filter design consists essentially of finding a convenient transfer function with
the magnitude satisfying given attenuation specifications.
Other restrictions can exist, such as structure for implementation, maximum order, and maximum Q of the poles, but
in most cases the problem can be reduced to the design of a
normalized continuous-time low-pass filter, which can be described by a transfer function in Laplace transform. This filter
must present a given maximum passband attenuation (Amax),
between 0 and p 1 rad/s, and a given minimum
stopband attenuation (Amin) in frequencies above a given limit
r rad/s. From this prototype filter, the final filter can be obtained by frequency transformations and by continuous-time
to discrete-time transformations in the case of a digital filter (1).
A convenient procedure for the derivation of optimal magnitude filters is to start with the transducer function H(s) and
the characteristic function K(s). H(s), which can also be called
the attenuation function, is the inverse of the filter transfer
function, scaled such that min H( j) 1. K(s)is related to
H(s) by the equation
|H( j)|2 = 1 + |K( j)|2

(1)

This greatly simplifies the problem, because K( j) can be a

ratio of two real polynomials in , both with roots located
symmetrically on both sides of the real axis, while H( j) is a
complex function. K(s) is obtained by replacing by s/j in
K( j) and ignoring possible j or 1 multiplying terms resulting from the operation. The complex frequencies where
K(s) 0 are the attenuation zeros, and where K(s) correspond to the transmission zeros. If K(s) is a ratio of real polynomials, K(s) F(s)/P(s), H(s) is also a ratio of real polynomials in s, with the same denominator, H(s) E(s)/P(s), and
E(s) can be obtained by observing that for s j Eq. (1) is
equivalent to
H(s)H(s) = 1 + K(s)K(s) ) E(s)E(s)
= P(s)P(s) + F (s)F(s)

(2)

Because E(s) is the denominator of the filter transfer function,

which must be stable, E(s) is constructed from the roots of the
polynomial P(s)P(s) F(s)F(s) with negative real parts.
The desired transfer function is then T(s) P(s)/E(s).

CHEBYSHEV FILTERS

CHEBYSHEV POLYNOMIALS

Any signal can be considered to be composed of several sinusoidal components with different frequencies, amplitudes, and
phases. Filtering is one of the fundamental methods for signal

Two important classes of approximations, the direct and inverse Chebyshev approximations, can be derived from a class
of polynomials known as Chebyshev polynomials. These poly-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

268

CHEBYSHEV FILTERS

Or, the attenuation in decibels is

Table 1. Chebyshev Polynomials

A() = 10 log{1 + [Cn ()]2 }

Polynomial

0
1
2
3
4
5
6
7
8
9
10
11
12

1
x
2x 1
4x 3 3x
8x 4 8x 2 1
16x 5 20x 3 5x
32x 6 48x 4 18x2 1
64x 7 112x 5 56x 3 7x
128x 8 256x 6 160x 4 32x 2 1
256x 9 576x 7 432x 5 120x 3 9x
512x 10 1280x 8 1120x 6 400x 4 50x 2 1
1024x 11 2816x 9 2816x 7 1232x 5 220x 3 11x
2048x 12 6144x 10 6912x 8 3584x 6 840x 4 72x 2 1

nomials were first described by P. L. Chebyshev (2). The

Chebyshev polynomial of order n can be obtained from the
expression
Cn (x) = cos(n cos1 x)

(3)

It is simple to verify that this expression corresponds, for

1 x 1, to a polynomial in x. Using the trigonometric
identity cos(a b) cos a cos b sin a sin b, we obtain

Cn+1 (x) = cos[(n + 1) cos1 x]

= xCn (x) sin(n cos1 x) sin(cos1 x)

(4)

Applying now the identity sin a sin b 
[cos(a b)

cos(a b)] and rearranging, a recursion formula is obtained:
Cn+1 (x) = 2xCn (x) Cn1 (x)

(5)

For n 0 and n 1, we have C0(x) 1 and C1(x) x. Using

Eq. (5), the series of Chebyshev polynomials shown in Table
1 is obtained.
The values of these polynomials oscillate between 1 and
1 for x between 1 and 1, in a pattern identical to a stationary Lissajous figure (3). For x out of this range, cos1 x
j cosh1 x, an imaginary value, but Eq. (3) is still real, in the
form
Cn (x) = cos(n j cosh

x) = cosh(n cosh

x)

(9)

The parameter controls the maximum passband attenuation, or the passband ripple. Considering that when Cn()
1 the attenuation A() Amax Eq. (9) gives
=

p10

0.1A max

(10)

Figure 2 shows examples of the magnitude function T( j) in

the passband and in the stopband obtained for some normalized Chebyshev low-pass approximations, with Amax 1 dB.
The magnitude of the Chebyshev approximations presents
uniform ripples in the passband, with the gain departing from
0 dB at 0 for odd orders and from Amax dB for even
orders.
The stopband attenuation is the maximum possible among
filters derived from polynomial characteristic functions and
with the same Amax and degree (4). This can be proved by assuming that there exists a polynomial Pn(x) that is also
bounded between 1 and 1 for 1 x 1, with Pn(x)
Pn(x) and Pn() , which exceeds the value of Cn(x)
for some value of x 1. An approximation using this polynomial instead of Cn(x) in Eq. (7) would be more selective. The
curves of Pn(x) and Cn(x) will always cross x times for 1
x 1, due to the maximum oscillations of Cn(x), but if Pn(x)
grows faster, they will cross another two times for x 1 and
x 1. This makes Pn(x) Cn(x) a polynomial of degree n
2, because it has n 2 roots, which is impossible since both
are of degree n.
The required approximation degree for given Amax and Amin
can be obtained by substituting Eq. (6) in Eq. (9), with
A(r) Amin and solving for n. The result, including a denormalization for any p, is

cosh
cosh

(11)

(r / p )

where we define the constant as

100.1A min 1
100.1A max 1

(12)

(6)

For high values of x, looking at the polynomials in Table 1,

we see that Cn(x) 2n1xn and grows monotonically. The plots
of some Chebyshev polynomials for 1 x 1 are shown in
Fig. 1.

C1

C2

C3

C4

C5

C6

THE CHEBYSHEV LOW-PASS APPROXIMATION

This normalized Chebyshev low-pass approximation is obtained by using
K( j) = Cn ()

(7)

The result is a transducer function with the magnitude given

by [from Eq. (1)]
|H( j)| =

1 + [Cn

()]2

(8)

Figure 1. Plots of the first six Chebyshev polynomials Cn(x). The

squares limit the region 1 x 1, 1 Cn(x) 1, where the polynomial value oscillates.

CHEBYSHEV FILTERS

The transfer functions for the normalized Chebyshev filters

can be obtained by solving Eq. (2). For a polynomial approximation, using P(s) 1, from Eq. (7) it follows that

E(s)E(s) = 1 + Cn

s  2

j
cosh ( 1 sinh
n
sinh ( 1 sinh
n

(13)

The roots of this polynomial are the solutions for s in

Cn

s
j

= cos n cos1

s
j

j
=


1)

1)

(14)

s
= a + jb
j

2n

Identifying
n cos1

269

(15)

it follows that j/ cos(a jb) cos a cos jb sin a

sin jb cos a cosh b j sin a sinh b. Equating real and
imaginary parts, we have cos a cosh b 0 and sin a sinh b
1/ . Since cosh x 1, the equation of the real parts gives:
a=

(1 + 2k), k = 0, 1, . . ., 2n 1
2

(16)
Figure 3. Localization of the poles in a normalized Chebyshev lowpass approximation (seventh order, in this case). The pole locations
can be obtained as shown.

|T( j)|dB
0

1
3

and as for these values of a, sin a 1, the equation of the

imaginary parts gives

5
6

b = sinh

4
1

1


(17)

By applying these results in Eq. (15), it follows that the roots

of E(s)E(s) are

(a)
|T( j)|dB
1
0

10

sk = k + jk
k = sin
k = cos

k = 0, 1, . . ., 2n 1

1 + 2k 
2

1 + 2k 

sinh
cosh

1

1
n

sinh

sinh

1


1


(18)

The roots sk with negative real parts (k n) are the roots of

E(s). By the expressions in Eq. (18), it is easy to see that the
roots sk are located on an ellipse with vertical semi-axis cosh
(1/n sinh1 1/ ), horizontal semi-axis sinh (1/n sinh1 1/ ), and
foci at j. The location of the roots can be best visualized with
the diagram shown in Fig. 3 (3).

REALIZATION OF CHEBYSHEV FILTERS

10
100
(b)
Figure 2. Passband gain (a) and stopband gain (b) for the first normalized Chebyshev approximations with 1 dB passband ripple. Observe the uniform passband ripple and the monotonic stopband gain
decrease.

These approximations were originally developed for realization in passive form, and the best realizations were obtained
as LC doubly terminated structures designed for maximum
power transfer at the passband gain maxima. These structures are still important today as prototypes for active and
digital realizations, due to the low sensitivity to errors in element values. At each attenuation zero, and the Chebyshev
approximations have the maximum possible number of them

270

CHEBYSHEV FILTERS

distributed in the passband, maximum power transfer occurs

between the terminations. In this condition, errors in the capacitors and inductors can only decrease the gain (5). This
causes zeros in the derivative T( j)/L, C at all the attenuation zeros, and keeps low the error in all the passband. Table
2 lists polynomials, poles, frequency, and Q of the poles, and
values for LC doubly terminated ladder structures, with the
structure shown in Fig. 4(a), for some normalized Chebyshev
low-pass filters. Note in the realizations that odd-order filters
have identical terminations, but even-order filters require different terminations, because there is no maximum power
transfer at 0, since the gain is not maximum there. With
the impedance normalization shown, it is clear that the evenorder realizations have antimetrical structure (one side is the
dual of the other). The odd-order structures are symmetrical.

The selectivity of the inverse Chebyshev approximation is

the same as the corresponding Chebyshev approximation, for
the same Amax and Amin. This can be verified by calculating the
ratio p /r for both approximations. For the normalized Chebyshev approximation, p 1, and r occurs when Cn(r)
. For the normalized inverse Chebyshev approximation, r
1, and p occurs when ()/Cn(1/p) . In both cases, the
resulting ratio is r /p C1
n (). Equation (11) can be used to
compute the required degree.
The transmission zero frequencies are the frequencies that
make Eq. (19) infinite:

Cn (1/k ) = cos(n cos1 (1/k )) = 0 )

k =
cos

1
,
1 + 2k
2
n

k = 0, 1, . . ., n 1

(23)

THE INVERSE CHEBYSHEV LOW-PASS APPROXIMATION

This normalized inverse Chebyshev approximation is the
most important member of the inverse polynomial class of approximations. It is conveniently obtained by using the characteristic function obtained from
K( j) =


 n
F( j)
=
= n
P( j)
Cn (1/)
Cn (1/)

(19)

where and are given by Eqs. (10) and (11). The polynomials F(s) and P(s) are then
F (s) =  (s/ j)n
P(s) = (s/ j) Cn ( j/s)
n

(20)

Ignoring j or 1 multiplying factors in Eq. (20) and renormalizations, F(s) reduces to sn, and P(s) to a Chebyshev
polynomial with all the terms positive and the coefficients in
reverse order. The magnitude characteristic of this approximation is maximally flat at 0, due to the n attenuation
zeros at s 0, and so is similar in the passband to a Butterworth approximation. In the stopband, it presents a series of
transmission zeros at frequencies that are the inverse of the
roots of the corresponding Chebyshev polynomial. Between
adjacent transmission zeros, there are gain maxima reaching
the magnitude of Amin dB. Without a renormalization, the
stopband starts at 1 rad/s, and the passband ends where the
magnitude of the characteristic function, Eq. (19), reaches :

1
1



p = 1
=
1
Cn ( )
cosh n1 cosh

(21)

Odd-order filters present a single transmission zero at

infinity, and even-order filters end up with a constant gain
Amin at . From Eqs. (1) and (19), the attenuation in
decibels for a normalized inverse Chebyshev approximation is

2 


(22)
A() = 10 log 1 +
Cn (1/)
The gains for some normalized inverse Chebyshev approximations are plotted in Fig. 5. A frequency scaling by the inverse
of the factor given by Eq. (21) was applied to make the passband end at 1.

The pole frequencies are found by solving Eq. (2) with F(s)
and P(s) given by Eq. (20):
E(s)E(s) = ( )2

s 2n
s 2n
j

Cn

j 2
s

(24)

The roots of this equation are the solutions of

Cn

j
s

= j

(25)

By observing the similarity of this equation to Eq. (14), the

roots of E(s)E(s) can be obtained as the complex inverses of
the values given by Eq. (18), with replaced by 1/(). They
lie on a curve that is not an ellipse. E(s) is constructed from
the roots with negative real parts, which are distributed in
a pattern that resembles a circle shifted to the left side of
the origin.
The similarity of the passband response to the Butterworth response makes the phase characteristics of the inverse
Chebyshev filters much closer to linear than those of the
Chebyshev filters. The Qs of the poles are also significantly
lower for the same gain specifications.
REALIZATION OF INVERSE CHEBYSHEV FILTERS
The realization based on LC doubly terminated ladder structures is also convenient for inverse Chebyshev filters for the
same reasons mentioned for the direct approximation. In this
case, the passband sensitivities are low due to the nth-order
attenuation zero at s 0, which results in nullification of the
first n derivatives of the filter gain in relation to all the reactive elements at s 0 and keeps the gain errors small in
all the passband. Stopband errors are also small, because the
transmission zero frequencies depend only on simple LC series or parallel resonant circuits. The usual structures used
are shown in Fig. 4(b).
Those realizations are possible only for the odd-order
cases, because those structures cannot realize the constant
gain at infinity that occurs in the even-order approximations
(realizations with transformers or with negative elements are
possible). Even-order modified approximations can be obtained by using, instead of the Chebyshev polynomials, poly-

CHEBYSHEV FILTERS

271

Table 2. Normalized Chebyshev Filters with Amax 1 dB

Polynomials E(s)
n
a0
1
1.96523
2
1.10251
3
0.49131
4
0.27563
5
0.12283
6
0.06891
7
0.03071
8
0.01723
9
0.00768
10
0.00431
Poles
n
re/im 1
1
1.96523
2
0.54887
0.89513
3
0.24709
0.96600
4
0.13954
0.98338
5
0.08946
0.99011
6
0.06218
0.99341
7
0.04571
0.99528
8
0.03501
0.99645
9
0.02767
0.99723
10
0.02241
0.99778
Polynomials P(s)
n
Multiplier
1
1.96523
2
0.98261
3
0.49131
4
0.24565
5
0.12283
6
0.06141
7
0.03071
8
0.01535
9
0.00768
10
0.00384
Doubly terminated
n
Rg/Rl
1
1.00000
1.00000
2
1.63087
0.61317
3
1.00000
1.00000
4
1.63087
0.61317
5
1.00000
1.00000
6
1.63087
0.61317
7
1.00000
1.00000
8
1.63087
0.61317
9
1.00000
1.00000
10
1.63087
0.61317

a1
1.00000
1.09773
1.23841
0.74262
0.58053
0.30708
0.21367
0.10734
0.07060
0.03450
/Q 1
1.05000
0.95652
0.99710
2.01772
0.99323
3.55904
0.99414
5.55644
0.99536
8.00369
0.99633
10.89866
0.99707
14.24045
0.99761
18.02865
0.99803
22.26303

a2
1.00000
0.98834
1.45392
0.97440
0.93935
0.54862
0.44783
0.24419
0.18245
re/im 2

a3

1.00000
0.95281
1.68882
1.20214
1.35754
0.84682
0.78631
0.45539
/Q 2

a4

1.00000
0.93682
1.93082
1.42879
1.83690
1.20161
1.24449
re/im 3

a5

1.00000
0.92825
2.17608
1.65516
2.37812
1.61299
/Q 3

a6

1.00000
0.92312
2.42303
1.88148
2.98151
re/im 4

a7

1.00000
0.91981
2.67095
2.10785
/Q 4

a8

1.00000
0.91755
2.91947
re/im 5

a9

a10

1.00000
0.91593

1.00000

/Q 5

0.49417
0.33687
0.40733
0.23421
0.61192
0.16988
0.72723
0.12807
0.79816
0.09970
0.84475
0.07967
0.87695
0.06505
0.90011

a0
1.00000
1.00000
1.00000
1.00000
1.00000
1.00000
1.00000
1.00000
1.00000
1.00000
LC ladder realizations
L/C1
L/C2

0.52858
0.78455
0.65521
1.39879
0.74681
2.19802
0.80837
3.15586
0.85061
4.26608
0.88056
5.52663
0.90245
6.93669

L/C3

0.28949
0.23206
0.26618
0.18507
0.44294
0.14920
0.56444
0.12205
0.65090
0.10132
0.71433

0.35314
0.76087
0.48005
1.29693
0.58383
1.95649
0.66224
2.71289
0.72148
3.56051

L/C4

L/C5

0.20541
0.17600
0.19821
0.14972
0.34633
0.12767
0.45863

0.26507
0.75304
0.37731
1.26004
0.47606
1.86449

L/C6

L/C7

0.15933
0.14152
0.15803

0.21214
0.74950

L/C8

L/C9

L/C10

1.01769
1.11716
1.11716
0.99410
2.02359

2.02359
1.73596

1.28708

1.73596

1.28708

3.00092

1.09111
1.87840

1.09111
2.13488
1.80069
1.32113

1.87840
1.11151

2.16656

1.17352

1.82022

1.93073

1.11918

1.18967

1.33325
1.82022

1.18967
3.17463

1.94609
1.91837

2.16656
1.90742

1.93073

3.12143
1.82874

1.33890

1.11151
3.09364

1.90742

2.17972

1.32113
1.80069

3.09364

1.33325

2.13488

1.11918
3.12143

1.95541
1.95541

2.17972
1.91837

1.94609

1.33890
1.82874

272

CHEBYSHEV FILTERS

nomials obtained by the application, to the Chebyshev polynomials, of the Moebius transformation (4,6):

|T( j)|dB
0

x
x
1
2

x2z1
;
x2z1

xz1

kmax
= cos
2n

Ln

C3

Rl

Cn

Rg

Rg

L1

10

1
(a)
|T( j)|dB
1

100

0
1
1

100
(b)
Figure 5. Passband gain (a) and stopband gain (b) for the first normalized inverse Chebyshev approximations with Amax 1 dB and
Amin 50 dB. Observe the maximally flat passband and the uniform
stopband ripple.

OTHER SIMILAR APPROXIMATIONS

L2

C2

Rl

(a)

C1

L2

C1

(26)

where kmax is the greatest odd integer that is less than the
filter order n. This transformation moves the pair of roots
closest to the origin of an even-order Chebyshev polynomial
to the origin. If the resulting polynomials are used to generate
polynomial approximations, starting from Eq. (7), the results
are filters with two attenuation zeros at the origin, which are
realizable as doubly terminated ladder filters with equal terminations, a convenience in passive realizations. If the same
polynomials are used in inverse polynomial approximations,
starting from Eq. (19), the results are filters with two transmission zeros at infinity, which now are realizable by doubly
terminated LC structures. The direct and inverse approximations obtained in this way have the same selectivity, slightly
smaller than in the original case.
Table 3 lists polynomials, poles, zeros, frequency and Q of
the poles, and LC doubly terminated realizations for some inverse Chebyshev filters. The filters were scaled in frequency
to make the passband end at 1 rad/s. The even-order realizations are obtained from modified approximations and are
listed separately in Table 4. The structures are a mix of the
two forms in Fig. 5(b). Note that some realizations are missing. These are cases where the zero-shifting technique for the
realization of LC doubly terminated ladder filters fails. For
inverse Chebyshev filters, and other inverse polynomial filters, there is a minimum value of Amin for each order that
makes the realization in this form possible (7).

Rg

C3

L3

Rl

Cn

Ln

L2
Rl
C2
(b)
Figure 4. LC doubly terminated ladder realizations for Chebyshev
filters, in the direct form (a), and in the inverse form (b). These classical realizations continue to be the best prototypes for active realizations, due to their low sensitivity to errors in element values.

Different approximations with uniform passband or stopband

ripple, somewhat less selective, can be generated by reducing
the number or the amplitude of the oscillations in a Chebyshev-like polynomial and generating the approximations
starting from Eqs. (7) or (19) numerically (8).
A particularly interesting case results if the last oscillations of the polynomial value end in 0 instead of 1. This
creates double roots close to x 1 in the polynomial. In
a polynomial approximation, the higher-frequency passband
minimum disappears, replaced by a second-order maximum
close to the passband border. In an LC doubly terminated realization, the maximum power transfer at this frequency
causes the nullification of the first two derivatives of the gain
in relation to the reactive elements, substantially reducing
the gain error at the passband border. In an inverse polynomial approximation, this causes the joining of the first two
transmission zeros, as a double transmission zero, which increases the attenuation and reduces the error at the beginning of the stopband, allowing also symmetrical realizations
for orders 5 and 7.

CHEBYSHEV FILTERS

273

Table 3. Normalized Inverse Chebyshev Filters with Amax 1 dB and Amin 50 dB

Polynomials E(s)
n
a0
1
1.96523
2
1.96838
3
2.01667
4
2.19786
5
2.60322
6
3.35081
7
4.64002
8
6.82650
9
10.54882
10
16.95789
Poles
n
re/im 1
1 1.96523

a1
1.00000
1.98099
3.14909
4.52937
6.42983
9.35051
14.09440
22.03426
35.60372
59.19226
/Q 1

a2
1.00000
2.51015
4.90289
8.61345
14.61162
24.72451
42.29782
73.49954
129.8094
re/im 2

0.99049
1.40299
0.99363
0.70823
3 0.61468
1.25481
1.28079
1.09395
1.02071
4 0.42297
1.18385
1.14262
1.10571
1.39945
0.51249
5 0.30648
1.13993
0.94418
1.09795
1.85969
0.79849
6 0.23016
1.10962
0.75398
1.08549
2.41056
0.95283
7 0.17794
1.08768
0.59638
1.07303
3.05632
1.02930
8 0.47425
1.16431
0.14101
1.06334
1.22752
1.06205
9 0.38185
1.14152
0.77805
1.07575
1.49471
1.06189
10 0.63221
1.27960
0.31203
1.11252
1.01201
1.07766
Polynomials P(s)
a2
n Multiplier
a0
1
1.96523
1.00000
2
0.00316
622.4562
1.00000
3
0.05144
39.20309
1.00000
4
0.00316
695.0228
74.56663
5
0.03477
74.86195
19.34709
6
0.00316 1059.620
494.9652
7
0.03463
133.9940
95.81988
8
0.00316 2158.727
2130.497
9
0.03786
278.6600
354.3952
10
0.00316 5362.556
8380.916
Zeros
2
3
n
1
1
2
24.94907
3
6.26124
4
7.97788
3.30455
5
3.74162
2.31245
6
6.92368
2.53424
1.85520
7
3.60546
2.00088
1.60458
8
7.29689
2.56233
1.71209
9
3.88896
2.06927
1.53587
10
8.08496
2.78589
1.78865
LC doubly terminated realizations
n
Rg/Rl
L/C 1
L/C 2
1
1.00000
1.00000
1.01769
3
1.00000
1.56153
1.00000
0.78077
0.01634
5
1.00000
1.16364
1.00000
0.37813
0.16071
7
1.00000
0.72897
1.00000
0.09574
0.34265

a3

1.00000
3.13118
7.26320
14.91369
29.03373
55.31092
104.6829
198.2422
/Q 2

a4

1.00000
3.81151
10.30744
24.18372
52.89124
111.4815
230.3472
re/im 3

a5

a6

a7

a8

a9

a10

1.00000
4.54023
14.09633
37.20009
90.07839
207.4480

1.00000
5.30979
18.68307
54.81844
145.4877

1.00000
6.11268
24.10445
77.89699

1.00000
6.94337
30.39330

1.00000
7.79647

1.00000

/Q 3

re/im 4

/Q 4

re/im 5

/Q 5

1.25229
0.54799
1.23656
0.65483
1.21506
0.80576
1.18959
0.99735
1.07137
3.79891
1.31643
0.84597
1.12193
1.79777

1.31018
1.28598
0.43545
1.14085
0.75619
0.95398
0.95496
0.11413
1.05282
0.09407
1.04521

a4

a6

1.00000
1.00000
57.80151
19.57753
657.0734
150.2380
4584.365

1.00000
1.00000
64.84805
23.58892
1023.530

1.45144
1.35062
1.41948
L/C 3

1.35770
0.52789
1.36871
0.59986
1.34983
0.70747
1.05899
4.63922
1.04944
5.57772
a8

1.00000
1.00000
79.98165

1.47946
1.48710
0.44316
1.34453
0.79596
1.13939
1.02161

1.55173
0.52173
1.56247
0.58105
1.53032
0.67155

1.32044

1.72054
0.47954

1.78611
0.51906

L/C 8

L/C 9

a10

1.00000

1.28053
L/C 4

L/C 5

L/C 6

L/C 7

0.96491
0.07972

0.30081

0.78077
1.62010

1.70623

1.30631
0.05468
1.34370
0.28905

0.47172
1.32059

L/C 10

274

CHEBYSHEV FILTERS

Table 4. Normalized Even-order Modified Inverse Chebyshev Filters with

Two Transmission Zeros at Infinity, with Amax 1 dB and Amin 50 dB
Polynomials E(s)
a1
a2
n
a0
2
1.96523
1.98254
1.00000
4
2.12934
4.47598
4.86847
6
3.14547
9.02141
14.23655
8
6.32795 20.98707
40.68275
10
15.69992 56.17036
124.1801
Poles
n
re/im 1
/Q 1
re/im 2
2 0.99127
1.40187
0.99127
0.70711
4 0.43134
1.18419
1.12886
1.10284
1.37268
0.49409
6 0.23626
1.11107
0.76275
1.08566
2.35141
0.93457
8 0.14421
1.07247
0.48399
1.06273
3.71848
1.05767
10 0.64341
1.27784
0.31781
1.10404
0.99303
1.07652
Polynomials P(s)
a2
n
Multiplier
a0
2
1.96523
1.00000
4
0.16412 12.97454
1.00000
6
0.11931 26.36278
10.89186
8
0.13145 48.13911
44.73326
10
0.16119 97.39855
147.0191
Zeros
2
3
n
1
2
4
3.60202
6
2.69467
1.90542
8
2.71078
1.74464
1.46706
10
2.94484
1.82001
1.43081
LC doubly terminated ladder realizations
n
Rg/Rl
L/C 1
L/C 2
2
1.00000
1.00881
1.00000
1.00881
4
1.00000
1.51207
1.00000
0.64094
6
1.00000
0.87386
1.00000
0.17880
0.31519
8
1.00000
0.67581
1.00000
0.32898

a3

a4

a5

a6

a7

a8

a9

a10

3.12041
14.65051
53.69811
191.3464

1.00000
10.18872
51.69862
223.6989

4.51414
36.58972
202.6490

1.00000
18.48009
142.8395

6.07949
76.84994

1.00000
30.12162

7.76165

1.00000

/Q 2

re/im 3

/Q 3

re/im 4

/Q 4

re/im 5

/Q 5

1.67803
0.44586

1.73625
0.51735

1.23225
0.54580
1.20632
0.79077
1.16315
1.20162
1.12245
1.76590
a4

1.00000
12.54437
76.50032

1.25806
0.41016
0.96075
0.92940
0.09573
1.04574
a6

1.00000
15.68797

1.32324
0.52590
1.33672
0.69566
1.05011
5.48452

1.45079
0.41357
1.14584
0.99132

1.50858
0.51992
1.51514
0.66115

a8

1.00000

1.28694
L/C 3

L/C 4

0.05275
1.46110

0.58997
1.67233

1.63514
0.32023
1.02594

1.34317

Other variations arise from the shifting of roots to the origin. This is also best done numerically. Odd- (even-) order
polynomial approximations with any odd (even) number of attenuation zeros at 0, up to the approximations order (in
the last case resulting in a Butterworth approximation), can
be generated. The same polynomials generate inverse polynomial approximations with any odd (even) number of transmission zeros at infinity.
In all cases, the Q of the poles is reduced and the phase is
closer to linear. Similar techniques can also be applied to elliptic approximations. For example, a low-pass elliptic approximation can be transformed into a Chebyshev approximation by the shifting of all the transmission zeros to infinity,
or into an inverse Chebyshev approximation by shifting all
the attenuation zeros to the origin. There are many variations
between these extremes.

L/C 5

L/C 6

0.13065
1.05413
0.38303
1.21303

0.32187
1.12998

L/C 7

L/C 8

0.18178
0.74862

0.16760

BIBLIOGRAPHY
1. A. Antoniou, Digital Filters: Analysis, Design, and Applications,
New York: McGraw-Hill, 1993.
2. P. L. Chebyshev, Theorie des mecanismes connus sous le nom de
parallelogrammes, Oeuvres, Vol. I, St. Petersburg, 1899.
3. M. E. Van Valkenburg, Analog Filter Design, New York: Holt,
Rinehart and Winston, 1982.
4. R. W. Daniels, Approximation Methods for Electronic Filter Design, New York: McGraw-Hill, 1974.
5. H. J. Orchard, Inductorless filters, Electronics Lett., 2: 224225,
1996.
6. G. C. Temes and J. W. LaPatra, Circuit Synthesis and Design,
Tokyo: McGraw-Hill Kogakusha, 1977.
7. L. Weinberg, Network Analysis and Synthesis, New York:
McGraw-Hill, 1962.

CHEMICAL LASERS
8. A. C. M. de Queiroz and L. P. Caloba, An approximation algorithm for irregular-ripple filters, IEEE International Telecommunications Symposium, Rio de Janeiro, Brazil, pp. 430433, September 1990.

ANTONIO CARLOS M. DE QUEIROZ

Federal University of Rio de Janeiro

CHEMICAL INDUSTRY. See PETROLEUM INDUSTRY.

275

398

CIRCUIT STABILITY

CIRCUIT STABILITY
Stability is a property of well-behaved circuits and systems.
Typically, stability is discussed in terms of feedback systems.
Well-established techniques, such as Nyquist plots, Bode diagrams, and root locus plots are available for studying the stability of feedback systems. Electric circuits can be represented
as feedback systems. Nyquist plots, Bode diagrams, and root
locus plots can then be used to study the stability of electric
circuits.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

CIRCUIT STABILITY

FEEDBACK SYSTEMS AND STABILITY

T (s) =

A(s)
Vo (s)
=
Vi (s)
1 + A(s)B(s)

(1)

Suppose that the transfer functions A(s) and B(s) can each be
expressed as ratios of polynomials in s. Then
A(s) =

NA (s)
DA (s)

and B(s) =

NB (s)
DB (s)

(2)

where NA(s), DA(s), NB(s), and DB(s) are polynomials in s. Substituting these expressions into Eq. (1) gives

NA (s)
NA (s)DB (s)
N(s)
DA (s)
=
=
T (s) =
NA (s) NB (s)
DA (s)DB (s) + NA (s)NB (s)
D(s)
1+
DA (s) DB (s)
(3)
where the numerator and denominator of T(s), N(s) and D(s),
are both polynomials in s. The values of s for which N(s)  0
are called the zeros of T(s) and the values of s that satisfy
D(s)  0 are called the poles of T(s).
Stability is a property of well-behaved systems. For example, a stable system will produce bounded outputs whenever
its input is bounded. Stability can be determined from the
poles of a system. The values of the poles of a feedback system
will, in general, be complex numbers. A feedback system is
stable when all of its poles have negative real parts.
The equation
1 + A(s)B(s) = 0

(4)

is called the characteristic equation of the feedback system.

The values of s that satisfy the characteristic equation are
poles of the feedback system. The left-hand side of the characteristic equation, 1  A(s)B(s), is called the return difference

vi(t)
Input
signal

Summer
+
+

vT(s) = 1

vR(s) = A(s)B(s)

Consider a feedback system such as the one shown in Fig. 1.

This feedback system consists of three parts: a forward block,
sometimes called the plant, a feedback block, sometimes
called the controller, and a summer. The signals vi(t) and
vo(t) are the input and output of the feedback system. A(s) is
the transfer function of the forward block and B(s) is the
transfer function of the feedback block. The summer subtracts
the output of the feedback block from vi(t). The transfer function of the feedback system can be expressed in terms of A(s)
and B(s) as

Foward block
A(s)

vo(t)
Output
signal

vi(s) = 0

399

Foward block

Summer
+
+

A(s)

B(s)
Feedback block
Figure 2. Measuring the return difference: The difference between
the test input signal, VT(s), and the test output signal, VR(s), is the
return difference.

of the feedback system. Figure 2 shows how the return difference can be measured. First, the input, vi(t), is set to zero.
Next, the forward path of the feedback system is broken.
Figure 2 shows how a test signal, VT(s)  1, is applied and
the response, VR(s)  A(s)B(s), is measured. The difference
between the test signal and its response is the return difference.
The calculation

return difference = 1 +A(s)B(s) =

1+

NA (s) NB (s) DA (s)DB (s) +NA (s)NB (s)

=
DA (s) DB (s)
DA (s)DB (s)

shows that
1. The zeros of 1  A(s)B(s) are equal to the poles of T(s).
2. The poles of 1  A(s)B(s) are equal to the poles of
A(s)B(s).
Consider a feedback system of the form shown in Fig. 1
with
A(s) =

s+5
s2 4s + 1

and B(s) =

3s
s+3

(5)

The poles of the forward block are the values of s that satisfy
s2  4s  1  0 (that is, s1  3.73 and s2  0.26). In this case,
both poles have real, rather than complex, values. The forward block would be stable if both poles were negative. They
are not, so the forward block is itself an unstable system. To
see that this unstable system is not well behaved, consider its
step response (1,2). The step response of a system is its zero
state response to a step input. In other words, suppose the
input to the forward block was zero for a very long time. At
some particular time, the value of input suddenly becomes
equal to 1 and remains equal to 1. The response of the system
is called the step response. The step response can be calculated by taking the inverse Laplace transform of A(s)/s. In
this example, the step response of the forward block is

B(s)

step response = 5 + 0.675e3.73t 5.675e0.27t

Feedback block

As time increases, the exponential terms of the step response

get very, very large. Theoretically, they increase without

Figure 1. A feedback system.

400

CIRCUIT STABILITY

bound. In practice, they increase until the system saturates

or breaks. This is typical of the undesirable behavior of an
unstable system.
According to Eq. (3), the transfer function of the whole
feedback system is

s+5
4s + 1
T (s) =
3s
s+5

1+ 2
s 4s + 1 s + 3
(s + 5)(s + 3)
s2 + 8s + 15
= 2
= 3
(s 4s + 1)(s + 3) + (s + 5)(3s)
s + 2s2 + 4s + 3
s2

ber of encirclements of the point 1  j0 by the curve in the

A(s)B(s)-plane. Let

N = the number of encirclements, in the clockwise direction,

of 1 + j0 by the closed curve in the A(s)B(s)-plane
Z = The number of poles of T (s) in the right half of the splane
P = The number of poles of A(s)B(s) in the right half of the
s-plane
The Nyquist stability criterion states that N, Z, and P are
related by
Z=P+N

The poles of the feedback system are the values of s that satisfy s3  2s2  4s  3  0that is, s1  1, s2  0.5 
j1.66 and s3  0.5  j1.66. The real part of each of these
three poles is negative. Since all of the poles of the feedback
system have negative real parts, the feedback system is stable. To see that this stable system is well behaved, consider
its step response. This step response can be calculated by taking the inverse Laplace transform of T(s)/s. In this example,
the step response of the feedback system is

step response = 5 11.09et cos( 2t + 63 )

A(s)B(s) =

3s2 + 15s
3s2 + 15s
=
s3 s2 11s + 3
(s 3.73)(s 0.26)(s + 3)
(7)

Figure 3 shows the Nyquist plot for this feedback system.

This plot was obtained using the MATLAB commands

STABILITY CRITERIA
Frequently, the information about a feedback system that is
most readily available is the transfer functions of the forward
and feedback blocks, A(s) and B(s). Stability criteria are tools
for determining if a feedback system is stable by examining
A(s) and B(s) directly, without first calculating T(s) and then
calculating its polesthat is, the roots of the denominator of
T(s). Two stability criteria will be discussed here: the Nyquist
stability criteria and the use of Bode diagrams to determine
the gain and phase margin.
The Nyquist stability criterion is based on a theorem in the
theory of functions of a complex variable (1,3,4). This stability
criterion requires a contour mapping of a closed curve in the
s-plane using the function A(s)B(s). The closed contour in the
s-plane must enclose the right half of the s-plane and must
not pass through any poles or zeros of A(s)B(s). The result of
this mapping is a closed contour in the A(s)B(s)-plane. Fortunately, the computer program MATLAB (5,6) can be used to
generate an appropriate curve in the s-plane and do this
mapping.
Rewriting the characteristic equation, Eq. (4), as
(6)

suggests that the relationship of the closed contour in the

A(s)B(s)-plane to the point 1  j0 is important. Indeed, this
is the case. The Nyquist stability criterion involves the num-

num=[0

15 0]; %Coefficients of the

numerator of A(s)B(s)
den=[1 -1 -11 3]; %Coefficients of the
denominator of A(s)B(s)
nyquist (num,den)

Since A(s)B(s) has two poles in the right half of the s-plane,
P  2. The Nyquist plot shows two counterclockwise encirclements of 1  j0 so N  2. Then Z  P  N  0, indicating
that the feedback system is stable.
Feedback systems need to be stable in spite of variations
in the transfer functions of the forward and feedback blocks.
The gain and phase margins of a feedback system give an
indication of how much A(s) and B(s) can change without
causing the system to become unstable. The gain and phase

0.8
0.6
0.4
Image axis

In contrast to the previous case, as time increases et becomes

zero so the second term of the step response dies out. This
stable system does not exhibit the undesirable behavior typical of unstable systems.

A(s)B(s) = 1

A stable feedback system will not have any poles in the right
half of the s-plane so Z  0 indicates a stable system.
For example, suppose the forward and feedback blocks of
the feedback system shown in Fig. 1 have the transfer functions described by Eq. (5). Then

0.2
0
0.2
0.4
0.6
0.8
1.4

1.2

0.8
0.6
Real axis

0.4

0.2

Figure 3. A Nyquist plot produced using MATLAB.

CIRCUIT STABILITY

margins can be determined using Bode diagrams. To obtain

the Bode diagrams, first let s  j so that Eq. (6) becomes
A( j)B( j) = 1

vi(t)

The value of A( j)B( j) will, in general, be complex.

Two Bode diagrams are used to determine the gain and
phase margins. The magnitude Bode diagram is a plot
of 20 log[A( j)B( j)] versus . The units of
20 log[A( j)B( j)] are decibels. The abbreviation for decibel
is dB. The magnitude Bode diagram is sometimes referred to
as a plot of the magnitude of A( j)B( j), in dB, versus . The
phase Bode diagram is a plot of the angle of A( j)B( j) versus .
It is necessary to identify two frequencies: g, the gain
crossover frequency, and p, the phase crossover frequency.
To do so, first take the magnitude of both sides of Eq. (7) to
obtain
A( j)B( j) = 1

20 log[ A( j)B( j) ] = 0

(9)

Equation (8) or (9) is used to identify a frequency, g, the gain

crossover frequency. That is, g is the frequency at which

\(A( j)B( j)) = 180

(10)

Equation (10) is used to identify a frequency, p, the gain

crossover frequency. That is, p is the frequency at which

\ A( jp ) + \ B( jp ) = 180

(11)

Pm = 11.62 ( = 2.247)

20
Gain (dB)

RL

vo(t)

The gain margin of the feedback system is

gain margin =

1
A( jp ) B( jp )

(12)

The phase margin is

phase margin = 180 (\ A( jg ) + \ B( jg ))

(13)

The gain and phase margins can be easily calculated using

MATLAB. For example, suppose the forward and feedback
blocks of the feedback system shown in Fig. 1 have the transfer functions described by Eq. (3). Figure 4 shows the Bode
diagrams for this feedback system. These plots were obtained
using the MATLAB commands
15 0]; %Coefficients of the
numerator of A(s)B(s)
den=[1 -1 -11 3]; %Coefficients of the
denominator of A(s)B(s)
margin (num,den)

Next, take the angle of both sides of Eq. (4) to

MATLAB has labeled the Bode diagrams in Fig. 4 to show the

gain and phase margins. The gain margin of 1.331 dB indicates that a decrease in A(s)B(s) of 1.331 dB or, equivalently,
a decrease in gain by a factor of 0.858, at the frequency p 
1.378 rad/s, would bring the system the boundary of instability. Similarly, the phase margin of 11.6 indicates that an increase in the angle of A(s)B(s) of 11.6, at the frequency g 
2.247 rad/s, would bring the system the boundary of instability.
When the transfer functions A(s) and B(s) have no poles or
zeros in the right half of the s-plane, then the gain and phase
margins must both be positive in order for the system to be

20
40
102

101

100
Frequency (rad/s)

101

102

vi(t)
0
Phase (deg)

Figure 5. A circuit that is to be represented as a feedback system.

num=[0

A( jg ) B( jg ) = 1

Gm = 1.311 dB, ( = 1.378)

(8)

Converting to decibels gives

A circuit consisting of
resistors, capacitors, and
op amps

401

NB
RL

vo(t)

90
180

The rest of
the circuit

270
360
102

101

100
Frequency (rad/s)

101

102

Figure 4. Bode plot used to determine the phase and gain margins.
The plots were produced using MATLAB.

an op amp
Figure 6. Identifying the subcircuit NB by separating an op amp
from the rest of the circuit.

402

CIRCUIT STABILITY

model of the op amp indicates that the op amp input and output voltages are related by
vi(s)

NB

RL

VB (s) = K(s)VA (s)

vo(s)

The network NB can be represented by the equation



Vo (s)
VA (s)

+
+ v (s) = K(s) v (s)
A
B

vA(s)

(14)

T11 (s)
T21 (s)



T12 (s)
T22 (s)

Vi (s)
VB (s)

(15)

Combining Eqs. (14) and (15) yields the transfer function of

the circuit
T (s) =

Figure 7. Replacing the op amp with a model of the op amp.

Vo (s)
T (s)K(s)T21 (s)
= T11 (s) + 12
Vi (s)
1 K(s)T22 (s)

(16)

or
stable. As a rule of thumb (7), the gain margin should be
greater than 6 dB and the phase margin should be between
30 and 60. These gain and phase margins provide some protection against changes in A(s) or B(s).
STABILITY OF LINEAR CIRCUITS
The Nyquist criterion and the gain and phase margin can be
used to investigate the stability of linear circuits. To do so
requires that the parts of the circuit corresponding to the forward block and to the feedback block be identified. After this
identification is made, the transfer functions A(s) and B(s) can
be calculated.
Figures 58 illustrate a procedure for finding A(s) and
B(s) (8). For concreteness, consider a circuit consisting of resistors, capacitors, and op amps. Suppose further that the input and outputs of this circuit are voltages. Such a circuit is
shown in Fig. 5. In Fig. 6 one of the op amps has been separated from the rest of the circuit. This is done to identify the
subcircuit NB. The op amp will correspond to the forward
block of the feedback system while NB will contain the feedback block. NB will be used to calculate B(s). In Fig. 7, the op
amp has been replaced by a model of the op amp (2). This

Vi(s) = 1

NB

RL

+
Vo(s) =
T11(s)

T (s)(1 + K(s)T22 (s)) + T12 (s)K(s)T21 (s)

Vo (s)
= 11
Vi (s)
1 + K(s)T22 (s)

Equation (15) suggests a procedure that can be used to

measure or calculate the transfer functions T11(s), T12(s),
T21(s, and T22(s). For example, Eq. (15) says that when Vi(s) 
1 and VB(s)  0, then Vo(s)  T11(s) and VA(s)  T21(s). Figure
8 illustrates this procedure for determining T11(s) and T21(s).
A short circuit is used to make VB(s)  0 and the voltage
source voltage is set to 1 so that Vi(s)  1. Under these conditions the voltages Vo(s) and VA(s) will be equal to the transfer
functions T11(s) and T21(s). Similarly, when Vi(s)  0 and
VB(s)  1, then Vo(s)  T12(s) and VA(s)  T22(s). Figure 9 illustrates the procedure for determining T12(s) and T22(s). A short
circuit is used to make Vi(s)  0 and the voltage source voltage is set to 1 so that VB1(s)  1. Under these conditions the
voltages Vo(s) and VA(s) will be equal to the transfer functions
T11(s) and T21(s).
Next, consider the feedback system shown in Fig. 10. (The
feedback system shown in Fig. 1 is part, but not all, of the
feedback system shown in Fig. 10. When D(s)  0, C1(s)  1
and C2(s)  1; then Fig. 10 reduces to Fig. 1. Considering the
system shown in Fig. 10, rather than the system shown in

NB
RL

Vi(s) = 0

+
Vo(s) =
T12(s)

+
VA(s) = T21(s)

T (s) =

VB(s) = 0

Figure 8. The subcircuit NB is used to calculate T12(s) and T22(s).

VA(s) = T22(s)

VB(s) = 1

Figure 9. The subcircuit NB is used to calculate T11(s) and T21(s).

CIRCUIT STABILITY

403

D(s)
+
vi(t)

C1(s)

A(s)

C2(s)

vo(t)

Figure 10. A feedback system that corresponds to

a linear system.

B(s)

Fig. 1, avoids excluding circuits for which D(s) 0, C1(s) 1,

or C2(s) 1.) The transfer function of this feedback system is
T (s) =

C (s)A(s)C2 (s)
Vo (s)
= D(s) + 1
Vi (s)
1 + A(s)B(s)

T (s) =

(17)

or
T (s) =

As an example, consider the SallenKey bandpass filter (9)

shown in Fig. 11. The transfer function of this filter is

D(s)(1 + A(s)B(s)) + C1 (s)A(s)C2 (s)

Vo (s)
=
Vi (s)
1 + A(s)B(s)

Comparing Eqs. (16) and (17) shows that

A(s) = K(s)

(18a)

B(s) = T22 (s)

(18b)

5460s
Vo (s)
= 2
Vi (s)
s + 199s + 4 106

The first step toward identifying A(s) and B(s) is to separate

the op amp from the rest of the circuit, as shown in Fig. 12.
Separating the op amp from the rest of the circuit identifies
the subcircuit NB. Next, NB is used to calculate the transfer
functions T11(s), T12(s), T21(s), and T22(s). Figure 13 corresponds
to Fig. 8 and shows how T12(s) and T22(s) are calculated. Analysis of the circuit shown in Fig. 13 gives
T12 (s) = 1 and T22 (s) =

C1 (s) = T12 (s)

C2 (s) = T21 (s)
D(s) = T11 (s)
Finally, with Eqs. (18a) and (18b), the identification of A(s)
and B(s) is complete. In summary,
1. The circuit is separated into two parts: an op amp and
NB, the rest of the circuit.

0.259s2 + 51.6s + 1.04 106

(20)
s2 + 5660s + 4 106

(The computer program ELab, Ref. 10, provides an alternative to doing this analysis by hand. ELab will calculate the
transfer function of a network in the form shown in Eq. (16)
that is, as a symbolic function of s. ELab is free and can be
downloaded
from
http://sunspot.ece.clarkson.edu:1050/
svoboda/software.html on the World Wide Web.)
Figure 14 corresponds to Fig. 9 and shows how T11(s) and
T21(s) are calculated. Analysis of the circuit shown in Fig. 14
gives

2. A(s) is open-loop gain of the op amp, as shown in Fig. 7.

3. B(s) is determined from the subcircuit NB, as shown in
Fig. 9.

vi(t)

vi(t)

R1

R4
C1

+
vo(t)

1410s
s2 + 5660s + 4 106

T11 (s) = 0 and T21 (s) =

R3
C2

(19)

R1

R3

R4

C2

+
vo(t)

R5

R2

C1

(21)

R2
R5
Rb

Figure 11. A Sallen-Key bandpass filter. R1  R2  R3  R5  7.07

k, R4  20.22 k, and C1  C2  0.1 F.

An op amp
Figure 12. Identifying the subcircuit NB by separating an op amp
from the rest of the circuit.

404

CIRCUIT STABILITY

Vi(s) = 1

R1

R3

R5

R2

C1

+
Vo(s) = T11(s)

R4

C2

example, when the op amp is a A741 op amp, then Ao 

200,000 and B  2 106 rad/s, so
K(s) =

Equation (18) indicates that A(s)  K(s) and B(s) 

T22(s), so in this example
A(s) =

NB

200, 000
s + 31.4

VA(s) = T21(s)

VB(s) = 0

200, 000
and B(s) = 0.259
s + 31.4

s2 + 51.6s + 1.04 106 

s2 + 5600s + 4 106

To calculate the phase and gain margins of this filter, first

calculate

A(s)B(s) =
Figure 13. The subcircuit NB1 is used to calculate T11(s) and T21(s).

Substituting Eqs. (20) and (21) into Eq. (16) gives

1410s
s2 + 5660s + 4 106
T (s) =

0.259s2 + 51.6s + 1.04 106 
1 K(s)
s2 + 5660s + 4 106
K(s)

(22)

When the op amp is modeled as an ideal op amp, K(s)

and Eq. (22) reduces to Eq. (19). This is reassuring but only
confirms what was already known. Suppose that a more accurate model of the op amp is used. A frequently used op amp
model (2) represents the gain of the op amp as

K(s) =

Ao
B
s+
Ao

(23)

where Ao is the dc gain of the op amp and B is the gain-bandwidth product of the op amp (2). Both Ao and B are readily
available from manufacturers specifications of op amps. For

s3

51, 800(s2 + 51.6s + 1.04 106 )

+ 5974s2 + 5777240s + 1246 106

Next, the MATLAB commands

num=20000*[0 0.259 51.6 1040000];
%Numerator Coefficients
den=[1 5974 5777240 1256*10^6];
%Denominator Coefficients
margin(num,den)
are used to produce the Bode diagram shown in Fig. 15. Figure 15 shows that the SallenKey filter will have an infinite
gain margin and a phase margin of 76.5 when a A741 op
amp is used.
OSCILLATORS
Oscillators are circuits that are used to generate a sinusoidal
output voltage or current. Typically, oscillators have no input.
The sinusoidal output is generated by the circuit itself. This
section presents the requirements that a circuit must satisfy
if it is to function as an oscillator and shows how these requirements can be used to design the oscillator.
To begin, recall that the characteristic equation of a circuit
is
1 + A(s)B(s) = 0
Suppose this equation is satisfied by a value of s of the form
s  0  jo. Then

Vi(s) = 0

R1

R3
R4

C2

C1

Vo(s) = T12(s)

R5

R2

NB
+
VA (s) = T22(s)

+ V (s) = 1
B

Figure 14. The subcircuit NB is used to calculate T12(s) and T22(s).

A( jo )B( jo ) = 1 = 1e j180

(24)

In this case, the steady-state response of the circuit will contain a sustained sinusoid at the frequency o (11). In other
words, Eq. (24) indicates that the circuit will function as an
oscillator with frequency o when A( jo)B( jo) has a magnitude equal to 1 and a phase angle of 180.
As an example, consider using Eq. (24) to design the Wienbridge oscillator, shown in Fig. 16, to oscillate at o  1000
rad/s. The first step is to identify A(s) and B(s) using the procedure described in the previous section. In Fig. 17 the amplifier is separated from the rest of the network to identify the
subcircuit NB. Also, from Eqs. (14) and (18),
A(s) = K

CIRCUIT STABILITY

Gm = Inf dB, () = (NaN) Pm = 76.51 () = (1961)

Gain (dB)

50

50
101

102

103

104

105

104

105

Frequency (rad/s)

0
Phase (deg)

405

90
180
270
360
101

102

103
Frequency (rad/s)

Next, the subcircuit NB is used to determine B(s)  T22(s), as

shown in Fig. 18. From Fig. 18 it is seen that

T22 (s) =

+
RL

Figure 15. The Bode diagrams used to determine the

phase and gain margins of the SallenKey bandpass
filter.

vo(t)

Figure 16. A Wien-bridge oscillator.

1
R
Cs
1
+R
Cs

1

R

1
Cs
+ R+
1
Cs
+R
Cs

1+ R+

Vo(s)

Cs

1

Cs

1
R
Cs
R+

1
1


=
1
1
1
3 + RCs +
1+ R+
Cs +
RCs
Cs
R

+
R


1

Vo(s) = T12(s)

NB

NB
+
VA(s)

+
VB(s)

Figure 17. The amplifier is separated from the rest of the Wienbridge oscillator to identify the subcircuit NB.

+
VA(s) = T22(s)

VB(s) = 1

Figure 18. The subcircuit NB is used to calculate B(s)  T22(s) for

the Wien-bridge oscillator.

406

CIRCUIT STABILITY

so

A(s)B(s) =

3 + RCs +

1
RCs

A( jo )B( jo ) =

K
1
3 + jo RC j
o RC

(25)

1
1
= 0 o =
o RC
RC

0
2

The phase angle of A( jo)B( jo) must be 180 if the circuit is

to function as an oscillator. That requires
jo RC j

Imag axis

Now let s  0  jo to get

(26)

Oscillation also requires that the magnitude of A( jo)B( jo)

be equal to 1. After substituting Eq. (26) into Eq. (25), this
requirement reduces to
K=3
That is, the amplifier gain must be set to 3. Design of the
oscillator is completed by picking values of R and C to make
o  1000 rad/s (e.g., R  10 k and C  0.1 F).
THE ROOT LOCUS

6
6

A(s) =

NA (s)
DA (s)

and B(s) = K

(27)

In this case, A(s) is the ratio of two polynomials in s and

B(s) is the gain that is used to adjust the system. The transfer
function of the feedback system is
T (s) =

N(s)
NA (s)
=
DA (s) + KNA (s)
D(s)

(28)

The poles of feedback system are the roots of the polynomial

D(s) = DA (s) + KNA (s)

0
Real axis

Figure 19. A root locus plot produced using MATLAB. The poles of
A(s) are marked by xs and the zeros of A(s) are marked by os. As K
increases from zero to infinity, the poles of T(s) migrate from the poles
of A(s) to the zeros of A(s) along the paths indicated by solid lines.

pose that the forward and feedback blocks in Fig. 1 are described by
A(s) =

Frequently the performance of a feedback system is adjusted

by changing the value of a gain. For example, consider the
feedback system shown in Fig. 1 when

s2 2s
s(s 2)
= 3
and B(s) = K
(s + 1)(s + 2)(s + 3) s + 6s2 + 11s + 6

The root locus plot for this system is obtained using the
MATLAB (5,6) commands
num=([0 1 -2 0]);
den=([1 6 11 6]);
rlocus(num, den)

This root locus plot is shown in Fig. 19. After the root locus
has been plotted, the MATLAB command
rlocfind(num, den)

can be used to find the value of the gain K corresponding to

any point on the root locus. For example, when this command
is given and the cursor is placed on the point where the locus
crosses the positive imaginary axis, MATLAB indicates that

(29)

Suppose that the gain K can be adjusted to any value between

0 and . Consider the extreme values of K. When K 0,
D(s)  DA(s) so the roots of D(s) are the same as the roots of
DA(s). When K  , DA(s) is negligible compared to KNA(s).
Therefore D(s)  KNA(s) and the roots of D(s) are the same as
the roots of NA(s). Notice that the roots of DA(s) are the poles
of A(s) and the roots of NA(s) are the zeros of A(s). As K varies
from 0 and , the poles of T(s) start at the poles of A(s) and
migrate to the zeros of A(s). The root locus is a plot of the
paths that the poles of T(s) take as they move across the splane from the poles of A(s) to the zeros of A(s).
A set of rules for constructing root locus plots by hand are
available (1,4,7,13). Fortunately, computer software for constructing root locus plots is also available. For example, sup-

+
vi(t)

vo(t)

Figure 20. A single device is separated from the rest of the network.
The parameter associated with this device is called x. The transfer
function of the network will be a bilinear function of x.

CIRCUIT STABILITY

104

then the transfer function of this SallenKey filter is

K(1414s)
s2 + (4 K)(1414s) + 4 106
K(1414s)
= 2
(s + 5656s + 4 106 ) + K(1414s)

0.8

T (s) =

0.6
0.4
Imag axis

407

0.2

(32)

As expected, this transfer function is a bilinear function the

gain K. Comparing Eqs. (30) and (32) shows that E(s)  0,
F(s)  1414s, G(s)  s2  5656s  4
105, and H(s) 
1414s. The root locus describing the poles of the filter is
obtained using the MATLAB commands

0
0.2
0.4

G=([1
5656
H=([0 -1414
rlocus(H,G)

0.6
0.8
1
1

0.5

0
Real axis

0.5

1
104

Figure 21. This root locus plot shows that the poles of the Sallen
Key bandpass filter move into the right of the s-plane as the gain increases.

gain corresponding to the point 0.0046  j0.7214 is K 

5.2678. For gains larger than 5.2678, two poles of T(s) are in
the right half of the s-plane so the feedback system is unstable.
The bilinear theorem (12) can be used to make a connection between electric circuits and root locus plots. Consider
Fig. 20, where one device has been separated from the rest of
a linear circuit. The separated device could be a resistor, a
capacitor, an amplifier, or any two-terminal device (12). The
separated device has been labeled as x. For example, x could
be the resistance of a resistor, the capacitance of a capacitor,
or the gain of an amplifier. The bilinear theorem states that
the transfer function of the circuit will be of the form
T (s) =

E(s) + xF (s)
N(s)
Vo (s)
=
=
Vi (s)
G(s) + xH(s)
D(s)

(30)

where E(s), F(s), G(s), and H(s) are all polynomials in s. A

transfer function of this form is said to be a bilinear function
of the parameter x since both the numerator and denominator
polynomials are linear functions of the parameter x. The poles
of T(s) are the roots of the denominator polynomial
D(s) = G(s) + xH(s)

(31)

As x varies from 0 to , the poles of T(s) begin at the roots of

G(s) and migrate to the roots of H(s). The root locus can be
used to display the paths that the poles take as they move
from the roots of G(s) to the roots of H(s). Similarly, the root
locus can be used to display the paths that the zeros of T(s)
take as they migrate from the roots of E(s) to the roots of
F(s).
For example, consider the SallenKey bandpass filter
shown in Fig. 11. When
R1 = R2 = R3 = 7.07 k, C1 = C2 = 0.1 F,

and K = 1 +

R4
R5

4*10^6]);
0]);

Figure 21 shows the resulting root locus plot. The poles move
into the right half of the s-plane, and the filter becomes unstable when K  4.
BIBLIOGRAPHY
1. R. C. Dorf and R. H. Bishop, Modern Control Systems, 7th ed.,
Reading, MA: Addison-Wesley, 1995.
2. R. C. Dorf and J. A. Svoboda, Introduction to Electric Circuits,
New York: Wiley, 1996.
3. R. V. Churchill, J. W. Brown, and R. F. Verhey, Complex Variables and Applications, New York: McGraw-Hill, 1974.
4. S. M. Shinners, Modern Control System Theory and Design, New
York: Wiley, 1992.
5. R. D. Strum and D. E. Kirk, Contemporary Linear Systems using
MATLAB, Boston: PWS, 1994.
6. N. E. Leonard and W. S. Levine, Using MATLAB to Analyze and
Design Control Systems, Redwood City, CA: Benjamin Cummings, 1995.
7. K. Ogata, Modern Control Engineering, Englewood Cliffs, NJ:
Prentice Hall, 1970.
8. J. A. Svoboda and G. M. Wierzba, Using PSpice to determine the
relative stability of RC active filters, International Journal on
Electronics, 74 (4): 593604, 1993.
9. F. W. Stephenson, RC Active Filter Design Handbook, New York:
Wiley, 1985.
10. J. A. Svoboda, ELab, A circuit analysis program for engineering
education, Comput. Applications in Eng. Education, 5: 135149,
1997.
11. W.-K. Chen, Active Network and Feedback Amplifier Theory, New
York: McGraw-Hill, 1980.
12. K. Gehler, Theory of Tolerances, Budapest, Hungary: Akademiai
Kiado, 1971.
13. A. Budak, Passive and Active Network Synthesis, Prospect
Heights, IL: Waveland Press, 1991, Chap. 6.

Reading List
P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd ed., New York: Wiley, 1993, Chaps. 8 and 9.
A. Sedra and K. Smith, Microelectronic Circuits, 4th Ed., Oxford: Oxford University Press, 1998, Chap. 8.

JAMES A. SVOBODA
Clarkson University

420

CIRCUIT TUNING

CIRCUIT TUNING
Circuit tuning refers to the process of adjusting the values of
electronic components in a circuit to ensure that the fabricated or manufactured circuit performs to specifications. In
digital circuits, where signals are switched functions in the
time domain and correct operation depends largely on the active devices switching all the way between their ON and OFF
states, tuning in the sense discussed in this chapter is rarely
necessary. In analog continuous-time circuits, however, signals are continuous functions of time and frequency so that
circuit performance depends critically on the component values. Consequently, in all but the most undemanding applications with wide tolerances, correct circuit operation almost
always requires some form of tuning. Naturally, components
could be manufactured with very tight tolerances, but the resulting fabrication costs would become prohibitive. In practice, therefore, electronic components used in circuit design
are never or only rarely available as accurately as the nominal design requires, so we must assume that they are affected
by fabrication and manufacturing tolerances. Furthermore,
regardless of whether a circuit is assembled in discrete form
with discrete components on a printed circuit board (as a hybrid circuit), or in integrated form on an integrated circuit
chip, the circuit will be affected by parasitic components and
changing operating conditions, all of which contribute to inaccurate circuit performance. Consider, for example, the requirement of implementing as a hybrid circuit a time of 1 s
for a timer circuit via an RC time constant RC with an
accuracy of 0.1%. Assume that R and C are selected to have
the nominal values R 100 k and C 10 F, that inexpensive chip capacitors with 20% tolerances are used, and that
the desired fabrication process of thin-film resistors results in
components with 10% tolerances. The fabricated time constant can therefore be expected to lie in the range
0.68 s = 100 k(1 0.1)10 F(1 0.2) 1.32 s
In other words, the -error must be expected to be 32%,
which is far above the specified 0.1%. Tuning is clearly necessary. Because capacitors are difficult to adjust and accurate
capacitors are expensive, let us assume in this simple case
that the capacitor was measured with 0.05% accuracy as C
11.125 F (i.e., the measured error was 11.25%). We can
readily compute that the resistor should be adjusted
(trimmed) to the nominal value R /C 1 s/11.125 F
89.888 k within a tolerance of 45 to yield the correctly
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

CIRCUIT TUNING

implemented time constant of 1 s with 0.1% tolerances. Observe that tuning generally allows the designer to construct a
circuit with less expensive wide-tolerance parts because subsequent tuning of these or other components permits the errors to be corrected. Thus, C was fabricated with 20% tolerances but measured with a 0.05% error to permit the resistor
with fabrication tolerances of 10% to be trimmed to a 0.05%
accuracy. Note that implied in this process is the availability
of measuring instruments with the necessary accuracy.
Tuning has two main purposes. Its most important function is to correct errors in circuit performance caused by such
factors as fabrication tolerances such as in the preceding example. Second, it permits a circuits function or parameters,
such as the cut-off frequency of a given low-pass filter, to be
changed to different values to make the circuit more useful or
to be able to accommodate changing operating requirements.
But even the best fabrication technology together with tuning
will not normally result in a circuit operating with zero errors;
rather, the aim of tuning is to trim the values of one or more,
or in rare cases of all, components until the circuits response
is guaranteed to remain within a specified tolerance range
when the circuit is put into operation. Figure 1 illustrates the
idea for a low-pass filter. Examples are a gain error that is
specified to remain within 0.05 dB, the cut-off frequency f c
of a filter that must not deviate from the design value of, say,
f c 10 kHz by more than 85 Hz, or the gain of an amplifier
that must settle to, say, 1% of its final value within less than
1 s. As these examples indicate, in general, a circuits operation can be specified in the time domain, such as a transient
response with a certain highest permissible overshoot or a
maximal settling time, or in the frequency (s) domain through
an input-output transfer function with magnitude, phase, or
delay specifications and certain tolerances (see Fig. 1). This
article focuses on the tuning of filters, that is, of frequencyselective networks. Such circuits are continuous functions of
components, described by transfer functions in the s domain,
where tuning of design parameters (e.g., cut-off frequency,
bandwidth, quality factor, and gain), is particularly important
in practice. The concepts discussed in connection with filters
apply equally to other analog circuits. Obviously, in order to
tune (adjust) a circuit, that circuit must be tunable. That is,
its components must be capable of being varied in some man-

Gain

;;;;
;;;;
;;
QQ

;;;;
;;
QQ

Frequency

Figure 1. The shaded area in the gain vs. frequency plot shows the
operating region for a low-pass filter that must be expected based on
raw (untuned) fabrication tolerances; the dotted region is the acceptable tolerance range that must be maintained in operation after the
filter is tuned.

421

n1
C1

R2

R1

C2

V1

n2

A
+

V2

Figure 2. Active RC bandpass filter.

ner (manually or electronically) by an amount sufficient to

overcome the consequences of fabrication tolerances, parasitic
effects, or other such factors.
An example will help to illustrate the discussion and terminology. Consider the simple second-order active band-pass
circuit in Fig. 2. Its voltage transfer function, under the assumption of ideal operational amplifiers, can be derived to be

V2
b1 s
= 2
V1
s + a1 s + a0
1
s
R1C1


=
1
1
1
1
s2 +
+
s+
R2 C1 C2
R1 R2C1C2

T (s) =

(1)

We see that T(s) is a continuous function of the circuit components, as are all its coefficients that determine the circuits
behavior:
b1 =

1
C + C2
1
,a = 1
,a =
R1C1 1
R2C1C2 0
R1 R2C1C2

(2)

Just as in the earlier example of the RC time constant, the

coefficients will not be implemented precisely if the component values have fabrication tolerances. If these component
tolerances are too large, generally the coefficient errors will
become too large as well, and the circuit will not function
correctly. In that case, the circuit must be tuned. Furthermore, circuits are generally affected by parasitic components.
Parasitic components, or parasitics, are physical effects that
often can be modeled as real components affecting the circuits performance but that frequently are not specified with
sufficient accuracy and are not included in the nominal design. For instance, in the filter of Fig. 2, a parasitic capacitor
can be assumed to exist between any two nodes or between
any individual node and ground; also, real wires are not
ideal short circuit connections with zero resistance but are
resistive and, at high frequencies, even inductive. In the filter
of Fig. 2, a parasitic capacitor Cp between nodes n1 and n2
would let the resistor R2 look like the frequency-dependent
impedance Z2(s) R2 /(1 sCpR2). Similarly, real resistive
wires would place small resistors rw in series with C1 and C2
and would make these capacitors appear lossy. That is, the
capacitors Ci, i 1, 2, would present admittances of the form
Yi(s) sCi /(1 sCirw). Substituting Z2(s) and Yi(s) for R2 and
Ci, respectively, into Eq. (1) shows that, depending on the frequency range of interest and the element values, the presence
of these parasitics changes the coefficients of the transfer
function, maybe even its type, and consequently the circuits

422

CIRCUIT TUNING

performance. Similarly, when changes occur in environmental

operating conditions, such as bias voltages or temperature,
the performance of electronic devices is altered, and as a result the fabricated circuit may not perform as specified.
As discussed by Moschytz (1, Sec. 4.4, pp. 394425), and
Bowron and Stevenson (2, Sec. 9.5, pp. 247251), the operation of tuning can be classified into functional and deterministic tuning. In functional tuning, the designed circuit is assembled, and its performance is measured. By analyzing the
circuit, we can identify which component affects the performance parameter to be tuned. These predetermined components are then adjusted in situ (i.e., with the circuit in operation), until errors in performance parameters are reduced to
acceptable tolerances. The process is complicated by the fact
that tuning is most often interactive, meaning that adjusting
a given component will vary several circuit parameters; thus
iterative routines are normally called for. As an example, consider again the active RC filter in Fig. 2. If its bandpass transfer function, Eq. (1), is expressed in the measurable terms of
center frequency 0, the pole quality factor Q 0 /, the parameter that determines the filters bandwidth , and midband (at s j0) gain K as

1
s
R1C1


T (s) =
1
1
1
1
s+
s2 +
+
R2 C1 C2
R1 R2C1C2
0
K s
Q
=
0
2
+ 02
s +s
Q

(3)

SENSITIVITY

These parameters are expressed in terms of the circuit components and we arrive at the more meaningful and useful design equations

0 =
,Q =
R1 R2C1C2

R
R2 C1C2
C2
,K = 2
R1 C1 + C2
R1 C1 + C2

(4)

instead of Eq. (2). It is clear that varying any of the passive

components will change all three filter parameters, so that
expensive and time-consuming iterative tuning is required.
However, functional tuning has the advantage that the effects of all component and layout parasitics, losses, loading,
and other hard-to-model or hard-to-predict factors are accounted for because the performance of the complete circuit
is measured under actual operating conditions. In general,
more accurate results are obtained by basing functional
tuning on measurements of phase rather than of magnitude
because phase tends to be more sensitive to component
errors.
Deterministic tuning refers to calculating the needed value
of a component from circuit equations and then adjusting the
component to that value. We determined the resistor R
/C 89.888 k to set a time constant of 1 s at the beginning
of this article in this manner. Similarly, from Eq. (4) we can
derive the three equations in the four unknowns R1, R2, C1,
and C2
Q
R2 =
0

1
1
+
C1 C2


, R1 =

1
1 Q
,C =
R2 02C1C2 1
KR1 0

with C2 a free parameter. That there are more circuit components than parameters is normal, so the additional free elements may be used at will, for example, to achieve practical
element values or element-value spreads (i.e., the difference
between the maximum and minimum of a component type,
such as Rmax Rmin). Technology or cost considerations may
place further constraints on tuning by removing some components from the list of tunable ones. Thus, in hybrid circuits
with thin- or thick-film technology as in the preceding example, the capacitors will likely be fixed; only the two resistors
will be determined as in Eq. (5) from the prescribed circuit
parameters 0 and Q and the selected and measured capacitor
values. This choice leaves the midband gain fixed at the
value K Q/(0C1R1). Precise deterministic tuning requires
careful measurements and accurate models and design equations that, in contrast to the idealized expressions in Eq. (5),
describe circuit behavior along with loss, parasitic, and environmental effects. As we saw in Eq. (5), the equations that
must be solved are highly nonlinear and tend to be very complex, particularly if parasitic components also are involved.
Computer tools are almost always used to find the solution.
Typically, automatic laser trimming is employed to tune the
resistors to the desired tolerances (e.g., 0.1%). A second tuning iteration using functional tuning may be required because
the assembled circuit under power may still not meet the
specifications as a result of further parasitic or loading effects
that could not be accounted for in the initial deterministic
tuning step.

(5)

We mentioned earlier that a filter parameter P depends on

the values ki of the components used to manufacture a circuit, P P(ki), and that real circuit components or parts can
be realized only to within some tolerances ki. That is, the
values of the parts used to assemble circuits are ki ki.
Clearly, the designer needs to know how much these tolerances will affect the circuit and whether the resulting errors
can be corrected by adjusting (tuning) the circuit after fabrication. Obviously, the parameter to be tuned and must depend on the component to be varied. For example, Q in Eq.
(4) is a function of the components R1, R2, C1, and C2, any one
of which can be adjusted to correct fabrication errors in Q. In
general, the questions of how large the adjustment of a
component has to be, whether it should be increased or
decreased, and what the best tuning sequence is are answered by considering the parameters sensitivity to component tolerances. How sensitive P is to the component-value
tolerances, that is how large the deviation P of the parameter in question is, is computed for small changes via the
derivative of P(ki) with respect to ki, P/ki, at the nominal
value ki:
P =

P(ki )
ki
ki

(6)

Typically, designers are less interested in the absolute tolerances than in the relative ones, that is,
k P ki
P
ki
= i
= SPk
i k
P
P ki ki
i

(7)

CIRCUIT TUNING

SPki is the sensitivity, defined as the relative change of the

parameter divided by the relative change of the component,
SPk =
i

P/P
ki /ki

(8)

A detailed discussion of sensitivity issues can be found in

many text books [see Schaumann, Ghausi, and Laker (3),
Chap. 3, pp. 124196]. For example, the sensitivity of 0 in
Eq. (4) to changes in R1 is readily computed to be

SR0 =
1

R1 0
0 R1

R1
=
1/(R1 R2C1C2 )1/2

R2C1C2
1
1
=

2 (R1 R2C1C2 )3/2

2

(9)

SR01 0.5 means that the percentage error in the parameter

0 is one-half the size of the percentage error of R1 and opposite in sign (i.e., if R1 increases, 0 decreases). A large number
of useful sensitivity relations that make sensitivity calculations easy can be derived [see, for example, Moschytz (1), Sec.
1.6, pp. 103105, 1.5, pp. 71102, and 4.3, pp. 371393, or
Schaumann, Ghausi, and Laker (3), Chap. 3, pp. 124196].
Of particular use for our discussion of tuning are

SkP(k

n)

= nSP(k)
, SP(k)
= SP(k)
,
k
k
k

SP(1/k)
= SP(k)
, and SkP(
k
k

k)

1 P(k)
S
2 k

(10)

where is a constant, independent of k. The last two of these

equations are special cases of the first one for n 1 and
n 1/2, respectively. The last equation generalizes the result
obtained in Eq. (9). Equations (7) and (8) indicate that, for
small differential changes, the parameter deviation caused by
a component error and, conversely from the point of view of
tuning, the change in component value necessary to achieve
a desired change in parameter can be computed if the sensitivity is known.
In Eqs. (6) and (7) we purposely used partial derivatives,
P/ki, to indicate that circuit parameters normally depend
on more than one component [see Eq. (4)], all of which affect
the accuracy of the parameter. To get a more complete picture
of the combined effect of the tolerances and to gain insight
into the operation of tuning involving several parameters, total derivatives need to be computed. Assuming P depends on
n components, we find [see Schaumann, Ghausi, and Laker
(3), Chap. 3, pp. 124196]

0
R 0 R1
R 0 R2
C 0 C1 C2 0 C2
= 1
+ 2
+ 1
+
0
0 R1 R1
0 R2 R2
0 C1 C1
0 C2 C2
R
R
C
C

1
2
1
2
= SR0
+ SR0
+ SC p
+ SC0
1 R1
2 R2
1 C1
2 C2
1 R1
1 R2
1 C1
1 C2
=

2 R1
2 R2
2 C1
2 C2


1 R1
R2
C1
C2
=
+
+
+
2 R1
R2
C1
C2
(12)
The last expression gives insight into whether and how 0 can
be tuned. Because the effects of the errors are additive, tuning just one component, say R1, will suffice for given tolerances of R2, C1, and C2 if R1 can be large enough. If we have
measured the R2 errors at 12%, and those of C1 and C2 at
15% and 10%, respectively, Eq. (12) results in


1 R1
0
=
0.12 + 0.15 + 0.10
0
2 R1
(13)


R1
+ 0.13
= 0.5
R1
indicating that R1 must be decreased by 13% to yield, within
the linearized approximations made, 0 0. Inserting components with these tolerances into Eq. (4) for 0 confirms the
result obtained.
To expand these results and gain further insight into the
effects of tolerances, as well as beneficial tuning strategies
and their constraints, we remember that a transfer function
generally depends on more than one parameter. Returning to
the example of Fig. 2 described by the function T(s) in Eq. (3)
with the three parameters 0, Q, and K given in Eq. (4) and
applying Eq. (11) leads to

0
R1
R2
C1
C2
= SR0
+ SR0
+ SC0
+ SC0
0
1 R1
2 R2
1 C1
2 C2

(14a)

R1
R2
C1
C2
Q
= SQ
+ SQ
+ SCQ
+ SCQ
R1 R
R2 R
1
2
Q
C
C2
1
2
1

(14b)

K
R1
R2
C1
C2
= SK
+ SK
+ SCK
+ SCK
R1
R2
1 C
2 C
K
R1
R2
1
2

(14c)

These equations can be expressed in matrix form as follows:

(11)

indicating that the sum of all relative component tolerances,

weighted by their sensitivities, contributes to the parameter

R1
R
1

0
SC R2

R2
Q

SC

2
C1

K
SC C1
2

C2

0
0 S 0

R1

Q

SQ
R
Q =

SK
K
R1
K

that is

P
k P k1
kn P kn
= 1
+ +
P
P k1 k1
P kn kn
n

k1
kn
ki
= SPk
+ + SPkn
=
SPk
1 k
i k
k
n
1
i
i=1

error. To illustrate the calculations, let us apply Eq. (11) to

0 in Eq. (4). Using Eqs. (9) and (10), the result is

P
P
P
P =
k1 +
k2 + +
kn
k1
k2
kn

423

SR0

SC0

SQ
R

SCQ

SK
R

SCK

1
1

(15)

C2
The sensitivity matrix in Eq. (15) [see Moschytz (1), Sec. 4.3,
pp. 376393, or Schaumann, Ghausi, and Laker (3), Sec. 3.3,
pp. 161188], a 3 4 matrix in this case, shows how the
tolerances of all the filter parameters depend on the compo-

424

CIRCUIT TUNING

nent tolerances. We see that adjusting any one of the circuit

components will vary all filter parameters as long as all the
sensitivities are nonzero, which is indeed the case for the circuit in Fig. 2. Thus, noninteractive tuning is not possible. To
illustrate the form of the sensitivity matrix, we calculate for
the circuit in Fig. 2
R


0

Q

K
K

0.5

0.5

=

0.5
0.5
1

0.5
1 C1 C2

2 C1 + C2

C1
C1 + C2

R
1

0.5
R2

1 C1 C2
R
2
2 C1 + C2

C1

C1
C
1
C1 + C2

C
C2

SQ
= SQ
= SQ
= 0.5 and
R
R
R
1

(16)

SCQ
1

SCQ
2

Note that the first line of Eq. (16) is equal to the last part of
Eq. (12).
The tuning situation is simpler if the matrix elements
above the main diagonal are zero as was assumed for an arbitrary different circuit in Eq. (17a):

R1

0
R1

0 R
0 S 0
0
0
S
2

R1
C2

Q
R2
Q
Q
Q

S
S
0
S
R
R2
C2
Q
C1

SK
SK
SCK
SCK
C1
R1
R2
K
1
2

C2
K
C
R 2
(17a)
1

0
0
0 R1
SC
SR0
2

Q
Q C2
R2 +
S
0
= S Q

SC
R1
R2

R2

2 C2

SK
SCK
SCK
SK
C
R1
R2
1
2
1
C1
Here the sensitivities to C2 are irrelevant because C2 is a free
parameter and is assumed fixed so that the effects of C2 tolerances can be corrected by varying the remaining elements.
We see then that first 0 can be tuned by R1, next Q is tuned
by R2 without disturbing 0 because SR02 is zero, and finally K
is tuned by C1 without disturbing the previous two adjustments. Thus a sensitivity matrix of the structure indicated in
Eq. (17a) with elements above the main diagonal equal to zero
permits sequential noninteractive tuning if the tuning order
is chosen correctly. Completely noninteractive tuning without
regard to the tuning order requires all elements in the sensitivity matrix off the main diagnonal to be zero as indicated
for another circuit in Eq. (17b):

R
0
1

0
0
0
R1
0
0
SR
SC

1
Q

R
C

Q
2
2

S Q

0
S
0

R2
Q C2 C =
(17b)
R

2
2
K
K

SC
0
0
SC
K
2
1
C
1

C1

As can be verified readily, each component affects only one

circuit parameter. Again, sensitivities to C2 are irrelevant because C2 is fixed, and the effects of its tolerances can be corrected by the remaining components.
An important observation on the effects of tolerances on
circuit parameters and the resultant need for tuning can
be made from Eq. (16). We see that the sensitivities of the
dimensionless parameters (parameters with no physical
unit) Q and K to the two resistors and similarly to the two
capacitors are equal in magnitude but opposite in sign.
Because dimensionless parameters are determined by ratios
of like components [see Eq. (4)], we obtain from Eq. (4)
with Eq. (10)

= SCQ =

1 C1 C2
2 C1 + C2

Thus, the tolerances of Q are


R2
C2
Q
Q R1
Q C1
= SR

+ SC

Q
R1
R2
C1
C2

(18)

(19)

with analogous expressions obtained for the gain K [see the

last line of Eq. (16)]. Thus, if the technology chosen to implement the filter permits ratios of resistors and capacitors to be
realized accurately (i.e., if all resistors have equal tolerances,
as do all capacitors), tuning of dimensionless parameters will
generally not be necessary. A prime example is integrated circuit technology, where absolute value tolerances of resistors
and capacitors may reach 20 to 50%, but ratios, depending
mainly on processing mask dimensions, are readily implemented with tolerances of a fraction of 1%. As an example,
assume that the circuit in Fig. 2 was designed, as is often the
case, with two identical capacitors C1 C2 C with tolerances of 20% and that R1 and R2 have tolerances of 10% each,
that is,

C1 = C2 = Cn + C = Cn (1 + 0.2),
R1 = R1n + R1 = R1n (1 + 0.1), and

(20)

R2 = R2n (1 + 0.1)
where the subscript n stands for the nominal values. From
Eq. (19), we find
Q = [SQ
(0.1 0.1) + SCQ (0.2 0.2)]Q = 0
R
That is, the quality factor Q, depending only on ratios of like
components, is basically unaffected because all like components have equal fabrication tolerances. This result can be
confirmed directly from Eq. (4) where, for equal capacitors,


1 R2
1 R2n (1 + 0.1)
Qn
Q=
=
(21)
2 R1
2 R1n (1 + 0.1)
Naturally, if R1 and R2 are selected from different manufacturing lots, or if R1 and R2 are from physically different fabrication processes (such as a carbon and a metal-film resistor),
tolerances cannot be assumed to be equal, Q errors are not
zero, and tuning will be required.
The situation is quite different for any dimensioned circuit
parameter, that is, a parameter with a physical unit (e.g., a

CIRCUIT TUNING

frequency or time constant, or a voltage or a current). Such

parameters are determined by absolute values of components,
as seen for 0 in Eq. (4). Absolute values, depending on physical process parameters e.g., resistivity, permittivity, or diffusion depth, are very difficult to control and will usually suffer
from large process variations. Thus, for the component tolerances in Eq. (20), sensitivity calculations predict from Eqs.
(10) and (12) the realized center frequency error


1 R1
R2
C1
C2
+
+
+
0
2 R1
R2
C1
C2
1
= (0.1 + 0.1 + 0.2 + 0.2) = 0.30
2

0

(22a)

that is, all individual component tolerances add to a 30%

frequency error. Again, the validity of this sensitivity result
can be confirmed directly from Eq. (4):

0 =

1
R1 R2C1C2

C R1 R2
1

Cn (1 + 0.2) R1n R2n (1 + 0.1 + 0.1 + 0.01)

0n
0n

(1 + 0.2)(1 + 0.1)
(1 + .02) 1 + 0.2
0n
0n (1 0.24)
=
(1 + 0.32)
=

(22b)

The difference between the exact result in Eq. (22b) and

the one obtained via the sensitivity approach in Eq. (22a)
arises because the latter assumes incremental component
changes whereas the former assumed the relatively large
changes of 10 and 20%. The center frequency 0 is approximately 2530% smaller than specified and must be corrected
by tuning. This can be accomplished, for example, by trimming the two resistors to be 27% smaller than their fabricated
values, that is,

R1 = R1n (1 + 0.1)(1 0.27) R1n (1 0.2),

R2 R2n (1 0.2)
so that sensitivity calculations yield
0 0.5(0.2 0.2 + 0.2 + 0.2) = 0

TUNING DISCRETE CIRCUITS

Whether implemented on a printed circuit board, with chip
and thin- or thick-film components in hybrid form, by use of
wire-wrapping, or in any other technology, an advantage of
discrete circuits for the purpose of tuning is that circuit elements are accessible individually before or after assembly for
deterministic or functional adjusting. Thus, after a circuit is
assembled and found not to meet the design specifications,
the circuit components (most commonly the resistors or inductors), can be varied until the performance is as required. All
the previous general discussion applies to the rest of the article so we shall present only those special techniques and considerations that have been found particularly useful or important for passive and active filters.
Passive Filters
Discrete passive filters are almost always implemented as
lossless ladder circuits, that is, the components are inductors
L and capacitors C as is illustrated in the typical circuit in
Fig. 3. These LC filters are designed such that the maximum
signal power is transmitted from a resistive source to a resistive load in the frequency range of interest; a brief treatment can be found in Schaumann, Ghausi, and Laker (3),
Chap. 2, pp. 71123. As pointed out in our earlier discussion,
accurate filter behavior depends on precise element values so
that it is normally necessary to trim components. This tuning
is almost always accomplished via variable inductors whose
values are changed by screwing a ferrite slug (the trimmer)
into or out of the magnetic core of the inductive windings.
Variable discrete capacitors are hard to construct, expensive,
and rarely used.
LC filters have the advantage of very low sensitivities to
all their elements [see Schaumann, Ghausi, and Laker (3),
Chaps. 2 and 3, pp. 71196], which makes it possible to assemble the filter using less expensive wide-tolerance components. This property is further enhanced by the fact that lossless ladders are very easy to tune so that large tolerances
of one component can be compensated by accurately tuning
another. For example, the resonant frequency f 0 1/ LC of
an LC resonance circuit has 15% tolerances if both L and C
have 15% tolerances; if then L is trimmed to 0.5% of its
correct value for the existing capacitor (with 15% tolerances), f 0 is accurate to within 0.25% without requiring any
narrower manufacturing tolerances. Without tuning, a 0.25%
f 0 error would require the same narrow 0.25% tolerance in

More exact deterministic tuning requires the resistors to be

trimmed to 24.2% smaller than the fabricated value as shown
in Eq. (23):

0n
1
=
0n

Cn (1 + 0.2) R1n R2n (1 + 0.1)(1 ) 1.32(1 )

(23)

C1
R1

C2

L1

Vi

L2

C3

L3
Vo

n2

where is the trimming change to be applied to the resistors

as fabricated. Equation (23) results in 0.242. Of course,
0 tuning could have been accomplished by adjusting only one
of the resistors by a larger amount; we trimmed both resistors
by equal amounts to maintain the value of their ratio that
determines Q according to Eq. (21), thereby avoiding the need
to retune Q.

425

A
C4

C5

R2

Figure 3. Sixth-order LC low-pass filter. The filter is to realize a

maximally flat passband with a 2 dB bandwidth of f c 6 kHz, minimum stopband attenuation s 57.5 dB with transmission zeros at
12 and 24 kHz. The nominal components are listed in Table 1. Note
that at dc the filter has 20 log[R2 /(R1 R2)] 6.02 dB attenuation.

426

CIRCUIT TUNING

Table 1. LC Low-pass Filter (elements in mH, nF, and k)

Components
Nominal values
Performance
15% tolerance
values
Performance
untuned
Tuned values
Performance
tuned

L1

C1

L2

C2

L3

C3

C4

C5

R1

R2

27.00 6.490 46.65 0.943 12.67 6.977 45.55 33.90 1.00 1.00
fc 6.0 kHz @ p 8.03 dB; fz1 12.0 kHz, fz2 24.0 kHz, s 57.5 dB
31

7.5

52

1.1

14

51

38

1.05

1.05

fc 5.36 kHz @ p 8.01 dB; fz1 10.3 kHz, fz2 20.7 kHz, s 56.7 dB
23.5
7.5
40
1.1
14
8
51
38
1.05 1.05
fc 6.07 kHz @ p 8.03 dB; fz1 12.0 kHz, fz2 24.0 kHz, s 57.8 dB

both components, which is likely more expensive than a simple tuning step.
It is well known that lossless ladders can be tuned quite
accurately simply by adjusting the components to realize the
prescribed transmission zeros [see Heinlein and Holmes (4),
Sec. 12.3, pp. 591604, and Christian (5), Chap. 8, pp. 167
176]. Transmission zeros, frequencies where the attenuation
is infinite, usually depend on only two elements, a capacitor
and an inductor in a parallel resonant ciruit (see Fig. 3) with
the parallel tank circuits L1, C1 and L2, C2 in the series
branches of the filter, or alternatively with series LC resonance circuits in the shunt branches. The resonant frequencies f zi 1/ LiCi, i 1, 2, of the LC tank circuits are not
affected by other elements in the filter, so that tuning is
largely noninteractive. As mentioned, the effect of the tolerances of one component, say C, are corrected by tuning L. It
is performed by adjusting the inductors for maximum attenuation at the readily identified frequencies of zero transmission
while observing the response of the complete manufactured
filter on a network analyzer. Tuning accurancies of the transmission zeros of 0.05% or less should be aimed at. Such tuning of the transmission zeros is almost always sufficient even
if the circuit elements have fairly large tolerances [see Heinlein and Holmes (4), Sec. 12.3, pp. 594604]. If even better
accuracy is needed, adjustments of those inductors that do
not cause finite transmission zeros, such as L3 in Fig. 3, may
need to be performed [see Christian (5), Chap. 8, pp. 167
176]. For instance, consider the filter in Fig. 3 realized with
unreasonably large tolerances of 15%, using the components
shown in Table 1. This places the two resonant frequencies at
10.3 and 20.7 kHz, with the minimum stopband attenuation
equal to only 56.7 dB; the 2 dB passband corner is reduced to
5.36 kHz. If we next tune the transmission zero frequencies
to 12 and 24 kHz by adjusting only the inductors L1 and L2 to
23.5 and 40 mH, respectively, the minimum stopband attenuation is increased to 57.8 dB, and the 2 dB bandwidth of the
passband is measured as f c 6.07 kHz (refer to Table 1).
We still note that when functional tuning is performed, the
filter must be operated with the correct terminations for
which it was designed [see Christian (5), Sec. 8.2, pp. 168
173]. Large performance errors, not just at dc or low frequencies, will result if the nominal terminations are severely altered. For example, an LC filter designed for 600
terminations cannot be correctly tuned by connecting it directly without terminations to a high-frequency network analyzer whose input and source impedances are 50 . Also, if
maintaining an accurate narrow passband ripple is impor-

tant, the tolerances of the untuned capacitors must not be

too large. Finally, we observe that the tuning properties of
passive LC ladders translate directly to active simulations of
these filters via transconductance-C and gyrator-C circuits,
which are widely used in high-frequency integrated circuits
for communications (see the following discussion).
Active Filters
Several differences must be kept in mind when tuning active
filters as compared to passive lossless filters, particularly to
ladders:
1. Active filters are almost always more sensitive to component tolerances than LC ladders. Consequently, tuning is always required in practice.
2. Tuning in active filters is almost always interactive;
that is, a filter parameter depends on many or all circuit
components as discussed in connection with the circuit
in Fig. 2 and the sensitivity discussion related to Eqs.
(15) and (16). Consequently, tuning active filters usually requires computer aids to solve the complicated
nonlinear tuning equations [see, for example, the relatively simple case in Eq. (4)].
3. The performance of the active devices, such as operational amplifiers (op amps), and their often large tolerances almost always strongly affects the filter performance and must be accounted for in design and in
tuning. Because active-device behavior is often hard to
model or account for, functional tuning of the fabricated
circuit is normally the only method to ensure accurate
circuit performance.
In discrete active filters constructed with resistors, capacitors, and operational amplifiers on a circuit board or in thinor thick-film form, tuning is almost always performed by varying the resistors. Variable resistors, potentiometers, are
available in many forms, technologies, and sizes required to
make the necessary adjustments.
Second-Order Filters. The main building blocks of active
filters are second-order sections, such as the bandpass circuit
in Fig. 2. Many of the tuning strategies and concepts were
presented earlier in connection with that circuit and the discussion of sensitivity. An important consideration when tuning an active filter is its dependence on the active devices as
mentioned previously in point 3. To illustrate the problem,

CIRCUIT TUNING

consider again the bandpass filter in Fig. 2. The transfer function T(s) in Eq. (1) is independent of the frequency-dependent
gain A(s) of the op amp only because the analysis assumed
that the amplifier is ideal, that is, it has constant and very
large (ideally infinite) gain, A . In practice, T(s) is also a
function of A(s) as a more careful analysis shows:

V
T (s) = 2
V1
A(s)
1
s
R1C1 1 + A(s)


=
1
1
1
1
1
s+
s2 +
+
+
R2 C1 C2 R1C1 [1 +A(s)]
R1 R2C1C2
(24)
Evidently, for A , Eq. (24) reduces to Eq. (1), but finite
and frequency-dependent gain can cause severe changes in
T(s) in all but the lowest-frequency applications. Consider the
often-used integrator model for the operational amplifier,
A(s) t /s, where t is the unity gain frequency (or the gainbandwidth product) of the op amp with the typical value
t 2 f t 2 1.5 MHz. Using this simple model, which
is valid for frequencies up to about 10 to 20% of f t, and assuming t , the transfer function becomes

V
T (s) = 2
V1

V1

(25)
To get an estimate of the resulting error, let the circuit be
designed with C1 C2 C 10 nF, R1 66.32 and R2
9.55 k to realize the nominal parameters f 0 20 kHz, Q
6, and K 72. Simulation (or measurement with a very fast
op amp) shows that the resulting circuit performance is as
desired. However, if the filter is implemented with a 741-type
op amp with f t 1.5 MHz, the measured performance indicates f 0 18.5 kHz, Q 6.85, and K 76.75. Because of the
complicated expressions involving a real op amp, it is appropriate to use functional tuning with the help of a network
analyzer. Keeping C constant, the resulting resistor values,
R1 68.5 and R2 8.00 k, lead to f 0 20 kHz and Q
6.06. The midband gain for these element values equals K
62.4 (remember from the earlier discussion that K for the
circuit in Fig. 2 cannot be separately adjusted if the capacitors are predetermined).
High-Order Filters. The two main methods for realizing active filters of order greater than two are active simulations
of lossless ladders and cascading second-order sections. We
mentioned in connection with the earlier discussion of LC ladders that tuning of active ladder simulations is completely
analogous to that of the passive LC ladder: the electronic circuits that simulate the inductors are adjusted until the transmission zeros are implemented correctly. It remains to discuss tuning for the most frequently used method of realizing
high-order filters, the cascading of first- and second-order sections. Apart from good sensitivity properties, relatively easy

T2

1, Q1, K1

2, Q2, K2

Tn

...

n, Qn, Kn

Figure 4. Cascade realization of 2nth-order filter. The n second-order sections do not interact with each other and can be tuned independently, that is, each section Ti can be tuned to its nominal values
i, Qi, and Hi, i 1, 2, . . ., n, without being affected by the other sections.

tuning is a main advantage of cascade implementations because each section performs in isolation from the others so
that it can be tuned without interactions from the rest of the
circuit. Remember, though, that each section by itself may
require interactive tuning. Figure 4 shows the circuit structure where each of the blocks is a second-order section such
as the ones in Figs. 2 and 5. If the total filter order is odd,
one of the sections is, of course, of first order.
To illustrate this point, assume a fourth-order Chebyshev
low-pass filter is to be realized with a 1 dB ripple passband
in 0 f 28 kHz with passband gain equal to H 20 dB. The
transfer function is found to be

T (s) = T1 (s) T2 (s)

=

1
s
C1 R1


1
1
1
1
1
s2 1 +
+
+
s+
t C1 R1
R2 C1 C2
R1 R2C1C2

T1

427

s2

1.6602
1.6602
2
2
+ 0.2790s + 0.9870 s + 0.6740s + 0.27902

(26)

with 0 2 28,000 s1 175.93 103 s1 [see Schaumann,

Ghausi, and Laker (3), Sec. 1.6, pp. 3664]. Let the function
be realized by two sections of the form shown in Figure 5.
Assuming that the op amps are ideal, the transfer function of
the low-pass section is readily derived as

K02
V2
=

V1
s2 + s 0 + 02
Q
1
C1 R1C2 R2


=
1
1
1
1 2
+
s2 + s
+
C1 R1
C2 R2
C1 R1C2 R2
1 2

(27)

If the op amp gain is modeled as A(s) t /s, i is to be replaced by

i

V1

i
i

1 + i /A(s)
1 + si /t

R1
R2

C1

V2

+
+

R0( 11)

R0( 21)

C2
R0

(28)

R0

Figure 5. Two-amplifier active low-pass filter.

428

CIRCUIT TUNING

We observe again that the circuit parameters 0, Q, and gain

K are functions of all the circuit elements so that design and
tuning of each section will require iterative procedures, although section 1 is independent of section 2 as just discussed.
Because there are six components (R1, R2, C1, C2, 1, and
2) and only three parameters, some simplifying design
choices can be made. Choosing C1 C2 C, R1 R, and
R2 k2R (and assuming ideal op amps), Eq. (27) leads to in
the expressions

0 =

1
,Q =
kRC

1
, and K = 1 2
1
k + (1 K)
k

(29)

The circuit is designed by first computing k from the given

values Q and K; next we choose a suitable capacitor value C
and calculate R 1/(k0C). Finally, we determine the feedback resistors on the two op amps. Because only the product 12 is relevant, we choose 12 2 K (i.e.,
K 1.66 1.288). Working through the design equations
and choosing all capacitors equal to C 150 pF (standard 5%
values) and R0 10 k, results in ( 1)R0 2.87 k for
both sections: k 0.965, R1 40.2 k, R2 36.5 k for section 1 and k 1.671, R1 42.2 k, R2 120.1 k for section
2. All resistors have standard 1% tolerance values. Building
the circuit with 741-type op amps with f t 1.5 MHz results
in a ripple width of almost 3 dB, the reduced cut-off frequency
of 27.2 kHz, and noticeable peaking at the band-edge. Thus,
tuning is required. The errors can be attributed largely to the
5% capacitor errors and the transfer function changes as a
result of the finite f t in Eq. (28).
To accomplish tuning in this case, deterministic tuning
may be employed if careful modeling of the op amp behavior,
using Eq. (28), and of parasitic effects is used and if the untuned components (the capacitors) are measured carefully
and accurately. Because of the many interacting effects in the
second-order sections, using a computer program to solve the
coupled nonlinear equations is unavoidable, and the resistors
are trimmed to their computed values. Functional tuning in
this case may be more convenient, as well as more reliable in
practice. For this purpose, the circuit is analyzed, and sensitivities are computed to help understand which components
affect the circuit parameters most strongly. Because the sections do not interact, the high-order circuit is separated into
its sections, and each sections functional performance is measured and adjusted on a network analyzer. After the performance of all second-order blocks is found to lie within the
specified tolerances, the sections are reconnected in cascade.
TUNING INTEGRATED CIRCUITS
With the increasing demand for fully integrated microelectronic systems, naturally, analog circuits will have to be
placed on an integrated circuit (IC) along with digital ones.
Of considerable interest are communication circuits where
bandwidths may reach many megahertz. Numerous applications call for on-chip high-frequency analog filters. Their frequency parameters, which in discrete active filters are set by
RC time constants, are in integrated filters most often designed with voltage-to-current converters (transconductors),
Io gmVi, and capacitors (i.e., as 1/ gm /C). As discussed
earlier, filter performance must be tuned regardless of the im-

plementation method because fabrication tolerances and parasitic effects are generally too large for filters to work correctly without adjustment. Understandably, tuning in the
traditional sense is impossible when the complete circuit is
integrated on an IC because individual components are not
accessible and cannot be varied. To handle this problem, several techniques have been developed. They permit tuning the
circuits electronically by varying the bias voltages VB or bias
currents IB of the active electronic components (transconductors or amplifiers). In the usual approach, the performance of
the fabricated circuit is compared to a suitably chosen accurate reference, such as an external precision resistor Re to set
the value of an electronic on-chip transconductance to gm
1/Re, or to a reference frequency r to set the time constant
to C/gm 1/r. This approach is indeed used in practice,
where often the external parameters, Re or e, are adjusted
manually to the required tolerances. Tuning can be handled
by connecting the circuit to be tuned into an on-chip control
loop, which automatically adjusts bias voltages or currents
until the errors are reduced to zero or an acceptable level [see
Schaumann, Ghausi, and Laker (3), Sec. 7.3, pp. 418446,
and Johns and Martin (6), Sec. 15.7, pp. 626635]. [A particularly useful reference is Tsividis and Voorman (7); it contains
papers on all aspects of integrated filters, including tuning.]
Naturally, this process requires that the circuit is designed to
be tunable, that is, that the components are variable over a
range sufficiently wide to permit errors caused by fabrication
tolerances or temperature drifts to be recovered. We also
must pay attention to keeping the tuning circuitry relatively
simple because chip area and power consumption are at a premium. Although digital tuning schemes are conceptually attractive, analog methods are often preferred. The reason is
the need to minimize or eliminate generating digital (switching) noise, which can enter the sensitive analog signal path
through parasitic capacitive coupling or through the substrate, causing the dynamic range or the signal-to-noise ratio
to deteriorate.
Automatic Tuning
Let us illustrate the concepts and techniques with a simple
second-order example. Higher-order filters are treated in an
entirely analogous fashion; the principles do not change. Consider the gm C filter in Fig. 6, which realizes the transfer
function


g
g
g g
s2 + s m1 m2 + m0 m2
V0
C1
C2
C1C2
T (s) =
=
(30)
gm1
gm1 gm2
V1
2
s +s
+
C1
C1C2
with pole frequency and pole Q equal to


0 =

gm1 gm2
C
,Q = 0 1 =
C1C2
gm1

C1 /C2
gm1 /gm2

(31)

Comparing Eq. (31) to Eq. (2) indicates that the filter parameters for this technology are determined in fundamentally the
same way as for discrete active circuits: the frequency is determined by time constants (Ci /gmi) and the quality factor, by
ratios of like components. Analogous statements are true for
the numerator coefficients of T(s). We can conclude then that,

CIRCUIT TUNING

in principle, tuning can proceed in a manner quite similar to

the one discussed in the beginning of this article if we can
just develop a procedure for varying the on-chip components.
To gain an understanding of what needs to be tuned in an
integrated filter, let us introduce a more convenient notation
that uses the ratios of the components to some suitably chosen unit values gm and C,
gmi

gm
= gi gm , Ci = ciC, i = 1, 2, and u =
C

(32)


g
g
g g
s2 + s 1 2 u + 0 2 u2
V
c1
c2
c1 c2
T (s) = 0 =
g1
g1 g2 2
V1
2
s + s u +

c1
c1 c2 u

V2

gm0
+

C1

(1 )C1

gm2

gm1
+

+
+

gmc

VC

gm

PD

C
VB
To the main filters
transconductors

Ic

Figure 7. Automatic control loop to set u gm /C via an applied reference signal VR with frequency R. The capacitor voltage equals
VC VR(gm /jRC), which makes the control current Ic gmcVR(1
gm /jRC). The operation is explained in the text.

(33)

Casting the transfer function in the form shown in Eq. (33)

makes clear that the coefficient of si is proportional to uni,
where n is the order of the filter, n 2 in Eq. (33); the constants of proportionality are determined by ratios of like components, which are very accurately designable with IC technology. The same is true for filters of arbitrary order. For
example, the pole frequency for the circuit in Fig. 6 is determined as u times a designable quantity, 0 ug1 g2 /(c1c2).
We may conclude therefore that it is only necessary to tune
u gm /C, which, as stated earlier, as a ratio of two electrically dissimilar components will have large fabrication tolerances. In addition, the electronic circuit that implements the
transconductance gm depends on temperature, bias, and other
conditions, so that u can be expected to drift during operation. It can be seen from Eq. (33) that u simply scales the
frequency, that is, the only effect of varying u is a shift of
the filters transfer function along the frequency axis.
We stated earlier that tuning a time constant, or, in the
present case, the frequency parameter u, is accomplished by
equating it via a control loop to an external reference, in this
case a reference frequency R such as a clock frequency. Con-

PD

VR

Cc

where u is a unit frequency parameter and gi and ci are the

dimensionless component ratios. With this notation, Eq. (30)
becomes

V1

429

gm3
+

(1 )C2

C2

Figure 6. A general second-order transconductance-C filter. The circuit realizes arbitrary zeros by feeding the input signal into portions
C1 and C2 of the capacitors C1 and C2.

ceptually, the block diagram in Fig. 7 shows the method (8).

The control loop equates the inaccurate unit frequency u
gm /C to the accurate reference frequency R in the following
way: R is chosen in the vicinity of the most critical frequency
parameters of the filter (the band-edge for a low-pass, midband for a bandpass filter), where sensitivities are highest.
The transconductance gm to be tuned is assumed to be proportional to the bias voltage VB, such that gm kVB where k is a
constant of proportionality with units of A/V2. gm generates
an output current I gmVR, which results in the capacitor
voltage VC gmVR /( jRC). The two matched peak detectors PD
convert the two signals VR and VC to their dc peak values, so
that any phase differences do not matter when comparing the
signals at the input of gmc. The dc output current Ic
gmcVR1 [gm /( jRC)] of the control-transconductance gmc
charges the storage capacitor Cc to the required bias voltage
VB for the transconductance gm. The values gmc and Cc determine the loop gain; they influence the speed of conversion but
are otherwise not critical. If the value of gm gets too large
because of fabrication tolerances, temperature, or other effects, Ic becomes negative, Cc discharges, and VB, that is gm
kVB, is reduced. Conversely, if gm is too small, Ic becomes positive and charges Cc, and the feedback loop acts to increase
VB and gm. The loop stabilizes when VC and VR are equal, that
is, when gm(VB)/C is equal to the accurate reference frequency
R. The gmc Cc combination is, of course, an integrator with
ideally infinite dc gain to amplify the shrinking error signal
at the input of gmc. In practice, the open loop dc gain of a
transconductance of 35 to 50 dB is more than adequate. Note
that the loop sets the value of u to R regardless of the causes
of any errors: fabrication tolerances, parasitic effects, temperature drifts, aging, or changes in dc bias.
We point out that although the scheme just discussed only
varies gm, it actually controls the time constant C/gm, that is,
errors in both gm and C are accounted for. If one wishes to
control only gm, the capacitor C in Fig. 7 is replaced by an
accurate resistor Re, and the feedback loop will converge to
gm 1/Re.
Notice that the feedback loop in Fig. 7 controls directly
only the transconductance gm (as does the frequency control
circuit in Fig. 8) such that the unit frequency parameter u
within the control circuit is realized correctly. The actual filter
is not tuned. However, good matching and tracking can be

430

CIRCUIT TUNING

f-VCO

EXOR

f control

LPF 1

LPF 2

VR
Vf
PD
Q-VCO

Q model

K
PD

To main filter

VQ

Q control
Figure 8. Dual-control loop-tuning system for tuning frequency parameters and quality factors of an integrated filter. Note that the
frequency loop converges always, but for the Q loop to converge on
the correct Q value, the frequency must be correct. Details of the
operation are explained in the text.

assumed across the IC because all gm cells are on the same

chip and subject to the same error-causing effects. This assumes that the ratios gi defined in Eq. (32) are not so large
that matching problems will arise and that care is taken to
account for (model the effect of) filter parasitics in the control
circuit. The same is true for the unit capacitor C in the control
loop and the filter capacitors (again, if the ratios ci are not too
large). Consequently, the control bias current IB can be sent
to all the main filters transconductance cells as indicated in
Fig. 7 and thereby tune the filter. Clearly, this scheme depends on good matching properties across the IC chip. Accurate tuning cannot be performed if matching and tracking
cannot be relied upon or, in other words, if the gm C circuit
in the control loop is not a good representative model of the
filter cells.
An alternative method for frequency tuning [see Schaumann, Ghausi, and Laker (3), Sec. 7.3, pp. 418446, and
Johns and Martin (6), Sec. 15.7, pp. 626635] relies on phaselocked loops [see Johns and Martin (6), Chap. 16, pp. 648
695]. The top half of Fig. 8 shows the principle. A sinusoidal
reference signal VR at R and the output of a voltagecontrolled oscillator ( f-VCO) at vco are converted to square
waves by two matched limiters. Their outputs enter an EXOR
gate acting as a phase detector whose output contains a dc
component proportional to the frequency difference vco
R of the two input signals. The low-pass filter LPF 1 eliminates second- and higher-order harmonics of the EXOR output and sends the dc component to the oscillator f-VCO, locking its frequency to R. Just as the gm C circuit in Fig. 7, the
oscillator is designed with transconductances and capacitors
to represent (model) any frequency parameter errors of the
filter to be tuned so that, relying on matching, the filter is
tuned correctly by applying the tuning signal also to its gm
cells. The low-pass filter LPF 2 is used to clean the tuning
signal Vf further before applying it to the filter.
We saw in Eq. (33) that all filter parameters depend, apart
from u, only on ratios of like components and are, therefore,
accurately manufacturable and should require no tuning.
This is indeed correct for moderate frequencies and filters
with relatively low Q. However, Q is extremely sensitive [see

Schaumann, Ghausi, and Laker (3), Chap. 7, pp. 410486] to

small parasitic phase errors in the feedback loops of active
filters, so that Q errors may call for tuning as well, especially
as operating frequencies increase. The problem is handled in
much the same way as frequency tuning. One devises a model
(the Q-model in Fig. 8) that represents the Q errors to be
expected in the filter and encloses this model circuit in a control loop where feedback acts to reduce the error to zero. Figure 8 illustrates the principle. In the Q control loop, a Q-VCO
(tuned correctly by the applied frequency control signal Vf )
sends a test signal to the Q model that is designed to represent correctly the Q errors to be expected in the filter to be
tuned, and through a peak detector PD to an amplifier of gain
K. K is the gain of an accurately designable dc amplifier. Note
that the positions of PD and K could be interchanged in principle, but a switch would require that K is the less well-controlled gain of a high-frequency amplifier. The output of the
Q model goes through a second (matched) peak detector.
Rather than measuring Q directly, which is very difficult in
practice, because it would require accurate measurements of
two amplitudes and two frequencies, the operation relies on
the fact that Q errors are usually proportional to magnitude
errors. The diagram in Fig. 8 assumes that for correct Q the
output of the Q model is K times as large as its input so that
for correct Q the inputs of the comparator are equal. The dc
error signal VQ resulting from the comparison is fed back to
the Q model circuit to adjust the bias voltages appropriately,
as well as to the filter. In these two interacting control loops,
the frequency loop will converge independently of the Q control loop, but to converge on the correct value of Q, the frequency must be accurate. Hence, the two loops must operate
together. The correct operation and convergence of the frequency and Q control scheme in Fig. 8 has been verified by
experiments [see Schaumann, Ghausi, and Laker (3), Chapter
7, pp. 410486] but because of the increased noise, power consumption, and chip area needed for the control circuitry, the
method has not found its way into commercial applications.
BIBLIOGRAPHY
1. G. Moschytz, Linear Integrated Networks: Design. New York: Van
Nostrand-Reinhold, 1975
2. P. Bowron and F. W. Stevenson, Active Filters for Communications and Instrumentation. Maidenhead, UK: McGraw-Hill, Ltd.,
1979.
3. R. Schaumann, M. S. Ghausi, and K. R. Laker, Design of Analog
Filters: Passive, Active RC and Switched Capacitor. Englewood
Cliffs, NJ: Prentice-Hall, 1990.
4. W. E. Heinlein and W. H. Holmes, Active Filters for Integrated
Circuits. Munich: R. Oldenburg, 1974.
5. E. Christian, LC Filters: Design, Testing and Manufacturing. New
York: Wiley, 1983.
6. D. A. Johns and K. Martin, Analog Integrated Circuit Design. New
York: Wiley, 1997.
7. Y. Tsividis and J. A. Voorman, Eds., Integrated Continuous-Time
Filters: Principles, Design and Implementations. Piscataway, NJ:
IEEE Press, 1993.
8. J. F. Parker and K. W. Current, A CMOS continuous-time bandpass filter with peak-detection-based automatic tuning. Int. J.
Electron., 1996 (5): 551564, 1996.

ROLF SCHAUMANN
Portland State University

CLIENTSERVER SYSTEMS

CIRCULAR BIREFRINGENCE. See CHIRALITY.

CIRCULAR DICHROISM, MAGNETIC. See MAGNETIC
STRUCTURE.

CIRCULATORS, NUMERICAL MODELING. See NUMERICAL MODELING OF CIRCULATORS.

CLEAR WRITING. See DOCUMENT AND INFORMATION

DESIGN.

431

562

COMBINATIONAL CIRCUITS

COMBINATIONAL CIRCUITS
Combinational (combinatorial) circuits realize Boolean functions and deal with digitized signals, usually denoted by 0s
and 1s. The behavior of a combinational circuit is memoryless; that is, given a stimulus to the input of a combinational
circuit, a response appears at the output after some propagation delay, but the response is not stored or fed back. Simply
put, the output depends solely on its most recent input and is
independent of the circuits past history.
Design of a combinational circuit begins with a behavioral
specification and selection of the implementation technique.
These are then followed by simplification, hardware synthesis, and verification.
Combinational circuits can be specified via Boolean logic
expressions, structural descriptions, or truth tables. Various
implementation techniques, using fixed and programmable
components, are outlined in the rest of this article. Combinational circuits implemented with fixed logic tend to be more
expensive in terms of design effort and hardware cost, but
they are often both faster and denser and consume less
power. They are thus suitable for high-speed circuits and/or
high-volume production. Implementations that use memory
devices or programmable logic circuits, on the other hand, are
quite economical for low-volume production and rapid prototyping, but may not yield the best performance, density, or
power consumption.
Simplification is the process of choosing the least costly implementation from among feasible and equivalent implemenJ. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

COMBINATIONAL CIRCUITS

tations with the targeted technology. For small combinational

circuits, it might be feasible to do manual simplification based
on manipulating or rewriting logic expressions in one of several equivalent forms. In most practical cases, however, automatic hardware synthesis tools are employed that have
simplification capabilities built in. Such programmed simplifications are performed using a mix of algorithmic and heuristic transformations. Verification refers to the process of ascertaining, to the extent possible, that the implemented circuit
does in fact behave as originally envisaged or specified.
A half adder is a simple example of a combinational circuit.
The addend, augend, carry, and sum are all single binary digits or bits. If we denote the addend as A and the augend as
B, the Boolean function of carry-out Co and sum S can be written as
Co = AB

implementation of combinational circuits using gate networks

and multiplexers. These are fixed (as opposed to programmable) logic devices in the sense that they are used by suitably
interconnecting their input/output terminals, with no modification to the internal structures of the building blocks.
Using Gate Networks
Let us begin with the Boolean function D defined as
D = AB + BC
where A, B, and C are input variables whose values can be
either 0 or 1. Direct implementation based on the preceding
expression would require three chips: one that contains inverters (such as 7404), one that contains two-input AND
gates (such as 7408), and one that contains two-input OR
gates (such as 7432). Rewriting the logic expression for D as

S = A B = AB + AB

D = B(A + C )

The carry-out and sum functions can also be specified in the

form of a truth table with eight rows (corresponding to the
eight possible combinations of values for the three Boolean
inputs) and two columns in which the values of Co and S are
entered for each of the eight combinations.
The process of designing combinational circuits involves
certain levels of abstraction. For structured circuit implementation, the key is to find high-level building blocks that are
sufficiently general to be used for different designs. While it
is easy to identify a handful of elements (such as AND, OR,
and NOT gates) from which all combinational circuits can be
synthesized, the use of such simple building blocks reduces
the component count by only a modest amount. A more significant reduction in component count may be obtained if each
building block is equivalent to tens or hundreds of gates.
A commonly used building-block approach is based on
array structures. Programmable logic devices (PLDs) are composed of primitive gates arranged into logic blocks whose connections can be customized for realizing specific functions.
Programmable elements are used to specify what each logic
block does and how they are combined to produce desired
functions. This fundamental idea is used in connection with
various architectures and fabrication technologies to implement a wide array of different PLDs.
IMPLEMENTATIONS WITH FIXED LOGIC
If the input-output behavior of the combinational circuit is
defined by means of a logic statement, then the statement can
be easily expressed in sum-of-products form using Boolean algebra. Once in this form, its implementation is a relatively
straightforward task. In the following, we will consider the

reduces the number of gates from 4 to 3, but does not affect

the component or chip count discussed in the preceding.
By applying DeMorgans theorem, we can derive an equivalent logic expression for our target Boolean function that can
be implemented using a single chip containing only NOR
gates (such as 7402).
D = B + (A + C)
Similarly, DeMorgans theorem allows us to transform the
logic expression into one whose implementation requires only
NAND gates:
D = (AB)(BC)
Figure 1 shows the three gate network implementations of D
using NOT-AND-OR, NOR, and NAND gates, as discussed
in the preceding. The output D of such a combinational gate
network becomes available after a certain delay following the
application of its inputs. With gate-level components, the input-to-output delay, or the latency, of a combinational circuit
depends on the number and types of gates located on the
slowest path from an input terminal to the output. The number of gate levels is a rough indicator of the circuits latency.
Practical combinational circuits may contain many more
gates and levels than the simple examples shown in Fig. 1.
As combinational circuits are often placed between synchronously clocked storage elements, or latches, the circuits latency dictates the clock rate and, thus, the overall system
speed. One way to improve the computation rate, or
throughput, is to partition the gates into narrow slices, each

A
D

A
D

C
B

C
Not-and-or

563

B
C

Nor-only

Nand-only

Figure 1. Realizing the Boolean function D AB BC by gate networks.

564

COMBINATIONAL CIRCUITS

Figure 2. Schematic of a pipelined combinational circuit.

Using Multiplexers
The application of discrete logic circuits becomes impractical
as our Boolean expression grows in complexity. An alternative solution might be the use of a multiplexer. To implement
the Boolean function with a multiplexer, we first expand it
into unique minterms; each of which is a product term of all
the variables in either true or complement form
D = AB(C + C) + (A + A)BC = ABC + ABC + ABC
With L input variables, there are 2L possible minterms, each
corresponding to one data line of a 2L-to-1 multiplexer. Figure
3 shows an 8-to-1 multiplexer and the logic expression for its

x0

x1

x2

x3

x4

x5

x6

x7

s1

...

...

...

Outputs

Clock

consisting of only a few levels, and buffer the signals going

from one slice to the next in latches. In this way, the clock
rate can be made faster and a new set of inputs processed in
each clock cycle. Thus, the throughput improves while both
latency and cost deteriorate due to the insertion of latches
(see Fig. 2).
Today, digital implementation technologies are quite sophisticated and neither cost nor latency can be easily predicted based on simple notions such as number of gates, gate
inputs, or gate levels. Thus, the task of logic circuit implementation is often relegated to automatic synthesis or CAD
tools. As an added benefit, such tools can take many other
factors, besides cost and latency, into account. Examples of
such factors include power consumption, avoidance of hazards, and ease of testing (testability).

s2

...

Inputs

...

Latches

output. A 2L-to-1 multiplexer can be used to implement any

desired L-variable Boolean function by simply connecting the
input variables to its select lines, logic 1 to the data lines
corresponding to the minterms, and logic 0 to the remaining
data lines. The select inputs s2, s1, and s0, when viewed as a
3-bit binary number, represent an index i in the 0 to 7 range.
The value on data line xi is then chosen as the output.
To implement a Boolean function with more variables than
can be accommodated by a single multiplexer, we can connect
other multiplexers to the xi inputs to obtain a multilevel multiplexer realization. For example, to implement a 6-variable
function, we can expand it in terms of three of the variables
to obtain an expression similar to the one shown on the output in Fig. 3, where the xi are residual functions in terms of
the remaining variables.
Figure 4 shows how the function D can be implemented by
an 8-to-1 multiplexer. We can view the single wire entering
each AND gate as representing multiple inputs. In effect, we
have an 8-bit memory whose hardwired data are interrogated
by the input variables; the latter information filters through
the decoder, which finds the corresponding data line and selects it as the output.
With a multiplexer that can supply both the output D and
its complement D, we can choose to tie the minterms to logic
1 and the remaining data lines to logic 0, or vice versa. This,
again, is an application of DeMorgans theorem.
A 2L-to-1 multiplexer can be implemented as an L-level
network of 2-to-1 multiplexers. This becomes clear by noting
that a 2-to-1 multiplexer is characterized by the equation
Y = sx0 + sx1

s0

and that the output logic expression for the 8-to-1 multiplexer
of Fig. 3, say, can be written as:
Y = s2 ( s1 ( s0 x0 + s1 x1 )) + s1 ( s0 x2 + s0 x3 ))
+ s2 ( s1 ( s0 x4 + s0 x5 )) + s1 ( s0 x6 + s0 x7 ))
Y

s2
+ s2
+ s2
+ s2

s1
s1
s1
s1

s0 x0 +
s0 x2 +
s0 x4 +
s0 x6 +

s2
s2
s2
s2

s1
s1
s1
s1

s0 x1
s0 x3
s0 x5
s0 x7

Figure 3. A multiplexer or selector transfers one of its data inputs

to its output depending on the values applied to its select inputs.

Another way to justify the preceding is to note that a 2-to-1

multiplexer can act as a NOT, AND, or OR gate:

NOT:
AND:
OR:

x0 = 1, x1 = 0
x0 = 0
x1 = 1

yields
yields
yields

Y =s
Y = sx1
Y = s + x0

We have just concluded our examination of a simple programmable logic device. The basic elements include a means
to store data, a decoding function to retrieve data, and an
association of data with logic values. In the case of a multi-

COMBINATIONAL CIRCUITS

A
0

565

0
0

1
1
2
2
3
Y

4
4
5
5
6
6
7

1
7
Decoder

plexer, the programmability is provided by manual wiring.

Slightly more complicated schemes use fuse or antifuse elements. A fuse is a low-resistance circuit element that can be
opened permanently by a relatively high surging current,
thus disconnecting its endpoints. An antifuse is the opposite
of a fuse; it is an open circuit element that can be made permanently low resistance. Both fuse and antifuse offer onetime programmability (OTP). Once programmed, they cannot
be modified.
IMPLEMENTATIONS WITH MEMORY DEVICES
Multioutput Boolean functions can be implemented by several
multiplexers connected in parallel. However, it seems wasteful to have multiple decoders, especially when the number of
variables is large. Removing all but one of the replicated decoders in the multiplexers and making the hardwiring
changeable lead to a memory structure, as shown in Fig. 5.
This approach of logic being embodied in the memory content

D1

D2

DN

...

...

...

Figure 5. The read path of a memory device goes through the address decoder and the memory array. Such a device can be viewed as
a multiplexer with multiple outputs.

Figure 4. Realizing the Boolean function

D AB BC by an 8-to-1 multiplexer.

is the well-known table-lookup method for implementing

Boolean functions.
Table lookup is attractive for function evaluation as it
allows the replacement of irregular random logic structures
with much denser memory arrays. The input variables constitute an address that sensitizes a word select line and leads to
the stored data in that particular word being gated out. As in
the case of the multiplexer, the values to be stored are related
to the minterms of the Boolean function. Thus, the content of
each memory column in Fig. 5 is the truth table of the associated output function.
Figure 6 shows the use of an 8 2 bit memory device to
implement a full adder. The full adder is a half adder augmented with a single-bit carry-in Ci and is specified by the
Boolean functions

Co = AB + ACi + BCi
S = A B Ci = ABCi + ABCi + ABCi + A BCi
In general, memory cells can be classified in two major categories: read-only memory (ROM) (in some cases, read-mostly),
which is nonvolatile, and random-access memory (RAM)
(read-write memory is a better designation), which is volatile.
They are distinguished by: (1) the length of write/erase cycle
time compared with the read cycle time; and (2) whether the
data are retained after power-off. Programmability refers to
the ability to write either a logic 0 or 1 to each memory cell,
which in some cases must be preceded by a full or partial
erasure of the memory content (such as in EPROM and EEPROM). In this respect, PLDs are no different and actually
use some form of memory in their structures.
Strictly speaking, implementations of Boolean functions
based on such memory devices cannot be viewed as combinational. Many PLDs are in fact sequential in nature. They become combinational only because the clocked latches are bypassed. However, the programming will never occur in
operation and, in some cases, is limited to a certain maximum
number of times during the life of the device. Thus, between
programming actions, even such latched or registered PLDs
behave as truly combinational circuits.

566

COMBINATIONAL CIRCUITS

A
A

Inputs
B Ci

Minterms

Co

Outputs
Co S

Figure 6. Using memory to realize a full

adder. The memory content on the right
is in one-to-one correspondence with the
truth table on the left.

ABCi

ABCi

ABCi

ABCi

ABCi

1
4

ABCi

ABCi

ABCi

6
7

It is noteworthy that in Fig. 5, the programmable elements

(memory cells) along each column are wire-ORed together. Intuitively, the programmable elements can also be placed in
the decoder so they are wired-ANDed together along each column. These and other variations lead to different building
blocks. Programmable logic array (PLA) and programmable
array logic (PAL) are two types of building blocks that are
universally used for implementing combinational circuits in
PLDs.
IMPLEMENTATIONS WITH PROGRAMMABLE LOGIC
The memory-based implementation of Fig. 5 has the essential
feature of array logic, that is, a regular array that is programmable. Array logic operates by presenting an address in the
data path to the memorylike structure. Decoding of this address starts the process whereby a predetermined result is
extracted from the array. Because the result generated by
such an array depends on the content of the array, the Boolean function can, in principle, be changed in the same way as
writing into a memory.
Using Programmable Logic Arrays
Instead of expanding the product terms into minterms exhaustively, we take advantage of dont care conditions to let

the decoder select more than one row simultaneously. Programmable logic devices are organized into an AND array
and an OR array, with multiple inputs and multiple outputs.
The AND array maps the inputs into particular product
terms; the OR array takes these product terms together to
produce the final expression. Figure 7 shows a block diagram
for the array component.
Figure 8 shows a commonly used scheme for representing
the topologies of PLAs. The input variables x1, x2, . . ., xL and
their complements x1, x2, . . ., xL constitute the columns of the
AND array. The rows correspond to the product terms z1, z2,
. . ., zM in both the AND and OR arrays. The columns of the
OR array represent the Boolean functions y1, y2, . . ., yN in
sum-of-products form. The complexity of PLA is determined
by the number L of inputs, the number M of product terms,
and the number N of outputs. An L-input, M-product-term, Noutput PLA is sometimes referred to as an L M N device.
The number of product terms is often selected to be much
smaller than 2L (for example, M 4L). There is a penalty for
this tremendous compression. Whereas a memory device with
its full decoder can generate any function of the input variables, the partial decoder of the PLA device generates a very
limited number of product terms.
Because of the severe limitation on the number of available
product terms, an aggressive two-level logic minimization

x1

Outputs

Inputs

x2

xL

y1

...

y2

yN

...

...

...

z1
OR array
(OR plane)

...

...

z2
AND array
(AND plane)

zM
Product terms
Figure 7. The basic logic array component consists of an AND array
and an OR array.

x1

x1

x2

x2

xL

xL

Figure 8. A commonly used scheme for representing the topology of

array logic explicitly shows its columns and rows. The cross-points
mark the locations of programmable elements whose states may be
changed through programming.

COMBINATIONAL CIRCUITS

Inputs
A B Ci

Product
terms

Outputs a
Co S

AB

ACi

BCi

ABCi

ABCi

ABCi

ABCi

Co

Figure 9. A personality matrix defines

the inputs, product terms, and outputs of
a PLA.

a These

specify the connections in the OR

array rather than output logic values.

method is critical for effective utilization of PLAs. A convenient way to describe a function for PLA realization is
through a personality matrix, which is a minor reformulation
of the truth table. Figure 9 shows an example for a full adder
and the corresponding PLA realization.
For the realization of Boolean functions PLAs are widely
used within integrated circuit designs. A distinct advantage
is that their regular structures simplify the automatic generation of physical layouts. However, only a few devices are
available as stand-alone parts for combinational circuit design. Currently available configurations include 16 48 8,
18 42 10, and 22 42 10 (by Philips Semiconductors).
Multilevel logic structures can be realized with PLAs either by interconnecting several PLAs or by connecting certain
of the outputs to the inputs in a single PLA. As an example,
an 18 42 10 PLA can implement the parity or XOR function in two-level AND-OR form for no more than six inputs.
The reason is that the seven-input XOR function has 64 minterms which is beyond the capacity of the preceding PLA.
Consider the problem of implementing the nine-input XOR
function. One way is to divide the inputs into three groups of
three and separately realize 3 three-input parity functions using 9 of the inputs, 12 of the product terms, and 3 of the
outputs. The preceding three outputs can then be fed back to
three of the unused inputs and their XOR formed on one of
the available outputs by utilizing four more product terms.
Using Programmable Array Logic
A more common programmable solution is to use PALs. There
is a key difference between PLAs and PALs: PLAs have the
generality that both the AND and OR arrays can be programmed; PALs maintain the programmable AND array, but
simplify the OR array by hardwiring a fixed number of product terms to each OR gate.
For example, the commercial PAL device 16L8 (which
means that the device has 16 inputs and 8 outputs, and it is
active low combinational) arranges the AND array in 32 columns and 64 rows. Each AND gate has programmable connections to 32 inputs to accommodate the 16 variables and
their complements. The 64 AND gates are evenly divided into
8 groups, each group associated with an OR gate. However,
there are only 7 AND gates connected to each OR gate and,
thus, each Boolean function is allowed to have at most 7 product terms. The remaining one AND gate from each group is

567

connected to a tri-state inverter right after the OR gate, as

depicted in Fig. 10. The device shown in Fig. 10 actually has
10 inputs, 2 outputs, and 6 bidirectional pins that can be used
as either inputs or outputs.
There exists a fundamental trade-off between speed and
capacity in PLDs. It is fair to say that for devices with comparable internal resources, a PLA should be able to implement
more complex functions than a PAL. The reason is that the
PLA allows more product terms per output as well as productterm sharing; that is, outputs of the AND array can be shared
among a number of different OR gates. On the other hand,
the PLA will be slower because of the inherent resistance and
capacitance of extra programmable elements on the signal
paths.
In reality, NOR-NOR arrays may be used, instead of ANDOR arrays, to achieve higher speed and density. (Transistors
are complementary, but the N-type is more robust than the
P-type and is often the preferred choice.) Consider the full
adder example. We can rewrite the Boolean functions as follows:

Co = A B + ACi + BCi
S = A B Ci = A BCi + ABCi + ABCi + ABCi
The inverted inputs and outputs preserve the original ANDOR structure so the realization is equivalent, as shown in
Fig. 11.
As in the case of PLAs, we can use several PALs to implement logic functions that are too complex for the capabilities
of a single device. Feeding back the outputs into the array in
order to realize multilevel circuits is facilitated by the builtin feedback paths (see Fig. 10). As an example, to implement
the 9-input XOR function using the PAL device 16L8 shown
in Fig. 10, we can divide the inputs into three groups of 3
and proceed as we did for the PLA implementation. The only
difference is that the feedback paths are internal and no external wiring is needed.
Other PLD Variants
Generic array logic (GAL) is a slight enhancement of PAL
that includes an XOR gate after each OR gate. The XOR gate
can be viewed as a controlled inverter that changes the output polarity if desired. Given that y 0 y and y 1 y,

568

COMBINATIONAL CIRCUITS

1
0

19
7
2
8

18
15
3
16

17
23
4
24

16
31
5
32

15
39
6
40

14
47
7
48

13
55
8
56

12
63
9

11
0

11 12

15 16

19 20

23 24

27 28

31

Figure 10. Schematic diagram of the PAL device 16L8 known as its programming map. Locations to be programmed are specified by their numbers (11-bit integers in the range 0 to 2047,
composed of a 6-bit row number and a 5-bit column number).

COMBINATIONAL CIRCUITS

Ci

Co

569

In order to cover most designs, PLDs are organized to balance speed and capacity within the constraints of fabrication
technologies. Because the assemblages of logic blocks are positioned where they are anticipated to be useful to each other,
such an approach is necessarily wasteful. There were once
expectations that PLDs could replace discrete components.
While this has not yet materialized, PLDs do indeed offer a
compact means of implementing Boolean functions that is
particularly attractive for rapid prototyping to evaluate possible improvements or to verify new ideas.
Reading List
Advanced Micro Devices, PAL Device Data Book, 1996.
J. W. Carter, Digital Designing with Programmable Logic Devices,
Englewood Cliffs, NJ: Prentice-Hall, 1997.

Figure 11. The implementation of a full adder in PAL using NOR

gates is equivalent to that using AND and OR gates. The figure assumes that four product terms are tied to each sum term.

H. Flesher and L. I. Maissel, An introduction to array logic, IBM J.

Res. Develop., 19 (2): 98109, 1975.
J. W. Jones, Array logic macros, IBM J. Res. Develop., 19 (2): 120
126, 1975.
R. H. Katz, Contemporary Logic Design, Redwood City, CA: Benjamin/
Cummings, 1994.

we can choose to implement a Boolean function directly or

generate its complement and then invert it. As an extreme
example, y x1 x2 x16 cannot be implemented by
PAL16L8, but it can be easily realized by a similar device
that includes the aforementioned XOR gates through implementing y x1 x2, . . ., x16 and then complementing the result. It is therefore not surprising that most PALs now allow
one to control their output polarity through an XOR gate or
with a multiplexer that chooses the true or complement
result.
The ultimate in flexibility is provided by field-programmable gate arrays (FPGAs) which consist of a regular array of
logic blocks with programmable functionalities and interconnections. Figure 12 shows part of a generic FPGA component.
Each block can implement one or more simple logic functions,
say of four or five logic variables. The inputs to the block can
be taken from its adjacent horizontal or vertical signal tracks
(channels) and its output(s) can be routed to other blocks via
the same channels. The logic blocks of an FPGA store their
outputs in storage elements, thus making the result a sequential circuit. Combinational circuits can be implemented by
programmed bypassing of the storage elements.

Lattice Semiconductor, Introduction to GAL device architectures,

ISP Encyclopedia, 1996.
Philips Semiconductors, Programmable Logic Devices Data Handbook, 1993.
K. Tsuchiya and Y. Takefuji, A neural network approach to PLA folding problems, IEEE Trans. Comput.-Aided Des. Integr. Circuits
Syst., 15: 12991305, 1996.

BEHROOZ PARHAMI
DING-MING KWAI
University of California

COMBINATORIAL DESIGN THEORY. See THEORY OF

DIFFERENCE SETS.

COMBINATORIAL OPTIMIZATION PROBLEMS.

See GRAPH THEORY.

COMBINERS AND DIVIDERS, POWER. See POWER

COMBINERS AND DIVIDERS.

COMMERCE, ELECTRONIC. See ELECTRONIC DATA INTERCHANGE.

COMMUNICATION CHANNEL NOISE. See NOISE

AND INTERFERENCE MODELING.

Logic
block

COMMUNICATION FOR LOCATING MOBILE USERS. See PAGING COMMUNICATION FOR LOCATING MOBILE
USERS.

COMMUNICATION, INTERNATIONAL. See INTERNATIONAL COMMUNICATION.

COMMUNICATION, MILITARY. See MILITARY COMMUNICATION.

COMMUNICATION PROTOCOLS. See COMPUTER

COMMUNICATIONS SOFTWARE.

Figure 12. Part of an FPGA, consisting of four rows and two columns
of logic blocks and their associated programmable interconnections
(channels). The upper left logic block has been configured to receive
three inputs from its upper and lower horizontal channels and to send
its output to the logic block at the lower right via a vertical and a
horizontal channel segment.

COMMUNICATIONS. See SPEECH, HEARING AND VISION.

COMMUNICATIONS, COMPUTER. See COMPUTER
NETWORKS.

COMMUNICATIONS, METEOR BURST. See METEOR

BURST COMMUNICATION.

570

COMPANDORS

COMMUNICATIONS, MULTIPLE USERS. See MULTIPLE ACCESS MOBILE COMMUNICATIONS.

COMMUNICATIONS SOFTWARE, COMPUTER.

See COMPUTER COMMUNICATIONS SOFTWARE.

COMMUNICATION THEORY. See INFORMATION

THEORY.

COMMUNICATION USING POWER LINES. See

POWER LINE COMMUNICATION.

COMPACT DISK READ ONLY. See CD-ROMS, DVDROMS, AND COMPUTER SYSTEMS.

COMPACT MODELS. See NONLINEAR NETWORK ELEMENTS.

COMPARATOR CIRCUITS

577

COMPARATOR CIRCUITS
Comparators are used to detect the sign of the difference between two analog signals x(t) and x(t), and to codify the
outcome of the detection through a digital signal y. This operation can be formulated as follows:


y=

> EOH
< EOL

for
for

x+ (t) > x (t)

x+ (t) < x (t)

(1)

where EOH and EOL are levels that guarantee correct logic
interpretation of the output signal, that is, y EOH guarantees that the output is unambiguously interpreted as a true
logic one (1D) by any digital circuit connected to the output
node, whereas y EOL guarantees that the output is interpreted as a true logic zero (0D). The definition of these levels
is related to the concepts of logic restoration and digital noise
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

578

COMPARATOR CIRCUITS

(a)

ESH

(b)

ESH

(c)

(0,0)
L
ESL

(0,0)

x
H

(0,0)

ESL
Figure 1. Some useful extensions of the binary comparator concept.

margins that the interested readers will find in Ref. 1. In

many applications one of the inputs is a reference value, say
x(t) E, and the comparator function is to detect whether
the signal applied to the other input, say x(t) x(t), is larger
or smaller than such reference.
Comparators are classified according to the physical nature of their inputs and output. The most significant structures for practical applications have voltage input and voltage
output and are called voltage comparators. Most of this article
is devoted to them. Others that are also of interest for the
newest class of current-mode circuits that have current-input
and voltage-outputcurrent comparatorsare also covered
in this article.
Another criterion for classifying comparators is their operation in the time domain. Continuous time (CT) comparators
operate asynchronously. They respond to input changes at
any time instant. The speed of change is limited only by the
intrinsic comparator response. On the other hand, discretetime (DT) comparators operate in synchronization with a
clock signal. They respond only at some prescribed time intervals (called compare, or active, intervals), whereas others
(called reset, or strobe, intervals) are used to establish initial
conditions. In many applications synchronization is imposed
by system-level timing considerations. But, even when synchronization is not mandatory, DT operation can be used for
error correction. On the other hand, although DT comparator
speed is limited by clock frequency, proper architectures enable operation in the video range and above. Overall responses faster than with CT comparators might even be
achieved through proper design.
Comparators are the basic building blocks of analog-to-digital converters. Hence they are crucial components for realizing the front-ends of the newest generations of mixed-signal
electronic systems (2). Mixed-signal systems are those which
combine analog and digital signals. Most modern electronic
systems are mixed-signal. They handle analog signals at the
input and output interfaces and perform most of the processing, control, and memory tasks by using digital techniques. Other comparator applications include such diverse
areas as signal and function generation (3), digital communications (4), or artificial neural networks (5), among others.
Because in these applications the prevalent trend is towards
microelectronic realizations, this article emphasizes those issues related to the realization of comparators as integrated
circuit components. There are also a few extensions of the
basic comparator concept of Eq. (1) which further increase the
scope of comparator application. Figure 1 shows transfer
characteristics for some typical extensions, namely: the hysteresis comparator [Fig. 1(a)] (This device has memory. Once

the output is in the high state, it remains there whenever the

input remains larger than L. On the other hand, once the
output is in the low state, it remains there whenever the input remains smaller than H.), the window comparator [Fig.
1(b)], and the M-ary (multilevel) comparator [Fig. 1(c)] not
covered in this article.
COMPARATOR BEHAVIOR
Ideal Comparator Behavior
Figure 2(a) illustrates the ideal comparator operation, where
ESL and ESH are saturation levels for the output signal. The
interval defined by these levels is usually wider than that defined by the restoring logic levels logic. According to Eq. (1)
the output is at the high logic state whenever the differential
input x(t) x(t) x(t) is positive, and at the low logic state
otherwise. Thus, the ideal transfer characteristic exhibits a
step transition at x 0, as Fig. 2(a) illustrates. On the other
hand, ideally the transitions between the two output states
should happen instantaneously following any change of the
sign of x(t), also illustrated in Fig. 2(a).
Let us focus on voltage comparators. Ideal voltage comparators have the following features:
infinitely large voltage gain [equivalently, infinitely
small transition region between the output states, or the
capability of detecting infinitely small values of x(t)]
zero input offset voltage (meaning that the transitions
occurs at x 0)
zero delay (meaning that changes in the sign of the analog input voltage x(t) are transmitted instantaneously to
the output)
infinitely large variation range for the common-mode input voltage (meaning that the operation should depend
only on the input voltage difference, not on the value of
the positive and negative components despite how small
or large these components are)
infinitely large input impedance and unlimited driving
capability at the output node
Correspondingly, ideal current comparators must have infinitely large transimpedance gain, zero input offset current,
zero delay, infinitely large range for the common-mode input
current, zero input impedance, and unlimited driving capability at the output node.
There is no practical voltage or current comparator circuit
capable of realizing all of these ideal features. Actual com-

COMPARATOR CIRCUITS
y

y(t)

ESH
EOH

579

ESH

x(t) = x+ (t) x (t)

t

(0,0)
EOL
ESL

ESL
(a)

EOS

x(t)

EOH

EOS

2s
x

(0,0)

(0,0)

(0,0)

EOL
T1

T2 T3

2s

T4

(b)

(c)

y(t)

(d)

y(t)

y(t)

ESH
EOH
(0,0)

(0,0)

(0,0)

t
EOL
ESL

T1 T2 T3

T4

T1 T2 T3

(e)

T4

T1

T2 T3

(f)

T4

(g)

y(t)
ESH
EOH

EOH

(0,0)
EOL
ESL

t=0

T2 T3
(h)

T4

y(t)
x(t)

TC
T1

EOH

y(t)
x(t)

(0,0)

TA

TD
(i)

parator behavior deviates from the ideal comparator illustrated in Fig. 2(a). Depending on how large the deviations
are, comparator circuits may qualify for some applications
and not for others. Thus, comparator users should quantify
the maximum allowed deviations through a proper set of specification parameters, and comparator designers should try to
fulfill these specifications when implementing a comparator
circuit.

(j)

Figure 2. (a) Ideal comparator operation.

(b)(j) Illustrating static and dynamic errors in the comparator response.

Nonideal Comparator Behavior and Comparator Specification

Consider the input waveform shown in Fig. 2(b) whose sign
changes at the time instants T1, T2, T3, and T4. Figure 2(e)
shows the corresponding ideal output waveform. On the other
hand, Figs. 2(f)(h) show erroneous waveforms. To understand the causes and meaning of these errors, first let us assume that the instantaneous transient response feature is retained. Then the error sources are comparator finite gain and

580

COMPARATOR CIRCUITS

offset. First consider the effect of finite gain. It results in the

transfer characteristic of Fig. 2(c), whose transition region
(shaded in the figure) is not abrupt. Because the input values
inside this transition region are not large enough to drive the
output voltage to a logical state, their sign is not correctly
coded, as Fig. 2(f) shows. For simplicity, it has been assumed
that this transition region is symmetrical around the origin
(equivalently, the central piece of the transfer characteristic
is linear and EOH EOL). However, in the more general case,
this symmetry constraint should be removed for proper
analysis.
Now consider the added influence of input offset voltage.
Figure 2(d) shows the transfer characteristics where the zero
crossing is shifted to EOS. Consequently, sign codification is
incorrect for all positive levels smaller than EOS S, as illustrated in Fig. 2(g). Now assume that the gain is infinite and
the input offset is zero. Then errors may appear because the
intrinsic transient comparator response. Because the comparator takes a finite time to react to the input changes, the
comparator output may be unable to follow the fastest input
transitions, as illustrated in Fig. 2(h) for the input change
at T2.
The errors due to nonideal comparator behavior can be anticipated through proper specification of the comparator resolution and transient response (6). Resolution of the comparator
under static excitation is characterized by the following specification parameters,
S (incremental static sensitivity) defined as the input increase (decrease) needed to drive the output voltage to
EOH (EOL) from the central point of the transfer characteristics. This is closely related to the static gain kS
(EOH EOL)/(2S). The larger this gain, the smaller S,
and hence the more sensitive the comparator. Rigorously
speaking and because EOH EOL, two different incremental sensitivities should be defined, one for positive excursions S and other for negative excursions S. However,
for simplicity both are considered equal.
EOS (input offset) defined as the input level required to
set the output voltage at the central point of the transfer
characteristics.
From these parameters, the comparator static resolution is
calculated as
S = |EOS | + S

(2)

where the modulus is used because the offset is essentially

a random variable. For any input level inside the interval
[S, S] the comparator digital output state is uncertain. On
the other hand, any input level outside this interval is called
an overdrive. The overdrive variable measures how far from
this interval the actual input is: xovd xS.
Parameters used to characterize the comparator transient
operation include the following:
TD (delay time) defined as the time required for the comparator output voltage to emerge from a saturated state,
either at ESH or at ESL, and to start evolving to the other
after a falling/rising input edge among two overdrive levels [see Fig. 2(i)]. A closely related figure is the TC (response, or comparison time), which measures the time in-

terval between the falling/rising input edge and the

instant where the output reaches the corresponding restoring logic level [see Fig. 2(i)]. For completeness, the
rise TR and fall TF times might also be considered. As is
conventional in digital circuits, they are defined as the
time between 10% and 90% of the total output swing.
TA (amplification time) defined as the time needed for the
output to reach a restoring logic level, starting from
steady state at the central point of the characteristics
and following the application of an overdrive with amplitude D EOS D [see Fig. 2(j)]. Generally this time
differs for positive and negative excursions. For simplicity we assume full symmetry and calculate TA from the
following expression:
EOH = y(t)|t=T =
A

y(t)|t=T

D

D k D D

(3)

It shows that the output value at t TA is obtained by

multiplying the incremental input D by a number kD
that represents the equivalent dynamic gain featured
after a time TA. On the other hand, parameter D defines
the incremental dynamic sensitivity, and D defines the
dynamic resolution, both functions of TA. When the output waveform is monotonic and bounded and assuming
D S, Eq. (3) shows that kD kS TA finite, and that
kD kS, for TA . It means that the dynamic resolution parameter D is larger than the static one, that is D
poses a stronger constraint on resolution than S. On the
other hand, Eq. (3) highlights a tradeoff between resolution and speed, that is, the smaller TA, the smaller the
dynamic gain, and hence, the less sensitive the comparator.
Because discrete-time comparators are driven to their central
point during the reset phase, the amplification time is particularly pertinent for them. It is complemented with the reset
time TR, defined as the time needed for the output to evolve
from a logic state to reach the steady state at the central
point.
Commonly, timing parameters for falling edges differ from
those for rising edges. To distinguish between rise and fall
parameters, an additional subscript, r for rising and f for
falling, is used with TD, TC, TA, and TR. Thus, TAr denotes the
amplification time for a rising edge. On the other hand, because the output waveform depends on the input signal level,
this level should be indicated when specifying delay, comparison, and amplification times.
ONE-STEP VOLTAGE COMPARATORS
Concept and Circuits
Equation (1) and the transfer characteristics of Figs. 2(a), (c),
and (d) show that the voltage comparator function consists of
amplifying a voltage difference while it is transmitted from
input to output. There are several circuit architectures for
achieving this. Each one features different properties for
static and dynamic behavior. Figure 3(a) shows the symbol,
and Fig. 3(b) shows a first-order behavioral model for the simplest architecture. Such a model is representative of a wide

Co

Gm(x)

Go(y)
ESH

+
x

+
+
y

slopegm
m

slopego
ESL

ESH

(a)

(b)

x+

(c)
Node +

Node

i+

ESL

Node +

MNd

MNd

x+

MNB

Node

i+

BN

BN

IB

MNB

slope( gm/go )
x

Go(y)

IB Gm(x)

IB

(d)

MP11
MP1

VBP

MP12

MP11

MP1
MP12
i+ i

Node +

i i+

Node

Node

Node +
MN1

(e)

MN1

i+ i

MP1
y

MP1

MCP

MCP

VCP

Node + Node

(f)

MP1

MP1

MCN

MCN

MN1

MN1

VCN

MPB
(g)

y+

y
IB
2
i+
x+

MP

MNd

IB

MNd

MPB
y

x
MN

MNB

MPB
y

IB

MN

MNB

(h)

(i)
Figure 3. One-step voltage comparators.
581

(j)

582

COMPARATOR CIRCUITS

Table 1. Model Parameters of One-Step CMOS Comparator Structures

Param.

gm

Structure

go

Co

CL
nNdWNdCGD0Nd
nPlWPlCGD0Pl

CL
nNlWNlCGD0Nl
nPl2WPl2CGD0Pl2

AOTAC

IB 1
1

2 VANd VAPl

SOTAC

IB 1
1

2 VANl VAPl2

0Nd W
L
Nd

2 n

nNdIB

Nd

IB

20Nd

W
L

1
4VANlVACN

Nd

0CN W
nCN L

CN

CL
nCNWCNCGD0CN
nCPWCPCGD0CP

I 3B

1
VAPIVACP

0CP W
nCP L

CP

CL
nNdWNdCGD0Nd
nPlWPlCGD0Pl

IB 1
1

2 VANd VAPl

FDPC

0N W
IQ
L N
N

0P W
IQ
2
nP L P

InvC

FOTAC

CInvC

I 3B

0,N W
nN L

1
1

VAN VAP

IQ

CL
nNWNCGD0N
nPWPCGD0P

Not
applicable
IB

IB

catalog of circuit implementations, using either BJTs or

MOSTs.
The model of Fig. 3(b) consists of connecting a transconductor and a resistor, plus a capacitor to represent the unavoidable parasitic dynamics, and obtains the voltage gain in
a single step, as the product of transconductance gm and resistance ro g1
o , so that kS gmro gm /go. It is shown at the
transfer characteristic of Fig. 3(c) where it has been assumed
that m(gm /go) (ESH, ESL) which is fulfilled by all well-behaved practical circuits.
The transconductor of Fig. 3(b) is commonly realized in
practice through a differential pair [Fig. 3(d)] shows realizations using MOSTs and BJTs, respectively) (7). With small
variations of the differential input voltage x x x around
the quiescent point (defined by x x 0), these pairs produce incremental currents i i gm(x/2). On the other
hand, large values of x produce saturated transconductor
characteristics similar to those in Fig. 3(b). The resistor of
Fig. 3(b) is commonly built by using an active-load transistorbased configuration. Figures 3(e)(g) show three CMOS alternatives (7). By connecting each of these active loads to the
CMOS differential pair of Fig. 3(d), three one-step CMOS
comparator structures are obtained, called, respectively, AOTAC [Fig. 3(e)], SOTAC [Fig. 3(f)] and FOTAC [Fig. 3(g)]. For
purposes of illustration, the first three rows in Table 1 includes expressions for the pertinent model parameters of
these one-step comparators as functions of the transistor
sizes, the large-signal MOST transconductance density 0,

1
1

VAN VAPB

CL
nNWNCGD0N
nPBWPBCGD0PB

and the zero-bias threshold voltage VT0 (see Appendix I for a

simplified MOST model).
Some practical one-step comparators provide a differential
output voltage given as the difference between the voltages at
the output terminals of symmetrically loaded differential
pairs. In such cases the differential-pair bias current (henceforth called tail current) must be controlled through feedback
circuitry to stabilize and set the quiescent value of the common-mode output voltage (8). Figure 3(h), where the commonmode regulation circuitry has not been included, shows a
CMOS circuit realization called FDPC. The fourth row in Table 1 shows the corresponding model parameter expressions.
In some applications it is also possible to use logic inverters as one-step comparators. Figures 3(i) and (j) show two
CMOS examples (9), called CInvC and InvC, respectively. The
fifth and sixth rows in Table 1 contain their corresponding
model parameter expressions. These structures have only the
negative input x accessible, whereas the positive input x is
set to an internal reference given approximately by

x+ E

nP

(VDD |VT0P |) +

P

nn I
P

x+ E VSS + VT0N +

N B

nN

(VSS + VT0N )
for CInvC

nN
for InvC

(4)

COMPARATOR CIRCUITS

This feature constrains the usefulness of these circuits as isolated comparators. They are used mostly as components of
multistage comparator architectures.

tion limit, that is, as D S EOH /kS. Because then it is not

possible to assume TA 0, Eq. (6) cannot be approximated,
and the resolution for speed tradeoff is given by

Static and Dynamic Gain in One-Step Comparators

The static resolution of the one-step comparator is given by
S |EOS | +

EOH
go
= |EOS | + EOH
kS
gm

y(t) = D


t
gm

1 e o
go

, where o

Co
go

(6)

D must be larger than S for monotonic comparator responses. Here it is assumed that D S, so that D(gm /go)
EOH. This means that the output reaches the restoring level
EOH in a small fraction of o and, hence, Eq. (6) can be seriesexpanded and approximated to obtain the following expressions for the output waveform and the amplification time:


gm t 
t 
y(t)  D


(7)
D
go o tT
u tT
A

where u Co /gm is the unitary time constant of the amplifier.

From here and Eq. (3), the amplification time and dynamic
resolution, respectively, are given by
TA = u

EOH
u
|EOS | + EOH
kD
TA

T 
A

EOH

k S D
= EOH
E
OH


ln

1 EOH
1
k S D

(8)

(9)

The curve labeled N 1 in Fig. 6(a) illustrates this tradeoff

for a typical EOH 1 V. Because practical applications require D EOH, this curve and Eq. (8) show that TA u,
meaning that the comparator is much slower than the underlying voltage amplifier.
As D decreases, Eq. (9) shows that TA increases at the
same rate. On the other hand, the comparator becomes increasingly slower as the input approaches the static resolu-

(10)

Consider D S(1 ) with 1. Equation (10) can be

simplified to obtain a relationship between the static gain and
the amplification time needed to obtain such limiting sensitivity;

T 
A

= A0 ln

1

(11)

where for homogeneity with subsequent discussions, the

static gain has been renamed as A0. In the limit, as D S
and 0, TA .
The time-transient performance of one-step comparators is
illustrated through a typical example with kS 2 103, u
10 ns and EOH 1 V, such that D TA 108 Vs. Thus,
D 10 mV requires from Eq. (9), that TA 1 s, and D
1 mV requires from Eq. (10) that TA 14 s. On the other
hand, if the static resolution limit has to be approached
within 1%, Eq. (11) yields TA 92 s.
Overdrive Recovery and Comparison
Time in One-Step Comparators
In CT applications, where comparators are not reset prior to
applying the input, characterization of the comparator transient requires calculating the delay and comparison times.
For the purpose consider that the output is saturated because
of an overdrive and that an opposite overdrive of amplitude
D is applied at t 0. Let us assume that y(0) ESL. The
model of Fig. 3(b) gives zero delay time TD and the following
comparison time:

1+

which highlights a tradeoff between resolution and speed:

D

1 ESL
TC
k S D
= kS ln
1 EOH
u
1
k S D

EOH
D

and
D = |EOS | +

D

T 

(5)

Hence, it is limited by the input offset voltage and by the

amount of voltage gain which can be realistically built into a
single step. It depends on technology, circuit structure, and
transistor sizes. The FOTAC can obtain up to around 105,
whereas the others obtain smaller gain values. For such medium-to-large gain values, say kS 103, the static resolution
is basically constrained by the offset voltage, whereas the constraint imposed by the gain dominates for lower values of kS.
Now let us consider the dynamic resolution. Assume that
the capacitor in the model of Fig. 3(b) is discharged at t 0
and consider a unit-step excitation of amplitude D, such that
D is in the linear transconductor region. The output waveform is given by

583


(12)

For kSD EOH and ESL and assuming EOH ESL, this equation
implies a resolution for speed tradeoff similar to that in Eq.
(9): D (TC / u) 2EOH. On the other hand, in the worst case
when the comparator is used close to the static resolution
limit so that D S(1 ) with 1, Eq. (12) can be simplified to give the following fundamental relationship between
static gain A0 and the comparison time required to attain such
limiting sensitivity:

T 
C

= A0 ln

2


(13)

Assuming that A0 2 103 and u 10 ns, TC 106 s is

needed to approach the resolution limit within 1%, slightly
larger than TA 92 s obtained from Eq. (11).

584

COMPARATOR CIRCUITS

OFFSET CANCELLATION IN ONE-STEP COMPARATORS

AOTAC and the FDPC structures, this latter input offset

component is calculated as

The Offset Problem

As already mentioned, the input offset voltage EOS poses an
important constraint on one-step comparator performance.
This nonideal feature reflects a lack of symmetry and has two
different components. Deterministic offset is caused by asymmetries of the comparator circuit structure itself. For instance, the FDPC structure of Fig. 3(h) is symmetrical,
whereas the AOTAC structure formed by connecting the MOS
differential pair of Fig. 3(d) and the active load of Fig. 3(e) is
asymmetric. Consequently, the output voltage at the quiescent point YQ is typically nonnull, thus making EOS YQ /kS.
However, because YQ, in the worst case, is of the same order
of magnitude as EOH, the deterministic offset component
places a similar constraint on comparator resolution as on the
static gain, not significant enough to justify further consideration. On the other hand, random offset contemplates asymmetries caused by random fluctuations of the transistor technological parameters and is observed in asymmetrical and in
symmetrical structures. These fluctuations mismatch nominally identical transistors. The amount of mismatch is inversely proportional to the device area and distance between
them. Particularly, it has been observed that the threshold
voltage and the large-signal transconductance density of
MOSTs fluctuate with standard deviations given by (10),

2 (VT0 )

V2

T0

WL

and

 
0

(14)

WL

EOS |AL VT0Pl

= VT0Pl

Pl

Nd

IB
8Nd

Pl
I 1
+ B
Nd
2 gm

 
0

 

EOS |DP VT0Nd +

IB
8Nd

I 1
= VT0Nd + B
2 gm

 
0

 

Nd

(15)

Nd

has to be applied to equalize these currents. Another voltage

difference EOSAL has to be added to this to compensate for the
asymmetries in the active-load circuitry. In the case of the

(16)

Pl

to obtain EOS EOSDP EOSAL.

Equations (14), (15), and (16) suggest that EOS can be reduced through proper transistor sizing. However, these techniques hardly obtain offsets less than a few millivolts, not
low enough for many practical applications. This drawback
is overcome by adding offset-cancellation circuitry, by which
residual offset values as small as 0.1 mV are obtained (11).
There are three basic approaches for offset cancellation; component trimming; control through an auxiliary nulling port;
and dynamic correction.
Component trimming commonly refers to modifications of
some critical component geometries, for instance, through laser or electron beam cutting, to compensate for the asymmetries and thus minimize offset. Because such trimming is applied only once during the circuit life right after circuit
production, the adjustment must be stable to temperature
and circuit aging. Recently, techniques for nondestructive
trimming have been proposed that exploit the long-term analog storage capabilities of floating-gate MOSTs (12,13).
Another common offset cancellation technique uses additional components controlled through a nulling port. Figure
4(a) illustrates this technique for the SOTAC comparator.
Note that a differential pair controlled by the voltages zos
and zos has been added to the uncompensated structure
(drawn with solid black lines). Mismatch-induced current unbalances are compensated for by setting these control voltages
and the transconductance of the additional differential pair
such that
os
gmos (zos+ zos EOS
) = EOS gm

where W and L are the channel width and length, respectively, V2 T0 and 20 are technological constants, and 0 /0 denotes percentage variations. There is at least one additional
term due to the separation between transistors, but this can
be attenuated through proper layout. On the other hand, typical characterization values for the parameters of Eq. (4) in a
0.5 m technology are V2 T0 105 V2m2 and 20 104 m2.
In the case of the MOST differential pair of Fig. 3(d), random
mismatches between the two transistors labelled MN1 render
their currents different for x x, and a voltage difference
given by

Pl

(17)

where Eos
OS is the offset voltage of the offset-nulling differential
pair. For increased robustness under environmental changes,
the control voltages are generated through a control feedback
loop that monitors EOS and updates the control voltages until
this error is annulled. Figure 4(b) shows a conceptual block
diagram for this technique which implies two different operating modes. During the calibration mode, switches labeled
Scal are ON and those labeled Scom are OFF. Thus the nulling
control voltage is generated by the control loop and stored in
memory. Then, during the comparison mode the circuit features the comparator operation with reduced offset. Alternative implementations of the control loop reported in technical
literature use either fully analog control loops or mixed
analog/digital control loops and feature offset voltages between 40 V and 120 V over a 120C temperature range
(11,14,15). Although this offset cancellation technique involves synchronization, careful design may enlarge the time
interval between calibration events to enable quasi-continuous-time operation.
Self-adjusting comparators are not easy to design and are
area-intensive. Thus they are especially suitable for large cir-

COMPARATOR CIRCUITS

585

Scom
+

+
x
MNOS

zos

zos+

Scom

Scal

y
x

MNd

x+

MNd

IBos

Scal

Memory

Control

IB
Timing

IBR

(a)

(b)
y

x+

xa

MP

Eos

(0,0)
I+

xa

EOS

Eos ks

r
y
xa
MN

1 + ks

Tca

x+

x+

Tcr
(c)

(d)

(e)

VCH
C0V
x+

VCL

xa

xa

Ca

I+

0,

Eos

Eosks
1 + ks

(f)

x+

a
a

(g)

r
+

I+
Eos

TR

x+

a
a

r
+

I+
Eos

(h)

(i)
Figure 4. Offset cancellation in one-step voltage comparators.

586

COMPARATOR CIRCUITS

cuits where the correction circuitry is shared by many comparators.

Offset Compensation Using Dynamic Techniques
The Self-Biased Comparator Circuit. A simple, yet efficient
correction technique uses dynamic self-biasing to extract the
offset and offset storage to annul their influence (16,17). Figure 4(c) shows the corresponding circuit, consisting of an uncompensated comparator (its offset has been represented
through a separate voltage source for enhanced clarity) plus
three clocked analog switches and a capacitor. The circuit requires two nonoverlapping clocks, as indicated in the figure.
While r is at the high-state and correspondingly a is at
the low-state, switches controlled by the latter clock are ON,
and the others are OFF. Thus, the amplifier is shorted, and
hence its output voltage evolves toward a steady state xar
1
EOS(1 k1
defined by the intersection of the amplifier
S )
transfer characteristics and the bisecting line, as represented
in Fig. 4(d). Providing that the reset interval is long enough
for the transient to vanish, capacitor C is charged at a voltage vCr x xar. Note that for kS 1, xar EOS. Hence,
during the reset phase the negative plate of the capacitor
samples a voltage very close to the offset.
During the subsequent active time interval, r goes low,
a goes high, and C keeps its charge because the current flow
is blocked. Thus, the comparator input xa xa xa evolves
to a steady state xa EOS (x vCr) EOS xar (x
x) where the offset is substracted from its previous sample.
The following static resolution expression results:
S

|EOS |
E
|EOS |
go
+ OH =
+ EOH
1 + kS
kS
1 + gm /go
gm

(18)

which shows that the offset error is smaller by a factor 1

kS than for uncompensated comparators, see Eq. (5).
This procedure of dynamically sampling the central point
of an inverting transfer characteristic during reset intervals
and substracting it from the input during active intervals can
also be applied to single-ended amplifiers. Figure 4(e) shows
the CInvC circuit which yields

y k S x+ x +

E
1 + kS

(19)

where E is the intrinsic reference voltage of the single-ended

amplifier, given by Eq. (4). Although the underlying amplifier
is single-ended, dynamic biasing renders it capable of handing a differential input which may be of interest for practical
applications.
Residual Offset and Gain Degradation in Self-Biased Comparators. There are several second-order phenomena that modify
the voltage stored at node xa and consequently degrade the
static resolution of self-biased comparators. The most important among them take place during the ON OFF transition
of the reset feedback switch, namely feedthrough of the clock
signal that controls this switch and injection of its channel
charge. They make the voltage stored at note xa exhibit a
step during this transition so that its value in the active
phase differs from that stored during the reset phase, that is,
xaa xar xa. During the active phase this value also

continues degrading due to leakage current. Figure 4(f) is a

simplified model for evaluating all of these degradations. In
addition to the nominal capacitor C this model includes a parasitic capacitor between node xa and ground and another
parasitic capacitor between node xa and the feedback switch
control. Analysis using this model provides the following expression for static resolution:

|q | |I |
|EOS |
E
Cov
+ ch + leak t +
+ OH
C
C
C
1 + kS
C kS
|EOS |
E
|EOSd | +
+ OH
1 + kS
C kS

S |VCH + VCL|

(20)

where C C/(C Cov Ca), qch is the charge built in the

switch channel while it is ON during the reset phase, and t is
measured from the instant when the ON OFF transition
happens. This expression shows the residual offset EOSd that
is not attenuated by comparator gain. If capacitance C is chosen very small, this offset may become larger than the original offset. Small values of this capacitance also may result in
small values of C, thus increasing the incremental sensitivity
[last term in Eq. (20)], and hence producing additional resolution degradation.
Transient Behavior and Dynamic Resolution in Self-Biased Comparators. The calculations for amplification time apply to the
active phase of self-biased comparators and show the resolution for speed tradeoff in Eq. (10) already discussed. On the
other hand, the transients during the reset phase arise from
another tradeoff related to the onset of an additional residual
offset component. The dynamic behavior within the reset
phase can be calculated using the model of Fig. 3(b). Two different transients are observed. First of all there is a very fast
charge redistribution transient, dominated by the ON resistances of the switches. The output value y(0) at the end of
this transient, in the worst case, is equal to one of the saturation levels. Let us assume that y(0) EOH. From this value,
1
the output evolves toward the steady state at EOS(1 k1
S )
through a second transient which is dominated by comparator
dynamics. Figure 4(g) provides a global view of this second
transient. It consists of a nonlinear part, where the transconductor is in the saturation region and y evolves from y(0) to
m with a fixed slew-rate m / u, followed by a linear segment
where the evolution is realized with time constant ur (C
Ca Co)/(gm go) C/gm u. Thus, the reset time needed
to reach a final value larger than the steady state by xa is
given by
TR

EOH m
m
u + u ln
m
xa


(21)

xa remains as a residual offset after cancellation. For the

typical values of kS 2 103, u 10 ns, EOH 1 V and
m 250 mV, Eq. (21) yields TR 8.5 s for a 1 mV residual
offset. This time is smaller than the amplification time (TA
14 s) required to obtain D 1 mV from Eq. (10).
Offset Cancellation Through Storage at the Output Node.
Figure 4(c) employs offset storage at the comparator input
node. Alternatively, offset can be compensated for by storing
it at the output node. Such storage can be realized in either

COMPARATOR CIRCUITS

the voltage or the current domain. Figures 4(h) and (i) show
the corresponding circuits.
MULTISTEP VOLTAGE COMPARATORS
Static and Dynamic Gain
The resolution for speed tradeoff of one-step voltage comparators is improved by using a multistep architecture (18,19)
similar to the strategy used to enhance the voltage gain of
operational voltage amplifiers (20). Such a multistep architecture consists of the cascade connection of several one-step
stages. These stages are different in the more general case. A
structure typically found in practice is a differential one-step
comparator at the front-end and single-ended inverters in the
rest of the chain, as shown in Fig. 5(b) (21). However, for improved clarity in presenting the architectural principles, it
will be assumed that the cascade is formed of N identical
stages [see Fig. 5(a)], each having gain kS gm /go and time
constant o Co /go. Hence the static resolution is given by
S |EOS | + EOH

g N
o

gm

(22)

where EOS is the offset of the front-end stage at the cascade.

Equation (22) shows that for a large enough value of N, the
static resolution becomes basically constrained by offset voltage, that is, the constraint due to static gain becomes negligible. Such a feature is specially important when the amplifiers
are realized through inverters, such as InvC and CInvC,
which have inherently low dc gain.
For the dynamic resolution, assume as for the one-step
case that offsets are null, that all capacitors are discharged
at t 0, and that an input step of amplitude D is applied at
this instant. The output voltage Laplace transform is given
by
Y (s) =

kS
1 + so

N

D
s

(23)

Assuming that D(gm /go)N EOH, TA o, and hence Eq. (23)

simplifies Y(s) D /(sN1uN). From here the output waveform
and TA, respectively, are given by
y(t)

D 1 N
t
uN N!

E

OH

D

(24)

and the expressions for the dynamic resolution and the resolution for speed trade-off are

N
u

TA

and
D

T N
A

Nopt 1.1 ln

N!EOH

E 
OH

D

+ 0.79

(26)

For instance, for D (102 EOH), maximum speed is achieved

by using N 6. Using either less or more stages in the cascade yields slower operation.
Offset Cancellation in Multistep Comparators
Dynamic self-biasing can also be applied to cancel the offset
of multistage comparators. However, the high-order dynamics
preclude direct feedback connection of the overall output node
and the negative input. Unless compensation circuitry is
used, such direct feedback connection leads to instabilities,
similar to the problem found in two-stage op amps (7,20). Instabilities are avoided by making each stage store its own offset, as shown in Fig. 5(c). Thus, only residual offsetssee Eq.
(20)generated at the different stages remain. However,
they are also attenuated through proper timing of the
switches used for self-biasing. The inset of Fig. 5(c) shows this
timing. Note that the stages are switched ON at different instants, each one after the previous. Consequently, the residual offset of each stage is stored at the input capacitor of the
next stage while the latter remains grounded, and hence the
output remains unaltered. In this way only the residual offset
of the last stage EOSdN contributes to the output. Because this
offset is amplified only by the last stage itself, whereas the
signal is amplified by all of the stages, the following expression results for static resolution:
|EOSdN |
EOH
+
N1
(C kS )
(C kS )N

(27)

Overdrive Recovery and Delay Time

in Multistep Voltage Comparators

1/N
N!

D |EOS | + EOH N!

As for the one-step comparator [see Eq. (9)], Eq. (25) yields
TA u for the practical case where D EOH. However, because of the potential dependence on N, the multistep architecture yields smaller values of TA for any D such that D
(EOH /2). For instance, for u 10 ns, EOH 1 V and D 10
mV, Eq. (24) yields TA 141 ns for N 2, TA 65 ns for
N 5, and TA 67 ns for N 8, smaller in all cases than
for the one-step.
Figure 6(a) depicts TA / u as a function of D for different
values of N and EOH 1 V. Figure 6(b) is an enlargement of
the previous diagram. It shows that for each D there is an
optimum value of N that minimizes TA. For D (103 EOH)
this optimum number is given by (19),

and
TA u

587

(25)

Transient characterization of multistep comparators for CT

applications requires calculating delay and comparison times.
The worst case happens when the initial condition is such
that all stages are saturated due to an input overdrive applied and held for some instant t 0 and then an opposite
overdrive of amplitude D very close to the static resolution
limit is applied at t 0. Assume, as for the calculation of
comparison time in the one-step comparator, that y(0)
ESL. During the transient evolution toward the steady-state,
y() kSND, each stage remains saturated and hence latent,
while its input is smaller than ESL /kS. Figures 5(d) and 5(e)
show the transient waveforms for comparators with two and
three stages, respectively.

588

COMPARATOR CIRCUITS
+

k s, u

k s, u

+
y1

1st

y2

k s, u
+

k s, u

2nd

+
3rd

Nth
(a)

x+

i+

MNd

MNd

r0

MP1

MCP

MCP

MP

VBP

MP

VCP
y

MNB

x+

MP1

MCN

MCN

MN1

MN1

VCN

IB

MNB

MN

MN

r1

C
xa

y1

I+

r2

xa

y2

EOS

rN

I+

I+

EOS

EOS
(b)

r1

r2

r0

Tca
Tcr

rN
(c)
ESH

V02

EOH
V01

ESL/kS

ESL/kS

V02

V01

V03

ESL
T1

T2
(d)

T1

T2

T3
(e)

Figure 5. Multistep voltage comparators.

COMPARATOR CIRCUITS

Normalized amplification time Ta / u

Comparative performance of the

comparator architectures

Normalized amplification
time Ta / u

103

10

R = 1.0

N=1

N=2
101

100
101

N=5

R = 0.4

R = 0.2

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

10
N=2
9
8

N=3

7
6
N=5

N=6
N=4

4
3

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

Incremental dynamic sensitivity, V

Incremental dynamic sensitivity, V

(a)

(b)

xCM = 0.5
20
18
16
14
12
10
8
6

xCM = 0.0

xCM = 0.5
20
18
16
14
12
10
8

30
25

Wrong output

20
15
10
5
0.08 0.04

589

0
0.08 0.04

0.04 0.08

0.04 0.08

Wrong output

6
0.08 0.04

0.04 0.08

(c)
Figure 6. Illustrating the resolution-speed tradeoff for different voltage comparators.

Two-Stage Comparator. First consider the two-stage comparator whose waveforms are depicted in Fig. 5(d). The delay
time is that invested by the first stage in delivering the voltage ESL /kS. Because the transient at node y1 is the first-order
type, TD is mathematically expressed similarly to Eq. (12):

TD
= kS ln
u

ESL
k S D
E
1 + 2 SL
k S D
1+

(28)

From t TD, the second stage starts contributing to the voltage gain thus giving

1
y(t) = k2S D (ESL + k2S D ) 1 +
k S u


e

1
kS u

y(t) ESL +

(ESL + k2S D )
2

2

k S u

TC
T
D + kS
u
u

ESL + EOH
k2S D
2
E
1 + 2 SL
k S D

(29)

(30)

(31)

Because D S and taking into account Eqs. (2) and (22),

kS2 D EOH. Thus, by assuming that EOH ESL,
k
TD
kS ln S
u
2
and

where t TD. This equation is difficult to solve exactly.

However, for our purposes it can be approximated by the first
two terms of its power expansion:

1

The comparison time is the instant at which y(t) EOH:

k
TC
T
D + kS 2 kS ln S + 2
u
u
2

(32)

By comparing this TC with an optimistic estimation of the corresponding value for one-step architecture and assuming the
same overall static gain (A0 kS for one-step; A0 kS2 for twostep),

A0

TC |twostep
1
2 + ln
<1
=
(33)
TC |onestep
2
2 A




590

COMPARATOR CIRCUITS

It shows that the possibility of distributing the gain between

the two stages also gives faster operation in overdrive recovery.
Three-Stage Comparator. Now consider Fig. 5(e), corresponding to the three-stage comparator. The delay time now
has two components. The first TD1 is given by Eq. (28). The
second is the time needed for the second-stage output to
reach ESL /kS and is calculated by using Eqs. (29) and (30):

TD
T
T
= D1 + D2
u
u
u

ESL

1+ k 
S D
kS ln
+
ESL

1+ 2

k S D

E
ESL
3 SL
2
k D
k S D
2 S
ESL
1+ 2
k S D

(34)
From t TD the third stage starts working so that after a
power-series expansion,

(ESL + k3S D )

3!
k S u

 E +E

SL
OH


k3S D
TD

+ kS 
3!
E
u

3
1 + 3 SL
k S D

y(t) ESL +

3

TC
u

0No
nNo

and

This can be easily generalized to N stages:


N

ln(A0 ) 
m
+
m!
N
m=2

gm
gm 1
=

go gmo
go F

(37)

It shows that for the same static gain, equivalently, the same
static incremental sensitivity S EOH /A0, the comparison
time decreases with the number of stages, even in overdrive
recovery.

(38)

Let us consider that go gmo, and hence F 0. Equation (38)

shows that as gmo increases by approaching the go value, the
voltage gain also increases, thereby confirming the action of
positive feedback. Because the incremental static sensitivity
S is inversely proportional to the static gain, such an effect
could be exploited to improve the resolution of one-step comparators, with no additional stages needed. In the limit for
gmo go, kS , and hence S 0. On the other hand, Eq.
(10) shows that for u and D fixed, the speed of a one-step
comparator also increases with increasing kS. For instance,
with u 10 ns, EOH 1 V and D 1 mV, Eq. (10) yields
TA 47 s for kS 1010 and TA 10 s for kS 11000.
Figure 7(b) shows a circuit implementation of positive
feedback in one-step comparators. Figure 7(f) shows a CMOS
schematic for this implementation where
gmo =





TC
ln(A0 )
3
3
+ 2 + 3!
kS [ln(kS ) + 2 + 3!] = 3 A0
u
3
(36)

kS =

(35)

Under assumptions similar to those for two-stages, namely,

kS3 D EOH and EOH ESL, the following expression is obtained for the comparison time as a function of the overall
gain A0 kS3 :


TC
N A0
u

This is confirmed through analysis of Fig. 7(a). Assuming

that both transconductors and the resistor Go(y) operate inside their linear regions [see Fig. 3(b)] and defining F 1
(gmo /go),

I + IBo
go = B
2

W 
L

1
VANl

No

IBo

1
VAPl


(39)

Because of the positive feedback action, this circuit, as any

other including positive feedback, for instance, Fig. 7(g), is
very sensitive to random fluctuations of technological parameters, such as 0 in Eq. 39. Consequently, very small nominal
values of F should be avoided if this parameter must be kept
positive in the presence of such fluctuations. In practice it is
hard to guarantee robust operation with F 0.01. A robust
conservative value might be F 0.1, which reduces S by a
factor of 10 and improves the nominal speed by a factor
around 4.7not too much improvement. Actually, analysis of
Eq. (10) taking into account Eq. (38) shows that speed cannot
be improved any further despite the value of F. The following
section shows that much larger speed improvement is
achieved by allowing F to be negative, the counterpart being
degradation of resolution.

VOLTAGE COMPARATORS WITH POSITIVE FEEDBACK

One-Step Comparators with Global Positive

Feedback: The Onset of Hysteresis

Using Partial Positive Feedback to Enhance the Voltage Gain

Let us focus again on Fig. 7(a) and define F F

(gmo /go) 1. Consider F 0. This implies that gmo go and
hence that the amount of negative feedback exercised by go is
smaller than the positive feedback due to gmo. The global feedback is hence positive. This has two major consequences on
comparator behavior:

Consider the conceptual circuit of Fig. 7(a). In addition to the

conventional transconductor Gm(x) controlled by input voltage, this circuit contains another Gmo(y) controlled by output
voltage. The former injects a current proportional to x into
the output node, whereas the current injected by the latter is
a function of the output node voltage. Hence this new transconductor is acting as a resistor. Its current enters the node
for positive values of y which means that its incremental resistance is negative and, consequently, induces a positive
feedback action on the overall comparator operation.

The time constant for small-signal variations around y

0 is negative. Consequently, the transient evolution from
this point follows an exponentially increasing law. In
particular, assuming that y(0) 0 and that an input step

COMPARATOR CIRCUITS

ic
y
+
x

Ca
Gm(x)

Gmo( y)

Go( y)

+
y

gm

iC

(a)

gmo

(b)
3

iC

gmx

Gmo(x)
IBo

Slope go
ESL

ESL

mo

mo

ESH

g
Slope gm
o

1 0 1 2

3
ESH
H

ESH

ESL

Go(y)

3 2 1 0 1

Slope (gmo go)

Slope

MPI

MPI
MPo

MPI MPI
MNo

MNo
y

MNd

MNd

x+

MNd

MNd

y
x+

MNI
IBo

MNI

IBR

IB
IBR

(g)

(f)

gm 1
go F

(e)

(d)

(c)

( (

y
+

y
EOH

y(t)
H

1 /ks

t
H
x(t)

EOL
(h)
Figure 7. Using positive feedback in one-step comparators.

(i)

591

592

COMPARATOR CIRCUITS

of amplitude D is applied at t 0, the output waveform

is given by
y(t) = D

gm 1

go F

g
t F Co


(40)

This exponentially increasing law enables much faster

operation than for conventional one-step and multistep
comparators.
The large-signal comparator transfer characteristics are
multivalued. Hence, the comparator exhibits hysteresis
when operating in the CT mode with large-signal excitations.
Let us focus on the second feature. Graphical analysis of Fig.
7(a) using the models of Fig. 3(b) yields the characteristics
drawn in solid black in Fig. 7(c). It displays iC gmx as a
function of y, where iC is the current leaving the capacitor.
This figure shows that the capacitor sees a negative resistance around y 0the reason why the time constant
around this point is negative. The figure also shows that the
global characteristic seen by the capacitor is multivalued. To
better understand why this latter feature leads to hysteresis,
let us consider x changing, and draw a family of iC versus y
curves with x as parameter. Figure 7(d) shows such a family
and Fig. 7(e) shows the corresponding y versus x comparator
transfer characteristic. Assume that x is such that the capacitor sees the curve labeled 3 in Fig. 7(d). This curve intersects
the y axis only at y ESH. Hence this is the steady-state output as Fig. 7(e) shows. At the intersection points the current
through the capacitor is null and hence dy/dt 0. These
points are equilibrium states where y(t) cte and the circuit
may remain static (22). In practice the circuit actually remains static provided that the slope of the io versus y curve is
positive around the point (stable equilibrium) and is not otherwise (unstable equilibrium). Starting from any arbitrary
initial value of y, the circuit trajectory toward steady-state is
determined by the attraction exercised by stable equilibrium
points and the repulsion exercised by unstable equilibrium
points.
Now consider that x decreases such that the curve seen by
the capacitor changes sequentially from that labeled 2 to that
labeled 3. For x corresponding to curve 2, the circuit operates at the rightmost edge of the multivalued region:
H = mo

go

gm F

(41)

and yields y ESH. For smaller x and until the other edge is
reached, the circuit operates inside the multivalued region
where there are two valid solutions. However, the output voltage remains positive. The reason is that this voltage is stored
in the capacitor and the capacitor charge remains unchanged
because at steady-state iC 0. When x reaches the leftmost
edge of the hysteresis region, for x H, the capacitor sees
the curve 2, whose only valid solution is y ESL. Consequently, around this x value the output must jump from y
mo to y ESL. The dynamics of such a jump are dictated by
the slopes of the different segments of the characteristic seen
by the capacitor. First, the output evolves from y mo to y
mo with negative time constant (1
F Co)/go. Then,
from y mo to y ESL the evolution is with positive time

constant Co /go. Once on the bottom segment of the transfer characteristics, the output remains negative while the
edge x H is not surpassed.
Obviously, the incremental static sensitivity of hysteretic
comparators is inherently smaller than H. Hence the onset
of hysteresis implies degradation of resolution. However,
small hysteresis is useful to avoid glitches in those applications where signals are embedded in a noisy environment.
This is illustrated in Fig. 7(i), which shows that by defining
the edges of the hysteretic characteristic equal or slightly
greater than the amount of the largest expected noise amplitude, spurious glitches are avoided.
The circuits of Figs. 7(f) and 7(g) can be designed to have
hysteresis. Figure 7(h), where we assume 0 1, shows
another hysteretic circuit that uses a single one-step comparator and exploits the positive input terminal for positive
feedback. The figure also shows the cycle featured by the circuit, where the hysteresis region edges are set through proper
gain setting of the scaling block in the feedback path.
Discrete-Time Regenerative Comparators
The onset of hysteresis in positive-feedback comparators is a
consequence of capacitor memory. If comparators are made to
operate in discrete time and the memory is periodically eliminated through resetting, hysteresis disappears (in practice
some hysteresis remains because of second-order phenomena). As in any discrete-time (DT) comparator, a clock must
be used to control operation. In the clock-reset phase the comparator is disconnected from the inputs and driven to a central point. Then, in the comparison phase, the input is applied
and a transient evolution happens toward one of the saturated states. The qualitative issues for this behavior are illustrated in Fig. 8(a) for the circuit of Fig. 7(b). During the reset
phase the output is driven to the central point of Fig. 8(a),
P0, where y 0. During the comparison phase, for x 0, the
capacitor sees the bottom characteristics of Fig. 8(a) which
include three equilibrium points (see previous discussion of
intersection points): two stable, QL and QH, and the other unstable, Q0 (refer again to the previous discussion). Because
the capacitor charge cannot change instantaneously, the initial state is y 0 corresponding to P on the characteristic,
which is located on the right-hand side of Q0. From P the
repulsion action exercised by Q0, precludes reaching the lefthand stable equilibrium at QL, and the trajectory is attracted
toward the right-hand stable equilibrium at QH, where y
ESH. On the other hand, for x 0, the central point pushes
the trajectory toward the equilibrium at QL, where y ESL.
In both cases, dynamic evolution is realized with negative
time constants and hence at very high speed.
Except for the influence of second-order effects, the operation described is valid no matter how small the input signal
magnitude may be. Only the input sign is significant. It
means that DT positive feedback comparators can build infinitely large dynamic gaina feature not shared by one-step
or by multistep comparators whose maximum dynamic gain
is smaller than the static gain. This is confirmed by Eq. (40),
which shows that the output waveform is not bounded no
matter how small D may be.
DT positive-feedback comparators, usually called regenerative comparators, are commonly built by cross-coupling a pair
of inverters to form a latcha circuit structure often used as

COMPARATOR CIRCUITS

x<0
x

y+ y

xa

Q0
ESL

Q0

QH

P0

x>0

xa+ xa

QL

xa+

(b)

x>0
Q0

x+

MPB

(c)

MNS

a
MNS

xa+

MPB
y+

x<0

P+
(a)

QH

y+

ESH
QL

593

xa

xa+

y+

x+
xa

xa+

xa

y+

xa

xa+

y+

y
MNB
(d)

MNB

a
(e)

(f)
y+

xa+

gmin+ x+

g0+

gm+ y

Co+

(g)

xa

EOS
2

gm y+ +

EOS
2

Co

g0+

gmin x

(h)

x
x+

r
a1
r

i+ i

xa

a2

y+
MNd

x+
x+
x

a2

a1
r

xa+

MNd

x
y+

r
IB

r
MNB

a1
a2

MNB

(j)
(i)

r
xa

a1

(k)

x+
x

x
x+

a2

y+

a1
+

a2

C
C

xa+

Figure 8. Regenerative comparators.

xa+

xa

594

COMPARATOR CIRCUITS

a sense amplifier in dynamic RAMs (1). Figure 8(b) shows the

concept of a regenerative comparator based on a latch, where
the triangles in the feedback loop model delays in the transmission of voltages around the loop. [This is a very crude
model. Correct modelling requires a nonlinear vectorial differential equation of at least second-order that takes into account impedances at the different nodes. Then the dynamic
has to be analyzed in the phase space (22).] The inverters
amplify the differential input xa xa to obtain the saturated
differential output y y according to the characteristics
drawn in solid black in Fig. 8(c). During the reset phase, the
circuit is driven to the central state Q0. During the active
phase, the differential input is applied, forcing an initial state
either at the right, x 0, or at the left, x 0, of Q0. From
this initial state, the action of positive feedback forces the output to evolve either toward QH, for x 0, or toward QL, for
x 0, as illustrated by the gray line trajectories in Fig. 8(c).
Figures 8(d) to 8(g) show several CMOS latches reported
in the literature (2327). For Figures 8(d) and 8(e) during the
reset phase, transistors MNB and MPB are OFF so that the
latch is disabled. Hence, nodes xa and xa are at a high-impedance state and input voltages can be sampled at these
nodes. Transistors MNS in Fig. 8(d) are used for that purpose.
Then, the voltage difference is amplified when the latch becomes enabled during the active phase. Alternatively, the
nodes xa and xa are driven in the active phase with currents
obtained from the input voltages by transconductors, as illustrated in Fig. 8(k). This is the only excitation alternative for
Figs. 8(f) and 8(g).
The circuit of Fig. 8(h) is a small-signal, first-order model
of the latch behavior during the active phase. It corresponds
to the case where signals are applied through transconductors
and includes asymmetries between the two latch branches
and capacitive coupling between the two latch outputs. Such
coupling and asymmetries appear in practical circuits and are
responsible for significant errors observed in actual latch operation (28). The circuit of Fig. 8(h) captures the latch dynamic in the following state equations:

(Co+ + Cc )

dy+
= go+ y+ gm+ y + gm in+ x+
dt
E
dy
+ gm+ OS + Cc
2
dt

and

(Co + Cc )

dy
= gm y+ go y + gm in x
dt
E
dy+
gm OS + Cc
2
dt

(42)

First assume full symmetry, equal positive and negative parameters, EOS 0, and negligible capacitive coupling. Then,
the previous two equations can be substracted so that dynamics are represented by a single differential equation:

Co

d(y+ y )
= gm (y+ y ) go (y+ y ) + gm in (x+ x )
dt
(43)

The first term on the right-hand side of this equation represents positive feedback, the second negative feedback, and the
last the input. Assume (gm /go) 1. Then, assuming that the

circuit is initialized at t 0 such that y(0) y(0) y(0) and

that a differential input step of amplitude D x x is
applied at this instant, the differential output waveform can
be approximated as
y(t) y+ (t) y (t) D

gm in
gm

g
t Cm

D

gm in
gm

e u

(44)

A similar equation is found for those cases where the latch is

driven during the reset phase by establishing a voltage unbalance y(0) y(0) y(0) D. Then y(t) Det/ u. From Eq.
(44) the following expression is found for the resolution for
speed tradeoff:

D

T 
A

 EOH



D
EOH

 
ln

EOH gm
D gm in


(45)

Figure 6(a), where R gm /gmin compares this tradeoff to that

given by Eq. (25) for multistep comparators. It shows that, as
already anticipated, regenerative comparators feature faster
operating speed despite the value of N.
Asymmetries in DT Regenerative Comparators:
Mixed Comparator Architectures
Spurious differential signals, coupling between the two latch
branches, and mismatches between their parameters preclude correct amplification of small D values. Their influence
can be assessed by studying the equilibrium points of Eq.
(42), their eigenvalues, and their eigenvectors (22) which are
out of this articles scope. On the other hand, the influence of
spurious random signals is a much harder problem.
Note from Eq. (42) that the influence of offset EOS between
two branches is similar to that observed in one-step and
multistep comparators, that is, D EOS. It can be attenuated
through separate self-biasing of the two latch branches. The
circuit of Fig. 8(i) employs this strategy (29). Larger offset
attenuation is achieved by using capacitors, instead of just
wires, in the latch coupling branches of this circuit.
However, dissymmetries between transconductances gm
and gm and between the capacitors Co and Co produce much
larger errors for regenerative comparators than for one-step
and multistep comparators. The amount of error depends on
the input signal common mode xCM, as Fig. 6(c) illustrates.
This figure shows the outcome of simulations realized using
Eq. (42) with realistic transconductance mismatches of 10%
and capacitive coupling of 30%. For zero common mode the
figure does not anticipate limitations on D. On the other
hand, as the common mode increases to half of the swing
range, D has to be larger than 30 mV for correct codification of the input signal polarity. This value increases up to
50 mV if 10% mismatches are considered for transconductances and capacitances. It imposes a strong constraint on
comparator resolution, not shared by either one-step or
multistep comparators.
This problem of regenerative comparators is overcome by
placing a preamplifier in front of the regenerative core. This
is actually the role played by transconductances gmin in Fig.
8(h), and resolution improvement is roughly proportional to
the ratio gmin /gm. Figure 8(j) shows an actual CMOS circuit
implementation of this concept (25). Alternatively, if the latch
is driven through voltages, a mixed comparator architecture

COMPARATOR CIRCUITS

595

consisting of the cascade of a self-biased one-step comparator

and a self-biased latch can be used. Larger accuracy is
achieved by making the latter a fully differential type, as
shown in Fig. 8(k) (18,29).

example of a practical current comparator belonging to the

former class (31), and Fig. 9(d) shows a corresponding example for the latter (32). These two classes display quite different properties for dynamic resolution D.

BASIC CURRENT COMPARATORS

About the Resolution of Resistive-Input and

Capacitive-Input Current Comparators

Building Current Comparators from Voltage Comparators

As defined in the first Section, current comparators are used
to map the difference between two analog currents x(t) and
x(t) onto a digital voltage y, so that the state of the latter
codifies the sign of the former. The larger the transimpedance
gain kS, the smaller the incremental static sensitivity parameter S, and the more sensitive the comparator under dc excitation. Hence, the process of current comparator synthesis consists essentially of finding circuit structures to obtain the
largest possible kS. One obvious architecture uses a large resistor for current-to-voltage conversion and a buffer for output
voltage isolation [shown at the conceptual level in Fig. 9(a)].
Thus, the transimpedance gain is contributed only by the resistor. For greater design flexibility, the buffer is replaced by
a voltage comparator that also contributes to kS. The frontend current-sensing device can also be replaced by a more
general reactive impedance Za(s) (30), thus leading to the conceptual architecture of Fig. 9(b).
For design purposes it is worth considering two extreme
cases for the architecture of Fig. 9(b), one where the sensing
device is dominated by the resistive component and one where
the capacitive component is dominant. Figure 9(c) shows an

Buffer

Obviously, the resolution of Fig. 9(b) depends on the sensing

device and on the voltage comparator structure. For comparison, consider the simplest case where the latter is realized
through a one-step architecture with dc gain gmRb and unitary
time constant u Cb /gm as shown at the conceptual level in
Fig. 9(e). Assume, as shown in Fig. 9(e), that an overdrive
current step of magnitude D is applied at t 0 and that the
circuit is at its central point before applying the step. Routine
analysis obtains the following expression for the output voltage waveform:

y(t) = gm Ra Rb D

x(t)

R = ks
x+(t)

x(t)

Ca

Ra

b
0
1
et/ a
et/ b
a b
b a

t>0
(46)

where a RaCa and b RbCb. From here the amplification

time TA and the incremental dynamic sensitivity D are calculated by using Eq. (3).
Consider the resistive-input case first. It yields Ra Rb
and Ca Cb. The resistance Ra and capacitance Ca in the input stage of Fig. 9(e) model the parallel combination of the
nominal sensing elements and the parasitics from the driving
and amplifying stages. This means that in an optimum de-

Za(s)
x+(t)

ya

(a)
(b)

x(t)

x(t)

(d)
(c)

D
0
x+(t)

x(t)

Za(s)
t=0
Ra

Ca

+
ya

Rb

Cb

gm ya

(e)

Figure 9. Basic current comparator architectures and exemplary CMOS implementations.

596

COMPARATOR CIRCUITS

sign Ca is of the same order of magnitude as Cb and that the

maximum attainable Ra value is limited by the devices early
voltage, similar to what occurs for Rb. Therefore the time constant of the input stage is much lower than that of the output
stage. Taking this into account and assuming t b, Eq. (46)
is simplified to obtain
D

RI

1 Cb EOH
u EOH
=
TA gm Ra RI
TA Ra RI

(47)

which shows a direct dependence with the unitary time constant of the voltage comparator and an inverse dependence
with TA, similar to that observed for one-step voltage comparators.
Now consider the capacitive-input case. The input node of
this structure is the high-impedance type and hence, a and
b are of the same order of magnitude. Taking this into account and assuming t b, the dynamic resolution is calculated by making a Taylor expansion of Eq. (46) and keeping
the linear and the quadratic terms:
D

CI

E
1 C

= 2 2 b (Ca Ra CI ) OH
TA gm
Ra CI

u a CI EOH
2
TA2 Ra CI

(48)

where DCI is directly proportional to the unitary time constants of the voltage comparator and the current sensing
front-end and inversely proportional to the square of the amplification time.
Comparative analysis of Eqs. (47) and (48) shows a different accuracy for speed tradeoff for each current comparator
architecture. The two architectures feature the same speed
(i.e., the same amplification time) for the following value of
the dynamic resolution parameter:

1 u EOH Ra CI
D
2 a CI Ra RI Ra RI

(49)

Analysis of Eq. (49) using a feasible set of parameter values,

namely u 108 s, aCI 107 s, EOH 1 V, RaRI 105 , and
RaCI 106 , yields *D 5 A. For D *D and because DCI
T2
A , capacitive-input architecture yields smaller TA than resistive-input, where DRI T1
A . This means that capacitiveinput architecture is faster for applications involving small
input currents.
The advantages of capacitive-input for small currents are
confirmed by calculating the static sensitivity S and the offset EOS. The former is inversely proportional to the dc transimpedance, given as the product of Ra and the dc voltage comparator gain. Thus,
S =

1 EOH + EOL
2 g m Ra Rb

(50)

On the other hand, the offset has two components: the input
current offset of the sensing device and the input offset of the
voltage comparator attenuated by Ra. Thus,

Hence, the static resolution parameter is given by

1
Rc

S |EOS | + S = |EOSa | +

|EOSb| +

EOH + EOL
2gm Rb


(52)

where the larger Ra, the smaller S. Actually, for ideal capacitive input, where RaCI , Eq. (52) yields S EOSa. Then,
any input current x(t) such that x(t) EOSa, no matter how
small x(t) EOSa may be, is integrated by the input capacitor forcing the input of the voltage comparator to evolve so
that the sign of the input current is correctly coded.
Now consider applications involving large currents. Analysis of Eq. (47)(49) shows that the resistive-input architecture
is faster whenever D *D . Also, because the voltage variations at the input node ya x Ra are smaller for resistiveinput comparators, this structure can be expected to exhibit
smaller interstage loading errors and to perform better under
overdrive excitations.
Multistep Current Comparators
Multistep current comparators are implemented by cascading
a current-sensing device to perform current-to-voltage conversion, followed by a multistep voltage comparator. Analysis of
such a structure yields the following expressions for amplification time:

TA  u

!1/N

EOH
N!
D Ra RI

for resistive input

RI

and

TA u

a CI EOH (N + 1)!
 D u
Ra CI

!1/(N+1)
for capacitive input

CI

(53)

Both architectures feature the same speed (i.e., the same amplification time) for the following value of the dynamic resolution parameter:

D

N!

(N + 1)N

EOH
Ra RI

R

a CI

Ra RI

u
a CI

N

(54)

Analysis of Eq. (54) using a feasible set of parameter values,

namely, u 108 s, aCI 107 s, EOH 1 V, RaRI 105 ,
RaCI 106 , and N 2 results in *D 2.2 A which is lower
than the dynamic resolution term obtained for the one-step
current comparator for the same parameters.
ADVANCED CURRENT COMPARATORS
The previous section shows that resistive-input and capacitive-input comparators are complementary architectures.
This section presents improved architectures that combine
the advantages of these two basic schemes, namely, large sensitivity and reduced amplification time for low-current levels
and reduced input voltage excursion for large current levels.
Current Comparators with Nonlinear Current Sensing

|E |
|EOS | = |EOSa| + OSb
Ra

(51)

Figure 10(a) shows the conceptual block diagram of a current

comparator where the linear resistor Ra of Fig. 9(b) is re-

COMPARATOR CIRCUITS

597

Slope 1/Ra*
xR

x+(t)

Ra

x(t)

xR

ya

Slope 1/Ra
L

Ca

(0,0) H

ya

(a)

x(t)

(b)

xR

P2

JH

ya

x(t)

xP

P1

JL

xN
A

MP
MN

(c)

MP
x(t)

xN

(d)

MP

x(t)

xP

MN

MN
(e)

Figure 10. Current comparator with nonlinear current sensing.

(f)

placed by a nonlinear resistor a with the driving-point characteristics of Fig. 10(b). This characteristic has three segments. In the inner one, for low currents, the equivalent
resistance Ra is very large, and the circuit behaves as a capacitive-input architecture. On the other hand, for large currents, the equivalent resistance R*a is much smaller and the
circuit behaves as a resistive-input one.
To calculate the incremental dynamic sensitivity, consider
that the voltage comparator has one-step architecture, similar
to Fig. 9(e). Following the application of a current step of amplitude D, the input voltage evolves quasi-linearly with time
while in the inner segment of the nonlinear resistor and remains quasi-constant otherwise. Correspondingly, the output
voltage evolves quadratically with time during the first part
of the transient and linearly afterward. To keep the speed
advantages of capacitive-input architecture, the restoring
logic level EOH should be reached during the first part of the
transient, that is, such that,
ya (TA )

TA
 Ra < H
a D

and
y(TA ) = EOH

1 TA2
 Ra
2 u a D

(55)

where it is assumed that a RaCa b RbCb and *a

R*a Ca b RbCb. This results in the following design constraint:
2
H
a
> 2D EOH
Ra u

(56)

where the incremental dynamic sensitivity is given by Eq.

(48). On the other hand, the formula for the static resolution
parameter [Eq. (52)] remains valid.
In the more general case of an excitation between two overdrive levels JL and JH, the dynamic evolution of the input
node also includes points in the outer segments of the nonlinear resistor [see the dynamic route of Fig. 10(c)], and calculating the output waveform is not direct. However, neglecting
delays in the devices used to realize the nonlinear resistor,
the response time will be a monotonic function of the time
invested for the input voltage to change from L to H.
Hence,


Ca
TC = f
( + L )
(57)
JH H
where the exact functional relationship depends on the actual
voltage comparator used.
Figures 10(d) and 10(e) show simple CMOS nonlinear resistor realizations. Both yield L VTP and H VTN. This
results in a rather large dead zone around 2V, and hence Eq.

598

COMPARATOR CIRCUITS

(57) anticipates rather poor response time. In the case of Fig.

10(e), the dead zone length can be reduced by biasing the
gates of MN and MP with different voltages, namely, VGN
VTN L and VGP VTP H. This can be done with the
circuit of Fig. 10(f), which consists of two stacked complementary, first-generation current conveyors as originally proposed
by Smith and Sedra (33). The circuit is similar to the class
AB current amplifier proposed in Ref. (34) (see also Ref. 35
for an improved version). In any case, H and L should be
large enough to guarantee that the central region of the driving-point characteristics matches that of the voltage comparator under global and local statistical variations of the technological parameters. Such a large central region length may
induce significant loading errors in operating the stage used

to drive the comparator (30). Besides, the aspect ratios of MN

and MP must be large enough to reduce R*a .
Current Comparators with Nonlinear Feedback
Figure 11(a) shows an improved architecture that reduces the
central region length. Contrary to Fig. 10(a), the voltage-mode
comparator of Fig. 11(a) does not operate in open loop but
uses the nonlinear resistor for negative feedback. There are
three different operating regions that correspond to the three
segments of the nonlinear resistor characteristic depicted in
Fig. 10(b). For small changes around the quiescent point
(x x 0), the equivalent resistance of the feedback resistor is large, the voltage amplifier operates practically in open

Ra

Ra
A

+
x+(t)

Ca ya

x(t)

B
+
y

E
(a)

Slope

Ra

( (
1 + A0

Slope

Ra
L

( (
1 + A0

xN

MN

Ra

x(t)

xp
MP

(b)

(c)

IB
MP
xN

MP
+

E
x(t)

xN
y

+
y

x(t)

xp

xp

MN

MN
(d)
IB
Figure 11. Current-mode comparator using nonlinear feedback.

(e)

COMPARATOR CIRCUITS

loop, and the circuit preserves the capacitive-input feature

(the comparator input is the high-impedance type). For x
x, voltage ya is pulled up and the amplifier decreases y. Thus,
the resistor enters in the rightmost segment of the characteristic, allowing the input voltage to reach a bounded steadystate (the input of the comparator is a low-impedance node).
A dual situation occurs for x x, where ya is pulled down
and y is high. Consequently, the comparator sees the characteristics of Fig. 11(b), where, when E 0,
L =

L
1 + A0

H =

H
1 + A0

and
(58)

where A0 denotes the amplifier gain and L and H are the

nonlinear resistor breakpoints. Note that the central region
length reduces as the amplifier gain increases. A negative
consequence of feedback is that the output signal becomes
clamped at L and H, respectively. Hence, it may be necessary to cascade an additional voltage comparator to restore
the logic level.
Figures 11(c) and 11(d) show practical CMOS realizations
of the nonlinear feedback current comparator. A common feature of these circuits is that the transition region of the nonlinear resistor tracks by construction that of the voltage amplifier, which means that the operation is insensitive to
mismatches and hence permits using minimum size transistors. This is important because minimum transistors mean
minimum parasitic capacitances and hence reduced response
times.
In the case in Fig. 11(c), simple CInvC or InvC structures
can be used for the voltage comparator, thus leading to very
compact realizations. However, this structure has the drawback that the transient behavior is largely dominated by the
overlapping capacitance Cf which connects input and output
terminals of the voltage amplifier. Analysis obtains the following expression for comparison time (30):
TC

A0
C
(V + |VTP |) f
1 + A0 TN
JH

(59)

which implies that, although the high-resolution properties of

the capacitive-input architecture remain, the quadratic response feature is lost due to the Miller effect created around
Cf , significant even for minimum size feedback transistors.
The circuit of Fig. 11(d), called a current steering comparator, circumvents this problem by decoupling the amplifier input and output nodes. Its static operation follows principles
similar to those used in the circuit of Fig. 11(c). When x(t)
0, transistors MP and MN are OFF and the circuit realizes
capacitive-input behavior. Positive currents integrate in the
input capacitor increasing the node voltage and consequently
decreasing y until the transistor MN becomes conductive, absorbing the input current and stabilizing the output. The
same occurs for negative currents, where MP is the conductive
transistor. For transient behavior, analysis shows, that under

599

the same assumptions as for the circuit of Fig. 11(a), the response time is given by (36),
TC

2 C
u

JH

(VTN + |VTP |)

(60)

where u is the unitary time constant of the voltage comparator and Cs is the input capacitance.
To conclude this section, Fig. 11(e) shows a circuit similar
to Fig. 11(c) where transistors MP and MN are swapped and
the feedback is positive, instead of negative. It operates as a
CMOS current Schmitt trigger where the positive and negative threshold values of the hysteretic characteristic are defined by the lower and upper current sources, respectively.
APPENDIX I. SIMPLIFIED MOST MODEL
MOS transistors exhibit different operation depending on the
current and voltage levels. Throughout this article we considered only the MOST model under strong channel inversion,
and described its first-order behavior using a model with four
parameters, namely, zero-bias threshold voltage VT0, the slope
factor n, the intrinsic transconductance density 0, and the
equivalent Early voltage VA (37). Two subregions are considered within strong inversion:
Triode (or ohmic) region. In this regime, the source and
drain voltages VS and VD remain below Vp (VG
VT0)/n, where VG is the gate voltage (all voltages are referred to the local substrate). The drain current takes the
form
ID = 20


n
W 
VG VT 0 (VD + VS ) (VD VS )
L
2

(61)

where W/L is the aspect ratio of the transistor.

Saturation region. Assuming forward operation, this regime is reached when VS Vp VD and the drain current
is given by
ID = N (VG VT0 nVS )2

1+

VD Vp
VA

(62)

where

0 W
n L

ACKNOWLEDGMENT
This work has been partially supported by Spanish C.I.C.Y.T.
Project TIC96-1392-C02-02 (SIVA).
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ANGEL RODRIGUEZ-VAZQUEZ
MANUEL DELGADO-RESTITUTO
JOSE M. DE LA ROSA
Institute of Microelectronics of
Seville

RAFAEL DOMINGUEZ-CASTRO
University of Seville

402

COUNTING CIRCUITS

C1
I1

C2
T

C3
T

Figure 1. Simple binary counter. A three-bit counter will count from

0 to 7.

ond or the frequency of the signal. In typical simple meters,

this value is converted from its binary form stored in the
counter circuit to a binary coded decimal form used to drive a
set of light-emitting diode (LED) displays.
Digital counters are generally based on a series of binary
storage elements called flip-flops. A flip-flop element stores
either a binary 0 or 1. By logically connecting a set of flipflops, it is possible to represent related binary digits and thus
represent numbers.
An elementary binary counter can be constructed by connecting a set of T flip-flops as shown in Fig. 1. Each T flipflop changes the state of its output Q from 0 to 1 or vice versa
every time the T input changes from 1 to 0. The output waveform produced at each stage output C1 through C3 is shown
in Fig. 2. Output C1 represents the lowest-order binary digit
(called a bit), while C3 is the highest-order bit. By examining
the waveform, it can be seen that before the first 1 to 0 transition on the input I1 signal, the outputs represent the binary
value 000. After the first 1 to 0 transition on input I1, the
outputs represent the value 001. The second 1 to 0 transition
on I1 causes a 010, or binary 2, to be output by the counter.
Counting continues until the value 111 is reached. Once this
maximum counter value of 7 is reached, the next 1 to 0 transition on input I1 causes the outputs to change to 000 and the
counter begins counting up again.
Each successive stage of the counter in Fig. 1 changes
state, or counts, every second time the preceding flip-flop
changes state. The frequency of the waveform produced at
any output is half the frequency of the stage input. Each stage
is said to be a divide-by-two counter, and the overall effect of
the three-stage counter is to produce an output waveform that
has the frequency of the input waveform divided by eight. An
N-stage counter divides the frequency of the input waveform
by 2N. The binary values actually stored in an N-bit counter
actually range between 0 and 2N1.

COUNTING CIRCUITS
Counting circuits are found in a wide variety of electronic instrumentation and general digital computing systems. These
circuits are used to count events, to accumulate sums, to hold
pointers to memory instructions and data, and to perform
other similar functions which require iterative computations.
The term counter is most commonly used to refer to circuits
that perform counting functions and, more specifically, to
binary counters used in digital or hybrid digital/analog
systems.
An example of the use of a counting circuit can be seen in
a simple frequency meter. The input waveform is sampled
over a fixed interval. A counter is used to add up the number
of times that the signal increases above a certain threshold
voltage. If the sample interval is 1 s and the waveform is
sinusoidal, the counter contains the number of cycles per sec-

1
I1

C1
C2
C3
Figure 2. Binary counter output waveforms. The inherent delay in
each flip-flop stage delays the transition of the next higher-order
stage. In the worst case situation, the output of the highest-order
stage will be delayed by an amount proportional to the number of
stages.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

COUNTING CIRCUITS

403

Up
C1

C2

And

Q
I1

C3

And

Or

Q*

Or

Q*

Q*

And

And

Dn
Figure 3. Three-bit up/down counter. Signals Up and Dn must remain constant during
counting.

The specific interconnection of the feed-forward or feedback signals within a counter determine its counting characteristics. The counter shown in Fig. 3 is a 3-bit up/down
counter. Each time the I1 input line transitions from 1 to 0,
the counter changes states. When the input UP is a 1, the
counter counts up; when DN is a 1, the counter counts down.
Only one of the two inputs UP or DN may be at logic 1 any
particular time.
The counters shown in Figs. 1 and 3 are both said to be
asynchronous counters since each of the flip-flops in the
counters operates independent of a central clock. In fact, this
type of counter is generally referred to as a ripple counter,
indicating that the change of state of the overall counter actually transitions through the counter stage by stage rather
than having all flip-flops change state simultaneously. This
ripple effect can cause difficulties in systems that are meant
to be operated synchronously. For example, as the 3-bit ripple
counter transitions from state 111 to state 000, there is an
inherent delay of signals passing from one stage to the next.
The actual output signals transition from 111 to 110 to 100
and finally to 000. Although the intermediate values of 110
and 100 only last for a very short time, their appearance can
cause problems. For example, if a logic circuit is monitoring
the counter output for the state 110, a false signal will be
incorrectly generated for a short duration when the counter
transitions from 111 to 000.
For a ripple counter, the amount of delay involved in transitioning from one correct state to the next correct state is
dependent upon the delay of the individual flip-flops. Assume
that a T flip-flop exhibits a one-unit delay before a change in
the input signal effect the output signal. A 3-bit ripple
counter presents its worst-case delay behavior when the state
of the counter changes from 111 to 000 (or vice versa when
counting down). This worst-case delay amounts to a threeunit delay. Although this may seem insignificant, when a
more typical counter like a 16- or 32-bit counter is considered,
the cumulative delay of 16 or 32 units can become very significant.

C1

Count
Clk

T
C

A mechanism to relieve this potential error condition is to

design all of the counter flip-flops to be simultaneously triggered by the same clock. That is, the outputs of all flip-flops
are directed to change at the same time under the control of
a single clock signal. This type of counter is called a synchronous counter.
An example of a synchronous 3-bit binary counter is shown
in Fig. 4. The T flip-flops in this circuit change state if the T
input is 1 when the clock input C changes from a 1 to a 0.
The circuit counts input CLK pulses whenever the input
COUNT is 1. All outputs of this counter change in synchronization with the clock signal CLK. The disadvantage of this
type of counter is the additional logic gates that must be included in the circuit. For an N-bit counter, each subsequent
stage N requires an additional logic gate which must have
N 1 inputs.
The timing waveform for the synchronous counter of Fig.
4 is shown in Fig. 5. Notice that this waveform looks very
similar to that shown in Fig. 2. The difference is the lack of
ripple delay at each of the individual stage transitions.
Other variations on the basic counter scheme are found in
a wide variety of applications. Counters that are capable of
loading arbitrary starting values are typically used to keep
track of the sequence of instructions being executed in a digital computer. The ability to load a new starting value allows
the programmer to cause branching within a sequence of instructions. Some counters are configured to have arbitrary reset or terminal count values. This type of counter contains
external logic that loads a new starting value once a certain
termination count has been reached. Counters of this type are
called modulo-x counters, where x is the value representing
the terminal count. An example of this type of counter is one
which counts from 000 to 101, returns back to 000, and starts
counting again. The ability to reset a counter after a fixed
count sequence is quite handy when nonprogrammable hardware is being used.
Counters are also frequently used to apply test vectors to
a digital circuit. A counter is loaded with an initial count, and

C2

T
C

C3

And

T
C

Figure 4. Synchronous binary counter.

More logic gates are needed than in the
ripple counter.

404

CRITICAL PATH ANALYSIS

I1
C1
C2
C3
Figure 5. Synchronous 3-bit counter output waveforms. All outputs
change together after a short flip-flop delay.

a prescribed count sequence applies counter outputs to the

inputs to combinational circuits. The response of the combinational circuit is monitored to determine if errors exist in the
behavior of the circuit. In this situation the counter is not
part of the operational circuit but is rather an ancilliary device which only comes into play during the circuit testing procedure. This type of counter must be designed and built to be
highly reliable since it becomes the key link in the testing
chain of an operational circuit.
Implementation of a counter is no different from the implementation of any other logic circuit. Good very large scale integration (VLSI) design practices dictate that the clocked
components (the flip-flops) be physically as close as possible
in order to minimize timing anomalies.
BIBLIOGRAPHY
W. I. Fletcher, An Engineering Approach to Digital Design, Englewood
Cliffs, NJ: Prentice-Hall, 1980.
R. J. Feugate, Jr. and S. M. McIntyre, Introduction to VLSI Testing,
Englewood Cliffs, NJ: Prentice-Hall, 1988.
R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Techniques
for Analog and Digital Circuits, New York: McGraw-Hill, 1990.
F. J. Hill and G. R. Peterson, Introduction to Switching Theory and
Logical Design, 3rd ed., New York: Wiley, 1981.
E. J. McCluskey, Logic Design Principles with Emphasis on Testable
Semicustom Circuits, Englewood Cliffs, NJ: Prentice-Hall, 1986.
D. A. Pucknell, Fundamentals of Digital Logic Design with VLSI Circuit Applications, Englewood Cliffs, NJ: Prentice-Hall, 1990.
N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A
Systems Perspective, Reading, MA: Addison-Wesley, 1985.

JOSEPH G. TRONT
Virginia Polytechnic Institute and
State University

COUPLERS. See DIRECTIONAL COUPLERS.

COUPLING MEASURES. See SOFTWARE QUALITY.
COVERAGE, INSURANCE. See INSURANCE.
CPM. See MINIMUM SHIFT KEYING.
CRITICAL CURRENT, SUPERCONDUCTING. See
SUPERCONDUCTING CRITICAL CURRENT.

434

CURRENT CONVEYORS

iY
vX
iZ

vY
iX
vZ

0 0 0
1 0 0
0 1 0

Drain
iD

Gate

vY

iZ
Y
Z

CCII
X

vG

iS

iX

Source
Figure 2. Comparison of a CCII and an ideal field effect transistor.

CURRENT CONVEYORS
A current conveyor is an active circuit used to carry out analog signal processing functions for many different types of applications. In general, this device has two inputs and n outputs; however, most applications involve a current conveyor
with two inputs and one output port, as illustrated in Fig. 1
(1). The current conveyor can be thought of as a basic design
building block much like an operational amplifier. During
work on his masters thesis in 1966, Adel Sedra was developing a voltage-controlled waveform generator to be used as
part of a design of a programmable instrument for incorporation in a system for computer controlled experiments, when
he happened upon a novel circuit (2). He generalized the concept and developed the current conveyor, a circuit that conveys
current from one port to another. His original design, now
called a first-generation current conveyor (CCI) is a three-port
device (with ports defined as X, Y, and Z) described by the
following hybrid matrix:

i 
0
Y

vX
iZ

1
0

1
0
1


v 

0
0
0

iX
vZ

(1)

This circuit exhibited a virtual short circuit at node X, a virtual open circuit at node Y, and the current supplied at X was

Iy
Vy

Iz

Y
Z

Vx

X
(a)
I z+
Z 1+

Vy

Vx

.
.

Z N+
ZN+1

.
.

Ix

.
.
.
.

Z M
(b)

V z+

Iz+ = Iz = Ix

V z+
N
V z

N+1

V z

i 
0
Y

vX
iZ

1
0

0
0
1


v 

0
0
0

iX
vZ

(2)

The current supplied to node X has either a positive or negative polarity resulting in the CCII or CCII, respectively.
The CCII can be thought of as an ideal field effect transistor
(FET) where the gate node Y, drain node Z, and source
node X. This relationship is illustrated in Fig. 2. Traditionally, the current conveyor has been implemented using lowfrequency bipolar transistors, FETs, or operational amplifiers
(35). Two particular applications of the current conveyor are
active network synthesis and analog signal processing. Table
1 (6) illustrates several networks useful in active network
synthesis. These circuit topologies are by no means the only
way to implement these functions.
An important application is analog signal processing. Table 2 (6) illustrates the use of current conveyors to carry out
five different signal-processing functions. For purposes of
analysis, it is much easier to relate the current conveyor to
two ideal one-port networks known as norators and nullators.
NULLATORNORATOR CIRCUIT ANALYSIS AND ITS
APPLICATION TO CURRENT CONVEYOR DESIGN

Vz

Ix

Iy

conveyed to Z. Node Z had a very high impedance. Applications of the CCI included current meters and negative impedance converters (NICs). To increase the versatility of the current conveyor, a second-generation current conveyor (CCII)
was introduced (2). This design was the same as the previous
except that no current flowed through node Y. This design
was introduced in 1968 and is described by the following hybrid matrix:

I z

Figure 1. Current conveyor schematic definitions: (a) basic current

conveyor and (b) multiple output current conveyor. 1996 IEEE.

There is good reason to discuss the design of current conveyor

circuits using nullatornorator design techniques. One of the
strongest motivations is that numerous papers and texts have
been written that address circuit synthesis using these ideal
circuit elements (711). As a result, the use of this technique
provides the designer with a wealth of information on designing many types of active networks including negative impedance converters, negative impedance inverters, positive impedance inverters, and a myriad of other useful active
networks. All that is required to use this information is a basic understanding of circuit analysis using the norator
nullator approach and an understanding of how to convert
noratornullator topologies into current conveyor topologies.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

CURRENT CONVEYORS

435

Table 1. Application of Current Conveyors to Active Network Synthesis

Characterization
1
2
i1
i2
2-Port
Realized

Voltage
controlled
Voltage
source

v1

v2

Current
controlled
Current
source

CCII
+

g
Y=

0 0
g 0

0 0
H= 1 0

Z=

INIC

0 0
R 0

Y=

CCII
+

R
2

CCII
+
1
g1

g2
NIV

CCI
+

0 1
G=
1 0
1

0 g1
g2 0

CCII
+

CCII
+
2

1
g

Gyrator

Y=

0
g

g
0

g
CCII
+

CCII

2
CCII

2
5

CCII

CCII
+

Current
controlled
Voltage
source

0 0
G= 1
0

Voltage
controlled
Voltage
source

Realization Using Current Conveyors

x
z
CC
y

1970 IEEE.

When analyzing active linear networks, several distinct

types of circuit elements are used. These include resistors,
capacitors, inductors, transmission lines, independent voltage
sources, independent current sources, dependent voltage
sources, and dependent voltage sources. The dependent voltage and current sources tend to be two-port networks that
associate a voltage or current from one port to a voltage or
current to the second port. Although analyzing circuits containing these two-port networks is relatively straightforward,
the simultaneous solution of equations that usually results
from such analysis serves to reduce the designers intuition
about the circuit. The use of two ideal one-port network representations known as nullators and norators can help to restore some of this lost intuition. Nullators and norators can
replace all dependent voltage and current sources in a network so as to reduce the primitive elements in a linear network to only one-port networks. This is a very powerful tech-

nique that can be used to gain insight into active network

synthesis (79). The properties of the nullator and norator
will now be introduced.
Definition 1. A nullator is a one port network with v1(t)
i1(t) 0 defining the the voltage and current on its one port
(9).
Definition 2. A norator is a one port network with v1(t)
A1(t) and i1(t) A2(t) defining the voltage and current on its
one port. The functions A1(t) and A2(t) are arbitrary, and thus
v1(t) and i1(t) are unconstrained resulting in a degree of freedom not found in any other one port network (9).
The schematic symbol used to describe the nullator and
norator are shown in Fig. 3. When carrying out nodal circuit
analysis of a circuit that has nullators and norators, Defini-

436

CURRENT CONVEYORS

Table 2. Application of Current Conveyors to Analog

Signal Processing
Realization Using Current Conveyor
x
z
CC
y

Functional
Element

Function
R2

Current
amplifier

R1

I0 = (R1/R2)II

CCII
+

I0

CCII
+

I0

CCII
+

I0

CCII
+

I0

CCII
+

I0

Ii
C
Current
differentiator

I0 = CR

dI1
dt

Ii
R

Current
integrator

I0 = 1
I1 dt
CR

Current
summer

I1
I2

I0 = Id

In

Weighted
current
summer

I0 = Id
i

Ii

Rj
R

I1
In

R
R1
R
Rn

1970 IEEE.

tions 1 and 2 can be easily applied when the node being analyzed has a norator or nullator connected to it. When a node
has a nullator connected to it, the voltage at that node is assumed to be equal to the voltage at the other node of the nullator; however, it is assumed that no current can flow through
the nullator. When a node has a norator connected to it, it is
assumed that current flows through the norator, but the voltages on either node of the norator are determined by the rest
of the circuit. Similarly, the current through the norator is
determined by the rest of the circuit.

i1

v1

i1

v1

Nullator

Norator

v1 = i1 = 0

v1 = i1 arbitrary

Figure 3. Norator and nullator schematic representations.

Several equivalence properties of norators and nullators

that allow for network simplification will be described presently (9):
1. A series or parallel connection of Rs, Ls, Cs, and
at least one nullator is equivalent to a single nullator.
2. A series or parallel connection of Rs, Ls, Cs, and
at least one norator is equivalent to a single norator.
3. A series or parallel connection of Rs, Ls, Cs, and
at least one norator and at least one nullator is equivalent to an open circuit or a short circuit, respectively.
4. A four-terminal circuit composed of two nullators and
two norators all of which have a single terminal tied to
one node is equivalent to a four-terminal network composed of an uncoupled single nullator and a single
norator.
Another circuit element that is worth mentioning is the nullor. The nullor is a two-port network, which is simply composed of a nullator at one port and a norator at the second
port. Effectively, it is two uncoupled one-port networks. The
schematic symbol for this network is illustrated in Fig. 4. The
reason for its use is that many dependent current and voltage
sources can be expressed in terms of this unit. It is important

CURRENT CONVEYORS

i1

+
Port 1
v1 = i1 = 0

i2

v1

v2

Port 2
v2 = i2 arbitrary

Figure 4. Nullor schematic representation.

to note that the nullor can always be thought of as simply a

nullator and a norator and, therefore, provides no additional
insight into the analysis of a network. It is mentioned here
merely so that the reader will be familiar with the terminology.
Given the matrix definition of the negative second-generation current conveyor (CCII) from Eq. (2), an equivalent representation for the CCII can be expressed in terms of a single nullator and norator as illustrated in Fig. 5. The hybrid
matrices for these two circuits are equivalent. In summary,
any active network composed of nullators and norators in
pairs, as illustrated in Fig. 5, can be fabricated using CCII
networks. This fact will prove to be a useful property for synthesizing many types of active circuits.
As an example, two useful illustrations of the nullator
norator design technique types will be discussed. First, the
impedance inverter is presented. Table 3 (10) illustrates five
different methods for carrying out voltage and current inversion. It is important to note that these realizations do not
require a specific hardware realization. By looking for pairs
of norators and nullators, we can convert these circuits into
current conveyor circuits. Each topology will have its own specific performance benefit as explained in Ref. 10.
Another useful topology is shown in Fig. 6 and can be used
as a general impedance converter (GIC). Each of the branches
of the circuit can be a complex impedance. The relationship
that will hold between impedances is
Z1 Z3 Z5 = Z2 Z4 Z6

(3)

The way the network is used is to remove one of the complex

load impedances illustrated in Fig. 6 and solve for its value
in terms of the remaining five impedances. The relationship
in Eq. (3) will define the effective impedance at the circuit
port where the complex impedance was removed. This process
allows for the transformation of one of the five remaining load
impedances to an effective output impedance whose proper-

v1

i2

P1

v1

P1
CCII

P2

P3
P3

i3

P2
i3

i3 = i2
v1 = v3
Pi denotes the ith port
Figure 5. Nullatornorator representation of a CCII.

i2

437

ties depend on the circuit elements used in the network, thus

the name general impedance converter (GIC). This type of circuit can be used as a positive impedance converter (PIC) or a
positive impedance inverter (PII). Another useful application
of this circuit is realization of a frequency-dependent negative
resistance (FDNR), sometimes called a D element or an E element (9). These are very useful in active filter synthesis as
explained by Bruton (9). Filters can be synthesized using only
FDNRs and resistor elements. The D element has an impedance Z k/s2 where k is real and s is the complex frequency
variable of the Laplace transform. Similarly, the E element
has the form Z ks2 where again k is real.
Note that pairs of norators and nullators from Fig. 6 can
be replaced with second-generation current conveyors. The
way in which these current conveyors can be realized in hardware is the subject of the next section.
CURRENT CONVEYOR CIRCUIT ARCHITECTURE
Current conveyors can be built using either bipolar or metal
oxide semiconductor (MOS)type transistors. Because the
majority of applications to date have focused on the secondgeneration current conveyor, this type of current conveyor
will be addressed here. Another motivation for focusing on
the implementation of second-generation current conveyors is
that first- and third-generation current conveyors can be realized using multiple output second-generation current conveyors (1,12). As mentioned earlier, a CCII can be thought
of as an ideal FET. Similarly, it can also be thought of as an
ideal bipolar transistor. In reality, FETs and bipolar devices
do not behave ideally, and thus more complex circuit implementations result in order to compensate for the imperfections of real devices. In the process of obtaining more ideal
performance, many devices may need to be combined in order
to model more closely the ideal behavior exhibited by an ideal
device. Implementation of CCIIs with bidirectional current
capabilities require the use of complementary devices (i.e.,
pnp and npn bipolars or nMOS and pMOS FETs) (13).
It is difficult to fabricate an integrated circuit (IC) with identically performing pnp and npn devices. It is much easier to support complementary structures using MOS devices,
and thus many IC current conveyor designs are based on
MOS implementation. Figures 7 and 8 (13) illustrate CMOS
implementation of CCII and CCII current conveyors, respectively. In Fig. 7 current is transferred to the output using
complementary current mirrors. To fabricate a CCII (Fig.
8), two additional current mirrors are required.
A new approach to designing current conveyors at microwave frequencies has been proposed by Sinsky and Westgate
(14). This approach uses a GaAs monolithic microwave integrated circuit (MMIC) to closely approximate the required hybrid matrix parameters of Eq. (2) over a specified band of microwave frequencies. This technique was developed to support
the design of tunable synthetic microwave circuit elements
using negative impedance converters (NICs) and positive impedance converters (PICs). Such circuits can be used to design
tunable microwave filters and matching networks.
NOISE CONSIDERATIONS
In many applications, it is necessary to have a current conveyor that has good noise performance. Current mode circuits

438

CURRENT CONVEYORS

Table 3. Voltage and Current Inversion Using Nullators

and Norators
Type

Voltage Inversion

Current Inversion

I
V2 = V1

I2 = I 1

I2 = I1

V2 = V 1

G1
II

R1
V2 = (R2/R1)V1
R1

G2

R2
I2 = I1

I2 = (G2/G1)I1

R2

III

G1
V2 = (R2/R1)V1
R1

V2 = V 1

I2 = I1

G2

I2 = (G2/G1)I1

R2

G1

V2 = V 1

G2

IV
V2 = (R2/R1)V1

R1

I2 = I1

I2 = (G2/G1)I1

R2

V2 = [1 (R2/R1)]V1 I2 = I1

G1

V2 = V 1

G2

I2 = [1 (G2/G1)]I1V2 = V1

1970 IEEE.

(such as the current conveyor) are candidates for use in lowvoltage analog signal processing because large current swings
can be obtained even with small voltage excursions. Unfortunately, for low-noise performance in such circuits, low-noise
bias circuitry, which tends to require higher voltages for the
required low-transconductance devices, is required. This presents a design challenge when trying to obtain low-noise, low-

Z2

VDD

iZ = iX
A(s)

iX
Z1

Z4

Z5

Figure 6. Noratornullator immitance converter/inverter topology.

VSS
Figure 7. Positive second-generation current conveyor using MOS
devices and OP amp. IEE 1990.

CURRENT CONVEYORS

voltage current conveyors. The problem of designing low-noise

current conveyors is best addressed by Bruun (1,12) who has
developed a way to look at the problem and drawn some important conclusions.

439

dv2yeq

Iy
+

Vy

Y
Z

Ix
Vx

Iz

Ideal Current Conveyor Noise Analysis

To address noise issues in the CCI, CCII, and CCIII type current conveyors, it is sufficient to analyze the multi-output
CCII current conveyor as shown by Bruun (1,12). The general
noise analysis requires addressing the multi-output current
conveyor illustrated in Fig. 1. Because this device has multiple outputs, noise contributions cannot be modeled using only
an equivalent noise input voltage and current as done on conventional amplifiers. The multiple outputs may have correlated and uncorrelated noise contributions, and thus noise
sources must be assumed at each of the output ports as well
as the input ports. For more details on the mathematical formulation of the noise for the multioutput second-generation
current conveyor, see Refs. 1 and 12. Because most applications simply require single output CCII or CCII current
conveyors, the noise modeling for this type of device will be
emphasized here. For an ideal two-input single-output second-generation current conveyor whose input X terminal is
terminated in an impedance RX and whose Y input is terminated in an impedance RY where RSX RSY, Bruun (1,12) has
shown that

di2z = di2xeq + di2z eq +

dv2yeq
R2SX

4kT
df
RSX

(4)

where k is Boltzmanns constant, T is the absolute temperature, and df is the frequency bandwidth considered (see Fig.

VDD

iZ = iX
A(s)

2
diyeq

2
dixeq

2
dizeq

Figure 9. Second-generation current conveyor with equivalent

noise sources.

9). The dominant source of error in this formulation is the

finite input and output impedances to the current conveyor.
CMOS Current Conveyor Noise Considerations
A detailed analysis of noise optimization for CMOS current
conveyors has been carried out by Bruun (1,12). For class A
designs, it was found that the optimal signal-to-noise ratio is
proportional to the maximum output terminal current (the Z
terminal of Fig. 1 is the output terminal). This is because the
output noise power of the current conveyor is proportional to
the bias current and the output signal power is proportional
to the square of the output terminal current. Interestingly,
the class AB-biased current conveyor can provide better performance than the class A circuit because the output signal
swing is not limited by the bias current. In summary, the use
of low-noise bias circuitry and current mirrors are essential
in the design of low-noise CMOS current conveyors.
CONCLUSION
The current conveyor is a very powerful building block that
can be used in a myriad of applications ranging from power
supply control circuits to the design of high-frequency active
filters. Despite the many different applications and implementations of this circuit, there is one important point to remember: the current conveyor is a fundamental building
block that can be used in circuit synthesis in much the same
way as the operational amplifier. It allows the circuit designer
to concentrate on a higher level of circuit functionality. The
current conveyor has the capability to revolutionize the circuit design industry in much the same way as the operational
amplifier has. With much interest in current mode circuits, it
is inevitable that the current conveyors time has finally come.
BIBLIOGRAPHY

iX

1. E. Bruun, Noise Properties of CMOS Current Conveyors, IEEE

MTT-S Symp. Des., 1996, pp. 144147.
2. A. Sedra, G. Roberts, and F. Gohh, The current conveyor: history,
progress, and new results, IEE Proc., Part G, 137 (2): 7887,
1990.

VSS
Figure 8. Negative second-generation current conveyor using MOS
devices and OP amp. IEE 1990.

3. R. Senani, Novel circuit implementation of current conveyors using an O.A. and an O.T.A., Electron. Lett., 16 (1): 23, 1980.
4. K. Pal, New inductance and capacitor flotation schemes using
current conveyors, Electron. Lett., 17 (21): 807808, 1981.

440

CURRENT-MODE LOGIC

5. M. Higashimura and Y. Fukui, Novel methods for realising lossless floating immitance using current conveyors, Electron. Lett.,
23 (10): 498499, 1987.
6. A. Sedra and K. Smith, A second-generation current conveyor
and its applications, IEEE Trans. Circuit Theory, CT-17: 132
134, 1970.
7. R. Senani, Floating immittance realisation: Nullor approach,
Electron. Lett., 24 (7): 403405, 1988.
8. R. Senani, New tunable synthetic floating inductors, Electron.
Lett., 16 (10): 382383, 1990.
9. L. Bruton, RC-Active Circuits, Englewood Cliffs, NJ: PrenticeHall, 1980.
10. J. Braun, Equivalent NIC networks with nullators and norators,
IEEE Trans. Circuit Theory, CT-12: 441442, 1965.
11. V. Pauker, Equivalent networks with nullors for positive immittance inverters, IEEE Trans. Circuit Theory, CT-17: 642645,
1970.
12. E. Bruun, Analysis of the noise characteristics of CMOS current
conveyors, Analog Int. Circuits Signal Process., 12: 7178, 1997.
13. C. Ioumazou et al., Analogue IC design: The current-mode approach, London, UK: Peregrinus, 1990.
14. J. H. Sinsky and C. R. Westgate, A new approach to designing
active MMIC tuning elements using second-generation current
conveyors, IEEE Microw. Guided Wave Lett., 6 (9): 326328, 1996.

JEFFREY H. SINSKY
Bell LaboratoriesLucent
Technologies

CHARLES R. WESTGATE
Johns Hopkins University

CURRENT-FEEDBACK AMPLIFIERS. See ANALOG INTEGRATED CIRCUITS.

CURRENT MEASUREMENT. See AMMETERS; ELECTRIC

CURRENT MEASUREMENT.

CURRENT-MODE CIRCUITS. See TRANSLINEAR CIRCUITS.

44

DC AMPLIFIERS

DC AMPLIFIERS
The term direct coupled amplifier, or dc amplifier, means direct coupling between the amplifier and the input signal to
be amplified. Basically, a directly coupled amplifier has no
capacitive or inductive coupling between the input source and
the amplifier. Consequently, the dc amplifier, as opposed to
capacitively coupled or ac amplifiers, allows amplification of
continuous and low-frequency signals (1,2). Direct coupled
amplifiers appeared at the same time as amplifiers. But they
have performed better ever since, and with the introduction
of integrated circuits (ICs), it was possible to use a truly differential input stage implemented from a pair of matched
transistors (2,3). Figure 1 illustrates the direct and capacitive
coupling amplifications with alternating current (ac) and direct current (dc) input voltage sources. For proper operation,
it is necessary to have the same reference voltage level for the
amplifier and the input signal. In most cases the ground is
used as the reference.
A large number of applications require dc amplifiers to amplify low-frequency signals down to dc. They are, for example,
used in dcdc voltage down converters in which it is necessary to amplify a dc voltage reference (4). Directly coupled
amplifiers are also used in linear feedback loops to control
speed or position of dc motors. There are many measurement
transducers, such as temperature sensors, or load transducers used to measure weights. These exhibit a very low dc output voltage and are often directly coupled to a high-gain dc
amplifier (2). Direct coupled amplifiers are predominantly
used in monolithic integrated circuits where using coupling
capacitors would necessitate a large and expensive silicon
area (1). In addition, at very low frequencies, dc feedback amplifiers are also preferred to ac coupled feedback amplifiers,
which can induce motorboating or stability problems due to
the phase shift caused by several capacitive coupled stages
(2). Other high-speed applications, such as optical communi-

Rs

e(t)

dc

GENERAL SCHEMA FOR DC AMPLIFIERS

Basic dc Amplifiers
Figure 2 shows the building blocks of a classical dc amplifier.
It is composed of three main stages. The first block corresponds to a differential input stage and is followed by a second which consists of a high-gain voltage amplifier. The last
stage is a voltage follower. Usually, the dc amplifier is biased
between positive (Vcc) and negative voltages (Vee Vcc).
Considering the various gain stages, the output voltage
VO in the case of Fig. 2 is given by
VO = AGV Vid

(1)

This expression clearly shows the dependence of the amplifier

gain on the parameters A and GV. Because these parameters
are sensitive to process variation and thermal drift, amplifier
gain varies from one component to the other. The differential

+Vcc

Input

Direct
coupling
A

ac

cations, necessitate high-performance dc amplifiers with a

wide bandwidth (5).
The amplifier gain and the dc operating point depend on
multiple parameters, such as transconductance, load resistor
values, bias currents, and power supplies. Inherent fabrication process variation, thermal drifts, and component sensitivity inevitably introduce amplification and biasing errors.
The predominant errors result from voltage and current offsets corresponding to the input voltage and input current
which must be applied to force the output voltage of the amplifier to zero.
Considering the high process sensitivity of transistor parameters, offsets, and thermal drifts, the use of a single transistor input stage to build a dc amplifier is unreasonable. In
contrast, an input stage built from a differential pair of
matched transistors allows considerable reduction of these effects. This is the case, for example, of voltage-feedback operational amplifiers (VFOA), usually called op-amps. So, a highgain voltage-feedback amplifier allows designing an accurate
dc amplifier. In this case, with a very low common mode rejection ratio (CMRR), the gain of the dc amplifier depends only
on the feedback ratio that can be easily kept invariable.

Voltage gain
stage

S(t) = A [V + e(t)]

Out
e+

(a)

Output
Gv

e
V0

Capacitive
coupling
A

S(t) = A [ + e(t)]

(b)
Figure 1. Different kinds of coupled amplifiers: (a) dc amplifier; (b)
ac amplifier using coupling capacitor.

Differential
input stage

Voltage follower

Vee
Figure 2. Schema block for a dc amplifier showing the various
stages.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

DC AMPLIFIERS
R2

45

R2

R1
Dc input

R1

Dc input

e
AGV

e
AGV

VI

e+

e+
VO

VO

VI

(a)

(b)

input stage behaves as a preamplifier, and it amplifies offset

and drift voltages and currents. Consequently, the characteristics of this preamplifying stage define the performance and
limits of the dc amplifier. Another important parameter is the
input noise that also limits the minimum detectable signal.
In the next section describing the characteristics of the differential input stage, we show that its components have to be
well matched to obtain the smallest error signal possible.
Main Effects of Feedback Loop
The feedback loop is used mainly to prevent amplification
from the variation of the dc amplifier gain (AGV). Figures 3(a)
and 3(b) describe the feedback loop technique in both noninverting and inverting amplifiers. In these cases, considering
a dc amplifier with infinite gain (AGV ) and infinite input
resistance gain, the transfer functions VO /Vi is given as follows:

Noninverting amplifier
Inverting amplifier

Figure 3. The two configurations for dc

feedback amplifiers: (a) noninverting amplifier; (b) inverting amplifier.

VO
R
= 1+ 2
Vi
R1
VO
R
= 2
Vi
R1

(2a)
(2b)

When resistors R1 and R2 are accurate, this system constitutes an excellent directly coupled amplifier. Thus, this technique is a good solution for removing some of the shortcomings of the dc amplifier.
ANALYSIS OF THE BIPOLAR DIFFERENTIAL INPUT STAGE

rents Ib1 and Ib2, so that their effects are negligible, then the
collector currents are given by (69)
IC1 = (F I0 )/[1 + exp(Vid /VT )]

(3)

IC2 = (F I0 )/[1 + exp(+Vid /VT )]

(4)

In these equations F (Ic /Ie)VBC0 is the common-base forward, short-circuit current gain. Thus the expression of the
differential output voltage of this stage can directly be deduced from Eqs. (3) and (4):
Vod = RC (IC2 IC1 ) = F RC I0 tanh(Vid /2VT )

(5)

As a result, for Vid 2VT, the differential output voltage has

a 180 phase difference with respect to Vid, and the amplifier
gain is given by A Rc I0 (as F 1). In this way, A is
increased by increasing either the value of load resistors RC
or the bias current I0. Nevertheless, increasing I0 leads to a
rise in power consumption. However, the value of RC is artificially enlarged by using active loads (current mirrors), which
are easier to fabricate in IC form than high-value resistors.
Figure 5, which shows the variation of output voltage as a
function of Vid, illustrates the nonlinear effects that appear as
soon as Vid approaches 2VT. For an ideal differential stage,
this reveals that the output voltage Vod is zero for Vi1 Vi2.
Real Differential Stage
For a real differential stage implemented in IC form, the base
currents of Q1 and Q2, the component mismatches (amplifier
dissymmetry), the equivalent input noise, and the thermal

In this section, the relationship between input and output

voltages is determined for an ideal stage implemented from
bipolar transistors. Then, the mismatch effects (offsets and
drift sensitivities) are analyzed for a real dc amplifier.

+Vcc
Rc2

Rc1

Ideal Differential Stage

Ic1

Ic2

Figure 4 shows the schema of an ideal differential input stage

(or emitter-coupled pair), implemented from bipolar transistors. Vid Vi1 Vi2 is the differential input voltage, and
Vod Vo1 Vo2 is the differential output voltage of the circuit.
For an ideal amplifier, i.e., including perfectly matched elements, transistors Q1 and Q2 are assumed identical, and resistors RC1 and RC2 have the same value of RC.
For forward-biased transistors Q1 and Q2 (i.e., Vbe VT;
VT kT/q is the thermal voltage), the reverse saturation currents of the collectorbase junctions can be ignored. Neglecting the Early effect and assuming very low values for cur-

Vo1

Ib1

Vod
Q1

Vo2
Q2

Vi1

Ib2
Vi2

I0
Vee
Figure 4. Bipolar differential input stage using matched devices.

46

DC AMPLIFIERS

Perfectly matched
stage
Differential stage
with mismatches
Vod

+ F I0 Rc
Perfectly matched
stage

Differential stages
with mismatches
VS

4VT 2VT

2VT

Vid

4VT

Figure 5. Differential output voltage as a function of input voltage

showing the curves for matched and mismatched stages.

drifts must be taken into account to determine the minimum

differential dc voltage detectable (amplifier sensitivity).
Base Input Bias Currents. The dc input bias currents (Ib1
Ib2 in Fig. 4, for Vod 0) required for biasing the transistors
are taken from the driving generators connected to the inputs. Their value, Ibias (Ib1 Ib2)/2, is directly related to the
design of the differential stage. A very low base current value
requires high current gain (). This can be obtained, for example, by using Darlington or super transistors. It can
also be noted that the influence of the base currents is reduced to the minimum, if both inputs are driven by generators with the same equivalent output resistance.
Component Mismatch Effects. All of the effects due to amplifier dissymmetry can be characterized with only two continuous generators: a voltage generator (Vos) and a current generator (Ios). These two generators are discussed in the next
paragraphs. Thus, as indicated in Fig. 6, the real amplifier is

+Vcc
Rc2

Rc1
Ic2

Ic1
Ib1

Vod

Vo1
Q1

Vi1

Vos = VT ln[(IC1 /IC2 )(IS2 /IS1 )]

(6)

Now the saturation and collector currents can be written as

IS1 IS IS2 IS and IC2 IC IC1 IC. In addition, with
RC1 RC RC2 RC, which represents the resistor dissymmetry,

F I0 Rc

Vos

equivalent to the ideal differential stage previously discussed,

with Vos and Ios connected on input.
Input Offset Voltage. This voltage results principally from
the dissymmetries between transistors Q1 and Q2: mismatches in the base widths, in the base and collector doping
levels, and in emitter areas. It is also caused by mismatch in
collector resistors RC1 and RC2. By definition Vos is the ideal
equivalent generator voltage, which applied to the input,
drives the output voltage (Vod) to zero. Then Vos Vbe1 Vbe2
(Fig. 6).
Assuming that the relationship between the base-emitter
voltage and collector current for a forward biased transistor
is VBE VT ln(IC /IS),

Vo2
Q2

Finally, assuming that IS /IS 1 and RC /RC 1, Vos can be

described by


Vos = VT

RC
IS
+
RC
IS


(7)

Input Offset Current. This current results principally from

the mismatched values of the current gains of Q1 and Q2.
When Vod is zero, Ios is defined by Ios Ib1 Ib2. Assuming
that 1 2 , from the previous equations
this gives
Ios =

IC

RC

+
RC


(8)

Now we can deduce that the offset current is directly proportional to the base input bias current. Then a low value for Ios
necessitates either a low I0 or a high . High RC values also
reduce this unwanted current Ios.
Thermal Drift. We define thermal drift as the variation of
component electrical parameters with temperature. So, for a
given differential amplifier design, the drift of Ib, Vos, and Ios
characterizes the influence of temperature on the output voltage Vod. Thus, the drift of the bias current Ib determines the
output stability for different values of the driving generator
resistance. The thermal drift of Vos can be directly calculated
from Eq. (7). Assuming that RC and IS are temperature-independent,

Ib2
Vi2

Ios

RC2 IC2 = RC1 IC1

I0
Vee
Figure 6. Mismatched differential stage. Equivalent circuit with a
perfectly matched amplifier and offset voltage and current sources.

dVos
Vos
=
dT
T

(9)

Equation (9) shows a direct proportionality to Vos. Moreover,

a low drift for Ios is necessary to obtain low output variation
when the internal resistances of the driving generators have
high values.
Long-Term Drift Variation. All of the previous values of drift
given by manufacturers are rigorously valid for fresh components, but drift changes as components age.

DC AMPLIFIERS

Voltage Input Noise. Low-frequency input noise is an important limitation in precision dc application, as, for example,
instrumentation measurements.

47

Vod
+ R dI 0

ANALYSIS OF MOS DIFFERENTIAL PAIR

I0
K

Now we analyze a differential stage implemented from MOS

transistors to compare their performance to bipolar ones.

I0
K

Vid

Ideal Input Stage

An NMOS source-coupled pair is shown in Fig. 7. We assume
that both M1 and M2 are matched transistors with equal
W/L ratios (W is the channel width and L is the channel
length) and equal threshold voltage Vth. We neglect the body
effect and the channel modulation length. The load resistors
Rd are assumed identical. As usual we suppose that the drain
current is related to the gate-source voltage Vgs and the
threshold voltage Vth by the well-known approximate squarelaw relationship Id K(Vgs Vth)2, where the gain factor K
1/2Cox W/L ( is the electron-mobility and Cox is the gate
capacitance per unit). From Kirchhoff s laws it follows that
the differential input voltage is given by Vid Vi1 Vi2
Id1 /K Id2 /K, and at the source node, Id1 Id2 I0. Combining these expressions yields (8)

Id1

Id2

s

V 2
I0
2
id

1 + KVid
=

2
KI0
I0

s

V 2
I0
2
id

1 KVid
=

2
KI0
I0

(10)

(11)

Consequently the differential output voltage Vod is expressed

by
Vod = Rd (Id2 Id1 ) = Rd KVid

r 2I

(Vid )2

(12)

This expression is valid as long as both transistors M1 and

M2 are in the saturated mode which is proved by Vid
I0 /K. When this condition is satisfied, the gain A of the differential amplifier is given by Vod /Vid Rd 2I0K.

+Vdd
Rd2

Rd1

Vo1
M1

Vod

Vo2
M2

Vi1

Vi2
I0
Vss

Figure 7. The NMOS source-coupled pair using matched devices.

R dI 0
Figure 8. The dc transfer characteristic of the ideal source-coupled
pair.

Note that for the MOS differential pair, the Vid range for
linear operation depends on the biasing current I0 and the
W/L ratio of the transistors. In contrast, for the bipolar differential pair this range is about 2VT and is independent of
transistor size and bias current. The gain of the source-coupled pair depends on bias current I0, load resistance Rd, and
transistor dimensions (W/L). In contrast, the gain for the bipolar differential pair depends only on the biasing current I0
and load resistance Rc.
The dc transfer characteristic of the source-coupled pair is
shown in Fig. 8. When Vid I0 /K, either M1 or M2 is completely turned off, and Vod is equal to RdI0. An increase in I0
increases the linear operating region, whereas an increase in
the W/L ratio causes the opposite effect (8).
Real Input Stage
Technological Constraints. Until now we have studied the
behavior of the ideal MOS amplifier. A real differential pair
presents some dc errors that produce basic limitations for
many analog systems.
In dc and low frequencies, the threshold voltage Vth and
the gain factor K represent the predominant sources of static
errors in a source-coupled pair (3). The deviations in the
threshold voltage and the gain factor are due to technological
parameters. The difference in Vth between two matched transistors results mainly from differences in oxide thickness and
bulk doping. Actually the oxide thickness in VLSI MOS processing is so reproducible that it has only a negligible effect
on Vth. Consequently, changes in substrate doping are the
principal source of threshold voltage mismatch Vth which is
typically 10 mV to 25 mV. The gain factor includes two parameters, the factor K 1/2Cox and the gate dimensions W
and L. The changes in mobility in K depend on deviations in
bulk doping. Deviations in W and L result from photolithography variations. The latter variations represent the main
source of deviations in the gain factor. The differences between the load resistances, whose typical values depend on
size, also contribute to the dc errors in the source-coupled
pair (3).
The effects of mismatches on dc performance in MOS amplifiers are represented only by the input offset voltage due to
high impedance of the gate of MOS transistors (6).

48

DC AMPLIFIERS

Input Offset Voltage. As mentioned earlier, the input offset

voltage Vos is the input voltage required to force the differential output voltage to zero. Summing voltages around the
source loop in Fig. 9 gives
Vos = Vth1 Vth2 +

I

d1

K1

I

R2

Vos

R1

K2

Vo

R3

where the difference quantities are given by Vth Vth1

Vth2, Rd Rd1 Rd2, and K K1 K2, and the average
quantities are given by
Vth1 + Vth2
R + Rd2
, Rd = d1
,
2
2

and K =

K1 + K2
2

The offset voltage in Eq. (13) consists of two parts. One equals
the threshold voltage mismatch and the other contains mismatches in load resistances and gate dimensions. Note that
Vos mismatch depends on differences and also on biasing
points. When the transistors are biased at small values of
(Vgs Vth), the influence of Rd and K becomes smaller. Consequently, at weak inversion the main factor influencing the
input offset voltage is Vth.
The main difference between bipolar and MOS differential
stages is the mismatch in the threshold voltage. For a MOS
stage, this results in a constant offset component that is independent of bias current. Consequently the MOS differential
stage displays a higher offset voltage than the bipolar pair.
Offset Voltage Drift. The drift of the input offset voltage of
a MOS differential pair is given by Vos /T (8). Contrary to
the bipolar case, the offset voltage drift in MOS stages is not
directly correlated with the offset voltage.
The temperature drift of the offset value depends on variations of Vth and K. The variation of Vth is as high as some mV/
C. But the changes in K are considerably larger because K
includes mobility.

+Vdd
Rd2
Vos

Vo1
M1

I0S

Figure 10. Schematic form of the feedback implementation including

offset generators.

GENERAL CRITERION FOR IMPLEMENTING DC AMPLIFIERS

Comparison Between Bipolar and MOS Stages
Generally bipolar input stage amplifiers have much better
long-term stability than MOS devices can offer. Very good
matching between the input transistors is obtained with bipolar differential pairs. Indeed for bipolar transistors the transconductance parameters do not depend on both the area of
the transistor and the technology. In contrast, for MOS differential stages the transconductance is strongly dependent on
the W/L ratio and the fabrication processes. As a result bipolar stages exhibit lower offset voltage and temperature drift.
In addition for the same value of the bias current, they will
be smaller than MOS to have the same value for the transconductance. Nevertheless bipolar stages exhibit large input bias
currents. In contrast, MOS input stages take advantage of a
high input impedance resulting in low offset current and low
bias current. This makes them ideal for portable systems and
micropower applications.
Feedback Loop Effects
Figure 10 shows the circuit that can be used to calculate the
output offset voltage of an amplifier in its usual feedback configuration. This is valid for both the inverting and noninverting amplifier configurations, shown in Fig. 3. The value
of R3 is assumed to be (R1 //R2) and to cancel the effects of the
bias current Ib.
Calculation gives

Rd1

Vo = 1 +

Vod

d2

To make the differential output Vod exactly zero requires that

Rd1Id1 Rd2Id2. Using the last expression, we find that (3)



Vgs Vth
Rd
K

(13)
Vos = Vth +

2
Rd
K

Vth =

Vo2
M2

Vi1

Vi2

I0
Vss
Figure 9. The NMOS source-coupled pair with the dc offset voltage
source.

R2
R1

Vos + R2 Ios

(14)

This reveals that the coefficient of Vos can be expressed directly in terms of the closed loop gain. Consequently the input
offset voltage becomes preponderant for low values of R2.
GENERAL TECHNIQUES USED TO REDUCE
DC ERRORS IN AMPLIFIERS
As shown previously, dc offset limits numerous applications
in linear IC. For example, offset voltage is a particularly important parameter for precision instrumentation amplifiers

DC AMPLIFIERS

+Vcc

+Vcc

+Vcc

+Vcc

External
variable
resistor

Zener diode

...

...

Current
injection

VO
Q1

49

Q2

VO

Vi

Q1

Q2

Vi

Vee
Figure 11. Conventional method for canceling dc offset voltage using
a variable resistor to adjust the collector resistors ratio.

Vee

and for applications where rail-to-rail output signal swing is

required. In these latter cases, the dc offset reduces the dynamic range, which is, in turn, very restrictive when designing in low-voltage technology (CMOS). Several techniques,
however, can be used to compensate for this nonideal effect.
Two ways to proceed are addressed in this section. We have,
on the one hand, what we call offset trimming techniques
and, on the other, improved circuit designs tending to eliminate the dc offset.
Various Adjustment Possibilities
Because the input differential stage generates the dc offset, it
is exclusively on this stage that any corrections need to be
performed. The emitter-coupled pair (or source-coupled pair)
analyzed previously, is the most commonly used input stage.
One solution for canceling the offset is to adjust the collector
resistor ratio (which should be equal to one) with an external
(out of chip) variable resistor, as shown in Fig. 11. This variable resistor is controlled by a potentiometer which adjusts
its value for canceling the dc offset voltage. Thus Vod 0
when Vid 0. The well-known operational amplifier 741 uses
this technique to eliminate the dc offset which is typically
about 2 mV without correction. The offset drift is about 70
V/C. Moreover, this resistor adjustment can also be realized
with a laser beam. This automated process is performed directly on the wafer, and the laser adjusts the resistor size
on the chip. This has the possible disadvantage of being an
irreversible process. The precision operational amplifier
OPA177 from BurrBrown combines both of these methods:
laser-trimming offset and an optional connection to an external potentiometer. Then the offset achieved is about 10 V,
and the drift is only 0.3 V/C.
Another nulling technique consists of replacing each of the
two load resistors Rc with several resistors in series. Then
each resistor is in parallel with Zener diodes, as shown in Fig.

Figure 12. Zener-zap trimming technique. Zener diodes are placed

in parallel with load resistors, and must be shorted with a current
injection to adjust the offset voltage to zero.

12. Injecting a current pulse into the diode permanently

shorts its parallel resistor. In practice the series resistors
have different values for refining the adjustment. In the OP07A from Precision Monolithic Inc., this Zener-zap trimming technique reduces the offset voltage to 10 V and the
drift to 0.2 V/C (9).
We demonstrated previously that in the bipolar, emittercoupled pair, the dc offset voltage and drift are given by Eqs.
(7) and (9). Thus in theory, if we null Vos, then the drift is also
nulled. In practice, however, introducing the potentiometer
creates a new drift factor, which cannot be eliminated simultaneously (10).
In conclusion it is important to see in these offset trimming
techniques that adjusting the resistors is performed at a single fixed temperature. In consequence, for applications over a
wide range of temperature, the drift will be important (11).
In the next part we see more ways to improve the performance when designing specific circuits to correct dc errors.

Vos
Vi1

Ibias
+
Ios/2

Vo

Vi2
Ibias

Figure 13. An amplifier with dc offset sources; input offset voltage

(Vos), and input offset current (Ios).

DC AMPLIFIERS
+Vcc

+Vcc

Amplitude

50

+Vcc

Clock

Time
Vi

Vo

Vo
Ib3

Vi1

Q4

Q3

Q1

Q2

Time

Ib3 Ib2
I 0
Ib2

Vi2

Figure 16. Input, output, and clock signals in a basic autozero amplifier. The discontinuities in output signal must be eliminated with
a low-pass filter.
Vee

Figure 14. A method for canceling the input bias current in a bipolar
differential pair. The base current of Q3 is mirrored to the base of
Q2. It reduces considerably Ibias current and Ios current.

Circuits with Improved Design

Correcting the dc Offset Current and Input Bias Current. We
can represent an amplifier with different offset sources as
shown in Fig. 13. The advantage of the MOS differential pair,
compared with the similar bipolar input stage, is the very low
(about 100 pA) input bias current (Ibias). In addition, the MOS
differential pair results in very low input offset current (Ios),
about 10 pA. The isolated gate of the MOS allows this characteristic. Nevertheless, this advantage practically disappears
when diodes are included to protect the gates from electrostatic discharges. In the case of the bipolar differential pair,
the values of Ibias and Ios are directly proportional to the base
currents of the transistors, as explained previously.
A method for canceling the input bias current is shown in
Fig. 14. The base currents of Q2 and Q3 are practically identical because the same current flows through their collectors.
Then the base current of Q3 is mirrored to the base of Q2. The
same applies for Q4 and Q1. As a result, the Ibias current is
nulled, and Ias is considerably reduced. For example, using
this method, the precision operational amplifier OPA177 from
BurrBrown provides 0.5 nA for Ibias and 0.1 nA for Ios.

Correcting the dc Offset Voltage. In this section we address

a widely used method for designing low-offset voltage and
low-drift amplifiers. This technique, based on the autozero
concept (AZ) (12), in addition, allows canceling low-frequency
noise (12,13). An AZ amplifier is shown in Fig. 15. This technique consists of sampling the dc offset of the amplifier and
subtracting it from the signal. The sample operations, moreover, are performed with switched-capacitor circuits. This
brings us to the functioning of such a configuration. Two
phases are needed. In a first stage (1), the switch shorts the
input, and the dc offset appears at the output. Then this
quantity is sampled, held by capacitor Cn, and applied at an
auxiliary nulling input (N), to eliminate it. In the second
stage (1), the amplifier is ridded of the offset and is connected back to the input signal for amplification. Figure 16
shows the input and output signals and the clock which
drives the nulling operations. It is easy to see that the output

V+

+
Main amp

Vo

N
1

C2

2
1

+
C1

Figure 15. A basic autozero amplifier. The offset voltage is sampled,

held in capacitor Cn, and injected at a nulling input (N). This correction is controlled by a clock ().

Figure 17. Continuous time autozero amplifier using a main amplifier and a basic auto-zero amplifier.

DC AMPLIFIERS

51

Table 1. Integrated Circuits Used for dc Applications and Main Characteristics at 25C
Designation
LM741C
OP07A
AD708S
OPA177F
ICL7650
LTC1100ACN
TLC2652AM

Manufacturer

Function

National Semiconductor
PMI
Analog Devices
BurrBrown
Maxim
Linear Technology
Texas Instrument

op amp
ultra low offset op amp
ultra low offset op amp
Precision op amp
Chopper
Chopper op amp
Chopper op-amp

signal displays discontinuities due to phase 1. Hence it must

be low-pass filtered to reduce continuity of the signal. Note
that the clock frequency must have at least twice the signal
frequency to fulfill the Shannon criterion. Consequently this
reduces the application of autozero amplifiers to the low-frequency domain.
Nevertheless, some applications require continuous time
amplification. In these cases the amplifier should not be disconnected from the input signal. An improved schema is proposed in Fig. 17: the continuous time AZ amplifier or chopper amplifier. Generally designed with MOS transistors,
such amplifiers incorporate two amplifiers internally, a main
amplifier and an AZ amplifier. Two phases are needed to describe the operation. During the first phase (1), the AZ amp
corrects its own offset, as addressed previously. Then, during
the second phase (2), the offset-free AZ amplifier senses the
main amplifiers offset, stores this value in capacitor C2, and

Input Offset
Voltage

Voltage Drift

Input Bias
Current

Input Offset
Current

2 mV
10 V
5 V
10 V
0.7 V
1 V
0.5 V

0.2 V/C
0.1 V/C
0.3 V/C
10 nV/C
5 nV/C
3 nV/C

80 nA
0.7 nA
0.5 nA
0.5 nA
1.5 pA
2.5 pA
4 pA

20 nA
0.3 nA
0.1 nA
0.1 nA
0.5 pA
10 pA
2 pA

applies it at the nulling input of the main amplifier. Because

the offset is constantly corrected even during temperature
variations, chopper amplifiers feature very good performance.
For instance, the LTC110 precision chopper instrumentation
amplifier from Linear Technology reduces the offset voltage
to typically 1 V and the drift to 5 nV/C. Therefore such
amplifiers are very useful for precision applications. Table 1
lists the main dc characteristics at 300 K of different amplifiers used for dc operation (9,1416).
OTHER AVAILABLE IMPLEMENTATIONS
Dc amplifiers can also be designed from basic building blocks
other than operational amplifiers. Various possible implementations and their particularities are addressed in this section.
Their typical dc input errors are listed in Fig. 18. This figure
also displays the errors of classical IC amplifiers.

1,00E-01
High-speed bipolar
EL2211
Current feedback O.A

1,00E-02

Input offset voltage, Vos (V)

FET / CMOS
AD549

1,00E-03
TLC2272
TLC2252
1,00E-04

AD509

EL2165C

OPA627

EL2165C

Bipolar O.A

AD820
AD795

LT1206
EL2166C

Inst O.A

TLE2021

AD829

INA2128
OPA77
1,00E-05

Chopper

OPA177

INA101SM

TLC2654C

1,00E-06
TLC2654C
1,00E-07
1,00E-14 1,00E-13 1,00E-12 1,00E-11 1,00E-10 1,00E-09 1,00E-08 1,00E-07 1,00E-06 1,00E-05 1,00E-04
Input bias current, Ib (A)
Figure 18. Typical voltage and current offsets for various IC amplifier families.

52

DC AMPLIFIERS

Vi1

+
R2

A2

RB

R1

A1

RA

Vo

+
RB

R1

R2

A2
+

Vi2

Figure 19. Instrumentation amplifier.

Instrumentation Amplifiers
Such integrated amplifiers incorporate three operational amplifiers in a single chip (1,7). Matched resistors obtained with
laser trimming are also included to cancel typical dc errors.
The resulting circuit is shown in Fig. 19. A1 is connected as a
difference amplifier. A2 and A2 are in a noninverting configuration. Thus the output voltage is given by

tions are realized as shown in Fig. 3. But in that case the

output voltage is given by
Vo = ZT i

(17)

So, the amplifier gain can be easily adjusted with RA connected out of chip.

with ZT RTCT which is the output impedance at port Z of

the CCII. The CFOA exhibits higher bandwidths than classical operational amplifiers. Indeed the bandwidths are proportional to 1/R2CT (R2 is the feedback resistor in Fig. 3). The
slew rate is also greatly increased (about 1000 V/s). Nevertheless, dc errors are particularly prevalent in CFOA designs.
The dissymmetries between the inputs imply that their bias
currents do not match or cancel.

Current Feedback Operational Amplifiers

High-Speed Operational Amplifiers

In current feedback operational amplifiers (CFOA) also called

transimpedance op-amps, the input cell is different from that
used in voltage-feedback op-amps (VFOA) (see Figs. 4 and 7)
(17). This cell is basically a second-generation current conveyor (CCII) as shown in Fig. 20, which is commonly described by the following matrix relation:

The input stage of high-speed operational amplifiers is generally identical to the one of classical op-amps. Their output is
nevertheless constituted from the difference between two output currents. This improves the speed and bandwidth to the
detriment of input errors.

Vo = (Vi1 Vi2 )

iy 
0
=

vx
iz

1
0

R2
R1

0
0
1

0
0
0

1+

2RB
RA

(15)


vy

ix
vz

(16)
+

Figure 21 represents the equivalent electrical circuit for a

CFOA (1721). The inverting and noninverting configura-

I =o
1

I = ix
Rx

Ix

Rx

Vo

ZT
ix

Rz

Ix
X

Figure 20. Equivalent macromodel of the second generation current conveyor.

Figure 21. Current feedback operational amplifier obtained from a

second generation current conveyor and a voltage follower.

DCDC POWER CONVERTERS

CONCLUDING REMARKS AND PROSPECTIVE DEVELOPMENTS

In this article we have inspected the mismatches and drift
effects on the performance of dc amplifiers implemented from
op-amps. Bipolar and MOS differential inputs stages have
successively been analyzed. NPN and NMOS transistors have
only been considered above. Nevertheless differential amplifiers can also be implemented from PNP or PMOS elements.
In these cases note that PNP transistors exhibit lower values and the mobility of PMOS transistors is about three
times smaller.
The general criterion to consider for implementing dc amplifiers and the most commonly used techniques to reduce dc
errors have been investigated.
As indicated, dc amplifiers can also be designed from other
available building blocks: Traditionally all these dc amplifier
implementations use voltage input signals. Rushing into the
opening created by the introduction of the CFOA, another design approach could consist in using current input signals in
place of voltages.
Second-generation current conveyors can be driven from
current signals and these could certainly be used advantageously in designing dc amplifiers.

16. D. Soderquist, The OP-07 ultra low offset voltage op amp; A bipolar op amp that challenges choppers, eliminates nulling, application note 13 in Precision Monolithics Inc. Linear and Conversion
Applications Handbook, 1986.
17. C. Toumazou, F. J. Lidgey, and D. G. Haigh, Analog IC Design:
The Current Mode Approach, London: Peter Peregrinus, 1990.
18. A. Fabre, O. Saaid, and H. Barthelemy, On the frequency limitations of the circuits based on 2nd generation current conveyors,
Analog Integrated Circuits Signal Process., 7: 113129, 1995.
19. A. Fabre, Gyrator implementation from commercially available
transimpedance operational amplifiers, Electron. Lett., 28: 263
264, 1992.
20. A. D. Wang, The Current-feedback op amp, a high-speed building
block, in Applications Handbook, Tucson, AZ: BurrBrown, 1994.
21. B. Harvey, Current feedback op-amp limitations: a state of the
art review, Conf. Proc. Int. Symp. Circuits Syst., 1993.

ALAIN FABRE
FABRICE SEGUIN
HOUNAIDA ZOUAOUI ABOUDA
Universite de Bordeaux I

HERVE BARTHELEMY
Institut Superieur dElectronique de
la Mediterranee

BIBLIOGRAPHY

DC CONVERTERS. See HVDC POWER CONVERTERS.

1. A. S. Sedra and K. Smith, Microelectronics Circuits, 4th ed., New
York: Oxford Univ. Press, 1998.
2. Horowitz and W. Hill, The Art of Electronics, 2nd ed., New York:
Cambridge University Press, 1989.
3. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, New York: McGraw-Hill, 1994.
4. S. J. Jou and T. L. Chen, On-chip voltage down converter for LV/
LP digital, IEEE Int. Symp. Circuits Syst., Hong-Kong, 1996
1999.
5. S. Kimura, Y. Imai, and Y. Miyamoto, Direct-coupled distributed
baseband amplifier ICs for 40-Gb/s optical communication, IEEE
J. Solid State Circuits, 31: 13741379, 1996.
6. J. F. Gazin, Manuel dApplications C.I.L., Les Amplificateurs Operationnels, 2nd ed., Arcueil, France: Thomson-CSF, Tome 1,
1974.
7. J. Millman and A. Grabel, Microelectronics, New York: McGrawHill, 1988.
8. P. R. Gray and R. G. Meyer, Analog Integrated Circuits, 2nd ed.,
New York: Wiley, 1984.
9. D. A. Johns and K. Martin, Analog Integrated Circuit Design, New
York: Wiley, 1997.
10. Anonymous, Low Drift Amplifiers, National Semiconductor, Linear Brief 22, June 1973.
11. Robert J. Widlar, Reducing DC Errors in Op-Amp, Santa Clara,
CA: National Semiconductor, Technical Paper 15, December
1980.
12. C. C. Enz and G. C. Temes, Circuit techniques for reducing the
effects of op-amp imperfections: Autozeroing, double sampling,
and chopper stabilisation, Proc. IEEE 84: 15841614, 1996.
13. G. Erdi, Chopper versus bipolar op amps; an unbiased comparison, design notes n 42 in Application Handbook, 1993, volume
II, Milpitas, CA: Linear Technology, 1993.
14. Analog Devices, Linear Product Data Book, Norwood, MA, 1990.
15. Analog Devices, Amplifier Applications Guide, Norwood, MA,
1992.

53

DATA ACQUISITION AND CONVERSION

Data acquisition and conversion pertain to the generation of
signals from sensors, their conditioning, and their conversion
into a digital format. In this article we describe typical sensors that generate signals and examples of data converter topologies suitable for sensor interfaces. We restrict ourselves
to integrated implementations of sensors and sensor interface
circuits. In particular, we target sensors and sensor interfaces
that are compatible with CMOS fabrication technologies.
This article is organized as follows. First, we describe some
examples of sensors and sensor interfaces; then we describe
some sample data converter topologies. After that, we provide
two complete design examples.

Integrated sensors are used in many applications, including automotive, manufacturing, environmental monitoring,
avionics, and defense. In the past few years, integrated sensors that monolithically combine the sensor structure and
some signal-processing interface electronics on the same substrate have begun to emerge. By combining microsensors and
circuits, integrated smart sensors increase accuracy, dynamic
range, and reliability and at the same time reduce size and
cost. Some examples of semiconductor sensors are pressure
sensors used in pneumatic systems, magnetic sensors used
in position control, temperature sensors used in automotive
systems, chemical sensors used in biological diagnostic systems, and acoustic emission sensors used in structural diagnostics.
In the next two sections we illustrate the use of sensors
and sensor interfaces with the two most common types of sensors: resistive and capacitive sensors. We then describe two
complete sensor systems that include an acoustic emission
sensor and a temperature sensor.

SENSORS
Sensors are devices that respond to a physical or chemical
stimulus and generate an output that can be used as a measure of the stimulus. The sensed inputs can be of many types:
chemical, mechanical, electrical, magnetic, thermal, and so
on. The input signal sensed by the sensor is then processed
(amplified, converted from analog to digital, etc.) by some signal conditioning electronics, and the output transducer converts this processed signal into the appropriate output form.
The primary purpose of interface electronics is to convert the
sensors signal into a format that is more compatible with the
electronic system that controls the sensing system. The electric signals generated by sensors are usually small in amplitude. In addition to this, sensors often exhibit errors, such as
offsets, drift, and nonlinearities, that can be compensated for
with the correct interface circuitry. Analog elements have
been improved substantially to achieve high speed and high
accuracy; however, for many applications digital is still the
preferred format. The sensors yield a wide variety of electric
output signals: voltages, currents, resistances, and capacitances. The signal conditioning circuitry modifies the input
signal into a format suitable for the follow-on data converter.
Figure 1 shows the system architecture for a sensor
actuator-based control system. The sensor(s) senses the external physical and chemical parameters and converts them into
an electrical format. The sensed data are processed and digitized using integrated circuitry and transmitted to the host
controller. The host uses this information to make the appropriate decisions, and information is fed back to the external
environment through a set of actuators (1). These microprocessor-based controllers have revolutionized the design and
use of instrumentation systems by allowing system operation
to be defined in software, thus permitting a substantial increase in signal-processing and user-interface features. In
general, a power supply is also connected to these blocks but
is not explicitly shown in Fig. 1. If a sensor can provide a
signal without a power supply, it is referred to as a self-generating sensor.

Resistive Sensors
Sensors based on the variation of electric resistance are called
resistive sensors. They can be further classified according to
the physical quantity that they measure: thermal, magnetic,
optical, and so on.
A potentiometer is a simple resistance measurement device
in which the resistance is proportional to its length. However,
the linearity of a potentiometer is limited because its resistance is not perfectly uniform. The resistance value also drifts
with temperature. Applications of potentiometers are in the
measurement of linear or rotary displacements.
Another simple and commonly used resistive sensor is the
strain gauge, which is based on the variation of the resistance
of a conductor or semiconductor when subjected to a mechanical stress. The variation in the resistance of a metal is given
(2) by
R = R0 (1 + G
)

(1)

where R0 is the resistance when there is no applied stress, G

is the gauge factor, and is the strain. There are a number of
limitations on strain gauges, such as temperature dependence, light dependence, and inaccuracies in the measurement of a nonuniform surface; but in spite of these limitations, they are among the most popular sensors because of
their small size and linearity.
Some of the applications of the strain gauge are in measuring force, torque, flow, acceleration, and pressure. Figure 2
shows a micromachined piezoresistive cantilever beam used
as a strain gauge sensor. Strain gauges are capable of detecting deformations as small as 10 m or lower.
A resistance temperature detector (RTD) is a temperature
detector based on the variation in electric resistance. An increase in temperature increases the vibrations of atoms
around their equilibrium positions, and this increases the resistance in a metal: Thus there is a positive temperature coefficient of resistance. The complete temperature dependence

493

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

494

DATA ACQUISITION AND CONVERSION

Control parameters

Sensed parameters

Actuators

Sensors

Driver

Amp

DAC

ADC

temperature dependence of thermistors is given (2) by





1
1

RT = R0 exp B
T
T0

Microcomputer control

Higher-level control
Figure 1. Overall system architecture of a sensoractuator control
system.

can be expressed (2) as

R = R0 (1 + 1 T + 2 T 2 + + n T n )

(2)

where T is the temperature difference from the reference and

R0 is the resistance at the reference temperature.
The main advantages of these sensors are their high sensitivity, repeatability, and low cost. There are some limitations
too. Firstly, to avoid destruction through self-heating, the
RTD cannot measure temperatures near the melting point of
the metal. Secondly, the change in temperature may cause
physical deformations in the sensor. Additionally, for each
metal there is only a small range over which the RTD is linear. The most common metals used for RTDs are platinum,
nickel, and copper.
Thermistors are also temperature-dependent resistors but
are made of semiconductors rather than metals. The temperature dependence of the resistance of a semiconductor is due to
the variation in the available charge carriers. Semiconductors
have a negative temperature coefficient, as the resistance is
inversely proportional to the number of charge carriers. The

Figure 2. Micromachined piezoresistive cantilever beam used as a

strain gauge sensor.

(3)

where T0 is the reference temperature, R0 is the resistance at

T0, and B is the characteristic temperature of the material,
which itself is temperature-dependent. The limitations and
advantages of a thermistor are similar to those of a RTD, except that the thermistor is less stable. There are many types
of thermistors available, and each type has its own applications. The foil and bead types are suitable for temperature
measurement, whereas the disk and rod types are suitable for
temperature control. Some of the applications of thermistors
are in the measurement of temperature, flow, level, and time
delay. Two simple applications of thermistors are discussed
below.
Light-dependent resistors, or LDRs, are devices whose resistance varies as a function of the illumination. LDRs are
also known as photoconductors. The conductivity is primarily
dependent on the number of carriers in the conduction band
of the semiconductor material used. The basic working of the
photoconductor is as follows. The valence and conduction
bands in a semiconductor are quite close to each other. With
increased illumination, electrons are excited from the valence
to the conduction band, which increases the conductivity (reduces the resistance). The relation between resistance and optical radiation or illumination is given (2) by
R = AE

(4)

where A and are process constants, R is the resistance, and

E is the illumination.
An important limitation of LDRs is their nonlinearity.
Also, their sensitivity is limited by fluctuations caused by
changes in temperature. Finally, the spectral response of
LDRs is very narrow and primarily depends on the type of
material used.
Some of the most common LDRs are made of PbS, CdS,
and PbSe. Some applications of LDRs are shutter control in
cameras and contrast and brightness control in television receivers.
Measurement Techniques for Resistive Sensors. Various measurement techniques can be used with resistive sensors. The
basic requirement for any measurement circuitry is a power
supply to convert the change in resistance into a measurable
output signal. In addition, it is often necessary to custombuild interface circuits for some sensors. For example, we may
be required to add a linearization circuit for thermistors.
Resistance measurements can be made by either the deflection method or the nulling method. In the deflection
method the actual current through the resistance or the voltage across the resistance is measured. In the nulling method
a bridge is used.
The two-readings method is a fundamental approach to resistance measurement. A known resistance is placed in series
with the unknown resistance as shown in Fig. 3. The voltage
is then measured across each of them. The two voltages can

DATA ACQUISITION AND CONVERSION

495

1
VK

RK

CS
Vref p

RU

VU

Vref n

VK =

V
R
RK + RU K

(5)

VU =

V
R
RK + RU U

(6)

where V is the supply voltage, VK and RK are the known voltage and resistance, and VU and RU are the unknown voltage
and resistance. Thus from the above equations RU can be written as follows:

R2
R1

R1

R2
G

R4

R3 = R0(1+x)

Figure 4. Simple Wheatstone bridge measurement method.

ADC

k=

(8)

R1
R
= 2
R4
R0

(9)

Thus the voltage difference between the outputs can be written as follows.
V0 = V

Thus the resistance R3 is directly proportional to the change

required in R4 in order to balance the circuit.

CI

The Wheatstone bridge can also be used for deflection measurement. In this case, instead of measuring the change
needed to balance the bridge, the voltage difference between
the bridge outputs is measured or the current through the
center arm is measured. This method is shown in Fig. 4.
When the bridge is completely balanced (i.e., x 0), k is defined as follows:

(7)

A similar method is the voltage divider, in which the unknown resistance is once again calculated from known voltages and resistances. It is easier to resolve small voltage
changes for low voltages than it is for high voltages. Thus to
measure small changes in resistance, another voltage divider
is placed in parallel to the one with the sensor. The parallel
voltage dividers are designed to give the same voltage for no
input. Thus the signal obtained by taking the difference between their output signals is totally dependent on the measured signal. This method of measuring small changes using
parallel voltage dividers is called the Wheatstone bridge
method (25). A simple Wheatstone bridge measurement
method is shown in Fig. 4.
The Wheatstone bridge is balanced with the help of a feedback system, which adjusts the value of the standard resistor
until the current through the galvanometer is zero. Once this
is done, the value for R3 is given by
R3 = R4

Figure 5. Capacitive sensor interface.

be written as

VU
VK

2
Cref

Figure 3. Two-readings method for resistance measurement.

RU = RK

CI

R4
R3

R2 + R3
R1 + R4

=V

kx
(k + 1)(k + 1 + x)

(10)

The maximum sensitivity for very small changes in x is obtained when k 1.

Capacitive Sensors
Recently capacitive sensor have gained popularity. They generally exhibit lower temperature sensitivity, consume less
power, and provide an overall higher sensor sensitivity with
higher resolution than resistive sensors. For these reasons
they have begun to show up in areas where resistive sensors
were the norm. They are used in many applications such as
pressure sensors and accelerometers. Capacitive sensors typically have one fixed plate and one moving plate that responds
to the applied measurand. The capacitance between two
plates separated by a distance d is given by C A/d, where
is the dielectric constant and A is the area of the plate. It is
easily seen that the capacitance is inversely proportional to
the distance d.
For capacitive sensors there are several possible interface
schemes. Figure 5 shows one of the most common capacitive
sensor interfaces. The circuit is simply a charge amplifier,
which transfers the difference of the charges on the sensor
capacitor CS and the reference capacitor Cref to the integration
capacitor CI. If this interface is used in a pressure sensor, the
sensing capacitor CS can be written as the sum of the sensor
capacitor value CS0 at zero pressure and the sensor capacitor
variation CS(p) with applied pressure: CS CS0 CS(p). In
many applications CS0 can be 5 to 10 times larger than the
full-scale sensor capacitance variation CS(p)max; the reference
capacitor Cref is used to subtract the nominal value of the sensor capacitor at half the pressure range, which is Cref
CS0 CS(p)max /2. This ensures that the transferred charge is

496

DATA ACQUISITION AND CONVERSION

the charge that results from the change in the capacitance.

This results in a smaller integration capacitor and increased
sensitivity.
This type of capacitive interface is insensitive to the parasitic capacitance between the positive and negative terminals
of the opamp, since the opamp maintains a virtual ground
across the two terminals of the parasitic capacitor. This type
of interface is also much faster than most other capacitive
interfaces; its speed of operation is determined by the opamps
settling time. This technique also allows for the amplifiers
offset and flicker noise to be removed very easily by using
correlated double sampling or chopper stabilization. The resolution of this interface is in most cases limited by kT/C noise
and charge injection due to the switches.
There are a number of other sensor types, and two more
will be discussed later in this article. However, we first describe the most common data converters that are used as part
of sensor interfaces.
DATA CONVERTERS
The analog signals generated and then conditioned by the signal conditioning circuit are usually converted into digital
form via an analog-to-digital converter (ADC). In general,
most of the signals generated by these sensors are in the low
frequency region. For this reason, certain data converter topologies are particularly well suited as sensor interface subblocks. These include the charge redistribution implementation of the successive approximation converter, along with
incremental and sigmadelta converters (6). In the following
subsections we shall briefly describe successive approximation (incremental) and sigmadelta converters. Incremental
and sigmadelta converters are very similar and the details
of the former are later described extensively as part of a sample system design.
Successive-Approximation Converter
A block diagram for the successive approximation converter
is shown in Fig. 6. The successive approximation topology requires N clock cycles to perform an N bit conversion. For this
reason, a sample-and-held (S/H) version of the input signal is
provided to the negative input of the comparator. The comparator controls the digital logic circuit that performs the binary
search. This logic circuit is called the successive approximation register (SAR). The output of the SAR is used to drive
the digital-to-analog converter (DAC) that is connected to the
positive input of the comparator.

Vin

S/H

Control
+

Successive approximation
register

DAC

N bit output

Figure 6. Successive approximation converter: block diagram.

During the first clock period the input is compared with

the most significant bit (MSB). For this, the MSB is temporarily raised high. If the output of the comparator remains high,
then the input lies somewhere between zero and Vref /2 and
the MSB is reset to zero. However, if the comparator output
is low, then the input signal is somewhere between Vref /2 and
Vref and the MSB is set high. During the next clock period the
MSB-1 bit is evaluated in the same manner. This procedure
is repeated so that at the end of N clock periods all N bits
have been resolved.
The charge-redistribution implementation of the successive approximation methodology is the most common topology
in metaloxidesemiconductor (MOS) technologies (7). The
circuit diagram for a 4 bit charge redistribution converter is
shown in Fig. 7. In this circuit the binary weighted capacitors
C, C/2, . . ., C/8 and the switches S1, S2, . . ., S5 form the
4 bit scaling DAC. For each conversion the circuit operates as
a sequence of three phases. During the first phase (sample),
switch S0 is closed and all the other switches S1, S2, . . ., S6
are connected so that the input voltage Vin is sampled onto all
the capacitors. During the next phase (hold), S0 is open and
the bottom plates of all the capacitors are connected to
ground, i.e., switches S1, S2, . . ., S5 are switched to ground.
The voltage Vx at the top plate of the capacitors at this time
is equal to Vin, and the total charge in all the capacitors is
equal to 2CVin. The final phase (redistribution) begins by
testing the input voltage against the MSB. This is accomplished by keeping the switches S2, S3, . . ., S5 connected to
ground and switching S1 and S6 so that the bottom plate of
the largest capacitor is connected to Vref . The voltage at the
top plate of the capacitor is equal to
Vx =

Vref
Vin
2

(11)

If Vx 0, then the comparator output goes high, signifying

that Vin Vref /2, and switch S1 is switched back to ground. If
the comparator output is low, then Vin Vref /2, and S1 is left
connected to Vref and the MSB is set high. In a similar fashion
the next bit, MSB-1, is evaluated. This procedure is continued
until all N bits have been resolved. After the conversion process the voltage at the top plate is such that

Vx = Vin + b3

Vref
V
V
V
+ b2 ref
+ b1 ref
+ b0 ref
21
22
23
24
V
ref
< Vx < 0
24


(12a)
(12b)

where bi is 0 or 1 depending on whether bit i was set to zero

or one, and LSB is the least significant bit.
One of the advantages of the charge-redistribution topology is that the parasitic capacitance from the switches has
little effect on its accuracy. Additionally, the clock feedthrough from switch S0 only causes an offset, and those from
switches S1, S2, . . ., S5 are independent of the input signal
because the switches are always connected to either ground
or Vref . However, any mismatch in the binary ratios of the
capacitors in the array causes nonlinearity, which limits the
accuracy to 10 or 12 bits. Self-calibrating (8) techniques have
been introduced that correct for errors in the binary ratios of
the capacitors in charge redistribution topologies. However,
these techniques are fairly complex, and for higher resolu-

DATA ACQUISITION AND CONVERSION

S0

497

+
C

C
2

S1

S2

C
4
S3

C
8
S4

C
8
S5

Vin
Vref

Figure 7. Charge-redistribution implementation of

the successive approximation architecture.

S6

tions sigmadelta converters are the preferred topology. We

now briefly describe sigmadelta converters.
SigmaDelta Data Converters
Oversampling converters sample the input at a rate larger
than the Nyquist frequency. If f S is the sampling rate, then
f S /2f 0 OSR is called the oversampling ratio. Oversampling
converters have the advantage over Nyquist rate converters
that they do not require very tight tolerances from the analog
components and that they simplify the design of the antialias
filter. Sigmadelta converters (9) are oversampling single-bit
converters that use frequency shaping of the quantization
noise to increase resolution without increasing the matching
requirements for the analog components.
Figure 8 shows a block diagram for a general noise-shaping oversampled converter. In a sigmadelta converter both
the ADC and DAC shown in Fig. 8 are single-bit versions and
as such provide perfect linearity. The ADC, a comparator in
the case of a sigmadelta converter, quantizes the output of
the loop filter, H1. The quantization process approximates an
analog value by a finite-resolution digital value. This step introduces a quantization error Qn. Further, if we assume that
the quantization noise is not correlated to the input, then the
system can be modeled as a linear system. The output voltage
for this system can now be written as
V0 =

Qn
V H
+ in 1
1 + H1
1 + H1

(13)

For most sigmadelta converters H1 has the characteristics of

a low-pass filter and is usually implemented as a switchedcapacitor integrator. For a first-order sigmadelta converter
H1 is realized as a simple switched-capacitor integrator, H1
z1 /(1 z1). Making this substitution in Eq. (13), we can
write the transfer function for the first-order sigmadelta
converter as
V0 = Vin z1 + Qn (1 z1 )

Vin

H1

ADC

(14)

V0

DAC
Figure 8. Figure for a general noise-shaping oversampled converter.

As can be seen from Eq. (16) below, the output is a delayed

version of the input plus the quantization noise multiplied by
the factor 1 z1. This function has a high-pass characteristic
with the result that the quantization noise is reduced substantially at lower frequencies and increases slightly at
higher frequencies. The analog modulator shown in Fig. 8 is
followed by a low-pass filter in the digital domain that removes the out-of-band quantization noise. Thus we are left
with only the in-band (0 f f 0) quantization noise. For
simplicity the quantization noise is usually assumed to be
white with a spectral density equal to erms2/f s. Further, if
the OSR is sufficiently large, then we can approximate the
root-mean-square (rms) noise in the signal band by
N f erms
0

2 f 3/2
0

fs

(15)

As the oversampling ratio increases, the quantization noise

in the signal band decreases; for a doubling of the oversampling ratio the quantization noise drops by 20(log 2)3/2 9 dB.
Therefore, for each doubling of the oversampling ratio we effectively increase the resolution of the converter by an additional 1.5 bits.
Clearly, H1 can be replaced by other, higher-order functions that have low-pass characteristics. For example, in Fig.
9 we show a second-order modulator. This modulator uses one
forward delay integrator and one feedback delay integrator to
avoid stability problems. The output voltage for this figure
can be written as
V0 = Vin z1 + Qn (1 z1 )2

(16)

The quantization noise is shaped by a second-order difference

equation. This serves to further reduce the quantization noise
at low frequencies, with the result that the noise power in
the signal bandwidth falls by 15 dB for every doubling of the
oversampling ratio. Alternatively, the resolution increases by
2.5 bits for every doubling of the oversampling ratio. In general, increasing the order of the filter will reduce the necessary oversampling ratio for a given resolution. However, for
stability reasons, topologies other than the simple Candystyle (10) modulator discussed above are required for filter
orders greater than two. Topologies that avoid this stability
problem include the MASH and interpolative topologies (6).
For low-frequency inputs, the white noise assumption for
the quantization noise breaks down. This results in tones
which reduce the effective resolution of lower-order sigma
delta converters. Incremental converters utilize this observa-

498

DATA ACQUISITION AND CONVERSION

Qn
Vin

z1

V0

z1
Figure 9. Modulator
oversampled converter.

for

second-order

tion to simplify the low-pass filter that follows the sigma

delta converter. Details for the incremental converter are discussed below.
We now consider two system design examples. The first is
an acoustic emission sensor system and the second is a temperature measurement system.
SYSTEM DESIGNS EXAMPLES
We illustrate the sensor and sensor interface scenario with
two examples. The first uses a piezoelectric acoustic emission
sensor interfaced with a charge amplifier and a data converter. The second describes an integrated temperature
sensor.
Acoustic Emission Sensing System
Acoustic emission sensors are microsensors that are used for
the detection of acoustic signals. These devices use elastic
acoustic waves at high frequencies to measure physical,
chemical, and biological quantities. Typically, integrated
acoustic sensors can be made to be extremely sensitive and
also to have a large dynamic range. The output of these sensors is usually a frequency, a charge, or a voltage.
The piezoelectric effect is one of the most convenient ways
to couple elastic waves to electrical circuits. Piezoelectricity is
caused by the electric polarization produced by mechanical
strain in certain crystals. Conversely, an electric polarization
will induce a mechanical strain in piezoelectric crystals. As a
consequence, when a voltage is applied to the electrodes of a
piezoelectric film, it elongates or contracts depending on the
polarity of the field. Conversely, when a mechanical force is
applied to the film, a voltage develops across the film. Some
properties of a good piezoelectric film are wide frequency
range, high elastic compliance, high output voltage, high stability in wet and chemical environments, high dielectric
strength, low acoustic impedance, and low fabrication costs.
Piezoelectric materials are anisotropic, and hence their electrical and mechanical properties depend on the axis of the
applied electric force. The choice of the piezoelectric material
depends on the application.

TSM

SAW

FPW

Side
Side

Measurement Techniques. The different modes of use for an

acoustic sensor are summarized in Fig. 12. Using either a resonator-transducer or a delay line, measurements can be made

APM
Top

;
;;

;
;

Top

Crystalline quartz (SiO2) is a natural piezoelectric substance. Some other commonly used piezoelectric materials are
ferroelectric single-crystal lithium niobate (LiNbO3) and thin
films of ZnO and lead zirconium titanate (PZT). Recently, advances have been made in sensor technology with ultrasonic
sensor configurations such as the surface acoustic wave
(SAW) and acoustic plate mode (APM). In SAW devices the
acoustic waves travel on the solid surface, and in an APM
arrangement they bounce off at an acute angle between the
bounding planes of a plate. The main types of acoustic wave
sensors are shown in Fig. 10 (11).
Piezoelectric thin films are particularly well suited for microsensor applications that require high reliability and superior performance. When prepared under optimal conditions
piezoelectric thin films have a dense microstructure without
cracks and holes, good adherence, and good electrical properties. The three most popular materials used for thin films include ZnO (zinc oxide), AlN (Aluminum nitride), and PZT
(lead zirconium titalate). Deposition, sputtering, and solgel
are some of the methods used for preparing piezo films; the
choice depends on the material and substrate used. ZnO thin
films are prepared using laser-assisted evaporation and are
often doped with lithium. Such films have excellent orientation. AlN thin films maintain a high acoustic velocity and are
able to withstand extremely high temperatures. PZT thin
films have a much higher piezoelectric coefficient than ZnO
and AlN.
Recently, it has become possible to generate piezoelectric
thin films with extremely good properties through the solgel
process. This process consists of the following steps: synthesis
of a metalorganic solution, deposition of this solution by spin
coating, and a final heating that helps to crystallize the ceramic film. A cross-sectional view of a thin film PZT sensor is
shown in Fig. 11. The advantages of thin film PZT sensors
include their small size, which allows them to be positioned
virtually anywhere, and their ability to operate at high frequencies.

Side

Top

Bottom

Side

Gold
PZT
Ti/Pt electrode
Poly
Nitride
Si

End

Figure 10. Types of acoustic wave sensors.

Figure 11. Cross-sectional view of a thin film PZT sensor.

DATA ACQUISITION AND CONVERSION

Elastic wave propagation

Delay line

R2

Transducer

R1

Vin
Passive
device
Measure
phase
shift

Active
device

Active
device

Measure oscillation
frequency

499

Passive
device

V0
+

Measure
f, Q, Zin

Figure 12. Different measurement techniques for acoustic sensors.

Figure 14. Voltage amplifier.

on the device itself or incorporated into an oscillator circuit.

There are basically two ways to implement this measurement
technique: active or passive. In the case of passive bulk-wave
resonators, we measure the resonant frequency to infer the
wavelength and hence the velocity. Likewise, for passive delay lines the phase shift between the input and the output of
the transducer, which are separated by a known distance,
yields the velocity. On the other hand, for active resonators
or delay-line oscillators, the frequency can be directly measured with the help of a digital counter.
As an example, let us consider the complete design and
implementation of an integrated acoustic emission sensor
with low-power signal-conditioning circuitry for the detection
of cracks and unusual wear in aircraft and submarines.
Within a health and usage monitoring system, it is necessary
by some means, either directly or indirectly, to monitor the
condition of critical components, e.g., airframe, gearboxes,
and turbine blades. The overall aim is to replace the current
practice of planned maintenance with a regime of required
maintenance. Typical parameters used include stress (or
strain), pressure, torque, temperature, vibration, and crack
detection. In this example, acoustic emission sensors are used
for crack detection. The thin film piezoelectric sensor, coupled
to an aircraft component, senses the outgoing ultrasonic
waves from any acoustic emission event as shown in Fig. 13.
The magnitude of the output signal is proportional to the
magnitude of the acoustic emission event. For our example
design, the acoustic emission signal bandwidth varies from 50
kHz to approximately 1 MHz. Mixed in with the desired
acoustic emission signal is vibration noise due to fretting of
the mechanical parts. However, this noise is limited to about
100 kHz and is easily filtered out.
Due to the acoustic emission event, the piezoelectric sensor
generates a charge on the top and bottom plates of the sensor.

There are two basic methods of interfacing to this sensor. We

can use either a voltage amplifier (Fig. 14) or a charge amplifier (Fig. 15).
In general, the charge amplifier interface provides a number of advantages. First, it is not affected by parasitic capacitances at the input of the amplifier. Second, the output voltage at the piezoelectric sensor is very small. This is because
the piezoelectric material, PZT, that is used for its high piezoelectric coefficient also has a very high dielectric constant. As
shown below, the output voltage is proportional to the charge
and inversely proportional to the dielectric constant:

Output charge
or voltage

0.3 m to 1 m

TiPt
PZT
TiO2TiPt

Outgoing
ultrasonic waves

V =

Q
eSA
eSd
Q
=
=
=
C

A/d

A/d

[The output voltage can also be written in terms of the strain

S, the distance d, the electron charge e, and the dielectric
constant as shown in Eq. (19) below.] For these and other
reasons the charge amplifier interface was selected for our
design example.
The charge amplifier circuit shown in Fig. 15 is in its simplest form. The charge Q and capacitance CS are used to
model the sensor charge and sensor capacitance. The inverting terminal of the operational amplifier is a virtual
ground, and no charge flows into the operational amplifier inputs. Therefore, any charge that is generated across the sensor has to flow into the feedback capacitance Cf . The output
voltage developed across the feedback capacitor is inversely
proportional to the value of this capacitance. The voltage gain
of the circuit is given by the ratio of CS to Cf , and hence, to
obtain high gain, Cf can be made much smaller than CS. This
basic topology has a number of limitations, including low-frequency flicker noise of the amplifier, operational amplifier offset, and long-term drift. Traditionally, correlated double sam-

Cf
Si3N4
Si
Package
wear plate

V0
Q

Cs

Acoustic emission event

Figure 13. Acoustic emission sensor.

(17)

Figure 15. Charge amplifier.

500

DATA ACQUISITION AND CONVERSION

proportional to the square of the signal bandwidth and sensor capacitance.

If, however, bipolar transistors are used to implement the
operational amplifier, the minimum power requirements is
given by

Cf

V0
Q

P = V I = V 2 BW UTC

Cs
V

gm
Figure 16. Modified charge amplifier circuit.

pling and chopper stabilization are used to remove lowfrequency noise and offset. However, as noted earlier, our signal band does not include the frequencies from dc to 50 kHz,
and our maximum signal frequencies are fairly high. Therefore, an alternative design topology shown in Fig. 16 was selected to circumvent the problem.
Here, low-frequency feedback is provided to reduce the effects of offset, long-term drift, and low-frequency noise. In the
modified circuit, a transconductor is connected in negative
feedback. The transfer function of the modified circuit is
given by
s ( gm a gm Cf s)
V0 (s)
=
Qin (s)
Cs Cf s2 + s(Cs gm + gm a Cf ) + gm a gm

(18)

Here, UT is the thermal voltage, which is equal to 26 mV at

room temperature. From this equation it is clear that in the
case of bipolar transistors, the power is linearly proportional
to the signal bandwidth and sensor capacitance. This difference in the power consumption between bipolar and MOS implementations for a signal frequency of 1 MHz is shown in
Fig. 17. Here we note that the power consumption for both
MOS and bipolar implementations increases with increased
sensor capacitance. However, for very low frequencies, the
MOS devices can be operated in weak inversion (WI). In WI,
MOS devices behave very similarly to bipolar devices, and
hence the slopes for weak inversion and bipolar devices are
initially very similar. However, at higher frequencies MOS
devices are forced to operate in strong inversion and hence
consume more power for the same performance.
Next, we consider the design tradeoffs in connection with
device noise.
Noise Analysis. The power spectral density for the wideband gate-referred noise voltage for MOS transistors is given
by
2
VnT
=

In this equation, Cs is the sensor capacitance, Cf is the feedback capacitance of the operational amplifier, gma and gm are
the transconductances of the operational amplifier and the
transconductor. If the higher-order terms are neglected, then
Eq. (18) can be simplified to

1

Cs s
1+
gm a

(19)

From Eq. (19) it is clear that the circuit has the characteristics of a high-pass filter, that is, none of the low-frequency
noise or offsets affect the circuit performance.
Next, we perform a power analysis to analyze the effects
of different design tradeoffs. Both MOS and bipolar transistor
technologies are considered, and power and noise analysis
and design tradeoffs for both technologies are presented.
Power Analysis. If MOS transistors in strong inversion (SI)
are used to implement the operational amplifier, then the
minimum power requirement is given by
P = VI =

V (2 BWC)2
2K W/L

8 kT
3 gm

(22)

Here, k is Boltzmanns constant, T is the temperature, gm is

the transconductance. Likewise, for bipolar transistors the
power spectral density for the wide band input-referred noise
voltage is given by
2
VnT
= 2qIC

(23)

For both MOS and bipolar implementations the total rms

input referred noise is independent of frequency and inversely

MOS
Power (mW)

s
V0 (s)
=

Qin (s)
gm

(21)

0.1

0.01

SI

Bipolar

WI

(20)
0.001

where BW is the signal bandwidth, C is the sensor capacitance, K is the transconductance factor, V is the output voltage, I is the supply current, and W/L is the aspect ratio of the
transistor. From this equation it is clear that the power is

20
40
60
80
Sensor capacitance (pF)

100

Figure 17. Minimum power requirements versus sensor capacitance

for a MOS or bipolar design.

DATA ACQUISITION AND CONVERSION

RMS noise ( V)

1000

100

10

10
Sensor capacitance (pF)

100

Figure 18. Noise power spectral density versus capacitance.

proportional to the sensor capacitance as shown in Fig. 18.

Here, we note that the ratio of the noise spectral density for
the MOS and the bipolar implementations is a constant equal
to four.
In summary we note that: For a MOS implementation the
power consumption is proportional to the square of the sensor
capacitance, whereas for a bipolar implementation it is linearly proportional to the sensor capacitance. On the other
hand, the input-referred noise for both the MOS and bipolar
implementations is inversely proportional to the sensor capacitance. Thus, there is a clear tradeoff between the minimum power consumption and the maximum input-referred
noise. If the sensor capacitance is increased, then the inputreferred noise decreases, but the power increases, and vice
versa. Using the equation above, we can calculate the minimum bound on the power requirements for our application.
For 10 bits of accuracy and a signal bandwidth of 1 MHz, the
minimum sensor capacitance size is 5 pF and the minimum
power consumption is around 500 W.
Next, we provide some simulation and measurement results for our acoustic emission sensor system.
Results. Simulation and measurement results for the
charge amplifier with a sensor capacitance of 100 pF and a
feedback capacitance of 10 pF are shown in Fig. 19. For this
measurement, discrete versions of the sensor and feedback

25
20

Gain (dB)

15

501

capacitors were used. As expected, the signal band gain is

given by the ratio of the sensor to the feedback capacitance,
which is equal to 20 dB. Both measurement and simulation
results agree fairly well with this value. The primary difference between the measurement and simulation results is in
the low-frequency and high-frequency poles. It is expected
that this is largely a result of parasitic capacitances and possibly a lower realized transconductance in comparison with
the simulated value.
The charge amplifier circuit design just described converts
the sensor charge into a voltage. This amplified signal voltage
is then converted to digital form using an ADC. For our implementation a 10-bit fourth-order sigmadelta implemented as
a MASH topology was used. The fourth-order topology was
used to keep the oversampling ratio low, as the signal frequency is fairly high. Details of this implementation are not
included here; interested readers are referred to Ref. 6 for
more information.
Next, we describe a complete temperature sensor system.
Temperature Sensing System
In many control systems, temperature sensors are used as the
primary sensor. Additionally, as most electronic components
and circuits are affected by temperature fluctuations, temperature sensors are often needed in microsensor systems to
compensate for the temperature variations of the primary
sensor or sensors.
Because integrated sensors can be manufactured on the
same substrate as the signal-processing circuitry, most recent
temperature measurement schemes concentrate on integrated
silicon temperature sensors. The resulting smart sensor is extremely small and is also able to provide extremely high performance, as all the signal processing is done on chip before
the data is transmitted. This avoids the usual signal corruption that results from data transmission. The disadvantage of
the smart sensor is that since all the processing is done on
chip, it is no longer possible to maintain the signal preprocessing circuits in an isothermal environment. The on-chip
sensor interface electronics must therefore be temperatureinsensitive or be compensated to provide a temperature-insensitive output.
A smart temperature sensor is a system that combines on
the same chip all the functions needed for measurement and
conversion into a digital output signal. A smart temperature
sensor includes a temperature sensor, a voltage reference, an
ADC, control circuitry, and calibration capabilities. A block
diagram for a smart temperature sensor is shown in Fig. 20.
The use of pn junctions as temperature sensors and for the
generation of the reference voltage signals has been reported
extensively (12,13). A bandgap voltage reference can be gener-

10
Simulated
Measured

Temp.
sensor

ADC

5
10
101

Reference
voltage

CS = 100 pF, Cf = 10 pF
102

103
104
105
Frequency (Hz)

106

Bitstream

107

Figure 19. Small-signal frequency response of the charge amplifier.

Digital
filtering

Control and calibration

Figure 20. Smart temperature sensor.

Digital
output

502

DATA ACQUISITION AND CONVERSION

Therefore, the difference between the two baseemitter voltages (Vbe) is given by

V
Vref = Vbe1 + GVbe

Ic

Vbe = Vbe1 Vbe2 =

Vbe1
+
PTAT cell
Vbe
generator

Vref

GVbe

Vbe2

Temperature

VR =
2

Figure 21. Principle of bandgap reference.

ated with the help of a few pn junctions. The basic principle

for the operation of a bandgap voltage reference is illustrated
in Fig. 21.
The baseemitter voltage Vbe of a bipolar transistor decreases almost linearly with increasing temperature. The
temperature coefficient varies with the applied current, but is
approximately 2 mV/C. It is also well known that the difference between the baseemitter voltages of two transistors,
Vbe, operated at a constant ratio of their emitter current densities, possesses a positive temperature coefficient. At an
emitter current density ratio of 8, the temperature coefficient
of this PTAT (proportional to absolute temperature) source is
approximately 0.2 mV/C. Amplifying this voltage (GVbe) and
adding it to a base-emitter voltage Vbe produces a voltage reference that is independent of temperature. Many circuits
have been developed to realize bandgap voltage references using this principle (14,15). A circuit diagram for one of the
early bandgap reference implementations is shown in Fig. 22
(16).
For an ideal operational amplifier, the differential input
voltage is equal to zero, so that resistors R1 and R2 have equal
voltages across them. Since the voltage across the resistors is
the same, the two currents I1 and I2 must have a ratio that is
determined solely by the ratio of the resistances R1 and R2.
The baseemitter voltage of a diode-connected bipolar transistor is given by Eq. (24) below, where T is the absolute temperature of the junction, Is is the reverse saturation current,
Id is the current through the junction, k is Boltzmanns constant, q is the electronic charge, and n is a constant that depends on the junction material and fabrication technique. To
see this, we write
Vbe =

I + Is
I
nkT
nkT
ln d
ln d

q
Is
q
Is

Vout = Vbe1 +

(24)

(27)

1
2

C2
+

C3

Vref

Vref

R3

CT
Q1

R I
R2 nkT
ln 2 s2 = Vbe1 + G Vbe
R3 q
R1 Is1

R2

I2

(26)

Therefore, this circuit behaves as a bandgap reference, where

the gain factor G is set by the ratios R2 /R3, R2 /R1, and Is2 /Is1.
In many designs R2 R1 and Is2 8Is1. Since the reverse
saturation current Is is proportional to the emitter area, to
make Is2 8Is1 we let the emitter area of Q2 be 8 times as
large as the emitter area of Q1.
The operational amplifiers input-referred voltage offset is
the largest error source in this type of voltage reference. This
voltage offset is highly temperature-dependent and nonlinear,
making an accurate calibration of such a reference virtually
impossible. It is therefore necessary to use some type of offset
cancellation technique such as autozero or chopper stabilization (17).
Another source of error is the nonzero temperature coefficient of the resistors. Usually on-chip resistors are used, in
the form of polysilicon resistors or well resistors. Both of these
resistor implementations tend to occupy very large amounts
of chip area if low power is desired. Low-power implementations demand the use of large-value resistors, which unfortunately require large areas. Though well resistors have a much
larger resistivity than polysilicon resistors, they also have a
very nonlinear temperature coefficient, which makes for difficult calibration.

+
I1

R I
R2
R nkT
ln 2 s2
Vbe = 2
R3
R3 q
R1 Is1

as desired.
The output voltage is the sum of the voltage across R1 and
the voltage across Q1. Since the voltage across R1 is equal to
the voltage across R2, the output voltage is equal to

C2
R1

(25)

This voltage appears across R3. Since the same current that
flows through R3 also flows through R2, the voltage across R2
is given by

Vbe

I I
R I
nkT
nkT
ln 1 s2 =
ln 2 s2
q
I2 Is1
q
R1 Is1

CF
1

CT

Q2

Gnd
Figure 22. Example bandgap voltage reference circuit.

Figure 23. A switched-capacitor implementation of the bandgap reference.

DATA ACQUISITION AND CONVERSION

503

S6
CB
Vin
Vref

S1

CA

S2

S5
S4

S3

II

S1 to S1

ai

Digital
Up
output
down
counter

Switch control
logic

Figure 24. Incremental ADC.

A solution to these problems is to use switched-capacitor

circuits to implement the resistors in the voltage reference
circuit. A switched-capacitor implementation makes offset removal simple and also reduces the power consumption, as the
area occupied by large-value switched-capacitor resistors is
significantly smaller than the area occupied by continuoustime resistors. In fact, the area occupied by switched-capacitor resistors is inversely proportional to the value of the resistance desired. Another advantage is that the temperature coefficient of on-chip polypoly capacitors is much smaller than
that of on-chip resistors, making design and calibration easier. A switched-capacitor implementation of the bandgap voltage reference is shown in Fig. 23.
The structure of this voltage reference is similar to the one
shown in Fig. 22, except that the continuous time resistors
have been replaced by switched-capacitor resistors, and capacitors CT and CF have been added. The switched capacitors
emulate resistors with an effective resistance value given by
Reff =

1
f CC

(28)

where f C is the clock frequency of the switch. The feedback

capacitor CF is designed to be very small and is added to ensure the operational amplifier is never in an open-loop mode
of operation. The capacitors located in parallel with the diodes
act as tank capacitors to ensure that current is constantly
supplied to the diodes. The output of this voltage reference
can similarly be calculated and is given by
Vref = Vbe1 +

C I
C3 nkT
ln 1 s2 = Vbe1 + G Vbe
C2 q
C2 Is1

(29)

which is the desired bandgap voltage reference.

Most temperature-sensing devices also use the difference
between two diodes (Vbe) as the sensing element of the system. Since the temperature coefficient of Vbe is small (0.2

Vin2

2
Vin1

mV/C), it is almost always amplified to a much larger value

(10 mV/C) for increased sensitivity. Since we already have
an amplified value of Vbe in the voltage reference (GVbe), all
that needs to be done is to subtract Vbe1 from the voltage reference to obtain an amplified value of Vbe. If more sensitivity
is needed, the additional amplification can be incorporated in
the ADC by simply adjusting the capacitor ratio of CA and CB
as shown in Fig. 24. Additionally, the subtraction of Vbe1 from
the voltage reference can be easily accomplished with the circuit shown in Fig. 25, where Vin1 is the output of the voltage
reference, Vin2 is equal to Vbe1, and VG is the negative input of
the operational amplifier in the follow-on data converter. During clock cycle 1 the capacitor C is charged to the input voltage Vin2. During clock cycle 2, the charge (Vin1 Vin2)/C is
transferred. This circuit effectively does the voltage subtraction that is needed to obtain the amplified temperature-dependent output voltage (GVbe).
Incorporating the voltage reference and temperature-sensing circuitry shown in Figs. 23 and 25 into a smart temperature sensor system involves some additional circuitry. Since
switched capacitors are already being used for the voltage reference and the sensing circuitry, it makes sense to use
switched-capacitor technology for the ADC. A simple ADC
that utilizes oversampling techniques is the incremental converter (18). The advantage of this data converter topology,
shown in Fig. 24, is its low power consumption, small area,
and insensitivity to component mismatch. Additionally, in
comparison with sigmadelta converters the postquantization
digital low-pass filter is much simpler. It consists of just an
updown counter instead of a more complicated decimation
filter. Unfortunately, the first-order incremental ADC has a
relatively long conversion time, making this converter suitable only for very slow signals such as temperature.
The first-order incremental ADC shown in Fig. 24 is composed of a stray-insensitive switched-capacitor integrator, a
comparator, switch control logic, and an up-down counter. A
four phase nonoverlapping clock as shown in Fig. 26 consti-

VG

Figure 25. Switched-capacitor subtraction circuit.

2
3
4

Integration period
Figure 26. Four-phase nonoverlapping clock.

504

DATA ACQUISITION AND CONVERSION

1
2

C2

C2
VRef

+
2

C3

CT

CF
Q1

Q1

CT

S6
CB
S1

CA

S2

S5

S4
Vbe1

VI

Digital
output
Up
down
counter

ai

Ssub
S1 S6 Switch control
logic

Figure 27. Smart temperature sensor circuit.

tutes an integration period. The integrator output voltage is

designated by VI[i, j], where i corresponds to the current integration period and j to the clock cycle (1, 2, 3, or 4).
During clock cycle 1, S1 and S4 are closed, charging CA to
the input voltage Vin. During 2, S3 and S5 are closed, transferring the charge that was stored on CA to CB. At the end of the
charge transfer from CA to CB the comparator output is denoted by

1 if VI [i, 2] > 0
ai =
1 if VI [i, 2] < 0

Also during 4, the integrator output voltage VI[i, 4] is given

by
VI [i, 4] = VI [i, 1] +

CA
(V aiVref )
CB in

(30)

The final N bit output code, denoted by Dout, that results from
the updown counter is obtained by evaluating the quantity
Dout =

n
1
a
n i=1 i

(31)

During 3, S4 is closed, and if:

Here n is the number of integration periods, and is a function
of the resolution that is required of the ADC.
The complete smart temperature sensor is shown in Fig.
27. The subtraction circuit of Fig. 25 is incorporated into the
ADC by simply adding switch Ssub. The only difference in the
operation of the incremental converter shown in Fig. 27 from
the one shown in Fig. 24 is that now during 2, S3 is not closed
but instead Ssub is closed.

S3 is closed
S2 is closed

During 4, S5 is closed, and if:

ai = 1,
ai = 1,

S2 is closed
S3 is closed

1.4

0.85

1.35

0.80
Vref Vbel (V)

ai = 1,
ai = 1,

Vref (V)

1.3
1.25
1.2
1.15

Figure 28. Measurement results for the (a)

voltage reference, (b) the temperature sensor.

0.75
0.70
0.65
0.60
0.55

1.1
220 240 260 280 300 320 340 360 380
Temperature (K)
(a)

0.50
220 240 260 280 300 320 340 360 380
Temperature (K)
(b)

DATA ACQUISITION AND CONVERSION

505

system was a smart temperature sensor. As feature sizes continue to decrease and integrated sensor technologies progress,
it is likely that extremely smart and high-performance systems will be integrated on single chips. Additionally, significant reduction in power and area as a result of smaller feature sizes will make such systems ubiquitous.
BIBLIOGRAPHY
1. W. Gopel, Sensors in Europe and Eurosensors: State-of-theart and the science in 1992, Sensors Actuators A, 3738: 15,
1993.

Figure 29. Measurement results for the analog-to-digital converter.

The calibration of this system is done in two steps. First

the voltage reference is calibrated by adjusting the ratio of
C3 and C2; next the amplified sensor voltage is calibrated by
adjusting the ratio of CA and CB. Adjusting the ratios of the
capacitors is done with the use of a capacitor array that is
controlled digitally. The output is an N bit digital word.
In Fig. 28 we show measurement results for the voltage
reference and final temperature output. For these results a
first-pass design of the circuit in Fig. 27 was used. This design
was not completely integrated and included external resistors
to obtain gain. We expect final integrated results to behave
similarly. Figure 28(a) shows the reference voltage obtained
as a sum of a Vbe and an amplified Vbe as described in Eq.
(29). The x axis shows the temperature in kelvin and the y
axis shows the measured output reference voltage in volts.
The measured value is fairly close to the expected value except for some small experimental variations. We suspect
these variations are a result of the length of time used to
stabilize the temperature between temperature output measurements. The graph in Fig. 28(b) shows the output voltage,
which is Vref Vbe. As expected, this voltage varies linearly
with temperature. Figure 29 shows the expected 1 bit output
stream (ai shown in Fig. 24) of the sigmadelta converter before the digital low-pass filter. This output corresponds to an
input voltage equal to one-eighth of the reference voltage.
We have provided detailed designs for two complete data
acquisition systems, namely an acoustic emission sensor system and a smart temperature sensor system. We provide both
measurement and simulation results to show their performance.
CONCLUSION
In this article we have provided brief descriptions of data acquisition and data conversion systems. In particular, we provided some general descriptions of integrated capacitive and
resistive sensors. This was followed by descriptions of two of
the most common data converter topologies used in sensor
interface systems, namely successive approximation and
sigmadelta. Finally, these were followed by detailed descriptions of two complete acquisition systems. The first system
was based on a piezoelectric acoustic emission sensor interfaced to a charge amplifier and data converter. The second

2. R. Pallas-Areny and J. G. Webster, Sensors and Signal Conditioning, New York: Wiley-Interscience, 1991.
3. K. Najafi, K. D. Wise, and N. Najafi, Integrated Sensors, in S. M.
Sze (ed.), Semiconductor Sensors, New York: Wiley, 1994.
4. D. H. Sheingold (ed.), Transducer Interfacing Handbook, Norwood, MA: Analog Devices, 1980.
5. R. J. van de Plassche, J. H. Huijsing, and W. M. C. Sansen, Analog Circuit DesignSensor and Actuator Interfaces, Norwell, MA:
Kluwer, 1994.
6. R. Harjani, Analog to digital converters, in Wai-Kai Chen (ed.),
The Circuits and Filters Handbook, New York: IEEE/CRC
Press, 1995.
7. J. L. McCreary and P. R. Gray, All-MOS charge redistribution
analog-to-digital conversion techniquespart I, IEEE J. SolidState Circuits, 10: 371379, 1975.
8. H. S. Lee, D. A. Hodges, and P. R. Gray, A self-calibrating 15
bit CMOS A/D converter, IEEE J. Solid-State Circuits, 19 (6):
813819, 1984.
9. F. Wang and R. Harjani, Design of modulators for oversampled
converters, Norwell, MA: Kluwer, 1998.
10. J. C. Candy and G. C. Temes (eds.), Oversampling DeltaSigma
Data ConvertersTheory, Design and Simulation, New York:
IEEE Press, 1992.
11. S. M. Sze (ed.), Semiconductor Sensors, New York: Wiley, 1994.
12. A. Bakker and J. Huijsing, Micropower CMOS temperature sensor with digital output, IEEE J. Solid-State Circuits, SC-31 (7):
933937, 1996.
13. G. Meijer, An IC temperature transducer with an intrinsic reference, IEEE J. Solid-State Circuits, SC-15 (3): 370373, 1980.
14. S. Lin and C. Salama, A Vbe(T) model with applications to bandgap reference design, IEEE J. Solid-State Circuits, SC-20 (6):
12831285, 1985.
15. B. Song and P. Gray, A precision curvature-compensated CMOS
bandgap references, IEEE J. Solid-State Circuits, SC-18 (6): 634
643, 1983.
16. K. Kuijk, A precision reference voltage source, IEEE J. SolidState Circuits, SC-8 (3): 222226, 1973.
17. C. Enz and G. Temes, Circuit techniques for reducing the effects
of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization, Proc. IEEE, 84 (111): 1584
1614, 1996.
18. J. Robert and P. Deval, A second-order high-resolution incremental A/D converter with offset and charge injection compensation,
IEEE J. Solid-State Circuits, 23 (3): 736741, 1988.

KAVITA NAIR
CHRIS ZILLMER
DENNIS POLLA
RAMESH HARJANI
University of Minnesota

506

DATA ANALYSIS

DATA ACQUISITION SYSTEMS. See MICROCOMPUTER

APPLICATIONS.

DELAY CIRCUITS

127

A delay circuit shifts an input signal in time by a specific

magnitude. In other words, the output of a delay circuit is a
replica of the input, occurring a specific length of time later.
In many situations arising in practice, the specifications (coming from magnitude or bandwidth, for example) are better
met by cascading identical delay circuits. A delay line is so
obtained. Other applications require generating a number of
shifted replicas at arbitrary intervals. This is generally done
by taps placed at the output of every stage of a delay line,
and then a tapped delay line is obtained.
According to this definition, the class of circuits which
must be considered ranges from the most simple resistancecapacitance (RC) stages to finite impulse response (FIR) or
infinite impulse response (IIR) filters able to delay a discretetime signal by a magnitude which is not a multiple of the
sampling interval. Given this wide circuit scope, there is in
consequence a possible overlap with the contents of other articles in this Encyclopedia. In order to minimize this overlap,
the design and implementation of some of these circuits will
be more extensively treated than others.
The article is structured in two well-differentiated sections, as the continuous-time and the discrete time approaches are dealt with separately. Each section has been organized in several subsections. In both cases we address
mathematical modelling, system implementation, and circuitlevel implementation issues. Continuous amplitude signals
(analog signals) and discrete amplitude signals (digital signals) have a very distinct nature and it is well established
that depending on the signal type, the implementation of delay elements follows very different circuit approaches. In consequence, we differentiate the analog and digital domain
when required.
CONTINUOUS-TIME APPROACH
Delay Models
The building of a device which delays a continuous-time signal, xc(t), by an amount, tD, as shown in Fig. 1, is conceptually
simple. There is nothing physically unreasonable with such a
device if tD is positive (the response occurs after the excitation). If we only require that the response be a scaled (by k)
replica without distortion of the excitation occurring tD time
units later, we can define a linear operator, Lc, which yields
its output, yc(t), as:
yc (t) = Lc {xc (t)} = kxc (t tD )

(1)

The delayed signal output response must be zero for 0 t

tD because we analyze the behavior from t 0 onward. In Eq.

DELAY CIRCUITS
There are two forms in which delays can appear in circuits.
First, there are inevitable delays associated with wiring and
physical devices, which are not at the invitation of the designer. However, delays can also be included for very different
purposes and with distinct applications. In this article, we
shall describe the circuits or systems employed for generating
these intentional delays. We will refer to them with the generic term of delay circuits.

y(t) = xc(t tD)

y(t) = xc(t)

T
t

tD

Figure 1. Delaying a continuous-time signal.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

128

DELAY CIRCUITS

(1), k is a constant which represents amplification or attenuation, and perhaps polarity reversal.
Delaying continuous-time signals can be considered in a
suitable transform domain provided by the Laplace transform. The ideal transfer function of such a device can be easily derived as:




Yc (s) =
yc (t)est dt = k
xc (t tD )est dt
0
0


Yc (s) = k
xc ()es(+t D ) d where = t tD
(2)
0


st D
s
st D
Yc (s) = ke
xc ()e
d = ke
Xc (s)
0

Hid (s) = kest D

From Eq. (2), we obtain for ideal distortionless transmission that the transfer function Hid(s), is Hid(s) kestD. This
condition is frequently more useful when expressed in the
frequency domain (-domain) by setting s j. It gives
Hid( j) (kestD)sj kejtD, which expressed in terms of modulus Hid( j), and argument argHid( j) id() allows us to
obtain two properties for the transfer function: first, a constant modulus for all frequencies is required, and second, a
phase shift depending linearly on the frequency, id(), is
needed in order to provide a frequency-independent group delay g():

|Hid ( j)| = k

id () = tD
g () =  () = t
D
id

constant
linear with
constant

Two models of delays are widely used for digital signals. Pure
delays shift the input signal in time by a specific magnitude
tD. This model corresponds to the mathematical operator introduced at the beginning of this section. A second useful
model is the inertial delay. An inertial delay of magnitude tD
shifts the input signal in time by tD and filters out pulses
(both positive and negative) of duration less than tD.
Delay Circuits for Analog Signals
A device implementing distortionless transmission condition
cannot be a finite, lumped linear constant element network,
because its transfer function is transcendental and not rational in s. Ideal transmission lines have such transfer functions
and they are described by partial differential equations.
Hence physical realizations of ideal delay-transfer functions
do exist, although not as networks.
Good approaches for devices implementing distortionless
transmission, however, can be obtained, for example, with allpass filters (1). Table 1 shows the transfer and group delay
Table 1. Transfer and Group Delay Functions for Firstand Second-Order All-Pass Filters
Order
First

Second

Transfer Function
s 0
s 0

s2 0 s 20
Q
H(s)

s2 0 s 20
Q
H(s)

functions for first- and second-order all-pass filters. Both filters satisfy the amplitude condition: they have an amplitude
of 1 for all frequencies. The group delay condition, is only partially fulfilled: the associated group delay is only approximately constant if (/0)2 1 in a first-order all-pass filter,
with the specific properties of this function being controlled
by Q and 0 in a second-order all-pass filter. Hence, for bandlimited signals, all-pass filters can perform as delay sections.
Two or more of these sections can be cascaded to obtain delay
lines. Delay lines using low-pass filters (first- or second-order
follower-integrator sections) have also been proposed for specific applications (2). For such lines, the response at high frequencies will decrease sharply, in a very steep way, but in the
range of application in which they are used, the group delay
is approximately constant in the same conditions as the allpass filters are.
The field of filter design and implementation is the subject
of many other articles in this work, so we do not deal with
the circuit and physical level implementation issues here. We
will just mention that time constants depend on parameters
such as capacitors and transistors which are temperatureand process-dependent; therefore, some extra circuitry is required to control the delay time. Solutions to this problem
resort either to control the delay time by an external voltage
or, more commonly, to locking it to an external reference frequency.

Group Delay Function

g()

2/0
1 (/0)2

g()

2
Q0

1 (/0)2
1
[1 (/0)2]2 2 (/0)2
Q

Delay Circuits for Digital Signals

A different point of view is taken in many applications that
require delaying digital signals. These delay circuits are a key
component of phase locked loops (PLLs) and delay locked
loops (DLLs), which find wide application in wireless and
communication circuits, high-speed digital circuits, disk drive
electronics, and instrumentation, because a number of design
problems can be efficiently solved with them. The main problems that can be solved are jitter reduction, skew suppression, frequency synthesis, and clock recovery. A different and
familiar application area is the control of the timing of a data
sampling or of a generation process. Very fine resolution is
often required in these types of applications. Very large-scale
integration (VLSI) automated test equipment and time measurement systems for nuclear instrumentations are some examples. Finally, another interesting application of these delay
circuits is that of self-timed circuits. Following, a brief review
of the relevant issues and options for these delay circuits is
presented.
Neither pure nor inertial delays can be perfectly realized
in the real world. A real inertial delay of magnitude tD, when
stimulated with pulses of width varying from tD e to tD e
for some small value e 0, produces a continuum of waveforms between a pulse of width tD e to no pulse at all. Real
delays are often better modelled as combinations of the two
types (3). The introduced models produce output waveforms
similar to the input waveforms. This is because both rising
and falling edges are propagated with the same delay. In
practice, delay circuits which have different delays for each
transition are useful for many applications. Also, there is another type of application for which only one transition polarity
is significant. The delay is then used to initiate events at arbitrary times. The response to an input edge or pulse is a fixedwidth pulse after a given time.

DELAY CIRCUITS

129

R2
Vref
Vref
Ramp
generator

Input

R3

Output

Vramp

Ramp
Input

Vin

Vref
Vramp
R1

Output
(a)

Input

Output

C1

(b)

.....

N 1

Output
(c)

Input +
Input

.....

Output
N 1

(d)

Because of the impossibility of ideal delay elements, a set

of figures of merit (4) are used to specify delay circuits in addition to nominal delay:
1. Bandwidth or maximum usable input signal frequency
(In many cases it is not limited by the functional failure
of the delay but by the accuracy degradation due to
what is called history effects or pulse memory. The delay of a signal edge is perturbed by the presence of other
edges in the recent past.)
2. Tolerance of nominal delay
3. Temperature coefficient of nominal delay
4. Voltage coefficient of nominal delay
5. Jitter or random variation in the delay of different
edges due to noise (It can be evaluated by maximum
error or by the standard deviation of errors.)
Basically, continuous digital signals can be delayed using
passive transmission lines which behave roughly as a pure
delay element, RC delays or logic gates. Transmission lines
can be used at the PC board and hybrid levels. Here, we focus
on delay circuits to be included with other elements within an
integrated circuit (IC). Figure 2 shows different generic ways
of realizing delays together with common ways of implementing their building blocks. The ramp and comparator approach
is depicted in Fig. 2(a). A transition of the input signal makes
a voltage ramp, Vramp, start from a stable initial level. The
ramp and a control voltage, Vref , are applied to the inputs of
a high-speed comparator, which switches at a time proportional to the control level. Fig. 2(b) shows a conventional RCdelay circuit for implementing the approach just described.
When the input signal Vin rises, the node Ramp starts to discharge through R1. The simplest method for delaying a digital

Output +

Figure 2. Generic schemes for delaying digital signals: (a) The ramp and comparator approach; (b) conventional RC delay element; (c) single-ended gate
chain; and (d) differential gate chain.

signal, an RC stage with input and output buffers, can be

viewed as a particular case of this generic scheme. The reference voltage is now the threshold voltage of the output buffer.
Another variation substitutes the comparator for a monostable circuit.
Logic gates are an obvious and almost universally available delay medium. Chains of logic gates are widely applied
to delay signals as shown in Figs. 2(c) and 2(d). The nominal
delay depends both on the delay of each cell and on the number of stages. When single-end gates are the basic cell of the
chain, inverting gates are usually used in order to balance the
propagation time of rising and falling edges which can affect
the accuracy of the delay element. Differential circuits techniques [Fig. 2(d)] are extensively used for several reasons.
First, differential gates achieve a high rejection of noise; secondly, they reduce edge dependency. In general, reduced
swing differential circuit techniques are a good choice because
they also allow maximize bandwidth. Finally, the functionality of the basic delay cell can be other than that of a buffer,
depending on the application. For example, exclusive OR
(XOR) gates and latches have been used in pattern generation
and time measurements systems (5,6).
Programmable or adjustable delays, that is, delays depending on one or more control inputs, are interesting for
many reasons. Devices that can satisfy a wide range of applications and that can be of manual or automatic calibration
are the main ones. Control inputs can be digital or analog.
The specification of these delays requires additional variables
such as range of available delays, resolution, tolerance and
stability of range, and linearity (4).
There are three different strategies for realizing controllable delays which are summarized in Fig. 3. The first one consists of selecting one of several fixed delay paths between in-

130

DELAY CIRCUITS

Input

Fixed delay
D1

Input
MUX
Output

Fixed delay
D2

Fixed
delay
D1

Fixed
delay
D2

MUX
Output

Sel

Sel

(a)

(b)

Input

Variable delay

Output

Delay control
(c)

Input

Figure 3. Generic methods for realizing

variable delays: (a) Selectable path approach, parallel implementation; (b) selectable path approach, serial implementation; (c) variable delay fixed path
approach; (d) delay interpolation.

put and output. Figures 3(a) and 3(b) show two possibilities.
Care must be taken to match the delays in all paths in the
selector logic. This can be critical if selectable delays differ
little or in certain applications. In the second approach [Fig.
3(c)], the physical path of the signal remains constant but its
delay is varied. A third approach, called delay interpolation,
uses two paths with different delays in parallel. The total delay is an adjustable weighted sum of the delays of the two
paths as shown in Fig. 3(d).
In Fig. 3(c), the delay is tuned by the control input. The
Vref input of the ramp and comparator delay circuit can be
used as the control input in order to build a variable delay
element. This approach is popular because of its flexibility
and naturally linear response. A different strategy is used in
the circuit shown in Fig. 4(a) (2), where the control input,
Vctrl, affects the slew rate at node V1 instead of the triggering
voltage. Starting with Vout low, when Vin becomes active, current Iin charges C1 until Vout triggers. The delay is inversely
proportional to Iin which depends on Vctrl. This element has
been used in an adaptative delay block which exhibits a high
pull-in frequency range partially because the transistor M1
operates in the subthreshold region (7).
In gate-based delay generators, control can be accomplished through capacitive tuning or resistive tuning of the
basic delay stages which form the chain. Figures 4(b)4(e)
show different methods of implementing capacitive-tuned
variable-delay elements. These techniques vary the capacitance at the output node. The generic circuit shown in Fig.
4(b) uses a voltage-controlled resistor to control the amount
of effective load capacitance seen by the driving gate. Figure
4(c) shows a metal oxide semiconductor (MOS) implementation of this approach (8,9). Transistor M2 has its source and
drain shorted together forming an MOS capacitor. The effective capacitance is larger as Vctrl increases and the resistance

Fixed delay
D1
+
Fixed delay
D2

Output
Weights' control

(d)

of transistor M1 is reduced. It can exhibit a poor linearity if a

wide delay range is required. Figure 4(d) employs a voltagecontrolled capacitor. This capacitor can be a reversed biased
pn junction diode. A different option with digital control (10)
is depicted in Fig. 4(e). Node OUT is loaded by m pairs of
pn load devices. When the ith enable line is low, the capacitance load that the pair of devices present to node OUT is
minimal because inversion layer cannot be formed for any
voltage on OUT. When the ith enable line is high, the capacitive load that the pair presents is maximal, because an inversion layer can be formed under the gate of one or both of the
pn devices.
Resistive tuning approaches use variable resistances to
control the current available to charge and discharge the
load capacitance. A classical example is the current-starved
inverter shown in Fig. 4(f). Voltage Vctrl controls the ON
resistance of transistor M1 and through a current mirror,
the transistor M2. Delay decreases as Vctrl increases,
allowing a large current to flow. A Schmitt trigger followed
by a buffer can be included to achieve fast rising and falling outputs (11). If a simple current mirror is used, the
delay is a very nonlinear function of the control voltage.
Moreover, its high gain coefficient (steep slope of delay
characteristic) makes it sensitive to noise on the control
voltage line. The linearity of the delay characteristic in the
current-starved inverter can be improved by using more
complex current mirror configurations (12).
Resistive tuning of differential delay elements is also possible. Other parameters such as the logic swing or dc gain are
controlled in addition to the effective load resistance. Figure
4(g) depicts the generic structure of a number of reported circuits (5,1315). Clearly, the delay of the generic differential
gate can be changed with the voltage Vc1, since the effective
resistance of the load changes with this control voltage. Also,

DELAY CIRCUITS

Vin
Iin

V1

Vout

M1
Vctrl

C1
Vbias

(a)

Vin

Vout

Vin

Vout

Vctrl

Vctrl
(d)

C1
(b)

Vin

OUT

Vout

Vin

Vctrl

M1
Enable[1, m]
M2
m cells
(e)

(c)

Differential gate

M2

Vctrl
Vc1

Vout

Vin

Load

Biasing
circuit
Vin+

M1

Vctrl

(f)

Load

Vin

Vc2

(g)

Figure 4. Voltage-controlled variable delay elements: (a) Variation of the ramp-and-comparator

technique; (b) capacitive tuning using voltage-controlled resistor; (c) MOS implementation for
(b); (d) capacitive tuning using voltage-controlled capacitance; (e) digitally controlled MOS implementation for (d); (f) conventional resistive tuning circuit or current-starved inverter; (g) resistive
tuning of differential gates.

131

132

DELAY CIRCUITS

Vc2 can vary the delay of the gate as it adjusts the tail current.
The biasing circuit generates Vc1 and Vc2 from Vctrl. One of the
two voltages, Vc1 or Vc2, may be nominally equal to Vctrl. The
biasing block produces the appropriate value for the other
bias in order to control the parameters previously mentioned.
This can be done by implementing the replica biasing concept
in which a copy of the delay cell, a differential amplifier, and
feedback are used. Also, the noise insensitivity of the delay
cell is improved with this technique, as the appropriate bias
voltage values are generated independently of supply voltage
variations. Finally, resistive tuning allows fully differential
approaches. That is, the control path is also differential. Partially because of this feature, resistive tuning has been identified as the most suitable for implementing voltage-controlled
ocillators (VCOs) (16).
An important consideration in designing accurate delay elements is to compensate for variations in process, temperature, and supply voltage. Some of the delay circuits described
use an RC time charge constant and generate delays almost
independent of MOS transistor characteristics. The delay deviations due to these ambient and process conditions are
lower than those of a chain of single-ended conventional inverters (17). This sensitivity has been further reduced by
making the charging current proportional to the reference
voltage, Vref (18). Thus, even if the reference voltage fluctuates
as the result of supply-voltage, temperature, and device parameter variations, the current charging the capacitor compensates it, so the delay is constant.
In general, there are several ways to improve the stability
of delay circuits. Actions can be taken at different levels in
order to achieve the desired stability. In the architectural domain, a useful approach is to use adjustable delay elements
and continuously control them with a feedback mechanism.
Phase and delay locked loop techniques have been widely
used. For example, a DLL can be used to maintain the accuracy of a chain of delay elements through which a periodic
signal (clock) is propagating (5,6,8,9). The effect of the DLL
approach is that two taps of the voltage-controlled delay line
(VCDL) driven by a clock reference are examined, and the
delay element control voltage (Vctrl) is adjusted until the two
taps are in phase. Different delay values within the range
of the delay elements can be maintained with different clock
frequencies and different selections of the taps. This concept
has been applied to tuning in production, calibration, and active delay regulation. In some cases, a pair of matched VCDLs
that depend on a common Vctrl are used. A feedback circuit
can make the delay of a reference chain match an external
time signal. The second line is the functional delay generator
which is also stabilized. Physical design techniques which can
reduce the effect of process and temperature gradients within
the chip, on-chip voltage, and temperature regulation and optimization of the gates for delay insensitivity can also be considered.
Noise is common to all electrical systems and it appears in
digital circuits primarily as timing jitter. Jitter can be reduced by careful application of the standard noise decoupling
and isolation techniques: guard rings, for example. Also, the
use of differential circuits and replica biasing circuits helps
reduce the sensitivity to noise.
Delays can be combined in various ways in order to extend
the range or the resolution. A serial connection of a selectedpath delay and a constant-path variable-delay stage may

have a wide range and fine control of rising and falling delays.
Other schemes can be used to improve the resolution of a
chain of delay elements, which is limited to the basic delay of
one or two (if single-ended, inverting gates are used) of its
stages. They include delay interpolation performing an analog
sum of consecutive taps. Precise delay interval generators
with subgate resolution have been proposed based on a series
of coupled ring oscillators (19) and using an array of similar
DLLs with a small phase shift between them (12).
DISCRETE-TIME APPROACH
Delay Models
Discrete-time signals are obtained by sampling a continuoustime signal at discrete times [Fig. 5(a)] or they are directly
generated by a discrete-time process. Delaying a uniformly
sampled bandlimited (baseband) signal presents several major differences when compared with the continuous time addressed previously. If we simply convert Eq. (1) into discrete
time by sampling the continuous signal at time instants t
nT, where n is an integer and T is the sampling interval, then
we obtain:
y[n] = L{x[n]} = kx[n D]

(3)

If D is an integer (when tD is a multiple of the sampling interval), the output value is one of the previous signal samples,

y(t) = xc(t)

x[n]

T
t

n
(a)

y(t) = xc(t tD)

tD

y(n) = x[n D]

y[n] = x[n D]

y(t) = xc(t)

tD

(b)

(c)

Figure 5. Delaying a discrete-time signal: (a) Sampling a continuoustime signal at discrete times; (b) delaying a discrete-time signal by an
integer D; (c) delaying a discrete-time signal by a noninteger D.

DELAY CIRCUITS

and consequently, we have a delay of D samples [Fig. 5(b)].

But if D is not an integer, Eq. (3) has no formal meaning
because the output value would lie somewhere between two
samples, and it is impossible [Fig. 5(c)]. Other important differences with the continuous time problem are related to the
necessity of clocking and the occurrence of aliasing effects.
In a similar way to the continuous-time case, delaying discrete-time signal can be considered in a suitable transform
domain: the z-domain. An ideal transfer function in this domain can be obtained formally as:

Y (z) = k
Y (z) = k

x[n D] zn

n=

x[m] z(m+D)

where m = n D

m=

Y (z) = kzD

(4)

x[m] zm = kzD X (z)

and so, the ideal impulse response is obtained as:

hid [n] = k

for all n

sin[ (n D)]
(n D)


sin[ (n l D)]
y[n] = k
x[l]
(n l D)
l=
y[n] = x[n] hid [n] = x[n] k

which strictly holds only for integer values of D. The term

kzD represents an ideal discrete-time delay system in the zdomain, which performs the bandlimited delay operation at
the specified sampling rate.
As the specifications are usually given in the frequency domain, it is interesting to obtain the response frequency (Fourier transform) of the ideal delaying system we are concerned
with. It is determined from Eq. (4) by setting z ej, where
2f T is the normalized angular frequency, which give us
Hid(ej) kejD. This system has constant magnitude response, linear phase, and constant group delay:

|Hid ( j)| = k
id () = D

g () = id () = D

sin[ (n D)]
(n D)

(6)

The impulse response in Eq. (6) is now an infinitely long,

shifted, and sampled version of the sinc function. We have
here a fundamental difference with the continuous-time approximation problem. Causal continuous-time delays are always causal and bounded input-bounded output (BIBO) stable whereas in the discrete-time problem for fractional sample
delays, neither of these properties hold: hid[n] is noncausal
and is not absolutely summable. This noncausality makes it
impossible to implement it in real-time applications.
The output of the system for an input x[n] can be formally
obtained as:

m=

Hid (z) = kzD

133


(7)

constant
linear with , || <

that is, input samples spread over all the discrete-time values
weighted by appropriate values of the sinc function. Results
obtained in Eq. (7) have important consequences: ideal fractional delays are impossible to implement and any system intending to do an emulation of this delay must be alike to the
ideal response in some meaningful sense. Ideal fractional delays can be approached by using finite-order causal FIR or
IIR filters. An excellent tutorial on fractional delays can be
found in Ref. 20.

constant in the whole frequency

band

Unit Delay Circuits

with periodicity 2 in assumed.

The inverse Fourier transform of Hid(e j) is the impulse response. In case of a delay D taking an integer value, the impulse response is a single impulse at n D: that is, hid[n]
k[n D], where [ ] is the Kronecker delta function. The
system simply shifts (and scales by k) the input sequence by
D samples:
y[n] = x[n] hid [n] = x[n] k[n D] = kx[n D]

(5)

When D is a noninteger value, appropriate values of y[n] on

the sampling grid must be found via bandlimited interpolation. This problem has a straightforward interpretation as a
resampling process: the desired solution can be obtained by
first reconstructing the bandlimited signal, shifting it, and
finally resampling it.
To obtain the impulse response corresponding to a system
able to give us the frequency response required, we use the
inverse discrete-time Fourier transform:


1
hid [n] =
H (e j )e jn d for all n
2 id


k
hid [n] =
e jD e jn d
2

This section is mainly devoted to the implementation of the

z1 term, identified in the previous section with the bandlimited unit delay operation at the sampling rate we are interested in. This term is a basic block in the realization of any
discrete delay. In the case of integer delays, zN can be implemented by cascading N unit delay elements. In case of a fractionary delay, this must be approximated by a filter whose
realization also needs these integer delays (besides arithmetic elements).
Analogous to the continuous-time case, approximations to
the implementation of the z1 term depend on the type of application we are interested in. Thus, digital and analog approximations will be treated separately.
Digital Implementations. Delays are realized using digital
storage devices or memory cells to store data during a sampling period. There are different ways of implementing these
delay operators depending on both architectural and circuit
choices.
From an architectural point of view, a widely used approach for implement a delay line of N clock cycles employs a
shift register. A shift register is a linear array of storage devices, such as flip-flops or latches, with the capability of exe-

134

DELAY CIRCUITS

Din

1D
C1

1D
C1

1D
C1

....

1D
C1

Out

(a)
Din
1
2

1D
C1

1D
C1

1D
C1

1D
C1

.... 1D
C1

1D
C1

Out

(b)
Figure 6. Implementation of zN with shift register: (a) one-phase
clock; (b) two-phase clock.

cuting right shifts of one position. Figure 6 shows shift register structures for different clocking strategies. The one in Fig.
6(a), employs flip-flops as basic units in a one-phase clock
scheme. In Fig. 6(b), the architecture when using a two-phase
clock scheme and latches is shown. Data present at the Din
input of the registers (Fig. 6) will be available in the output
OUT after N cycles and so OUT[n] Din[n N] as required.
We briefly summarize the different available approaches
to the circuit realization of memory cells. An excellent treatment can be found in Ref. 21. The memory cells can be implemented as static or dynamic circuits. The first approach uses
positive feedback or regeneration. That is, one or more output
signals are connected to the inputs. A second approach uses
charge storage as a means of storing signal values. This approach, which is very popular in MOS designs, has the disadvantage that the charge tends to leak away in time. Thus,
there are restrictions on the sampling frequency used: it must
be high enough so that the state is not lost. Figure 7 shows
several CMOS memory cells suitable for register architectures. Note that flip-flops suitable for one-phase register architectures can be realized by cascading two latches operating
on complementary clocks, in what is called a masterslave
configuration.
The circuit depicted in Fig. 7(a) is a static latch. It consists
of a cross-coupled inverter pair. The extra transistors are
used to store the value of Din when the clock is high. Let us
consider the case when Q is high and D is zero: in this situation with high, and the appropriate sizing of transistors
M1, M2, and M3, Q is brought below the threshold of the inverter M5 M8. Then, the positive feedback forces Q to be zero.
Although these latches have reduced noise margins and require careful design, they are small and can be very fast.
In Fig. 7(b) a pseudostatic latch is shown. The feedback
loop is closed when is high. In this mode, the circuit behaves as a biestable element. When the clock goes high, the
loop opens and the input value is stored in the internal capacitor. It is called pseudostatic because frequently 1 and 2, as
shown in the figure, are used to control the pass transistors in
order to avoid overlapping of both phases even if clock routing
delays occur. During 12 the circuit employs dynamic storage.
A fully dynamic approach is less complex, as illustrated in
Fig. 7(c). Only three transistors are required to implement a
latch. Possible variants for circuits in Figs. 7(b) and 7(c) include using complementary transmission gates instead of
NMOS pass transistors. Also, versions of these latches can be
built adding level-restoring devices, as illustrated in Fig. 7(d).
Figure 7(e) shows the C2MOS latch. This circuit operates
in two modes. With high, it is in the evaluation mode be-

cause it acts as an inverter (transistors M3 and M4 are ON).

With low it is in the hold or high-impedance mode and so
Q retains its previous value stored in the output capacitor,
CL. This structure presents advantages over both the pseudostatic and the fully dynamic latches. These two require the
availability of two nonoverlapping clocks (four if complementary transmission gates are used) for correct operation of a
cascaded configuration. Ensuring the nonoverlapping condition might involve making 12 large, which has a negative
impact on circuit performance, or generating the required
clocks locally, which increases area. The operation of a cascaded pair of C2MOS latches controlled by 1 and 2, respectively, is insensitive to overlap as long as the rise and fall
times of the clock edges are small enough. The C2MOS latch
is useful for high speed as, in that case, it is hard to avoid
clock overlap.
Finally, memory elements with a single clock have also
been proposed. Figure 7(f) shows a single clock version of the
circuit depicted in Fig. 7(e). With high, it corresponds to a
cascade of two inverters and so it is transparent. With low,
no signal can propagate from its input to its output. This circuit is called a true single-phase clock latch (TSPC latch) and
is the basis for the TSPC logic design methodology. Figure
7(g) depicts a positive edge-triggered flip-flop built using p
versions of the TSPC latch in Fig. 7(f).
Another approach to implement a delay line is based on
a multiport random access memory (RAM) which is used to
simulate a shift register. The selection of the most convenient
technique (shift-register or multiport RAM memory) depends
on the application.
Analog Implementations. We must essentially consider two
approaches to analog discrete-time signal processing:
switched-capacitor (SC) and switched-current (SI) techniques.
Switched-capacitor techniques are extensively used in mixedmode designs and SC delay-stages circuits have found applications in the implementation of sampled analog filters based
on digital filter architectures as well as in the realization of
interpolators and decimators. The high-quality capacitors
needed are generally implemented using two polysilicon layers. Recently, the SI technique has appeared as an alternative
to SC techniques that is fully compatible with digital CMOS
standard processes. More details about these techniques can
be found in Refs. 22 and 23.
Switched-Capacitor Techniques. If SC techniques are employed, delay elements can be realized in a simple way: by
cascading two sample-and-hold (S/H) elements provided there
are complementary clocking phases. If the output is sampled
at the clock phase 1 and the input signal at the beginning of
the phase 1, then it is possible to use only one S/H element.
Figure 8(a) shows the simplest configuration of an S/H element in which a voltage signal vin is sampled and held in a
linear capacitor Ch through the switch controlled by clock .
Noise and unbalanced charge injection are the major sources
of error in this configuration, and some compensatory techniques can be employed to reduce the switch-induced error.
The signal source can be isolated from the capacitor load
by using an op-amp as a voltage follower. Avoiding any
loading of the holding capacitor by an output circuit can be
realized in a similar way. Configurations following this idea
are sensitive to the offset voltages of the amplifiers. A feed-

DELAY CIRCUITS

M5

135

M1
Q

M6

Din

M7

M8

M4

M2
M3

(a)
Q
Din

12
(b)

M2

Din

Din

Din

M4
Q

M3

CL

M1
(c)

(d)

(e)

Q
Din

Din

(f)

(g)

Figure 7. CMOS memory cells suitable for register architectures: (a) Static latch; (b) pseudostatic latch; (c) fully dynamic latch; (d) fully dynamic latch with level restoring device; (e)
C2MOS; (f) TSPC latch; (g) positive edge-triggered TSPC flip-flop.

back loop around the hold capacitors can be used to reduce

this offset error, as shown in Fig. 8(b), where offset and
common mode error of the output follower are reduced by
the gain of the first op-amp. However, the offset of the first
op-amp appears at the output. Further improvements in
both speed and accuracy are obtained in the configuration

shown in Fig. 8(c), when the second op-amp is connected

as an integrator.
Figure 8(d) shows a configuration with an autozeroing feature which can be used to solve the problems related with the
offset voltage. This S/H circuit also has unity-gain and is offset free and parasitic capacitance insensitive. Another inter-

136

DELAY CIRCUITS

Vout

+1
Vin

Vin

Ch

Vout

Vin

Ch

(a)

Ch

(b)

Vout

(c)

Ch

V
out

Vin

Vin

Ch2

Cs

Ch1

Voff

Voff

(d)

1
2

2
C1

CF

Vin

A=1

(e)

V
out

2
Vout

C1

CF

Vin

Vout

2
1

C2 = C1 + CF

(f)
(g)
Figure 8. Switch capacitor configurations: (a) Elementary sample-and-hold (S/H) element; (b)
S/H amplifier configuration with feedback loop; (c) S/H amplifier configuration with integrator;
(d) offset and parasitic free unity gain S/H stage; (e) offset- and gain-compensated unity gain
S/H stage; (f) basic configuration S/H gain stage; (g) switch-induced error compensated S/H
gain stage.

esting configuration is shown in Fig. 8(e), where the voltage

amplifier has approximate unity-gain ( denotes the gain error) and an auxiliary hold capacitor Ch2 is used to provide
compensation of the gain and the offset voltage of the amplifier. Both structures use a technique usually known as correlated double sampling (CDS): the offset voltage of the op-amp
is measured in one of the clock phases, stored in the capacitors, and then substracted in the subsequent signal amplification clock phase. This technique eliminates the offset voltage and additionally reduces the low-frequency 1/f noise and
the power supply noise. Switch-induced errors and other parasitic effects such as power supply noise and common-mode
signals can be drastically reduced by employing fully differential configurations.
These configurations provide unity gain. If an S/H stage
with arbitrary positive gain is required, we can resort to the
circuit shown in Fig. 8(f), which also uses the CDS technique.
Assuming there is an infinity op-amp gain, the circuit operation is as follows: During clock phase 1, it operates as a
unity-gain voltage follower (both inverting input and output
are short circuited). Capacitors CF and C1 are charged to the
offset voltage and to the input voltage minus the offset voltage, respectively. Next, during clock phase 2, the capacitor
C1 is discharged through CF, giving an output voltage which

is independent of the op-amp input offset voltage. Improvements in eliminating the switch-induced voltage error at the
expense of doubling the total amount of required capacitance
can be obtained with the configuration shown in Fig. 8(g),
where CDS technique has been again applied. It adds an appropriate network (capacitor C2 and switch controlled by 1)
to the noninverting input of the op-amps in order to cancel
the signal injected at the inverting terminal by the clock feedthrough. However, a switch-induced voltage error remains,
which is determined by the mismatching of the switches and
capacitors and the common mode rejection ratio (CMRR) of
the op-amp.
To obtain an analog delay line of N clock periods we only
need to connect in cascade N delay elements. The cascading
of delay elements transfers errors due to such effects as gain
mismatch, offset voltage, or clock feedthrough from stage to
stage, accumulating them and limiting the maximum possible
number of S/H stages in the cascade.
Another approach employs a parallel of N S/H elements
rather than a cascade implementation, as shown in Fig. 9.
It is composed of N channels, each one containing an S/H
stage with a unity gain buffer and an array of switches
controlled by the clock sequence shown in the figure. The
S/H stages sequentially sample the input signal and hold

DELAY CIRCUITS

vin(n)

1
1

C1

1
3

C2

2
3

.
.
.

N
1
CN

vin(n (N 1))

...

N
1

.
.
.

.
.

1
1

vin(n)
vin(n )
. vin(n 2)

.
.
.

137

2
3

.
.
.

it for the next N clock cycles: thus, the errors are added
only once. Errors caused by the unity gain buffer are minimized by connecting the S/H stages in a feedback loop of
a single time-sharing op-amp. Errors in the S/H stages are
greatly reduced because they are divided by the gain of the
op-amp. Errors due to the offset voltage and the finite gain
of the op-amp are not compensated but they likewise affect
all the outputs.
Switched-Current Techniques. In SI techniques, delay elements are simply made by cascading memory cells. Topologies
used for delay elements are included in one of two categories:
the current-mode track-and-hold (T/H) and the dynamic current mirror. The current-mode T/H delay is shown in Fig.
10(a). A digital clock signal switches ON and OFF switch S,
which, when ON, shorts the gates of transistors T1 and T2,
and the circuit functions as a current mirror: with an input
iin applied to the drain of T1, the output iout tracks such input
current. When the switch is turned off, the gates of T1 and
T2 are disconnected, and the gate voltage of T1, corresponding
to the input current value in this moment, is sampled on
Cgs2. Voltage Vgs2 remains constant while the switch is open,
and so the output current is held at a constant value which
is the input current value in the instant when the switch
was opened.
An important drawback of this circuit refers to the exact
reproduction of the input current at the output: it depends
on the matching of the two transistors T1 and T2 and the
two bias current sources J1 and J2. This disadvantage is
solved by the second generation of memory cells, the dynamic current mirror or current copier, by using only one
transistor for both input and output of current, as explained in the following.
The conventional SI memory cell is shown in Fig. 10(b). It
can achieve current memory in the transistor T1 when driven
by the clock waveforms of Fig. 10(c). Its operation is as follows: on phase 1, switch S1 is closed and current iin adds to
the bias current J flowing into the circuit. Current J iin
begins to charge the initially discharged capacitor Cgs1. As
Cgs1 charges, the gate-source voltage Vgs of T1 increases and

Figure 9. SC delay line and clock sequence

controlling it.

when it exceeds its threshold voltage, T1 conducts. Eventually, when Cgs1 is fully charged, all of the current J iin flows
in the drain of T1. On phase 2, switch S1 is opened and the
end value of Vgs when 1 finishes is held on capacitor Cgs1 and
it sustains the current J iin flowing in the drain of T1. As
the input switch is open and the output one closed, there is a
current imbalance which forces an output current, iout iin,
to flow throughout phase 2.
A delay cell comprises two cascaded current memory cells
with the phase reversed on alternate memory cells. A delay
line of N clock periods could be generated by cascading N delay cells (2N memory cells), as shown in Fig. 10(d). Another
approach uses an array of N 1 memory cells in parallel, as
shown in Fig. 10(e). By using the clock sequence shown in the
figure, on clock phase i, memory cell Mi acquires the input
current and memory cell Mi1 releases its output, for i 0,
. . ., N 1. On phase N, cell MN receives its input signal
and cell M0 delivers its output.
Actual operation of the basic memory cell deviates from
the ideal behavior due to transistor nonidealities which degrade the performance of the cell. Previous structures for the
delay line inherit these problems: if the memory cell has
transmission errors (which occur through conductance ratio
errors and charge injection errors) or signal-to-noise ratio errors, then the serial solution increases both by a factor of
2N; in the other solution, errors are the same as those of the
memory cell, but two extra problems arising from the parallel
nature of the structure can be found. One problem comes from
unequal path gains and the other from nonuniform sampling.
The degree of importance of both problems is different: very
close path gains are obtained as transmission accuracy is not
achieved by component matching. Nonuniform sampling
could be carefully considered if the cell is used for the sample
and hold function. An additional drawback of that structure
results from leakage which discharges Cgs during the N clocks
between sampling and output.
Some of these error sources can be controlled by a precise
choice of transistor sizes and currents, in particular those
coming from mismatching, charge injection, conductance ra-

138

DELAY CIRCUITS

Vdd

Vdd

J1

J2

Vdd

iin

iout

iin

iout

1
T1

1
T2

S
Cgs2

S1

T1
Cgs1

T
(a)

(b)

Unit delay #1

Unit delay #N

J
2

(c)

J
2

iin

iout

M11

M12

MN1

MN2

(d)

Vdd
J

iin

N 1

iout

0
0

M0

M1

1
N

MN

(e)
Figure 10. Switch current (SC) configurations: (a) Track-and-hold delay; (b) memory cell with
a single transistor; (c) clock waveforms; (d) serial delay line; (e) parallel delay line.

DELAY SYSTEMS

tios, settling, and noise. However, if we are interested in

achieving a performance in terms of precision, dynamic range,
and linearity, which is competitive with state-of-the-art SC
circuits, a different approach must be taken by resorting to
circuit techniques.
At present, main circuit techniques use either negative
feedback techniques or fully differential structures. Feedback
techniques are specially indicated to reduce conductance ratio
errors and increase dynamic range. Two groups can be considered depending on how negative feedback is applied in the
memory cell. The first one includes the op-amp and the
grounded-gate active memory cells, which use feedback to increase the input conductance by the creation of a virtual earth
at the input. Op-amp option can make monotonic settling difficult to achieve, and this behavior is improved if the op-amp
is substituted by a grounded-gate amplifier. Conductance error improvement is similar but the dynamic range is a little
better than that of the basic memory cell. In the second group,
negative feedback is used to decrease the output conductance.
Monotonic settling is also achieved in simple and folded cascodes, but it may be necessary to use of compensation in regulated cascode memory cells. More details can be found in
Ref. 22.
Fully differential structures are able to reduce errors coming from charge injection and improve noise immunity. Compared with basic cells of the same supply voltage and current,
much lower charge injection errors and similar bandwidth,
dynamic range, and chip area are obtained with fully differential cells designed with half-width transistors. Additionally,
any of the cascode variations previously cited may be used
with this approach.
Finally, if quiescent power consumption is a basic concern,
then the class AB SI technique can be indicated, because an
important reduction of it is obtained. Additionally, delay cells
using class AB memory cells are generated without duplicating the entire cell; instead the output of the first stage is simply cross-coupled to a second stage of memory cells. Simulation results in some applications have shown how charge
injection can produce significant errors.

9. M. G. Johnson and E. L. Hudson, A variable delay line PLL for

CPU-coprocessor synchronization, IEEE J. Solid-State Circuits,
23: 12181223, 1988.
10. M. Bazes, R. Ashuri, and E. Knoll, An interpolating clock synthesizer, IEEE J. Solid-State Circuits, 31: 12951301, 1996.
11. D. K. Jeong et al., Design of PLL-based clock generation circuits,
IEEE J. Solid-State Circuits, 22: 255261, 1987.
12. J. Christiansen, An integrated high resolution CMOS timing generator based on an array of delay locked loops, IEEE J. SolidState Circuits, 31: 952957, 1996.
13. J. G. Maneatis, Low-jitter process-independent DLL and PLL
based on self-biased techniques, IEEE J. Solid-State Circuits, 31:
17231732, 1996.
14. M. Mizuno et al., A GHz MOS adaptive pipeline technique using
MOS current-mode logic, IEEE J. Solid-State Circuits, 31: 784
791, 1996.
15. I. A. Young, J. K. Greason, and K. L. Wong, A PLL clock generator with 5 to 110 MHz of lock range for microprocessors, IEEE J.
Solid-State Circuits, 27: 15991607, 1992.
16. B. Razavi, Design of monolithic phase-locked loops and clock recovery circuitsA tutorial, in B. Razavi (ed.), Monolithic PhaseLocked Loops and Clock Recovery Circuits: Theory and Design,
Piscataway, NJ: IEEE Press, 1996.
17. Y. Watanabe et al., A new CR-delay circuit technology for highdensity and high-speed DRAMs, IEEE J. Solid-State Circuits, 24:
905910, 1989.
18. T. Tanzawa and T. Tanaka, A stable programming pulse generator for single power supply flash memories, IEEE J. Solid-State
Circuits, 32: 845851, 1997.
19. J. G. Manneatis and M. Horowitz, Precise delay generation using
coupled oscillators, IEEE J. Solid-State Circuits, 28: 12731282,
1993.
20. T. I. Laakso et al., Splitting the unit delay, IEEE Signal Process.
Mag., 13: 3060, 1996.
21. J. M. Rabaey, Digital Integrated Circuits: A Design Perspective,
Upper Saddle River, NJ: Prentice-Hall, 1996.
22. C. Tomazou, J. B. Hughes, and N. C. Battersby (eds.), SwitchedCurrents, An Analogue Technique for Digital Technology, London:
Peregrinus, 1993.
23. R. Unbenhauen and A. Cichocki, MOS Switched-Capacitor and
Continuous-Time Integrated Circuits and Systems, Berlin:
Springer-Verlag, 1989.

BIBLIOGRAPHY

JOSE M. QUINTANA
MARIA J. AVEDILLO

1. K. Bult and H. Wallinga, A CMOS analog continuous-time delay

line with adaptative delay-time control, IEEE J. Solid-State Circuits, 23: 759766, 1988.
2. C. Mead, Analog VLSI and Neural Systems, Reading, MA: Addison-Wesley, 1989.
3. S. Unger, The Essence of Logic Circuits, 2nd ed., Piscataway, NJ:
IEEE Press, 1997.
4. R. Feldman and D. Rosky, A step-by-step guide to programmable
delays, Electron. Design, 39: 9798, 100, 102104, 107, 1991.
5. G. C. Moyer et al., The delay vernier pattern generation technique, IEEE J. Solid-State Circuits, 32: 551562, 1997.
6. T. E. Rahkonen and J. T. Kostamovaara, The use of stabilized
CMOS delay lines for the digitization of short time intervals,
IEEE J. Solid-State Circuits, 28: 887894, 1993.
7. S.-Ch. Liu and C. Mead, Continuous-time adaptive delay system,
IEEE Trans. Circuits Syst. II: Analog and Digital Signal Processing, 43: 744751, 1996.
8. M. Bazes, A novel precision MOS synchronous delay line, IEEE
J. Solid-State Circuits, 20: 12651271, 1985.

139

Universidad de Sevilla

DELAY LINE. See DELAY CIRCUITS; PHASE SHIFTERS.

DELAYS. See CLOCK DISTRIBUTION IN SYNCHRONOUS
SYSTEMS.

378

DIFFERENTIAL AMPLIFIERS

DIFFERENTIAL AMPLIFIERS
AMPLIFICATION OF DIFFERENCE AND DC SIGNALS
Differential amplifiers represent a class of amplifiers, which
amplify the difference between two signals, including dc. To
obtain their desired characteristics, differential amplifiers
critically depend on component matching. Therefore, discrete
realizations, based on vacuum tubes or transistors, necessitate careful component pairing, which is not just painstaking
for the design engineer, but also significantly raises the amplifiers cost. In contrast, integrated circuit technology with
its inherent small relative component tolerances is particularly suited for this application.
It is a well-known fact that the active elements used for
amplification are far from linear devices. To circumvent the
problems associated with the nonlinear inputoutput relationship, the amplifier circuit in a typical application is linearized through the selection of a suitable operating point. An
example of an elementary single-stage amplifier is shown in
Fig. 1. While the circuit includes a bipolar transistor, it can
readily be adapted to MOS technology, or even vacuum tubes.
In Fig. 1, the input bias and dc level at the output are separated from the desired inputoutput signals by means of coupling capacitors Cci and Cco. The role of the emitter degeneration resistor RO is to reduce the drift of the operating point.
Further, the decoupling capacitor CO counteracts the gain reduction associated with the insertion of RO. Obviously, the
presence of coupling and decoupling capacitors makes the circuit in Fig. 1 unsuitable for dc amplification. But, even at
low frequencies this amplifier is impractical, due to the large
capacitor values required, which, in turn, give rise to large
RC time constants and, consequently, slow recovery times
from any transient disturbances.
The requirement to avoid capacitors in low-frequency or dc
amplifiers leads to a mixing of the concepts of bias and signal.
VCC

RL

Vo
CCO

CCi
Vi

RO

CO

Figure 1. Single-transistor amplifier.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

DIFFERENTIAL AMPLIFIERS

V1

A1

V3

V4

A2

through a combination of careful device matching, precise selection of the amplifiers bias and operating point, as well as
by a high common-mode rejection. While we have only considered differential output signals up to this point, in some instances a single-ended output is desired. Equations (5) and
(6) can be rearranged as

V2

Figure 2. Conceptual drawing of a differential amplifier.

A second characteristic of such amplifiers is the application of

symmetry to compensate for the drift of the active components. An intuitive solution appears to lie in the use of two
amplifiers, connected in a difference configuration, as illustrated in Fig. 2. For this circuit one can write the following
equations:
V3 = A1V1

(1)

V4 = A2V2

(2)

Assuming A1 approximately equal to A2, that is, A1 A /

2 and A2 A /2, yields

(V + V2 )
2 1

V3 + V4 = A(V1 + V2 ) + (V1 V2 )
2
V3 V4 = A(V1 V2 ) +

379

(3)
(4)

Clearly, when both amplifiers are perfectly matched or 0,

the difference mode is completely separated from the sum
mode. Upon further reflection, though, the difference amplifier of Fig. 2 is not really the solution to the amplification
problem under consideration. Indeed, in many instances,
small signals, which sit on top of large pedestal voltages, need
to be amplified. For example, assume A 100, a difference
signal of 10 mV and a bias voltage equal to 10 V. The amplifier scheme of Fig. 2 would result in a 1 V difference signal,
in addition to a 1000 V output voltage common to both amplifiers. It is clearly unrealistic to assume that both amplifiers
will remain linear and matched over such extended voltage
range. Instead, the real solution is obtained by coupling the
amplifiers. The resulting arrangement is known as the differential pair amplifier.
In the mathematical description of the differential pair,
four amplification factors are generally defined to express the
relationship between the differential or difference (subscript
D) and common or sum mode (subscript C) input and output
signals. Applied to the circuit in Fig. 2, one can write
V3 V4 = VoD = ADDViD + ADCViC

(5)

V3 + V4 = 2VoC = 2ACCViC + 2ACDViD

(6)

where ViD V1 V2 and ViC (V1 V2)/2. The ratio ADD /ACC
is commonly referred to as the amplifiers common-mode rejection ratio or CMRR. While an amplifiers CMRR is an important characteristic, maximizing its value is not a designers goal, in itself. Rather, the real purpose is to suppress
large sum signals, so that the two amplifiers exhibit a small
output swing and, thereby, operate indeed as a matched pair.
Furthermore, the ultimate goal is to avoid that the application of a common-mode input signal results in a differential
signal at the output. This objective can only be accomplished

V3 = VoC +

1
1
1
V = ACD + ADD ViD + ACC + ADC ViC
2 oD
2
2
(7)

V4 = VoC

1
1
1
V = ACD ADD ViD + ACC ADC ViC
2 oD
2
2
(8)

One concludes that in the single-ended case all three ratios

ADD /ACC, ADD /ACD, and ADD /ADC must be high, to yield the desired result.
Vacuum-tube-based differential circuits are not discussed
in this article, which is devoted solely to mainstream integrated circuit technology, more specifically, bipolar junction
and MOS field effect transistors. The next section provides an
in-depth analysis of the bipolar version of the differential
pair, also known as the emitter-coupled pair. The subsequent
treatment of the MOS source-coupled pair adheres to a similar outline, with an emphasis on similarities, as well as important differences.
BIPOLAR DIFFERENTIAL PAIRS (EMITTER-COUPLED PAIRS)
Figure 3 depicts the basic circuit diagram of a bipolar differential pair. A differential signal ViD is applied between the
bases of two transistors, which, unless otherwise noted, are
assumed to be identical. The dc bias voltage Vbias and a common-mode signal ViC are also present. The transistors common emitter node is connected to ground through a biasing

VCC

IC1

RL

IC2

RL
+

VO

Q1

Q2

ViD

ViC

Vbias

IEE

RO

Figure 3. Bipolar differential pair (emitter-coupled pair).

380

DIFFERENTIAL AMPLIFIERS

network, which, for simplicity, is represented by a single resistor RO. The amplifier output is taken differentially across
the two collectors, which are tied to the power supply VCC,
by means of a matched pair of load resistors RL.

two transistors is almost completely cut off and for further

increases in ViD the differential output signal eventually clips
at RLIEE. On the other hand, for small values of x, tanh
x x. Under this small-signal assumption,

Low-Frequency Large-Signal Analysis

ADD =

Applying the bipolar transistors EbersMoll relationship

with Vbe VT (where VT kT/q is the thermal voltage) and
assuming that both transistors are matched (i.e., the saturation currents IS1 IS2), the difference voltage ViD can be expressed as follows:
ViD = Vbe1 Vbe2 = VT ln

I 
C1

(9)

IC2

After some manipulation and substituting IC1 IC2 IEE (the

total current flowing through RO), one gets

IC1 =

IC2 =

IEE

V 
iD
1 + exp
VT

(10)

IEE
1 + exp

V 

(11)

iD

VT

where is defined as /( 1).

Since VoD RL(IC1 IC2), the expression for the differential output voltage VoD becomes

exp

VoD

V 
iD

exp

iD

ACC =

VoC
R
L
ViC
2RO

(14)

Combining Eqs. (13) and (14) yields

(12)

CMRR =

ADD
2gm RO
ACC

(15)

Half Circuit Equivalents

From Eq. (12) one observes that the transfer function is quite
non-linear. When ViD 2VT, the current through one of the

Figure 4 illustrates the derivation of the common-emitter circuits differential mode half circuit equivalent representation.

VCC
VCC

RL

RL
+

VCC

RL

RL

VoD

VoD/2

VoD/2

+
ViD

(13)

While the next subsection contains a more rigorous

small-signal analysis, a noteworthy observation here is that,
under conditions of equal power dissipation, the differential
amplifier of Fig. 3 has only one-half the transconductance
value and, hence, only one-half the gain of a single transistor amplifier. From Eq. (13) one furthermore concludes that,
when the tail current IEE is derived from a voltage source,
which is proportional to absolute temperature (PTAT), and
a resistor of the same type as RL, the transistor pairs
differential gain is determined solely by a resistor ratio. As
such, the gain is well controlled and insensitive to absolute
process variations.
An intuitive analysis of the common-mode gain can be carried out under the assumption that RO is large (for example,
assume RO represents the output resistance of a current
source). Then, a common-mode input signal ViC results only
in a small current change iC through RO and, therefore, Vbe
remains approximately constant. With iC ViC /RO and VoC
RLiC /2, the common-mode gain can be expressed as

V 

2VT
T

2V

V

= RL IEE
ViD
iD
exp
+ exp
2V
2VT

VT 
iD
= RL IEE tanh
= RL IEE tanh x
2VT

VoD
I
= EE RL = gm RL
ViD
2VT

ViD/2

Difference mode
Figure 4. Derivation of the emitter-coupled pairs half circuit equivalent for difference signals.

ViD/2

DIFFERENTIAL AMPLIFIERS

381

VCC
VCC

RL

RL

VCC

RL

VoC

RL

VoC

VoC

ViC

ViC

+
2RO

ViC

2RO

2RO

2RO

Sum mode
Figure 5. Derivation of the emitter-coupled pairs half circuit equivalent for common-mode
signals.

For a small differential signal, the sum of the currents

through both transistors remains constant and the current
through RO is unchanged. Therefore, the voltage at the emitters remains constant. The transistors operate as if no degeneration resistor were present, resulting in a high gain. In sum
mode, on the other hand, the common resistor Ro provides
negative feedback, which significantly lowers the commonmode gain. In fact, with identical signals at both inputs, the
symmetrical circuit can be split into two halves, each with a
degeneration resistor 2RO, as depicted in Fig. 5.

Figure 6 represents the low-frequency small-signal differential mode equivalent circuit wherein RSD models the corresponding source impedance. Under the presumption of
matched devices,

VoD
= gm RL
ViD

r
r + rb +

1
R
2 SD

(16)

With rb r and assuming a low-impedance voltage source,

Eq. (14) can be simplified to gmRL as was previously derived
in Eq. (13). The low-frequency common-mode equivalent circuit is shown in Fig. 7. Under similar assumptions as in Eq.
(16) and with RSC representing the common-mode source impedance, one finds
ACC =

CMRR =

ADD
r + rb + 2RSC + 2( + 1)RO
=
2gm RO (18)
1
ACC
r + rb + RSD
2

Consider the special case where RO models the output resistance of a current source, implemented by a single bipolar
transistor. Then, RO VA /IEE, where VA is the transistors
Early voltage. With gm IEE /2VT,
CMRR =

Low-Frequency Small-Signal Analysis

ADD =

The combination of Eqs. (16) and (17) leads to

VoC
r
= gm RL
ViC
r + rb + 2RSC + 2( + 1)RO

(17)

Upon substitution of gmr 1, Eq. (17) reduces to

RL /2RO, the intuitive result obtained earlier in Eq. (14).

VA
VT

(19)

which is independent of the amplifiers bias conditions, but

only depends on the process technology and temperature. At
room temperature, with 1 and VA 25 V, the amplifiers
CMRR is approximately 60 dB. The use of an improved current source, for example, a bipolar transistor in series with
an emitter degeneration resistor RD, can significantly increase
the CMRR. More specifically,
CMRR =

VA
VT

1+

IEE RD
VT

(20)

For IEERD 250 mV, the CMRR in Eq. (20) is eleven times
higher than in Eq. (19).
In addition to expressions for the gain, the emitter-coupled
pairs differential and common-mode input resistances can
readily be derived from the small-signal circuits in Figs. 6
and 7.
RinD = 2r
RinC =

1
r + RO ( + 1)
2

(21)
(22)

382

DIFFERENTIAL AMPLIFIERS

i1

RL

RL

i2

VoD

rb1

rb2

gm1v 1
r 1

RL
VOD /2

rb

gm2v

gm2v 2

v 1

v 2

r 2

ViD

ViD /2
RO (replaced by short circuit)

RSD

RSD /2

Difference mode
Figure 6. Differential mode small-signal equivalent circuit for the emitter-coupled pair. The
complete circuit is on the left and the half circuit equivalent is on the right.

Taking into account the thermal noise of the transistors base

resistances and the load resistors RL, as well as the shot noise
caused by the collector currents, the emitter-coupled pairs total input referred squared noise voltage per hertz is given by

2
1
1
ViN
= 8kT rb +
+ 2
f
2gm
g m RL

(23)

Due to the presence of base currents, there is also a small

input noise current, which, however, will be ignored here and
in further discussions.
Small-Signal Frequency Response
When the emitter-base capacitance C, the collector-base capacitance C, the collector-substrate capacitance Ccs, and the
transistors output resistance ro are added to the transistors

i1

RL

RL

hybrid- small-signal model in Fig. 6, the differential gain

transfer function becomes frequency dependent. With Ri representing the parallel combination of (RsD /2 rb) with r, and
RC similarly designating the parallel combination of RL with
ro, Eq. (16) must be rewritten as

ADD =

sC
1
N(s)
gm
=
D(s)
1 + s(C Ri + C Ri + C RC + C Ri RC gm + Ccs RC )
+ s2 (C Ccs Ri RC + C C Ri RC + CCcs Ri RC )

i
rb2

r 1

VoC

RL
VoC

rb

gmv

gm2v 2

v 1

(24)

where

i2

rb1
gm1v 1

gm Ri RC N(s)
1
D(s)
R + rb
2 sD

r 2

v 2

+
ViC
RO

2RSc

ViC
RSC

Sum mode
Figure 7. Common-mode small-signal equivalent circuit for the emitter-coupled pair. The complete circuit is on the left and the half circuit equivalent is on the right.

2RO

(25)

DIFFERENTIAL AMPLIFIERS

One observes that Eq. (25) contains a right half-plane zero

located at sz gm /C, resulting from the capacitive feedthrough from input to output. However, this right half-plane
zero is usually at a frequency sufficiently high for it to be
ignored in most applications. Furthermore, in many cases,
one can assume that D(s) contains a dominant pole p1 and a
second pole p2 at a substantially higher frequency. If the dominant pole assumption is valid, D(s) can be factored in the
following manner:
D(s) =

s
p1



s
p2

s
s2
+
p1
p1 p2

(26)

Equating Eqs. (25) and (26) yields

p1 =

p2 =

1
Ri

1

R
RC
C + Ccs
+ C 1 + gm RC + C
Ri
Ri

1
RC (C + Ccs )

C + Ccs

(27)

R
RC
+ C 1 + gm RC + C
Ri
Ri
CCcs
C +
C + Ccs

(28)
The collector-base capacitance C in Eqs. (27) and (28) appears with a multiplication factor, which is essentially equal
to the amplifiers gain. This phenomenon is widely referred to
as the Miller effect.
Rather than getting into a likewise detailed analysis, the
discussion of the emitter-coupled pairs common-mode frequency response is limited here to the effect of the unavoidable capacitor CO (representing, for instance, the collectorbase and collector-substrate parasitic capacitances of the
BJT), which shunts RO. The parallel combination of RO and
CO yields a zero in the common-mode transfer function. Correspondingly, a pole appears in the expression for the amplifiers CMRR. Specifically,
CMRR = 2gm

RO
1 + sCO RO

(29)

The important conclusion from Eq. (29) is that at higher frequencies the amplifiers CMRR rolls off by 20 dB per decade.
Dc Offset
Input Offset Voltage. Until now, perfect matching between
like components has been assumed. While ratio tolerances in
integrated circuit technology can be very tightly controlled,
minor random variations between equal components are unavoidable. These minor mismatches result in a differential
output voltage, even if no differential input signal is applied.
When the two bases in Fig. 3 are tied together, but the transistors and load resistors are slightly mismatched, the resulting differential output offset voltage can be expressed as

VoO = (RL + RL )(IC + IC ) + RL IC

= (RL + RL )(IS + IS ) exp

V 
be

VT

+ RL IS exp

V 

or

VoO

R

(30)

IS
Vbe

+
RL IS exp
RL
IS
VT

R I 
L
S
=
+
RL IC
RL
IS
L


(31)

Conversely, the output offset can be referred back to the

input through a division by the amplifiers differential gain.
ViO =

VoO
= VT
gm RL

R

RL

IS
IS


(32)

The input referred offset voltage ViO represents the voltage,

which must be applied between the input terminals, in order
to nullify the differential output voltage. In many instances,
the absolute value of the offset voltage is not important, because it can easily be measured and canceled, either by an
auto-zero technique or by trimming. Rather, when offset compensation is applied, the offset stability under varying environmental conditions becomes the primary concern. The drift
in offset voltage over temperature can be calculated by differentiating Eq. (32).
dViO
V
= iO
dT
T

(33)

From Eq. (33) one concludes that the drift is proportional to

the magnitude of the offset voltage, and inversely related to
the change in temperature.
Input Offset Current. Since, in most applications, the differential pair is driven by a low-impedance voltage source, its
input offset voltage is an important parameter. Alternatively,
the amplifier can be controlled by high-impedance current
sources. Under this condition, the input offset current IiO,
which originates from a mismatch in the base currents, is the
offset parameter of primary concern. Parallel to the definition
of ViO, IiO is the value of the current source, which must be
placed between the amplifiers open-circuited input terminals
to reduce the differential output voltage to zero.
IiO =

I
I
IC + IC
C C
+

I

IC


(34)

The requirement of zero voltage difference across the output

terminals can be expressed as
(RL + RL )(IC + IC ) = RL IC

(35)

Eq. (35) can be rearranged as

RL
IC

IC
RL

(36)

Substituting Eq. (36) into Eq. (34) yields

be

VT

383

IiO =

IEE
2

R

RL


(37)

384

DIFFERENTIAL AMPLIFIERS

IiOs linear dependence on the bias current and its inverse relationship to the transistors current gain , as expressed by
Eq. (37), intuitively make sense.
Gain Enhancement Techniques
From Eq. (13) one concludes that there are two ways to increase the emitter-coupled pairs gain, namely, an increase in
the bias current or the use of a larger valued load resistor.
However, practical limitations of the available supply voltage
and the corresponding limit on the allowable I R voltage
drop across the load resistors, in order to avoid saturating
either of the two transistors, limit the maximum gain that

can be achieved by a single stage. This section introduces two

methods, which generally allow the realization of higher gain
without the dc bias limitations.
Negative Resistance Load. In the circuit of Fig. 8 a gain
boosting positive feedback circuit is connected between the
output terminals. The output dc bias voltage is simply determined by VCC, together with the product of RL and the
current flowing through it, which is now equal to (IE
IR)/2. However, for ac signals the added circuit, consisting
of two transistors with cross-coupled base-collector connections and the resistors RC between the emitters, represents
a negative resistance of value (RC 1/gmc) where gmc

VCC

RL

RL
+

VO

RC

RC

ViD

ViC
IEE

Vbias

Figure 8. Emitter-coupled pair with negative resistance load circuit, used to increase the amplifiers gain.

IR

DIFFERENTIAL AMPLIFIERS

385

VCC

VO

RF
RF /2
RF

ViD

ViC

Vbias

RO

IL

IL

IF

VREF

IL

Figure 9. Fully differential emitter-coupled pair with active current source loads and commonmode feedback circuit.

IR /2VT. The amplifiers differential gain can now be expressed

as

ADD gm RL

1
gmc RL
1
1 + gmc RC

(38)

put terminal is similarly tied to a reference voltage VREF. The

negative feedback provided to the pnp load transistors forces
an equilibrium state in which the dc voltage at the output
terminals of the differential pair gain stage are equal to
VREF. The need for CMFB can be avoided in a single-ended
implementation as shown in Fig. 10. Contrary to the low
VCC

Active Load. Another approach to increase the gain consists of replacing the load resistors by active elements, such
as pnp transistors. Figure 9 shows a fully differential realization of an emitter-coupled pair with active loads. The differential gain is determined by the product of the transconductance of the input devices and the parallel combination of the
output resistances of the npn and pnp transistors. Since
gm IC /VT, ron VAn /IC and rop VAp /IC, the gain becomes
ADD = gm

VAnVAp
(VAn + VAp )IC

1 VAnVAp
VT VAn + VAp

VO

(39)

Consequently, the gain is independent of the bias conditions.

The disadvantage of the fully differential realization with active loads is that the output common-mode voltage is not well
defined. If one were to use a fixed biasing scheme for both
types of transistors in Fig. 9, minor, but unavoidable mismatches between the currents in the npn and pnp transistors
will result in a significant shift of the operating point. The
solution lies in a common-mode feedback circuit (CMFB),
which controls the bases of the active loads and forces a predetermined voltage at the output nodes. The CMFB circuit
has high gain for common-mode signals, but does not respond
to differential signals present at its inputs. A possible realization of such CMFB circuit is seen in the right portion of Fig.
9. Via emitter followers and resistors RF, the output nodes are
connected to one input of a differential pair, whose other in-

ViD

ViC
RO
Vbias

Figure 10. Single-ended output realization of an emitter-coupled

pair with active loads.

386

DIFFERENTIAL AMPLIFIERS

CMRR of a single-ended realization with resistive loads, the

circuit in Fig. 10 inherently possesses the same CMRR as a
differential realization since the output voltage depends on a
current differencing as a result of the pnp mirror configuration. The drawback of the single-ended circuit is a lower frequency response, particularly when low-bandwidth lateral
pnp transistors are used.

Consequently,
ADD

(43)

In comparison with the undegenerated differential pair,

the gain is reduced by an amount gmRE, which is proportional
to the increase in linear input range. The common-mode gain
transfer function for the circuit in Fig. 11 is

Emitter Degeneration

ACC

The most common technique to increase the linear range of

the emitter-coupled pair relies on the inclusion of emitter degeneration resistors, as shown in Fig. 11. The analysis of the
differential gain transfer function proceeds as before, however, no closed-form expression can be derived. Intuitively,
the inclusion of RE introduces negative feedback, which lowers the gain and extends the amplifiers linear operating region to a voltage range approximately equal to the product of
REIE. The small-signal differential gain can be expressed as
ADD GM RL

(40)

where GM is the effective transconductance of the degenerated

input stage. Therefore,
gm
1

1 + g m RE
RE

(41)

RL

VO

RE

RE

ViC
RO
+

(44)


2
1
1
ViN
= 8kT rb +
( g2m R2E ) + 2
( g 2m R2E ) + RE
f
2 gm
g m RL

(45)

This means that, to a first order, the noise too increases by

the factor gmRE. Consequently, even though the amplifiers
linear input range is increased, its signal-to-noise ratio (SNR)
remains unchanged. To complete the discussion of the emitter
degenerated differential pair, the positive effect emitter degeneration has on the differential input resistance RinD and,
to a lesser extent, on RinC should be mentioned. For the circuit
in Fig. 11,
RinD = 2[r + ( + 1)RE ]
RinC =

RL

RL
2RO + RE

For practical values of RE, ACC remains relatively unchanged

compared to the undegenerated prototype. As a result, the
amplifiers CMRR is reduced approximately by the amount
gmRE. Also, the input referred squared noise voltage per Hertz
can be derived as

VCC

Vbias

RL
RE

ADD

As derived previously, the linear range of operation of the

emitter-coupled pair is limited to approximately ViD 2VT.
This section describes two techniques, which can be used to
extend the linear range of operation.

ViD

(42)

In case gmRE 1,

Linearization Techniques

GM =

g m RL
1 + g m RE

(46)

1
( + 1)RE
r +
+ RO ( + 1)
2
2

(47)

Parallel Combination of Asymmetrical Differential Pairs. A

second linearization technique consists of adding the output
currents of two parallel asymmetrical differential pairs with
respective transistor ratios 1 : r and r : 1, as shown in Fig. 12.
The reader will observe that each differential pair in Fig. 12
is biased by a current source of magnitude IEE /2, so that the
power dissipation, as well as the output common-mode voltage, remain the same as for the prototype circuit in Fig. 3.
Assuming, as before, an ideal exponential input voltage
output current relationship for the bipolar transistors, the following voltage transfer function can be derived:







ln r
ln r
ViD
ViD
VoD = IEE RL tanh

+ tanh
+
2
2VT
2
2VT
2
(48)
After Taylor series expansion and some manipulation, Eq.
(48) can be rewritten as

Figure 11. Bipolar differential pair with emitter degeneration resistors used to extend the linear input range.

VoD

1
ViD
= IEE RL (1 d)
+ d
2VT
3



ViD
2VT

3
+

(49)

DIFFERENTIAL AMPLIFIERS

Fig. 12 is 1/0.64 or 1.56 times higher than for the circuit

in Fig. 3. Combined with the nearly threefold increase in
linear input range, this means that the SNR nearly doubles. The increase in SNR is a distinct advantage over the
emitter degeneration linearization technique. Moreover, the
linearization approach introduced in this section can be extended to a summation of the output currents of three,
four, or more parallel asymmetrical pairs. However, there
is a diminished return in the improvement. Also, for more
than two pairs the required device ratios become quite
large, and the sensitivity of the linear input range to small
mismatches in the actual ratios versus their theoretical values increases as well.

VCC

RL

RL
+

VO

ViD

387

ViC
IEE /2
Vbias

Rail-to-Rail Common-Mode Inputs and

Minimum Supply Voltage Requirement

IEE /2

Figure 12. Two asymmetrical emitter-coupled pairs with respective

transistor ratios r : 1 and 1 : r. The collector currents are summed. If
r is selected appropriately, the linear input range and SNR are increased.

With the consistent trend toward lower power supplies, the

usable input common-mode range as a percentage of the supply voltage is an important characteristic of differential amplifiers. Full rail-to-rail input compliance is a highly desirable
property. Particularly for low power applications, the ability
to operate from a minimal supply voltage is equally important. For the basic emitter-coupled pair in Fig. 3, the input is
limited on the positive side when the npn transistors saturate. Therefore,

where
d=

ViC,pos = VCC

r 1 2

ADD 0.64 gm RL

(51)

where gm IEE /2VT as before. Equation (51) means that the

trade-off for the linearization is a reduction in the differential
gain to 64 percent of the value obtained by a single symmetrical emitter-coupled pair with equal power dissipation. The
squared input referred noise voltage per hertz for the two parallel asymmetrical pairs can be expressed as

r

1
1
+
+ 2
5
2 gm
g m RL
b

(53)

(50)

r+1

Equation (49) indicates that the dominant third harmonic distortion component can be canceled by setting d 1/3 or r
2 3 3.732. The presence of parasitic resistances within
the transistors tends to require a somewhat higher ratio r for
optimum linearization. In practice, the more easily realizable
ratio r 4 (or d 9/25) is frequently used. When the linear
input ranges at a 1% total harmonic distortion (THD) level of
the single symmetrical emitter-coupled pair in Fig. 3 and the
dual circuit with r 4 in Fig. 12 are compared, a nearly
threefold increase is noted. For r 4 and neglecting higherorder terms, Eq. (49) becomes

2
8kT
ViN
=
f
(0.64)2

1
R I + Vb c ,forward
2 L EE


(52)

The factor rb /5 appears because of an effective reduction in

the base resistance by a factor (r 1), due to the presence
of five transistors versus one in the derivation of Eq. (23).
If the unit transistor size in Fig. 12 is scaled down accordingly, a subsequent comparison of Eqs. (23) and (52) reveals
that the input referred noise for the linearized circuit of

If one limits RLIEE /2 Vbc,forward, ViC,pos can be as high as VCC or

even slightly higher. On the negative side, the common-mode
input voltage is limited to that level, where the tail current
source starts saturating. Assuming a single bipolar transistor
is used as the current source,
ViC,neg > Vbe + Vce,sat 1 V

(54)

The opposite relationships hold for the equivalent pnp transistor based circuit. As a result, the rail-to-rail commonmode input requirement can be resolved by putting two
complementary stages in parallel. In general, as the input
common-mode traverses between VCC and ground, three distinct operating conditions can occur: at high voltage levels
only the npn stage is active; at intermediate voltage levels
both the npn and pnp differential pairs are enabled; finally,
for very low input voltages only the pnp stage is operating.
If care is not taken, three distinct gain ranges can occur:
based on gmn only; resulting from gmn gmp; and, contributed
by gmp only. Nonconstant gm and gain, which depends on
the input common-mode, is usually not desirable for several
reasons, not in the least in case of phase compensation if
the differential pair is used as the first stage in an operational amplifier. Fortunately, the solution to this problem
is straightforward if one recognizes that the transconductance of the bipolar transistor is proportional to its bias
current. Therefore, the only requirement for a bipolar constant gm complementary circuit with full rail-to-rail input
compliance is that under all operating conditions the sum
of the bias currents of the npn and pnp subcircuits remains

388

DIFFERENTIAL AMPLIFIERS

Equation (56) can be rearranged as

VCC

RL

IEE
+

ID1 ID2

RL

W
1
= Cox ViD
2
L

VO

4IDD
2
ViD
= KpViD
W
Cox
L

r 2I

DD

Kp

2
ViD

(57)

where
IDD = ID1 + ID2

(58)

Hence, the relationship between the differential output and

input voltages is

ViD

ViC

VoD

VREF

W
1
= RL (ID1 ID2 ) = Cox RLViD
2
L
= Kp RLViD

Figure 13. Complementary bipolar differential amplifier with railto-rail input common-mode compliance.

r 2I

DD

Kp

4IDD
2
ViD
W
Cox
L

2
ViD

(59)

As mentioned above, Eq. (59) is only valid as long as both

transistors are in saturation or
ViD

constant. A possible implementation is shown in Fig. 13.

If ViC VREF, the pnp input stage is enabled and the
npn input transistors are off. When ViC VREF, the bias
current is switched to the npn pair and the pnp input
devices turn off. For RLIEE /2 Vcb,forward,n the minimum required power supply voltage is Vbe,n Vbe,p Vce,sat,n
Vce,sat,p, which is lower than 2 V.

r 2I

DD

(60)

Kp

Similar to the bipolar case, Eq. (59) is quite nonlinear and the
output voltage eventually clips when one of the input transistors is completely starved of current. However, unlike the
emitter-coupled pair, the linear operating range of the sourcecoupled pair also depends on the bias current and device
sizes. Equation (60) indicates that the linear range of operation can be expanded by increasing IDD and/or reducing the
W/L ratio of the MOS devices.

MOS DIFFERENTIAL PAIRS (SOURCE-COUPLED PAIRS)

The MOS equivalent of the emitter-coupled pair is the
source-coupled pair. Since the analysis of both circuits is
generally quite similar, the discussion of the source-coupled
pair will be more concise with an emphasis on important
differences.

VCC

ID1

RL

Low-Frequency Large-Signal Analysis

RL

ID2

VO

Figure 14 depicts the source-coupled pair with a resistive

load. When the MOS transistors are in the saturation region,
their currentvoltage relationship can be described by the
square law characteristic.

M1

M2

ViD

ID =

1
W
Cox (Vgs Vt )2 = Kp (Vgs Vt )2
2
L

(55)
ViC

Using Eq. (55) and assuming perfect matching, the differential input voltage can be expressed as

ViD = Vgs1 Vgs2 =

2ID1
W
Cox
L

2ID2
W =
Cox
L

rI

D1

Kp

IDD
Vbias

RO

rI

D2

Kp
(56)

Figure 14. MOS differential pair (source-coupled pair) with resistive loads.

DIFFERENTIAL AMPLIFIERS

The current mismatch ID can be expanded as

Low-Frequency Small-Signal Analysis

An expression for the small-signal transconductance of the
source-coupled pair can be derived by taking the derivative of
Eq. (57) with respect to the input voltage.

gm =

d(ID1 ID2 )
gm =
dViD

Cox

W
I =
L DD

2K I

p DD

389

(61)

= 2 Kp ID = 2Kp (Vgs Vt )
(62)

As was noted for the bipolar differential pair, the transconductance of the source-coupled pair is only equal to the transconductance of one of the input devices. However, in contrast
to the bipolar transistor, gm in Eq. (62) is only proportional to
the square root of the bias current. Due to gms dependence on
the mobility and the threshold voltage Vt, stabilization of
gm over temperature is not as straightforward as is the case
for bipolar. Furthermore, gm of the source-coupled pair is a
function of the device size and the oxide capacitance.

ID = (Kp + Kp )(Vgs Vt Vt )2 Kp (Vgs Vt )2

2Kp Vt (Vgs Vt ) + Kp (Vgs Vt )2

(64)

Kp
= gm Vt +
I
Kp D
Substituting Eqs. (62) and (64) into (63) yields




RL ID
Kp
VoO = gm RL Vt +
+
Kp
RL
gm





Kp
RL (Vgs Vt )
= gm RL Vt +
+
Kp
RL
2

(65)

This output offset voltage can be referred to the input by dividing Eq. (65) by the amplifiers gain.
ViO =

VoO
(Vgs Vt )
= Vt +
gm RL
2

K

Kp

RL
RL


(66)

Dc Offset
As pointed out previously, small device mismatches are unavoidable and they give rise to an offset voltage. Assuming
such small differences in the circuit of Fig. 14 where the inputs are tied together, one can derive an expression for the
output offset voltage as follows:
VoO = (RL + RL )(ID + ID ) + RL ID RL ID RL ID
(63)

The input referred offset voltage Vio is the voltage, which

must be applied between the open-circuited gate terminals
to cancel the differential voltage across the output nodes.
Equation (66) indicates that ViO is directly related to the
mismatch of the threshold voltages. The second term in Eq.
(66) is reminiscent of Eq. (32) for the bipolar differential
pair. However, since the multiplicative term (Vgs Vt)/2 in
Eq. (66) is usually much larger than its counterpart VT in

VCC

VO

ViD

ViC

Vbias

RO

IF

VREF

Figure 15. Fully differential source-coupled pair with active current source loads and commonmode feedback circuit.

390

DIFFERENTIAL AMPLIFIERS

Eq. (32), one concludes that the source-coupled pair is inherently subject to a larger offset voltage. On the other
hand, the source-coupled pair has no input offset current
since there is no gate current.

VCC

Active Load
Source-coupled pairs are almost exclusively used in conjunction with active loads. Figure 15 illustrates a fully differential
realization, including a possible implementation of the required common-mode feedback circuit. Its operation is similar
to the bipolar version in Fig. 9. A single-ended circuit is
shown in Fig. 16.

VO
VC

ViD

Linearization
In addition to controlling the linear range of operation by
proper selection of bias current and device sizes, the techniques discussed for the emitter-coupled pair can also be applied to the source-coupled pair. Figure 17 illustrates the application of source degeneration. However, the degeneration
resistor is implemented by a MOS transistor, which operates
in the linear region by connecting its gate to an appropriate
control voltage VC. The differential pairs gain can be adjusted
by varying VC. Similarly, the technique of multiple asymmetrical pairs in parallel can also be extended to the MOS
domain.

ViC
IE /2
Vbias

IE /2

Figure 17. MOS differential pair with degeneration implemented by

a MOS transistor in the linear region.

Rail-to-Rail Common-Mode Input Signals

As for the bipolar case, the highly desirable rail-to-rail input
voltage compliance can be obtained by a parallel combination
of NMOS and PMOS differential pairs. However, the realization of a constant gm over the whole range of operation is not
as straightforward. One possible solution is to operate the
MOS differential pairs in the subthreshold region, where the

exponential currentvoltage relationship holds and, as in the

bipolar case, gm is only a function of the bias current. Many
circuits using MOS transistors in saturation require some
kind of matching between the NMOS and PMOS devices,
which is extremely difficult to achieve in mass production. Research into new circuit techniques to circumvent this problem
continues and, judging by the numbers of recent papers on
the subject, constitutes an area of significant contemporary
academic interest.

VCC

BIBLIOGRAPHY

VO

ViD

ViC

Vbias

RO

Figure 16. Single-ended output implementation of a source-coupled

pair with active current source loads.

P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Fort

Worth, TX: Holt, Rinehart and Winston, 1987.
G. A. De Veirman, et al., A 3.0 V 40 Mbit/s hard disk drive read
channel IC, IEEE J. Solid-State Circuits, SC-30: 788799,
1995.
J. F. Duque-Carrillo, J. M. Valverde, and R. Perez-Aloe, Constant-gm
rail-to-rail common-mode range input stage with minimum CMRR
degradation, IEEE J. Solid-State Circuits, SC-28: 661666,
1993.
J. Fonderie, Design of Low-Voltage Bipolar Operational Amplifiers,
Delft: Delft University Press, 1991.
L. J. Giacoletto, Differential Amplifiers, New York: Wiley, 1970.
P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated
Circuits, 2nd ed., New York: Wiley, 1984.
A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design,
New York: Wiley, 1984.
R. Hogervorst, et al., CMOS low-voltage operational amplifiers with
constant gm rail-to-rail input stage, Proc. IEEE Int. Symp. Circuits
Systems (ISCAS) : 1992, pp. 28762879.
J. H. Huijsing and D. Linebarger, Low-voltage operational amplifier
with rail-to-rail input and output ranges, IEEE J. Solid-State Circuits, SC-20: 11441150, 1985.

DIFFERENTIATING CIRCUITS
C. Hwang, A. Motamed, and M. Ismail, Universal constant-gm inputstage architectures for low-voltage opamps, IEEE Trans. Circuits
Syst.I, 42: 886895, 1995.
R. D. Middlebrook, Differential Amplifiers, New York: Wiley, 1963.
J. Schmoock, An input stage transconductance reduction technique
for high-slew rate operational amplifiers, IEEE J. Solid-State Circuits, SC-10: 407411, 1975.
S. Sakurai and M. Ismail, Robust design of rail-to-rail CMOS operational amplifiers for low power supply voltage, IEEE J. Solid-State
Circuits, 31: 146156, 1996.
J. O. Voorman, W. H. A. Bruls, and P. J. Barth, Bipolar integration of
analog gyrator and Laguerre type filters, Proc. ECCTD, Stuttgart,
108110, 1983.
R. J. Widlar and M. Yamatake, A fast settling opamp with low
supply current, IEEE J. Solid-State Circuits, SC-24: 796802,
1989.

GEERT A. DE VEIRMAN
Silicon Systems, Inc.

DIFFERENTIAL AMPLIFIERS. See INSTRUMENTATION AMPLIFIERS.

DIFFERENTIAL EQUATIONS. See ORDINARY DIFFERENTIAL EQUATIONS.

DIFFERENTIAL EQUATIONS, ORDINARY. See ORDINARY DIFFERENTIAL EQUATIONS.

DIFFERENTIAL PAIRS. See DIFFERENTIAL AMPLIFIERS.

DIFFERENTIAL RESISTANCE, NEGATIVE. See NEGATIVE RESISTANCE.

391

DIFFERENTIATING CIRCUITS

391

to Eq. (1), ideally the differentiator is a linear system, mapping the input into the output linearly. If D is a constant,
then on taking the bilateral Laplace transform, L[ ], of Eq.
(1) we obtain the system transfer function description,
H(s) L[y]/L[u], in terms of the complex frequency variable
s j,
H(s) = Ds

(2)

Evaluating this in terms of real frequency, , we find that

H( j) = jD

(3)

which shows that the differentiator introduces a constant

phase shift of 90 and amplifies the input proportionally to
the frequency. This illustrates the difficulty one runs into
when practically using a differentiator since high-frequency
signals, which are often noise components, get greatly amplified compared to low-frequency signals, which most often are
the ones carrying intelligence, according to H( j) D (for
0).

CIRCUIT IMPLEMENTATIONS

DIFFERENTIATING CIRCUITS
Since the dynamics of systems comes through derivatives,
electronic circuits that perform differentiation are important
components both in theory and in practice. In the following
article we define differentiators, giving their transfer functions from which some properties can be inferred. Highly accurate voltage mode physical realizations in terms of op-amp
circuits, as well as current mode ones suitable for very large
scale integration (VLSI) realization, are given. Also included
are approximate ones in terms of simple resistor-capacitor
(RC) circuits appropriate for many control system applications. Since differentiators are not represented in terms of
standard state variables, we conclude with a semistate representation.

If the output is measured at the same terminals as the input,

then the device is a one-port differentiator; and in the case
where u is a voltage v and y is a current i, the differentiator
is equivalent to a capacitor so that the gain constant becomes
an equivalent capacitance, D C, as illustrated in Fig. 1(a).
Figure 1(b) shows the dual case of an inductor.
For voltage mode circuits, differentiators are customarily
two-port devices constructed from operational amplifiers according to the circuit of Fig. 2(a) (1, p. 10). In Fig. 2(a), u is a
voltage, vin, as is y, vout, and the gain constant is D RC. If
an ideal op-amp is assumed, it is an infinite gain device with
a virtual ground input. Thus,
vout (t) = RC

dvin (t)
dt

(4)

It should be noted that achieving a gain D RC near unity

in magnitude usually requires a large resistor; for example, if
C 1 F, then R 1 M.

DEFINITION
Here a differentiating circuit, also known as a differentiator,
is defined as an electronic circuit satisfying the law
y(t) = D

du(t)
dt

(1)

y=i

u=i

+
u=v

(a)

where u( ) is the input to the circuit, y( ) is the output,

and D is the differentiator gain, usually taken to be a real
constant in time t. Because the differentiator is electronic,
we take u and y to be voltages or currents, though at times
one may wish to consider flux linkages or charge. According

+
y=v

(b)

Figure 1. (a) Capacitor as a differentiator. Here the input u equals

v and the output y equals i, which gives Y(s) I(s) CsV(s) in the
frequency domain. (b) Inductor as a differentiator. Here the input u
equals i and the output y equals v, which gives Y(s) V(s) LsI(s)
in the frequency domain.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

392

DIFFERENTIATING CIRCUITS

VDD

M1

M3

M5

OA
+
+
Vout

Vin

iin

iout

Figure 2. Op-amp differentiator.

M2

M4

M6

For practical op-amps there are several points to consider.

One is that the op-amp gain is reasonably well approximated
by a one-pole model K(s) K0 /(s p1) so that the differentiator transfer function becomes

H(s) =

1
K0

sRC
s2 RC s(1 + RCp1 )

+
K0
K0

VSS

(5)

from which we see that as the frequency gets large the gain
drops toward zero according to K0 /s. Besides this sometimes
favorable behavior, there are also nonlinearities due to saturation of the op-amp at the bias voltages and added noise due
to the transistors and resistors used in the construction of the
op-amp.
In some cases, such as derivative control, it is more economical to use the RC circuit of Fig. 3, which gives an approximate differentiator having the transfer function
H(s) =

sC
1 + sRC

+
Vin

+
Vout

Figure 3. RC ladder circuit.

rating their transconductances, gm. Ignoring their source to

drain conductances, the analysis gives the small-signal transfer function as [2, Eq. (6)]

H(s) =

iout
=
iin

kC
gm p + gmn


s
2sC
1+
gm p + gmn

(7)

(6)

For frequencies lower than p 1/RC, this circuit approximates a differentiator reasonably well, and its gain saturates at higher frequencies so that noise is not unduly amplified.
In terms of modern very large scale integration (VLSI) implementations, it is most convenient to use current mode
structures. Figure 4 shows a current mode structure which
differentiates the signal component of the input using complementary metal oxide semiconductor (CMOS) transistors (2).
Here the input transistors M1 and M2 act as resistors to convert the input current iin to a voltage which is applied to the
capacitor. The capacitor current, which is essentially the derivative of this voltage, is transferred through the output current mirror transistors M5 and M6, which can give an added
gain k. The analysis of the circuit proceeds by replacing all
transistors by their small-signal equivalent circuits incorpo-

Figure 4. Current mode differentiator.

where k is the current gain of the output current mirror transistors and gmn and gmp are the transconductances of the n
channel metal oxide semiconductor (NMOS) and p channel
metal oxide semiconductor (PMOS) transistors. Consequently, the circuit makes a reasonably good current-in current-out differentiator through the mid-megahertz frequency
range. Note that since the transistor transconductances depend on the bias point of the transistors, it is important to
use a regulated voltage source to keep the direct current
bias stable.

NOISE AND SIGNAL SWING CONSIDERATIONS

When working with op-amp differentiators, it is important to
consider noise behavior. For this the noise sources are normally reflected into the input and then the output noise is
found by applying the equivalent noiseless amplifier to the
input noise sources with a good treatment given in Ref. 1, p.
141. Such an operation is automatically carried out in the
PSpice noise analysis. A typical frequency response example
circuit is shown in Fig. 5(a) with its noise input, Fig. 5(b, top)
and noise output, Fig. 5(b, middle), along with the output,
Fig. 5(b, bottom), for a 1 mV input plus noise. In this circuit
a 701 op-amp is used and a reasonably small resistor is inserted in series with the differentiation capacitor to assist in
damping out the noise signal.

DIFFUSION

3
Rin 100

1 F

C1

Vin

Direct current = 0 V
Alternating current
= 1 mV

+ V+

7
+

V+

10 V

10 V

4
+

1 M

R1

393

+
out

(a)

194.8 nV

194.6 nV

100 Hz

1.0 kHz
Frequency

10 kHz

V(input noise)

10 mV

1.0 V

V(output noise)

10 V

1.0 mV
10 Hz
V(out)

100 kHz

(b)

SEMISTATE EQUATIONS

known to be less sensitive to noise compared to the conventional op-amp differentiator.

Because the standard state-space equations do not exist for a

differentiator, we give a description of it in terms of semistate
equations. These latter are equations of the form
E

Figure 5. (a) PSpice circuit of a differentiator using 701 op-amp. (b) Response and
noise behavior in the frequency domain.
The top curve represents the input noise,
the middle curve is the output noise, and
the bottom curve is the output response to
an input voltage of 1 mV plus noise.

dx
= Ax + Bu
dt
y = Cx

(8)
(9)

which have the transfer function

H(s) = C(sE A)1 B

(10)

BIBLIOGRAPHY
1. E. J. Kennedy, Operational Amplifier Circuits, Theory and Applications, New York: Holt, Rinehart and Winston, 1987.
2. E. I. El-Masry and J. W. Gates, A novel continuous-time current
mode differentiator and its applications, IEEE Trans. Circuits
Syst. II, 43: 5659, 1996.
3. M. E. Zaghloul and R. W. Newcomb, Semistate implementation:
Differentiator example, J. Circuits Syst. Signal Process., 5 (1):
171183, 1986.

On choosing the semistate vector x [x1, x2]T [y, u]T, where

T denotes transpose, one can write
E


dx
0
=
0
dt



D dx
1
=
0 dt
0


 
0
0
x+
u = Ax + Bu
1
1

y = [1 0]x = Cu

ROBERT W. NEWCOMB
LOUIZA SELLAMI
University of Maryland at College
Park

(11)
(12)

DIFFERENTIATION. See CALCULUS.

DIFFRACTION. See BACKSCATTER; ELECTROMAGNETIC

which gives


1
H(s) = [1 0]
0

1  
Ds
0
= Ds
1
1

WAVE SCATTERING.

(13)

These semistate equations can be transformed via a linear

transformation into a form that is useful for circuit realizations based upon integrators (3). Op-amp integrators are

DIGITAL FILTERS
FILTERS, DIGITAL
DISCRETE-TIME FILTERS
Most phenomena in nature occur in continuous time, such
as temperature change, lifetime of a human being, wind
speed at a given location, and so on. As a result, if we intend
to design a system to interfere with or to measure a natural phenomenon, the system should be analog. A widely
used procedure to design systems with interaction with a
natural phenomenon is to convert some quantities from
the nature into electric signals. Electric signals, which are
represented by voltage or current, have a continuous-time
form. However, continuous-time signals are not suitable to
be processed using computer-type processors (digital machines), which are meant to deal with sequential computation involving numbers. Fortunately, many signals taken
from nature can be fully represented by their sampled versions, where the sampled signals coincide with the original analog signals at predened time instants. Lets take
a real live example by supposing we are watching a movie
at home. If the movie is monotonous, we can pay attention to what is happening in the movie only from time to
time and still understand the story. On the other hand, if
the movie gives important information at short periods of
time, we can not miss it for a long time. In the latter case,
the director already made a tough sample of the story for
the viewer. In conclusion, if we know how fast the important information changes, we can always sample and convert the information in numbers for a fast enough digital
machine. Fortunately, the electronic technology is at our
side, by allowing very fast digital processors to be built at
a reasonable cost. This is one of the reasons the so called
digital lters, which are lters suitable to process sampled
signals implemented in digital machines, are replacing the
analog lters in a number of applications. Also, there are
a number of signals that are originally discrete-time, take
for example the stock-market daily nancial indicators.
The rapid development of high-speed digital integrated
circuit technology in the last three decades has made digital signal processing not only a tool for the simulation of
analog systems but also a technique for the implementation of very complex systems. Digital signal processing has
found applications in many areas such as image processing,
multimedia systems, speech analysis and synthesis, mobile
radio, sonar, radar, biomedical engineering, seismology, and
modern communication systems.
The main advantages of digital systems relative to analog systems are high reliability, ease of modifying the characteristics of the lter, and low cost. These advantages motivated the digital implementation of many signal processing systems, which were usually implemented with analog
circuit technology. In addition, a number of new applications became viable after the availability of the very-largescale integration (VLSI) technology. Usually in the VLSI
implementation of a digital signal processing system the

concern is in reducing power consumption or area, or in

increasing the circuits speed in order to meet the demands
of high-throughput applications.
The digital lter is in general the most important tool
in most digital signal processing systems. The digital lter processes signals that are discrete in time and in amplitude, that is, signals occurring at distinct and usually
equidistant times that can assume a discrete set of amplitude values. In this article, we are primarily concerned
with linear, shift-invariant digital lters implemented using nite-precision arithmetic.
In practice, a digital lter is implemented using software on a general-purpose digital computer or a digital signal processor (DSP), or by using application-specic hardware usually in the form of an integrated circuit. In any
type of implementation, quantization errors are inherent
due to nite-precision arithmetic. In implementations for
specic applications there are techniques such as algorithms and topologies for digital lters that allow us to
meet low-power, low-area, and/or high-speed specications.
The quantization errors can be classied as follows:
Roundoff errors resulting when the internal signals like
the output of multipliers are quantized before or after
additions
Errors in the magnitude and phase response of the lter
caused by the use of nite wordlength for the representation of the multiplier coefcients
Errors due to the representation of the input signal with
a set of discrete levels
The quantization errors described depend on the type of
arithmetic used in the actual implementation. If the digital lter is implemented on a general-purpose processor or
a DSP, oating-point arithmetic is usually available; therefore this type of arithmetic is the choice. On the other hand,
if the digital lter is implemented by means of applicationspecic hardware or lower cost DSPs, xed-point arithmetic is usually the best choice because of its low complexity in terms of silicon area for the hardware. In this article,
only xed-point arithmetic is addressed.
DIGITAL FILTERS
In a digital lter represented in the block diagram of Fig.
1, the input signal x(n) is a sequence of numbers, indexed
by the integer n, which can assume only a nite number
of amplitude values. Such input sequence comes, most of
the time, from an analog (or continuous-time) signal x(t) by
periodically sampling it at the time instants t = nT, where
T is called the sampling interval. The output sequence y(n)
is the response of the digital lter when excited by the input x(n), with the relationship between x(n) and y(n) represented by the operator H as

The most important class of digital lters is composed

by linear, time-invariant (LTI) and causal lters. A linear
digital lter is one whose response to a weighted sum of
input signals is equal to the same weighted sum of the

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Discrete-Time Filters

and the response of an LTI digital lter to x(n) can then be

expressed by

The summation in the last line of the above expression,

called the convolution sum, relates the output sequence of
a digital lter to its impulse response h(n) and to the input
sequence x(n). The convolution operation is represented by

Figure 1. Frequency response of the notch lter of Eq. (7) with r

= 0.9 and = /4.

By applying a change of variables in the summation of Eq.

(7), one can verify that the convolution operation is commutative; that is, the output of a digital lter with impulse
response h(n) and input x(n) is also given by

corresponding individual responses, that is,

for any sequences x1 (n) and x2 (n), and any arbitrary constants and . A digital lter is said to be time invariant
when its response to an input sequence is always the same,
independent of the time instant when the input is applied
to the lter (assuming that the lter is always operating
under the same initial conditions); that is, if H[x (n)] = y(n),
then

for all integers n and n0 . A causal digital lter is one whose

response does not depend on the future values of the excitation signal. Therefore, for any two input sequences x1 (n)
and x2 (n) such that x1 (n) = x2 (n) for n n0 , the corresponding responses of the digital lter (with same initial conditions) are identical, that is,

An LTI digital lter is completely characterized by its

response to the unit sample or impulse sequence (n) (assuming it is initially relaxed). The impulse sequence is dened as

and the lter response when excited by such a sequence is

denoted by h(n) and it is referred to as impulse response of
the digital lter. Observe that if the digital lter is causal,
then h(n) = 0 for n < 0. An arbitrary input sequence can
be expressed as a sum of delayed and weighted impulse
sequences; that is,

Dening the z transform of a sequence x(n) as

the transfer function of a digital lter is the ratio of the z

transform of the output sequence to the z transform of the
input signal; that is,

Taking the z transform of both sides of the convolution expression of Eq. (9), that is,

and substituting variables (m = n k),

the following relation among the z transforms of the output

Y(z), of the input X(z) and of the impulse response H(z) of
a digital lter is obtained:

Hence, the transfer function of an LTI digital lter is the z

transform of its impulse response.
SAMPLING RATE
Most of the signals encountered in science, such as speech,
biological signals, seismic signals, radar, and sonar, are
analog. To process them by a digital lter, they need to be
sampled and converted to digital by an analog-to-digital
(A/D) converter.

Discrete-Time Filters

The sampling theorem states that a bandlimited analog

signal x(t) whose highest frequency component is at the frequency fmax can be exactly recovered from its sample values
x(n) at the time instants t = nT, if the sampling frequency
fs = 1/T is larger than twice fmax . The sampling rate 2fmax is
called the Nyquist rate. The original continuous-time signal can be recovered from the sampled signal x(n) by the
interpolation formula

with s = 2fs .
The recovery of an analog signal from its samples by
the above interpolation formula is impractical, because it
involves the summation of innite duration functions and
the knowledge of future samples of the signal x(t) involved
in the summation. Practical circuits which convert back the
ltered signal to analog form are called digital-to-analog
(D/A) converters.
In general, if an analog signal x(t) is sampled with a
sampling frequency fs smaller than twice its maximum frequency fmax , then distinct frequency components of x(t) will
be mixed, causing an undesirable distortion in the recovered continuous-time signal referred to as aliasing.

The frequency response H(ej  ) is a periodic function of

 with period 2; that is,

for any integer k. Thinking in terms of analog frequency

(for sampled analog signals), the function H(e ja T ) is periodic in a with period 2/T = s . This periodicity is explained by observing that continuous-time sinusoidal signals of frequencies a and a + ks result, when sampled,
in identical sequences. Therefore, both signals must produce the same output when processed by the same digital
lter.
In general, H(ej  ) is a complex-valued function, which
can be expressed in polar form as

where |H(ej  )| and H(ej  ) are called the magnitude response and phase response, respectively, of the digital lter.
A large class of sequences can be expressed in the form

where

FREQUENCY RESPONSE
The response of an LTI digital lter to a complex exponential (or complex sinusoid) of radian frequency , that is,
x(n) = ej n for < n < , is a complex exponential of
the same frequency  with a possible complex amplitude
modication. Such property can be veried from the convolution expression of Eq. (9), where the output of a digital
lter with impulse response h(n) and excited by the complex exponential of frequency  is given by

In the above expression, H(ej  ) describes the changes in

amplitude introduced by the digital lter to the complex
exponential input signal. Such function of  is called the
frequency response of the digital lter, and it corresponds
to the transfer function H(z) evaluated on the unit circle in
the z plane (|z| = |ej  | = 1).
Observe that if the complex sinusoidal sequence comes
from sampling an analog sinusoidal signal, the relation between the frequency of the discrete-time sinusoid  and the
frequency of the continuous-time analog sinusoid a is obtained by making t = nT in the analog signal and equating
both signals, resulting in  = aT = a /fs . Hence, the digital
frequency is equivalent to the analog frequency normalized
by the sampling frequency, and, therefore, is always between and if the sampling theorem is satised. The
low frequencies are the frequencies  close to zero, whereas
the high frequencies are the frequencies close to , with 
= corresponding to the Nyquist frequency (a = s/2 ).

X(ej  ) is called the Fourier transform of the sequence x(n).

A sufcient but not necessary condition for the existence
of the Fourier transform X(ej  ) is that the sequence x(n) is
absolutely summable, that is,

Using the above Fourier representation, the input sequence can be written as the sum of the complex exponentials ej n weighted by X(ej  )d. From the superposition
property of linear systems, the output of the digital lter
with frequency response H(ej  ) and with x(n) as input is
given by the corresponding sum of the responses to each
complex exponential, that is,

Hence, each frequency component of the input sequence

x(n) is modied by the frequency response of the digital
lter at the corresponding frequency.
From Eq. (22) and from the denition of the Fourier
transform in Eq. (20), the frequency response of a digital
lter is the Fourier transform of its impulse response. From
Eq. (22), the Fourier transform of the output of a digital
lter is given by the product of the Fourier transforms of
the input and of the impulse response, that is,

Filters that select the low-frequency components of the input signal are called low-pass lters; those that select only
high-frequency components of the input are called highpass lters; bandpass and bandstop lters keep and reject,

Discrete-Time Filters

input values by

In the particular case when ak = 0 for k = 1, . . . , N, the

digital lter implemented by the above equation is called
a nonrecursive lter, because there is no feedback from the
past output in the computation of its present value. When
there is feedback, that is, ak = 0 for at least one k for k
= 1, . . . , N, the lter implementation given by the above
difference equation is called recursive.
The computation of each output value by Eq. (25) requires the storage of past samples of the input and output
sequences, the multiplication of these samples by the corresponding coefcients of the difference equation, and the addition of the results of such multiplications. Therefore, the
calculation of y(n) can be represented in a block diagram
through the interconnection of the three basic elements,
with symbols shown in Fig. 3: the unit delay, the multiplier, and the adder. The unit delay is represented by z1 ,
which is the transfer function associated with it. The block
diagram corresponding to Eq. (25) when there is feedback
(recursive implementation) is given in Fig. 4. Such lter
implementation is called a direct form I structure. Another
implementation of recursive digital lters which satises
Eq. (24) is based on the following pair of equations

Figure 2. (a) Frequency response of highpass lter of Eq. (8); (b)

Frequency response of comb lter of Eq. (9).

respectively, components in a frequency band in the interval 0  < . The ideal frequency responses of such lters
are illustrated in Fig. 2.
DIFFERENCE EQUATIONS

The block diagram of the resulting implementation is

shown in Fig. 5 and is called a direct form II structure.
The direct form II realization requires a number of unit
delays (or memory locations) equal to the maximum value
of M and N. This value is the minimum number of delays
needed to obtain the output of the lter satisfying Eq. (24),
and, therefore, the direct form II structure is said to be
canonic.
The block diagram corresponding to the nonrecursive
case is shown in Fig. 6, where there is no feedback of the
past output values.
The transfer function of a system with input and output
related by a difference equation can be obtained by taking
the z transform of both sides of Eq. (24), that is,

A large and important subclass of linear time-invariant

digital lters consists of the lters whose input and output
sequences satisfy an equation of the form
where we have used the linearity property of the z transform and the fact that the z transform of a delayed sequence
x(n nd ) is given by znd X(z), where X(z) is the z transform
of x(n). Thus, from the above equation,
where ak and bm are constant coefcients. The above equation is referred to as an Nth order difference equation. For
a causal lter with inputoutput related by the above difference equation with coefcients scaled such that a0 = 1,
the present value of the output y(n) can be computed from
the N past output values and from the present and M past

Therefore, the transfer function of a digital lter that satises Eq. (24) is a rational function of z; that is, it is given by a
ratio of polynomials in z, with the coefcients of such poly-

Discrete-Time Filters

Figure 3. Frequency responses of a fourth-order elliptic lter

realized with the normalized lattice structure, with coefcients
quantized to 12, 8 and 6 bits.

nomials equal to the coefcients of the difference equation.

The values of z for which H(z) = 0 are called the zeros of the
transfer function of the digital lter, and are the roots of
the numerator polynomial of H(z). The roots of the denominator polynomial of H(z) are called the poles of the digital
lters transfer function, and are the values of z for which
H(z) is innite. The transfer function H(z) can be written
in terms of its poles pk and zeros zm as

The above factored form of H(z) can be useful for estimating

the frequency response of a digital lter from its zeros and
poles. From Eq. (16), the frequency response of a digital
lter is equal to its transfer function evaluated on the unit
circle in the z plane, that is, at z = ej  . Representing the
differences (z zm ) for z = ej  in the z plane by the vectors
Cm and the differences (z pk ) for z = ej  by the vectors Dk ,
we can express the magnitude and phase of the frequency
response by

and

Figure 4. Recursive implementation of a digital lter obtained

from the difference equation given in Eq. (25) (direct form I structure).

with transfer function

where |Cm | and |Dk | represent the magnitudes of the vectors Cm and Dk , and Cm and Dk represent the angles of
the vectors Cm and Dk as related to the real axis measured
counterclockwise, respectively.
Figure 7 illustrates the polezero diagram as well as
the vectors dened above for the second-order digital lter

One can observe that for frequencies  near the zeros,

|H(ej  )| will be very small since the zeros are close to
the unit circle and the vectors from the zeros to ej  will
have small magnitudes. The phase response, H(ej  ), will

Discrete-Time Filters

Figure 5. Canionic recursive implementation obtained from the

pair of difference equations given in Eq. (26) (direct form II structure).

Figure 8. Frequency response of the digital lter with transfer

function H(z) given in Eq. (32).

Figure 6. Nonrecursive implementation of a digital lter from

the difference equation given in Eq. (25) with ak = 0 for k = 1, . . . ,
N.

Figure 7. Geometric frequency response evaluation from the

poles and zeros of the transfer function H(z) of Eq. (32).

change by almost rad near the zeros frequencies. For frequencies close to the poles, there will be a peak in |H(ej  )|,
and H(ej  ) will change by almost rad. Such frequency
response estimation can be veried in the plots of the magnitude and phase responses shown in Fig. 8.

FINITE IMPULSE RESPONSE FILTERS

A digital lter whose impulse response is of nite duration (i.e., it is zero outside a nite interval) is called a nite
impulse response (FIR) lter. From the convolution expression of Eq. (9), the output of a causal FIR lter with h(n) =
0 for n < 0 and for n > M is given by

Comparing the above expression with the output of the difference equation given in Eq. (25), we can observe that the
output of an FIR lter can be obtained by the nonrecursive
implementation of Fig. 4 with the multipliers bm equal to
the impulse response samples h(m). Usually FIR lters are
implemented nonrecursively, even though recursive implementations of FIR lters are also possible resulting in a
reduction in the number of multipliers in some cases.
The transfer function of an FIR lter has the form

which has all of its M poles at z = 0. Hence, an FIR lter

is characterized by the locations of the zeros of its transfer
function.
A simple example of an FIR lter is the moving average
lter, whose output is the average of the present and the

Discrete-Time Filters

last M samples of the input sequence; that is,

The transfer function of an FIR lter satisfying one of the

above conditions with M even is

The impulse response of this system is

and with M odd is

and its transfer function is given by

The zeros of H(z) are at zm = ej [2m/(M +1)] for m = 1, . . . , M.

From the rst line of the above equation, the output of this
system can be obtained by the nonrecursive implementation of Fig. 6 with coefcients bm = 1/(M + 1), for m = 0,
. . . , M. The second line of the above expression suggests a
recursive implementation such as that of Fig. 4, with the
nonzero coefcients given by a1 = 1, b0 = 1, and bM+1 =
1.
FIR lters are specially useful for implementing linearphase transfer functions, that is, transfer functions H(z)
such that

where the signs in the above equations represent the +

sign for symmetric impulse responses satisfying Eq. (42)
and for antisymmetric impulse responses as in Eq. (43).
The frequency responses corresponding to the above transfer functions with z = ej  can be written in the form

for symmetric impulse responses, and

for antisymmetric impulse responses, with R() being a

real-valued function of . For M even, the corresponding
group delay M/2 is an integer, and R() is given by

for a symmetric impulse response, and

The response of a linear-phase digital lter to a complex
sinusoid of frequency  is given by

which for integer is

Hence, the phase modication introduced by the linear

phase lter in the sinusoidal input signal corresponds to a
constant delay that is independent of . From the superposition property of LTI systems, an arbitrary signal x(n)
ltered by a linear phase lter will have all its frequency
components delayed by the same amount . Dening the
group delay of a lter as

a linear phase lter with phase response as in Eq. (38) has

a constant group delay .
An FIR lter with linear phase response can be easily
obtained by imposing one of the symmetry conditions below
on the impulse response of the lter:

or

for an antisymmetric impulse response, where h(M/2 ) = 0

in the latter case. For M odd, M/2 is not an integer, resulting
in a group delay that does not correspond to an integer
number of sampling periods. R() is given by

for a symmetric impulse response, and

for an antisymmetric impulse response.

An FIR lter with antisymmetric impulse response
presents a zero at z = 1 for M even or odd, and a zero
at z = 1 for M even, as can be seen from Eqs. (44) and
(45). Therefore, FIR lters with antisymmetric impulse responses cannot implement lowpass lters. Also, such lters cannot implement highpass lters when M is even.
An FIR lter with symmetric impulse responses and M odd
presents a zero at z = 1 and, therefore, cannot implement
highpass lters. The other zeros of a linear-phase FIR lter
H(z) are such that if zm is a zero of H(z), so is 1/z m .
An FIR lter can be designed truncating the innite impulse response of an ideal lter hideal (n) through the multiplication of hideal (n) by a nite length sequence w(n) called

Discrete-Time Filters

window. Other FIR lter design methods are based on optimization techniques, such as the Remez exchange algorithm, which minimizes the maximum deviation of the frequency response of the lter from a prescribed specication. Such design methods can be found elsewhere (1).

stop lters are, respectively,

HBP (z) = k

1 z2
1 2r cos z1 + r2 z2

(3)

1 2 cos z1 + z2
1 r2 z2

(4)

and
HBS (z) = k

INFINITE IMPULSE RESPONSE FILTERS

Filters with innite-length impulse responses are called innite impulse response (IIR) lters. The output of an IIR lter is obtained by a recursive implementation, such as the
direct-form structures shown in Figs. 4 and 5. The directform structures have high sensitivity to coefcient variations, especially when implementing transfer functions
with poles clustered close to the unit circle.
Other IIR lter structures, which present lower sensitivity than the direct form, are based on the implementations of the lter transfer function H(z) in a factored
form. In the cascade structure, H(z) is factored as a product of rst- and/or second-order transfer functions, which
are implemented separately by either one of the directform structures of Figs. 4 and 5 and connected in cascade.
The parallel structure is based on the implementation of
H(z) when expressed as a sum of rst- and/or second-order
transfer functions, obtained by partial fraction expansion
of H(z). The wave and lattice realizations, both presenting
low sensitivities, will be introduced in this article.
As opposed to FIR lters, IIR lters have poles in locations other than the origin of the z plane. To guarantee
stability of an IIR lter, that is, that an input of bounded
amplitude results in a bounded output sequence when processed by the lter, the poles of H(z) must lie inside the unit
circle in the z plane (1). The design of an IIR lter consists
of nding the coefcients or the poles and zeros of the transfer function, such that the frequency response of the lter
satises a given specication. Some IIR lter design techniques use established analog lter approximation methods with the application of a transformation technique to
the analog transfer function or impulse response to obtain
the digital transfer function. One of such transformations
is the bilinear transformation, where the variable s in the
transfer function of the analog lter is replaced by

with |r| < 1 for stability. The parameters r and determine,

respectively, the passband width and the center frequency
of the passband/stopband.
Some special IIR lters are allpass, notch, and comb lters. The allpass lters are useful for phase equalization,
and are characterized by having unity magnitude response
for all frequencies, i.e.,
|HAP (e j )| = 1,

HLP (z) = k

1 + z1
1 z1

(1)

(5)

The transfer function of an N-th order allpass lter is of

the form:

N

k=0
HAP (z) =

N

ak zN+k

k=0

ak zk

= zN

A(z1 )
A(z)

Observe that if z0 = re j is a pole of HAP (z), z1

0 =

(6)
1 j
e
r

will be a zero of HAP (z).

The notch lters are bandstop lters with very narrow
rejection band. They are useful in eliminating narrowband
noise, such as the 60-Hz power-line interference. A typical second-order notch transfer function has zeros over the
unity circle and poles close to it, with same angles , i.e.,
HN (z) =

1 2 cos z1 + z2
1 2r cos z1 + r2 z2

(7)

with |r| < 1. Figure 1 shows the frequency response of the

.
4
Comb lters nd application in pitch detection of speech
signals and cancellation of periodic interferences, among
others. Their frequency responses are periodic with period
2
, where M is a positive integer. The transfer function of a
M
comb lter can be obtained from a single passband transfer function H(z) by substituting zM for z, that is, HC (z)
= H(zM ). For example, the high-pass lter with transfer
function given by

notch lter of Eq. (7) with r = 0.9 and =

HHP (z) = 0.25

Other design techniques for IIR lters are based on optimization methods, such as the quasi-Newton method described elsewhere (1).
Examples of rst-order IIR low-pass and high-pass lters are, respectively,

for all

1 z1
1 + 0.5z1

(8)

and frequency response illustrated in Fig. 2(a), generates

the 8-band comb lter with transfer function
HC (z) = HHP (z8 ) = 0.25

1 z8
1 + 0.5z8

(9)

Its frequency response is shown in Fig. 2(b).

WAVE DIGITAL FILTERS

and
HHP (z) = k

1z
1 z1

(2)

with || < 1 for stability. The constant k determines the

lter gain, while the parameter controls the passband
width. Examples of second-order IIR bandpass and band-

The designer of lters, regardless of the implementation

technology, is usually interested in nding structures with
low sensitivity to coefcient variations. In digital lter design the low sensitivity implies small effect on the overall transfer function when the values of the coefcients

Discrete-Time Filters

deviate from their ideal values. As a result, the coefcients of a low-sensitivity digital lter can be implemented
with short wordlengths without violating the prescribed
specications. Also, coefcients with short wordlengths are
cheaper, faster, and simpler to implement. It is possible to
show that low-sensitivity realizations usually generate low
roundoff noise.
It is well known from classical analog circuit theory
that doubly terminated lossless lters have zero sensitivities of the transfer function with respect to the lossless
components at frequencies at which the maximal power
is transferred to the lter load. For lter approximations
with equiripple characteristics in the passband, such as
Chebyshev and elliptic lters, there are several frequencies in which maximal power transfers to the load. Because
the ripple values are small in the passband, the sensitivities remain small over the frequency range consisting of
the passband. As a result, several methods have been proposed attempting to imitate the behavior of the doubly terminated lossless lters.
The simplest and most widely used method of transformation of a transfer function from the Laplace (s-domain)
to the z-transform domain is the bilinear transformation
[see Eq. (52)]. This transformation is the one used to establish the correspondence between the analog prototype and
the wave digital lter. The bilinear transformation keeps a
frequency domain correspondence between the analog and
digital lters. The direct simulation of the internal quantities, such as voltages and currents, of the analog prototype
in the digital domain leads to delay-free loops. A delay-free
loop does not contain any delay, and as such cannot be computed sequentially since all node values in the loop are initially unknown (1). The values of the previous nodes must
be known before we start computing any value in the loop.
Alternative transformations can be tried; however, practice
has shown that it is desirable to use the bilinear transformation. As a solution a linear combination of voltage and
current are used in the transformation from continuous to
the discrete-time domain.
It is well known that any analog n-port network can
be characterized by using the concepts of incident and reected waves quantities known from scattering parameter
theory (5). Through the application of wave characterization, and the use of the bilinear transformation, digital lter realizations can be obtained from passive and active
lters as rst proposed by Fettweis (6, 7). By this means,
analog lters can be converted in digital lter structures
that are free from delay-free loops. The name wave digital lter derives from the fact that wave quantities are
used to represent the internal analog circuit signals in the
simulation in the digital domain. The possible wave quantities are voltage, current or power quantities. The choice of
power waves leads to more complicated digital realizations,
whereas the choice between voltage and current waves is
irrelevant. Traditionally, voltage wave quantities are the
choice in the open literature.
Another advantage of the wave digital lters imitating
doubly terminated lossless lters is their inherent stability
under linear conditions (i.e., innite precision arithmetic)
as well as in the nonlinear case where the signals are subjected to quantization. In the real-life nonlinear case, if

Figure 9. General representation of a generic one-port network.

magnitude truncation is applied to quantize suitable signals inside the wave digital lter structure, no zero-input
limit cycles can be sustained. Also, as will be discussed in
the section on quantization effects, the wave digital lters
are free of overow limit cycles when simple overow nonlinearities are employed such as saturation arithmetic.
The wave digital lters are also adequate to analog systems simulation, such as power systems, due to their topological equivalence with their analog counterparts.
An analog one-port network, see Fig. 9, can be described
in terms of wave characterization as

where a and b are the incident and reected voltage wave

quantities, respectively, and R is the port resistance assigned to the one-port network. The value of the port resistor is chosen appropriately to simplify the one-port realization. In the frequency domain the wave quantities are
A and B which are given by

In the equations above, we notice that the voltage waves

consist of a linear combination of the voltage and current
of the one-port network.
Consider now the case where the one-port impedance
consists of a single element. That is, Z(s) = csl , where l = 0
for a resistor, l = 1 for an inductor, l = 1 for a capacitor,
and c is a positive constant. Since

from Eq. (54), one can easily deduce the ratio between the
reected and incident voltage waves as follows:

By applying the bilinear transformation, that is, by substituting

the digital realization of the one-port network is obtained.

However, the choice of the port resistance is crucial to obtain a simple realization, where in the present case the
choice is

For the capacitor, the port resistor is chosen as R = T/2C,

where T is the sample period and C is the value of the
capacitor, leading to a digital realization of the wave ratio

10

Discrete-Time Filters

Figure 11. (a) Parallel connection of two ports. (b) Realization of

two-port adaptor.

Because V1 = V2 and I1 = I2 , we have that

Figure 10. Wave digital realization of the main one port elements.

If we eliminate V1 and I1 in the above equations we have

1

as B/A = z . For the resistor the choice is R = R, where R

is the resistor value and the resulting digital realization is
B/A = 0. Finally, the inductor is simulated by B/A = z1 if
R = 2L/T, where L is the inductor value. Figure 10 depicts
the realization of some important one-port elements.
Similarly an analog N-port network can be described in
terms of wave characterization as

for i = 1, . . . , N, where the parameters Ai and Bi are the incident and reected voltage wave quantities, respectively,
and Ri is the resistance of port i.
The main multiport elements required in the wave digital lter realization are the adaptors. The adaptors guarantee that the current and voltage Kirchoff laws are satised
at the series and parallel interconnections of ports with
different port resistances.
Consider the interconnection of two elements with port
resistances given by R1 and R2 , respectively, as shown in
Fig. 11(a). The wave equations in this case are given by

where = (R1 R2 )/(R1 + R2 ). A realization for the twoport adaptor is depicted in Fig. 11(b). It should be noted
that there are other realizations for the two-port adaptor.
The same approach can be extended to derive the threeport series and parallel adaptors. The parallel interconnection of three ports is shown in Fig. 12(a), where we have
V1 = V2 = V3 , I1 + I2 + I3 = 0, and Gi = 1/Ri . The digital
realization of the parallel adaptor has internal multipliers
whose coefcients are given by

Because 1 + 2 + 3 =2, one of the required multiplier

coefcients can be eliminated. With the denition above,
after a few manipulations one can show that a possible set
of relations between the incident and reected waves is
given by

The realization corresponding to these equations is shown

in Fig. 12(b).

Discrete-Time Filters

Figure 12. (a) Parallel connection of three ports. (b) A possible

realization of a three-port parallel adaptor. (c) Interconnection between two adaptors. (d) Realization of a reection-free three-port
parallel adaptor 2 = 1 1 .

If two adaptors are connected directly, a delay-free loop

appears between the adaptors as shown in Fig. 12(c). A solution to this problem is to constrain one of the coefcients
of the adaptor to be equal to one, for example 3 = 1. In this
case, the adaptor equations are given by

11

Figure 13. (a) Series connection of three ports. (b) A possible

realization of a three-port parallel adaptor. (c) Realization of a
reection-free three-port series adaptor.

The series interconnection of three ports is shown in

Fig. 13(a), where we have V1 + V2 + V3 = 0 and I1 = I2 = I3 .
The equations related to the series adaptor are derived by
following the same procedure used for the parallel adaptor.
The resulting equations are

where

where since 1 + 2 = 1, one of the required multiplier

coefcients can also be eliminated. The realization of the
reection-free is depicted in Fig. 12(d), where it can be veried that there is no direct path between A3 and B3 . As
a consequence, the reection-free property of port three is
key to allow the connection between adaptors.

for i = 1, 2, 3. The realization corresponding to these equations is shown in Fig. 13(b). The reection-free series adaptor can be generated by considering 3 = 1.
As an illustration, consider the third-order elliptic lowpass analog lter depicted in Fig. 14(a). The corresponding
wave-digital realization is shown in Fig. 14(b), where the
multiplier coefcients of the adaptors are calculated as fol-

12

Discrete-Time Filters

reduction strategy. Dene the polynomial

We calculate a reduced order polynomial as

where

Note that the rst and last coefcients of DN (z) are 1 and
aN,N , whereas the rst and last elements of the polynomial
zBN (z) are aN,N and 1, respectively. This strategy to achieve
the order reduction turns the polynomial DN1 (z) monic
(i.e., with the leading coefcient equal to one).
By induction, this procedure can be repeated as described in the following equations:
Figure 14. (a) LC doubly-terminated ladder; element values: C1
= C3 = 0.968F, C2 = 0.085F , L = 1.058H, R1 = R2 = 1 . (b) A possible
wave digital realization. Notice that there are other choices for the
position of the reection-free ports. The sampling period is T = 14
s.

lows:

because

following similar procedure for the remaining elements we

have

for j = N, N 1, . . . , 0, where zB0 (z) = D0 (z) = 1.

The pair of equations above leads to a convenient relation given by:

Assuming that we can implement the desired denominator using the recursion above, it is required that we implement the numerator polynomial as well. The convenient
way to form the desired numerator is to apply weights to
the polynomials zBj (z) such that:

where the tap-coefcients are calculated through the following order-reduction recursion:

for j = M, M 1, . . . , 1, and v0 = b0,0 .

The overall transfer function of the lattice structure is

LATTICE FILTERS
The general transfer function we aim to realize using the
lattice structure is described by

In the lattice construction, we rst concentrate in the realization of the denominator polynomial through an order-

The recursive lattice realization derives from Eqs. (75) and

(78) in a simple way. Let us consider that the relations
represented in Eq. (75) divided by DN (z) (due to the recursive structure) is implemented through a two-port network. Starting with zB0 (z)/DN (z) = D0 (z)/DN (z) = 1/DN (z),
the structure of Fig. 15(a) results. Figure 15(b) depicts a
realization for the two-port network.
There are some properties related to the lattice realization that are worth mentioning. If DN (z) has all the roots

Discrete-Time Filters

13

Figure 15. (a) General lattice digital lter structure. (b) The two-multiplier realization of the twoport network. (c) The single-multiplier realization of the two-port network. The plus and minus signs
indicates that two different realizations are possible. The choice of these signs can vary from section
to section aiming the reduction of the quantization noise at the lter output. (d) The normalized
section for the lattice structure.

inside the unit circle the lattice structure will have all coefcients aj,j with magnitude less than one. Otherwise H(z)
represents an unstable system. The straightforward stability test turns the lattice realization useful to implement
time-varying lters. Also in the lattice realization, the polynomials zBj (z) for j = 0, . . . , M, form an orthogonal set; this
feature justies the choice of these polynomials to form the
desired numerator polynomial NM (z).
The overall transfer function of the lattice realization
will not change if any kind of internal scaling is applied to
the internal signals in the following way:

where the numerator coefcients have to be scaled according to v j = vj /kj , with k j = kj kj1 k1 . Each coefcient ki is
the individual scaling factor applied to the lattice section i.
With this possibility, we can derive a more economical twoport network using a single multiplier as shown in Fig.
15(c).
Another important realization for the two-port network
results when the scaling parameters ki are chosen such
j (z) become orthonormal. The apthat the polynomials zB
propriate scaling can be easily derived by induction if we
recall that zB0 (z) = A0 (z) = 1. Since

1 (z)] if we mula polynomial with unit

norm results [i.e., zB
2
tiply zB1 (z) by k1 = 1/ 1 a1,1
. Identically, we can easily
show that

1 (z) has unit norm, zB2 (z) will have unit norm if
Because zB

2
we choose k2 = 1/ 1 a2,2
. Following a similar procedure,
we can show that
the
appropriate
value for the scaling fac
tor j is kj = 1/

1 a1, j . After a few manipulations of Eqs.

(76) and (80), we can show that the two-port section of the
normalized lattice is as depicted in Fig. 15(d). The most
important feature of the normalized lattice realization is
that all its internal nodes have unit energy leading to an
automatic scaling in the L2 norm sense. This explains the
low roundoff noise generated by the normalized lattice realization as compared with the other forms of the lattice
realization.
QUANTIZATION EFFECTS IN DIGITAL FILTERS
The choice of a digital lter structure for a given application
is based on evaluating the performance of known structures and choosing the most suitable one. The effects of
quantization are important factors to be considered when
assessing the performance of digital lter structures.

14

Discrete-Time Filters

Figure 16. Model for the noise generated after a multiplication.

Quantization Noise
A number with modulus less than one can be represented
in xed-point arithmetic as follows:

where b0 is the sign bit and b1 b2 b3 bb represents the modulus of the number using a binary code. The most widely
used binary code is the twos-complement representation
where for positive numbers b0 = 0 and for negative numbers b0 = 1. The fractionary part of the number, called x2
here, is represented as

In oating-point a number is represented as

where xm is the mantissa and c is the number exponent,

with |xm | < 1. In oating-point arithmetic, the mantissa must be quantized after every multiplication and addition, whereas in xed-point arithmetic quantization is
required only after multiplications. The main advantage
of the oating-point representation is the large dynamic
range, while xed-point representations are easier to implement. Our discussion from now on concentrates in the
xed-point implementation.
A nite-wordlength multiplier can be modeled in terms
of an ideal multiplier followed by a single noise source e(n)
as shown in Fig. 16. If the product quantization is performed by rounding and the signal levels throughout the
lter are much larger than the quantization step q = 2b , it
can be shown that the power spectral density of the noise
source ei (n) is given by

Figure 17. Digital lter including scaling and the relevant transfer functions for scaling, noise analysis and sensitivity calculation.

A gure of merit usually employed in evaluating the

performance of digital lters is the relative power spectral
density (RSPD) of the output noise in decibels given by

The RPSD eliminates the dependence of the output noise

on the wordlength. Hence the RPSD is a measure of the
extent to which the output noise depends upon the internal
structure of the lter.
Another useful performance criterion to evaluate the
roundoff-noise generated in digital lters is the noise gain
or the relative noise variance (1, 2) given by

where we used the relation

The input signal quantization is similar to product

quantization and can be represented by including a noise
source at the input of the digital lter structure.
Granularity Limit Cycles

which means that ei (n) represents a zero mean white-noise

process. Also, we can consider that in practice ei (n) and ej (n
+ l) are statistically independent for any value of n or l (for
i= j). As a consequence the contributions of different noise
sources can be accounted for separately using the principle
of superposition.
In a xed-point digital-lter implementation, the power
spectral density of the output noise is given by

where Pe (ej  ) = 2 e , Gi (z) are the transfer functions from

each multiplier output [gi (n)] to the output of the lter as
shown in Fig. 17. The wordlength, including sign, is b + 1
bits and K is the number of multipliers of the lter.

On many occasions, signal levels in a digital lter can become constant or very low, at least for short periods of
time. Under such circumstances, the noise signals become
highly correlated from sample to sample and from source to
source. This correlation can cause autonomous oscillations
called granularity limit cycles.
Limit-cycles oscillations can occur in recursive digital
lters implemented with rounding, magnitude truncation
(where the magnitude of the number is reduced aiming the
decrease of its energy), and other types of quantization.
In many applications, the presence of limit cycles can be
a serious problem. Thus, it is desirable to eliminate limit
cycles or to keep their amplitude bounds low.
For wave and lattice digital lters and some secondorder structures, the stability under nite precision arithmetic can be proved by means of the second method of Lyapunov. Magnitude truncation is applied to quantize suit-

Discrete-Time Filters

15

Figure 19. Regions allowed for the overow nonlinearities in order to guarantee freedom from overow limit cycles.
Figure 18. Digital lter including quantizers at the delay inputs.

able signals inside the structure such that a dened positive denite pseudoenergy function is proved to be a Lyapunov function.
The concept of pseudoenergy function can be applied
to show how to eliminate zero-input limit cycles in some
digital lter structures, for example, in wave, lattice, and
state-space digital lter structures. The basic strategy is
to apply magnitude truncation to the state variables of the
digital lter, namely the delay inputs. An interesting result
(11) establishes how constant-input limit cycles can also be
eliminated in digital lters in which zero-input limit cycles
can be eliminated.
In a recursive lter implemented with xed-point arithmetic each internal loop contains a quantizer in order to
keep the wordlength limited. Assuming that the quantizers are placed at the delay input (i.e., at the state variables
as shown in Fig. 18), we can describe the digital lter, including the quantizers, using the statestate formulation
as follows:

where []Q indicates the quantized value of [], A is the state

matrix, b is the input vector, c is the output vector, and
d represents the direct connection between the input and
output of the lter.
Given that the digital lter has a state matrix with
eigenvalues inside the unit circle such that

where G is an N N diagonal positive denite matrix, and

u is any N 1 vector. Then, the granular zero-input limit
cycles can be eliminated if the quantization is performed
through magnitude truncation. In this case, the quadratic
energy function given by

is used as Lyapunov function.

Overow Limit Cycles
Overow limit cycles can occur when the magnitude of
the internal signals exceed the available register range.
To avoid the increase of the signal wordlength in recursive digital lters, overow nonlinearities must be applied
to the signal. Overow nonlinearities inuence the most
signicant bits of the signal causing severe distortion. An

Figure 20. A second-order digital lter including a granularity

and overow quantizer.

overow can give rise to self-sustained, high-amplitude oscillations known as overow limit cycles.
A digital lter structure is considered as free of overow
limit cycles or to have a stable forced response if the error,
which is introduced in the lter after an overow, decreases
with time in such a way that the output of the nonlinear
lter (including the quantizers) converges to the output of
the ideal linear lter (10).
A digital lter that is free of zero-input limit cycles, according to the condition of Eq. (92), is also forced-input stable if the overow nonlinearities are in the shaded regions
of Fig. 19. Figure 20 illustrates a digital lter realization
incorporating a quantizer implementing rounding for the
granular quantization and saturation arithmetic for the
overow nonlinearity.
In the presence of input signal, overow can occur in any
digital lter structure. As a consequence, input signal scaling is required to reduce the probability of overow to an
acceptable level. Ideally, signal scaling should be applied
so as to ensure that the probability of overow is the same
at each internal node of the digital lter, to maximize the
signal to noise ratio in xed-point implementations.
The choice of twos complement arithmetic leads to a
simplied scaling technique, where only the multiplier inputs require to be scaled. Specically, in this type of number representation the addition of two or more numbers
will be correct independently of the order in which they
are added even if overow occurs in a partial summation,
as long as the overall sum is within the available range of
representable numbers. In this scaling technique a scaling
multiplier is used at the input of the lter section as illustrated in Fig. 17. We know that the signal at the multiplier

16

Discrete-Time Filters

input is given by

The variation in the magnitude response of the digital

lter due to the variations in the multiplier coefcients are
approximated by

where c is the convergence region common to Fi (z) and U(z).

The constant is usually chosen on the basis of the Lp
norm of the transfer function from the lter input to the
multiplier input Fi (z), depending on the known properties
of the input signal. The Lp norm of Fi (z) is dened as

where mi , i = 1, 2, . . . , K, are the multiplier coefcients of

the digital lter. If we consider that the multiplier coefcients were rounded and that the errors introduced are
statistically independent, the variance of the error in each
coefcient is given by

for each p 1, such that 2 0 |Fi (ej  )|p d . In general

the following expression is valid
where b is the number of fractionary bits.
With the assumptions above the variance of |H(ej  )| is
given by
for p, q = 1, 2 and .
The scaling ensures that the amplitudes of multiplier
inputs are bounded by a number M when |u(n)| M. Therefore, to ensure that all multiplier inputs are bounded by M,
we must choose as follows

which means that

where K is the number of multipliers in the lter section.

The norm p is usually chosen to be innity or 2. The L
norm is used for input signals that have some dominating
frequency component, whereas the L2 norm is most commonly used for random input signal. Usually, the scaling
coefcients are powers of two, provided they satisfy the
overow constraints. In this way, the scaling parameters
can be implemented by simple shift operations.
In case of modular realizations such as cascade or parallel realizations of digital lters, optimum scaling is accomplished by applying one scaling multiplier per section.
Coefcient Quantization
During the approximation step the coefcients of a digital
lter are calculated with high accuracy. If these coefcients
are quantized, the frequency response of the realized digital lter will deviate from the ideal response. In fact, the
quantized lter may even fail to meet the prescribed specications. The sensitivity of the lter response to errors in
the coefcients is highly dependent on the type of structure.
This fact led to the development of low-sensitivity digital
lter realizations such as the wave and lattice.
Several sensitivity criteria exist to evaluate the effect of
the variation of a coefcient value on the digital lter transfer function. In this article, the sensitivity of the transfer
function H(z) with respect to variations in the multiplier
constant mi is dened as

If we assume that |H(ej  )| has a Gaussian distribution, it

is possible to estimate the probability of |H(ej  )| as less
or equal to x|H(e j )| . The equation below estimates the
number of bits that are required in the fractionary part for
a given digital lter to meet a given modulus specication.

where () is the tolerance on the magnitude response

given in the specications Hd (ej  ).
Example:
An elliptic bandpass lter was designed satisfying the
following prescribed specications:

Maximum ripple in the passband: 1 dB.

Minimum attenuation in the stopband: 30 dB.
Passband frequency range: 2880 to 3120 Hertz.
Stopband frequency edges: 2450 and 3550 Hertz.
Sampling frequency: 10000 Hertz.

The resulting lter has order four.

In order to access the coefcient quantization effects of
a given realization, the fourth-order elliptic lter was implemented utilizing a normalized lattice structure. The coefcients of the lattice are displayed in Table 1. These coefcients are then quantized to 12, 8 and 6 bits, respectively.
The resulting transfer functions are depicted in Figure 3.
As can be observed the transfer functions for 8 and 6 bits
deviate substantially from the desired one, whereas 12 bits
leads to acceptable results.
A procedure widely used in practice to evaluate the design of digital lters with nite-coefcient wordlength is to
design the lters with tighter specications than required,
quantize the coefcients, and check if the prescribed specications are still met.

Discrete-Time Filters

17

Figure 21. (a) Full adder; (b) bit-parallel; (c) bit-serial adder; (d) serial/parallel multiplier.
Table 1. Normalized Lattice Coefcients
ajj
vj
0
1
2
3
4

0.31382198601433
0.98733578085783
0.30596231306686
0.85033475836150

0.01451571512296
0.01127246045032
0.01164209398292
0.00464776905230
0.03432034632233

DIGITAL FILTER IMPLEMENTATION

Digital lters can be implemented by software in generalpurpose computers, in digital signal processor (DSP) chips,
or by hardware in special-purpose logic circuits. Although
software implementations allow rapid prototyping and
exibility in testing and modifying the lter characteristics, special-purpose hardware implementations allow for
higher-speed and lower-consumption performances.
A software implementation consists of generating the
program code corresponding to the digital lter structure
being implemented, in a high-level language or directly
in assembly language. A compiler then generates a set of
instructions to the processor from the code. Because, in
general-purpose computers the instructions are executed
sequentially, the speed of the digital lter becomes limited

by the execution time of each instruction. Digital signal

processor chips are specially designed to execute very efciently sum-of-product operations, which are the main computations required in the implementation of digital lters
and of other digital processing algorithms, as can be seen
in Figs. 4, 5, 6, 14, and 15. The efcient implementation
of the multiply-and-accumulate operation, as well as the
high-degree of parallelism with which the instructions are
executed in a DSP, result in a relatively high inputoutput
throughput rate.
A hardware implementation consists in the design and
integration of a digital circuit, specied in terms of logical
gates. Advances as well as reduction in costs of integrated
circuit technologies have made special-purpose hardware
implementations of digital lters even more attractive
for high-speed real-time applications and/or for large production quantities. Besides providing higher-speed and
lower-power consumption, hardware implementations using VLSI (very-large-scale integration) technologies permit to include in a single chip not only a digital lter but
a whole signal processing system. Arithmetic operations
required in the implementation of digital lters can be
performed either in bit-serial or in bit-parallel form. The
bit-parallel implementation of arithmetic operations uses

18

Discrete-Time Filters

a basic element the full-adder shown in Fig. 21(a), which

adds the two input-bits a and b, and the carry-in bit c,
resulting in a sum bit and an output carry bit. The sum
of two (b + 1)-bit numbers, A and B, in bit-parallel arithmetic can be implemented by connecting (b + 1) full-adders,
one for each bit, as shown in Fig. 21(b), where ai and bi
represent the ith bit of A and B, respectively, with ab and
bb corresponding to the least signicant bits (LSB). A bitparallel implementation for the product of two numbers
A and B uses a full-adder for the partial sum of each bit
product ai bk , requiring about b(b + 1) full-adders. Reduction in chip area can be achieved by using bit-serial arithmetic. In such an implementation approach, the bits are
processed one at each clock period, with the LSB treated
rst. A bit-serial adder is shown in Fig. 21(c), where D represents a one-bit delay (or a ip-op) and CLR is set to zero
during the processing of the LSB. A serial/parallel implementation of a multiplier (for B > 0) is shown in Fig. 21(d),
where A is treated in bit-parallel form, whereas B is processed in bit-serial form. More details and other implementations of bit-serial, bit-parallel, and serial/parallel arithmetics can be found elsewhere (4). A different hardware implementation approach of digital lters, called distributed
arithmetic, uses a look-up table to obtain partial results of
the required sum-of-products. Such approach uses memory
(corresponding to the look-up table) to replace most of the
circuitry required to implement the computations.
The execution speed of the operations as well as the
degree of parallelism associated to the digital lter implementation determine the maximum sampling rate for
which the lter can operate. To increase this maximum
rate, block processing algorithms have been proposed,
where a block of output samples is calculated using a block
of input samples. There is a delay in the production of the
output samples in such algorithms, which might not be tolerable in some real-time applications. More details of block
processing algorithms are given elsewhere (2, 3).

BIBLIOGRAPHY
1. P. S. R. Diniz, E. A. B. da Silva, and S. L. Netto. Digital Signal Processing, System Analysis and Design. Cambridge, UK:
Cambridge, 2002.
2. A. Antoniou. Digital Signal Processing. New York, NY: McGraw Hill, 2006.
3. S. K. Mitra. Digital Signal Processing. New York, NY: McGraw
Hill, 3rd Edition, 2005.
4. L. Wanhammer. DSP Integrated Circuits. New York, NY: Academic Press, 1999.
5. V. Belevitch. Classical Network Theory. San Francisco, CA:
Holden-Day, 1968.
6. A. Fettweis. Digital lters structures related to classical lters
networks. Archiv. fur Elektronik und Ubertragungstechnik, 25:
7989, 1971.
7. A. Fettweis. Wave digital lters: theory and practice. Proc.
IEEE, 74: 270327, 1986.
8. A. H. Gray, Jr. and J. D. Markel. Digital lattice and ladder lter
synthesis. IEEE Trans. Audio Electroacoust., AU-21: 491500,
1973.

9. A. H. Gray, Jr. and J. D. Markel. A normalized digital lter

structure. IEEE Trans. Acoust. Speech Signal Process., ASSP23: 268277, 1975.
10. T. A. C. M. Claasen, W. F. G. Mecklenbrauker,

and J. B. H. Peek.
On the stability of the forced response of digital lters with
overow nonlinearities. IEEE Trans. Circuits Syst., CAS-22:
692696, 1975.
11. P. S. R. Diniz, and A. Antoniou. More economical state-space
digital lter structures which are free of constant-input limit
cycles. IEEE Trans. Acoust. Speech Signal Process., ASSP-34:
807815, 1986.

PAULO S. R. DINIZ
MARIANE R. PETRAGLIA
Federal University of Rio de
Janeiro, Rio de Janeiro,
Brazil
Federal University of Rio de
Janeiro, Rio de Janeiro,
Brazil

518

DIGITAL-TO-ANALOG CONVERSION

put digital word Di. bN is the most significant bit (MSB), and
b1 is the least significant bit (LSB). The digital-to-analog
(D/A) conversion is a linear mapping of the input digital word
to the analog output. Although purely current-output DACs
are possible, voltage-output DACs are more common.
Because digital numbers are limited in length, the number
of different possible DAC output levels depends on the number of bits used to form digital input word. For example, a
DAC with two-bit digital word can have four possible outputs.
A digital number of 00 represents one possible output,
whereas 01, 10, and 11 each represents a different distinct
output. That is, the total number of the output levels of a
DAC using an N-bit long digital input word is 2N. Therefore,
the step size between the outputs created by two adjacent digital input words is Vr /2N. This value represents the minimum
voltage that can be resolved by an N-bit DAC. The resolution
of a DAC is defined as the minimum resolvable output step,
but the number of bits used for the digital input word is also
quoted as resolution. In a strict sense, it is impossible to represent an analog waveform accurately with any limited number of discrete levels. However, real applications are limited
either by noise or by other system requirements and need no
finer resolution than necessary. For example, a video signal
digitized with 8-bit resolution is sufficient for the current
video standard, whereas CD players use 16 bit data to reproduce music.

DIGITAL-TO-ANALOG CONVERSION
FUNDAMENTALS OF D/A CONVERSION
All electrical signals in the real world are analog in nature,
and their waveforms are continuous in time. However, most
signal processing is done numerically in a sample data form
in discrete time. A device that converts a stream of discrete
digital numbers into an analog waveform is called a digitalto-analog converter (DAC). One familiar example of a DAC
application is the CD player. Digital bits, 1s and 0s, stored in
the CD represent the electrical music waveform sampled in
discrete time. DACs inside CD players convert the digital
data stream read from optical discs into an audible sound
waveform. DACs are used as stand-alone devices or as subblocks of other systems, such as analog-to-digital converters
(ADCs), and cover the frequency spectrum from subsonic to
microwave frequencies. Some examples of the systems in
which DACs play an integral role are TV monitors, graphic
display systems, digital voice/music/video systems, digital
servo controllers, test systems, waveform generators, digital
transmitters in modern digital communications systems, and
multimedia systems (1).
DAC Resolution
The basic function of a DAC is the conversion of a digital
number into an analog level. An N-bit DAC generates a discrete analog output level, either voltage or current, for every
digital input word. The maximum range of the DAC is set by
the reference voltage or current. In mathematical terms, the
output of an ideal voltage DAC can be represented as

V0 (Di ) =

b
bN
b2
b
+ N1
+ + N1
+ N1
2
22
2
2


Vr

(1)

where Vr is a reference voltage setting the output range of the

DAC and bNbN1 b1 is the binary representation of the in-

Static and Dynamic Performance

An ideal N-bit voltage DAC generates 2N discrete analog output voltages for digital inputs varying from 000 . . . 0 to 111
. . . 1 as illustrated in Fig. 1(a) for the ideal 4 bit DAC example. In the unipolar case, the reference point is the lowest
output of the range when the digital input D0 is 000 . . . 0.
However, in the bipolar case or in differential DACs, the reference point is the midpoint of the full scale when the digital
input is 100 . . . 0, whereas 000 . . . 0 and 111 . . . 1 represent the most negative and most positive DAC input ranges,
respectively. An ideal DAC has a uniform step size and displays a linear transfer characteristic with a constant slope.
However, in reality, the DAC transfer characteristic is far
from being ideal as shown in Fig. 1(b). First, typical DACs
have variance in step size and a curvature in the transfer
characteristic measured in terms of differential and integral
nonlinearities (DNL and INL), respectively. In addition, the
overall transfer curve shifts up or down, and the slope is different from the ideal one. The former is defined as offset error, and the latter as gain error.
DAC performance is limited by two factors. One is the
static linearity in representing digital numbers with a finite
number of discrete output levels, and the other is the dynamic
accuracy in the transition from one level to another. The D/A
conversion process is illustrated in Fig. 2(a) with time-domain
waveforms on the left and frequency spectrums on the right.
Figure 2(b) shows the sampled digital waveform and its spectrum repeating at multiples of the sampling frequency f s. Because the impulse response does not exist in the analog domain, the ideal D/A conversion is a sample-and-hold
operation as shown in Fig. 2(c). It is still assumed that the
DAC output is fast enough to make a step response. This sample-and-hold process exhibits a frequency response of a
(sin x)/x function. If this sample-and-held waveform is low-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

DIGITAL-TO-ANALOG CONVERSION

Vr

519

Vr

Analog output

Analog output

INL

Vr
2

0
0000

1000
Digital input

Offset

Vr

DNL

1 LSB

Gain error

0
0000

1111

1000
Digital input

(a)

(b)

Figure 1. DAC transfer characteristics: (a) ideal case and (b) nonideal case.

Frequency

Time

(a)

Time

fs

Frequency

(b)

Time

fs

Frequency

(c)
Figure 2. D/A conversion process: (a) input and its spectrum, (b) sampled data and its spectrum,
and (c) sample-and-held DAC output and its spectrum.

1111

520

DIGITAL-TO-ANALOG CONVERSION

termodulation from DAC nonlinearity is the most critical issue because strong interfering tones produce inband spurious
components and degrade the inband SNR. The DAC performance for such applications is often measured as spuriousfree dynamic range (SFDR), which is the ratio of the maximum signal component and the largest spurious component.
The INL is the key design factor for low SFDR applications.

P(Q x)
1

Qx

DNL and INL

Figure 3. Density function of the quantization noise.

pass filtered, the original signal is restored except for a gain

droop resulting from the (sin x)/x function. In practice, the
DAC output cannot change instantaneously, and real DACs
are designed to settle exponentially from one level to another.
Therefore, the dynamic performance depends heavily on the
actual implementation.

The fundamental limit of the DAC performance is SNR, but

it is more likely that DAC performance is limited by spurious
and harmonic components. The DAC nonlinearity can be measured by DNL and INL. DNL is a measure of deviation of
actual step size from the ideal size. Similarly, INL is defined
as a measure of deviation of the midpoint of the actual step
from the midpoint of the ideal step. DNL and INL are indicators of how ideal a DAC is and can be defined in an N-bit
voltage DAC as

Signal-to-Noise Ratio
The lower bound in DAC resolution is set by the step size of
the minimum incremental amount of the DAC output. Ideally
this finite step size of the DAC output appears as a random
noise in the D/A conversion. It is similar to the quantization
noise of the A/D conversion process. The random noise can be
modeled as an ideal DAC with an additive random noise
source between values of Vr /2N1 to Vr /2N1 as illustrated in
the probability density function of Fig. 3, where is Vr /2N.
Estimating the noise as the difference between the actual input and the nearest level, the noise Qx(n) lies between



Qx (n)
2
2

(2)

as shown in Fig. 3. Then the average noise power 2 can be

calculated as

2 =

/2
/2

x2
2
dx =

12

(3)

The signal-to-noise ratio (SNR) is defined as the power ratio

of the maximum signal to the inband uncorrelated noise. Because the maximum signal power is Vr2 /8, the well-known relation of the noise is derived using Eq. (3) as

SNR = 10 log

32
2

2N


(6.02N + 1.76) dB

(4)

If the number of bits increases by one, noise is lowered by

about 6 dB.
The SNR accounts for inband uncorrelated noise only. In
reality, the DAC transfer characteristic is not linear, and the
nonlinearity in the D/A conversion process appears as harmonics or intermodulation components in the DAC output.
Considering nonlinearity, DAC performance is more accurately defined using the total signal-to-noise ratio (TSNR) or
sometimes referred to as the signal-to-noise-and-distortion ratio (SNDR). For an ideal DAC without nonlinearity, noise is
limited only by quantization, and SNDR should be identical
to SNR. In some applications such as generating complex
spectrums in wireless radio-frequency (RF) systems, the in-

DNL(Di ) =

V0 (Di+1 ) V0 (Di ) Vr /2N

Vr /2N

(5)

V0 (Di ) i Vr /2N
Vr /2N

(6)

INL(Di ) =

for i 0, 1, . . ., 2N 1. DNL and INL are normalized to the

ideal one LSB step, and the largest positive and negative
numbers for both DNL and INL are usually quoted to specify
the static performance of a DAC.
Several different definitions of INL may result depending
on how two endpoints are defined. The two endpoints are not
exactly 0 and Vr because of the offset and gain errors explained in Fig. 1(b). In most DAC applications, the offset and
gain errors resulting from the nonideal endpoints do not matter, and the integral linearity can be better defined in a relative measure using the straight-line linearity concept rather
than the endpoint linearity in the absolute measure. The
straight line can be defined as two endpoints of the actual
DAC output voltages or as a theoretical straight line adjusted
to best fit the actual DAC output characteristic. The former
definition is sometimes called endpoint linearity, whereas the
latter is called best-straight-line linearity.
Monotonicity
A DAC is monotonic if its output increases as the digital input
increases. The condition for monotonicity requires that the
derivative of the transfer function never change sign and that
the DNL be better than 1 LSB. Monotonicity of a DAC is
important in all DAC applications, but it is a necessity in
such applications as digital control and video. The worst DNL
and INL in binary-weighted DACs usually appear at a major
transition point. The major transition point is the point at
which the MSB changes in the digital input such as between
011 . . . 1 and 100 . . . 0. If the MSB weight is smaller than
the ideal value (1/2 of the full range), the analog output
change can be smaller than the ideal step Vr /2N when the
MSB changes. If the decrease in the output is larger than one
LSB, the DAC becomes nonmonotonic. The similar nonmonotonicity can take place when switching the second or lower
MSB bits in binary-weighted multibit DACs.

DIGITAL-TO-ANALOG CONVERSION

Monotonicity is inherently guaranteed if an N-bit DAC is

made of 2N elements for thermometer decoding. However, it
is impractical to implement high-resolution DACs using 2N
elements because the number of elements grows exponentially as N increases. For high-resolution DACs, four different
ways of achieving monotonicity exist. They are using the
slope-type approach, the multilevel segmented DAC approach, calibration, and the interpolative oversampling technique. The first one is to use a linear voltage ramp and to
control the time to stop digitally so that accurate voltage proportional to the digital word can be obtained. Oversampling
interpolative DACs also achieve monotonicity by converting a
pulse-density modulated bitstream into analog waveform.
The slope-type DAC has a limited use in digital panel meters
and in other slow measurement uses, and it is not covered
here. However, the calibration and oversampling approaches
are covered in separate sections.
DAC ARCHITECTURES
Resistor-String DAC
A resistor string made of 2N identical resistors is a straightforward voltage divider. Switching the divided reference voltages to the output makes a DAC as shown in Fig. 4, which
uses a 3-bit binary tree decoder. Because it requires a good
switch, the stand-alone resistor-string DAC is easier to implement using metal-oxide-semiconductor (MOS) technologies.
Resistor strings are widely used as an integral part of the
flash ADC. One major drawback of using it as a stand-alone
DAC is that the DAC output resistance depends on the digital
input word and switch on-resistance. This nonuniform settling time constant problem can be alleviated either by adding
low-resistance parallel resistors or by compensating for MOS
switch overdrive voltages (2). The code-dependent settling has
no effect on the DAC performance when used as an ADC subblock.
Film resistors such as Tantalum, NiCr, or CrSiO used
in bipolar process exhibit very good matching of above the 10-

1
V
8 r

2
V
8 r

3
V
8 r

bit level with low voltage and temperature coefficients. However, in the MOS process, such high-quality resistors are not
available. Either diffusion or undoped poly resistors are used,
and the achievable matching accuracy is below 8-bit level
with one-order higher voltage and temperature coefficients
than those of film resistors in bipolar process. Although resistors are carefully laid out using large geometry, matching of
resistors in integrated circuits is still limited by the mobility
and resistor thickness variations. Differential resistor DACs
with large feature sizes are reported to exhibit higher matching accuracy at the 11 to 12 bit level.
A resistor-string DAC is inherently monotonic and exhibits
good DNL, but it suffers from poor INL. For higher INL, trimming or adjustment techniques are needed, but it is impractical to apply them to all 2N resistor elements. A very practical
method to improve the INL of the resistor-string DAC is to
use on-chip unity-gain buffers and to adjust voltages at intermediate taps of the resistor string using conventional trimming techniques. For this, the buffers require high open-loop
gain, low output resistance, large current driving capability,
and wide bandwidth for accurate and fast setting. The more
taps that are adjusted, the better integral linearity obtained.
An added benefit of this INL trimming method is the reduced
RC time constant due to the voltage sources applied to the
adjustment taps.
Binary-Weighted Current DAC
Although the resistor-string DAC is simple to make for a
small number of bits, the complexity grows exponentially as
the number of bits increases. Binary-ratioed elements are
simpler to use for a large number of bits. One of the simplest
DAC architectures using the binary-weighted current sources
is shown in Fig. 5 (3). It is the most popular stand-alone DAC
architecture in use today. In bipolar technology, transistors
and emitter resistors are ratioed with binary values as
shown. In MOS technology, only ratioed transistors are used
as in, for example, a video random-access-memory (RAM)
DAC that is made up of simple PMOS differential pairs with

4
V
8 r

5
V
8 r

6
V
8 r

7
V
8 r
Vr

1
b1 = 1

1
b2 = 0

521

1
b3 = 1
+
Out

Figure 4. Resistor-string DAC.

522

DIGITAL-TO-ANALOG CONVERSION

Out
+

bN

bN

bN1

bN1

b3

b2

b3

b1

b2

b1

Ir

Ir

Ir

Ir

Ir

2 N2

2 N1

2N

Vb
2 N1

2 N2
2R

2N2R

4R

2N1R

2 NR

Figure 5. Binary-weighted current DAC.

binary-weighted tail currents. Although MOS DACs exhibit 8

bit level matching using 10 to 20 m device size, bipolar
DACs are known to have above 10-level matching using thinfilm resistors. The current sources are switched on or off either by means of switching diodes or differential pairs as
shown. The output current summing is done by a wideband

transresistance amplifier, but in high-speed DACs, the output

current is used directly to drive a resistor load.
Although binary weighting reduces circuit complexity, the
number of transistors and resistors still grows exponentially
because a unit component is repeatedly used for good matching. This complexity problem is alleviated using another type
R
Io

Out

Id

bN

bN

bN 1

Ir

b1

Ir

N2

Ir

N1

2N

2R
R

b1

b2

2R

2R
R

b2

Ir

2R

b3

b3

Ir

Vr

bN 1

2R
R

Figure 6. R2R DAC.

2R
D

DIGITAL-TO-ANALOG CONVERSION

523

Reset

2 NC

Out

2 N 1C

bN

4C

bN

b3

2C

b3

b2

b2

b1

b1

Vr

of current-ratioed DAC known as R2R DAC shown in Fig. 6.

The R2R network consists of series resistors of value R and
shunt resistors of value 2R. Each shunt resistor 2R has a single-pole double-throw electronic switch that connects the resistor either to ground or to the output current summing
node. The operation of the R2R ladder network is based on
the binary division of current as it flows down the ladder. At
any junction of series resistor R, the resistance looking to the
right side is 2R. Therefore, the input resistance at any junction is R, and the current splits equally into two branches at
the junction because it sees equal resistances in both directions. The advantage of the R2R ladder method is that only
two values of resistors are used, greatly simplifying the task
of matching or trimming and temperature tracking. Also, for
high-speed applications, relatively low-valued resistance can
be used for even more savings in the chip area. The major
disadvantage of this architecture is the nonmonotonicity and
high nonlinearity due to poor matching in fabricated resistors. The R2R DAC is a multiplying DAC (MDAC) that has
an output proportional to the product of the reference voltage
and the digital input word.
Binary-Weighted Capacitor-Array DAC
Capacitors made of double-poly or poly-diffusion in the MOS
process are known to be very accurate passive components
comparable to film resistors in the bipolar process both in the
matching accuracy and voltage and temperature coefficients.
The binary-weighted capacitor-array DAC is shown in Fig. 7.
The DAC is made of a parallel capacitor array of N capacitors
with a common top plate (4). Unlike DACs using resistors and
currents, the capacitor-array DAC is based on a dynamic
charge redistribution principle. Therefore, it is not convenient
to use it in continuous-time applications, and for stand-alone
applications, a resettable feedback amplifier periodically
charging the top plate of the array and an output S/H or deglitcher are needed. The capacitor array is known to give a 10bit level matching for this use. The matching accuracy of the
capacitor in MOS technology depends on the geometry sizes
of the capacitor width and length and the dielectric thickness.
As a stand-alone DAC, the top plate of the DAC is precharged either to the offset of the feedback amplifier or to the

Figure 7. Binary-weighted
array DAC.

capacitor-

ground. One extra smallest C is not necessary for DAC as

shown in Fig. 7, but as a subblock of an ADC, it is needed to
make the total capacitance of 2NC. Because the top plate is
connected to the summing node, the top plate parasitic capacitance has a negligible effect on the DAC performance. The
capacitor-array DAC requires two-phase nonoverlapping
clocks for proper operation. Initially, all capacitors should be
charged to ground. After initialization, depending on the digital input, the bottom plates are connected either to Vr or to
ground. Then the output is the same as given by Eq. (1). Like
the R-2R DAC, the capacitor-array DAC can be used as an
MDAC.
Monotonic Segmented DACs
As discussed in the previous section, a DAC system is greatly
simplified using a binary-weighted DAC and binary input
word, but monotonicity is not guaranteed. For monotonicity,
the DAC needs to be thermometer-coded. Three examples of
thermometer-coded DACs are shown in Fig. 8 for resistor,
current, and capacitor-array DACs. Their operation is the
same except for the thermometer-coded input. Because each
segment is individually represented by a unit element, the
DAC output should increase as a new unit element is
switched in as the thermometer-code input increases by one.
This guarantees monotonicity, but the problem is an exponential increase in the complexity as the number of bits increases.
Applying a two-step conversion concept, a monotonic DAC
can be made using coarse and fine DACs. The fine DAC divides the next MSB segment into fine LSBs. Two examples of
the monotonic-segmented approach exist. One is a combination DAC, and the other is the most widely used next-segment
approach. Because it is difficult to achieve fine resolution using one DAC, both approaches use two separate DACs. The
R C combination DAC uses two different DAC types to
achieve two-level D/A conversion as shown in Fig. 9. The
MSB resistor-string DAC supplies the reference voltages to
the LSB capacitor-array DAC. When the top plate is initialized, all capacitor bottom plates are connected to the higher
voltage of the next segment of the resistor-string DAC. During the next clock phase, the bottom plates of capacitors are

524

DIGITAL-TO-ANALOG CONVERSION
R

R
Vr

2N 3

2N 2

2N 1

Thermometercoded N bits
+
Out

(a)

Out
+

1
I

2
I

3
I

2N 3

2N 2

2N 1
Thermometercoded N bits

(b)
Reset
2 NC

C
0

C
1

C
2

C
2N 3

C
2 N 2

Out
+

2N 1

Thermometercoded N bits

Figure 8. Thermometer-coded monotonic

DACs: (a) resistor, (b) current, and (c) capacitor arrays.

Vr

selectively connected to the lower voltage of the segment if

the digital bit is 1 but stay switched to the higher voltage if
0. This segmented DAC approach guarantees inherent monotonicity as far as the LSB DAC is monotonic within its resolution. However, INL is still poor because the MSB is set by
the resistor string. Fully differential implementation of this
architecture is known to benefit from the lack of the evenorder nonlinearity and to achieve high INL.
The same idea used in the R C combination DAC can be
implemented using two DACs of the same type. A segmented
DAC with total N bits is shown in Fig. 10. For monotonicity,
the MSB M bits are selected by a thermometer code, but one
of the MSB current sources corresponding to the next seg-

(c)

ment of the thermometer code is divided by a current divider

for the fine LSBs. As in the R C capacitor array, the fine
DAC divider should have a monotonicity of N M bits. Although monotonicity is guaranteed with modest matching requirement, it is still limited in INL due to the limited matching accuracy in the MSB. This segmented current DAC, with
and without trimming, is the most widely used DAC architecture.
DAC CONVERSION ACCURACY
DAC performance is directly affected by static linearity and
dynamic settling. The former is limited by the matching accu-

DIGITAL-TO-ANALOG CONVERSION

525

Reset

2 NC

Vr

Out

2 N 1C

4C

2C

b2

b2 b1

bN

bN

b3

b3

b1

Thermometer-coded
M MSBs

Figure 9. R C combination monotonic

DAC.

racy of passive or active components, and the latter is limited

by nonideal settling. When a DAC is used in the feedback
path of an ADC, the DAC linearity also affects the ADC linearity. In ADC applications, the number of bits per stage is
determined by how many bits are resolved in the DAC, depending on ADC architecture. However, the dynamic DAC
settling requirement in ADCs is less stringent than those
used as stand-alone devices. As explained in Fig. 2, standalone DACs should settle either infinitely fast or purely exponentially in making transitions from one level to another.
Because fast settling is not possible except for extremely low-

speed DACs, most DAC output should settle exponentially

with a well-defined time constant. Main sources for nonideal
dynamic settling errors are slew, glitch, and clock jitter.
Element Matching
Mismatch between elements occurs because of parasitic elements, uncertainties in the size of drawn shapes, and other
varying process parameters. There is typically about 0.2%
mismatch between two resistors of the same value drawn
with a length of 10 to 20 m. For similar reasons, capacitors

Out
+

Binary NM bits
2

2NM

2NM

NM bit current divider

Thermometer coded M bits

Ir

Ir

Ir

Ir

Ir

2M

2M

2M

2M

2M

Segments
to output

Next
segment

Segments
dumped

Figure 10. Two-level segmented monotonic DAC.

526

DIGITAL-TO-ANALOG CONVERSION
15

Number of occurrences

Time

10

(a)

Time

(b)
0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

Figure 12. DAC transient errors: (a) settling and (b) slew.

DNL (LSB)
20
18

Number of occurrences

16
14
12
10
8
6
4
2
0
0

0.5

1.5

2.5

one value to another is an exponential function. High-speed

DACs usually have a current output, and the output is usually terminated with a 50 or 75 low-impedance load. Therefore, the current output DAC can be designed so that the output may settle exponentially with a fixed time constant.
However, for voltage output DACs, either a transconductance
amplifier or a sample-and-hold amplifier is used as a buffer
amplifier. In general, all amplifiers slew to a certain degree if
a large transient signal is suddenly applied to the input. Figure 12 shows two waveforms with transient errors resulting
from exponential settling and slew limiting.
In the exponential-settling case, the transient error defined by the shaded area is proportional to the height of the
jump. This implies that any single time-constant settling does
not produce any nonlinearity error. In reality, amplifiers settle with multiple poles although one of them is dominant. To
see this effect, consider a two-pole settling case. The transient
error can be calculated as follows:

INL (LSB)


Transient error = h

Figure 11. Simulated DNL and INL of a 12-bit DAC with 0.1% component matching.

Slew and Settling

The output of a DAC is a sampled step waveform held constant during a word clock period. The ideal transition from


(7)

where 1 and 2 are the two time constants. As in the single

time-constant case, the transient error is a linear function of

75
70
SNDR (dB)

and transistors also show mismatch due to process variations.

The effect of component mismatch appears as static nonlinearity. Because of statistical randomness of the process variation, the mismatch effect on the DAC performance can be better understood using statistical Monte Carlo analysis. Figure
11 show the distribution characteristics of DNL and INL of a
12-bit segmented DAC with 1% random mismatch in current
sources and the next-segment divider. The 12 bits are partitioned into four thermometer-coded MSBs and binaryweighted 8-bit LSBs. The x-axes for both graphs are in units
of LSB, whereas the y-axes represent the total number of occurrences out of 100 samples. The segmented DAC architecture guarantees monotonicity regardless of the amount of
mismatch in the elements. There exist many samples with
INL greater than 1 LSB, but no DNL exceeds 1 LSB.

12
22
+
1 2
2 1

65
60
55
50
45
0.5

1.5
2
Normalized slew rate

2.5

Figure 13. SNDR degradation of a 12-bit DAC due to limited slew

rate.

DIGITAL-TO-ANALOG CONVERSION

527

0.6

Magnitude (V)

0.4
0.2
0
0.2
0.4

500

1000

1500

2000

2500

3000

3500

4000

(a)
0.1

Magnitude (V)

0.08
0.06
0.04
0.02
0

10

20

30

40

50

60

70

80

90

100

(b)

SNR = 75.44 dB SDR = 80.17 dB SNDR = 74.18 dB

0

Magnitude (dB)

-20
-40
-60
-80
100
120
0

100

200

300

400

500

600

700

(c)
Figure 14. 12 bit DAC output with two poles: (a) time waveform, (b) its detail, and (c) its FFT.

h, and the preceding result implies that the two-pole settling

generates only linear errors and will not affect the DAC linearity.
However, in the latter slew-limited case, the area is proportional to h2. From the simple slewing distortion model, the
worst case harmonic distortion (HD) when generating a sinusoidal signal with a magnitude V0 with a limited slew rate of
S is

Tc
2 V0 ,
HDk = 8
k(k2 4) STc
sin2

k = 1, 3, 5, 7, . . .

(8)

where Tc is the clock period (5). For a given distortion level,

the minimum slew rate is given. Any sinusoidal waveform
has a maximum slew rate of 0V0 at the zero-crossing point.
Therefore, if a DAC has a slew rate much higher than this
maximum slew rate, the DAC output will exhibit negligible
slew-limited distortion. The summary plot of the SNDR vs.
slew rate of a 12 bit DAC example is shown in Fig. 13, where
the x-axis unit is normalized to the maximum slew rate of the
sinusoidal waveform. As expected from Eq. (8), the SNDR is
proportional to the slew rate. Figures 14 and 15 show the
simulated output spectrums of a 12-bit DAC for two cases.
One is the two-pole settling case, and the other is the slew-

528

DIGITAL-TO-ANALOG CONVERSION

0.6

Magnitude (V)

0.4
0.2
0
0.2
0.4

500

1000

1500

2000

2500

3000

3500

4000

(a)
0.1

Magnitude (V)

0.08
0.06
0.04
0.02
0

10

20

30

40

50

60

70

80

90

100

(b)

SNR = 71.55 dB SDR = 56.55 dB SNDR = 56.42 dB

0

Magnitude (dB)

20
40
60
80
100
120
0

100

200

300

400

500

600

700

(c)
Figure 15. 12 bit DAC output with slew limit: (a) time waveform, (b) its detail, and (c) its FFT.

limited case. As predicted in Fig. 13, the SNDR of the former

case stays high at 74 dB, whereas the latter case suffers from
lower SNDR of 56 dB. The harmonics of the input increase
drastically in the slew-limited case.
One more nonideal factor that contributes to the settling
of a DAC is the parasitic capacitance. The parasitic capacitance of the current sources shifts the poles to display a codedependent time constant. As a result, the dominant pole of
a DAC varies according to input digital words. Because the
parasitic capacitances are additive, the higher output levels

where more current sources are switched on can exhibit a

slower settling time than that of lower output levels.
Glitch and Clock Jitter
Ideally, all bits of the digital input word should switch at the
same time so that any change in the digital word can be reflected in the analog output waveform simultaneously. However, even with the use of an input data latch to synchronize
the digital word, different data paths cause a slight variation

DIGITAL-TO-ANALOG CONVERSION
MSB switches on early
MSB switches off late

Time

529

Even if the output waveform is correctly generated from the

input word, the timing error will raise the noise floor of the
DAC. If the jitter has a Gaussian distribution with a rootmean-square jitter of t, the worst-case SNR resulting from
this random word clock is
2 f t
SNR = 20 log
M

MSB switches on late

(9)

where f is the signal frequency and M is the oversampling

ratio. The timing jitter error is more critical in reproducing
high-frequency components. In other words, to make an N-bit
DAC, an upper limit for the tolerable word clock jitter is

MSB switches off early

(a)

Jitter <

1
2B2N

2M
3

(10)

Time

Clock jitter
(b)

The simulated spectrum of a 12 bit DAC with 5% clock jitter

is shown in Fig. 18. The effect is about the same as the glitch
case. Figure 19 shows the SNDR of the same 12 bit DAC as
functions of glitch and clock jitter percentages of the sampling
period. It clearly demonstrates that the SNDR decreases as
both glitch and clock jitter effects become more significant.

Figure 16. Effects of (a) MSB glitch and (b) clock jitter.

HIGH-RESOLUTION TECHNIQUES
in the switching time of the digital bits. This phenomenon
causes a glitch in the output and affects the performance of
the DAC. For example, at the major code transition in a binary-weighted DAC, the digital word changes from 011 . . .
1 to 100 . . . 0. If all bits change simultaneously, then the
output should increase exponentially by one LSB step. However, due to the slight time differences between switching of
the digital bits, there may be an instance where the MSB bit
switches on before the rest of the digital bits turn off, thus
creating the appearance of the digital word 111 . . . 1 even
momentarily. This will cause a positive spike in the output as
shown in Fig. 16(a). Similarly, there may be an instance when
the MSB switches on after the remaining digital bits turn off,
thus creating the appearance of digital word 000 . . . 0. This
will cause a downward trough in the output as shown. The
same glitch occurs when the MSB switches off.
Obviously this situation is the worst case. A more realistic
glitch spike and its effect on the output spectrum is shown in
Fig. 17 where 5% glitch is simulated for the same 12-bit DAC
with a sinusoidal input. The frequency spectrum of the output
with glitches exhibits an elevated noise floor. Although a few
techniques such as segmented antisymmetric switching have
been proposed to alleviate the glitch problem, an easier solution is to employ a sample-and-hold amplifier at the DAC output as a deglitcher. The basic idea of deglitching is to keep
the DAC in the hold mode until all the switching transients
have settled. If the deglitcher is faster than the DAC, the slew
rate limitation may improve. However, if the slew rate of the
deglitcher is of the same order as the DAC, the slew distortion
will still exist, now as an artifact of the deglitcher.
Another major source of conversion error is the nonideal
clock jitter. The glitch results from the switching time difference of digital bits while the clock jitter results from the randomness of the clock edge itself. The clock jitter generates
errors as explained in Fig. 16(b). The right signal at the
wrong time is the same as the wrong signal at the right time.

The current trend of high resolution at high frequencies has

stimulated many innovative DAC developments. Although
there may be numerous approaches in making high-resolution DACs, only two distinctive approaches need special mentioning. They are the monotonic segmented approach and the
oversampling interpolative approach. The former is exclusively used for high-speed DACs, but the oversampling approach is dominant at low-speed applications such as for instrumentations, digital audio, and digital communication
channels. For high-resolution DACs, bipolar and bipolarCMOS (BiCMOS) DACs are superior to bulk complementary
MOS (CMOS) counterparts in speed. In nonoversampling
DACs, linearity of more than 12 b requires resolution-enhancing methods such as trimming, dynamic matching, and electronic calibration.
Trimming
Component matching is limited by many variations in physical dimensions and process parameters. The effect of random
size variation is reduced using physically large dimension.
Careful layout using common centroid or geometric averaging
can also reduce the process gradient effect. However, it is possible to further improve component matching by trimming on
the wafer in a post-fabrication process. Resistor value can
be either laser trimmed (6), Zener-zapped (7), or electronically controlled by switches using programmable read-onlymemory (PROM) and erasable PROM (EPROM). The lasertrimming and the Zener-zapping processes are nonreversible.
The long-term stability of trimmed resistors is a major concern, although electronical trimming using EPROM can be repeated.
The laser-trimming method involves using a focused laser
beam to melt away part of the resistors to change their values. The precision required in the process and the irreversibility of the process make this option expensive. Because laser

530

DIGITAL-TO-ANALOG CONVERSION

0.6

Magnitude (V)

0.4
0.2
0
0.2
0.4

500

1000

1500

2000

2500

3000

3500

4000

(a)

Magnitude (V)

0.14
0.12
0.1
0.08
0.06
100

110

120

130

140

150

160

170

180

190

200

(b)

SNR = 56.09 dB SDR = 56.33 dB SNDR = 53.20 dB

0

Magnitude (dB)

20
40
60
80

100
120
0

100

200

300

400

500

600

700

(c)
Figure 17. 12 bit DAC output with 5% glitch: (a) time waveform, (b) its details, and (c) its FFT.

trimming is continuous, very accurate measurement tools are

needed to detect low levels of mismatch. The Zener-zapping
method creates a resistor of desired value by inserting a series of small incremental resistors and by selectively bypassing them. Zener diodes connected in parallel with resistors are melted with short current pulses over hundreds of
milliamperes. Fusible aluminum links are also used in this
discrete trimming technique. Like laser trimming, the Zenerzapping method is also irreversible and requires precision
equipment to measure matching errors. Furthermore, the stability of the trimmed values over a long period of time is still

in question. The new trend is toward a more intelligent solution that involves the ability to recalibrate on demand by
moving the error measurement process on-chip.
Dynamic Matching
The idea of dynamic matching is to improve the matching accuracy by time-averaging two component values (8). Figure
20 explains how the dynamic-matching technique can be applied to current dividers. Assume that two current sources are
mismatched by . By commuting the two currents I1 and I2 at

DIGITAL-TO-ANALOG CONVERSION

531

0.6

Magnitude (V)

0.4
0.2
0
0.2
0.4

500

1000

1500

2000

2500

3000

3500

4000

(a)
0.1

Magnitude (V)

0.08
0.06
0.04
0.02
0

10

20

30

40

50

60

70

80

90

100

(b)

SNR = 57.11 dB SDR = 60.05 dB SNDR = 55.33 dB

0

Magnitude (dB)

20
40
60
80
100
120
0

100

200

300

400

500

600

700

(c)
Figure 18. 12 bit DAC output with 5% jitter: (q) time waveform, (b) its detail, and (c) its FFT.

high speed to two new output ports with a 50% duty, the mismatch error /2 will be modulated by the high clock frequency. If these are lowpass filtered, the average current I
will come out of the two terminals. This dynamic matching
can be generalized for a large number of matching components using the butterfly-type randomizer as shown in Fig. 21
for the four-element matching case. The switches are controlled so that the four outputs can be the average of the four
currents. In this case, the modulating frequency is half of the
clock frequency. For matching a large number of elements,
this fixed pattern noise moves to lower frequencies. To reduce

this pattern noise, the clock frequency should be raised or the

lowpass filters should have a sharper cutoff slope. A more sophisticated randomizer selects the switching path randomly
with an equal probability to each output terminal using a
pseudorandom number generator. This general randomizer
can distribute mismatch errors over a wider frequency range.
At least an order of magnitude improvement is achieved using
the dynamic matching element method.
An alternative concept to dynamic matching is to replicate
current or voltage unit element. The idea is to copy one master voltage or current repeatedly on voltage or current sam-

532

DIGITAL-TO-ANALOG CONVERSION

80

1,2,3,4

LPF

1+2+3+4

LPF

1+2+3+4

LPF

1+2+3+4

LPF

1+2+3+4

SNDR (dB)

75
70

2,3,4,1

65

3,4,1,2

60
55

45

4,1,2,3

50

Figure 21. Butterfly-type randomizer.

10

Glitch (%)
(a)

is limited to N bits, it is equivalent to having passive components matching of N bits. Note that voltage and current sampling schemes alone are not sufficient enough to make a highresolution DAC. This approach is generally limited to creating
MSBs for segmented DACs or for multistep ADCs. The
amount of time required to copy one master source repeatedly
but accurately makes it impractical for high-speed DAC applications.

80
75
SNDR (dB)

70
65
60
55
50
45

Electronic Calibration
0

10

Jitter (%)
(b)
Figure 19. SNDR vs. (a) glitch and (b) clock jitter.

plers so that the sampled ones can be used to ratio elements.

The voltage is usually sampled on the holding capacitor of
sample-and-hold amplifier, and the current is sampled on the
gate of the MOS transistor (9). This sampling method is ultimately limited by sampling errors. If the sampling accuracy
I

LPF
I1

I+

I2

I1

1
I2
I
2
I+
2

I
2

2
I+
2

I
2

Figure 20. Dynamic matching of two currents and modulated two

currents.

Calibration is another alternative to the trimming and dynamic matching methods. It has become an intelligent electronic solution preferred to the factory trimming process. The
electronic calibration predistorts the DAC transfer characteristic so that the DAC linearity can be improved. DAC nonlinearity errors are measured and stored in memory. Later during normal operation, these errors are subtracted from the
DAC output. Error subtraction can be done either in the analog domain or in the digital domain. Calibration methods differ from one another in the measurement of nonlinearity errors. The most straightforward method is a direct codemapping technique. All DAC code errors must be measured
and stored in ROM. This method is limited because it requires precision measurements and large digital memory. A
more robust way of calibrating a DAC electronically is selfcalibration. This incorporates all the calibration mechanisms
and hardware on the DAC as a built-in function so that users
can recalibrate whenever calibration is necessary.
Self-calibration is based on the assumption that the segmented DAC linearity is limited by the MSB matching so that
only errors of the MSBs can be measured, stored in memory,
and recalled during normal operation. There are two different
methods of measuring the MSB errors. In one method, individual binary bit errors, usually appearing as component mismatch errors, are measured digitally (10). The total error,
which is called a code error, is computed from individual-bit
errors depending on the digital code during normal conversion. The other method measures segment errors and accumulates them to obtain code errors. Because code errors are
stored in memory, there is no need for the digital code-error
computation during normal operation (11). The former requires less digital memory, whereas the latter requires fewer
digital computations.

DIGITAL-TO-ANALOG CONVERSION

set to the average of the two tap values obtained with the two
measurements. The same principle can be applied to measure
the current difference as shown in Fig. 23. The calibration
DAC measures I1 first using the up/down converter and
moves on to measure I2. The difference between the two measurements is the current mismatch error.

V1

R1
Calibration
DAC

Up/
down

V2

R2

Figure 22. Resistor ratio calibration scheme.

Two examples of DAC ratio measurements are conceptually explained in Figs. 22 and 23. In the resistor ratio measurement of Fig. 22, the voltage across the two resistors is
sampled on the capacitors, and the comparator is nulled. During the next cycle, the capacitor bottom plates are connected
to the center point to sense the difference of V1 and V2. The
comparator decision will move the center tap connected to the
fine calibration DAC. This capacitive sensing is limited by the
capacitor-matching accuracy between C1 and C2. To average
out this capacitor mismatch error, the same measurement can
be repeated with C1 and C2 swapped. The final center tap is

Calibration DAC

Up/
down

I1

533

I2

INTERPOLATIVE OVERSAMPLING TECHNIQUE

All DACs have a discrete output level for every digital input
word applied to their input. Although digital numbers can
grow easily, generating a large number of distinct analog output levels is a difficult task. The oversampling interpolative
DAC achieves fine resolution by covering the signal range
with a few widely spaced levels and interpolating values between them. Rapid oscillation between coarse output levels is
controlled so that the average output may represent the applied digital word with reduced noise in the signal band (12).
This process is a tradeoff between speed and resolution. The
oversampling idea is to achieve high resolution with less accurate component matching and has been most widely used to
make DACs that need high resolution at low frequencies.
The interpolative oversampling DAC architecture is shown
in Fig. 24. A digital interpolator raises the word rate to a
frequency well above the Nyquist rate for oversampling. The
interpolated data stream is applied to a digital truncator to
shorten the word length. This data stream of shorter words,
usually a one-bit stream, is converted into analog waveform
at the oversampling rate. This oversampled output has a low
truncation error in the signal band, and the out-of-band truncation noise is filtered out using analog low-pass filter (LPF).
Figure 25 illustrates this oversampling D/A conversion
process.
The sampling rate upconversion for this is usually done
using two upsampling digital filters. The first filter, usually a
two to four times oversampling FIR filter, shapes the signal
band for sampling rate upconversion and equalizes the passband droop resulting from the (sin x)/x filter for higher-rate
oversampling. The truncator is made of a feedback system
called a delta-sigma modulator that pushes the truncation error out to high frequencies while passing the signal band unattenuated. Using a linearized model, the z-domain transfer
function of the general digital truncator shown in Fig. 24 is
V0 (z) =

H(z)
1
V (z) +
E(z)
1 + H(z) i
1 + H(z)

where E(z) is the truncation error. The loop filter H(z) is chosen so that the truncation error may be high-pass filtered
while the input signal is low-pass filtered. The order of noise
shaping depends on the order of H(z).
The oversampling effect begins to appear when the
oversampling ratio is larger than 2. The noise of the Nth-order loop is suppressed by 6N 3 dB for every doubling of the
sampling rate, providing N 0.5 extra bits of resolution.
Therefore, the dynamic range achievable by oversampling is
Dynamic range (6N + 3)(log2 M 1) dB

Figure 23. Current ratio calibration scheme.

(11)

(12)

where M is the oversampling ratio between the sampling frequency and twice the signal bandwidth. For example, a sec-

534

DIGITAL-TO-ANALOG CONVERSION

N << M
usually N = 1
M
Digital
in

Interpolation
filter, K

fs

M
fs

Truncation
loop

Analog
LPF

DAC
fs

Analog
out

M+1

M+1
H(z)

Digital
truncator

Figure 24. Interpolative oversampling DAC system.

ond-order loop with 256 times oversampling gives a dynamic

range of over 105 dB, but the same dynamic range can be
obtained using a third-order loop with only 64 times oversampling.
Digital Truncator
A noise-shaping delta-sigma modulator for digital truncation
can be built in many different ways. The simplest three examples are shown in Fig. 26. The first-order loop shown in Fig.
26(a) outputs only N MSBs out of M 1 bits from the integrator output. The remaining truncation error of M N 1
is fed back to the digital integrator along with the input.
Therefore, the output of the first-order modulator becomes
Y (z) = z1 X (z) (1 z1 )E(z)

(13)

This implies that the input appears at the output just delayed, but the truncation error in the integrator loop is highpass filtered with one zero at dc.
In general, first-order designs tend to produce correlated
idling patterns and require a high oversampling ratio to suppress inband truncation noise effectively. By increasing the
order of the error transfer function, the inband truncation error can be suppressed with steeper-slope high-pass filter. The
standard second-order modulator can be implemented as
shown in Fig. 26(b) using a double integration loop. The output of the second-order modulator becomes
Y (z) = z

X (z) + (1 z

1 2

) E(z)

(14)

This second-order modulator is vastly superior to the firstorder one both in terms of the oversampling ratio and the
improved randomness of the idling patterns. However, even
the second-order loop is not entirely free of correlated fixed
patterns in the presence of small constant inputs. If loop order is higher than 3, fixed pattern noise does not exist. Highorder modulators can be implemented using the same method
as in the standard filter design (13).

Another variation of the high-order modulator is the cascading method (14). Rather than using error feedback, modulators can be cascaded to reduce the truncation noise in the
same way. Figure 26(c) shows a second-order cascade modulator example. The truncation error E1 of the first modulator is
modulated again using another first-order modulator. If the
truncation error of the second modulator is E2, the outputs of
the two modulators Y1 and Y2 become
Y1 (z) = z1 X (z) (1 z1 )E1 (z)

(15)

Y2 (z) = z1 E1 (z) (1 z1 )E2 (z)

(16)

respectively. The two outputs are added after they are

multiplied by z1 and 1 z1, respectively. Then the final output becomes
Y (z) = z2 X (z) (1 z1 )2 E2 (z)

(17)

This is the same second-order modulator output given by

Eq. (14). The problem with the cascading approach is that
the output word is always longer than 2, even though two
cascaded modulators have one-bit output (N1 N2 1).
That is, the higher-order noise shaping is possible with
cascading, but error occurs in the output D/A conversion.
The multibit output DAC requires the same accuracy as
conventional DACs.
One-Bit Switched-Capacitor DAC/Filter
Digital processing for modulation and filtering is not limited
in accuracy. However, all oversampling DACs are followed by
an analog DAC and an analog low-pass filter, and DAC performance depends entirely on the rear-end analog components. The idea of oversampling to alleviate the componentmatching requirement for high resolution does not apply to
multibit DACs. Therefore, most oversampling DACs are designed with one-bit output. It is true that a continuous-time
low-pass filter can convert the one-bit digital bitstream into
an analog waveform, but it is difficult to construct an ideal

Frequency
(a)

Frequency
fs

fs
K
(b)

Frequency
fs
(c)

Frequency
fs
(d)

Frequency
fs
(e)

Frequency
fs
(f)

Frequency
fs
(g)

Frequency
(h)

Frequency
(i)

Figure 25. Oversampling D/A conversion: (a) input spectrum, (b) sampled spectrum, (c) interpolation filter, (d) interpolated spectrum, (e) noise-shaped spectrum, (f) sample-and-hold frequency
response, (g) sample-and-held spectrum, (h) low-pass filter, and (i) DAC output.

535

536

DIGITAL-TO-ANALOG CONVERSION

M+1

M+1

N
Y

z1
+
E

MN+1
(a)
M

z1

z1

M+2

M+4

N
(b)
M
X

N1

Y1

z1

z1

Y
+

M N1 + 1

E1
+

N2
z1

Y2

1 z1

+
E2
M N1 + N2 + 2
(c)
Figure 26. Digital truncators: (a) first-order loop, (b) second-order loop, and (c) cascaded architecture.

undistorted digital waveform without clock jitter. If the bitstream is converted into a charge packet, a high linearity is
guaranteed as a result of the uniformity of the charge packets. For this reason, most high-resolution oversampling DACs
are implemented using a switched-capacitor DAC/filter combination as the rear-end.
A one-bit switched-capacitor DAC with one-pole roll-off can
be built as shown in Fig. 27(a) using two-phase nonoverlapping clocks 1 and 2. The digital signal is fed on the bottom
plate of C2 by sampling Vr or Vr depending on the digital bit.
The end result is that a constant amount of charge C2Vr is
either added or subtracted from the integrator formed by C1
and the operational amplifier. Because the digital signal is
converted into a charge packet, the shape of the charge packet
is not important as far as the incremental or decremental
charge amount is constant. The use of the prime clocks is to
make switch feedthrough errors constant by turning off the
top plate switches slightly earlier than the bottom plate
switches. The bandwidth of the filter is set to f sC2 /(C1 C2).
Operational amplifiers for this application should have high
dc gain and fast slew rate. Operational amplifiers start to
slew when an input voltage larger than its linear range is
applied. When the charge packet of the sampled reference
voltage is dumped onto the input summing node, it causes a

sudden voltage step at the summing node. This one-bit DAC/

filter configuration helps to reduce this voltage step because
charge is directly dumped on the integrating capacitor.
The shaped noise is out of band and does not affect the
inband performance directly. More precise filtering of the
shaped noise can be done with higher-order switched-capacitor filters combined with the one-bit DAC. One second-order
filter combined with a one-bit DAC is shown in Fig. 27(b). It
is a second-order switched-capacitor biquad implementing the
low-pass function. In oversampling applications, even a onepole RC filter substantially attenuates high-frequency components around f s, but higher-order continuous-time smoothing
filters can be used. Analog filters for this application are often
implemented using a cascade of SallenKey filters made of
emitter follower unity-gain buffers.

DAC APPLICATIONS
DAC architectures are mainly determined by the operating
speed. In general, D/A conversion rate is inversely proportional to DAC resolution. DAC applications can range from 20
bits at a few tens of hertz to 6 bits at a couple gigahertz. The
most well-known applications are for 8 bit telephone voice,

DIGITAL-TO-ANALOG CONVERSION

537

VREF

C2

C1

Out
+

(a)

C2

C1

2
1

Out
1

VREF
2

(b)

16 bit digital audio, 8 bit digital video, 8 to 12 bit waveform

generation and high-resolution graphics, 12 bit communication channel, and 8 to 14 bit wireless radio and cell site. As
discussed, two architectures stand out. They are oversampling DAC at low frequencies and segmented DAC at high
frequencies. The former trades resolution for speed, but the
latter needs resolution-enhancing techniques for high linearity because there is no room for speed to trade with resolution.
The 8 bit pulse-coded modulation (PCM) within a frequency band of 300 Hz to 3.4 kHz has been a standard since
the 1970s for the telephone voice channel. One thing to note
in the voiceband quantization is the use of the so-called -law
coding scheme so that low-level signals can be quantized more
finely than high-level signals. Because low-level resolution
approaches that of a 14 bit system, it is possible to maintain
constant SNR over a wide range of signal magnitude. Most
voiceband DACs have been made using capacitor-array DACs
and integrated in voiceband coder/decoder (CODEC) systems
using MOS processes.
No field places a higher premium on DAC performance
than digital audio. New multimedia applications have opened
up new audio DAC applications as set forth in the audio CODEC standard AC97 (1). The new standard covers bit rates
of 8, 11.025, 16, 22.05, 32, 44.1, and 48 kHz. Even the 16 bit

Figure 27. Time

switched-capacitor
DACs: (a) first order and (b) second order.

44.1 kHz digital audio standard set for CD in the 1980s is

now seriously challenged by many improved high-definition
CD (HDCD) standards. The new DVD (Digital Versatile Disc)
format has the capacity of high-resolution uncompressed 20
bit audio at a 98 kHz sampling rate. Video or movie systems
also rely heavily on digital sound. Digital surround sound systems such as Dolby AC-3, DTS (Digital Theater System), and
5.1 digital surround systems have already become household
names. R-2R or segmented current DACs with laser-trimmed
film resistors are used to make 18 to 20 bit extremely linear
DACs for digital audio. However, the oversampling technique
can meet the demanding performance requirements of digital
audio without trimming.
In the 1990s, digital video is leading the multimedia revolution in modern digital communications. Compressed digital
video images are now accessible over computer networks from
anywhere and at anytime. A 2 h MPEG-encoded (Motion Picture Experts Group) compressed video can now be stored on
a 5 inch (12.7 cm) optical disc along with digital surround
sound channels. Digital satellite networks provide quality
digital video, and new HDTV (High-Definition TV) will eventually replace existing analog TV. All these are now possible
through digitization of video signals. Standard NTSC video
luminance signal covers about a 4 MHz bandwidth with color
subcarrier at 3.58 MHz. The standard video luminance signal

538

DIODES

is sampled with 8 bit resolution at 13.5 MHz, whereas color

signals are sampled at 6.75 MHz or lower depending on the
video formats. As more digital signal processing is used, the
trend is to use 10 bits. In the new HDTV, the sampling rate
is about five times higher at above 75 MHz.
DACs have become indispensable in the digital era. Digitization started from voiceband in the 1970s, digital audio in
the 1980s, and digital video in the 1990s is about to move into
intermediate frequency (IF) and RF for wireless telecommunications systems. Digitizing the IF in digital wireless systems
makes it possible to perform data modulation and demodulation digitally in software. Low-spurious ADC and DAC are
key components that will enable this software programmable
radio environment. The architecture that can deliver both
high-resolution and high-speed performance is limited to the
segmented DAC. The current art estimated by recent works
is projected to be 14 to 16 bits at low hundreds of megahertz
range depending on process with trimming (15,16). However,
the DAC performance envelope will be pushed out further as
new architectures and device processes evolve.

BIBLIOGRAPHY
1. Analog Devices, Creative Labs, Intel, National Semiconductors,
Yamaha, Audio Codel 97, Rev. 1.03, Sept. 1996.
2. M. J. M. Pelgrom and M. Roorda, An algorithmic 15-Bit CMOS
digital-to-analog converter. IEEE J. Solid-State Circuits, SC-23:
14021405, 1988.
3. J. J. Pastoriza, K. Krabbe, and A. A. Molinari, A High-Performance Monolithic D/A Converter Circuit. IEEE Int. Solid-State
Circuits Conf., Feb. 1970.
4. J. M. McCreary and P. R. Gray, All-MOS charge redistribution
analog-to-digital conversion techniquesPart I. IEEE J. SolidState-Circuits, SC-10: 371379, 1975.
5. D. M. Freeman, Slewing distortion in digital-to-analog conversion. J. Audio Eng. Soc., 25: 178183, 1977.
6. R. B. Craven, An Integrated Circuit 12-Bit D/A Converter. Dig.
IEEE Int. Solid-State Circuits Conf., Feb. 1975.
7. D. T. Comer, A monolithic 12-bit DAC. IEEE Trans. Circuits Syst.,
CAS-25: 504509, 1978.
8. R. J. Van de Plassche, Dynamic element matching for high accuracy monolithic D/A converters. IEEE J. Solid-State Circuits, SC11: 795800, 1976.
9. D. W. J. Groeneveld et al., A self-calibration technique for monolithic high-resolution D/A converters. IEEE J. Solid-State Circuits, SC-24: 15171522, 1989.
10. H. S. Lee, D. A. Hodges, and P. R. Gray, A self-calibrating 15bit CMOS A/D converter. IEEE J. Solid-State Circuits, SC-19:
813819, 1984.
11. S. H. Lee and B. S. Song, Digital-domain calibration of multistep
analog-to-digital converters. IEEE J. Solid-State Circuits, SC-27:
16791688, 1992.
12. J. C. Candy and A. H. Huynh, Double interpolation for digital-toanalog conversion. IEEE Trans. Commun., 34: 7781, 1986.
13. W. L. Lee and C. G. Sodini, A Topology for Higher-Order Interpolative Coder. Proc. Int. Symp. Circuits Syst., May 1987.
14. T. Hayashi et al., A Multistage Delta-Sigma Modulator without
Double Integration Loop. IEEE Int. Solid-State Circuits Conf.,
Feb. 1986.
15. D. Mercer, A 16-b D/A Converter with Increased Spurious Free
Dynamic Range, IEEE J. Solid-State Circuits, SC-29: 1180
1185, 1994.

16. B. J. Tesch and J. C. Garcia, A low-glitch 14-bit 100MHz D/A

converter. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 1996.

BANG-SUP SONG
University of Illinois

DIGITAL VIDEO. See IMAGE SEQUENCES; MULTIMEDIA

VIDEO.

DIGITAL WIRELESS COMMUNICATIONS. See CELLULAR RADIO.

DIODE LASERS, MANUFACTURING. See LASER DESKTOP MACHINING.

DIODE, RESONANT TUNNELING. See RESONANT TUNNELING DIODES.

570

DIODE-TRANSISTOR LOGIC

and is thus not large enough to turn on DL and QO. Hence,

QO is cutoff and IRC IC 0. The output voltage can be found
by following dashed path 2 to obtain
VOUT = VCC IRC RC = VCC = VOH
Input Low Voltage (VIL)

DIODE-TRANSISTOR LOGIC
The first transistor logic family was developed in the 1950s and
was named resistor transistor [bipolar junction transistor
(BJT)] logic (RTL). To improve upon RTL circuits of the past,
diode-transistor logic (DTL), was introduced based upon the design of preexisting circuits. As the name implies, circuits of the
DTL logic family utilize diodes and transistors in their design.
In 1964, a version of DTL was introduced in integrated circuit (IC) form that became the standard digital IC family of
that time. This line of DTL, marketed as the 930 series, is easy
to fabricate in IC form and was the standard digital IC for approximately 10 years after introduction in 1964. This family
was still in use in some military applications in the late 1980s.
In this article we describe the evolution of the DTL logic
family, describing in detail the operation and design of these
circuits. Several numerical examples are also included as an
aid to understanding. We begin with the basic inverter gate.

Increasing VIN to the point where QO just turns on is achieved

when
VIN = VBE (FA) = VIL
where VBE(FA) is the BE base-emitter forward active turnon voltage. The corresponding increase in VX is

VX = VIN + VD, I (ON) = VBE (FA) + VD (ON)

= VBE, O (FA) + VD, L (ON)
where VD(ON) is the diode turn-on voltage and both DL and
QO turn on (conduct) when QO is forward active. With QO forward active, VOUT VCC ICRC and begins to reduce from
VCC for increases in VIN as IC,O increases.
Output Low Voltage (VOL)
Increasing VIN (and therefore VX) further will eventually
drive QO into saturation, giving

BASIC DTL INVERTER

Figure 1 shows the basic DTL inverter and its voltage transfer characteristic. It should be mentioned that the primary
reason that DTL logic circuits were introduced was to overcome the low fan-out of RTL for VOUT VOH. From Fig. 1, note
that when VOH is the input voltage to a load gate, the input
diode DI is reverse-biased and sinks only the reverse saturation current, and this current is extremely small.

VOUT = VCE, O (SAT) = VOL

where VCE,O(SAT) is the BE saturation voltage.
Input High Voltage (VIH)

For VIN low, the input diode DI is forward-biased as can be

seen by following dashed path 1 in Fig. 1. The voltage between the diodes is given by

Transistor QO enters saturation at VIN VBE(SAT) VIH

where VBE(SAT) is the BE saturation voltage, which is
slightly larger than VBE(FA).
Since VX cannot increase any further, subsequent increasing of VIN opens D1. Resistor RB must be chosen small enough
such that QO is in saturation when VX increases to

VX = VIN + VD, I (ON) < VD, L (ON) + VBE, O (FA)

VX = VBE (SAT) + VD (ON)

Output High Voltage (VOH)

VOUT(V)

VCC
1

VOH = VCC
2

RC
RB

VIN

DI

VOUT

DL

QO

VOL = VCE (SAT)

VIH = 0.8

VIN(V)

VIL = 0.7
(a)

(b)

Figure 1. Basic DTL inverter. (a) Circuit. (b) Voltage transfer characteristic.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

DIODE-TRANSISTOR LOGIC

ditional-level shifting diode also avoids the problem of QO

turning on before VIN reaches VBE(FA). The addition of DL2 increases VIL and VIH by VD(ON) 0.7 V.

VCC

RC

Discharge Path

RB
VOUT
DIA

The inclusion of RD and VEE at the base of QO provides a

path for discharge of the stored base charge of QO, when
switched from saturation to cutoff. This decreases the transition period and propagation delay time. The need for an additional source voltage (and corresponding pin on the IC) can
be avoided by simply taking VEE to be ground and using a
smaller-valued resistance for RD.

DL

VINA

QO
DIB

VINB

Diode AND gate

571

BJT inverter

Figure 2. Basic DTL NAND gate.

TRANSISTOR MODIFIED DTL

The logical NOT function is verified by examination of the
resulting voltage transfer characteristic of Fig. 1(b). Since
VIL and VIH differ only by VBE(SAT) VBE(FA), the transition
width between output high and low logic states is quite
abrupt. The actual width can be obtained experimentally or
by circuit simulation with results quite close to these.
Basic DTL NAND Gate
Notice that addition of another input diode, as shown in Fig.
2, resembles a diode AND gate connected to a BJT inverter.
Indeed, the NAND function is inherently provided by the DTL
logic family by adding diodes in parallel at the input pointing
outward (OUT).
MODIFIED DTL
Additional Level-Shifting
Figure 3 shows a modified DTL inverter with an additional
level-shifting diode DL2 added in series with DL to shift the
logic level high-to-low transition by VD(ON) on the VTC input
voltage axis. This improves the low noise margin NML, while
still exhibiting an acceptable high noise margin NMH. The ad-

The fan-out of DTL circuits can be further improved by replacing the level-shifting diode DL2 with a BJT QL and splitting RB into two resistors, RB and (1 )RB, whose sum is
RB, as in Fig. 4. When QL is on, it is self-biased to operate in
the forward-active region and is used in an emitterfollower
configuration. This circuit improves fan-out by QL, providing
more base-driving current to QO, allowing QO to sink more
current from an output load. If 1, the base-collector junction of QL is shorted, causing QL to become a diode. The circuit
then reduces to the one in Fig. 3. The role of each element of
the DTL gate in Fig. 4 is summarized in Table 1. The state of
each diode and BJT is tabulated in Table 2.
Example 1. Voltage Transfer Characteristic of Transistor Modified DTL. Determine the voltage transfer characteristic (VTC) of the transistor modified DTL inverter in Fig.
4. Use VD(ON) 0.7 V for the diodes and VBE(FA) 0.7 V,
VBE(SAT) 0.8 V, VCE(SAT) 0.2 V for the BJTs, and VCC
5 V.
SOLUTION. The VTC for this improved DTL inverter is
found in a manner analogous to the method in the section

VOUT(V)

VCC

VOH

QO(OFF)
Edge of
conduction

RC
RB
VOUT
DI

DL2

QO(\FA)

DL

VIN

QO
Additional level
shifting diode

RD
VOL = VCE
(SAT)

VEE
Discharge
path
(a)

Edge of
saturation
QO(SAT)
VIH = 1.5
VIL = 1.4
(b)

Figure 3. Modified DTL with diode DL2 and discharge path.

VIN(V)

572

DIODE-TRANSISTOR LOGIC
Table 2. State of Diodes and BJTs for Output High and
Low Levels

VCC

Element

RB

(1 )RB
VIN

1.75 k

RC

6 k

2 k

DI
QL
DL
QO

VOH

VOL

On
Cutoff
Cutoff
Cutoff

Cutoff
Forward active
On
Saturated

VOUT

DTL NAND GATE

QL
DL
QO
RD

5 k

Adding additional inputs to a DTL inverter, as in Fig. 5, provides a circuit that performs the NAND function. This can be
seen by observing when any or all inputs are low,

VX = VIN (low) + VD, I (ON)

< VBE, L (FA) + VD, L (ON) + VBE, O (FA)
Figure 4. Transistor modified DTL (930 series).

and QO is cutoff with

VOUT = VOH = VCC

entitled Basic DTL Inverter. For VIN low, QO is cutoff and

for VIN high, QO is saturated. Thus,
VOH = VCC = 5V

When all inputs are high, VX is high, allowing QO to saturate

(provided that RB is chosen properly) and
VOUT = VCE, O (SAT) = VOL

and
VOL = VCE, O (SAT) = 0.2 V
Furthermore, QO turns on at

Thus, this basic DTL logic family provides the logical NAND
operation.
DTL FAN-OUT

VIL = VBE, O (FA) + VD, L (ON)

+ VBE, L (FA) VD, I (ON)
= 2VBE (FA) = 2(0.7) = 1.4V
and just enters saturation when

VIH = VBE, O (SAT) + VD, L (ON)

+ VBE, L (FA) VD, I (ON)

In determining the maximum fan-out for DTL logic gates, we

consider the case where VOUT VOL for the driving gate. The
opposite case, where VOUT VOH for the driving gate, reversebiases the input diodes of all load gates. Such gates sink very
little current and hence do not impose a current limitation on
fan-out. On the other hand, a low driving gate output voltage
is established with all driving gate inputs high, and fan-out
is limited for this situation.

= VBE (SAT) + VBE (FA)

= (0.8) + (0.7) = 1.5 V

VCC

Note that QL can never saturate because the voltage polarity

for the resistor (1 )RB maintains a negative VBC,L for QL.
RB

1.75 k

RC

6 k

Table 1. Purpose of DTL Elements

Element

Purpose

DI
RB
(1 )RB
QL

Input diode, limits IIH , and provides ANDing

Limits IIL
Self-biases QL
Base-emitter level shifting for shift of transition width
and provides base driving current to QO
Level shifting diode for shift of transition width
Provides discharge path for saturation stored charge
removal from base of QO
Output inverting BJT and output low driver for current
sinking pull-down
Passive current sourcing pull-up

DL
RD
QO
RC

(1 )RB
VINA

2 k

VOUT
QL

DIA

DL
QO

VINB
DIB

RD

5 k

VINi
DIi

Figure 5. 930 Series DTL NAND gate.

DIODE-TRANSISTOR LOGIC
VCC
N=

RB

(1 )RB

1.75 k

VINA

I'IL2

VOL = V'IN

2 k

IOL
IIL

I'IL1

6 k

RC

573

N identical
load gates

IOL

QL
DIA

I'ILN

DL
QO

VINB
DIB

RD

5 k

VINi
DIi

Figure 6. DTL NAND gate in output low

state driving N gates.

The maximum fan-out is obtained by determining how

much output current IOL the driving gate can sink from multiple, identical output gates as depicted in Fig. 6. Since each
load gate will have the same input current IIL, from Kirchhoff s current law we obtain

ual device and components in the output load gate have a

prime to distinguish the load gate components from the driving gate components.

NIIL = IOL

IIL is found by following dashed path 1 of Fig. 7, and then

writing this current as the difference in voltage across the
resistors in series divided by the sum of the resistors.
Hence,

Input Low Current (IIL)

or
N=

IOL
IIL

IRB
= IIL =

To determine N, we use Fig. 7, which shows one of the load

gates explicitly with VOUT VIN VOL. Note that the individ-

VCC
VD,
I (ON) VCE, O (SAT)

R
B + (1 )R
B

VCC VD (ON) VCE (SAT)

= IRB
RB

V'CC
1
VCC
3

RB

R'B

1.75 k

RC

3
(1 )RB
VIN

R'C

(1 )R'B

6 k
VOL = V'IN

2 k

2 k

V'OUT

I'IL1

1
1

I'IL2

D'IA

Q'L
D'L
Q'O

IOL

DL

R'D
QO
RD

5 k

I'ILn

2
1

Driving gate (output low state)

6 k

QL
DIA

1.75 k

Load gates (output high state)

Figure 7. Cascaded DTL gates for fan-out and power calculations.

5 k

574

DIODE-TRANSISTOR LOGIC

Output Low Current (IOL)

IOL is found by writing Kirchoffs current law (KCL) at the
collector of QO where
IOL = IC, O (SAT) IRC
The current through RC is found by following dashed path 2
of Fig. 7, yielding
IRC =

VCC VCE, O (SAT)

RC

The collector current of QO(SAT) is obtained from

IC, O (SAT) = OL F IB, O (SAT)
where OL is the saturation parameter, smaller for deeper saturation (larger IB,O). However, for maximum fan-out, we consider operation at the edge of saturation where 1 and
IC, O (SAT) = IC, O (EOS) = F IB, O (EOS)
To determine this quantitatively, we write KCL at the base
of QO to obtain
IB, O = IE, L IRD
where
IRD =

VBE, O (SAT)
RD

The emitter current of QL is found by analyzing the portion of

the driver gate including VCC, RB, (1 )RB, QL, DL, and QO
as redrawn in Fig. 8. Considering the base current of QL to be
zero, the current through RB is equal to the emitter current
of QL and the emitter current of QL is
IE, L =

VCC VBE, L (FA) VD, L (ON) VBE, O (SAT)

RB

The following example indicates the use of these equations.

VCC

Example 2. DTL Fan-Out. Calculate the fan-out for the

DTL inverter of Fig. 6 considering the circuit in Fig. 7 and
the subcircuit in Fig. 8. Let F 49, VBE(FA) 0.7 V,
VBE(SAT) 0.8 V, and VCE(SAT) 0.2 V for the BJTs and let
VD(ON) 0.7 V for the diodes. Also, use OL 0.85 for the
output low state and VCC 5 V.
SOLUTION. Substituting these values directly into the derived equations yields

(5) (0.7) (0.2)

= 1.09 mA
(3.75 k)
(5) (0.2)
= 800 A
=
(6 k)
(5) 2(0.7) (0.8)
= 1.60 mA
=
(0.467)(3.75 k)
(0.8)
= 160 A
=
(5 k)
= (1.60 mA) (160 A) = 1.44 mA

IIL = IRB =
IRC
IE, L
IRD
IB, O

IC, O = (0.85)(49)(1.44 mA) = 60 mA

IOL = (60 mA) (800 A) = 59.2 mA
N=

(59.2 mA)
= 54.3
(1.09 mA)

Hence, the fan-out of this DTL gate is 54. Note that IB,O
1.40 mA is indeed large enough to saturate QO.
DTL POWER DISSIPATION
To determine the average power dissipation of a DTL gate,
we first determine the currents being supplied by VCC for both
the high and the low output states. Notice that these currents
have already been obtained in the fan-out analysis of the previous section.
Output High Current Supplied [ICC(OH)]
For the output high state the input is low [i.e., VCE(SAT)], and
considering dashed path 3 in Fig. 7, we have
IRB (OH) = IIL =

VCC VD (ON) VCE (SAT)

RB

Since QO is cutoff, IRC(OH) 0, and

ICC (OH) = IRB (OH)

1.75 k

RB

Output Low Current Supplied [ICC(OL)]

For the low output state, the input is high, then

2 k

(1 )RB
DI open

IRB (OL) = IE, L

QL

DL
IDL
QO
VBE(FA)

VD(ON)
VBE(SAT)

VCC VBE (FA) VD (ON) VBE (SAT)

RB

Additionally, the current through RC for this output low state

is simply
IRC (OL) =

Figure 8. Portion of DTL driving gate.

VCC VCE (SAT)

RC

DIPOLE ANTENNAS

Thus,
ICC (OL) = IRB (OL) + IRC (OL)
Average Power Dissipation [PD(avg)]
The average power dissipated is now found by substituting
into

PD (avg) =
=

ICC (OH) + ICC (OL)

VCC
2
IRB (OH) + IRB (OL) + IRC (OL)
2

VCC

Example 3. DTL Power Dissipation. Calculate the average power dissipation for the DTL gate in Example 2.
SOLUTION. Direct substitution of the values calculated in
Example 2 yields

(1.09 mA) + (1.60 mA) + (800 A)

2
= 8.73 mW

PD (avg) =

Compared to metaloxidesemiconductor (MOS) logic families, this amount of power dissipation is quite large.

CONCLUSIONS
Although DTL logic circuitry can be fabricated quite conveniently in IC form, this family has many disadvantages and
was only used extensively prior to the introduction of TTL. In
the 1990s, there are numerous other logic families that offer
improvement in all aspects of operation.

BIBLIOGRAPHY
T. A. DeMassa, Electrical and Electronic Devices, Circuits and Instruments, St. Paul, MN: West, 1989.
T. A. DeMassa and Z. Ciccone, Digital Integrated Circuits, New York:
Wiley, 1996.

THOMAS A. DEMASSA
Arizona State University

JOHN CICCONE
VLSI Technology, Inc.

575

DIGITAL FILTER SYNTHESIS

475

brating at 494 Hz corresponds to the note B); (2) Ears are

sensitive to certain frequencies and completely deaf to others;
(3) Ears can discriminate between sounds regardless of their
relative loudness; that is, they can differentiate between the
A note played by a violin and the same note played by a trumpet, even if one is significantly louder than the other. The last
characteristic is an instance of frequency-selective processing.
Both instruments create a sound that is not a pure vibration
at 440 Hz, but has components that vibrate at frequencies
that are characteristic of each instrument. The vibration at
440 Hz is by far the strongest, allowing the ear to recognize
the note while the vibrations at other frequencies create an
aural perception unique to the instrument. The fact that loudness is not significant indicates that the relative strength of
the vibrations is more important than the actual intensity.
Any sound can be viewed as a combination of basic sound
waves, each of a unique frequency and strength. The relative
strength becomes a signature that permits the identification
of a sound regardless of its level. One can characterize classes
of sounds by the form in which their strength is concentrated
at the various frequencies; and more significantly, one can
create or enhance sounds by adjusting the signal energy at
the various frequencies.
Frequency-Selective Enhancement

DIGITAL FILTER SYNTHESIS

OVERVIEW OF THE PROBLEM
Direct digital synthesis is applied to problems in signal enhancing, such as the following case study: Assume that a
faulty tape recorder is used to record a critical message. Due
to all the hissing noises created by the tape and recording
systems, the message is unintelligible. In order to know the
message, it is imperative to improve the quality of the audio
signal. All the actions performed to attain that goal are said
to be intended to enhance the signal.
By extension, any effect that tends to reduce the quality of
data is called noise, and data are said to be corrupted by noise.
Data signals may originate not only from voice or audio, but
from many other sources such as radio and television, industrial and medical instrumentation, statistical sampling, and
so on. In general, one strives to manipulate the corrupted signal and recreate the original data.
A significant feature of signal-enhancing problems is that
neither the desired data nor the corrupting noise can be
known exactly. In the example of the recorded message, one
must enhance the signal to get the message; the noise, in general, is caused by random effects. At best, one may be able to
identify the signals as members of certain classes.
The enhancing considered in this article is based on the
concept of frequency-selective response and listening is an example of this type of processing. The human (animal) ears are
frequency-selective in the following essential ways: (1) Sounds
of different frequencies are recognized as being different (e.g.,
a sound wave vibrating at 440 Hz is the note A, and one vi-

Frequency-domain analysis is a generalization of the representation of sound waves as combinations of basic vibrations.
The Fourier transform is the mathematical tool used to determine how the energy of the signal is distributed at different
frequencies. Devices that have a frequency-selective behavior
are mathematically described by their frequency response. The
class of devices considered in this article are said to be linear
and time-invariant (1, pp. 4654). For these systems the frequency response is a complex-valued function which determines how the device responds to any linear combination of
sinusoids.
The statement that a continuous time system, also referred to as a filter, has a frequency response, H(2f), conveys
the following information: (a) The variable, f, corresponds to
the frequency in cycles per second (Hz), which is related to
the frequency measured in radians per second by the relationship 2f. (b) H(2f) is a complex number with magnitude
H(2f) and argument (2f) H. (c) If one applies as input
to this system the signal u(t) cos 2ft, the output of the
system will be the sinusoid, y(t) H(2f) cos[2ft
(2f)]. In an extreme case, if for some frequency, f 0, one has
H(2f 0) 0, then that particular frequency is completely
eliminated from the output of the system.
There are many practical signal-enhancing applications
which use frequency-selective processing based on an ideal
band-pass behavior. With the specified frequency range f l
f f h, the ideal device is given by


1; f l | f | f h
Hbp (2 f ) =
0; elsewhere
Standard variations of this ideal behavior are: ideal low-pass
filter ( fl 0), high-pass filter ( fh ), and a stop-band filter
(1 Hbp(2f)). All ideal filters are unrealizable since, in theory, they require complete knowledge of past, present, and

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

476

DIGITAL FILTER SYNTHESIS

future values of the input signal in order to operate. Creating

realizable filters which approximate the behavior of ideal
ones is still a very active research area.
In the early days of radio, telephony, and industrial instrumentation, all signals were converted into voltages or currents. All filtering was performed using analog components
such as resistors, inductors, and capacitors creating devices
known as passive filters. With the advent of electronicsin
particular, solid-state devicesit is now possible to emulate
and improve on the traditional passive filters. The new devices require an external power supply and are referred to as
active filters.
There is a significant amount of literature dealing with the
design of the basic filters. The reader is referred to Ref. 2
(pp. 666692) for designs based on analog filters, including
Butterworth, Tchebychev, elliptic, and Bessel filters. There
are also well-established computer-aided tools that only require from the user the specification of the frequency range
and the type of the filter desired, based on which, they deliver
a realizable filter which approximates the desired behavior
(3).
DIRECT DIGITAL DESIGN
Nowadays, it is possible to use computers to perform the recording and enhancing of signals. Figure 1 establishes basic
notation by showing a block diagram for filtering a signal using two techniques. In the figure, the continuous time signal,
x(t), is to be enhanced (e.g., the voltage from the audio amplifier going to the speakers). The block Analog Filter represents the conventional processing producing an enhanced signal, y(t). The block Sampling represents the physical process
of collecting the samples of the signal, x(t); the actual device
is an analog-to-digital converter (ADC). The sequence of values is modeled as a discrete time signal, xd[k]. If the sampling
process is ideal and the sampling period is T, then

constructed enhanced signal, yr(t) (4, pp. 9199). An ideal, and

hence unrealizable, reconstruction uses the formula
yr (t) =

k=

sin( (t nT )/T )
(t nT )/T

In practice, there are several efficient computational techniques to create reconstructed signals that satisfactorily approximate this ideal behavior (see also Ref. 5, pp. 100110;
Ref. 2, pp. 763774).
The goal of direct digital synthesis is to define the numerical processing that must be done to the samples so that the
complete sequence samplingdigital filteringsignal reconstruction creates desired enhancing effects on the signal.
Numerical algorithms designed to process the samples are
considered discrete time systems (the independent variable is
integer-valued). Conceptually, one can apply as input a discrete time sinusoid and characterize the frequency-selective
behavior using a discrete frequency response. In this case, the
frequency response is a 2 periodic function of the discrete
frequency, . The notation Hd(ej) is used to emphasize the
fact that the function is periodic. Knowledge of the discrete
frequency response permits, ideally, the complete determination of the numerical algorithm that is required. Using the
exponential Fourier series expansion (see Ref. 4, pp. 3951)
one can write

H(e j ) =
hn =

hn e jn

n=


H(e j )

d
2

The coefficients of the expansion, hn, define the impulse response of the discrete time system. The enhanced digital signal values are computed either by using directly the convolution formula

xd [k] = x(kT )

yd [k] =

The block Digital Filter corresponds to the numerical process

that will be applied to the samples of the input signal to produce samples of the enhanced signal, yd[k]. It is said to be a
realization of a discrete time system. The block Reconstruct
represents the process used by the computer to create an analog signal from a sequence of numerical values, yd[k]. The device is called a digital-to-analog converter (DAC). A sound
card (in a computer) or a CD player performs such a reconstruction operation to produce sounds from the digits stored
in the computer or in the compact disc. The result is the re-

yd [k]

hn xd [k n]

(1)

n=

or by using an equivalent efficient numerical algorithm. Notice that when

hn = 0;

n < 0

the value of yd[k] depends only on input samples, xd[m], where

m k. The algorithm is said to be causal and is suitable for
on-the-fly processing where the input samples arrive in real
time.

Analog
filter

y(t)

Signal
x(t)

ADC
Figure 1. Analog and digital signal filtering.

Sampling

xd[k]

Digital
filter

yd[k]

DAC
Reconstruct

yr(t)

DIGITAL FILTER SYNTHESIS

If the number of nonzero coefficients is finite, one has a

finite impulse response (FIR); otherwise it is infinite impulse
response (IIR). For this latter class of filters, the formula in
Eq. (1) is not an efficient algorithm and one must find an alternative representation. A standard form suitable for real
time operation is the recursive expression
yd [k] + a1 yd [k 1] + + am yd [k m]
= b0 xd [k] + + bm xd [k m]

(2)

However, it is known that some impulse responses, hn, do

not allow such a recursive representation, and there are no
general techniques to establish such a representation for a
given impulse response. The direct determination of a recursive implementation with a desired frequency response is
still an open research problem. References 6 and 7 provide
partial results for the direct design of IIR filters.
Relating Continuous and Discrete Frequency Responses
It is possible to relate the continuous time frequency, f, to the
discrete time frequency, . The procedure requires the development of a continuous time model for discrete time signals
and leads to the equation
2 f T = ,

This equation highlights two important issues in digital signal processing: (1) Under the ideal reconstruction scheme, the
analog signal created from the samples cannot contain any
frequencies above the frequency f N 1/2T; that is, it is bandlimited. (2) If the original analog signal, x(t), contains frequencies above the value 1/2T, it will not be possible to recreate the analog signal from the samples; even the ideal
reconstruction will be different. This phenomenon is known
as aliasing, and the frequency, f N, is called the Nyquist frequency in honor of H. Nyquist (8), who first stated the result
in his Sampling Theorem (2, pp. 2133).
The relationship has also been used to define discrete time
frequency responses when the desired continuous time response is known. In one approach (see Ref. 4, pp. 9799), one
period of the discrete frequency response is defined as follows:
Hd (e j ) = H(2 f ),

f =

||
2T

This approach actually relates the discrete impulse response

to samples of the continuous time frequency response. The
reader is referred to Ref. 4 (pp. 406438) for techniques based
on discretization of the transfer function.
In a simpler approach, the relationship between discreteand continuous-time frequency is used to define basic frequency-selective responses for discrete-time systems. Different techniques are used to determine a numerical processing
algorithm which gives (approximately) the desired frequency
response.
Example 1. In theory, the human ear can perceive frequencies up to 20 kHz. For simple voice applications, one can preserve intelligibility with a much smaller bandwidth. The
smaller the bandwidth, the larger the amount of noise that is
eliminated. For most applications this increases signal-tonoise ratio; but if the bandwidth is made too narrow, then the
message itself will be destroyed. If understanding the mes-

477

sage is the goal, one may recognize sentences even if all frequencies above 2 kHz are eliminated. Bandlimiting is thus a
viable technique to increase signal-to-noise ratio and would
be one of the techniques considered for recovering the message in the opening case study. As an example, assume that
the voice signal needs to be enhanced by eliminating all frequency components below f l 60 Hz and above f h 12,000
Hz. The signal is sampled at a frequency of f s 44.1 kHz, or
with a sampling period, T 1/f s, which is the normal sampling rate for storing music in compact discs.
An ideal analog filter to perform this operation is the filter


H(2 f ) =

1; f l < | f | < f h
0; elsewhere

To each of the frequencies, f l and f h, one associates the discrete frequencies, l 2f lT, h 2f hT. One period of the
ideal discrete frequency response will be


Hd (e ) =
j

1; l || h
0; elsewhere in [ ]

Once the desired ideal frequency response is defined, one can

use the Fourier series expansion to determine the coefficients, hn, of the impulse response. The result in this case is

1 (sin n sin n ); n = 0
h
l
hn = n

0;
n=0
It is clear from this expression that there are infinitely many
nonzero values of hn and the convolution representation in
Eq. (1) is not efficient. Moreover, there are nonzero values of
hn for negative values of n, showing that the system is noncausal and cannot be implemented in real time. It is also apparent that the values of hn get smaller and smaller as n increases. From a practical point of view, one could consider
that after a certain value N, they are zero. This effectively
implies a truncation of the impulse responsethat is, using
an FIR approximation. Once the response is truncated to a
finite number of terms, the problem of hn 0 for n 0, can
be solved by introducing a time delay in the computation of
the response (see Ref. 4, pp. 250254).
There are many situations where a simple truncation of
the impulse response introduces a significant deterioration of
performance (see Ref. 4, pp. 444462). A simple and effective
technique to overcome this is to perform the truncation by
means of a smooth window function. The new coefficients of
the impulse response are given by
h n = w(n)hn
An example of a window function is the generalized Hamming
window:

2 

+ (1 ) cos
;

N


N1
N 1
wH (n) =
,0 1
n

2
2

0;
elsewhere

478

DIGITAL FILTER SYNTHESIS

If 0.54, the window is called a Hamming window; and if

0.5, it is called a Hanning window (see Ref. 9, pp. 9293).
The computation of the impulse response coefficients can
be simplified to a great extent if one resorts to the discrete
Fourier transform (DFT), H(k), given by

H(k) =

N1

hn e j(2 nk/N ) ;

k = 0, 1, . . . , N 1

(3)

n=0

The values, H(k), correspond to samples of the Fourier transform for an N-periodic signal at the frequency points, k
2k/N, where k 0, 1, . . ., N 1. For direct digital filter
design, one would proceed as follows:
1. Define the discrete frequency selective behavior that is
required.
2. Select the number, N, that determines the number of
coefficients, hn, to be used. This value is application dependent and can be as low as 4 and as high as 256 or
more.
3. Determine the values of the desired discrete frequencyselective response, H(k), at the frequencies, k
2k/N, where k 0, 1, . . ., N 1.
4. Use the definition of the DFT as a system of algebraic
equations and solve for the values, hn. This operation is
the computation of the inverse DFT. The computation is
performed with high numerical efficiency using a variety of fast Fourier transform (FFT) algorithms (see Ref.
10, pp. 114152).
Remark 1. Using the DFT algorithm to determine the impulse response corresponding to a discrete frequency response, H(ej), has the implicit assumption that the impulse
response is a periodic function. Therefore, there is an aliasing
effect in this approach. If hp(n) is the nth coefficient computed
using the DFT technique, its relationship to the exact coefficients, determined from the series expansion, is given by


h p (n) =
h(n mN)
m

The values h(k) are the exact values of the impulse response
computed using the Fourier series expansion. In practice, by
using a suitably large value of N, the aliasing effect can usually be neglected.
Remark 2. In principle, one can specify any frequency-selective behavior which may lead to coefficients, hn, that are complex numbers. By placing constraints on the frequency response, Hd(ej), one can guarantee that the coefficients will be
real numbers. Also, it is known that if the argument of the
discrete frequency response is a linear function of the discrete
frequency over the interval [ ]linear-phase digital filtersone can obtain performances closer to the ideal using
fewer terms than nonlinear-phase filters.
OPTIMAL DIGITAL FILTER DESIGN
The techniques described in the previous section are aimed
at determining a numerical algorithm that approximates the
behavior of an ideal frequency-selective processing algorithm.

It is significant that they cannot ensure that the best approximation is being used. Moreover, the techniques do not permit
the design of special, or customized, frequency-selective characteristics. This section presents an overview of the extensive
literature on optimal digital filter design, which can be used
to define any type of filter. In this approach, the design is
transformed into a nonlinear optimization problem over a set
of parameters, or filter coefficients. The user must (a) specify
a merit index or cost function, which measures the quality of
a given solution and (b) specify possible constraints in the
optimization process. The various methods differ in the choice
of cost function and constraints.
If the desired frequency behavior is IIR, the problem cannot be solved or implemented unless the filter can be put in
the form of a recursive equation such as Eq. (2). Even in this
case, the frequency response is a highly nonlinear function of
the coefficients, (al, bl), and a general solution to even a simple
optimization problem is not known. Several special cases
have been considered in the literature, and the readers are
referred to Refs. 6, 7, and 9 (pp. 75293). The FIR case has
received much more attention because the frequency response
is a linear function of the coefficients. Moreover, FIR filters
have good numerical properties and can be easily implemented, even if the number of coefficients (taps) is large.
A causal FIR filter with N taps has a frequency response

H(e j ) =

N1

hk e jk

k=0

Let h colh0, h1, . . ., hN1 be the vector of real-valued variables over which the optimization is performed. The desired
specification is given as an ideal, or desired, frequency response, Hd(ej). A commonly used merit index is the Lp, 1
p , one which has the cost function of the form

h) =
J(h

W ()|Hd (e j ) H(e j )| p

d
2

(4)

The function W() is a weighting function used to assign different weights, corresponding to the relative importance of
different frequency ranges (e.g., zero on a frequency band of
no importance to the designer). The value of the exponent, p,
has a definite effect on the solution. If p 1, all errors have
the same importance while p 1 assigns increasingly more
significance to larger errors. The most common constraint is
the requirement of linear phase, which can be easily incorporated as a symmetry condition in the coefficients, leading to
standard canonical filter types (4, pp. 250270).
Least-Squares Solution
The special case, p 2, is called the least-squares method and
has a particularly simple analytical solution. Define

N = col{e jk ; k = 0, 1, . . ., N 1}


T d
Q = 2Re
W ()N N
2



d
u = Re
W ()N
2

(5)

(6)

DIGITAL FILTER SYNTHESIS

where Re indicates the real part of , and TN denotes the

transposed (row) vector. The optimal solution is known to exist and is unique whenever the matrix, Q in Eq. (5) is nonsingular. The expression for the solution is
h = Q1 u

(7)

The matrix, Q, is nonsingular for most practical cases of the

weighting function. For example, if W() is piecewise constant, it is sufficient to require that it be nonzero over at least
one interval (i.e., nontrivial). The trivial case, W 1, leads to
Q I and h u.
In spite of the analytical solution, one normally uses numerical algorithms to compute the solution. A popular algorithm uses the conjugate gradient technique (11), which has
the advantage of being relatively simple to implement and
has a guaranteed convergence to the solution in a finite number of iterations.
A variation of the least-squares approach is presented in
Ref. 12. Here, instead of defining an ideal response, the authors constrain the filter at specific frequencies and convert
the minimization into an eigenvalue problem.
The existence of a formula for the best filter makes the
least-squares method very popular. However, it has recognized limitations: Because of the squaring operation, small
errors are given less importance and may exist over larger
frequency ranges than with other methods; and the merit index will accept large errors over small frequency ranges. As a
result, the approximations that are obtained may display
large peaks (overshoots) and less desirable soft transitions, as
opposed to the sharp transitions of ideal filters. The choice of
weighting function will have a significant effect on the final
solution obtained; but there are no established criteria for its
definition. Lawson (13) provided a significant link between
this method and the equiripple approach presented next. He
proved that the equiripple solution can be obtained as a leastsquares solution for some weighting function, and he developed an iterative algorithm to modify the weighting function.
The algorithm can be used to make the optimization less sensitive to the choice of weighting function, or as a way to improve on a given least squares solution.
Equiripple Solution
The worst-case design avoids the problems in the leastsquares method by minimizing the largest error. The cost
function in this case is
h ) = max W ()|Hd (e ) H(e )|
J(h
j

(8)

This case can be shown to be equivalent to the Lp case for

p . Only special cases of this cost function have known
solutions (14,15), the most important being the case where
the function W() is piecewise constant and the FIR filter is
linear-phase. Using Tchebychev polynomials, it is possible to
give necessary conditions to characterize the optimal solution:
It alternates from maximum to minimum a known number of
times (which depends on the number of parameters); all maxima have the same value and so do all the various minima.
This characteristics give the solution the property called
equiripple. The case does not have an analytical closed-form
solution, but there are excellent numerical algorithms such

479

as the ParksMcClellan technique (see Refs. 16 and 17).

Kootsookos et al. (18), considered the case, W() 1, and developed an algorithm based on the solution of a number of
related extension (Nehari) problems. Their algorithm compares favorably with the exchange algorithm implemented by
Parks and McClellan, with the added advantages that linear
phase is not required and the algorithm is applicable to multivariable filters (filters which process several inputs at the
same time).
Extensions and Further Readings
The optimal design of IIR filters is an active area of research
with only partial results available. Least-squares techniques
have been applied to special forms, such as all pole systems
(see Ref. 4, pp. 701725). Zhang and Ikawara (6) use the
worst-case criterion and reformulate the design problem as a
generalized eigenvalue problem.
Perhaps the strongest extension of the direct design of digital filters has been motivated by problem in computer vision
and image processing. For such application, the signals (images) are modeled as functions of two independent time variables and are referred to as multidimensional signals. Leastsquares design of FIR filters has been formulated and solved
(e.g., in Ref. 19). Theoretical results characterizing multidimensional equiripple solutions are not complete, but some
practical results have been attained by using a modification
of Lawsons algorithm (20).
The technical literature on digital filtering is vast. The
reader can find good lists of references in textbooks such as
Refs. 2 and 4 for conventional signals and Ref. 21 for multidimensional signals.
BIBLIOGRAPHY
1. C.-T. Chen, System and Signal Analysis, 2nd ed., New York:
Saunders, 1994.
2. J. C. Proakis and D. G. Manolakis, Digital Signal Processing:
Principles, Algorithms, and Applications, 3rd ed., Englewood
Cliffs, NJ: Prentice-Hall, 1996.
3. J. N. Little and L. Shure, Signal Processing Toolbox for Use with
MATLAB, MA: The MathWorks, 1992.
4. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1989.
5. J. H. McClellan, R. W. Schafer, and M. A. Yoder, DSP First: A
Multimedia Approach, Englewood Cliffs, NJ: Prentice-Hall, 1998.
6. X. Zhang and H. Iwakura, Design of IIR digital filters based on
eigenvalue problem, IEEE Trans. Signal Proc., 44: 13251333,
1996.
7. L. B. Jackson, An improved Martinez/Parks algorithm for IIR
design with unequal number of poles and zeros, IEEE Trans. Signal Proc., 42: 12341238, 1994.
8. H. Nyquist, Certain topics in telegraph transmission theory,
AIEE Trans., 617644, 1928.
9. L. R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1975.
10. R. E. Blahut, Fast Algorithms for Digital Signal Processing, Reading, MA: Addison-Wesley, 1985.
11. M. Minoux, Mathematical Programming: Theory and Algorithms,
New York: Wiley, 1986.
12. P. P. Vaidyanathan and T. Q. Nguyen, Eigenfilters: A new approach to least squares FIR filter design and applications includ-

480

DIGITAL MULTIMETERS
ing Nyquist filters, IEEE Trans. Circuit Syst., CAS-34: 1123,
1987.

13. C. L. Lawson, Contribution to the theory of linear least maximum

approximation, Ph.D dissertation, University of California, Los
Angeles, 1961.
14. C. Charalambous, A unified review of optimization, IEEE Trans.
Microwave Theory Tech., MTT-22: 289300, 1974.
15. C. Charalambous, Acceleration of the least pth algorithm for minimax optimization with engineering applications, Math. Programming, 17: 270297, 1979.
16. T. W. Parks and J. H. McClellan, Chebyshev approximation for
nonrecursive digital filters with linear phase, IEEE Trans. Circuit
Theory, CT-19: 189194, 1972.
17. J. H. McClellan and T. W. Parks, Equiripple approximation of
fan filters, Geophysics, 7: 573583, 1972.
18. P. J. Kootsookos, R. R. Bitmead, and M. Green, The Nehari shuffle: FIR(q) filter design with guaranteed error bounds, IEEE
Trans. Signal Proc., 40: 18761883, 1992.
19. J. L. Aravena and G. Gu, Weighted least mean square design of
2-D FIR digital filters: general case, IEEE Trans. Signal Proc.,
44: 25682578, 1996.
20. Y. C. Lim et al., A weighted least squares algorithm for quasiequiripple FIR and IIR digital filter design, IEEE Trans. Signal
Process., SP-40: 551558, 1992.
21. D. E. Dudgeon and R. M. Merserau, Multidimensional Digital
Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1984.

JORGE L. ARAVENA
VIDYA VENKATACHALAM
Louisiana State University

DIGITAL HALFTONING. See HALFTONING.

DIGITAL IMAGE PROCESSING. See IMAGE PROCESSING.

DIGITAL LOGIC. See BOOLEAN FUNCTIONS; NAND CIRCUITS;

NOR CIRCUITS.

DIGITAL LOGIC BASED ON MAGNETIC ELEMENTS. See MAGNETIC LOGIC.

DIGITAL LOGIC CIRCUITS, FUNCTIONAL AND
CONFORMANCE TESTING. See LOGIC TESTING.
DIGITAL LOGIC DESIGN. See CARRY LOGIC.
DIGITAL MODULATION. See DIGITAL AMPLITUDE MODULATION.

612

DISCRETE EVENT SYSTEMS

DISCRETE EVENT SYSTEMS

A discrete event system (DES) can be defined as a dynamic
system for which the state changes in response to the occurrence of discrete events. The discrete events take place at possibly irregular or unknown points in time (i.e., asynchronously and nondeterministically) but are the result of
interactions within the system itself. The acronym DES, or
frequently DEDS (for discrete event dynamic systems), has
been used extensively in many different fields of mathematics
and applications to designate apparently widely different systems. Nevertheless, all these systems have in common the
property of being driven by events, rather than by time. The
conceptual structure of a DES is deceptively simple. It is a
system composed of multitudes of jobs that require various
services from a multitude of resources. The limited availability of the resources determines the interactions between
the jobs, whereas the start and the completion of the jobs, as
well as the changes of the resources, generate the events that
govern the dynamics of the system. But this conceptually simple model encompasses scores of event-driven, mostly human-

made, overwhelmingly complex systems: large international

airports, automated manufacturing plants, military logistic
systems, emergency hospital wards, offices, services and
spare parts operations of multinational companies, distributed computing systems, large communication and data networks, very large scale integrated circuits (VLSI), electronic
digital circuits and so on. Typical examples of events that can
trigger the response of a DES and the possible change of its
state are the arrival or the departure of a customer in a
queue, the arrival or the departure of a packet in the node of
a communication network, the completion of a task, the failure or the repair of a machine in a factory, the opening or the
closing of a switch in an electrical network, the pressing of a
key on the keyboard of a personal computer (PC), the accessing or the leaving of a resource, and so on.
System theory has traditionally been concerned with continuous variable dynamic systems (CVDSs) described by differential equations, possibly including random elements. The
essential feature of CVDSs is that they are driven by time,
which governs their dynamics. The discrete-time systems, for
which the time instances are elements of a sequence, are described by difference equations instead of differential equations, but they essentially belong to the CVDS approach as
long as their variables can take numerical values and are
time-driven. In most cases, the discrete-time systems can be
considered merely computational models, obtained by the
sampling of the continuous-time systems. The CVDS approach is a powerful paradigm in modeling real-world natural systems. Currently, CVDSs are the main objects of what
forms the core of our scientific and technical knowledge, ranging from Galileos and Newtons classical mechanics to relativist and quantum mechanics, thermodynamics, electrodynamics and so on. CVDS models have also been highly
successful in most engineering fields to describe low- or medium-complexity man-made systems and are still the main
objects of control theory.
With the continuous and rapid increase in complexity of
the systems to be modeled, analyzed, designed, and controlled, especially of the human-made systems that include
computer and communication subsystems as essential components, systems too complex to allow a classical CVDS description have emerged. For such systems, the variables attached
to the states and to the processes can have not only numerical
values, but also symbolic or logical values. This motivates the
interest in DESs in domains as different as manufacturing,
robotics, vehicular traffics, conveyance and storage of goods,
organization and delivery of services, and computer and communication networks, with particular emphasis on database
management, computer operating systems, concurrent programming, and distributed computing. In all these domains,
control is necessary to ensure the orderly flow of events in
highly complex systems. Significant efforts have been made in
the last two decades to develop a comprehensive framework to
handle DESs. The DES theory, even if still in its infancy
when compared to the differential/difference equations paradigm underlying the CVDS theory, is fast growing at the confluence of artificial intelligence, operations research, and control system theory. Notable among the various approaches
that have been used to represent DESs are the state machines and formal languages models (119), Petri nets (20
29), timed marked graphs (3033), Markov chains (34,35),
and generalized semi-Marcov processes (GSMP) (36,37).

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

DISCRETE EVENT SYSTEMS

These models allowed the analysis of DES qualitative properties, the quantitative evaluation of DES performances by
methods as perturbation analysis (3840) and likelihood ratio
method (41,42), as well as progress in the design and control
of DESs. Even if a general theory of DESs does not yet exist,
the previously mentioned partial approaches have provided
valuable concepts and insights and have contributed to the
understanding of the fundamental issues involved in the
analysis, design, and control of DESs. Discrete system simulation methods, algorithms, and software are now commercially available for both qualitative behavior analysis and
quantitative performance evaluation (4357).
Because of the complexity and the heterogeneity of the domain, as well as its fast growth, only some of the very basic
aspects will be presented in the rest of this article. The main
attention is focused on the modeling of DESs, which allows
one to grasp the basic features and the behavior of DESs.
Some elements of the control of DESs are presented, and
some examples of DES application are given.
MODELS OF DISCRETE EVENT SYSTEMS
The increased complexity of human-made systems, especially
as an effect of the widespread application of information technology, has made the development of more detailed formal
methods necessary to describe, analyze, and control processes
observed in environments such as digital communication networks and manufacturing plants. As opposed to the continuous time-driven evolution of a CVDS [Fig. 1(a)], the evolution
of a DES is piecewise-constant and event-driven [Fig. 1(b)].
The state variables of a DES may have not just numerical
values, but also symbolic or logical values, so that the set of
states Q does not have the vector space structure typical for
CVDS. The elements qj Q, j , may be seen as labels
attached to the various distinct states of the DES. The state
transitions may occur in response to the occurrence of discrete
events k, belonging to a set of events and taking place at
discrete time instances tk. From the point of view of the timing information, DESs can be classified into two main categories: (1) untimed (logical) and (2) timed.
Untimed Discrete Event Systems
Untimed or logical DES models ignore time as a variable that
specifies the moments when the events occur. Only the order

Input = u(t)
x(t) = f(x, u, t)

DES

State (set of states)

CVDS

State (state variable)

x(t)

qn 1

d
c
b

n 1 =
2 = q 3 =
2
q1

a
s

q0
t1 t2

n =
qn

q3

1 =

....

t3

tn 1 tn

Time (time variable)

Time (event sequence)

(a)

(b)

Figure 1. Comparison of generic trajectories of continuous variable

dynamic systems and of discrete event systems: (a) Example of an
illustrative one-dimensional CVDS trajectory. (b) Example of a DES
trajectory (, , , ; a, b, c, d, s Q).

613

of the events is relevant for these models. The untimed DES

models have been used for the deterministic qualitative analysis of control issues such as the reachability of states
(18,58,59) or deadlock avoidance (23,60). Finite-state machine
and Petri nets are the formal mechanisms mostly used for the
representation of untimed DESs. Other untimed frameworks,
such as the trace theory, have also been explored. Nevertheless, finite-state machines and their associated state transition graphs are still the most widely used models because of
their inherent simplicity and because they can be described
adequately by finite automata and regular languages. The
simplest untimed DES model is a deterministic state-machine
or automaton, called generator, described by the 4-tuple
G = (Q,
, , s)

(1)

where Q is the (countable) set of states of the system, is the

(countable) set of events, : Q Q is the transition
function, and s q0 is the initial (start) state of the system.
By a reminiscence of the classical system theory, the set of
states is sometimes called the state space, even if it does not
have the structure of a vector space, typical for the CVDSs.
The function describes the transition from a state q Q to
a new state q (q, ), in response to the occurrence of an
event . The symbol denotes the null element, which
is used to indicate that the transition is not defined for some
pairs (q, ) Q . For this reason, : Q Q is called
a partial function. It is convenient to designate by f(q) the
set of all feasible events for a given state q, i.e., f(q)
(q, ) . As usual in the regular expressions formalism,
we denote by * the set of all finite strings of elements of ,
including the empty string . A sample path (trajectory) of a
DES, starting from the specified initial state q0 s [see Fig.
1(a)], is given by the state-(event-state) sequence q01q12,
. . ., nqn. The set of all (physically) possible such sequences
is called the behavior B(G) of the generator G:
B(G) = {q0 1 q1 2 , . . ., n qn |n N , 1 k n, qk = (qk1, k )}
(2)
For a deterministic DES, the sample trajectory can be described equivalently by the event string kk1,2,. . .,n, or by the
state string qkk0,1,2,. . .n. In the formalism of regular languages, an event string corresponding to a sample trajectory
is called a word w built with the symbols taken from the
alphabet . Correspondingly, the set of all the (physically)
possible words is called the language L(G) * generated by
G over the alphabet . Sometimes, the language is also called
the behavior of the DES, or the behavior of its generator. In
the framework of automata theory, an automaton is described
by a 5-tuple, which includes as a fifth element a set of marker
states Qm Q. A marker state usually represents the completion of a task. This is not essential in this context, so it is
deferred for the following section.
Example 1. Consider a DES generator G that models a simple generic machine. The state set Q I, W, D, is composed
of the states: IIdle, WWorking, and DDown, whereas
the event set S, C, B, R is composed of the events: S
Start of a task, CCompletion of the task, BBreaking

614

DISCRETE EVENT SYSTEMS

I2

D2
R2

S
C
W

W2

S1
D

B2

I1

Figure 2. The transition graph of a simple generic machine model.

The system can be in the states: IIdle, WWorking, and DDown,
and the transitions are induced by the events: SStart of a task,
CCompletion of the task, BBreaking down, and RRepair.

S1

C2
S1

C1
R2

S1
C2
B1

R1

S1
D1

S1

C1

B2

W1
R1

down, and RRepair. Figure 2 shows the transition function

of the system. The states are designated by nodes, and the
events by oriented arcs connecting the nodes. The initial state
s I is marked with an entering arrow. The language generated by G, i.e., the set of all the (physically) possible sequences of events is

C1

B1

R1
R2

B1

B2

C2
Figure 4. The transition graph of a system made up of the two instances of the simple machine model shown in Fig. 2, operating as
elements of the system.

L(G) = {, S, SD, SC, SCS, SCSD, SDR, SDRS, SDRSD, . . . }

which can be written in the formalism of regular expressions
as L(G) (SC SDR)*( S SD).
Example 2. Let us now consider the case of two machines of
the type given in Example 1 working in parallel. Each machine has a generator of the previously considered type. The
transition graphs of the two machines working as independent entities are represented in Fig. 3. The system composed
of the two machines working in parallel, even without conditioning each other, has the state set Q Q1 Q2 (I1, I2),
(W1, I2), (D1, I2), . . ., (D1, D2), the set of events 1
2 S1, C1, B1, R1, S2, C2, B2, R2, and the transition graph
shown in Fig. 4. The combinatorial growth in complexity of a
DES with the increase of the number of components is obvious.
Since untimed models contain no quantitative timing information, they cannot be used to obtain performance measures involving time, such as holding times or event occurrence rates. Nevertheless, logical DES models have
successfully been used to represent and study qualitative aspects in areas such as concurrent program semantics, communicating sequential processes, synchronization in operating
systems, supervisory control, communication protocols, logical
analysis of digital circuits, and fault-tolerant distributed computing and database protocols. The control theory of discrete
event systems has been initiated by Ramadge and Wonham

I1

I2

S1
R1

S2

C1
W1
B1
D1

R2

C2
W2
B2
D2

Figure 3. The transition graphs of two instances of the simple machine model in Fig. 2, operating independently.

(see Refs. 1619,61,62) in the framework of untimed DESs.

The analysis of an untimed DES model typically proceeds as
follows. By using some state transition structure (e.g., automata or Petri nets), a set of algebraic equations, or a logical
calculus approach, one specifies the set of all admissible event
trajectories, that is, enumerates all the sequences of events
that do not contradict various physical restrictions inherent
to the modeled system. On this basis, the behavior of the systemusually expressed by the generated language L, that is,
by the set of all the possible finite sequences of events that
can occur in the systemis found as a strict subset of all
event orderings *. In the control context, one has to further
restrict the language so that each system trajectory has some
desired property such as stability (e.g., state convergence),
correct use of resources (e.g., mutual exclusion), correct event
ordering (e.g., data base consistency), desirable dynamic behavior (e.g., no deadlock/livelock), or the achievement of some
goal (e.g., distributed consensus).
The difficulties in applying logical DES models to real-life
size problems are caused by the computational complexity.
Even if problems like establishing controllability or designing
a supervisor to control the behavior of a DES are polynomially
decidable or polynomially solvable in the number of states of
the DES, the number of states itself grows in a combinatorial
manner when a complex system is built from simpler component subsystems. As a consequence, the number of the states
of a logical DES increases exponentially with respect to the
system size. This motivates the efforts to state/event formalisms that have the capability to suppress the aspects of the
system description irrelevant in a given context. One modality is event internalization, or partial observation, which
leads to nondeterministic process behavior and, consequently,
to inadequacy of formal languages as models of behavior. The
complexity issues are also talked with by using modularity,
hierarchy, and recursivity when building the system descriptions from the individual component features. Since all the
components of a complex process must interact and synchronize when operating in parallel, a suitable mechanism for
communication and interaction between modules is an important component of DES modeling.
Markov Chain Model of an Untimed DES. One way of modeling the random behavior of discrete event systems is by using

DISCRETE EVENT SYSTEMS

the Markov chain formalism. As pointed out earlier, the nondeterministic behavior of a system can be the result of its
incomplete (partial) description. Either some of the events are
aggregated into complex events that can yield multiple outcomes (event internalization) or the states of the system are
defined in a space of lower dimension than would be required
for their complete specification (hidden variables) so that the
states aggregate and actually correspond to classes of states.
Partial description can be necessary and desirable in order to
reduce the computational difficultiesto make complex systems tractableor can result from incomplete knowledge
about the modeled system. On the other hand, randomness
can be an irreducible feature of some of the processes in the
system itself. The Quantum Mechanics approach is the first
example at hand. The problem of whether or not such builtin randomness does exist is still open to philosophical debate.
From the engineering point of view, this is irrelevant because
the behavior of the system is similar in both cases.
A Markov chain model of a nondeterministic DES is defined by the set of states Q and the transition probability matrix PS [PSij], where
1. PSij P(qjqi), for i j, is the conditional probability that
the system passes into the state qj Q, i.e., the probability of occurrence of event ij (qi, qj), provided that
the current state is qi Q.
2. PSij 1 ji PSij is the probability of remaining in the
state qi, which is the probability of occurrence of event
ii (qi, qi), if ii f, or the probability that no event
occurs in the state qi, if ii f.
The probability that, starting from the initial state s
q(0) qi, the system arrives after n steps into the state
q(n) qj is denoted by PSij P[q(n) qjq(0) qi]. Thus, the
entries of the transition probability matrix give the probabilities of paths of length one:
P ijS = P[q(n + 1) = q j |q(n) = qi ]
Markov chains can be used to represent the closed loop behavior of a controlled DES. In this case, the probabilities of
the enabled transitions (events) are strictly positive, whereas
the probabilities of the disabled transitions are zero. The control of a DES modeled by a Markov chain consists thus in
changing the transition probabilities, according to the commands issued by the supervisor, to achieve a certain controlling task.
Timed DES Models
Timed DES models were developed primarily to allow the
quantitative evaluation of DESs by computing performance
measures like holding times or event occurrence rates, which
imply counting events in a given time interval or measuring
the time between two specific event occurrences and obtaining
the appropriate statistics. The timed event trajectory of a
DES is specified by the sequence k, tkkN*, whereas the timed
state trajectory is qk, tkkN, where tk gives the moment of the
kth event occurrence. Significant analytical results have been
obtained in the special case of queuing theory. For the systems that do not satisfy the specific hypotheses of the queuing
theory, timed DES models have been studied by using simula-

615

tion and statistical analysis, which is computationally costly

and has little potential for real-time control. Both approaches
were used for the evaluation of performances related to resource contention and allocation, based on the oversimplifying
assumption that a manufacturing process can be described
adequately by using only timing considerations. For instance,
the problem of the yield percentage in semiconductor wafer
manufacturing is more closely related to the properties of the
materials and to the technological aspects than to resource
contention.
Another approach is based on the fact that sample paths
of parametric DESs contain a considerable amount of information that allows to predict the behavior of the system when
the values of the parameters are perturbed. Both infinitesimal perturbation analysis (IPA) and likelihood ratio (LR)
methodology have been used in conjunction with various gradient-based stochastic optimization schemes. These techniques yielded significant results in problems like routing in
communication networks or load balancing in distributed processing systems.
In order to define a timed DES, a mechanism for generating the event time instance sequence tkkN has to be added
to the untimed model. This mechanism should also take into
account the randomness of the event lifetime , . Cassandras and Strickland (36) have introduced a model to study
the properties of the sample paths of a timed DES. The generator
G = {Q,
, , s, F}

(3)

contains, in addition to the components of an untimed DES

[Eq. (1)], the event lifetime generator:
F = {F (),
}

(4)

which is a set of probability distribution functions (pdfs) associated with the events.
The basic simplifying hypothesis is that all events are generated through renewal processes, i.e., each pdf F( ) depends
only on the event , not on other factors such as the states
before and after the event occurs and the count of how many
events of type have already occurred.
Figure 5 shows a typical sample path of a timed DES. In
the general case, the set of events contains several types
of events and it is possible that for some states q there are
nonfeasible events , i.e., f(q). In the simplest case,
when there is only one type of event in and this event is
feasible for all the states in the path, the kth lifetime k,i of
the event of type i characterized by the pdf Fi( ) gives the
interval between two successive occurrences of the event
tk1 tk k,i where k 1,2,. . .. A certain time instant t in

q0

q1
t1

q2
t2

qk1

k+1

qk

tk

qk+1

t
k, j
xk,i

tk+1

yk,i

Figure 5. Generic sample path of a timed DES with one event type.
The moment t divides the kth lifetime k,i of event of type i into the
age xk,i and the residual lifetime yk,i.

616

DISCRETE EVENT SYSTEMS

this interval, t [tk, tk1], divides it into two parts that define
the age xk,i t tk of the event i (the time elapsed since its
most recent occurrence), and the residual lifetime yk,i tk1
t k,i xk,i of the event of type i (the time until its next
occurrence). When several types of events are possible, the
next event occurrence is determined by the currently feasible
event with the smallest residual lifetime k1 arg minif(qk)
yk,i, where yk,i is a random variable generated with
the pdf:

Hk,i (u, xk,i ) = P[ yk,i u|xk,i ] = P[k,i xk,i + u|k,i > xk,i ]
=

Fi (xk,i + u) Fi (xk,i )

(5)

1 Fi (xk,i )

The dynamic model of a timed DES, allowing the step-by-step

construction of a sample path, is thus given by
qk = (qk1 , k )
tk+1 = tk +

(6)

min { yk, j }

(7)

j
f (q k )

k+1 = arg min { yk, j }

(8)

j
f (q k )

xk+1,i =

xk,i +

0;

min { yk, j }; if i
f (qk ),

j
f (q k )

i = k

0;

j
f (q k )

otherwise

min { j xk, j }

j=
f (q k )

(11)

The model is similar to the one used by the min-plus dioid

algebra approach presented in a later section of this article.
Formal Languages and Automata DES Models
Formal LanguagesRegular Expressions. Using the previous
notation, let the generator G of an untimed (logical) DES have
the finite state set Q, the finite set of events , and the behavior described by the set of all (physically) possible finite event
strings L(G) *, a proper subset of *the set of all finite
strings built with elements of the alphabet , including the
empty string . In the formal language approach, let us consider that each event is a symbol, the event set is an alphabet, each sample event path w 12 . . . n of the DES is a
word, and the (event) behavior L(G) is a language over . The
length w of a word w (i.e., of a sample path) is the number
of symbols from the alphabet (i.e., events) it contains. The
length of is zero.
Given two languages, L1 and L2, their union is defined by
L1 + L2 = L1 L2 = {w|w L1

or w L2 }

(12)

or w L2 }

(13)

whereas their concatenation is

for k * and for initial conditions specified by some given

s qo and t1 minjf(q0) y1, j, 1 arg minjf(q0) y1, j, and
x1,i minjf(q0) y1, j, where y1, j are random variables drawn
from Fj( ) for all j. This stochastic dynamic model generates
a generalized semi-Markov process. For such processes, a
state is actually defined by two components: the discrete state
qk Q and the so-called supplementary variables xk,i (or,
equivalently, yk,i), for all i . A GSMP offers a convenient
framework for representing timed DESs. The deterministic
mechanism for the state transitions, defined here by the function (q, ), can also be replaced by a probabilistic state transition structure. Even more than in the case of untimed
DESs, despite the conceptual simplicity of the dynamics, the
exhaustive analysis of a stochastic timed DES model can be
of prohibitive computational complexity, not only because of
the large number of states but also because of the nonlinearity of the equations and the age-dependent nature of the pdfs
Hk,i(u, xk,i). On the other hand, if the dynamic equations are
seen as a sample path model, than the timed trajectories of
DES can be generated relatively simple when the lifetime distributions Fi( ) are known for all i . This allows the use
of techniques like perturbation analysis (38) or the likelihood
ratio method (39,40) for performance evaluation, control, or
optimization purposes.
The stochastic model can be reduced to a deterministic one
if the lifetimes are considered to be constants for all i .
The residual lifetimes of events are determined by yk,i i
xk,i, for all i, k, whereas the event ages xk,i result from the state
equation

xk+1,i =

tk+1,i = tk,i +

(9)

otherwise

xk,i + min { j xk, j }; if i
f (qk )\{k }

with x1,i 0. The event time instances are given by the time
Eq. (7)

(10)

L1 L2 = {w|w = w1 w2 ,

w L1

The Kleene (iterative) closure of a language L is

L = {w|k N

and w1 , w2 , . . ., wk L so that

w = w1 w2 wk }

(14)

The union, concatenation, and Kleene closure are regular operators.

A string u is a prefix of w *, if there is some v * so
that w uv. If w L(G), then so are all its prefixes. A prefix
is called proper if v , w.
The prefix closure of L * is
L = {u|uv L

for some v
}

(15)

A language L is prefix closed if L L, i.e., if it contains the

prefixes of all its words.
The (event) behavior of a DES can be modeled as a prefix
closed language L over the event alphabet . In the following,
the main relevant propositions will be stated, but the proofs
will be omitted for briefness. We will write v*, u v, and so
on, instead of v*, u v, when no confusion is possible.
A regular expression in L1, L2, . . ., Lm * is any expression in L1, L2, . . ., Lm containing a finite number of regular
operators. A language is called regular if it can be defined by
a regular expression in a finite set of symbols, i.e., events.
The set R of regular languages over an alphabet is the
smallest set of languages satisfying:
1. R , R ,
2. {a} R,

for a
,

3. A, B R , A B, AB, A* R .

(16)

DISCRETE EVENT SYSTEMS

Regular expressions are notations for representing the regular languages, constructed with these rules:
1. , , and the elements of the alphabet are regular
expressions.
2. If and are regular expressions, then , , *
are also regular expressions.
Obviously, a regular expression can be considered itself a
word (a string of symbols) over the alphabet ), (, ,
, *, .
A language L(), represented by a regular expression , is
defined by
1. L() , L() ,
2. L(a) a, a ,
3. L( ) = L() L( ),

(17)

4. L() L()L(),
5. L(*) L()*.
It can be shown that a language is regular if it is represented
by a regular expression. The set of all the words constructed
with the symbols from an alphabet 1, 2, . . ., n, including the empty word , is represented by the regular expression * 1 2 n*. The set of all the nonempty words constructed with symbols from is given by the
regular expression *.
DES Deterministic Generators. Consider the generator of a
DES modeled by a finite deterministic state machine (automaton) defined now by the 5-tuple
G = {Q, S, d, s, Qm }

(18)

where Q is a (finite) state set, is the (finite) alphabet recognized by G, : Q Q is the transition function, s q0 is
the initial state, and Qm Q is the set of marker states. For
sake of simplicity, we considered here f(q) , q Q [see
comments on Eq. (1)]. As already mentioned, the marker
states have been introduced by Ramadge and Wonham (see
Ref. 16) to represent the completed tasks of a DES by the
state trajectories that end in (or contain a) marker state.
Therefore, along with B(G), the previously defined
unmarked behavior of a DES [Eq. (2)], we define the marked
behavior
Bm (G) = {q0 1 q1 2 , . . ., n qn B(G)|qn Qm }

(19)

which includes all the system trajectories that end in a

marked state, i.e., result in the accomplishment of a certain
task. Correspondingly, in addition to the language generated
by G, the subset L(G) * of all the (physically) possible
words generated by G over the alphabet ,
L(G) = {w = 1 2 , . . ., n
|q0 1 q1 2 , . . ., n qn B(G)} (20)
we define the language marked or accepted by G, as the restricted subset Lm(G) L(G)
Lm (G) = {w = 1 2 , . . ., n
|q0 1 q1 2 , . . ., n qn Bm (G)}
(21)

617

which is composed the words that start from the specified initial state s q0, and lead to a marked state qn Qm. Because
the marked language Lm(G) is a subset of the language L(G),
so is its prefix closure [see Eq. (15)] Lm(G) L(G), i.e., every
prefix of Lm(G) is also an element of L(G). A generator G is
called nonblocking if the equality Lm(G) L(G) holds, meaning that every word in L(G) is a prefix of a word in Lm(G). In
this case, every sample path of events in L(G) can be extended
to include a marker state orin other wordscan be continued to the completion of a task.
The links between the states q Q and the words w
* can be put on a more formal basis using the concept of
configuration. The configuration of a finite automaton is defined by the ordered pair (q, w) Q *, which makes up a
state q and a word w applied in this state.
A configuration (q, w) can be derived from a configuration (q, w) by the generator G, the relation of which is denoted
*G (q, w), if there is a finite number k 0 and a
by (q, w)
sequence (qi, wi)0 i k 1 so that (q, w) (q0, w0), (q,
w) (qk, wk), and (qi, wi), (qi1, wi1), for every i, 0 i
k, i.e., wi i1 wi1, qi1 (qi, i). Each word wi is composed
of the first symbol i1 and the remaining word wi1, so that
the words in the sequence are related by
w = w0 = 1 w1 = 1 2 w2 = = 1 2 k wk = 1 2 k w
(22)
The execution of an automaton on a word w is (s, w) (q1,
w1) (qn, ), with
w = 1 w1 = 1 2 w2 = = 1 2 n

(23)

For a deterministic automaton, each word w defines a unique

execution, thus a unique trajectory of the system.
Using this formalism, a word w is accepted or marked by
a generator (automaton) G if the execution of the automaton
on the given word leads to a marker state qn Qm:

(q0 , w) (qn , ); qn Qm

G

(24)

The language Lm(G) accepted or marked by the automaton G

is the set of words accepted by G:

Lm (G) = {w
|(q0 , w) (qn , ); qn Qm }

G

(25)

DES Nondeterministic Generators. A finite nondeterministic

state machine (automaton) is the 5-tuple
G = {Q,
, , s, Qm }

(26)

where Q, , s q0, Qm retain the meanings defined for deterministic generators [Eq. (18)], whereas the evolution law is
given by the transition relation Q Q, which generalizes the previously defined transition function . For a given
state q Q, an event can induce a transition of the
system to a state p Q, with (q, , p) . The set of states
reachable in one step from the state q, after a transition induced by the event , is
Q(q, ) = {p Q|(q, , p) }

(27)

618

DISCRETE EVENT SYSTEMS

The set f(q) of all feasible events for a given state q can be
expressed as

f (q) = {
|p Q, (q, , p) } = {
|Q(q, ) =

?}

(28)

The deterministic generator can be seen as a special case of

the nondeterministic generator with the property that, for all
q Q and , there exist at most one state p Q such
that (q, , p) . In this case, a transition function : Q
Q can be defined such that (q, ) p Q, when
(q, , p) , and (q, ) , when (q, , p) , i.e., when
f(q).
It is convenient to extend further the definition of the evolution law to a relation * Q * Q, by stating (q0, w,
qn) * if there exist the sequences qkqk Q, k 0, 1, . . .,
n and w kk , k 1, 2, . . ., n *, such that
(qk1, k, qk) , for all k 1, 2, . . ., n.
Using the relation *, the language generated by G can be
expressed as
L(G) = {w
|q Q: (q0 , w, q)  }

(29)

and the language accepted or marked by G as the restricted

subset Lm(G) L(G)
Lm (G) = {w
|qm Qm ; (q0 , w, qm )  }

(30)

A configuration (q, w) is derivable in one step from the configuration (q, w) by the generator G, the relation of which is
denoted by (q, w)
G (q, w), if w uw, (i.e., the word w
begins with a prefix u *) and (q, u, q) *.
A class of equivalent states is a set of states that have the
property that the system can pass from one state in the class
to another without the occurrence of any event, i.e., by transitions on the empty word . The equivalence class E(q) of a
state q is defined as an equivalence class comprising the
state, q, i.e., the set of states reachable from the state q by
transitions on the empty word

E(q) = {p Q|(q, w) (p, w)} = Q(q, )

G

(31)

Two generators G1 and G2 are called equivalent if L(G1)

L(G2).
For any nondeterministic finite generator G Q, , *,
q0, Qm, it is possible to build formally an equivalent deterministic finite generator G Q, , , q0, Qm, for which the
states are replaced with classes of equivalent states. Correspondingly, the state set becomes the set of equivalence
classes Q 2Q (the set of the subsets of the state set Q), the
initial state is replaced by the set q0 E(q0) Q(q0, ) of
states in which the generator can be before any event occurs,
the transition function is defined by (q, ) pQ E(p)q
q : (q, , p) *, and the set of marker equivalence classes
is Qm q Qq Qm . The last equation shows that a
state of G is a marker state if it contains a marker state
of G.
Regular Languages and Finite Automata Representation. As
stated earlier, regular expressions and finite automata are
formalisms adequate for representing regular languages, as
well as for representing the behaviors of DESs, which are

Figure 6. Elementary automata that accept the languages corresponding to the basic regular expression , , and .

languages over some alphabets of events. The following propositions express the fundamental links between regular languages and finite automata:
A language is regular if it is accepted by a finite automaton.
If a language can be constructed by a regular expression,
then it is accepted by a finite nondeterministic automaton.
For each basic regular expression , , , there is an
automaton that accepts the corresponding language as
shown in Fig. 6.
For each composed regular expression 12, 1 2, *1 ,
an automaton accepting the same language can be built
based on the automata A1 and A2 that accept the languages described by 1 and 2, respectively: 1 A1
(1)
(2)
(2)
Q1, , *1 , q(1)
2 , q0 , Qm . For
0 , Qm , 2 A2 Q2, , *
instance, the automaton A corresponding to the regular
expression 12 is 12 A Q, , *, q0, Qm, where
(1)
Q Q1 Q2, 1 2 (q, , q(2)
0 )q Qm , q0
(1)
(2)
q 0 , Qm Q m .
Algorithm for Constructing the Marked Language of a Generator
G. Consider again the generator of a DES G Q, , , s,
Qm, with the finite set of states Q q1, q2, . . ., qn, where
the order is arbitrary. Let us find the language Lm(G) marked
by G, i.e., the set of words over the alphabet that end in a
marker state [see comments on Eq. (30)].
Let us denote by R(i, j, k) the partial language made up of
the set of words allowing the transition from the state qi to
the state qj, passing either directly, or only through states
with indices lower than k. Then

{w|(qi , w, q j )  }, i = j
R(i, j, 1) =
(32)
{} {w|(qi , w, q j )  }, i = j
and the following recurrence relation holds:
R(i, j, k + 1) = R(i, j, k) R(i, k, k) R(k, k, k) R(k, j, k),
k = 1, 2, . . ., n

(33)

Choosing the initial state s q1, the language Lm(G) marked

by G results:
Lm (G) =

R(1, j, n + 1)

(34)

q j Q m

Both the partial languages R and the language Lm(G) are regular languages.
Example 3. Consider a simple DES, having the generator G
given by Eq. (26), with the state set Q q1, q2, the event set
a, b, the initial state s q1, the set of marker states

DISCRETE EVENT SYSTEMS

a
q1

x1

b
q2

619

Aj1

Figure 7. Transition graph of a simple determinist generator. The

initial state s q1 is marked with an entering arrow, whereas the
marker state q2 is represented with a double circle.

Aif

xj

xi

Ain
xn
k

Qm q2, and the transition relation (q1, , q1), (q1, a,

q1), (q1, b, q2), (q2, a, q1), (q2, , q2), (q2, b, q2), for which corresponds the transition graph in Fig. 7. Using the relations (32)
and (33), the partial languages R(i, j, k), i, j, k 1, 2, of G
listed in Table 1 can be computed successively. Thus, the language accepted by G results:

L G) = R(1, 2, 3)
= [b ( a)( a) b] [b ( a)( a) b]
[ b) a( a) b] [( b) a( a) b]
Max-Plus Algebra Representation of
Timed Discrete Event Systems
The max-plus (max, ) algebra deals with a subclass of the
timed Petri nets, namely the timed event graphs. Originally,
Petri nets were introduced as nontimed logical models. Timed
Petri nets have been developed for modeling and performance
analysis, but were found less adequate for control purposes.
The theory of timed DES emerged from the combination of
the max-plus algebra framework with the system-theoretic
concepts. The trends of the research on the max-plus algebra
approach to DESs can be found in Ref. 23. Max-plus algebra
is a convenient formalism for the systems in which synchronization is a key request for event occurrence, including both
discrete events systems and continuous systems that involve
synchronization. Max-plus algebra adequately describes systems for which the start of an activity requires the completion
of all the activities that provide the inputs needed to perform
the considered activity. In such cases, maximization is the
basic operation. The complementary case is that of the systems in which an activity starts when at least one input becomes available. Minimization is the basic operation and the
min-plus algebra is the adequate algebraic structure. These
two limit cases correspond to the AND and OR operators from
the binary logic, respectively. In mixed systems, both types of
conditions can be present, and other related (usually isomorphic) dioid algebraic structures must be used. In the following
we will refer only to the max-plus case.

k+1

Figure 8. Section of a timed event graph showing only the edges

coming into the node attached to event i. Input variables xj(k); j 1,
. . ., n give the moments when events j occur at step k, and the
weights Aij; j 1, . . ., n of the edges correspond to the delays produced by the transport from j to i.

Consider the section of a timed event graph represented in

Fig. 8. Each node corresponds to a certain activity, whereas
the arcs coming into a node represent the conditions required
to initiate the activity attached to the node. An event i (e.g.,
the start of a process) occurs at step k 1 in the moment
xi(k 1) when all the input events (e.g., the end of the prerequisite processes) have occurred at step k in the respective moments xj(k); j 1, . . ., n, and have propagated from j to i
with the transport delays Aij; j 1, . . ., n. The corresponding
discrete-time dynamic system model is given by the equations:
xi (k + 1) = max(Ai1 + x1(k) , . . ., Aij + x(k)
, . . ., Ain + xn(k) ),
j
i = 1, . . ., n

The analysis of this model is significantly simplified by the

max-plus algebra formalism.
The max-plus algebra (max, , ) is a dioid over the set
max , where is the set of real numbers.
The additive operation is the maximization
x y = max(x, y)

R(i, j, k)

k1

k2

R(1,
R(1,
R(2,
R(2,

a
b
a
b

( a) ( a)( a)*( a)
b ( a)( a)*b
a a( a)*( a)
( b) a( a)*b

1,
2,
1,
2,

k)
k)
k)
k)

(36)

and the multiplicative operation is the usual addition

xy = x y = x + y

(37)

The neutral element e with respect to (the one element of

the structure) is 0, whereas the neutral element with respect to (the zero element of the structure) is , which
is also the absorbing element of the multiplicative operation:
a a , a max. This dioid is not a ring
because, in general, an element of max has no inverse with
respect to . One distinctive feature of this structure is the
idempotency of the addition:
x x = x,

Table 1. Partial Languages of the Generator G in Example 1

(35)

x Rmax

The matrix product AB A B of two matrices of fitting

sizes (m p) and (p n) is defined by

(A B)ij =

p


Aik Bk j = max (Aik + Bk j ), i = 1, . . ., m;

k=1

k=1,..., p

j = 1, . . ., n
(38)

620

DISCRETE EVENT SYSTEMS

The matrix sum A B of two matrices of the same size (m

n) is defined by
(A B)ij = Aij Bij = max(Aij , Bij ), i = 1, . . ., m; j = 1, . . ., n
(39)
The multiplication by a scalar a of a matrix A is defined by
(a A)ij = a Aij = a + Aij

(40)

With the formalism of the max-plus algebra, the equations of

a time event graph become

xi (k + 1) =

n


a path for which the initial and the final node coincide. In
the following, we will consider only elementary circuits, i.e.,
circuits that do not pass twice through the same node. The
length of a path (circuit) is defined as the number of edges in
the path (circuit). The weight of a path (circuit) is defined as
the multiplication (i.e., the conventional sum) of the
weights of all the edges in the path (circuit): w(i1 i2
ik) Aikik1 Ai2i1. The average weight of a path is
its weight divided (in the classical way) by its length. For a
circuit, the average weight is sometimes called the circuit
mean.
Example 5. Examples of paths in the graph in Fig. 9 are

Aij x j (k) i = 1, . . ., n

(41)

j=1

or, in matrix form,

x(k + 1) = Ax(k)

(42)

(k) T
where x(k) [x(k)
1 , . . ., xn ] is the state vector at time k, and
A [Aij, i, j 1, . . ., n] is the (n n) system matrix.
The weighted graph corresponding to a square (n n) matrix A is the triple G(A) (N, E, ), where N is the set of n
nodes, E is the set of edges, each representing a nonzero entry
of A, and : E N N, with (eij) ( j, i), eij E if and only
if Aij . The weight of the edge eij is Aij. In the following,
only graphs for which there is at most one edge between any
ordered pair of nodes, oriented from the first node to the second, will be considered.

1 2 (length 1, weight 1, average weight 1),

1 2 3 (l 2, w 3, aw 1.5),
1 2 3 3 2 (l 4, w 12, aw 3).
There are three (elementary) circuits in this graph:
1 2 1 (l 2, w 4, circuit mean 2),
2 1 2 (l 2, w 8, cm 4),
3 3 (l 1, w 3, cm 3).
A graph is strongly connected if there exists a path between any two nodes of the graph. The matrix corresponding
to a strongly connected graph is called irreducible. For an irreducible matrix A, then is a permutation P such that PTA P
is an upper triangular matrix.
Example 6. The graph in Fig. 9 is strongly connected.

Example 4. The graph in Fig. 9 corresponds to the system

matrix

A = 1


9

2

6
3

Ak = A Ak1 , k N

Considering the state at step k given by the vector x(k)

[3, 2, 1]T, the vector at step (k 1) is

 9 
3

x(k + 1) = Ax(k) = 1  6 2
 2 3
1

(9 2)
11

= (1 3) (6 1) = 7
(2 2) (3 1)
4
A path in a graph is a sequence of adjacent edges and nodes:
(i1, i2), (i2, i3), . . ., (ik1, ik) i1 i2 ik. In general,
it is accepted that a path can pass twice through the same
node or through the same edge. A circuit is a closed path, i.e.,

9
x1

6
x2

x3

The power of a square matrix Ak is defined recursively by

Figure 9. Timed event graph corresponding to the system matrix in

Example 4.

(43)

where A0 I is the identity matrix, which has (A0)ij e if

i j, and (A0)ij if i j. The entry (Ak)ij of the kth power
of a square matrix A equals the maximum weight for all the
paths of length k from node j to node i.
A square matrix is aperiodic if there exists k0 * such
that (Ak)ij for all k k0. Aperiodicity implies irreducibility
because (Ak)ij means that there exists at least one path of
length k from node j to node i with weight (Ak)ij. The reverse
is not true.
Example 7. The matrix A corresponding to the graph in Fig.
9 is aperiodic with k0 4.
As in conventional algebra, if for a square matrix A there
exist a vector v [, , . . ., ]T and a scalar such that
Av = v

(44)

then v is called an eigenvector of A, and is the corresponding eigenvalue.

Example 8. It is easy to check that


7
12
7


A 3 = 8 = 5 3
e
5
e

DISCRETE EVENT SYSTEMS

where A is the matrix corresponding to the graph in Fig. 9.

The vector v [7 3 e]T is an eigenvector of A for the eigenvalue 5.
Some very important properties of the eigenvalues and eigenvectors of irreducible matrices are stated next without
proof.
Every square matrix has at least one eigenvalue.
The eigenvalue is unique for an irreducible matrix.
For an irreducible matrix, the eigenvalue equals the
maximum circuit mean taken over all circuits in the
strongly connected graph corresponding to the matrix.
Any circuit for which the circuit mean is maximum is called
a critical circuit.
Example 9. The critical circuit of the graph in Fig. 9 is 1
2 1, which has the maximum average weight over all circuits of the graph. This weight determines the eigenvalue
5 of the matrix A.

Ak

(45)

k=1

Each entry (A)ij of the matrix gives the maximum weight for
all paths of arbitrary length from node j to node i. The length
increases unboundedly, so that the matrix A diverges. For
an irreducible matrix A, with the eigenvalue , a matrix A is
defined by
A = 1 A

(46)

meaning that (A)ij Aij .

The matrix A has the remarkable property that
A+
=


k=1

state is reached within a finite number of steps. The periodic

regime is determined only by the length and the average
weight of the critical circuit, which is the slowest circuit in
the system. If A is irreducible and the corresponding graph
has a unique critical circuit of length m and average weight
(the eigenvalue of A), then A is asymptotically periodic with
period m, i.e., there exists a kA * such that
Ak+m = m Ak , for all k kA

(48)

Example 11. For the matrix A considered in Example 4, the

length of the critical path m 2, its average weight (the eigenvalue of A) is 5, and kA 4, so that A6 10 A4.
Indeed, in the max-plus algebra 10 5 5 52.
The max-plus algebra can thus be used to evaluate the performance of timed discrete systems, in the asymptotic steady
state. For this purpose, the eigenvalue is the key parameter
of a system described by an irreducible matrix because determines the speed in the periodic state. Usually, 1/ is referred to as the throughput of the system.
Petri Nets Models

The matrix A is defined by

A+ =

621

Ak =

n


Ak

(47)

k=1

where n is the dimension of the square matrix A. As before,

(A)ij is the maximum weight for all paths of arbitrary length
from node j to node i, in the directed graph corresponding to
A. The critical circuit in this graph has the weight e. A has
the same eigenvectors as A, but for the eigenvalue e. For any
node j in a critical circuit of A, the jth column of A is an
eigenvector of A (and of A).
Example 10. For the matrix A considered earlier, the matrix A diverges, but we can readily calculate A and A:


4

e
4
5

A = 4

1 ,
e
1
A+
= 4

3 2
7 3 2
The first two columns of A are eigenvectors of A for the eigenvalue 5. It happens that the third column is also an eigenvector.
The asymptotic behavior of the systems described by irreducible matrices is periodic. Remarkably enough, the steady

Petri nets theory has been developed as a formalism able to

describe in a unified way systems that included computers,
programs, and a certain environment. Previously, the various
components of such systems had to be described in different
and unrelated formalisms: automata theory for the computer
hardware, code in a sequential programming language for the
program, and narrative prose for the interaction of the program with the environment. From the three mentioned elements, at most onethe programis sequential so that the
capacity to deal with the characteristics of parallel systems
was a basic request. The timed Petri nets have been introduced in the late seventeen to quantitatively study the performances of parallel systems, especially referring to (1) concurrence, the possibility that events occur independently; (2)
synchronization, the necessity that some events wait for the
others before they can occur; and (3) conflicts, the mutual exclusion of some events. Petri nets have the advantage to have
a precise semantics and to allow the efficient use of algebraic
techniques. The event graphs, which are adequate for modeling collision-free synchronous systems, form a special class of
Petri nets and can be described by linear equations when using max-plus algebra. An overview of Petri nets and of the
concepts related to their properties can be found in the survey
paper of Murata (26).
Untimed Petri Nets. An untimed Petri net is defined by (S,
M0), where S describes the structure of the graph attached to
the net and M0 is the initial marking of the net.
The structural part is characterized by the 5-tuple
S = (P, T, F, r, s)

(49)

with P the (finite) set of places and T the (finite) set of transitions. The places P (customarily represented by circles) and
the transitions T (drawn as bars) form the vertices of a graph.
The arcs of the graph are given by F P T T P. The
maps r : P T * and s : T P * give the (positive)
integer weights of the arcs going from the places toward the
transitions, and from the transitions toward the places, re-

622

DISCRETE EVENT SYSTEMS

p3

p1
1

2
1

p2

3
1

p3

p1
2

p4

1
p5

1
t

p2

(a)

3
1

p4
p5

(b)

Figure 10. Firing of a transition in a Petri net. (a) Transition t is

fireable because for p *t p1, p2, the markings exceed the
threshold: M(p1) 2 r(p1, t) 2 and M(p2) 2 r(p2, t) 1. (b)
After the firing, the markings are M(p1) M(p1) r(p1, t) 0,
M(p2) 1, M(p3) M(p3) s(t, p3) 1, M(p4) 4, M(p5) 2.

spectively. It is customary to inscribe only the arcs with the

weights exceeding one, whereas the arcs without any inscription have unit weight by default. Sometimes, edges with a
larger weight are represented by the corresponding number
of unit weight arcs in parallel. The places may contain zero
or more tokens, usually drawn as black circles. A marking or
state of a Petri net is given by the distribution of the tokens
at a certain moment: M : P , where M(p) gives the number
of tokens in the place p P. The initial marking is given
by M0.
Given a transition t T, the input place set of t is defined
by

t = {p P : (p, t) F}

(50)

and the output place set, by:

t = {p P : (t, p) F}

p = {t T : (t, p) F}

pP

(52)

A transition t in a Petri net is alive for a marking M

R(M0), if there exists M R(M) such that t is fireble under
M. A transition is structurally alive if it is alive for any initial marking. A Petri net is (structurally) alive if all its transitions are (structurally) alive.
The incidence matrix of a Petri net is the T P matrix
A with the elements
Aij = s(i, j) r( j, i)

u k = (1, 0, 1, . . ., 0, 0)T

The dynamics of the Petri net is determined by the marking

M. A transition t is enabled on a marking M, if the number
of tokens in each place p from which there is an arc toward
the transition t exceeds or at least equals the weight of the
arc, i.e., if M(p) r(p, t) for all p *t. An enabled transition
may fire. When a transition t fires, the number of tokens in
the places p *t t* P changes. The number of tokens is
decreased for each input place p *t with r(p, t) pieces and
increased with each output place p t* with s(t, p) pieces.
Consequently, the marking of the network places p P
changes from M(p) to M(p), according to the rule

M(p) r(p, t), p t

M  (p) = M(p) + s(t, p), p t
(54)

M(p), otherwise
Example 12. Figure 10(a) represents a transition for which
the firing conditions are fulfilled. Figure 10(b) gives the marking resulted after the fire.
A marking M2 is reachable from a marking M1 if a sequence of transition firings leading from M1 to M2 exists. The

(56)

which has the entries one for the transitions that fire at step
k and zero for the others.
The net marking at step k can be described by a vector
Mk for which the evolution law is
M k = M k1 + A T u k ;

(53)

(55)

The evolution vector uk at step k is a unipolar binary vector

of size T

whereas the output transition set is

p = {t T : (p, t) F}

pP

Example 13. The Petri net in Fig. 10 is not conservative.

(51)

Similarly, for a place p P, the input transition sets of p is:

set of markings reachable when starting from a marking M

and firing transitions is denoted by R(M). The rechability
problemgiven M1 and M2, establish if M2 R(M1)is exponentially decidable.
A marking M is bounded if for any place p P the number
of tokens is bounded, i.e., there is a constant integer b *
such that M(p) b, p P. A Petri net is bounded for a
given initial marking M0 if it is uniformly bounded for any
M R(M0). A Petri net is safe if the bound is 1. A Petri net
is structurally bounded if it is bounded for any initial marking M0. A Petri net is conservative if the number of tokens is
constant during the evolution of the system:


|M(p)| =
|M0 (p)|, M R(M0 )

k N

(57)

A firing sequence ukk 1, 2, . . ., d is globally characterized by the firing vector

x=

uk

k=1

whereas the final marking is given by

M f = M0 + A T x

(58)

where M0 is the initial marking, and Mf is the final marking.

Example 14. Untimed Petri nets have been used for the validation of communication protocols. The Petri net in Fig. 11
Send message

Receive message

Write
message

Read
message

Read
acknowledgment

Write
acknowledgment
Receive
acknowledge

Send
acknowledge

Figure 11. Untimed Petri net model of a communication protocol

with acknowledge of reception.

DISCRETE EVENT SYSTEMS

shows such a protocol with acknowledge of reception. The system comprises cycles on the emitting and receiving parts. The
position of the tokens gives the state of the system, whereas
the actions are represented by the transitions. The sending
side waits for confirmation from the receiving part before proceeding to the transmission of the next message. The receiving side is ready for a new message only after having sent out
the acknowledgment for the preceding one. The arrival of the
next message can then trigger a new cycle for sending out
the confirmation.
Timed Petri Nets. Timed Petri nets offer a general formalism adequate for including a measure of time in the description of a DES. Petri nets are especially adequate to model
concurrent or parallel discrete systems. A First InFirst Out
(FIFO) discipline is usually adopted for all the places and all
the transitions. Time-related parameters are attached
to each process taking place in the net. If the nth token enters
a place p at the moment u, it becomes visible for the transitions in p* only after the moment u p(n), where p(n) is
the rest time of the nth token in place p. An initial latency
time is also ascribed to each initial token in a place p. If
M0(p) n, the nth token existing in place p at the initial
moment becomes available for the transitions in p* starting
from a moment p(n). The initial latency time is a special case
of the rest time and allows modeling the peculiarities of the
initial phase, whenever necessary. Similarly, the nth fire of a
transition t started at a moment u, ends at moment u
t(n), where t(n), is the duration of the nth firing of the transition t. The tokens are taken from the input places of the
transition t and moved to the output places at the moment
u t(n).
The time parameters have to satisfy certain natural restrictions:
All the rest times and transition durations must be nonnegative p(n) 0, t(n) 0 for all p P, t T, and
n N*.
The initial latency times can be both positive and negative, but they are restricted by the weak compatibility
conditions that require that for each place p: (1) there
exists no transition before the initial moment t 0 so
that M0(p) retains its meaning of initial marking, (2) the
initial tokens in a place p are taken by the output transitions in p* before the tokens supplied to p by the input
transitions in *p.

(59)

where S is the structural part, M0 is the initial marking,

p(n); n N*p P is the set of rest times, t(n); n
N*t T is the set of transition durations, and p(n);
n N*p P is the set of initial latencies.
Equivalent Petri nets having only timed transitions or only
timed places can be built, as shown in Fig. 12 (a, b).
The following state variables are defined to describe the
time evolution of a Petri net:
The schedulers: xt(n), yt(n) is the beginning and the end
moments, respectively, of the nth fire of the transition

tp

p(n)

p(n) = 0

p(n) = 0

tp(n) = p(n)

(a)

t(n)

pt

t(n) = 0

t(n) = 0

pt(n) = t(n)

(b)
Figure 12. (a) Petri net comprising only timed transitions where the
rest time of place p has been assigned as the duration of the equivalent transition tp. (b) Dual case of a net comprising only timed places
where transition t has been replaced with place pt.

t T; vp(n), wp(n) is the entering and the release moments, respectively, of the nth token in the place p P,
The counters: xt(u), yt(u) is the number of times the transition t T has started and ended, respectively, the fire
at moment u; vp(u), wp(u) is the number of tokens entering and leaving, respectively, place p at moment u.
The following conventions are commonly accepted:
xt(0) yt(0) vp(0) wp(0) ,
xt(n) yt(n) vp(n) wp(n) , if the transition t never
fires n times, or the place p never receives n tokens,
xt(u) yt(u) wp(u) 0 and vp(u) M0(p) for u 0.
For any transition t T, where n N*
yt (n) = xt (n) + t (n)

(60)

The FIFO rule requires

wp (n) vp (n) + p (n)

A timed Petri net is thus defined by the n-tuple

TPN(S, M0 ,
, , )

623

for p P, n N

(61)

meaning that the order of the tokens are not changed at any
of the places, and
y t [ yt (n)] = x t [xt (n)]

for t T, n N

(62)

meaning that a transition cannot start its (n 1)th fire before

ending the nth one.
A Petri net is called FIFO if all its places and transitions
observe the FIFO discipline. Usually, the stronger conditions
of constant rest times and constant transition durations are
used. The FIFO constrained can result from the structure of
network, without any hypothesis on the net temporizations.

624

DISCRETE EVENT SYSTEMS

tij

ti
pij

pi
pj
ph
Figure 13. Cyclic transition with structurally restricted FIFO behavior.

phj
thj

tj

th

(a)

(b)

Example 15. The Petri net in Fig. 13 contains a cyclic transition which behaves FIFO for any sequencing of the firing.

Figure 15. Special cases of Petri nets: (a) model of a state machine,
(b) model of an event graph.

Timed Petri nets can be used for quantitative performance

evaluation, e.g., when studying various queuing types. Most
classical networks like Jackson single classes, fork-join
queues, and token rings can be modeled with Petri nets,
whereas others like multiclass networks, Kelly networks, and
processor-sharing systems cannot.

parameters like throughput of a transition or average number

of tokens in a place. Petri nets include as special cases other
frequently used models like state machines, event graphs,
and free-choice nets. The following structural conditions define the mentioned special cases:

Example 16. Figure 14 represents the Petri net models of

some classic types of queues. The Kendall notation is used to
describe a queue. The simplest queue, with any input process
(.), any distribution of the timings of the server (.), one server
(1) and an unlimited buffer () is designated by ././1/.
Petri nets allow a unified treatment of a large class of systems, avoiding the usual case-by-case performance evaluation. It has been shown that Petri nets with inhibitor edges
(i.e., with a special kind of edges from places to transitions,
which trigger the transitions only when the place is empty)
have the computing power of a Turing machine.
The Petri nets can be characterized both by basic qualitative properties like stability, existence of a stationary state,
and the duration of the transient state and by performance

A state machine is a Petri net for which

| t| = |t | = 1; t T

i.e., each transition has exactly one input place and one
output place. As a consequence, between any two places
pi and pj there is at most one transition that would be
denoted by tij, with pi *tij, pj tij*, tij pi**pj, as
shown in Fig. 15(a).
An event graph is a Petri net with
| p| = |p | = 1; p P

...

(65)

meaning that if a place p has more than one output transition, than the place p is the only input place for each of
its output transitions. It results that a free-choice graph
contains substructures of the type shown in Fig. 16, so it
can model both synchronization [Fig. 16(a)] and choice
[Fig. 16(b)], but not both of them for the same process.
Free-choice machines include the state machines and the
event graphs, again as special cases. The event graphs
model only synchronization; they exclude choice. It has

(a)

Que././1/k

...
...
k

(64)

i.e., each place has exactly one input transition and one
output transition. Correspondingly, between any two
transitions ti and tj, there is at most one place pij, with
ti *pij, tj pij*, pij ti**tj, as shown in Fig. 15(b).
A free-choice net is a Petri net for which
p P, |p | > 1 t p , | t| = 1

Que././1/

(63)

(b)

Que././2/

...
(c)
Figure 14. Queue theory and Petri net models of some classic types
of queues: (a) Infinite buffer, single server; (b) Finite buffer, single
server; (c) Infinite buffer, double server.

(a)

(b)

Figure 16. Special cases of Petri netsthe free-choice nets: (a) substructures modeling synchronization, (b) substructures modeling
choice.

DISCRETE EVENT SYSTEMS

been shown than an event graph is alive if each circuit

in the graph contains at least one token. In the opposite
case, the net will run into a dead lock after a finite number of firing instances. In a timed event graph, a place
containing k tokens can be replaced by k chained places,
each one containing exactly one token, interlaced with
k 1 transitions (Fig. 17). The rest time p of the initial
place is attributed to one of the places in the chain, all
the other places and transitions having no delays.
Timed event graphs can be represented as linear systems
by using max-plus algebra. Because of the special structure
of a timed event graph, it is convenient to make the analysis
in terms of the transitions. Let us denote by xi(n) the start
moment of the nth firing instance of the transition ti, i 1,
. . ., k; k T, and by ti the set of the input transitions of
ti:
ti = (ti ) = {t j |t j p, p ti } T

(66)

jt i

(67)

where x xj[n 1 M(pji)] is the start moment of the [n

1 M(pji)]th firing of the transition tj, x tj is the end moment of this process, and xi tj pji is the moment the
transition ti is enabled by tj.
With the delay matrices A, 0,1, defined by

t i + p ji , if ti ti and M(p ji ) =
(68)
(A )ij =
 = , otherwise
Eq. (67) can be written in the matrix form
x(n + 1) A0 x(n + 1) A1 x(n)

(69)

With

A0 =

Ai =

k


i=0

Ai = I + A+
0

(70)

i=0

[see Eq. (45)],

A0 (I A0 ) = A0 (I A0 ) = I

(71)

x(n + 1) A0 A1 x(n)
t2

t1

t = 0

p = 0

(72)

t = 0

t2

p = 0

t1

t2

t1

p1

t1

p2

t2

(a)

././1/././1/

p1

t1

p2

p5

t2

p3

t3

p4

Figure 18. Chained queues: (a) no deadlocks, (b) after-service

deadlock.

The minimal solution of (71) is given by the linear recurrence

relation
x(n + 1) = A0 A1 x(n)

(73)

Using the max-plus algebra framework, the equations of a

timed event graph become linear. As shown at Eq. (48), a relation in the form of Eq. (73) determines a periodic stationary
solution. This means that event graphs have a cyclicity property: after n firings of each transition, the marking returns
exactly to the initial marking. However, this is only a formal
result valid in the firing event ordering scale, not in the time
scale. The nth firing for different transitions occurs at different time moments xti(n) so that there exists no time period
which after the marking is repeated.
Example 17. Figure 18 presents two examples of chained
queues and their corresponding Petri net (event graph) models. The systems contain each of two servers preceded by
queues. The example in Fig. 18(a), for which both queues
have infinite buffers, has no deadlocks. The example in Fig.
18(b), exhibits an after-service deadlock. A client leaving the
first queue when the buffer of the second queue is full must
wait in place p2; consequently, the access of a new client to
the first service is denied.
CONTROL OF DISCRETE EVENT SYSTEMS

results. Relation (69) becomes

t1

././1/././1/

(b)

Consider the nth firing of a transition ti ti. Using the

equivalence in Fig. 16, the place pji P contains at most one
token. If M(pji) 0, then the token enables the nth firing of
ti; else if M(pii) 1, it enables the (n 1)th firing of ti. This
results in the equation
x j (n + 1) > max{x j [n + 1 M(p ji )] + t + p ji }

625

t2

Figure 17. Equivalence of a place containing k tokens with k chained

places each one containing exactly one token.

One major goal in studying DESs has been to devise methods

for controlling the trajectory of a system so as to reach a certain set of desired states, or to avoid some undesired states
including deadlocks or traps. As pointed out in the work of
Ramadge and Wonham (1618), DESs fully qualify as objects
for the control theory because they exhibit the fundamental
features of potentially controllable dynamic systems. Actually, a large part of the work performed in the DES domain
has been motivated by the search for proper techniques to
control event sequences and to select the ones that comply

626

DISCRETE EVENT SYSTEMS

with various restrictions or optimization criteria. In the following, we will explore the basics of DESs control within the
framework of state machines and formal languages, as initiated by Ramadge and Wonham. The events are considered
spontaneous and process-generated. The control consists of
forbidding the occurrence of some of the events so as to restrict the behavior of a system to avoid undesirable trajectories. Automatic control is performed by means of another system, which tests the controlled system and acts upon it
according to the available information. Thus, the set of events
can be partitioned into two disjoint subsets: u, containing
the uncontrollable events, and c, containing the controllable
ones. The control is provided by a supervisor or a discrete
event controller (DEC), which has the ability to influence the
evolution of the system by enabling and disabling the controllable events, i.e., by allowing or prohibiting their occurrence,
so as to perform a certain control task. Various control tasks
can be defined: (1) control invariance requires that a specified
predicate remains invariantly satisfied whenever initially satisfied, meaning that the behavior of the system remains confined within specified bounds, (2) region avoidance requires
that the system does not satisfy undesirable predicates when
traversing the state space, and (3) convergence requires that
the system to evolve toward a specified target predicate from
given initial conditions.
The main difficulty in modeling complex processes by
considering all the states and all the events is the combinatorial explosion in the number of their states. A way to
keep the complexity manageable is to use event internalization, or partial observation, which leads to nondeterministic
process behavior. Markov chain representation, or GSMP
models, can be used to describe complex DESs in a formalism that has the capability to relax the requirement that
all states and all event sequences be explicitly in the model.
Other approaches to achieve an effective modeling are
based on the concept of modularity and hierarchy that lead
to structured models of lower complexity in comparison
with the case when all individual components are taken
directly into account.
Controllability and Reachability
Consider a DES modeled by the generator G (Q, , , s,
Qm), where Q is the state space (an arbitrary set), is the
event set (or the alphabet, a finite set), is the evolution law
[a relation on Q Q, which generalizes the transition
function, see comments on Eq. (26)], s q0 is the start (initial)
state, and Qm Q is the set of marker states. As mentioned
before, the marker states were introduced by Ramadge and
Wonham to identify the completed tasks. The set of events
is partitioned into c, the set of controllable events, and
u, the set of uncontrollable events, with c u, c
u 0
.
A state q Q is called reachable from the initial state
s q0, if there exists a path (q01q12 . . . nqn) B(G), such
that qn q, i.e., if there exists w 12 . . . n *, such
that (q0, w, qn) *.
A state q Q is called controllable if there exists w *
and qm Qm, such that (q, w, qm) *.
Correspondingly, a generator is called reachable (controllable) if all the states q Q are reachable (controllable).

A generator is called trim if it is both reachable and controllable.

A generator is called deterministic [see Eq. (18)] if for all
q Q and , there exist at most one state q Q such
that (q, , q) *. In this case, a transition (partial) function
can be defined such that q (q, ), as shown at Eq. (1) and
discussed at Eq. (26).
The control of a DES described by a generator G is provided through a control pattern : 0, 1, defined such
that for a state c, () 1 if is enabled and () 0
if is disabled. For all u, () 1 as these events can
not be disabled. The set of control patterns is denoted by
0, 1.
For each control pattern, a new generator G() (Q, ,
, s, Qm) is obtained, where the controlled evolution relation
is defined by
q, q Q,
:
(q, , q )  (q, , q )  and ( ) = 1

(74)

The set of enabled events, also called the control input, for a
control pattern is given by

e ( ) = {
| ( ) = 1} =
ce ( )
u

(75)

where the control pattern plays the role of the characteristic

function of the set.
As mentioned earlier, u e(), for any control pattern .
The set of feasible events for a state q Q of the generator G() is given by f(q) e().
The set of all control inputs is

e () = {
e ( )| } 2

(76)

The control of G through consists in choosing a specific

when the system is in a certain state q Q, after a certain
sequence of events w L, according to the assumed controlling task.
The choice of a particular control pattern can be
considered itself an event, so that a controlled discrete event
system (CDES) with the generator
G() = (Q,
,  , s, Qm )

(77)

can be defined where the evolution law given by

[q, ( , ), q]  (q, , q ) 

(78)

Example 18. For the single model of a machine shown in

Fig. 2, the control could consist of honoring or turning down
requests to start a new task and passing from idle (I) to working state (W), taking into account the history of machine evolution.
The set consist of two control patterns, namely 0, which
disables the requests
0 (S) = 0, 0 (C) = 0 (B) = 0 (R) = 1
and 1, which enables the requests
1 (S) = 1 (C) = 1 (B) = 1 (R) = 1

DISCRETE EVENT SYSTEMS

For the system in Fig. 4 comprising two simple machines, the

control of one of the machines can be made dependent of the
state of the other (e.g., the second machine accepts requests
only if the first one is down).

c2

627

2
m2

c3

1
m2

m1
c1

Supervision

In the standard control terminology, the generator G plays

the role of the plant, the object to be controlled. The agent
doing the controlling action will be called the supervisor. Formally, a supervisor over is a pair
S = (T, )

m6
c4

(80)

where

[(q1 , q1 ), , (q2 , q2 )] G,S


(81)
(q1 , , q2 )  and (q1 , , q2 )  and ( ) = [(q2 )]( ) = 1
The supervisor has authority only over controllable events.
The uncontrollable events f(q) u that may occur in a state
q of the plant are called disturbances (disturbing events).
Again, in standard control theory terminology T is the observer, while implements the feedback, so that the supervised generator operates in closed loop. Various algorithms
are given in the literature for the synthesis of supervisors
able to achieve different control tasks for deterministic or stochastic DESs.
The supervisor implements a map f: L(G) e specifying
for each observed string of events w L(G) the control input
e() f(w) that must be applied to G. When designing a
supervisor, the objective is to obtain a CDES that obeys the
control constraints imposed by the considered control task.
This means suppressing the undesirable sequences of events,
while restricting as little as possible the overall freedom of
the system.
The behavior of the supervised generator is described by
the language L(G, f) defined by L(G, f), w L(G, f), if
and only if w L(G, f), f(w) and w L(G).
The marked language controlled by f in G is Lm(G, f)
Lm(G) L(G, f), i.e., the part of the original marked language
that is allowed under the supervision. If Qm represents completed tasks, the language Lm(G, f) indicates the tasks that
will be completed under supervision.
The supervisor S can also be modeled as another DES
whose transition structure describes the control action on G.
The following requirements have to be satisfied:
If s L(G, f) then s L(S), and s L(S) only if
f(s). This condition ensures that the transitions disabled

m4

3
c5

c6
m5

(79)

where T is a reachable deterministic generator T (Q, , ,

s0, Qm) and : Q is the map that specifies, for each state
q Q reached by the generator of the supervisor, what control pattern (q) must be applied to G().
If the behavior of G() is used to determine the state of T,
a supervised generator results
(G, S) = [Q Q ,
, G,S , (s0 , s0 ), Qm Qm ]

c7

Figure 19. The cat-and-mouse maze. The cat starts from room 2; the
mouse starts from room 4. The cat and the mouse each use only the
passages labeled c and m, respectively. Control the system by (minimally) forbidding some of the passages (except c7), to prevent the dangerous encounter of the parties.

by the control are not included in the transition structure

of S.
If s L(G, f), s L(G) and f(s), then s L(S).
This condition ensures that a transition possible in G
and allowed by the control is included in the transitive
structure of S.
An event can occur in G S and produce the transition
(q, x) (q, x), only if is possible in both G and S, and
produces the transitions q q and x x. This form of supervision can be obtained from the state realization (S, ) by
trimming the transition structure of S (16).
Consider a DES for which the unsupervised (open loop) behavior is given by a language L. One of the key issues is to
specify the properties of a sublanguage K L that is achievable under supervision. Because the uncontrollable events
continue to occur even for the closed loop (supervised) system,
the prefix closure K of such a controlled language K has to be
invariant under the perturbation of the uncontrollable events.
On the other hand, as K is a restriction of L, not any words
in * containing uncontrollable events can occur, but only
those that are also generated in the open loop conditions (i.e.,
that belong to L). It results that every word that belongs to L
and is composed by a prefix string w K, followed by an
uncontrollable event u (i.e., every word of the form
w L), must also be a prefix string of K, i.e., w K.

c2
1

c1

c7
3

2
c3

m2

c4
c5

c6
4

m1

1
m3
m6

0
m4

3
m5

Figure 20. Generator models for the cat and for the mouse moving
independently in the maze of Fig. 19.

628

DISCRETE EVENT SYSTEMS

door c7 is uncontrollable, u c7, whereas all the other doors

can be opened or closed to control the movement of the cat
and the mouse. As shown earlier (see Figs. 3 and 4 at Example 2), the joint generator model when composing the generators of two subsystems has the state set Q Q1 Q2, and
the event set 1 2. The problem is to find the control
scheme that leaves the greatest freedom of movement to both
parties but that ensures that they (1) never occupy the same
room simultaneously and (2) can always return to their initial
state, i.e., the cat in room 2 and the mouse in room 4. The
first condition forbids the states (i, i), while the second sets
the marker state set Qm (2, 4). To build the generator of
the controlled system, i.e., of the system obeying the constraints, the following pruning steps are performed on the
composed generator model for both the cat and the mouse:

c 1, c 4, c 7, m 6
c 3, m 5
q0

c 2, m 4

q1

Figure 21. The generator of the supervisor for the cat-and-mouse

problem.

Thus, a language K L * is called controllable if

K
u L = K

(82)

Consider now a nonblocking DES with the behavior L(G) and

the marked behavior Lm(G). For any nonempty K L, there
exists a supervisor f such that Lf K if and only if K is a
prefix closed and controllable language. Similarly, for any
nonempty K Lm, there exists a supervision f such that
Lmf K and the closed loop behavior is not blocking
if and only if K is controllable and Lm is closed (i.e., K Lm
K).
Thus it is possible to find a supervisor f so that Lf K
when K is prefix closed and controllable. The proof of this
proposition (18) provides an algorithm for constructing the
state realization (S, ) of the supervisor f from a generator
of the controllable language K. For an arbitrary K *,
the family of controllable sublanguages of K is nonempty
and closed under the set union and has a unique supremal
element K under the partial order of subset inclusion. This
supremal sublanguage (which can be the empty language)
provides an optimal approximation of K by preserving the
restrictions imposed by K, but requiring a minimally restrictive control. Denote by P(*) the set of all languages
over * (the power set of *), and define : P(*)
P(*) by
(J) = K sup[T : T
, T = T, T
u L = J]

1. Delete the forbidden states (i, i)i 0, 1, . . ., 4, that

correspond to the cat and the mouse being in the same
room.
2. Eliminate the edges of the composed graph ending in
the forbidden states, i.e.,
c3

m6

c1

c7

m2

c2

m1

c4

c7

m5

c5

m4

(1, 1), (1, 2) (2, 2), (2, 0) (2, 2), (0, 3)

(3, 3), (1, 3) (3, 3), (3, 4) (3, 3), (3, 4)
(4, 4), (4, 0) (4, 4)
3. Discard the states reachable only from the previously
deleted states, i.e., the states (4, 3) and (2, 1).
4. Remove the states for which the output edges correspond to uncontrollable events (u c7) and lead to
previously deleted states, i.e., the states (1, 3) and
(3, 1).
5. From the resulting graph retain only the trim part, containing the reachable and controllable states.

(83)

j = 0, 1, 2, . . ., with K0 = K

m3

(0, 0), (0, 1) (1, 1)(3, 1) (1, 1), (1, 2)

The supremal sublanguage K is the largest fixpoint of , i.e.,

the largest language satisfying (J) J. The iterations
K j+1 = (K j ),

c6

(2, 0) (0, 0), (4, 0) (0, 0), (0, 1) (0, 0), (0, 3)

(84)

The supervisor can be further simplified by an aggregation

of technique. The result is a supervisor S (T, ), where T is
given in Fig. 21, and the map is given in Table 2. The state
set Q of T is made up of only two states q0, q1. In the initial
state q0 when the cat is in room 2 and the mouse in room
4all the transitions are enabled; in the state q1 when one
of the parties has left its initial roomthe set of transitions
c3, c5, m1, and m5 are disabled. This actually isolates either
the mouse in room 4 (closing c5 and m5) when the cat is out of
room 2 or the cat in room 2 (closing c3 and m1) when the
mouse is out of room 4. It can be noticed that transitions c5,
c6, m1, m2, m3 can no longer occur for the controlled system,
being either directly forbidden, or impossible because of the
restrictions.

converge to K after at most mn steps, where m and n are the

number of states of the generators of L and K, respectively.
Example 19. Consider the famous cat-and-mouse maze (Fig.
19) introduced by Ramadge and Wonham (16), and used as a
typical example of untimed DES control ever since (e.g., see
the attractive Ref. 15). The cat uses only the doors labeled
c1, . . ., c7, whereas the mouse uses only those labeled m1,
. . ., m6. The generator models for the cat and the mouse are
shown in Fig. 20. The state i for either of them corresponds
to the room it occupies, whereas the events correspond to the
transitions i j from one room to another. We assume that

Table 2. Mapping of Supervisor States to Control Patterns for the Cat-and-Mouse Maze Example

c1

c2

c3

c4

c5

c6

c7

m1

m2

m3

m4

m5

m6

(q0 ) 0
(q1 ) 1

1
1

1
1

1
0

1
1

1
0

1
1

1
1

1
0

1
1

1
1

1
1

1
0

1
1

DISCRETE EVENT SYSTEMS

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PAUL DAN CRISTEA

Politehnica University of
Bucharest

DISCRETE EVENT SYSTEMS (DES). See DISCRETE

EVENT DYNAMICAL SYSTEMS.

DISCRETE HARTLEY TRANSFORMS. See HARTLEY

TRANSFORMS.

DISCRETE-TIME ANALOG CIRCUITS. See SWITCHED

CAPACITOR NETWORKS.

631

DISCRETE TIME FILTERS

631

independent variable can be any physical value, for example

distance, it is usually refered to as time. The independent
variable may be either continuous or discrete. If the independent variable is continuous, the signal is called continuoustime signal or analog signal. Most of the signals that we encounter in nature are analog signal, such as a speech signal.
The discrete-time signals are those for which the independent
variable is discrete. The amplitude of both the continuousand discrete-time signals may be continuous or discrete. Digital signals are those discrete-time signals for which the amplitude is discrete, and switched-capacitor signals are discrete-time signals with continuous amplitude. Any operation
on a signal which is performed in order to obtain some more
desirable properties, such as less noise or distortion, is called
signal processing. A system which performs signal processing
is called a filter. Signal processing depends on used technology and can be (1) analog signal processing (ASP) and (2) discrete-time signal processing (DTSP). Prior to 1960, ASP was
mainly used; this means signals are processed using electrical
systems with active and passive circuit elements. ASP does
have some limitations such as (1) fluctuation of the component values with temperature and aging, (2) nonflexibility, (3)
cost, and (4) large physical size. In order to overcome those
limitations, discrete-time technologies are introduced, such as
digital technology and switched-capacitor technologies. Digital technology, which gives many advantages over ASP [see
Kuc (1) for a more detailed analysis], needs to convert an analog signal into a digital form. Processing the signal by digital
technology is called digital signal processing (DSP), and is a
special case of DTSP. In DSP, both amplitude and time are
discrete, unlike switched-capacitor processing where amplitude is continuous.

DISCRETE-TIME SIGNALS AND SYSTEMS

DISCRETE TIME FILTERS

A signal is defined as any physical quantity that varies with
the changes of one or more independent variables. Even that

A discrete-time signal (discrete signal) is defined as a function

of an independent variable n that is an integer. In many
cases, discrete signals are obtained by sampling an analog
signal (taking the values of the signal only in discrete values
of time). According to this, elements of the discrete signals
are often called samples. But this is not always the case.
Some discrete signals are not obtained from any analog signal
and they are naturally discrete-time signals. There are some
problems in finding a convenient notation in order to make
the difference between continuous-time and discrete-time signals, and various authors use different notations [see Rorabaugh (2) for detailed analysis]. Recent practice, introduced
by Oppenheim and Schafer, 1989, (3) uses parantheses () for
analog signals and brackets [ ] for discrete signals. Following
this practice, we denote a discrete signal as x[n] or x[n].
Therefore x[n] represents a sequence of values, (some of
which can be zeros), for each value of integer n. Although the
x-axis is represented as the continuous line, it is important to
note that a discrete-time signal is not defined at instants between integers. Therefore, it is incorrect to think that x[n] is
zero at instants between integers.
Discrete signals can be classified in many different ways.
If the amplitude of the discrete signal can take any value in
the given continuous range, the discrete signal is continuously in amplitude, or it is a nonquantized discrete-time signal. If the amplitude takes only a countable number of discrete values, the signal is discrete in amplitude or a quantized

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

632

DISCRETE TIME FILTERS

discrete-time signal. This signal is also called a digital signal.

If the signal has a finite number of elements, it is finite; otherwise, it is infinite. Therefore, the finite signal is defined for
a finite number of index values n. Unlike an infinite signal,
which is defined for an infinite number of index values n and
can be: (1) right-sided, (2) left-sided, and (3) two-sided. The
right-sided sequence is any infinite sequence that is zero for
all values of n less than some integer value N1. The left-sided
sequence is equal to zero for all n more than some integer
value N2. The infinite sequence which is neither right-sided
nor left-sided is a two-sided sequence. According to their nature, signals can be deterministic and random. The signals
where all values can be determined without any uncertainty
are deterministic. Otherwise, they are random and cannot be
described by explicit mathematical relationships but by using
the probability theory. We consider here deterministic signals
and systems. Schwartz and Shaw (4), Hayes (5), and Candy
(6) consider random discrete signals and systems. A discrete
signal is periodic if the values of the sequence are repeated
every N index values. The smallest value of N is called the
period. A continuous periodic signal does not always result in
a periodic discrete signal.
There are some basic discrete signals which are used for
the description of more complicated signals. Such basic signals are (1) unit sample, (2) unit step, and (3) complex exponential sequences. Unit sample sequence is the finite sequence which has only one nonzero element at the index
n 0,

1 n=0
[n] =
(1)
0 otherwise
It plays the same role in the digital signal processing as the
unit impulse (delta function) plays in continuous-time signal
processing so that the characteristic of a discrete system can
be represented as the response to the unit sample sequence.
Any discrete signal can be presented as the sum of scaled
delayed unit sample sequences,
x[n] =

x[k] [n k]

(2)

k=

Unit step sequence u[n] is the right-sided sequence which is

used to denote the start of any right-sided sequence and is
defined as

1 for n 0
u[n] =
(3)
0 otherwise
Therefore, any sequence x[n], which is zero for n N1, can be
written as

x[n] n N1
x[n]u[n N1 ] =
(4)
0
otherwise

that the frequency for the continuous signal has the dimension radians/sec. For this difference, several notations for the
frequency of the discrete signals and the continuous signals
are being used. The former is usually denoted as and the
latter as . Let the time axis t is divided into intervals
of the length T: t nT. The axes of the discrete time signals
can be understood as obtained from the axis t by dividing
with T: n t/T. Because the frequency and the time are inverse of each other, dividing in the time domain corresponds
to multiplying in the frequency domain. Therefore, the relation between continuous and discrete frequency is the
following:
= T

(6)

Due to the different units of those two values, there are some
important distinctions between them. Continuous frequency
has the values , and has only values from
0 to 2. All other values are repeated with the period 2.
Usually, the discrete frequencies are represented in the interval

(7)

As increases from 0 to , oscillations become higher and

have a maximum at , and going from to 2, they become slower. Therefore, is the highest frequency, and
0 and 2 are the lowest frequencies. Figure 1 shows
how the sequence oscillates more rapidly with the increase of
the frequency from 0 to and more slowly with the increase
of the frequency from to 2.
A discrete-time system (or discrete system) is defined as
the transformation that maps an input sequence x[n] into an
output sequence y[n]:
y[n] = T{x[n]}

(8)

where T presents transformations, or the set of rules for

obtaining the output sequence from the given input one. Depending on transformation a discrete-time system may have
different properties. The most common properties are (1) linearity, (2) time-invariance, (3) stability, (4) memoryless, and
(5) invertibilty. The system is linear if the response to a
scaled sum of the input sequences is equal to the sum of the
responses to each of the scaled input:


T

N

i=1


ai xi [n] =

a1 T{xi [n]}

(9)

i=1

This relation is also known as the superposition principle.

The system is time-invariant if the shift of the input sequence
causes the same shift of the output sequence. In other words,
the properties of the time-invariant system do not change the
time:
T{x[n n0 ]} = y[n n0 ]

(10)

A complex exponential sequence is defined as

e jn = cos(n) + j sin(n)

(5)

By analogy with the continuous-time case, the quantity is

called frequency, and has a dimension in radians. We recall

The systems that are in the same time linear and time-invariant are called linear time-invariant systems (LTI). The system is causal if the values of the output sequence at any index n0 depend only on the values of the input sequence at
indexes n n0. In other words, in a causal system the output

DISCRETE TIME FILTERS

x[n]

x[n]

= 0; = 2

= /4; = 7 /4

x[n]

x[n]

= 3 /4; = 5 /4

633

does not precede the input (i.e., it is not possible to get an

output before an input is applied to the system). Noncausal
systems occur only in theory, and do not exist in this universe. A causal system can be designed by introducing corresponding amounts of delay. The system is stable if a limited
input always gives a limited output. If for a limited input, the
output is unlimited, the system is not stable. Therefore, the
output of an unstable system is infinite with nondecaying values. The system is memoryless if the output y[n] depends only
on the input at the same value n. The system is invertible if
the input sequence may be uniquely determined by observing
the output.

Figure 1. The interpretation of high and low frequencies for a dicrete-time sinusoisal signal. As
increases from zero toward the sequence oscillates
more and more rapidly and as increases from
toward 2, the sequence oscillates more and more
slowly. Therefore the values of in the neighborhood of 0 are low frequencies (slow oscillations),
and those in the vicinity of are high frequencies (rapid oscillations). Due to the periodicity in
general the low frequencies are those in the vicinity
of 2k, k 0, 1, 2, . . . , and the high frequencies are those in the vicinity of 2k, k 0,
1, 2, . . . .

output to any other input sequence may be related with the

unit sample response. In order to answer we use relation (2),
and we obtain

y[n] = T{x[n]} = T


x[k] [n k]

(13)

k=

If the system is linear, the superposition principle (9) can be

used, and therefore, the Eq. (13) can be written as
y[n] =

T{x[k] [n k]} =

k=

x[k]T{[n k]}

(14)

k=

Time-Domain Description
There are two main ways to describe discrete systems in the
time domain. The first one considers only the relation between the input and the output of the system and is generally
named the input-output analysis. The second one, besides the
relation of the input and the output gives also an internal
description of the system, and it is named as a state-space
analysis. Both descriptions are useful in practice and are used
depending on the problem under the consideration (see Ref.
7). A convenient way to present the behavior of the discrete
system is to put the unit sample sequence at the input. If the
system is relaxed initially,
y[0] = 0

(11)

the output y[n] would be the only characteristic of the system,

and it is called unit sample response or shortly impulse response, and is denoted as h[n]:
h[n] = T{[n]}

(12)

A discrete system which has the finite impulse response is

called a finite impulse response (FIR) filter, and one with the
infinite impulse response is known as an infinite impulse response filter (IIR). The question which arises is whether the

From here, we obtain the relation for the linear system:

y[n] =

x[k]hk [n]

(15)

k=

where hk[n] depends on both k and n:

hk [n] = T{[n k]}

(16)

This relation is called the convolutional relationship. This

equation can be simplified for the time-invariant system, using Eq. (10),
y[n] =

x[k]h[n k]

(17)

k=

This relation is called the convolution sum or convolution. It

completely describes the output of an LTI system for the
known input and for zero initial conditions. The operation
convolution between sequences has its own signs *. Therefore,
the convolution (17) can be written as
y[n] = x[n] h[n]

(18)

634

DISCRETE TIME FILTERS

This operation is commutative and distributive [see Kuc (1)

for detailed analysis]. Proakis and Manolakis (7) explain the
computing of the convolution step by step. From the unit sample response, we may see some important characteristics of
the LTI system, such are stability and causality [see Orfanidis (8) for detailed analysis]. An LTI system is stable if and
only if this condition is satisfied:
S=

|h[n]| <

b0

x[n]

y[n]

z1

z1
b1

a1

bNp

aN

(19)

n=

z1

FIR filter has a finite length of impulse response, and the

condition (19) shall always be satisfied, which means that an
FIR filter is always stable. An LTI system is causal if the next
condition is satisfied:
h[n] = 0,

for n < 0

(20)

A natural question which may arise is if we can implement

digital filter by using the convolution. The answer depends on
whether the system is FIR or IIR. In the case of an FIR, the
convolution summation directly suggests how to implement
the filter. The problem arises for an IIR filter which has an
infinite impulse response since it requires an infinite number
of memory locations, additions, and multiplications. The solution is given by introducing the difference equations. Such a
difference equation describes an LTI system having any initial conditions unlike the discrete convolution that describes
the system in which all inputs and output are initially zero
(the system is initially relaxed). The difference equation is
often written in the form

y[n] =

Np

k=Nf

bk x[n k]

ak y[n k]

(21)

k=1

where bk and ak are constant coefficients and Nf and Np are

integer values. The first summation contains past, present,
and future inputs, while the second one contains only past
outputs. The difference equation for FIR filter contains only
the first sum where we can recognize the convolution (17). If
the system is casual, it does not depend on the future values
of the input, and the difference equation has Nf 0. The part
of the right side of the difference equation which involves past
outputs is called the recoursive part, and the other part is the
nonrecoursive one. The system which has only a nonrecoursive part is called the nonrecoursive filter. Otherwise, it is the
recoursive filter. In general, the computation of the output
y[n] at the index n of a recoursive filter needs previous outputs: y[n 1], y[n 2], . . ., y[0]. Therefore in this case, the
output must be computed in an order. As the difference, the
output of the nonrecoursive filter can be computed in any order. An implementation of the casual LTI filter based on the
difference equation (21) and which is called direct form I is
presented in the Fig. 2. We see that the filter consists of an
interconnection of three basic elements: (1) unit delay, (2)
multiplier, and (3) adder. Direct form I is not optimal in the
sense that it uses a minimum number of delaying elements.
Proakis and Manolakis (7) describe different and more efficient structures of discrete systems. Signal-flow graphs are
often used to describe the time-domain behavior of LTI systems [see Haykin (9) for a detailed analysis].

z1

Figure 2. Direct form I realization of the causal LTI filter follows

directly from the difference equation and shows explicitly the delayed
values of input and output. (z1 is interpreted as one-sample delay.)

A state-space approach considers that the output of the

system is the result of the actual input and the set of initial
conditions. This suggests that the system may be divided into
two parts. One part contains memory and describes past history, and the second one describes the answer to the actual
input. Following this approach, Antoniou (10) derived the
state space equations for the system of an order N in the matrix-vector form
q[n + 1] = Aq[n] + Bx[n]

(22)

y[n] = Cq[n] + Dx[n]

(23)

where q[n] is the n-dimensional state vector at time n, and

x[n] and y[n] are the input and output sequences, respectively. The matrices A, B, C, and D, correspond to a particular realization of the filter.
Transform Domain Description
Frequency Domain. The sinusoidal sequences are usually
used in frequency-domain description of discrete signals and
systems because sinusoidal sequences have one useful characteristic which is shown in Eq. (24):
y[n] = H(e j )e jn

(24)

Therefore, if the sinusoidal sequence is applied to the LTI system, the output is also a sinusoidal sequence with the same
frequency, multiplied with the complex value:
H(e j ) =

h[k]e jk

(25)

K =

The sum in Eq. (25) presents Fourier transform of h[n] and is

named as frequency response, as it specifies response of the
system in the frequency domain. The frequency response, being the Fourier transform of the unit sample response, is a
periodic function with the period 2. Therefore, low frequencies are those that are in the neighborhood of an even multiple of , and the high frequencies are those that are close to
an odd multiple of . Equation (24) has also an interpretation
using the eigenvalue and eigenfunction. If an input signal
produces the same output signal but multiplied by a constant,

DISCRETE TIME FILTERS

this signal is called eigenfunction, and the constant is the eigenvalue of the system. Therefore, the complex sinusoidal sequence is the eigenfunction, and H(ejw) is the corresponding
eigenvalue. Fourier transform of the unit sample response
h[n] exists only if the sum [Eq. (25)] converges, that is if the
next condition is satisfied:

|h[n]| <

(26)

k=

The magnitude of H(ej), H(ej), is called magnitude response, and the argument of H(ej) is called phase response
and denoted as ArgH(ej). Therefore, we have
H(e j ) = |H(e j )|e jArg{H (e

j )}

(27)

Frequency response can be expressed by its real and imaginary part:

H(e j ) = HR (e j ) + jHI (e j )

(28)

From here, the magnitude response and phase response can

be expressed as follows:
|H(e )| =
j

HR2

HI2

H(e H (e )
j

Arg{Y (e j )} = Arg{X (e j )} + Arg{H(e j )}

HI (e j )
HR (e j )


(30)

Instead, the linear scale, magnitude characteristic is usually

plotted on the logarithmic scale.
|H(e j )|db = 10 log10 |H(e j )|2 = 20 log10 |H(e j )|

Those changes can be either desirable or undesirable when

they are referred as to the magnitude and phase distortion.
Generally, we may view the LTI as a filter, passing some of
the frequencies of the input signal and suppressing the others. Filters are usually classified according to what frequencies pass and to what frequencies suppress as: (1) lowpass, (2)
highpass, (3) bandpass, and (4) bandstop filters. The ideal filters have constant magnitude response (usually 1) in the
passband and zero magnitude characteristic in the stopband.
The magnitude characteristics of the different ideal filters are
shown in Fig. 3. Ideal filters have the linear phase in the
passband which means that the output is equal to the scaled
and delayed input. Therefore, linear phase causes only delaying of the input sequence, what is not considered as the
distortion and the linearity of the phase is the desirable characteristic. The group delay is introduced as the measure of
the linearity of the phase

(32)

This expression explains why Fourier transform is so useful

in the analysis of LTI. As this expression shows, the operation
of convolution is replaced by a simpler operation of multiplication in the transform domain. This equation also shows that
the input spectrum is changed by the LTI system in both amplitude and the phase. The output magnitude is obtained as
the product of the input magnitude spectrum and the magnitude response:
|Y (e j )| = |H(e j )| |X (e j )|

d[Arg{H(e j )}]
d

(35)

The group delay can be interpreted as the time delay of the

signal components of the frequency , introduced by the filter.
Filters with symmetric impulse response have linear phase
[see Oppenheim and Schafer (3) for detailed analysis]. Ideal
filters are not physically realizable and serve as the mathematical approximations of physically realizable filters. As an
example, we consider in Fig. 4 the magnitude characteristic
of the physically realizable lowpass filter [see Ingle and Proakis (11) for a detailed analysis].

(31)

In order to show better both the passband and the stopband characteristics, the log-magnitude response is plotted on
two different scales: one for the passband and the second one
for the stopband. For an LTI system with a real impulse response, the magnitude and phase responses have symmetry
properties from which follows that the magnitude response is
an even function of , and the phase response is an odd function of .
Oppenheim and Schafer (3) show that the Fourier transform of the output is the product of the Fourier transforms of
the input and the impulse response:
Y (e j ) = H(e j )X (e j )

(34)

(29)

where H*(ej) is the complex-conjugate of H(ej).

Arg{H(e j )} = arctg

The output phase is equal to the sum of the input phase and
the phase response:

() =
j

635

(33)

Z-Domain. Z transform is a generalization of the Fourier

transform that allows us to use transform techniques for signals not having Fourier transform. It plays the same role in
discrete-time signals and systems as the Laplace transform
does in continuous-time signals and systems. Z transform of
the unit sample sequence is called system function:
H(z) = Z{h[n]} =

h[n]zn

(36)

n=

The concept of a Z transform is only useful for such values

of z for which the sum [Eq. (36)] is finite. Therefore, for the
sequence h[n] it is necessary to define the set of z values for
which

|h[n]zn | <

(37)

n=

This set of z values is called the region of convergency (ROC).

Many characteristics of a filter can be seen from ROC. For a
FIR filter, the number of elements in the sum [Eq. (36)] is
finite and, therefore, the problem of the existence of the Z
transform does not exist, and the ROC is all z-plane, except
the origin. Proakis and Manolakis (7) show that ROC for the
right-sided sequence is given by z R1, for the left-sided is

636

DISCRETE TIME FILTERS

H(e j )

H(e j )
Passband

Passband

Stopband

Stopband

Low-pass filter

High-pass filter

H(e j )

H(e j )
Passband

Figure 3. Magnitude characteristics of the different ideal frequency-selective filters. The ideal filters
pass without any attenuation all frequencies in the
passband and completely attenuate all frequencies
in the stopband.

Stopband
0

Passband

Stopband

given as z R2, and for the two-sided sequence as R1

z R2.
The operation of convolution in the time-domain reduces
to the most simple operation of multiplication in the
Z-domain:

Y (z) = Z{y[n]}

Bandstop filter

(38)

Remember that Eq. (38) is valid for LTI systems. The system
function for an important class of LTI systems which are described by the constant coefficients difference equation can be
expressed as the rational function and is expressed as the
ratio of polynomials in z1. By taking the Z transform of Eq.
(21) and using that the delay by k samples in the time-domain
corresponds to the multiplication by zk, we have:

(39)

N p
b zk
k=Nf k
Y (z)
=
H(z) =
N
X (z)
1 + k=1 ak zk

where
X (z) = Z{x[n]}

Passband

Stopband

Bandpass filter

Y (z) = Z{y[n]} = Z{x[n] h[n]} = X (z)H(z)

(40)

[see Proakis and Manolakis (7) for detailed analysis]. The values of z for which H(z) become zero are called zeros, and the
values of z for which H(z) become infinity are called poles.
The zeros are roots of the numerator N(z), and the poles are
roots of the denominators D(z). Both poles and zeros are
named as the singularities of H(z). The plot of zeros and poles
in the z-plane is called a pole-zero pattern. Pole is usually
denoted by a cross and the zero by a circle . We can write
the system function H(z) in the factoring form:

H(e j )
Passband
1+ 1
1
1+ 1

Np +N
H(z) = KzNf k=1
N

(1 zk z1 )

k=1 (1

Transition
band

Stopband

2
p

Figure 4. Magnitude specification of the physically realizable lowpass filter. Instead of sharp transition between passband and stopband, the transition band is introduced, and instead of a flat characteristic, a small amount of ripples is tolerable: In the passband: 1
1 H(ej) 1 1, where 1 is the passband ripple. In the stopband: H(ej) 2, where 2 is the stopband ripple.

pk z1 )

(41)

where zk and pk are the zeros and the poles, respectively, and
K is gain. Kuc (1) shows that each factor in the numerator of
Eq. (41) generates one zero at z zk and one pole at z 0;
each factor in the denominator generates one pole at z pk
and one zero at z 0; factor zNf generates Nf zeros at z 0
and Nf poles at z . For the system function, the total number of poles is equal to the total number of zeros. If pole and
zero are in the same location, they cancel each other. Complex
singularities are always in the complex-conjugate pairs for
the system presented by the difference equations with the
real coefficients.

DISCRETE TIME FILTERS

Pole-zero pattern gives much useful information about the

LTI system. From the polezero pattern, we can see whether
the filter is casual or not. For the casual filter, Nf 0 and
therefore there are no poles in the infinity. Besides causality,
the type of the filter can also be seen from the polezero pattern. For an FIR filter, all singularities are only zeros (except
poles at the origin and possibly in the infinity). Unlike a FIR
filter, an IIR filter has zeros and poles or only poles. (Zeros
are in the origin.) As the system function becomes infinity in
the poles, all poles must be outside the ROC. However, for
a casual right-sided sequence, ROC must be outside of the
outermost pole (the pole having the largest absolute value).
Another useful characteristic about LTI which can be seen
from the polezero pattern is the stability. The problem of
stability is only addressed to the IIRs and, therefore, is connected only with the position of poles. Kuc (1) shows that for
a causal IIR filter, all poles must be inside the unit circle. If
the pole is on the unit circle, the system is not stable.
Oppenheim and Shafer (3) shows that Z transform is equal
to the Fourier transform on the unit circle:
H(e j ) = H(z) z=e j

(42)

In this order, the frequency response belongs to the system

function evaluated on the unit circle. The magnitude response
at 0 can be presented geometrically as the ratio of the
distances between the zeros and the point z0 ej0 on the unit
circle and the distances between poles and the point z0 ej0,
as it is shown in Fig. 5:

Np +N
|H(e j 0 )| = K k=1
N

|(zk , z0 )|

(43)

k=1 |(pk , z0 )|

637

Ingle and Proakis (11) derive geometrical presentation of the

phase response as

arg{H(e j 0 )} = C + ((Np + Nf ) N)0 +

Np +Nf

arg{(zk , z0 )}

k=1

arg{(pk , z0 )}

(44)

k=1

where C is equal 0 or , depending if the real frequency response is negative or not. This expression can be interpreted
as the sum of the constant linear with term and the nonlinear term. We notice that the singularities in the origin do not
affect the magnitude response but affect the phase response.
As shown in Eq. (43), the magnitude response will be equal
to zero at the points corresponding to the zeros on the unit
circle. Similarly, the poles that are close to the unit circle (remembering that these cannot be on the unit circle for a stable
LTI) give the peak value to the magnitude response. Therefore, the singularities that are close to the unit circle dominate the magnitude response, and they are called the dominant singularities.
s-PLANE TO z-PLANE TRANSFORM
The s-plane to z-plane transform depends on the characteristic of the filter we want to preserve in the process of transforming an analog to a digital filter. The most used transforms are impulse invariance transformation, where the
impulse response is preserved, and bilinear transform, where
the system function is preserved.
Impulse Invariance Transformation
The unit sample response of a digital filter is obtained by
sampling the impulse response of the analog filter:

Z-plane

Im

h[n] = hA (nT )

Unit circle
pk

e j o = zo

(45)

where T is the sampling interval. Using Eq. (6) between the

discrete and analog frequency, knowing that the frequency
points in s-plane are
s = jT

Re
zk

(46)

and that those in the z-plane are

z = e j

(47)

z = esT

(48)

we obtain the relation:

Figure 5. Geometric presentation of the Fourier transform in Zplane along the unit circle. The magnitude response at 0 can be
presented geometrically as the ratio of the distances between the
zeros zk and the point z0 ej0 on the unit circle and the distances
between poles pk and the point z0 ej0. If the singularity is close to
the unit circle it is called dominant singularity, because the distances
from it to the neighborhood points on the unit circle are very small.
Therefore the dominant zero decreases and the dominant pole increases the magnitude characteristic at the corresponding frequency.
For every dominant zero on the unit circle, the magnitude characteristic is equal to the zero at the corresponding frequency.

From Eqs. (46)(48), it follows that the part of the frequency

axis in the s-plane from 0 to /T is mapped to the frequency
points on the unit circle from 0 to in the z-plane. In a
similar way, the frequency points from 0 to /T are mapped
to the points on the unit circle from 0 to . Expressing
the complex value z in the polar form
z = re j

(49)

638

DISCRETE TIME FILTERS

and the complex variable s, with real value and imaginary

value
s = + j

(50)

Cf

Rf

in

Ri

in

Ci

we have the relation between r and the real value

(a)

r = e T

We have the next observations: (1) the transform from continuous-time domain to the discrete-time domain is linear, (2)
the mapping is not one-to-one, but many-to-one and (3) the
frequency interval 0 to 2/T maps into the unit circle, and the
strips in the left side of the s plane of width 2/T are mapped
inside the unit circle. The entire left side of the s-plane maps
into the unit circle, which means that the stable analog filter
will result in a stable digital one. Due to the many-to-one
mapping, the aliasing effect is present, and this is the main
disadvantage of the impulse invariance transform.
Bilinear Transform
To overcome the aliasing limitation, the bilinear transform
could be used, as it presents a one-to-one mapping. The system function H(z) is obtained from HA(s) by replacing the s by
s=

2 z1
T z+1

(52)

To find the mapping of the frequencies from to , we set

s j and use Eqs. (49) and (52)

z=e

(b)

(51)

1 + (t/2)2 e jarctg(T /2)

1 + jT/2
=
=
1 jT/2
1 + (T/2) e jarctg(T /2)

Figure 6. Continuous-time amplifiers: (a) resistor based and (b) capacitor based. The small signal voltage gain for the resistor and the
capacitor based amplifiers is Rf /Ri and Ci /Cf, respectively.

rely on the precision of the absolute value of both resistors

and capacitors. In integrated circuits, the tolerances of RC
products can be as high as 30%. In the past, to overcome
this drawback, the resistors were adjusted by using laser
trimming techniques; this approach, however, increases the
cost of the system. In order to increase the precision of the
filters, several techniques have been aroused; the main idea
is to replace the resistor by another device like a switchedcapacitor or a switched-current. Switched-capacitor techniques are discussed in this chapter.
Basic Components of Continuous-Time Filters
Resistors, capacitors, and inductors are the main passive elements of continuous-time filters. The operational amplifiers
are other important elements for the implementation of active RC filters. For the resistor, the voltage to current relationship is given by
i=

(53)

= e2 jarctg(T /2)

1
v
R

(56)

For the inductor, this relationship is

From here follows

i=
= 2arctg(T/2)

2
T
tg
T
2

(57)

(54)

For low frequencies, the transform is approximately linear,

and for higher frequencies, the transform is highly nonlinear,
and frequency compression or frequency warping occurs. The
effect of the frequency warping can be compensated for by
prescaling or prewarping the analog filter before transform,
which means to scale the analog frequency as follows:
 =

1
v
sL


(55)

[See Kuc (1) for a detailed analysis.] The whole left side of the
s-plane is mapped into the inside of the unit circle, and the
right side is mapped outside of the unit circle. Therefore, the
stable analog filter will result in the stable digital filter [see
Proakis and Manolakis (7) for detailed analysis].
DISCRETE-TIME ANALOG FILTERS
During the 1960s and 1970s the analog integrated filters were
implemented by circuits based on resistors, capacitors, and
operational amplifiers; these are denominated RC active filters. The precision of RC filters depend on RC products which

where s is the frequency variable j. For the capacitor, the

voltage-current relationship is given by
v=

1
i
sC

(58)

In the design of complex transfer functions, a basic function

is the voltage amplification; two structures are depicted in
Fig. 6. The inband gain of the amplifiers is given by Rf /Ri
and Ci /Cf , respectively. While the resistor based amplifier is
stable, the circuit of Fig. 6(b) is quite sensitive to offset voltages due to the lack of dc feedback. Active filters are based
on lossless integrators; the typical RC implementation of this
block is shown in Fig. 7.

Cf

in

Ri

Figure 7. Continuous-time integrator. Note that the operational amplifier operates in open loop for dc signals.

DISCRETE TIME FILTERS

connected to a low impedance voltage source, and the other

one is connected to the input of an operational amplifier a
virtual ground. Hence, every clock period, in the case of the
inverting switched-capacitor resistor, the capacitor extract
charge equal to C(v1 v2) or the charge C(v1 v2) is injected
in the case of the non-inverting resistor. In average, the
switched-capacitor simulated resistors are transferring
charges proportional to the clock period leading to the following equivalent resistance

(a)

(b)

Figure 8. Switched-capacitor resistors: (a) series and (b) parallel.

1 and 2 are two nonoverlapping clock phases.

Req
=

If the voltage gain of the operational amplifier, AV, is large

enough, the voltage at the inverting input, given by v0 /AV, is
very small, and this terminal can be considered as a virtual
ground; hence, the current flowing through the resistor is determined by the value of both resistor and input voltage.
Since the input impedance of the operational amplifier is typically very large, the resistor current is injected to the capacitor, and the output voltage becomes

vo (t) = vo (t0 )

1
RiCf

vi (t) dt

(59)

The minus sign appears because the current is injected from

the virtual ground to the output node. As we are interested
in transfer functions, it is easier to manipulate the variables
in the frequency domain; therefore, the previous equation can
be expressed as follows
vo
1
=
vi
sRiCf

vo
C
= i
vin
Cf

(60)

vo
C
= i z1/2
vin
Cf

Building Blocks for Switched-Capacitor Filters

The parasitics-insensitive integrators allow the design of

high-performance analog integrated circuits. Biquadratic
based filters, ladder filters, and other type of filters are based
on active integrators. Switched-capacitor filters have the advantage that arranging the clock phases inverting and noninverting simulated resistors can be realized, as shown in Fig.

1
2

2
(a)

Cf

in

(64)

Switched-Capacitor Integrators

(61)

In switched-capacitor circuits, the resistors are implemented

by a capacitor, four switches and two non-overlapping clock
frequencies; Fig. 8 shows the stray insensitive switched-capacitor simulated resistors. Typically, one of the terminals is

Cf

(63)

where: z1/2 represents the half delay. Other voltage amplifiers can be found in Refs. 1315, 1920.

Herein after, it is assumed that the non-overlapping clock

phases are defined as follows:

2 (t) nT T < t nT T/2

(62)

Note that the amplifier is available during clock phase 1. The

amplifier shown in Fig. 9(b) behaves as the previous one, but
the input signal is sampled at the end of the clock phase 2,
and the charge is injected during the next clock period. Observe that the injected charge is inverted; hence, the voltage
gain is

The differentiator can be implemented by using inductors instead of capacitors or exchanging the role of the resistor and
capacitor in Fig. 7. Nevertheless, these approaches are impractical in most of the cases; the inductors are typically implemented by using integrators as will be shown in the next
section. More details can be found in Refs. 1215.

1 (t) nT T/2 < t nT

1
f ckC

where f ck is the frequency of the clock. Switched-capacitor

based resistors are the key elements for the design of
switched-capacitor filters; with these elements, voltage amplifiers, integrators, resonators, filters, and other type of functions can be implemented; more applications can be found in
Refs. 13, 15, 1920. The simplest voltage amplifier is the circuit of Fig. 6(b); other voltage amplifiers are shown in Fig. 9.
Observe that Cf and Ci are sharing several switches. In Fig.
9(a), during the clock phase 2, the operational amplifier is
shortcircuited, and the capacitors are discharged. During the
next clock period, the input capacitor is charged to Ci vin, and
the current needed for this charge flows through the feedback
capacitor; therefore, the gain voltage becomes

t
t0

639

2
o

in

2
1

2
(b)

2
o

Figure 9. Switched-capacitor amplifiers available

during clock phase 1 (a) inverting and (b) noninverting. Because the operational amplifier is shortcircuited during 2, the output is available only during the clock phase 1.

640

DISCRETE TIME FILTERS

Cf

Cf

Figure 10. Switched-capacitor integrators: (a)

inverting and (b) noninverting. The inverting
and noninverting integrators employ the series
and parallel switched-capacitor resistors, respectively.

in

Ci

vo (t) = vo (nT T )

(65)

In the next clock period, Ci extracts a charge equal to Ci vin;

therefore, the charge distribution can be described by the following expression
Cf vo (t) = Cf vo (nT T/2) Ci vin (t)

(66)


C
vo 
1
= i
vin 
Cf 1 z1

(67)

Note that the output voltage can be sampled during the next
clock period; then the output voltage is delayed by a half period, leading to the following transfer function


C z1/2
vo 
= i

vin
Cf 1 z1

(68)

2
Cf

in

Ci2

(b)

A similar analysis for the non-inverting integrator leads to

the following transfer functions:


C z1/2
vo 
= i

vin
Cf 1 z1

(69)


Ci z1
vo 
=
vin 
Cf 1 z1

(70)

First-Order Filters
The amplifiers and integrators can be easily implemented by
using switched-capacitor circuits; a general first order filter is
shown in Fig. 11. By using adequate equations, we can see
that the z-domain output-input relationship is described, during the clock phase 1, by the following expression:

(71)
where the left hand side term represents the charge contribution of Cf . The first right hand side term is due to capacitor
Ci1. Note the term 1 z1 present in the non-switched capacitors; these terms appear as the injected or extracted charge
is the difference between the actual one minus the previous
clock period charge. The other terms represent the charge
contribution of the Ci2, Ci3, and Cf2, respectively. In order to
facilitate the analysis of complex circuits, it is convenient to
represent the topologies with the help of flow diagrams; see,
for example, Ref. 20. Note that the output voltage is feedback
by the capacitor Cf2; this capacitor is considered in a similar
way as the other capacitors. Solving the circuit, or equivalently, arranging Eq. (71), the z-domain transfer function can
be found as


(1 z1 )Ci1 Ci2 + z1/2Ci3
v0 



=

Cf
vin
(Cf + Cf2 ) 1
z1
1
Cf + Cf2

Cf2

(1 z1 )Cf vo = (1 z1 )Ci1 vin Ci2 vin + z1/2Ci3 vin Cf 2 vo

If the output voltage is evaluated at the end of the clock

phase 1, and considering that v0(nT T/2) is equal to
v0(nT T), the z-domain transfer function will result in

Ci3

Ci

(a)

8. As a result of this, the design of systems can be further

simplified. The inverting and non-inverting integrators shown
in Fig. 10 are an example of this advantage. For the implementation of an RC noninverting integrator, an additional inverter is needed.
The inverting integrator operates as follows. During the
clock phase 2, Ci is discharged while the output voltage remains constant due to Cf ; the output voltage is then characterized by the next equation

in

Ci1

Figure 11. General first-order switched-capacitor filter. Ci1, Ci2, and

Ci3 implement an amplifier, an inverting integrator, and a noninverting integrator, respectively. Cf2 implements a switched-capacitor
resistor in parallel with C.

(72)

If the output voltage is sampled during 2 and assuming that

vin changes neither during the transition 1 2 nor during
the clock phase 2, we can observe that the output of the first
order circuit becomes
v0 | = z1/2v0 |
2

(73)

In the first-order filter of Fig. 11, we can note that all

switches connected to the inverting input of the operational
amplifier have been shared by several capacitors as all of
them are connected to ground during 2 and to the operational amplifier during clock phase 1.

DISCRETE TIME FILTERS

641

1
o

CR

+
C

CR

Figure 12. LC resonator: (a) passive and (b)

switched-capacitor implementation. The inductor
L is simulated by the switched-capacitor resistors,
the bottom operational amplifier and the bottom
capacitor C.

(b)

(a)

Active Resonator
Ladder filters are based on LC networks, series and parallel
connected. While the capacitors are easily implemented in
metal-oxide-semiconductor technologies, the inductor must be
simulated by integrators and resistors. The inductors current-voltage relationship is given by Eq. (57). For a grounded
resonator as shown in Fig. 12(a), the conductors current can
be generated from the output node and an integrator. The
transfer function of an RC integrator is given by 1/sRC; if
an integrators output is converted to current by a resistor,
and the resulting current is fed back to the node v0, the resulting current is then given by vo /sR2C. Hence, the simulated
inductance results in
L = R 2C

(74)

Figure 12(b) shows the switched-capacitor realization of the

resonator. For a high sampling rate ( f ck frequency of operation), the switched-capacitor resistors can be approximated by
R 1/f ckCR; for details, the reader may refer to Refs. 1215,
1920. According to Eq. (74), the simulated inductance is approximately given by
L=

1 C
2 C2
f ck
R

to component tolerances in the passband; see Refs. 1417. A

general biquadratic filter is shown in Fig. 13. The z-domain
transfer function of the topology is given by

H(z) =

A2 A5 z + (z 1)(A1 A5 + A4 z) + A3 (z 1)2

2 A (A + A ) + A  1 A A 

5
6
7
8
5 6
(1 + A8 ) z2
z+
1 + A8
1 + A8
(76)

By using this structure, several transfer functions could be

implemented, namely

A1
4A2 A5
A2
A1
A2
A1

= A3 = A4 = 0
= A3 , A1 = A4 = 0
= A3 = A4 = 0 or
= A3 = A4 = 0
= A3 = 0, A1 A5 = A4
= A2 = A4 = 0

Low-pass filter (LDI)

Low-pass filter (Bilinear)
Bandpass filter (LDI)
Bandpass filter (Bilinear)
High-pass filter

In order to illustrate the design procedure, consider a second

order bandpass filter with the following specifications:
Center frequency
Bandwidth
Clock frequency

(75)

10 kHz
1 kHz
60 kHz

Observe that in the LC implementation, similar integrators

have been used.
A7C2

HIGH-ORDER FILTERS
High-order filters can be synthesized by using several approaches; two of the most common are based on biquads and
the emulation of ladder filters. High-order filters based on biquadratic sections are more versatile, but ladder filters present low sensitivity to components tolerances in the passband.

A4C2

A2C1

1
2

in
A1C1

A3C2

A6C1

C1

2 A5C2 1
1

1
C2

Second-order Filters
Second order filters are often used for the implementation of
high-order filters; these filters are versatile in the sense that
the filter parameters like center frequency, bandwidth, and
dc or peak gain are controlled independently. A drawback of
the biquadratic filters is that they present high sensitivity

A3C2
Figure 13. General second-order switched-capacitor filter. By choosing appropriated coefficients either lowpass, bandpass, highpass, or
notch filters can be implemented.

642

DISCRETE TIME FILTERS

i1

in

L1

R1
Figure 14. Passive sixth-order bandpass filter:
(a) detailed RLC prototype and (b) simplified schematic. The element values can be obtained from
well-known tables; see, for example, Ref. 12.

L2

C1
L2

C2

i1

o
C1

in
Y1

R1

i3

o
Y3

Z2

Z4

(b)
(a)

The continuous-time bandpass filter has the following

form:
H(s) =

i3

V2

BWs
s2 + BWs + 02

(77)

where 0 is the center frequency, equal to 2f 0, and BW the

filter bandwidth. In low Q applications, it is more precise to
prewarp the center frequency and the 3 dB frequencies; this
prewarping scheme is discussed in (18). By using the bilinear
transform, the prewarped center frequency is f 0 11.0265
kHz, and the 3 dB frequencies are mapped into 10.37 kHz
and 11.7 kHz. Applying the s-domain to z-domain bilinear
transform to the continuous-time bandpass filter, the following z-domain transfer function is obtained:

BWT
2
H(z) =

T 2
BWT
0
+
1+
2
2
(z 1)(z + 1)

T 2

T 2
BWT
0
0
+
1

2 + 2
2
2
2

2
z +
z+

T 2

T 2

BWT
BWT
0
0
+
+
1+
1+
2
2
2
2
(78)
Using the prewarped values and equating the transfer function of the bilinear bandpass filter, Eq. (72) with appropriated
conditions, and the previous equation, the capacitor ratios are
found: A1 A4 0.04965, A5 1, A6 0.09931, A7 0.95034,
A8 0.

age and current Kirchhoff s laws. Although this topic is

treated in another chapter, here we consider an example to
illustrate the design procedure of switched-capacitor ladder
filters. Consider a third order, normalized, lowpass filter. For
the design of a bandpass filter, the low-pass to bandpass
transformation must be used; this transformation has the
form
slp

sbp
BW

02
sbp BW

(79)

where BW and 0 are the bandwidth and center frequency of

the bandpass filter, respectively. Observe that the inductor is
mapped into a series of another inductor and a capacitor,
while the capacitor is transformed into another capacitor in
parallel with an inductor. The bandpass filter prototype and
a simplified schematic are shown in Figs. 14(a) and 14(b), respectively. The transformed elements are then given by

LLP
BW
BW
C1 =
LLP 02
L1 =

BW
L2 =
CLP 02
C2 =

(80)

CLP
BW

Current i1 could be generated by the active circuit of Fig. 15.

By using circuit analysis, i1 could as well be obtained as
i1 =

1
R2QY11

(vin v2 )

(81)

Ladder Filters
Active ladder filters are based on the simulation of the passive components of low-sensitive passive prototypes. The active implementation of this type of filters is based on the volt-

in

RQ

Y11

Z22
i1

2
RQ

RQ

Figure 15. Active implementation of floating impedances. The admittance Y11 is directly associated with the floating impedance Z1.
Resistors RQ are scaling factors.

Equating i1 of the passive realization with the simulated current, the relationship between Y1 and Y11 can be determined
Y1 =

1
1
= 2
Z1
RQY11

(82)

This expression means that the impedance Z1 is simulated by

the admittance Y11 multiplied by the factor RQ2 . For the bandpass filter, Z1 is the series of a resistor, an inductor, and a
capacitor; this impedance can be simulated by the parallel of
similar elements. For grounded resonators, the capacitors are
connected to the operational amplifier, and the inductors are
simulated by using integrators and resistors, as previously
discussed. In the implementation of the 6th order bandpass
filter, three resonators are being employed, one for each LC
resonator.

DISCRETE TIME SYSTEMS DESIGN METHODS

BIBLIOGRAPHY
1. R. Kuc, Introduction to Digital Signal Processing, New York:
McGraw-Hill, 1988.
2. C. B. Rorabaugh, Digital Designers Handbook, New York:
McGraw-Hill, 1993.
3. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1989.
4. M. Schwartz and L. Shaw, Signal Processing: Discrete Spectral
Analysis, Detection, and Estimation, New York: McGraw-Hill,
1975.
5. M. H. Hayes, Statistical Digital Signal Processing and Modeling,
New York: Wiley, 1996.
6. J. V. Candy, Signal Processing: The Modern Approach, New York:
McGraw-Hill, 1988.
7. J. G. Proakis and D. G. Manolakis, Digital Signal Processing,
Principles, Algorithms, and Applications, 2nd ed., New York: Macmillan, 1992.
8. S. J. Orfanidis, Introduction to Signal Processing, Englewood
Cliffs, NJ: Prentice-Hall, 1996.
9. S. Haykin, Modern Filters, 2nd ed., New York: McGraw-Hill,
1990.
10. A. Antoniou, Digital Filters Analysis and Design, New York:
McGraw-Hill, 1979.
11. V. K. Ingle and J. G. Proakis, Digital Signal Processing Using
MATLAB V.4, Boston: PWS Publishing, 1977.
12. L. P. Huelsman and P. E. Allen, Introduction to the Theory and
Design of Active Filters, New York: McGraw-Hill, 1980.
13. P. E. Allen and E. Sanchez-Sinencio, Switched-Capacitor Circuits,
New York: Van Nostrand, 1984.
14. R. Gregorian, K. Martin, and G. C. Temes, Switched-capacitor
circuit design, Proc. IEEE, 71 (8): 941966, 1983.
15. R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits
for Signal Processing, New York: Wiley, 1986.
16. K. Martin, Improved circuits for the realization of switched-capacitor filters, IEEE Trans. Circuits Syst., 27 (4): 237244, 1980.
17. E. Sanchez-Sinencio, J. Silva-Martinez, and R. L. Geiger, Biquadratic SC filters with small GB effects, IEEE Trans. Circuits Syst.,
32 (10): 876884, 1984.
18. K. R. Laker and W. Sansen, Design of Analog Integrated Circuits
and Systems, New York: McGraw-Hill, 1994.
19. Wai-Kai Chen (Editor-in-Chief), The Circuits and Filters Handbook, Boca Raton, FL: CRC Press, 1995.
20. D. A. Johns and K. Martin, Analog Integrated Circuit Design, New
York: Wiley, 1997.

JOSE SILVA MARTINEZ

GORDANA JOVANOVIC-DOLECEK
Instituto Nacional de Astrofisica,
Optica y Electronica, INAOE

DISCRETE-TIME FILTERS. See DIGITAL FILTERS.

643

682

DISTRIBUTED AMPLIFIERS

DISTRIBUTED AMPLIFIERS
DEFINITION AND STRUCTURE
The objective of this article is to present various aspects of
distributed amplifiers. Distributed amplifiers are, by definition, electronic amplifiers consisting of distributed circuit parameters. Distributed circuit is a transmission line circuit,
and the physical length is comparable to operating wavelength. However, in practice, an amplifier system consists of
a number of discrete amplifiers associated with distributed
parameter circuits, often termed the distributed amplifier.
The latter amplifier is actually a pseudo-distributed amplifier.
In practice, the distributed parameter circuit often takes
the form of a transmission line. The circuit parameters, the
inductance, the capacitance, and the resistance are distributed throughout the transmission line. If the transmission
line is a conventional passive transmission line, the electrical
output power of the transmission line is either equal to or less
than the electrical input power, depending on the power loss
of the transmission line.
If the transmission line is active, then the output power is
greater than the input. In this case, the transmission line is
considered as an amplifier. This is a distributed amplifier.
For example, an ordinary optical fiber cable is a passive
transmission line for lightwaves. The output light of the optical cable is always less than the input light due to the cable
loss. However, an erbium-doped optical fiber cable is different. The lightwave output of the cable is larger than the
lightwave input. The input lightwaves, which are electromagnetic waves, are amplified. The erbium-doped optical fiber caJ. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

DISTRIBUTED AMPLIFIERS

Continuous Active Diode Distributed Amplifiers

Active transmission line

Input

Output

Active substrate
(a) Distributed amplifier
Discrete amplifiers

Input

Output
Transmission line
(b) Pseudo-distributed amplifier

Figure 1. Generic configuration of distributed amplifiers. Signals to

be amplified are fed at the left terminal. The signals are amplified
during propagation on the line. The amplified signals exit from the
right. (a) Distributed amplifier. The amplifier consists of a continuous
active transmission line. (b) Pseudo-distributed amplifier. Lumped
amplifiers are periodically loaded on a passive transmission line.

ble is an active transmission line and it is one type of distributed amplifier. A schematic diagram of a generic distributed
amplifier is shown in Fig. 1(a). In this distributed amplifier,
the transmission line is continuously loaded by the continuously distributed power-pumping active substrate.
In a pseudo-distributed amplifier, a number of discrete amplifiers are periodically loaded as shown in Fig. 1(b). The input power is amplified by these discrete amplifiers. Therefore,
the output of the transmission line is greater than the input
power.
The objective of the distributed amplifiers is to obtain a
wide-frequency bandwidth with high amplification gain. The
operating frequency ranges comprise radiofrequency (RF), microwaves, and lightwaves. Depending on the operating frequency range, the amplifier configurations differ significantly.
The transmission line can be a two-wire line, a coaxial line, a
waveguide, a microstripline, a coplanar waveguide, or an optical fiber cable.
The term distributed amplifier contrasts against the terms
discrete amplifier and lumped amplifier. A lumped amplifier
is represented in a block diagram as shown in Fig. 2. In a
lumped or discrete amplifier, point A is the input, point B is
the output, and the geometrical distance between points A
and B is negligibly small in comparison with the operating
wavelength. A distributed amplifier can also be represented
by a block diagram as shown in Fig. 2, but the geometrical
distance between actual point A and actual point B is comparable to the operating wavelength.

683

Figure 2. A block diagram representation of a discrete amplifier, a

lumped amplifier, or a distributed amplifier. A generic symbol of a
generic amplifier. G represents the gain of the amplifier. It can be the
voltage, current, or power gain. A is the input, and B is the output
terminal.

Activated or properly biased tunnel diodes, Gunn diodes, and

varactor diodes are considered to be active diodes. When tunnel diodes and Gunn diodes are properly biased, these diodes
exhibit negative resistance. Ordinarily a resistance is positive. A positive resistance consumes electrical energy. A negative resistance generates electrical energy. Therefore, if the
amount of negative resistance is adjusted by material composition, configuration and the bias current, and if the circuit
impedance of the transmission line is properly adjusted, then
the active diode-loaded transmission line can amplify propagating electromagnetic waves on the transmission line. One
possible biasing method is illustrated in Fig. 3(a). The transmission line is most likely a microstripline or a coplanar coupled waveguide. The microstripline is dc biased through an
RF choke. If the active substrate is a tunnel diode of long
degenerate or heavily doped pn junction, the properly forward
biased pn junction exhibits negative resistance by the tunnel
effect (1). If the active substrate is a long Gunn diode of properly doped n-type GaAs, the substrate exhibits negative resistance by the carrier momentum transfer effect (2).
The negative resistance can also be created by a properly
biased and pumped long varactor diode junction. The varactor
diode is a reverse biased pn-junction diode. This is a variable
capacitance diode and the junction capacitance is varied depending on the bias voltage across the diode. The junction
capacitance in the case of Fig. 3(b) is controlled by the dc bias
and the pump oscillator voltage launched on the microstripline transmission line. Some varactor diodes work without dc
bias. For optimal results, the pump oscillator frequency f p is
approximately twice that of the signal frequency f s. When the
pump oscillator frequency and phase are properly adjusted,
the energy of the pump oscillator transfers to the signal
through the variable junction capacitance and the signal
waves are amplified as the waves propagate on the microstripline. The amplifier that functions by using a junction capacitance is termed a varactor parametric amplifier (1). The
type of parametric amplifier shown in Fig. 3(b) is a traveling
wave varactor parametric amplifier. Because the junction capacitance is continuously distributed along the microstripline,
this is a distributed amplifier.
The pump oscillator wavelength and phase are adjusted.
The pumping waves are synchronized with the input signal
so that the junction capacitance of the varactor transmission
line is always minimum where the signal voltage wave traveling is maximum.
Periodically Loaded Active Diode Distributed Amplifiers
A schematic diagram of a periodically loaded active diode microstripline distributed amplifier is shown in Fig. 4(a). The
active diodes are either discrete tunnel diodes or Gunn diodes. Periodicity L is usually less than a quarter wavelength
in order to avoid resonance. When the periodicity is made
equal to either a quarter or a half wavelength the amplifier
will be at resonance. In such cases, the frequency bandwidth
narrows. It then may become unstable and oscillate. Resonance should therefore be avoided. One of the objectives of the
distributed amplifier is to obtain a wide frequency bandwidth.
Therefore it is safe to keep periodicity L at less than a quarter
of a wavelength. The diodes must be correctly dc biased in the
middle of the negative resistance region.

684

DISTRIBUTED AMPLIFIERS

Dc bias
supply
Microstripline

Microwave
RF
output

RFC

Microwave
RF input

Active subtrate
Ground plate
Tunnel diode junction or
Gunn diode subtrate
(a)
Variable
phase-shifter
Microstripline
Microwave
RF
input

Microwave
RF
output

RFC
N

Figure 3. Continuous diode distributed amplifiers.

Electromagnetic waves to be amplified are fed from the
left end, and amplified signals exit at right. (a) Continuously loaded tunnel diode or Gunn diode transmission
line distributed amplifier. The entire transmission line
consists of a long and narrow section of tunnel diode
junction or Gunn diode active region. (b) Continuously
loaded varactor diode transmission line parametric distributed amplifier. The entire section of the transmission
line consists of a reverse-biased variable capacitance
PN junction.

Varactor diode junction

P

Ground plate
Low-pass filter
High-pass filter

fs

fp

Low-pass filter

Pump oscillator
(b)

Periodicity
Microwave
RF
input

RFC

Microstripline
L

Ground plate

Microwave
RF
output

Discrete diodes

(a)
Microstripline
Variable
phaseshifter
Figure 4. Periodically loaded active diode distributed
amplifiers. (a) Periodically loaded active diode microstripline distributed amplifier. A microstripline is periodically loaded by active diodes with periodicity L. A
properly biased active diode is capable of amplifying
electromagnetic signals. (b) Periodically loaded active
capacitive parametric distributed amplifier. A microstripline is loaded periodically by properly biased and
pumped varactor diodes with periodicity L. Such varactor diode acts as a lumped amplifier.

Microwave
RF
input

RFC
L

fp

Microwave
RF
output

fs

HPF
LPF
Pump oscillator

Ground plate

(b)

Varactor
diodes

LPF

yy
;;
Coupled
waveguide
conducting
strips

Quarter
wavelength
choke

Lumped
diodes

Figure 5. An example of a coplanar coupled waveguide distributed

amplifier. This is an example of a case in which the transmission
line is a coplanar coupled waveguide. Lumped diodes are mounted on
it periodically.

A schematic diagram of a periodically loaded variable capacitance diode (varactor diode) parametric distributed amplifier is shown in Fig. 4(b). As seen from the diagram, varactor
diodes are reverse biased by the dc bias supply and are
pumped by the pump oscillator. Pump frequency f p must be
approximately twice that of the signal frequency f s to be amplified. The pump wave on the line must be synchronized with
the signal wave. Synchronization is accomplished using a
variable phase shifter as shown in the pump oscillator circuit.
The pump oscillator power is transferred into the signal
through the varactor and the signal wave is amplified (1,2).
The varactor diodes are pumped so that when and where the
signal waves crest the junction capacitance becomes minimum. This phasing amplifies the microwave signal voltage.
The transmission line can be a microstripline as shown in Fig.
4(b) or a coplanar coupled waveguide. An example of a coplanar coupled waveguide distributed amplifier is sketched in
Fig. 5. As seen from this figure, fabrication of a coplanar coupled waveguide amplifier is easier than the microstripline
amplifiers.
Continuous Transistor Distributed Amplifiers
A schematic diagram of a continuous transistor distributed
amplifier is shown in Fig. 6. This is a field effect transistor
(FET) of long configuration. Line length must be greater than
the wavelength of the operating carrier signals. The microwave input signals are fed into the coplanar coupled wave-

;;
yy
;;
yy

Intrinsic
semiconductor
substrate
Drain strip

RFC

Input

Source strip

Drain
dc
supply

Output

685

Drain-gate
coplanar
coupled
waveguide

Microwave
output

Microwave
input

Dielectric substrate

VD

;;;
yyy
;;;
yyy

DISTRIBUTED AMPLIFIERS

Discrete
transistors
(FET)

Periodicity

Gate-source
coplanar
coupled
waveguide

Gate
dc
supply

Figure 7. A schematic diagram of a periodically loaded transistor

distributed amplifier. Discrete transistors are periodically loaded on a
coplanar coupled waveguide. The input signals fed on the gate-source
coplanar coupled waveguide are amplified as propagation on the line.
The amplified output appears on the drain-gate coplanar coupled
waveguide. The output propagates on the line and exits from the
right.

guide, which consists of the gate strip and the source strip. As
the input microwaves propagate along this input gate-source
coplanar coupled waveguide, the amplified signal waves appear on the drain-gate coplanar coupled waveguide. Then the
amplified microwaves exit at the end of the drain-gate coplanar coupled waveguide. The long transistor must be properly
dc biased as shown in Fig. 6.
Periodically Loaded Transistor Distributed Amplifiers
A schematic diagram of a periodically loaded transistor distributed amplifier is shown in Fig. 7. To be qualified as a distributed amplifier, the length of a coplanar coupled waveguide
must be longer than the wavelength of operating microwaves.
If the length is very short it indicates simple parallel operation of the transistors. The input microwave signals are fed
to the input of the gate-source coplanar coupled waveguide as
shown in Fig. 7. As microwaves propagate down the gatesource waveguide, the amplified microwaves appear on the
drain-gate coplanar coupled waveguide. The amplified microwaves propagate toward the output and exit from there. The
coplanar coupled waveguides are periodically loaded by discrete field effect transistors. Periodicity L must be less than
a quarter of a wavelength to avoid resonance. Otherwise,
n(l /2) L (2n 1)(l /4) where l is the transmission line
wavelength and n 0, 1, 2, 3, . . ..

VG

Gate strip

Figure 6. A schematic diagram of a continuous transistor distributed amplifier. This is a case of an extremely long gate field effect
transistor. The length of the gate can be several wavelengths longer
than the operating wavelength. As the input signals propagate on the
gate-source line, the amplified output signals travel on the drain-gate
line. The amplified signals exit at the right.

Thermionic Traveling Wave Distributed Amplifiers

A thermionic traveling wave amplifier, also called a traveling
wave tube amplifier (TWTA), is a vacuum tube (2). Electrons
are emitted from an electron gun into a vacuum as shown in
Fig. 8. The emitted electrons are pulled by the anode (a helical transmission line) and focused by the longitudinally applied dc magnetic flux B. The electron beam is shot through
the helix line and hits at an end-plate called an electron collector. The electron collector collects used-up electrons. The

686

DISTRIBUTED AMPLIFIERS

lightwave is propagating in the fiber cable, the signal

lightwave is intensified by the emission of radiation from the
erbium atoms that are pumped by the lightwave (propagating
in the fiber cable) from the pump laser. The pump lightwave
travels with the signal lightwave and pumps the energy into
the signal lightwaves through the stimulated emission of radiation from erbium atoms. This particular optical fiber is
considered to be a distributed parameter transmission line
amplifier for propagating optical electromagnetic wave
signals.

Microwave
output

Microwave
input

RFC

Electron
gun

Electron
beam

Va

Electron
collector

Figure 8. A schematic diagram of a thermionic traveling wave distributed amplifier. The pitch of the helical transmission line is adjusted so that the axial speed of microwave propagation on the line
is almost equal to the speed of the electron beam. Under this condition, the kinetic energy of electrons is transferred into the traveling
microwaves on the line, and the propagating microwaves are amplified.

helix transmission line is a distributed parameter transmission line. The pitch angle of the helix transmission line, the
diameter of the helix, and the electron acceleration voltage
are adjusted in such a way that the speed of the electron
beam is equal to the axial propagation speed of microwaves
on the helix transmission line. Then the kinetic energy of the
electron beam is transferred to the microwave energy on the
helical line through the distributed capacitance between
the electron beam and the helical line. As the microwaves on
the line and the electrons in the beam travel together, the
microwaves are amplified and exit from the output of the tube
as shown in Fig. 8 (2). The helical transmission line can be
replaced by a meanderline or an interdigital transmission
line (2).
Fiber Optic Distributed Amplifiers
A schematic diagram of a fiber optic distributed amplifier is
shown in Fig. 9. The main part of this amplifier is a section
of erbium-doped optical glass fiber cable (3). As seen from this
figure, if a lightwave of proper wavelength is pumped into the
fiber cable through a directional coupler from a pump laser,
and the lightwave signal to be amplified is fed into the input
of the fiber cable through an isolator, then while the signal

GENERAL GOVERNING EQUATIONS

Gain
A generic configuration of a distributed amplifier transmission circuit is shown in Fig. 10. In this diagram, R is the series resistance per meter of the distributed amplifier, L is the
series inductance per meter of the distributed amplifier, G
is the negative conductance per meter of the distributed amplifier, and C is the capacitance per meter of the distributed
amplifier. The amplification constant of this amplifier is (1),

(CR LG)
1/2 [neper/m] (1)


2
2
2 (2 LC + RG) + (CR LG)
+(RG + 2 LC)2


where G is the magnitude of the negative conductance parameter. In a distributed amplifier, if the propagating power increase per meter is P(W/m) and the propagating voltage increase parameter is V(V/m), the magnitude of the negative
conductance per meter is G 2P/(V)2 (S/m).
The phase constant of this amplifier is (1),



 2
( LC +RG) + 2 (CRLG)2 + (2 LC +RG)2 1/2
[rad/m]
=

2
(2)
If the length of the active region of the amplifier is m long
then the voltage gain of the amplifier is
A = 

Optical
isolator
Lightwave
input

Amplified
lightwave
output

Input
connector

The total phase shift across the active region of the amplifier
is
 = 

Output
connector

Pump
laser
Directional
coupler

Optical
isolator

Erbium doped
optical fiber
cable

Figure 9. A schematic diagram of a fiber cable lightwave distributed

amplifier. Active part is a long section of erbium-doped fiber cable.
The erbium atoms are pumped by a light from the pump laser at left.
The input lightwave signals are amplified by the stimulated emission
of radiation from the pumped erbium atoms in the active fiber cable.

(3)

[neper]

(4)

[radian]

L
Output

Input

Figure 10. An equivalent circuit of a generic distributed amplifier.

The negative conductance G generates energy and amplifies signals
which are traveling on this line.

DISTRIBUTED AMPLIFIERS

Frequency Bandwidth

where Ap is given by

In a generic distributed amplifier, the circuit parameters R,

L, C, and G, are functions of operating frequency f. Therefore,
the voltage gain of the amplifier is

A( f ) = ( f )
=

687

2 ((2 f )2 L( f )C( f ) + R( f )G( f ))


1/2
(2 f )2 (C( f )R( f ) L( f )G( f ))2
+
+(R( f )G( f ) + (2 f )2 L( f )C( f ))2
(5)

At the edge of the frequency bandwidth at a frequency f,

(7)

According to the IEEE Standard Dictionary of Electrical and

Electronics Terms (4), sensitivity is defined as the minimum
input signal required to produce a specified output signal having a specified signal to noise ratio. This means that

So
No

No
KTBAp

(14)

where No is the noise output of the amplifier (W). For a distributed amplifier, both the frequency bandwidth B and the
power amplification A are given by Eqs. (6) and (7), respectively.

A range of input signal level in which the gain of the amplifier

is constant is termed the dynamic range of the amplifier. Usually, the gain of an amplifier is less at an extremely small
input signal level or at a large input signal level.
In semiconductor distributed amplifiers, thermionic distributed amplifiers, or even in fiber optic distributed amplifiers, the values of L, C, R, and G are inherently functions of
operating signal levels s. Therefore, in Eq. (1),

(s ) =

(C(s )R(s ) L(s )G(s ))



2 (2 L(s )C(s ) + R(s )G(s ))


1/2
2 (C(s )R(s ) L(s )G(s ))2
+
+(R(s )G(s ) + 2 L(s )C(s ))2
(15)

(9)

If the gain constant in the linear region of the distributed

amplifier is 0, then the power gain of the amplifier is
Ap0 = e2 0 

(10)

is used for the definition of the sensitivity of the amplifier.

Then, the sensitivity is


Ps 
= KTBF
(11)

(17)

where (s) is given in Eq. (15).

If the gain compression of n dB is chosen, then,
n[dB] = 10 log10

A(s )
A0

(18)

or

S o /No =1

For a distributed amplifier, the value of B is obtained using

Eq. (7). The value of the noise figure F can be obtained from
the next section. Then the sensitivity is


No
Ps 
=
(12)
Ap
S o /No =1

(16)

where is the length of the active region of the distributed

amplifier. In a large signal level s the gain will be compressed due to saturation and
Ap (s ) = e2 ( s )

As a specified signal to noise ratio, often

So
=1
No

F=

(8)

where Ap is the power gain of an amplifier, K is the Boltzmann constant 1.38054 1023 J/K, T is the absolute temperature of the input circuit to the amplifier, B is the overall
frequency bandwidth of the amplifier, Ps is the input signal
power, F is the noise figure of the amplifier, and So /No is the
signal-to-noise power ratio of the amplifier at the output.
Then,
Ps = KTBF

Noise figure F of an amplifier is given by definition (1)

Dynamic Range

Sensitivity

Ps Ap
So
=
KTBAp F
No

where is given by Eq. (5).

(6)

where f 0 is the center frequency of the amplifier. Usually Eq.

(6) is at least the second-order equation of f. One root is fH,
which is greater than f 0, and the other is fL, which is less
than f 0. Then the frequency bandwidth is
 f = f H f L

(13)

Noise Figure

(2 f )(C( f )R( f ) L( f )G( f ))

1
A( f  ) = A( f 0 )
2

Ap =  2

n[dB] = 10 log10 e2{ 0 ( s )} 

(19)

n[dB] = 8.686{0 (s )}

(20)

or

In practice, n 1 is often chosen, and the value of the input

voltage for n 1 is termed the input signal voltage at 1 dB

688

DISTRIBUTED AMPLIFIERS

compression point. The 1 dB compression point input signal

voltage is then
L

1
(s ) = 0
8.686

(21)
Rs

Stability
As seen from Eq. (1), a generic distributed amplifier is inherently stable. A controlling parameter in Eq. (1) is the magnitude of the negative conductance per meter G. Equation (1)
does not show any singularity due to the size of G within the
range of practical operation.
PERIODICALLY LOADED ACTIVE
DIODE DISTRIBUTED AMPLIFIERS

Cj

Figure 12. Equivalent circuit of a tunnel diode. This is for a packaged diode properly biased. C is the package capacitance; L is the
lead inductance; Rs is the spreading resistance; Cj is the junction capacitance; and G is the negative conductance of the tunnel diode
packaged.

Periodically Loaded Tunnel Diode Distributed Amplifiers

In a periodically loaded tunnel diode disturbed amplifier, a
number of discrete tunnel diodes are periodically loaded on
an RF transmission line as shown in Fig. 4(a). A generic volt
ampere curve of a tunnel diode is shown in Fig. 11. This is a
plot of the diode current and the voltage across the diode.
When the diode is biased in a negative conductance region,
the amount of the negative conductance is given by
G=

I
<0
V

(22)

In Fig. 12, an equivalent circuit of a discrete tunnel diode is

shown. In this figure, L is the lead inductance, Rs is the
spreading resistance, CJ is the junction capacitance, Cp is the
package capacitance, and G is the negative conductance of
the tunnel junction created by the tunnel effect. With the help
of additional impedance matching components it is possible
to tune out the inductances and capacitances; under a
matched and tuned condition, the tunnel diode can be represented by a negative conductance of magnitude GD.
The RF power gain due to a discrete negative conductance
GD, which is matched to a characteristic impedance of the
transmission line Z0, is (3),
A=

Tunnel
effect
I current

1
1 GD Z 0

I
V

(23)

<0

Negative
conductance
region

Diffusion
current

Figure 11. Generic volt-ampere curve of a tunnel diode. Note that

this volt-ampere curve does not follow Ohms Law. Note also the negative differential conductance at the mid-voltage region. This is a plot
of the diode current versus the diode bias voltage relationship.

At any diode in Fig. 4(a), half of the amplified power goes

back to the input and the other half of the amplified power
keeps traveling toward the output. Thus, actual power gain
of traveling waves toward the output is
A+ =

1
2(1 GD Z0 )

(24)

If there are N diodes used in a distributed amplifier as shown

in Fig. 4(a), the total power gain of the amplifier is
AT = (A+ )N =

1
2N (1 GD Z0 )N

(25)

after matching and tuning.

For the impedance matching and tuning, in addition to attaching the impedance matching circuit components to the diode mount, the adjustment of periodicity together with the
diode biasing must be done properly.
Periodically Loaded Gunn Diode Distributed Amplifiers
A volt-ampere characteristic of a generic Gunn diode is
shaped similarly to that shown in Fig. 11 except that the negative conductance is smaller than that of a tunnel diode. The
negative conductance of a Gunn diode is created by the transfer of the electronic momentum between a high electric field
domain and a low field domain in the bulk of a semiconductor
diode. The equivalent circuit of a Gunn diode is similar to the
circuit shown in Fig. 12. Therefore, the principle of a periodically loaded Gunn diode distributed amplifier is similar to the
principle of a periodically loaded tunnel diode distributed amplifier. Then the power gain equation of a Gunn diode distributed amplifier, which consists of N Gunn diodes in the negative conductance GD and with the characteristics impedance
Z0, is
AT =

1
2N (1 GD Z0 )N

(26)

Periodically Loaded Varactor Diode

Distributed Parametric Amplifier
When discrete variable capacitance diodes (varactor diodes)
are periodically mounted on a transmission line as shown in

DISTRIBUTED AMPLIFIERS

Fig. 4(b), RF voltage is amplified by the parametric effect of

the junction capacitance. The voltage gain across a single
parametric capacitance diode is given by Ref. 2.


p Qi
+ Qs
A=
(27)
4(vo + vro )
where p is the pump voltage across the junction capacitance
of the varactor diode, vo is the magnitude of the contact potential barrier of the diode, vro is the dc reverse bias voltage, and
Qi and Qs are the quality factors of the idler circuit and the
signal circuit per diode, respectively.
Usually in a parametric amplifier, the idler frequency
shown in Fig. 4(b) is
fi = fp fs

(28)

fp
2 fs

(29)

Qi
Qs

(30)

and

689

where e is the phase constant associated with the dc electron

beam and
e /u0

(34)

is the operating angular frequency and u0 is the speed of

the electrons in the beam. Term C in Eq. (33) is termed the
gain parameter (1,2) and is given by
C3 =

Z0 Ia
4Va

(35)

where Z0 is the characteristic impedance of the helical line,

Ia is the dc electron beam current, and Va is the acceleration
anode voltage of the traveling wave tube.
If the length of the active interaction region on the helical
transmission line is m long, then the voltage gain of this
traveling wave tube is (2)
A = e(

3/2)C e 

(36)

for a high gain (5). Then,

QUANTUM ELECTRONIC DISTRIBUTED AMPLIFIERS

Applying the same concept as was done in Eqs. (25) and

(26), the total voltage gain of an N-diode distributed parametric amplifier is, after matching and tuning,


A T =

N


p Qi
+ Qs
4(vo + vro )

(31)

PERIODICALLY LOADED TRANSISTOR

DISTRIBUTED AMPLIFIER
Similar concepts of Eqs. (25), (26), and (31) are applicable to
a periodically loaded discrete transistor amplifier. The transistors can be either junction transistors or field effect transistors (68). If the s-parameter of the discrete transistor
from the gate (or base) to the drain (or collector) is S21, then,
after impedance matching and tuning, the voltage gain of an
n-transistor distributed amplifier is given by
A T = SN
21

(32)

THERMIONIC DISTRIBUTED AMPLIFIERS

Thermionic distributed amplifiers are vacuum tubes that are
called traveling wave tubes. A schematic diagram of a generic
traveling wave tube is shown in Fig. 8. The principle of the
traveling wave tube distributed amplifier was already briefly
explained in this article. While microwaves travel along the
helical transmission line with the axial propagation speed approximately equal to the speed of electron beam, the kinetic
energy of the electron beam is transferred gradually into the
propagating microwaves in the transmission circuit; hence
the microwaves are amplified. The propagation constant of a
traveling wave tube is given by (1,2)



3
C
C+ j 1+
(m1 )
= e
(33)
2
2

A quantum electronic distributed amplifier can be a continuous configuration as shown in Fig. 9. If the signal to be amplified is a lightwave, then this distributed amplifier is a traveling wave laser. If the signal to be amplified is a microwave,
then this distributed amplifier is a traveling wave maser. For
a traveling wave maser, instead of the optical fiber cable, a
microwave transmission line continuously loaded with maser
material (such as a ruby or a rutile crystal) and a microwave
local pump oscillator instead of the pump laser, are used.
At any rate, the gain constant of a traveling wave maser
or laser distributed amplifier is given by (9)
=

2Qmo g

(37)

where is the angular frequency of the signal to be amplified, Qmo is the quality factor/meter of the active cable and vg
is the group velocity of the signal in the cable. The quality
factor Qmo is given by
Qmo =

Wso
P

(38)

where Wso is the electromagnetic energy of the signal stored

per meter of the cable and P is the signal power loss per
meter of the cable.
The voltage gain of this continuously loaded distributed laser or maser amplifier is
A =  /2Q mo g

(39)

where is the length of active part of the cable.

A quantum electronic distributed amplifier can be a periodical loading configuration as shown in Fig. 13. A microwave
transmission line of a periodic structure is continuously
loaded with an activated maser crystal and placed in a rectangular microwave waveguide. The pump power from a pump
oscillator is fed to the rectangular waveguide to activate the
maser crystal. The pumped-up maser crystal emits radiation
when stimulated by the input microwave signals.

690

DISTRIBUTED AMPLIFIERS

Microwave
input

EXAMPLES OF DISTRIBUTED AMPLIFIERS

Microwave
output

RF Distributed Amplifiers
Periodicity

In practice, at RFs of less than 300 MHz, a distributed amplifier can be built using discrete components or surface mountable discrete components (10). An example of such distributed
amplifiers is shown schematically in Fig. 14.
Discrete field-effect transistors (FETs) are sequentially excited through the gate delay line or the gate artificial transmission line and consist of Cg, 
Lg, Lg, Lgg, and Rg. These are
discrete components. The Cg is a dc blocking input coupling
capacitor, Lg is an inductor to produce desired phase delay
between stages of the FET amplifiers, and Rg is the matched
terminating resistor for the artificial transmission line. The
idea is to generate RF traveling waves on the gate artificial
transmission line. The Lgg is a stray inductance of the gate
lead. In most cases Lgg is negligibly small at most RF frequencies. The terms Rs and Cs signify the source bias resistor and
bypass capacitor and Ldd is the stray inductance of the drain
of the FET. By making the drain lead as short as possible, it
is possible to make Ldd negligibly small at RF frequencies.
The drain delay line or the drain artificial transmission
line is formed by Rd, Ld, and Cd. The Rd is an impedance
matched resistor to the drain artificial transmission line and
Ld is the phase delaying inductor between stages. The value
of Ld must be determined so that the phase of waves on the
drain artificial transmission line synchronizes with the phase
of waves on the gate artificial transmission line. The Cd is a
dc blocking RF coupling capacitor to the output load. The
transistors are biased through a radio frequency choke (RFC)
and a decoupling capacitor.

Pump
oscillator
input
Termination

Waveguide

Periodical
line

Ruby maser crystal

Figure 13. A schematic diagram of a periodically loaded quantum
electronic maser distributed amplifier. The ruby maser crystal is
pumped by the pump oscillator input in the waveguide. Microwave
input signals are amplified by the stimulated emission of radiation
from the pumped ruby maser crystal, while propagating down the
meander line. The meander line is structured to lengthen the interaction time between the input signals and the stimulated emission of
radiation.

The voltage gain of the periodically loaded quantum electronic distributed amplifier given by
A =  /2Q mp g

(40)

is in principle similar to the case of continuously loaded quantum electronic distributed amplifier where Qmp is the quality
factor within the periodicity of the periodical structure.
Qmp =

Wsp
P

(41)
Microwave Distributed Amplifiers

where Wsp is the signal energy stored within the periodicity of

the structure of the transmission line and P is the signal
power loss within the periodicity.

A variety of microwave frequency distributed amplifiers have

been built in the past (1012). In microwave frequencies, the
distributed amplifiers take the forms of monolithically devel-

Vdd
RFC
Ld

1/2Ld
Matched
termination

Rd

Lgg
Cg
RF
input

Ld

Ldd

Ldd

Cs

Rs

Lgg

RF
Output

Ldd

Cs

Rs

Lgg

Cd

1/2Ld

Cs

Rs

1/2Lg
Lg

Lg

Lg

Lg

Rg
Matched
termination

Figure 14. A schematic diagram of an example of an RF distributed amplifier. The input signals
are successively and sequentially amplified by properly phased multistage FET amplifiers.

DISTRIBUTED AMPLIFIERS

691

Vdd

RFC

Drain

Microstripline

Rd

Microwave
Output

Ccg

Microwave
input

Cdd

Rg
Gate

Microstripline

oped integrated circuits as shown in Fig. 15 (for example). As

is the case in Fig. 14, the microwave input signals to be amplified are fed to the gate microstripline with impedancematched terminating resistance Rg through a dc blocking coupling capacitor Ccg. The gate of each FET, which is properly
biased, is sequentially excited. Amplified microwave drain
current propagates along the drain microstripline toward the
output and it is coupled out to the output circuit through a dc
blocking coupling capacitor Ccd. The drain microstripline is
terminated with an impedance matched resistor Rd. If the circuit is properly balanced, current traveling toward Ccd adds
in-phase, while current traveling toward Rd adds out-ofphase. This amplifier is actually a current combiner. The
drain microstripline is biased through a RFC and a bypass
capacitor with VDD.
At best, a distributed amplifier has only half the efficiency
and requires twice the total gate width as a balanced amplifier, for the same gain (13). Gain, it should be noted, can be
increased by adding more FETsthat is, by making it longer;
best efficiency can be achieved, however, by optimizing the
length. Once an optimal length is achieved, these distributed
amplifiers can be cascaded in order to achieve the prescribed
gain.
Because of losses in the amplifier, best performance can be
achieved by tapering the gate (14), so as to pre-distort the
applied gate voltage along the length of the amplifier, and aid
in maintenance of a more steady voltage applied to the effective gate. Higher power, large signal amplifiers have also
been designed and evaluated (1519). Distributed amplifiers
are limited in the amount of power they deliver, generally
about 1 Watt (when using a 50 transmission line). Lowering the impedance of the line can allow greater output powers but at the expense of a reduction in gain. Tapering the
drain line has been found (20,21) to increase efficiency by improving the phasing of currents on the drain line.
Most microwave monolithic IC distributed amplifiers are
of extremely wide frequency band even though total gain is
not very high. They are also extremely compact. For example,
Kimura and Imai (11) monolithically integrated a seven-stage
distributed amplifier on a 1.5 mm 2.5 mm integrated circuit
(IC) substrate and reported that the flat gain over the frequency range 0 to 55 GHz with 6 dB noise figure was 9 dB.

Figure 15. A schematic diagram of a microwave monolithic distributed amplifier. Both

the gate and drain lines are microstriplines.
The gate line feeds the FET sequentially. On
the drain microstripline, the amplified signals are sequentially combined and propagate out at right.

Lightwave Distributed Amplifiers

The actual configuration of a lightwave distributed amplifier
is shown in Fig. 9. These amplifiers are actually deployed to
boost lightwave signals for a long-haul lightwave signal
transmission such as in transoceanic lightwave cables. For
example, the lightwave input signal to be amplified is 1500
nm wavelength (3). The pump laser is a 980 nm solid-state
laser diode that feeds the pump power through a directional
coupler to the main cable. The directional coupler is a pair of
lightwave waveguides placed in proximity to each other so
that the lightwaves can couple one waveguide to another. The
end of the lightwave guide for the pump laser, which is the
primary waveguide of the directional coupler, is reflectionlessly terminated using a lightwave absorbing component.
The pump-laser light is fed into the main lightwave waveguide, which is the erbium-doped optical fiber. The pump
laser light excites or pumps up the atoms of erbium to prepare for emission of radiation at 1500 nm. When these
pumped up erbium atoms receive stimulating radiation of
1500 nm from the input lightwaves, these atoms emit radiation at the same 1500 nm wavelength. This is a laser amplifier. The emission of radiation continues as the input
lightwave travels in the erbium-doped optical fiber. The emitted wave travels together with the stimulating lightwave. The
amplified lightwave exits the output connector. The pump
power is minimal at this point. It has been used in the amplification process. The signal output is taken out of the system
through a bandpass filter for the signal lightwave. Any residual pump lightwave is rejected at the filter. The lightwave
gain of 15 dB is reported for several meters-long erbiumdoped plastic optical fiber cable.
The amplifier cable can be praseodymium-doped fluoride
fiberglass cable with a wavelength of 1300 nm (3). The gain
of 40 dB for several meter-long cable length is reported (3).
CONTINUOUS DISTRIBUTED AMPLIFIERS
Continuous Active Diode Distributed Amplifiers
In Fig. 5, it is possible to monolithically develop a continuous
tunnel diode junction or Gunn effect diode contact between
the two strips of metallization by removing all discrete diodes

692

DISTRIBUTED AMPLIFIERS

and using an intrinsic semiconductor substrate instead of the

dielectric substrate. Then, if the conducting strips from the
coplanar waveguide are properly biased at the negative resistance of the diode, the microwaves fed into one end of the
coplanar waveguide will be amplified by the distributed negative resistance as it travels along the coplanar waveguide and
the amplified microwave exits from the other end of the coplanar waveguide.
Continuous Transistor Distributed Amplifiers
A conceptual diagram of a continuous transistor distributed
amplifier is shown in Fig. 6. It is desirable that the length of
the microstrips must be longer than several wavelengths of
the transmission line wavelength. The transmission line
wavelength on the coplanar waveguide is smaller than the
free space wavelength and inversely proportional to the
square root of the effective relative permittivity of the substrate in the gap between the conducting strips. For a semiconductor substrate, it is not uncommon that the effective relative permittivity is 10 or higher.
Continuous Parametric Varactor Diode Distributed Amplifier
A conceptual schematic diagram of a continuous parametric
varactor diode distributed amplifier is shown in Fig. 3(b). Using the same concept, an alternate method and more convenient approach to the monolithic integrated circuit technology
is shown. Instead of using the microstripline as shown in Fig.
3(b), the configuration is changed to a coplanar waveguide as
shown in Fig. 5. A long junction varactor diode is monolithically developed flatly between the gap of a long parallel metallization strip of the coplanar waveguide.
Continuous Ferrimagnetic Distributed Amplifiers
Space between the long gap of metallization strips of either
the microstripline as shown in Fig. 3(b) or the coplanar waveguide as shown in Fig. 5, can be filled with a magnetized ferrimagnetic material or a ferrite. This is a ferrimagnetic continuous distributed amplifier (1,22). The nonlinear magnetism of
a ferrite makes the system a variable inductance parametric
amplifier when both the pump oscillator power and the signal
power are launched into the same transmission line. The
pump oscillator power then gradually transfers into the signals through the distributed nonlinear inductance of the ferrites as both the signals and the pump oscillator power travel
together along the ferrite loaded transmission line.

BIBLIOGRAPHY
1. T. K. Ishii, Microwave Engineering, San Diego, CA: Harcourt
Brace Jovanovich, 1989.
2. T. K. Ishii, Practical Microwave Electron Devices, San Diego, CA:
Academic Press, 1990.
3. Editorials, Lightwaves, p. 26, November, 1993.
4. IEEE, IEEE Standard Dictionary of Electrical and Electronics
Terms, New York: Wiley-Interscience, 1972.
5. J. T. Coleman, Microwave Devices, Reston, VA: Reston Pub. Co.,
1982.
6. J. B. Beyer et al., MESFET distributed amplifier design guidelines, IEEE Trans. Microw. Theory Tech., 32: 268275, 1984.
7. K. B. Niclas et al., On theory and performance of solid-state microwave distributed amplifiers, IEEE Trans. Microw. Theory
Tech., 31: 447456, 1983.
8. W. Kennan and N. K. Osbrink, Distributed amplifiers: Their time
comes again, Microwaves RF, 23: 119125, 1984 (Part I); 23:
126153, 1984 (Part II); 24: 13, 1985 (correction).
9. T. K. Ishii, Maser and Laser Engineering, Huntington, NY: Robert
E. Krieger Pub. Co., 1980.
10. K. W. Kobyashi et al., Extending the bandwidth performance of
heterojunction bipolar transistor-based distributed amplifiers,
IEEE Trans. Microw. Theory Tech., 44: 739748, 1996.
11. S. Kimura and Y. Imai, 0-40 GHz GaAs MESFET distributed
baseband amplifier ICs for high-speed optical transmission,
IEEE Trans. Microw. Theory Tech., 44: 20762082, 1996.
12. A. H. Baree and I. D. Robertson, Monolithic MESFET distributed baluns based on the distributed amplifier gate-line termination technique, IEEE Trans. Microw. Theory Tech., 45: 188195,
1997.
13. J. L. B. Walker, Improving operation of classic broadband balanced amplifiers, Microwaves RF, 26: 175182, 1987.
14. J. L. B. Walker (ed.), High-Power GaAs FET Amplifiers, Boston:
Artech House, 1993, pp. 264281.
15. Y. Ayasli et al., 2-20 GHz GaAs travelling-wave power amplifiers,
IEEE 1998 Microw. and Millimeter-Wave Monolithic Circuits
Symp. Digest, 6770, Boston, MA, May 31June 1, 1983.
16. B. Kim and H. Q. Tserng, 0.5 W 221 GHz monolithic GaAs distributed amplifier, Electron. Lett., 288289, March 1984.
17. Y. Ayasli et al., Capacitively coupled-travelling-wave power amplifier, IEEE Trans. Microw. Theory Tech., 32: 17041711, 1984.
18. E. M. Chase and W. Keenan, A power distributed amplifier using
constant-R networks, IEEE 1986 Microw. and Millimeter-Wave
Monolithic Circuits Symp. Digest, 1317, Baltimore, MD, June
45, 1986.
19. M. J. Schindler et al., A K/Ka-band distributed power amplifier
with capacitive drain coupling, IEEE 1998 Microw. and Millimeter-Wave Monolithic Circuits Symp. Digest, NY, 58, May 24
25, 1988.

CONCLUSIONS

20. E. L. Ginzton et al., Distributed amplification, Proc. IRE, 36:

956969, 1948.

Distributed amplifiers are electrical transmission lines with

periodically or continuously loaded amplifiers. A feature of
distributed amplifiers is the wide frequency bandwidth. The
wide bandwidth amplifiers are capable both of having large
channel capacity and of handling extremely short or fast
pulses. Distributed amplifiers are useful for fast digital data
transmission systems of gigabit rates. Distributed amplifiers
can be made compact by the use of monolithic integrated circuit technology.

21. K. E. Jones, G. S. Barta, and G. C. Herrick, A 1 to 10 GHz tapered distributed amplifier in a hermetic surface mount package,
Proc. of IEEE GaAs I.C. Symp., 137140, Monterey, CA, November 1214, 1985.
22. P. K. Tien, Parametric amplification and frequency mixing in
propagating circuits, Jour. Appl. Physics, 29: 13471357, September 1958.

T. KORYU ISHII
Marquette University

DISTRIBUTED DATABASES

DISTRIBUTED BATCH PROCESSING. See BATCH

CESSING (COMPUTERS).

693

54

ELLIPTIC FILTERS

ELLIPTIC FILTERS
An electrical filter will be defined as an electrical system that
can process electrical signals on the basis of the frequencies
composing that signal. This signal processing can affect both
the magnitude and phase of each individual frequency component of the signal. For example, the output signal of an antenna may represent an electrical signal that requires magnitude processing. The output signal of the antenna has a fairly
wide spectrum of frequencies, and yet we would like only a
small range of these frequencies, such as those centered
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

ELLIPTIC FILTERS

2
1.8
1.6
1.4
Magnitude

around our favorite radio station, for example, to be processed

for our listening pleasure. One solution is to use a band-pass
filter in one of the stages following the antenna. The circuit
would process that signal in such a way that the band of frequencies containing the information from the station would
be passed, and the signals outside of that band would be rejected or would not pass through. Although this example is
very much simplified in comparison to what actually happens,
it nonetheless illustrates the general idea of filtering.
Because of a need to filter signals in a variety of ways,
several standard types of filters or signal processing
schemes have evolved. These are low-pass, high-pass, bandpass, band-reject, and all-pass filters. Low-pass filters strive
to allow frequencies below some predetermined cutoff frequency to pass, while rejecting those frequencies above the
cutoff frequency. High-pass filters strive to allow frequencies
above some predetermined cutoff frequency to pass, while rejecting those frequencies below the cutoff frequency. Bandpass filters allow a band of frequencies to pass, while rejecting
frequencies outside of that band. Band-reject filters reject a
band of frequencies, allowing frequencies outside that band to
pass. The main objective of these four types of filters is to
process the signals magnitude as a function of frequency. The
all-pass filter lets all signals pass through, but selects a band
of frequencies for phase angle processing. The choice of filter
depends on the application.
Filter design can be broken down into two broad phases.
The first phase is the selection of a transfer function possessing the mathematical properties of filtering. A transfer
function describes the relationship between the input signal
and the output signal. We will use it in the sense that for a
given input signal, we will have a specific output signal. Since
filters process electrical signals according to the frequency
content, the transfer function for a filter is a function of s
j j2f, where is the frequency in radians/s and f is the
frequency in hertz.
The second phase of filter synthesis is realization of a circuit that possesses the same transfer function as the mathematical function selected to do the filtering. The circuit may
be an analog, digital, or a mixed analogdigital circuit depending on the application.

55

1.2
1
0.8
0.6
0.4
0.2
0
0

0.2

0.4

0.6 0.8
1
1.2 1.4
Frequency (radians/s)

1.6

1.8

Figure 1. The magnitude versus frequency plot of an ideal low-pass

filter transfer function shows that all frequencies of a signal below 1
rad/s are passed while those above 1 rad/s are rejected.

cessing, at the output of the filter at the same time. If the two
input signals add together to create a distinct response in the
time domain at the input, it may be important that they reconstruct together at the output to maintain the shape of
the input signal. Sometimes this is important, and sometimes
it is not. A deviation from the linear phase response results
in phase distortion. The functions shown in Figs. 1 and 2 are
normalized filters. That is, they have cutoff frequencies of 1
rad/s and maximum gains of 0 dB, or 1 V/V in the passband.
It is conventional to begin a filter design with a normalized
filter. This allows for a common starting point for all low-pass
filters, for example, and is also a convenient way of comparing
the characteristics of other different types of low-pass filter

0
50

THE APPROXIMATION PROBLEM

100
150
Phase (deg)

When filtering, engineers tend to think in terms of ideal filters. For example, when deciding to use a low-pass filter, the
engineer typically desires that all frequencies above a defined
cutoff frequency should be eliminated. An ideal low-pass
transfer function magnitude response with a cutoff frequency
of 1 rad/s is shown in Fig. 1, and the ideal low-pass transfer
function phase characteristics are shown in Fig. 2. For the
magnitude plot, all frequencies below 1 rad/s are passed, with
a gain of one, and all frequencies above 1 rad/s are rejected.
It is a brick wall function. It is intuitively obvious that this
is an ideal magnitude characteristic. The ideal phase characteristic is not so intuitive. The important feature of the ideal
phase characteristics are not the values of the phase angle,
but that the phase response is linear. A transfer function that
has linear phase characteristics means that separate signals
composed of two different frequencies applied at the same instant of time at the input of the filter will arrive, after pro-

200
250
300
350
400
450
0

0.2

0.4

0.6 0.8
1
1.2 1.4
Frequency (radians/s)

1.6

1.8

Figure 2. The ideal low-pass filter function phase characteristics

may be summarized as a linear phase response.

ELLIPTIC FILTERS

band region located from s to infinity. Lastly, the transition

region is composed of the range between p and s. Figure 3
should be interpreted as follows: Signals at or below p will
have a gain of at least of G dB and at the most H dB, and
signals above s will be attenuated by at least A dB or will
have a maximum gain of SBR dB. Note that (GH) dB PBR
in dB. Filter types other than low-pass filters have similar
specifications, and the reader is encouraged to investigate
these (1,2).
Past research in network theory has resulted in several
classic mathematical approximations to the ideal filter magnitude function. Each of these were designed to optimize a property of the filter function. The low-pass filter approximations
are usually of the form

H
PBR
G

A
Passband
Stopband

0
0

|H( j)|2 =

SBR

Frequency (radians/s)
Figure 3. PBR, SBR, A, passband, and stopband are ways of characterizing an actual filter functions magnitude versus frequency response to that of an ideal response. For an ideal filter function,
PBR SBR 0 V/V and s and p are equal.

functions with each other. Moreover, numerous tables exist

that provide the coefficients or poles and zeros of filter transfer functions. These tables provide information for normalized
filters. Since there is an infinite number of possibilities for
cutoff frequencies, it would be impractical, if not impossible,
to generate tables for all possible cases. Thus, the tables deal
only with the normalized case. It is trivial to scale a filter for
a desired cutoff frequency from the normalized frequency.
The first step in low-pass filter design is to find a transfer
function of s having the same characteristics as the transfer
function depicted in Fig. 1 and being realizable with a circuit.
Without having transfer function with an infinite number of
terms, it is impossible to devise a transfer function with those
characteristics. Hence, from this simple example arises the
approximation problem. That is, may we find a transfer function magnitude response that approaches that shown in Fig.
1? In general, the higher the order of the filter, the closer the
transfer function magnitude response will approach the ideal
case. However, the higher the order of a filter, the more complex the design and the more components that are needed to
realize the transfer function. Thus, the concept of trade-offs
and compromises arise. In general, a set of filter specifications
must be determined before selecting the transfer function.
The specifications may viewed as how far the actual filter response may deviate from the ideal response.
Since it is impossible to come up with an ideal transfer
function that is practically realizable, several terms have
been defined and have been accepted as convention that
allows the description of the deviation of a practical filter
function from the ideal filter function. These terms are depicted in Fig. 3 and may be referred to as filter specifications.
The specifications are: the passband, the stopband, the passband ripple (PBR), the stopband ripple (SBR), and the stopband attenuation, A. PBR, SBR, and A are usually specified
in dB. There are three distinct regions. The passband is located from 0 rad/s to p rad/s. The second region is the stop-

1
1 +  2 T 2 ()

(1)

By replacing T() with different functions, different approximations arise. The standard approximations to the ideal magnitude response are the Butterworth Approximation, the
Chebychev Approximation, the Inverse-Chebychev Approximation, and the Elliptic Approximation. Each has strong
points and weak points. A fifth classic approximation worth
mentioning is the Bessel function. This approximation will
not be discussed, because it strives to approximate the ideal
phase response. This article will focus on the Elliptic Approximation.
THE ELLIPTIC APPROXIMATION
Before a mathematical discussion on the Elliptic Approximation is begun, it is useful to examine a plot of the magnitude
of an elliptic filter function. A fifth order elliptic filter lowpass transfer function magnitude response is depicted in Fig.
4. The passband exists for p. The stopband exists for
s. The passband and stopband may be characterized as
equiripple. That is, the amplitude oscillates between a maxi-

2
1.8
1.6
1.4
Magnitude

Magnitude

56

1.2
1
0.8
0.6
0.4
0.2
0

p s
Frequency (radians/s)

Figure 4. The magnitude characteristics of a fifth-order elliptic filter

show an equiripple passband and stopband, and at zero at .

ELLIPTIC FILTERS

57

Table 1. Filter Comparisons

2
1.8
1.6

Filter Type

Transition Region

Linear Phase Properties

Butterworth
Chebychev
Elliptic

Poor
Good
Best

Good
Poor
Very poor

1.4
1.2
Butterworth
1
0.8
Elliptic

0.6

Chebychev

0.4
0.2
0
0

0.2

0.4

0.6 0.8
1
1.2 1.4
Frequency (radians/s)

1.6

1.8

Figure 5. The fifth-order elliptic function magnitude characteristics

show a much sharper transition from the passband to the stopband
than the Butterworth and Chebychev function characteristics.

mum and minimum throughout a fraction of each band. If the

order of the filter is even, there are n/2 peaks in the passband, and n/2 minimums or zeros in the stopband. If the order of the filter is odd, there are (n 1)/2 peaks, plus one at
0 in the passband. Also for the odd order case, there are
(n 1)/2 minimums or zeros, plus one at , in the
stopband.
In discussing the properties of the elliptic filter, it is important to compare its characteristics with the other classic filter
types. A comparison of fifth-order, low-pass, normalized, Butterworth, Chebychev, and elliptic filter magnitude functions
is given in Fig. 5, and comparison of the phases is shown in
Fig. 6. From these comparisons, Table 1 may be generated.

From this discussion, the main attribute of the elliptic filter

may be stated. That is, for a given filter order, it provides the
sharpest cutoff characteristics; and thus out of all three filters, it best approximates the ideal low-pass magnitude function in terms of a sharp transition region. This is very important if filtering is required for frequencies near each other, if
we would like to pass one of these signals, and reject another.
The compromise in using the elliptic filter is its very poor
phase characteristics.
The theory behind the mathematics of the elliptic filter is
complicated and is not suitable for this publication. Interested
readers may consult Refs. 2 and 3. A summary of the mathematics is discussed in this article.
The general form of the elliptic filter magnitude squared
transfer function is given by Eq. (1). For the low-pass elliptic
filter function, T( j) is replaced with Rn( j). Rn( j) has two
different forms: one for an even-order function and one for an
odd-order function. Rn( j) will be described for a normalized
low-pass filter. For the even-order case we have

Rn () = M

n/2 2

(s /i )2
2 i2
i=1

For the odd-order case we have

Rn () = N

(n1)/2

i=1

2 (s /i )2
2 i2

(3)

M and N are normalization constants and are chosen so that

Rn(1) 1. The i are calculated for the even or odd case. For
the even case we have

0
50

sn

Elliptic

150

i =

100

Phase (deg)

(2)

(2i 1)K

1 

(4)

200

and for the odd case we obtain

Butterworth

250
Chebychev

300

i =
sn

2iK

1 

(5)

350
400

K(k) is the complete elliptic integral of the first kind and is

defined as

450
0

0.2

0.4

0.6 0.8
1
1.2 1.4
Frequency (radians/s)

1.6

1.8

Figure 6. The fifth-order elliptic function phase characteristics deviate much farther from the desired ideal linear phase characteristics
than the Butterworth and Chebychev function characteristics.

/2

K(x) =

(1 k2 sin2 x)1/2 dx

and sn is the Jacobian elliptic sine function.

(6)

58

ELLIPTIC FILTERS

The order of the filter function may be determined by

rounding up n to the nearest integer in the expression

1

n=
K
where L is defined as
L=

K

1

1s 
L1 
K

(7)

REALIZATIONS OF ELLIPTIC FILTERS

100.1 PBR 1
100.1 A 1

(8)

and PBR and A are in decibels. Lastly,

K  (k) = K(

(1 k2 ))

(9)

When Rn() is found, the substitution s /j is made, and

Rn(/j) may be inserted into Eq. (1). The poles of H(s)H(s*)
can be found. This is a standard synthesis technique (4). The
left half-plane poles and half of the zeros are selected and
combined to give the final form of the elliptic filter transfer
function. For n even, we have
n/2


H(s) = H

(s2 + i2 )

i=1

(10)

a0 + a1 s + + an1 sn1 + an sn

n1/2


There are an infinite number of possible synthesis algorithms

that may be used. In this section we describe one.
The first step in elliptic filter design is to find a transfer
function that will meet a set of specifications that have been
determined from the application. The design usually begins
with specifying the passband frequency p, PBR, s, and A. If
filter tables are to be used, the frequencies of the filter specifications must first be normalized. This is achieved by dividing s and p by p. Other normalizations are possible. This
results in a normalized passband frequency of 1, and a normalized stopband frequency of s /p. If a highpass filter is
desired, the specifications must be transformed further, by inverting p to 1/p. Once the desired transfer function is determined, a method of realization is selected. The realizations
may be analog or digital. The analog realizations may be
passive or active. The choice depends on many practical issues (1).
Passive Realizations

For the case of n odd, we obtain

H(s) = H

of products of poles and zeros, depending on the type of realization.

Because of the complexity of the calculations required to
find the transfer function, the usual method of finding H(s) is
usually either with a computer program or using one of the
numerous tables that have been generated and published
(2,5).

(s2 + i2 )

i=1

(11)

a0 + a1 s + + an1 sn1 + an sn

Note that the even-order transfer function given by Eq. (10)

has no zeros at infinity while the odd-order transfer function
of Eq. (11) has a single zero at infinity. It may be convenient
to have the denominator in the form of coefficients or in terms

Passive realizations utilize capacitors, inductors, and resistors. The source and load resistances are considered part of
the realization. Systematic procedures exist for the synthesis
of passive filters to realize elliptic transfer functions. Moreover, normalized passive filters are available as part of table
look-up approaches (5). Examples of passive elliptic filters are
depicted in Fig. 7.
Even-order passive realizations synthesized from Eq. (10)
will have negative elements because they do not have at least
a zero at infinity. This problem can be solved by shifting the

Rs

Vs

...

Rload Vout

n1

(a)

Figure 7. Typical nth-order low-pass passive

elliptic filters are realized with inductors and
capacitors, and include the source and load resistances. The circuit in (a) is for the odd-order
case and has n capacitors and (n1)/2 inductors. The circuit in (b) is for the even-order
case and has (n1) capacitors and n/2 inductors.

Vs

...

Rload Vout

n2
(b)

n1

ELLIPTIC FILTERS

59

C3
R5

R1

R3

R4

Vout

+
C1

Vs

C2

R2

C4

R6

Figure 8. A typical second-order stage used as

part of an active RC realization consists of an
operational amplifier, resistors, and capacitors
and is basically an active RC notch filter.

highest frequency zero to infinity. The resulting elliptic function filter function will have a double zero at infinity and the
passive filter realization will now have positive elements but
unequal terminating resistances. This even-order elliptic
transfer function is known as case B, while the original evenorder transfer function given by Eq. (10) is called case A.
Equal terminating resistances can be obtained by shifting the
first maximum to the origin. The resulting even-order elliptic
transfer function is known as case C (2,5). The new filter functions will be of the forms given by Eq. (12) for case B and Eq.
(13) for case C.
n/2


HB (s) = H

2
(s2 + Bi
)

i=2

b0 + b1 s + + bn1 sn1 + bn sn
n/2


HC (s) = H

(12)

2
(s2 + Ci
)

i=2

c0 + c1 s + + cn1 sn1 + cn sn

(13)

The magnitude response in the case B and case C filter functions are now slightly modified from the original type A.
One may ask if the passive realizations may utilize only
discrete elements. At the time of this writing, there is considerable interest in fabricating on-chip or on-package inductors
in integrated circuit (IC) design. If progress on these inductors continues at todays present rate, it is not inconceivable
that passive synthesis could become commonplace in integrated filter design.
Active Realizations
Elliptic filters may be synthesized with active RC filters. A
typical design procedure starts with dividing the elliptic filter
function into second-order sections. If the order of the filter is
odd, there will be one first-order section as well. All secondorder sections consist of complex conjugate poles and a pair
of zeros. An active filter stage may be used to create each
second-order stage. The active filter stages composing the second-order stages are notch filters that allow for z of the notch
to be different from 0 of the complex pole pair (not all notch
filters do). Once the filter is chosen, coefficients of the filter
are equated with coefficients of the active filter second-order
section. An example of such a filter section is shown in Fig. 8.

Once second-order sections have been synthesized, they may

be cascaded together to form the entire circuit. If a first-order
stage is used for an odd-order filter, a simple RC filter may
be added on. The first-order stage may also include a voltage
buffer. Active realizations may also be constructed using
switched-capacitor circuits.
Another popular method of elliptic filter synthesis is to
synthesize an active filter based on a passive realization. Generally, these types of filters replace inductors in the passive
circuit with simulated inductors. One type of simulated inductor is composed of an active RC circuit configured so that the
impedance of the circuit takes the form of the input impedance of an inductor. Active inductors may be also be realized
by transconductors and capacitors. Filters using this type of
active inductor are called gm C filters. They represent the
current state of the art in high-frequency active integrated
filter design using CMOS technology.
Another active filter based on a passive realization scales
the Rs, Cs, and Ls of a passive configuration by 1/s. The
resulting circuit contains capacitors, D elements, and resistors. The D element is a two-terminal device with an impedance of K/s2. Although the device doesnt exist as a passive
element, active circuits may be synthesized that achieve an
input impedance having this form.
Digital Realizations
Many of the techniques of digital filter synthesis are analogous to those used in analog filters. In particular, one of the
most systematic approaches to recursive digital filter design
is to first find a transfer function that meets specifications in
the analog domain, and then port it over to the digital domain. The transformation takes the transfer function from
the s domain into the z domain. The variable z plays the same
role in digital design that s plays in the analog domain. Often,
pre-distortion is applied, to account for errors the frequency
response that can occur in the transformation. The reader is
encouraged to consult Ref. 6 for more information on digital
filtering.
FREQUENCY AND MAGNITUDE SCALING
Frequently, a normalized design is the first step in filter realization. A frequency-normalized filter is designed for a pass-

60

ELLIPTIC FILTERS

band frequency of 1 rad/s. A typical normalized realization

has component values on the order of ohms, farads, and henries. The design is then frequency scaled so the frequency normalized response is shifted into place. That is, the passband
and stopband frequencies are transformed from normalized
values to the design values. The procedure is performed by
finding the scaling constant, p, and replacing s with s/p in
the circuit. This results in new values for the capacitances
and inductances, while the values for resistances remain unchanged. In circuit circumstances it may be desirable to frequency scale the normalized transfer function first and then
do the circuit synthesis.
Frequency scaling usually results in values for capacitors
and inductors that are close to practical, but still not practical. Moreover, the impedances of the resistors remain unchanged. The next step in denormalizing a normalized realization is to impedance scale. Impedance scaling amounts to
multiplying each impedance by a specified constant. The constant is picked so after scaling, the components have reasonable values. If all impedances are scaled by the same factor,
voltage transfer function remains the same. With good selection of the constant, practical values may be achieved.

HIGH-PASS ELLIPTIC FILTERS

The discussions in the preceding sections treat low-pass elliptic filters. There is little difference when discussing the properties of the high-pass elliptic filter.
The first step in high-pass filter design is to normalize
the high-pass parameters to the parameters that describe the
normalized low-pass filter. The parameters that describe
the high-pass are identical to the low-pass filter. One difference is that s p. In general, a low-pass filter transfer function may be transformed into a high-pass transfer function by
a s to 1/s transformation. This simply means that everywhere
s appears in the transfer function, 1/s is substituted.
Once the normalized low-pass elliptic transfer function has
been determined and a normalized circuit has been synthesized, a low-pass to high-pass transformation is applied. This
means that everywhere in the circuit, s is replaced with 1/s.
This results in capacitors becoming inductors, and inductors
becoming capacitors. If, in an active RC circuit for example,
inductors are not desired, the circuit may be magnitude
scaled by 1/s. This results in the inductors becoming resistors
and the resistors becoming capacitors.
Alternatively, if a normalized low-pass elliptic function has
been determined, it is possible to apply the s to 1/s transform
on the transfer function, resulting in a normalized high-pass
elliptic transfer function. It is now possible to synthesize a
circuit directly from this transfer function.

BANDPASS ELLIPTIC FILTERS

Bandpass filters may be classified as wideband or narrowband. A wideband bandpass filter seeks to allow a wide
range of frequencies to pass with equal magnitude scaling,
ideally. A narrowband filter seeks to allow only one frequency,
or a very small band of frequencies, to pass. One definition of
narrowband versus wideband filters is given by Ref. 1. This
particular definition states that if the ratio of the upper cutoff

frequency to the lower cutoff frequency is greater than one

octave, the filter is considered a wideband filter.
Synthesis of wideband bandpass filters may be performed
by a cascade of a high-pass filter and a low-pass filter. The
lower bound of the definition of wideband results in the separation of the high-pass and low-pass filters being such that
there is minimal interaction between the filters. If the ratio
is smaller than one octave, the cutoff frequencies are too close
together and the filters interact and must be treated as one
filter. Narrowband filters require different synthesis techniques.
Like the high-pass filter functions, bandpass filter functions may be synthesized from low-pass filter functions. This
is done by performing the transformation
1
s=
BW

s2 + 02
s

(14)

on a normalized low-pass filter function, where 0 is the center frequency and BW is the bandwidth of the filter. This
transform may also be used in the design of wideband bandpass filters.
BANDREJECT ELLIPTIC FILTERS
Like bandpass filters, bandreject filters may also be classified
as wideband or narrowband. A wideband bandreject filter
seeks to block a wide range of frequencies while allowing frequencies outside that band to pass with ideally equal magnitude scaling. A narrowband bandreject filter seeks to block
only one frequency or a very small band of frequencies. Like
the definition of narrowband versus wideband bandpass filter
definition, Ref. 1 gives a definition for narrowband versus
wideband bandreject filters. The definition is identical to that
of the bandpass filter.
Synthesis of wideband bandreject filters may be performed
by a cascade of a high-pass filter and a low-pass filter. The
lower bound of the definition of wideband results in the separation of the high-pass and low-pass filters being such that
there is minimal interaction between the filters. If the ratio
is smaller than one octave, the cutoff frequencies are too close
together and the filters interact and must be treated as one
filter. Narrowband filters require different synthesis techniques.
Bandreject filters may also be synthesized from normalized
low-pass filter functions by performing a transform of

s = BW

s
s2 + 02

(15)

on a normalized low-pass filter, where 0 is the center frequency and BW is the bandwidth of the filter. This transform
may also be used in the design of wideband bandpass filters.
SUMMARY
Elliptic filters are a class of filters used to shape the magnitude of an electric signal. They may be used in applications
for any of the standard magnitude processing filters. In comparisons to other available filters, the elliptic filter provides
the sharpest transition from the passband to the stopband for

EMERGENCY POWER SUPPLY

a given order. The magnitude response is equiripple in the

passband and the stopband. The drawback of the elliptic filters is very poor phase characteristics in comparison to other
filter types. Furthermore, evaluation of elliptic filter parameters is considerably more difficult than other filter approximation functions due to the use of elliptic sine functions and elliptic integrals.
BIBLIOGRAPHY
1. A. B. Williams, Electronic Filter Design Handbook, New York:
McGraw-Hill, 1981.
2. L. P. Huelsman and P. E. Allen, Introduction to the Theory and
Design of Active Filters, New York: McGraw-Hill, 1980.
3. R. W. Daniels, Approximation Methods for Electronic Filter Design, New York: McGraw-Hill, 1974.
4. A. Budak, Passive and Active Network Analysis and Synthesis,
reissue, Prospect Heights, IL: Waveland Press, 1991.
5. A I. Zverev, Handbook of Filter Synthesis, New York: Wiley, 1967.
6. E. P. Cunningham, Digital Filtering: An Introduction, Boston:
Houghton Mifflin Company, 1992.
Reading List
W.-K. Chen (ed.), The Circuits and Filters Handbook, Boca Raton, FL:
CRC Press and IEEE Press, 1995.
C. S. Lindquist, Active Network Design with Signal Filtering Applications, Long Beach, CA: Steward & Sons, 1977.

KENNETH V. NOREN
University of Idaho

EMBEDDING METHODS. See HIGH DEFINITION TELEVISION.

EMC, TELEPHONE. See TELEPHONE INTERFERENCE.

61

FEEDBACK AMPLIFIERS
AMPLIFIERS, FEEDBACK
Feedback is the process of combining a portion of the output of a system with the system input to achieve modied
performance characteristics. Found in a multitude of engineering applications, the process has become the foundation of several disciplines, such as feedback control systems, feedback receivers, feedback oscillators, and feedback
ampliers. It has become particularly pervasive in amplier design since the advent of transistors that can provide
high gain cheaply but cannot provide stable gain.
Negative feedback was originally applied by Harold S.
Black in 1927 at Bell Labs to valve (vacuum tube) ampliers to reduce distortion. In 1957 Blacks work was described by Mervin Kelly, president of Bell Labs, as one of the
two inventions of broadest scope and signicance in electronics and communications is the rst half of the century.
Negative feedback is the process of mixing an inverted portion of the output of a system with the input to alter system
performance characteristics. The process of negative feedback has become especially important in linear amplier
design and is characterized by several signicant benets:

The gain of the amplier is stabilized against variation in the characteristic parameters of the active
devices due to voltage or current supply changes, temperature changes, or device degradation with age.
Similarly, amplier gain is stabilized within a group
of ampliers that have active devices with somewhat
different characteristic parameters.

Nonlinear signal distortion is reduced.

The frequency range over which there is constant linear amplication (the midband region) is increased.

The input and output impedance of the amplier can
be selectively increased or decreased.
It is a rare occurrence when benets come without a
price. In the case of negative feedback, the aforementioned
benets are accompanied by two primary drawbacks:

The gain of the circuit is reduced. To regain the losses

due to feedback, additional amplication stages often
must be included in the system design. Complexity,
size, weight, and cost may be added to the nal amplier design.

There is a possibility for oscillation. Should oscillation
occur, the basic gain properties of the amplier are
destroyed.
This article considers the benets of negative feedback
for amplier design. Basic denitions are followed by a general discussion of the properties of a feedback system. Ampliers are divided into four categories of feedback topology,
and the specic properties of each topological type are derived. While the discussions must focus on circuit analysis
techniques, a clear understanding of feedback in general,
and effects of circuit topology in particular, is a necessity

Figure 1. Basic negative feedback topology.

for good feedback amplier design.

BASIC FEEDBACK CONCEPTS
Electronic ampliers are fundamentally characterized by
four properties:

The gain of the amplier. Gain is dened as the ratio

of the output signal to the input signal. Each signal
may be either a voltage signal or current signal.

The range of frequencies over which the gain is essentially constant: This range of frequencies is identied
as the midband region. It is bounded by the frequencies at which the output power is halved: the high and
low 3 dB frequencies.

The midband input impedance. Dened as the ratio
of input voltage to input current.

The midband output impedance. Dened as the
Thevenin impedance seen at the amplier output terminals.
The application of feedback to an amplier alters each of
these fundamental properties.
The basic topology of a feedback amplier is shown in
Fig. 1. An input signal, Xi , enters a summing (or mixing)
junction, symbolized by a circular symbol. At the summing
junction, the feedback signal, Xf , is subtracted from the
input signal and the resultant signal, X , is passed on to a
linear amplier, shown as a triangular symbol, of gain, A.
The output of the linear amplier, Xo , forms the output of
the feedback system. The rectangular symbol indicates a
feedback network that samples the output signal, scales it
by a feedback factor, f, and passes it forward to the input
of the system. Each signal can take the form of either a
voltage or a current and ideally travels only in the direction
of the indicated arrows. Subtraction of the two inputs at the
summing junction is the key factor in negative feedback
systems.
Feedback systems can be mathematically modeled with
a set of simple relationships. The output, Xo , of the amplier is related to the input signal, X , by a linear amplication factor (gain), A, often called the forward or open-loop
gain:

Since the quantities Xo and X can be either voltage or current signals, the forward gain, A, can be a voltage gain,
a current gain, a transconductance, or a transresistance.
Voltage gain is the ratio of output voltage to input voltage:
Similarly, current gain relates output and input currents.
Transresistance implies the ratio of an output voltage to

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Ampliers, Feedback

an input current: Transconductance is the ratio of an output current to an input voltage. The feedback signal, Xf (a
fraction of the output signal, Xo ), is then subtracted from
the input signal, Xi , to form the difference signal, X .

where f is the feedback ratio dening the relationship between Xf and Xo :

As is the case with the amplier gain, the feedback ratio,

f, is either a ratio of voltages, a ratio of currents, a transconductance, or a transresistance. The product fA, called the
loop gain, must be a positive, dimensionless quantity to
have stable negative feedback. Thus it is necessary, for negative feedback, that the mathematical sign of f be the same
as that of A within the midband region. The inputoutput
relationship for the overall feedback system can be derived
from Eqs. (1) and (2):

The overall gain of the system, including the effects of feedback, is then written as

The overall feedback amplier gain, Af , has the same dimensions as the forward gain, A. Equation (5) has special
signicance in the study of feedback systems and is typically identied as the basic feedback equation. The denominator of the basic feedback equation is identied as the
return difference, D, but is also commonly referred to as
the amount of feedback:

The return difference, for negative feedback systems,

has magnitude larger than unity (in the midband frequency region) and is often specied in decibels:

The return difference quanties the reduction in gain due

to the addition of feedback to the system. It also plays a
signicant role in quantifying changes in frequency bandwidth and input and output impedance. Specically, the
high and low 3 dB frequencies are increased and decreased,
respectively, by approximately a factor of D; and the input
and output impedances are increased or decreased by a
factor of D depending on the sampling and mixing circuit
topologies.
The derivation of the basic feedback equation is based
on two basic assumptions:

The reverse transmission through the amplier is

negligible (a signal at the output produces essentially
no signal at the input) compared to the reverse transmission through the feedback network.

The forward transmission (left to right in Fig. 1)
through the feedback network is negligible compared

to the forward transmission through the amplier.

In most feedback ampliers, the amplier is an active
device with signicant forward gain and near-zero reverse
gain: The feedback network is almost always a passive network. Thus, in the forward direction, the large active gain
will exceed the passive attenuation signicantly. Similarly,
in the reverse direction, the gain of the feedback network,
albeit typically small, is signicantly greater than the nearzero reverse gain of the amplier. In almost every electronic application, the aforementioned requirements for
the use of the basic feedback equation are easily met by
the typical feedback amplier.
ANALYSIS OF FEEDBACK AMPLIFIER PROPERTIES
The analysis and design of electronic ampliers is typically a multistep process. Complete, analytic characterization of an amplier is a complex process whose results
are in a form that often masks the individual amplier
properties. Amplier designers therefore investigate the
amplier gain, frequency response, and impedance properties separately, carefully balancing system requirements to
converge on a successful design. In addition to simplifying
the process, separate investigation of the amplier properties often leads to greater insight into design improvement.
When a successful design is apparent, nal ne-tuning is
accomplished with the aid of a computerized circuit simulator [i.e., System Program with Integrated Circuit Emphasis (SPICE)] and a breadboard prototype.
Essentially all of the drawbacks and benets of feedback
systems can be investigated on a simple level by looking at
the properties of the basic feedback equation [Eq. (5)]. Gain
stabilization, the reduction in nonlinear signal distortion,
the increase in the frequency range over which there is linear amplication, the reduction in gain, and the possibility of oscillation all can be investigated on a simple level.
The change in the input and output impedances cannot
be investigated at this level: It is necessary to specify the
nature (voltage or current) of the input and output quantities and the circuit topology to investigate these impedance
changes.
Amplier Gain
In the section on basic feedback concepts, it was shown
that feedback reduces amplier gain by a factor of the return difference, D. While reduction of gain can be a signicant drawback, the ancillary gains are signicant. Primary
among those benets is the stabilization of the amplier
gain against variation in the characteristic parameters of
the active devices. It is well known that the forward gain,
A, of an electronic amplier is highly dependent on the parameters of the active devices contained within that amplier. These parameters are typically dependent on temperature, bias conditions, and manufacturing tolerances. To
maintain consistent amplier performance, it is desirable
to design ampliers that are reasonably insensitive to the
variation of the device parameters.
The relationship between the differential change in gain
due to device parameter variation with and without feed-

Ampliers, Feedback

back is obtained by differentiating Eq. (5):

Stable negative feedback ampliers require that the return

difference have magnitude greater than unity:

Thus the absolute variation in gain is reduced by a factor

of the return ratio squared. Another measure of the change
in gain variation can be found by regrouping terms.

The factors in this equation more realistically describe the

benets: Equation (10) demonstrates the change in the percentage of gain variation about the nominal value. It can
be seen that the percentage variation of the overall amplier gain, Af , is reduced by a factor of the return ratio when
compared to the percentage variation of the gain, A, of the
forward amplier.
For example, a feedback amplier is constructed with
an amplier that is subject to a 3% variation in gain as its
fundamental forward-gain element and it is desired that
the feedback amplier have no more than 0.1% variation
in its overall gain due to the variation in this element. The
necessary return difference to achieve this design goal can
be obtained as follows: Equation (10) is the signicant relationship in determining the gain variation:

The signicant properties are

The minimum necessary return ratio is 30, more often identied as its decibel equivalent,

Equation (10) is extremely useful for small changes in amplication due to parameter variation but is inaccurate for
large changes. If the change in amplication is large, the
mathematical process must involve differences rather than
differentials:

To put this into the same format as Eq. (10), it is necessary

to divide both sides of the equation by A1f .

or

The results are similarly a reduction in gain sensitivity by

a factor of the form of the return difference.
The differential change in feedback amplier gain due
to variation in the feedback ratio, f, can be obtained by differentiating Eq. (5) with respect to the feedback ratio. Appropriate mathematical manipulation leads to the desired
results:

It is easily seen that the percentage variation of the overall amplier gain Af is approximately the same magnitude
(actually slightly smaller) than the percentage variation of
the feedback ratio, f. Since electronic feedback ampliers
typically employ a feedback network constructed entirely
with passive elements (usually resistors), variation in the
feedback ratio can be kept relatively small through the utilization of precision elements in the feedback network. In
good amplier designs, the variation of amplier gain due
to variability in the feedback network is usually of lesser
signicance than that due to variability of the basic forward amplier gain.
Nonlinear Signal Distortion
Stabilization of gain with parameter variation suggests
that amplier gain will be stabilized with respect to other
gain-changing effects. One such effect is nonlinear distortion. Nonlinear distortion is a variation of the gain with
respect to input signal amplitude. A simple example of
nonlinear distortion is demonstrated in Fig. 2, in which
the transfer characteristic of a simple amplier is approximated by two regions, each of which is characterized by
different amplication, A1 and A2 . To this transfer characteristic, a small amount of feedback is applied so that fA1
= 1, and the resultant feedback transfer characteristic is
shown. As can be seen easily, the overall feedback transfer characteristic also consists of two regions with overall
amplication A1f and A2f . In this demonstration, the amplication ratios are:

Feedback has signicantly improved the linearity of the

system and consequently has reduced the nonlinear distortion. Larger amounts of feedback (increasing the feedback
ratio, f) will continue to improve the linearity. For this example, increasing the feedback ratio by a factor of 5 will
result in a ratio of overall gain in the two regions of 1.067
(as compared to 1.5 previously). The saturation level of an
amplier is not signicantly altered by the introduction of
negative feedback. Since the incremental gain in saturation is essentially zero, the incremental feedback difference
is also zero. No signicant change to the input occurs and
the output remains saturated.
Another viewpoint on gain stabilization comes from a
limiting form of the basic feedback equation:

Ampliers, Feedback

Figure 2. The effect on feedback on an amplier transfer characteristic.

For large return difference (D = 1 + Af) the overall gain

with feedback is dominated by the feedback ratio, f, and
therefore virtually independent of the forward gain, A, and
any variations in A.
Frequency Response
Typical linear ampliers have a range of frequencies over
which the gain is essentially constant: This frequency
range is called the midband. As frequencies increase, the
performance parameters of an amplier degrade. Similarly, coupling and bypass capacitors internal to the amplier, when present, will degrade low-frequency performance. Using feedback to broaden of the frequency range
over which gain is relatively constant can be considered
a special case of the stabilization of gain due to variation
in amplier performance characteristics. Feedback reduces
the effects of these frequency-dependent degradations and
thereby increases the frequency band over which the amplier has stable gain.
A more exact description of the increase in the width of
the midband region can be obtained through a frequencydomain analysis. It is common practice to use the frequencies at which the output power is reduced by 50% (the high
and low 3 dB frequencies) as descriptors of the limits of the
midband region. Discussion focuses on the change in these
3 dB frequencies.
It can be shown that the basic forward amplier gain,
A, is described as the midband gain, A0 , divided by a polynomial in frequency (written as s or j):

The locations of the rst few poles of A(s) [or the zeroes of
P(s)] closest to the midband region are the dominant predictors of amplier frequency response: Specically, their
location controls the 3 dB frequencies.
The application of feedback to an amplier alters the
gain expression through the basic feedback equation so
that the total gain, Af , is described by

Figure 3. Pole migration due to feedback.

The application of feedback to the basic forward amplier

has the effect of vertically shifting the denominator polynomial by a constant, fA0 (see Fig. 3). This shift upward causes
movement in the zeroes of the denominator, thereby changing the location of the poles of the frequency response. Any
movement of the poles nearest the region of constant gain
(the midband region) equates into a change in the width
of the midband region. Observation of the consequences of
the result in graphical format is a great aid to understanding pole migration.
For example, when the high-frequency response is described by a single pole p1 , Eq. (21) takes the form

It can be seen easily that the gain has been reduced by a

factor of the return difference, D, and the pole frequency
has been increased by the same factor. Similarly, if the lowfrequency response is described by a single pole, pL1 , the
pole frequency will be reduced (that is, divided by) by a
factor of D. Since, in single-pole systems, the 3 dB frequency
coincides with the pole frequencies, the high and low 3 dB
frequencies, H and L , are shifted by a factor of the return
ratio:

As the number of poles increases, description of the

bandwidth increases with the application of feedback increases in complexity. When the high or low frequency response can be described by two poles, the damping coefcient due to the application of feedback is function ratio of
the initial pole locations, k, and the return difference. The
damping coefcient can be calculated to be:
1+k
1+k
=

=
2 kD
2 k(1 + f Ao )

(19)

where the k is dened as the ratio of the larger pole to the

smaller pole:
2H
1L
kH =
(20)
or kL =
1H
2L

Ampliers, Feedback

This simple expression for the damping coefcient is a

particularly important result in that it can tell the circuit
designer the atness of the frequency response in relation to the amount of feedback applied: a at frequency
response requires critically or overdamped pole pairs (
0.707).
Once the damping coefcient is determined, the expression for the high or low 3 dB frequency shift with the application of feedback takes a form similar to the single pole
case with an additional factor:
1L
H f = K(H , kH ) D 1H or L f =
, (21)
K(L , kL ) D
where k is the ratio of the initial pole spacing (k 1), is
the pole-pair damping coefcient, 1H and 1L are the poles
closest to the midband, and the factor, K(, k), is given by:
K(, k) =

2k
k+1


1 2 2 +

(1 2 2 )2 + 1

(22)

This relationship is shown in Fig. 4 for a variety of initial

pole spacing
ratios, k. In most amplier applications, 0.9 <
K(, k) < 2: some designers use a K(, k) 1 as a rstorder approximation.
For ampliers where the frequency response must be
described by more than two poles, the description of the
frequency shift is even more complicated. Fortunately, ampliers with a high- or low-frequency response that is described by more than two poles are reasonably modeled
by considering them to be two-pole systems (1). Equation
(26) adequately approximates the change in bandwidth for
these higher-order systems.
For example, an amplier has a midband gain, A0 =
1000 and has frequency response described by one lowfrequency pole, fL = 10, and two high-frequency poles, fH1 =
10 kHz and fH2 = 100 kHz, and feedback is applied so that
the midband gain is reduced to A0f = 140. The new low and
high 3 dB frequencies can be determined as follows: The
return difference is the ratio of the two gains:

D, and fl :
fHf = K(H , k)D f1 = (1.277)(7.4286)(1 MHz) = 9.12 MHz
The resultant frequency response plots are shown in Fig
5.
Input and Output Impedance
The input and output impedance of a feedback amplier
can be selectively increased or decreased through the application of feedback. As has been seen in the previous
sections, general discussions provide great insight into
many of the properties of feedback systems. To consider
the design of electronic feedback ampliers, it is necessary,
however, to specify the details of the feedback sampling
and mixing processes and the circuits necessary to accomplish these operations. The sampling and mixing processes
have a profound effect on the input impedance, the output
impedance, and the denition of the forward-gain quantity that undergoes quantied change due to the application of feedback. This subsection analyzes the various idealized feedback congurations. The following section looks
at practical feedback congurations.
The mixing and the sampling processes for a feedback
amplier utilize either voltages or currents. Voltage mixing
(subtraction) implies a series connection of voltages at the
input of the amplier: Current mixing implies a shunt connection. Voltage sampling implies a shunt connection of the
sampling probes across the output voltage: Current sampling implies a series connection so that the output current
ows into the sampling network. Either type of mixing can
be combined with either type of sampling. Thus, a feedback
amplier may have one of four possible combinations of the
mixing and sampling processes. These four combinations
are commonly identied by a hyphenated term: (mixing
topology)(sampling topology). The four types are as follows:

Shuntshunt feedback (current mixing and voltage

sampling)

Shuntseries feedback (current mixing and current

sampling)

The low-frequency response is described by a single pole;

thus the low 3 dB frequency is changed by a factor of D:

Seriesshunt feedback (voltage mixing and voltage

sampling)

Seriesseries feedback (voltage mixing and current

sampling)

The high-frequency response is described by two poles with

ratio, k.
k=

2H
f2H
10 MHz
=
=
= 10.
1H
f1H
1 MHz

The damping coefcient for the two poles are found to be:
1 + 10
1+k
=
H =

= 0.6508
2 10(7.14286)
2 k(1 + f Ao )
Notice that the high poles of the feedback amplier are
slightly underdamped and that there will be a small
bump ( 0.1 dB) in the frequency response as a result.
The high 3 dB frequency, fHf , is then found from K( H , k),

The four basic feedback amplier topologies are shown

schematically in Fig. 6. A source and a load resistance have
been attached to model complete operation. In each diagram the input, feedback, and output quantities are shown
properly as voltages or currents. Forward gain, A, must be
dened as the ratio of the output sampled quantity divided
by the input quantity that undergoes mixing. As such it is a
transresistance, current gain, voltage gain, or transconductance. The feedback network, as described by the feedback
ratio (f), must sample the output quantity and present a
quantity to the mixer that is of the same type (current or
voltage) as the input quantity. As such it is a transconductance, current gain, voltage gain, or transresistance. Table
1 lists the appropriate quantities mixed at the input, the

Ampliers, Feedback

Figure 4. High 3 dB frequency as a function of and nonfeedback pole spacing.

Figure 5. An example of the effect of feedback on frequency response.

output sampled quantity, the forward gain, and the feedback ratio for each of the four feedback amplier topologies.
It is important to remember that the product, fA, must be
dimensionless and, in the midband region of operation, positive.
In the previous section, all benets of feedback were
discussed except the modication of input and output
impedance. The specic denitions of the four feedback amplier topologies allow for that discussion to begin here.
The mixing process alters the input impedance of a negative feedback amplier. Heuristically, one can see that
subtraction of a feedback quantity at the mixing junction
increases the input quantity necessary for similar performance. Thus, subtracting current (shunt mixing) requires
an increase in overall input current and decreases the input impedance. Similarly, subtracting voltage (series mixing) requires an increase in overall input voltage and increases input impedance.
Shunt Mixing Decreases the Input Resistance. For the
shuntshunt feedback amplier (Fig. 7), the voltage across
its input terminals (arbitrarily identied as v) and the input current, ii , are related by the feedback amplier input
resistance, Rif :

Similarly, the forward-gain amplier has input quantities

related by its input impedance, Ri :

The two input currents, ii and i , are related through the

forward gain and the feedback ratio:

Figure 7. Input and output resistance for shuntshunt feedback.

Therefore, combining Eqs. (32) and (33) yields

The input resistance to feedback amplier is the input resistance of the forward-gain amplier reduced by a factor
of the return difference. Shuntseries feedback amplier
input resistance is similarly derived (replacing RM by AI ).
The same basic reduction in input resistance occurs:

Series Mixing Increases Input Resistance. For the

seriesseries feedback amplier of Fig. 8, the voltage
across its input terminals, vi , and the input current
(arbitrarily identied as i) are related by the feedback
amplier input resistance, Rif :

Ampliers, Feedback

Figure 6. Feedback amplier topologies.

(a) Shuntshunt feedback. (b) Shuntseries
feedback. (c) Seriesshunt feedback. (d)
Seriesseries feedback.

Figure 8. Input and output resistance for seriesseries feedback.

Similarly, the forward-gain amplier has input quantities

related by its input impedance, Ri :

The two input voltages, vi and v , are related through the

forward gain and the feedback ratio:

Therefore, combining Eqs. (37) and (38) yields

The input resistance to feedback amplier is the input resistance of the forward-gain amplier increased by a factor
of the return difference. Seriesshunt feedback amplier
input resistance is similarly derived (replacing GM by AV ).
The same basic reduction in input resistance occurs:

Resistors shunting the input, such as biasing resistors,

often do not t within the topological standards of series
mixing. Thus, they must be considered separate from the
feedback amplier to model feedback amplier characteristics properly using the techniques outlined in this and
other articles. Examples of such resistors are found in the
next section of this article.
The sampling process alters the output impedance of the
feedback amplier. As was the case for shunt mixing, shunt
sampling decreases the output resistance: Series sampling
increases the output resistance.

Shunt Sampling Decreases the Output Resistance. For the

shuntshunt feedback amplier of Fig. 7, the output resistance is measured by applying a voltage source of value,
v, to the output terminals with the input, ii , set to zero
value. A simplied schematic representation of that measurement is shown in Fig. 9. In this gure, the forwardgain amplier has been shown with its appropriate gain
parameter, RM , and output resistance, Ro .
The output resistance of the feedback system is the ratio,

The current, i, is calculated from Ohms law at the output

of the amplier:

Ampliers, Feedback

The output resistance of the feedback system is the ratio

The voltage, v, is given by

Since the input voltage, vi , has been set to zero value,

Figure 9. Schematic representation of shuntshunt feedback for

output resistance calculations.

Combining Eqs. (48) and (49) yields

The output resistance is then given by

The output resistance of the feedback amplier is the output resistance of the forward-gain amplier increased by a
factor of the return difference. Shuntseries feedback amplier output resistance is similarly derived (replacing GM
by AI ). The same basic increase in input resistance occurs:

Figure 10. Schematic representation of seriesseries feedback

for output resistance calculations.

In the case where the input current has been set to zero,

Resistances shunting the output, such as load resistances, do not t within the topological standards of series
sampling. Thus, they must be considered separate from the
feedback amplier to model feedback amplier characteristics properly using the techniques outlined in this and
other articles. The forward-gain parameters, AI and GM ,
must be calculated excluding these resistances.

Combining Eqs. (43) and (44) yields

PRACTICAL FEEDBACK CONFIGURATIONS

The output resistance of the feedback amplier is the output resistance of the forward-gain amplier decreased by a
factor of the return difference. Seriesshunt feedback amplier output resistance is similarly derived (replacing RM
by AV ). The same basic reduction in input resistance occurs:

Resistors that shunt the output terminals, such as a load

resistor, are considered as part of the feedback amplier.
The forward-gain parameter (RM or AV ) must be calculated
in a consistent fashion with the consideration of these elements.
Series Sampling Increases the Output Resistance. For the
seriesseries feedback amplier of Fig. 8, the output resistance is measured by applying a current source of value,
i, to the output terminals with the input, vi , set to zero
value. A simplied schematic representation of that measurement is shown in Fig. 10. In this gure, the forwardgain amplier has been shown with its appropriate gain
parameter, AV , and output resistance, Ro .

Previous discussions of feedback and feedback congurations have been limited to idealized systems and ampliers.
The four idealized feedback schematic diagrams of Fig. 6
identify the forward-gain amplier and the feedback network as two-port networks with a very specic property:
Each is a device with one-way gain. Realistic electronic
feedback ampliers can only approximate that idealized
behavior. In addition, in practical feedback ampliers there
is always some interaction between the forward-gain amplier and the feedback network. This interaction most often takes the form of input and output resistive loading
of the forward-gain amplier. The division of the practical
feedback amplier into its forward-gain amplier and feedback network is also not always obvious. These apparent
obstacles to using idealized feedback analysis can be resolved through the use of two-port network relationships
in the derivation of practical feedback amplier properties. Once amplier gain and impedance relationships have
been derived, the utility of the two-port representations becomes minimal and is typically discarded.
Identication of the Feedback Topology
Feedback topology is determined through careful observation of the interconnection of the feedback network and

Ampliers, Feedback

forward-gain amplier. Shunt mixing occurs at the input

terminal of the amplier. Thus, shunt mixing is identied
by a connection of feedback network and the forward-gain
amplier at the input terminal of rst active device within
the amplier; that is,

At the base of a BJT for a common-emitter or commoncollector rst stage

At the emitter of a BJT for a common-base rst stage

At the gate of a FET for a common-source or common-

been replaced by their equivalent y-parameter two-port

network representations so that parallel parameters can
be easily combined. A resistive load has been applied to
the output port; and, since shuntshunt feedback ampliers are transresistance ampliers, a Norton equivalent
source has been shown as the input. The forward-gain parameter of each two-port, y21 , is the transadmittance.
The basic feedback equation for a transresistance amplier takes the form:

drain rst stage, or

At the source of a FET for a common-gate rst stage

Series mixing occurs in a loop that contains the input
terminal of the forward-gain amplier and the controlling
port of the rst active device. The controlling port of a BJT
in the forward-active region is the base-emitter junction:
A FET in the saturation region is controlled by the voltage
across the gate-source input port. Series mixing is characterized by a circuit element or network that is both connected to the output and in series with the input voltage
and the input port of the rst active device.
Identication of the sampling is derived from direct observation of the connection of the output of the basic forward amplier and the feedback network. Shunt sampling
is typically characterized by a direct connection of the feedback network to the output node: Series sampling implies a
series connection of the amplier output, the feedback network, and the load. Two tests performed at the feedback
amplier output can aid in the determination of sampling
topology:

If the feedback quantity vanishes for a short-circuit

load, the output voltage must be the sampled quantity.
Thus, zero feedback for a short-circuit load implies
shunt sampling.

If the feedback quantity vanishes for an open-circuit
load, the output current must be the sampled quantity. Thus, zero feedback for an open-circuit load implies series sampling.
After the topological type has been identied, each amplier must be transformed into a form that allows for
the use of the idealized feedback formulations. This transformation includes modeling the amplier and the feedback network with a particular two-port representation
that facilitates combination of elements. Once the transformations are accomplished, the amplier performance parameters are easily obtained using the methods previously
outlined. The particular operations necessary to transform
each of the four feedback amplier topological types require separate discussion. Only the shuntshunt topology
is discussed in detail: The other three topologies use similar techniques that lead to the results shown in Fig. 13 and
described in Table 2.
ShuntShunt Feedback: a Detailed Derivation. Figure
11 is a small-signal model representation of a typical
shuntshunt feedback amplier. In this representation,
the forward-gain amplier and the feedback network have

The application of the basic feedback equation to this circuit in its current form is not immediately clear. It is necessary to transform the feedback amplier circuit into a
form that allows for easy application of the basic feedback
equation, Eq. (53). Such a transformation must meet the
previously stated feedback requirements:

The forward-gain amplier is to be a forward transmission system onlyits reverse transmission must
be negligible.

The feedback network is to be a reverse transmission
system that presents a feedback current, dependent
on the output voltage, to the amplier input port.
While a mathematically rigorous derivation of the transformation is possible, greater insight to the process comes
with a heuristic approach.
The two-port y-parameter representation, in conjunction with the shunt-shunt connection, is used to describe
the two main elements of this feedback amplier so that
all the input port elements of both two-port networks are
in parallel. Similarly, all output port elements are in parallel. It is well known that circuit elements in parallel may
be rearranged and, as long as they remain in parallel, the
circuit continues to function in an identical fashion. Hence,
it is possible, for analysis purposes only, to move elements
conceptually from one section of the circuit into another
(from the feedback circuit to the amplier circuit or the
reverse). The necessary conceptual changes made for the
transformation are as follows:

The source resistance, the load resistance, and all input and output admittances, y11 and y22 , are placed
in the modied amplier circuit. While inclusion of
the source and load resistance in the amplier seems,
at rst, counterproductive, it is necessary to include
these resistances so that the use of the feedback properties produces correct results for input and output
resistance (after appropriate transformations).

All forward transadmittances, y21 (represented by current sources dependent on the input voltage, v1 ), are
placed in the modied amplier circuit.

All reverse transadmittances, y12 (represented by current sources dependent on the output voltage, vo ), are
placed in the modied feedback circuit.

10

Ampliers, Feedback

Figure 11. Two-port realization of a shuntshunt feedback amplier.

The dependent current source can be easily combined:

output admittance, y22 f

A feedback network composed solely of the feedback

network reverse transadmittance, y12 f

and

In virtually every practical feedback amplier, the reverse transadmittance of the forward-gain amplier is
much smaller than that of the feedback network (y12 a <
y12 f ) and the forward transadmittance of the feedback network is much smaller than that of the forward-gain amplier (y21 f < y21 a ). Thus approximate simplications of the
amplier representation can be made:

and

The shuntshunt feedback amplier circuit of Fig. 11 is,

with these changes and approximations, thereby transformed into the circuit shown in Fig. 12.
This transformed circuit is composed of two simple elements:

The original amplier, with its input shunted by the

source resistance; the feedback network short-circuit
input admittance, y11 f , and its output shunted by the
load resistance; the feedback network short-circuit

It is also important to notice that the input resistance, Rif ,

of this circuit includes the source resistance, Rs . As such,
it is not the same as the input resistance of the true amplier, Rin . The input resistance of the true amplier can be
obtained as

Similarly, the output resistance, Rof , of this circuit includes

the load resistance, RL : Similar operations may be necessary to obtain the true output resistance of the amplier.
The y-parameters of the feedback network can be obtained:

where i2 is the current entering the output port of the feedback network (see Fig. 10). With the determination of these
two-port parameters, the circuit has been transformed into
a form that is compatible with all previous discussions. The
forward-gain parameter (in this case, GM ) of the loaded basic amplier must be calculated, while the feedback ratio
has been determined from the two-port analysis of the feedback network:

Ampliers, Feedback

11

Figure 12. Redistributed shunt

shunt realization.

In the case of totally resistive feedback networks, the

shunting resistances can be found in a simple fashion:

rin = (yf )1 is found by setting the output voltage to

11
zero value, vo = 0, and determining the resistance from
the input port of the feedback network to ground.

rout = (yf )1 is found by setting the input voltage to
22
zero value, vi = 0, and determining the resistance from
the output port of the feedback network to ground.
The feedback ratio, f, is simply the ratio of the feedback
current, if , to the output voltage when the input port of the
feedback network, vi , is set to zero value. All idealized feedback methods can be applied to this transformed amplier,
and all previously derived feedback results are valid.
The other three feedback amplier topologies can be
similarly analyzed using various two-port parameters for
analysis:

Shuntseriesg parameters

Seriesshunth parameters

Seriesseriesz parameters
Such analysis leads to a characterization of the loading of
the basic forward amplier as is described in Fig. 13. As
is the case with the shuntshunt topology, individual elements within the feedback network may appear more than
once in the loaded basic forward amplier equivalent circuit. Table 2 summarizes the analysis of feedback amplier
properties.
STABILITY IN FEEDBACK AMPLIFIERS
Under certain conditions, feedback ampliers have the possibility of being unstable. This instability stems from the
frequency-dependent nature of the forward gain of the basic amplier, A, and the feedback factor, f. The frequency
dependency is exhibited in the changes in magnitude and
phase of the product, fA, as a function of frequency.
Instability can be visualized by studying the basic feedback equation as a function of frequency:

It is important that an amplier be designed so that stability is present at all frequencies, not only those in the midband region. If the product f(j)A(j) approaches unity
at any frequency, the denominator of Eq. (61) approaches
zero value: The total gain of the amplier approaches innity. This condition represents an output that is truncated
only by power supply limitations regardless of input magnitude and is an unstable condition that is intolerable in
ampliers. To avoid this instability, it is necessary to avoid
a simultaneous approach of |f(j)A(j)| = 1 and f(j)A(j)
= 180 . Since each pole can only provide a phase shift of
between 0 and 90 , the second condition is only possible
for ampliers that have high- or low-frequency responses
described by three or more poles. Simultaneously satisfying both conditions can be avoided if the magnitude of fA is
always less than unity when the phase angle of fA is 180 .
Designers of feedback ampliers typically verify that this
is the case through the use of amplier frequency-response
plots.
Gain Margin and Phase Margin
A frequency-response plot of the loop gain, fA, for a typical amplier is shown in Fig 14. The frequency at which
|f(j)A(j)| = 1 is identied as m and the frequency at
which f(j)A(j) = 180 is identied as p . Since m =
p , it is apparent that this is a stable amplierthat is, the
two instability conditions are not simultaneously met. It is,
however, important to ensure that the two conditions are
not met simultaneously with a margin of safety. The margin of safety is dened by the gain margin and the phase
margin of the feedback amplier.
Gain margin is dened as the difference in the loop gain
magnitude (in decibels) between 0 dB (unity gain) and the
loop gain magnitude at frequency p :

Phase margin is the difference between the loop gain phase

angle at frequency m and 180 :

Each safety margin is shown in Fig. 14. It is common

to specify the design of feedback ampliers with gain
and phase margins greater than 10 dB and 50 , respectively. These margins ensure stable amplier operation

12

Ampliers, Feedback

Figure 13. Feedback network loading of

basic forward amplier. (a) Shuntshunt
feedback. (b) Shuntseries feedback. (c)
Seriesshunt feedback. (d) Seriesseries
feedback.

bination of poles and zeros to the loop gain characteristic.

The most commonly used compensation techniques are as
follows:

Dominant pole compensation

Laglead (polezero) compensation

Lead compensation

Figure 14. Gain margin and phase margin.

over component parameter variation, temperature change,

and other variations found in typical ampliers.
Compensation
Two fundamental techniques are available for ensuring
amplier stability:

Reducing the midband loop gain, fA, of the amplier

Adding a compensation network to the amplier to
shape the loop gain frequency response so that the
phase and gain margins are positive and in an acceptable range
Careful design is required in each of these cases to ensure
stable amplier operation over typical performance conditions.
In many cases, decreasing the loop gain to achieve stability is not an acceptable design possibility. Additionally,
as is often the case in operational amplier circuits, the
feedback ratio, f, may be determined by the user rather
than the amplier designer and can range widely. In such
cases, compensation networks are added within the feedback loop of the amplier to increase the gain and phase
margins. Such compensation networks add poles or a com-

Each technique modies the gain and phase proles of the

basic forward amplier through pole and zero manipulation.
In dominant pole compensation, the amplier is modied by adding a dominant pole that is much smaller in
magnitude than all other poles in the amplier gain function: Typically it is chosen so that the loop gain, fA, reaches
0 dB at the frequency of the next pole (the rst pole of the
uncompensated amplier). Consequently, the modied loop
gain falls below 0 dB before the nondominant poles shift
the total phase shift near 180 and the circuit is inherently
stable. Dominant pole compensation will typically result in
a phase margin of approximately 45 .
The location of the new compensation pole can be determined by modeling the loop gain response with a single
pole and setting its value to 0 dB at the rst pole of the
uncompensated amplier:

Solving Eq. (64) for the compensation pole frequency, c ,

results in:

If the design goals of the feedback amplier includes a

range of feedback ratios, the frequency of the compensation pole is determined by the maximum value of the feed-

Ampliers, Feedback

back ratio. That is, c is chosen to be the smallest value

predicted by Eq. (65).
An example of dominant pole compensation is shown
in Fig. 15 in the frequency domain. For clarity, the gain
plots are represented by straight-line Bode approximations, while the exact phase plots are retained. The example amplier is described by a midband gain of 60 dB with
poles at 1 MHz, 5 MHz, and 50 MHz: the feedback ratio is
f = 0.1.
The possibility of feedback amplier instability is focused at the frequency where |fA| = 1 or equivalently where
|A|dB = 20 log(f). For this particular three-pole example,
instability may occur at m 21 MHz. Here the phase margin is very small and negative ( 7 ). After compensation,
the focus is again centered where the gain plot (now compensated) intersects the negated feedback ratio plot. The
addition of the compensation pole, c , shifts this intersection to the frequency of the rst uncompensated pole, p1 .
For this example, the compensation pole is placed at 10
kHz and yields a phase margin of 43 and a gain margin
of 14 dB.
Dominant pole compensation reduces the open-loop
bandwidth drastically. Still, it is common in many circuits
with inherently large gain: Operational ampliers commonly utilize dominant pole compensation.
Leadlag (or polezero) compensation is similar to dominant pole compensation with one major exception. In addition to a dominant pole, a higher-frequency zero is added.
This zero is used to cancel the rst pole of the uncompensated amplier. The added dominant pole can then be chosen so that the gain reaches 0 dB at the frequency of the
next pole (the second pole of the uncompensated amplier).
Leadlag compensation has a distinct bandwidth advantage over dominant pole compensation.
The location of the new compensation pole can be determined in a similar fashion to the method utilized under
dominant pole compensation with the exception that the
loop gain (without the rst original pole) is to reach 0 dB
at the second pole of the uncompensated amplier. Solving
Eq. (64) for the compensation pole frequency, c , results in:

13

margin of 48 , and a gain margin of 20 dB.

Lead compensation can lead to the largest bandwidth
of the three most common compensation networks. Here,
as in leadlag compensation, a pole and a zero are added.
The zero is used to cancel the second pole of the uncompensated amplier, and the added pole is positioned at a
frequency higher than the zero. The objective is to reduce
the phase shift of the uncompensated amplier at the frequency where the loop gain reaches 0 dB (m ). Lead compensation can be extremely effective in feedback ampliers
where there are two or three dominant poles in the uncompensated amplier.
The previously described, uncompensated amplier is
compensated with a lead polezero pair and the frequency
domain results are displayed in Fig. 17. After compensation, the focus is again centered where the gain plot (now
compensated) intersects the negated feedback ratio plot.
The addition a zero at the second uncompensated pole, p2 ,
and a high-frequency compensation pole, c , shifts this intersection a frequency beyond the second uncompensated
pole, p2 . For this example, the high-frequency pole was
chosen at 500 MHz. This design choice leads to a positive
phase margin of 35 and a gain margin of 15 dB. Notice
that with lead compensation there is no signicant reduction in the frequency response of the feedback amplier.
A passive component circuit implementation of each of
the three compensation techniques is schematically shown
in Fig. 18. For the circuit of Fig. 18(a), the compensation
network component values are chosen so that

where Ao , Ro , and p1 are the midband gain, the output resistance, and the rst pole frequency, of the basic forward
amplier, respectively. For the circuit of Fig. 18(b), the compensation network component values are chosen so that

and

As with dominant pole compensation, design goals including a range of feedback ratios lead to the determination of
frequency of the compensation pole by the maximum value
of the feedback ratio. That is, c is chosen to be the smallest
value predicted by Eq. (66).
The previously described, uncompensated amplier is
compensated with a laglead polezero pair and the frequency domain results are displayed in Fig. 16. The possibility of feedback amplier instability is again focused at
the intersection of the gain and the negated feedback ratio
plots. After compensation, the focus is centered where the
gain plot (now compensated) intersects the negated feedback ratio plot. The addition of the compensation pole, c ,
and a zero at the rst uncompensated pole, p1 , shifts this
intersection to the frequency of the second uncompensated
pole, p2 . The previously identied amplier parameters
lead to a compensation pole at 50 kHz, a positive phase

For the circuit of Fig. 18(c), the compensation network component values are chosen so that

and

While the placement of a compensation network at the

output of the basic forward amplier is an effective technique for feedback topologies with shunt sampling, other
placement may be necessary. In particular, connections at
the output of a feedback amplier with series sampling
are not within the feedback loop and are therefore invalid.
In such cases, alternate placement of the compensation is

14

Ampliers, Feedback

Figure 15. Bode diagram for a dominant pole compensated amplier.

Figure 16. Bode diagram for a laglead compensated amplier.

Figure 17. Bode diagram for a lead compensated amplier.

necessary. One common placement intersperses the compensation network between individual gain stages of the
amplier. Similarly, it is possible to compensate a feedback amplier within the feedback network rather than
the basic forward amplier. Unfortunately, analysis of compensation within the feedback network is often extremely
complex due to the loading of the basic forward amplier
by feedback network components.

Ampliers, Feedback

15

J. W. Nilsson and S. Riedel, Electric Circuits, 7th. Ed., Prentice

Hall, New York, 2004.
S. Rosenstark, Feedback Amplier Principles, New York: Macmillan, 1986.
A. S. Sedra, K. C. Smith, Microelectronic Circuits, 5th. Ed., Oxford
University Press, New York, 2004.
D. L. Schilling, C. Belove, Electronic Circuits, 3rd ed., New York:
McGraw-Hill, 1989.
T. F. Schubert, Jr. E. M. Kim, Active and Non-Linear Electronics,
New York: Wiley, 1996.
R. Spencer and M. Ghausi, Introduction to Electronic Circuit Design, Prentice Hall, New York, 2003.

THOMAS F. SCHUBERT Jr.

University of San Diego, San
Diego, CA

Figure 18. Compensation networks. (a) Dominant pole compensation. (b) Laglead (polezero) compensation. (c) Lead compensation.

BIBLIOGRAPHY
1. T. F. Schubert, Jr. A heuristic approach to the development
of frequency response characteristics in the design of feedback ampliers, Proc. 1996 ASEE/IEEE Frontiers Educ. Conf.,
November 1996, pp. 340343.

Reading List
H. W. Bode, Network Analysis and Feedback Amplier Design, D.
Van Nostrand Company, Princeton, NJ, 1945.
F. C. Fitchen, Transistor Circuit Analysis and Design, Princeton,
NJ: Van Nostrand, 1966.
M. S. Ghausi, Electronic Devices and Circuits: Discrete and Integrated, New York: Holt Rinehart and Winston, 1985.
P. R. Gray, R. G. Meyer, Analysis and Design of Analog Integrated
Circuits, 4th. Ed., John Wiley & Sons, Inc., New York, 2001.
D. H. Horrocks, Feedback Circuits and Op Amps, London: Chapman and Hall, 1990.
P. J. Hurst, A comparison of two approaches to feedback circuit
analysis, IEEE Trans. Educ., 35: 253261, 1992.
J. Millman, Microelectronics, Digital and Analog Circuits and Systems, New York: McGraw-Hill, 1979.
J. Millman, C. C. Halkias, Integrated Electronics: Analog and Digital Circuits and Systems, New York: McGraw-Hill, 1972.

FIR FILTERS, DESIGN

555

There are many common applications of FIR filters, including

1. Differentiators: These filters have many uses in digital
and analog systems, such as the demodulation of frequency modulated (FM) signals (16).
2. Decimators and interpolators: FIR filters appear in
multirate systems as interpolator or decimator filters
forming filter banks. Interpolators and decimators can
be implemented, for instance, by comb filters, which are
a special class of multiband filters, commonly used in
the demodulation of video signals (16).
3. Power spectrum estimation: This process is used in digital speech, sonar, and radar systems. The moving average (MA) estimator is an example of an FIR filter (7).
4. Wiener and Kalman filters: These filters have been used
for the estimation of signals of interest, and they both
can be interpreted as extensions of FIR filters (8).
5. Adaptive filters: These systems have been widely used
in communication, control, and so on. Examples of this
type of system include adaptive antennas, digital equalization receivers, adaptive noise-canceling systems, and
system modelers. Adaptive FIR filters are widely employed because the adaptation of the filters coefficients
searches for a unique optimal solution and does not
cause instability in the transfer function, which is not
always true for adaptive IIR filters (810).
6. Wavelets: The wavelet transform has been used as an
orthogonal basis for decomposing signals in multiresolution layers. In image processing, it has been used for
compressing the image data. In this setup, FIR filters
have been normally employed as the basis function of
the wavelet transform (11).

FIR FILTERS, DESIGN

PROPERTIES OF FIR FILTERS

Filtering is a method of signal processing by which an input

signal is passed through a system in order to be modified,
reshaped, estimated, or generically manipulated as a way to
make it conform to a prescribed specification. In a typical application, filters are a class of signal-processing systems that
let some portion of the input signals frequency spectrum pass
through with little distortion and almost entirely cutting off
the undesirable frequency band. Digital filtering is a method
by which discrete time sequences are filtered by a discrete
system.
Finite-duration impulse response (FIR) filters are a class
of digital filters having a finite-length sequence as output
when an impulse is applied to its input. The details of the
FIR filtering method, its properties, and its applications will
be considered in the following pages. Analytical tools that enable us to perform the time and frequency analysis of FIR
filters will be examined and, in addition, systematic procedures for the design of these filters will be presented.
There are advantages and disadvantages in using FIR filters as opposed to infinite-duration impulse response (IIR)
filters. FIR filters are always stable when realized nonrecursively, and they can be designed with exact linear phase,
which is not possible with IIR filters. However, the approximation of sharp cutoff filters may require a lengthy FIR filter,
which may cause problems in the realization or implementation of the filter.

An FIR filter, with an input x(n) and output y(n), can be characterized by the following difference equation

y(n) = a(0)x(n) + a(1)x(n 1) + + a(N 1)x(n N + 1)

=

N1

a(i)x(n i)

(1)

i=0

where N is the filter length, a(n) (for 0 n N 1) are the

coefficients of the causal linear time-invariant system, and
the input and output samples are taken at a discrete time
t nT, n 0, 1, . . ., with T as the sampling period. From
Eq. (1), we notice that the present output sample y(n) is
formed by the combination of the present x(n) and the past
N 1 input samples weighted by the filters coefficients in
order attain some desired response.
Alternatively, Eq. (1) can be written as the convolution between the input signal samples x(n) and the impulse response
sequence h(n) of the filter (16), that is,

y(n) =

N1

h(n i)x(n)

i=0

N1

(2)
h(i)x(n i)

i=0

Clearly, then, h(n) equals a(n), for 0 n N 1.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

556

FIR FILTERS, DESIGN

Stability
A digital system is said to be bounded inputbounded output
(BIBO) stable if and only if any bounded discrete time sequence applied to the systems input yields a bounded output
sequence. Therefore, the BIBO stability criterion can be written as (16)

For an FIR filter as expressed in Eq. (2), we obtain



N1




| y(n)| = 
h(i)x(n i)
 i=0

By using the well known Schwartzs inequality, we get
N1

Linear Phase
In many applications, the design of a signal processing system with linear phase is desirable. Nonlinear phase causes
distortion in the processed signal, which is very perceptible in
applications like data transmission, image processing, and so
on. One of the major advantages of using an FIR filter is that
it can be designed with an exact linear phase, a task that
cannot be done with IIR filters. A linear-phase system does
not cause any distortion, only delay.
The frequency response of an FIR filter, as described in Eq.
(4), is given by

If |x(n)| < , n, then | y(n)| < , n

| y(n)|

ficients to process complex signals. Despite these cases, we

concentrate our efforts here on the analysis and design of FIR
filters with real coefficients, without much loss of generality.
The interested reader, however, may refer to (12,13).

|h(i)x(n i)|

H(e j ) =

i=0

N1

N1

h(n)e jn

(6)

n=0

|h(i)||x(n i)|

The magnitude M() and phase () responses of the filter

are respectively defined as

i=0

As the BIBO criterion imposes,

M() = |H(e j )|

|x(n)| M < , n
and
we thus have

|y(n)| M

N1

|h(i)|

() = arg [H(e j )]


Im[H(e j )]
= tan1
Re[H(e j )]

(3)

i=0

Since the filters coefficients are assumed finite, the righthand side of Eq. (3) is always finite and so is y(n). This implies that an FIR filter is always stable since the linear system coefficients are finite.
Alternatively, we can test filter stability by identifying its
poles. The stability of any digital filter can also be verified by
checking the poles of its transfer function. A necessary and
sufficient condition for BIBO filter stability is that all system
poles are inside the unit circle (16). In the case of an FIR
filter, its transfer function is obtained as

H(z) =

N1

where Im(.) and Re(.) represent the imaginary and real parts
of a complex number, respectively. The expression in Eq. (6)
can also be written as

H(e j ) =

N1

Now, by assuming that h(n) is a sequence of real numbers,

the phase response is given by

h(n)z

(4)

() = tan1

n=0

H(z) = h(0) + h(1)z1 + + h(N 1)z(N1)

h(0)zN1 + h(1)zN2 + + h(N 1)
zN1


N1
n=0 h(n) sin(n)
N1
n=0 h(n) cos(n)

(7)

To obtain a linear-phase response, () is constrained to be

of the form

which can be written as

h(n)[cos(n) j sin(n)]

n=0

() = 0

(5)

From Eq. (5), we see that an FIR filter of length N has N 1

poles, all located at the origin of the z-plane, and therefore, it
is always stable. As will be seen later, an FIR filter can be
realized nonrecursively and recursively. The stability of an
FIR filter is guaranteed only when the realization is nonrecursive since the quantization of filter coefficients in a recursive realization with finite precision arithmetic may
cause instability.
In some applications, like speech, image coding, and signal
transmission, it is possible to use FIR filters with complex coef-

(8)

for , where 0 is the constant delay of the filter.

When using the results of Eq. (7) and Eq. (8), we get


tan


N1
n=0 h(n) sin(n)
= 0
N1
n=0 h(n) cos(n)

which can be written as

N1
n=0
tan(0 ) = N1
n=0

h(n) sin(n)
h(n) cos(n)

(9)

FIR FILTERS, DESIGN

Eq. (9) admits two solutions. The first is a trivial one when
0 0, which implies h(n) (n); that is, the filters impulse
response is an impulse at n 0. This solution has very little
utility. The second solution is when 0 0, and thus, Eq. (9)
can be expressed as

N1
sin(0 )
n=0 h(n) sin(n)
= N1
cos(0 )
h(n) cos(n)
n=0

Consequently,
N1

h(n)[sin(n) cos(0 ) cos(n) sin(0 ) = 0

n=0

and accordingly,
N1

h(n) sin(n 0 ) = 0

(10)

n=0

The solution of Eq. (10) can be shown to be the following set

of conditions

N1
2
h(n) = h(N n 1)

(11a)

0 =

(11b)

It turns out that different solutions are obtained depending

on the value of N being either even or odd, and depending on
the two possibilities as expressed by Eq. (11b), that is, symmetrical (even symmetry) or antisymmetrical (odd symmetry)
filters. Therefore, from the set of conditions defined by Eq.
(11), it is practical to define four types of linear-phase FIR
filters, namely:

Type III. Length N odd and symmetrical impulse response

Type IV. Length N odd and antisymmetrical impulse response
Examples of these four types of linear-phase FIR filters are
depicted in Fig. 1. When N is even, see Fig. 1(a) and Fig. 1(b),
we notice that the axis of symmetry is located between two
samples; that is, the constant delay 0 is not an integer value.
Meanwhile, if N is odd, 0 is integer, and thus, the location of
the axis of symmetry is over a sample, as observed in Fig.
1(c) and Fig. 1(d). For N odd and an antisymmetrical impulse
response filter, the middle sample must be zero to satisfy this
symmetry, as seen in Fig. 1(d).
In some applications, the long delay associated with linearphase FIR filters is not allowed and then a nonlinear-phase
filter is required. An example of such filter is the filter with
minimum-phase distortion, the zeros of which are located
strictly inside the Z-domain unit circle. This class of filters
can be designed by starting from Type I and III (even symmetric) linear-phase filters as mentioned, for instance, in
(12,14,15).
Frequency Response
The four types of FIR linear phase filters defined before have
distinct frequency responses, as we shall see below.
Type I. From Eq. (6) and having that h(n) h(N n 1),
we can write the frequency response as

H(e j ) =

N/21

h(n)[e jn + e j(Nn1) ]

n=0

which can be written in the form

H(e j ) =

N/21

h(n)e j

n=0

Type I. Length N even and symmetrical impulse response

Type II. Length N even and antisymmetrical impulse response
h(n)

h(n)

Axis of
symmetry

N 1
2

 N/21

n=0

N 1
2



e j

N 12n
2

+ e j

N 12n
2




N 1 2n
2h(n) cos
2

Axis of
symmetry

(a)

(b)

h(n)

Axis of
symmetry

(c)

= e j

557

h(n)

Axis of
symmetry

6
0

(d)

n
Figure 1. Typical impulse responses for linearphase FIR filters: (a) Type I: N even, symmetric filter; (b) Type II: N even, antisymmetric filter; (c)
Type III: N odd, symmetric filter; (d) Type IV: N
odd, antisymmetric filter.

558

FIR FILTERS, DESIGN

Finally, letting
a(n) = 2h

N
2

for n 1, . . ., (N 1)/2, and b(0) h(N 1/2), we get

H(e j ) = e j

N 1
2

 (N1)/2

b(n) cos(n)

(14)

n=0

for n 1, . . ., N/2, the last summation in the above equation

can be written as




 N2
1
N 1

(12)
H(e j ) = e j 2
a(n) cos n
2
n=1
which is the desired result, having a pure delay term and an
even-symmetric amplitude term.
Type II. For this case, the frequency response is similar to
Type I above, except that in Eq. (12) instead of cosine summations we have sine summations multiplied by j or, equivalently, multiplied by ej(/2). Hence, Eq. (12) should be replaced
by

H(e

)=

N/2





j N 21
j( /2)
e
e
a(n) sin

n=1

1
n
2


(13)

Type III. By applying the even symmetry condition to Eq.

(6) with N odd, we obtain

H(e j ) = h
=h

N 1
2

N 1
2

+ e j

N 1
2

e j

N 1
2

(N3)/2

h(n)e jn

which is the desired result.

Type IV. For this case, the frequency response is similar to
Type III, except that in Eq. (14) instead of cosine summations,
we have, as before, sine summations multiplied by ej/2; that
is,

H(e j ) = e j

j N 21

 (N3)/2

H(z) =

N 1
2

where h(N 1/2) is the middle sample of the filters impulse

response. The above equation can also be expressed as


N 1



N 1
h
H(e j ) = e j 2
2

N 1 
(N3)/2


n
+
2h(n) cos
2
n=0
Now, when replacing the variable n by (N 1)/2 n, we
obtain

N 1



N 1
H(e j ) = e j 2
h
2


N 1 
(N1)/2


n cos(n)
+
2h
2
n=1

N 1
2

N/21



h(n) zn z(Nn1)

N/21

h(n)z

n=0

n=0

b(n) = 2h

(15)

The locations of zeros in the Z-plane for a linear-phase FIR

filter is highly restricted by the set of conditions defined by
Eq. (11). When N is even, by applying these conditions to the
transfer function in Eq. (4), we obtain





 j
N 1 n
j N 21 n
2
h(n) e
+e

Letting

b(n) sin(n)

n=0

The above equation can be written as

N 1



j
j N 21
h
H(e ) = e
2

(N1)/2

ej2

Locations of Zeros

N/21
=

n=0

(N3)/2

In this specific case, b(0) h(N 1/2) 0.

In Table 1, we summarize the properties of the four types
of linear-phase FIR filters, as given in Eq. (1215).

h(n)e jn e j

N 1
2

n=0

n=0

n=0

N 1
2



N 12n
2

N 12n
2



(16)



N 12n 
N 12n 
2
2
h(n) z
z

N 1
2

where the positive sign applies for symmetrical filters and the
negative sign for antisymmetrical filters. Now, by examining
the numerator of Eq. (16), that is, the zeros of the transfer
function, we see that if we replace z by z1, we obtain the
same or the negative numerator, respectively, for symmetrical and antisymmetrical filters. In both cases, the positions of
the zeros are similar. Therefore, if the transfer function has
a zero at point z ej, it will also have a zero at point
z (1/ )ej, where is the magnitude, and is the phase of
the mentioned zero. In such a case, the numerator of H(z) is
said to have the mirror-image zero property with respect to
the unit circle.
Similarly, for N odd we obtain the following transfer function

h
H(z) =

N 1
2

(N3)/2
n=0



N 12n 
N 12n 
2
2
h(n) z
z

N 1
2

(17)

where, as before, the positive sign applies for symmetrical filters and the negative sign for antisymmetrical filters. Also, in
this case, we see that the numerator of H(z) has the mirrorimage zero property.
Hence, the locations of the zeros of all four types of linearphase FIR filters have the mirror-image common property.
This implies that the locations of zeros have the following possibilities:

FIR FILTERS, DESIGN

559

Table 1. Characteristics of Linear-Phase FIR Filters

H(e j)

Type

even

symmetrical

II

even

antisymmetrical

e j (N1/2)e J(/2)

III

h(n)

odd

symmetrical

j (N1/2)

j (N1/2)

Coefficients

1
a(n) sin n
n1
2

(N1)/2

N/2

b(n) 2h

b(0) h

IV

odd

antisymmetrical

e j (N1/2)e j(/2)

(N1)/2

n0

z11 = e j , z12 = e j , z13 =

1 j
1
e , z14 = e j

2. Complex zeros located on the unit circle appear as a set

of conjugate pairs of the form
z21 = e , z22 = e
j

3. Real zeros off the unit circle appear as a set real pairs
of the form
z31 = , z32

1
=

N1
2

N1
n
2
n 1, . . ., (N 1)/2

b(n) sin(n)

b(n) 2h

b(0) h

1. Complex zeros located off the unit circle appear as a set

of four conjugate reciprocal zeros of the form

N
n
2
n 1, . . ., N/2

a(n) 2h

N1
n
2
n 1, . . ., (N 1)/2

b(n) cos(n)

n0

N
n
2
n 1, . . ., N/2

a(n) 2h

1
a(n) cos n
n1
2
N/2

N1
0
2

6. A type II linear-phase FIR filter must have a zero at

z 1. Thus, low-pass filters cannot be designed with
this type of filter.
7. A type IV linear-phase FIR filter must have zeros at
both z 1 and z 1. Therefore, either low-pass or
high-pass filters cannot be designed with this type of
filter.
Figure 2 depicts a typical plot of the zeros of a linear-phase
FIR filter.
FIR FILTER DESIGN
The complete design of FIR filters involves three distinct
stages, namely approximation, realization, and implementa-

z-plane

or
z13

z31 = , z32 =

z21
z11

4. Real zeros on the unit circle appear in an arbitrary

number

z31

z42

z41

z32

z41 = 1
z12

or
z14

z42 = 1
The locations of zeros at points z 1 have additional
importance. By examining the transfer function at
these points, it turns out that
5. A type I linear-phase FIR filter must have a zero at
z 1. Hence, high-pass filters cannot be designed
with this type of filter.

z22

Figure 2. Example of the locations of zeros of a linear-phase FIR

filter: In this case, z11, z12, z13, and z14 are four complex-valued zeros
that satisfy rule 1; the pair of complex zeros on the unit circle z21 and
z22 obey rule 2; the pair of real zeros z31 and z32 satisfy rule 3; real
zeros on the unit circle, like z41 and z42, may appear in any number,
obeying rule 4.

560

FIR FILTERS, DESIGN

tion. Approximation is the process by which a required set of

filter specifications yields a suitable transfer function with
the desired filter characteristics. The realization process
translates the transfer function obtained in the approximation stage into a digital network. Implementation is the process that transforms this digital network into a specific piece
of hardware or software code. Because they are easier to understand this way, we now analyze these tasks in their reverse order.

x(n)

z1

...

z1

h0

h1

h2

z1

...
hN 1

Implementation

y(n)

An FIR filter is a digital system, the implementation of which

can be accomplished by means of dedicated hardware, general
purpose hardware (e.g., digital signal processors), or computer programs. Both hardware and software forms are suitable for processing real-time and nonreal-time signals. Dedicated-hardware filters, however, tend to be much faster, thus
being able to process signals with higher frequency components and/or using high-order filters. The manufacturing
stage of these filters, however, can be a very cost- and timeexpensive process. In the other extreme, computer programs
are mainly used, although not restricted, to filter signals in a
nonreal-time fashion or to simulate the performance of practical systems. Generally speaking, filters implemented with
digital signal processors (DSPs) represent a good compromise
of cost and processing speed compared to the other two alternatives.
Currently, the two most well-known families of DSPs are
the TMS320 from Texas Instruments and the DSP56000 from
Motorola. Both families have DSPs that use fixed- or floatingpoint arithmetic, parallel processing, clock-rates from tens to
hundreds of MHz, and cost in the range of a few dollars to
several hundred dollars. Today, DSPs are becoming increasingly cheaper and faster, and this process shows no indication
of slowing down. For this reason, one can only predict this
type of implementation for FIR digital filters becoming more
and more popular in the future.

Figure 3. Direct-form realization of an FIR filter. Its derivation is

straightforward following Eq. (18).

nal y(n). Due to the chain of delay elements on the top of that
diagram, this structure is also referred to as the tapped delay
line or transversal filter.
Linear-Phase Direct Form. As seen before, FIR filters with
linear phase present a symmetrical or antisymmetrical transfer function. This fact can be used to halve the number of
multiplications needed to realize the filter. In fact, the transfer function of linear-phase FIR filters with length N even can
be written as

H(z) =

N/21



hn zn z(Nn1)

n=0

leading to the structure shown in Fig. 4.

Meanwhile, the transfer function of linear-phase FIR filters with length N odd can be written as

H(z) =

(N3)/2


n=0

N 1 
N 1 


hn zn z(Nn1) + h
z 2
2

and is suitable to be realized by the structure shown in Fig.

5. In both of these figures, the plus sign is associated to the

Realization
For any given transfer function, there is a wide variety of
network structures that are able to translate the mathematical aspect of the transfer function into an equivalent digital
circuit. In this section, we show some of the most commonly
used forms for realizing an FIR transfer function (16).
Direct Form. As given in Eq. (2), the transfer function of
FIR filters with length N assumes the form

H(z) =

N1

x(n)

z1
+

hn z

...

+
+/

z1

+/
z1

...

z1

+/
z1

...

(18)

n=0

where hn is the filter coefficient, corresponding to the filters

impulse response h(n), for 0 n N 1. The change in
notation, in this section, from h(n) to hn, is important to avoid
confusion with adaptive filters and to yield a more natural
representation of other realizations. The most natural way to
perform the operations in Eq. (18) is probably the direct form
shown in Fig. 3. This figure clearly depicts how, in this realization, each delayed value of the input signal is appropriately weighted by the corresponding coefficient hn and how
the resulting products are added to compose the output sig-

h0

h1

...

h(N 1)/2

+
y(n)
Figure 4. Direct-form realization of a linear-phase FIR filter with N
even: Type I and Type II filters. The reader should verify reduction
on the number of multiplications in the order of 50% when compared
to the general direct-form realization seen in Fig. 3.

FIR FILTERS, DESIGN

x(n)

z1

...

z1

z1

...

+
+/

+/
z1

+/
z1

h0

...

...

h1

z1

h(N 3)/2

h(N 1)/2
Figure 5. Direct-form realization of a linear-phase FIR filter
with N odd: Type III and Type IV filters. The reader should
verify reduction on the number of multiplications in the order
of 50% when compared to the general direct-form realization
seen in Fig. 3.

+
y(n)

symmetrical impulse response, and the minus sign is associated to the antisymmetrical case, as included in Table 1. It is
important to notice that the linear-phase direct forms shown
here preserve this important characteristic even when the
filter coefficients are quantized, that is, are represented with
a finite number of bits.
Cascade Form. Any FIR-filter transfer function can be factored into a product of second-order polynomials with real coefficients; that is,

H(z) = b0

M


(1 + b1 j z1 + b2 j z2 )

To obtain a useful relation between the lattice parameters

and the filters impulse response, we must analyze the recurrent relationships that appear in Fig. 8. These equations are
ei (n) = ei1 (n) + ki ei1 (n 1)

(20a)

ei (n) = ei1 (n 1) + ki ei1 (n)

(20b)

for i 1, . . ., N 1, with e0(n) e0(n) k0x(n), and

eN1(n) y(n). In the z domain, Eq. (20) becomes

Ei (n) = Ei1 (z) + ki z1 E i1 (z)

(19)

j=1

E i (z) = z1 E i1 (z) + ki Ei1 (z)

where M is the smallest integer greater or equal to (N 1)/2.

If N is even, then the coefficient b2M is equal to zero. The block
diagram representing Eq. (19) is shown in Fig. 6. Notice how
the second-order blocks appear in sequence, thus originating
the name of the cascade-form realization.

0(z) k0 X(z) and EN1(n) Y(z).

with E0(z) E
i(z), and
By defining the auxiliary polynomials, Hi(z) and H
the auxiliary coefficients hm,i as:

Lattice Form. Figure 7 depicts the block diagram of an FIR

lattice filter of length N, where e(m) and e(m) are auxiliary
signals that appear in lattice-type structures. This realization
is called lattice due to its highly regular structure formed by
concatenating basic blocks of the form shown in Fig. 8.

x(n)

Hi (z) = k0

z1
b11

z1

y(n)

...

z1
b12

z1
b21

i


Ei (z)
=
h zm
E0 (z) m=0 m,i

E (z)
H i (z) = k0 i
E 0 (z)

b0

z1

561

b1M

z1
b22

b2M

Figure 6. Cascade-form realization of an

FIR filter. Its derivation is straightforward following Eq. (19).

562

FIR FILTERS, DESIGN

x(n)

k0

k1

Figure 7. Lattice-form realization of a

FIR filter. Its name results from the intricate structure of each building block implementing Eq. (20).

z1

we can demonstrate, by induction, that these polynomials

obey the recurrence formulas (3)

Hi (z) = Hi1 (z) + ki zi Hi1 (z1 )

(21a)

H i (z) = zi Hi (zi )

(21b)

0(z) k0 and HN1(z) H(z). Therefore,

with H0(z) H
Hi1 (z) =

1
[H (z) ki zi Hi (z1 )]
1 k2i i

(22)

and then, the reflection coefficients ki can be obtained from

the direct-form coefficients hi by successively determining the
polynomials Hi1(z) from Hi(z), using Eq. (22), and making

k1

k2

...

H(z) =

for i 0, . . ., N 1.
The direct, cascade, and lattice structures differ from each
other with respect to a few implementation aspects. In general, the direct form is used when perfect linear-phase is essential. Meanwhile, the cascade and lattice forms present better transfer-function sensitivities with respect to coefficient
quantization, but their dynamic range may be an issue, as
their states can reach very high levels, forcing signal scaling
in fixed-point implementations (3,4).
Recursive Form. FIR filters are often associated to nonrecursive structures, as the ones previously seen here. However,
there are some recursive structures that do possess an FIR

ei1(n)

e~i1(n)

y(n) =

1 N1
zn
N n=0

1 zN 1
N z1 1

(23)

N1

hi x(n i)

i=0

If the input signal x(n) is known for all n, and null for n 0
and n L, a different approach to compute y(n) can be derived based on the discrete Fourier transform, which is usually implemented through an efficient algorithm commonly
referred to as the fast Fourier transform (FFT) (16). Complet-

1
N

y(n)
+

ki

Frequency-Domain Form. The computation of the output

signal of an FIR filter in the direct form is performed as

ei(n)

z1

z1

kN 1

The realization associated to this filter is seen in Fig. 9, where

the recursive nature of its transfer function is easily observed.
Other FIR filters can also be realized with recursive structures that make use of some form of zero/pole cancellation,
as exemplified here. This procedure, however, is somewhat
problematic in practice, as the quantization of the filter coefficients or of the filter internal signals can lead to a nonexact
cancellation, which can cause filter instability.

x(n)

ki

kN 1

As its name indicates, this filter determines, for each n, the

average value of N consecutive samples of a given signal.
Adding all N samples of the input signal at each time instant
n, however, can be a very time-consuming procedure. Fortunately, the same computation can be performed recursively
using the previous sum if we subtract the past input sample
delayed of N cycles and add the present input sample. This
procedure is equivalent to rewriting the moving-average
transfer function as
H(z) =

hi = hi,N

characteristic. Consider, for instance, the moving average-filter of length N

ki = hi,i
for i N 1, . . ., 0.
To determine the filters impulse response from the set of
lattice coefficients ki, we use Eq. (21a) to determine the auxiliary polynomials Hi(z) and make

...

k2

z1

y(n)

+ ... ...

zN

z1

ei(n)

Figure 8. Basic block for the lattice realization in Fig. 7.

Figure 9. Recursive-form realization of a moving-average filter. The

reader should be able to identify the feedback loop with the z1 block
that originates the transfer-function denominator term in Eq. (23).

;;;;
;;

FIR FILTERS, DESIGN

minimum attenuation, and p and s are the passband and

stopband edges, respectively. Based on these values, we define

H( )

1 + p

DBp = 20 log10

p s

(rad/s)

Figure 10. A typical set of specifications for a low-pass filter includes

definition of the maximum passband ripple p, the minimum stopband
attenuation s, as well as the passband and stopband edges p and
s, respectively.

ing these sequences with the necessary number of zeros (zeropadding procedure) and determining the resulting (N L)element FFTs of hn, x(n), and y(n), designated here as H(k),
X(k), and Y(k), respectively, we then have

1 + 
p

1 p
DBs = 20 log10 (s ) dB

1 p

563

dB

(23a)
(23b)

Bt = (s p ) rad/s

(23c)

Basically, DBp and DBs are the passband maximum ripple,

p, and the stopband minimum attenuation Sp, expressed in
decibel (dB), respectively. Also, Bt is the width of the transition band, where no specification is provided.
We now analyze the methods most used to convert this
typical set of specifications into a realizable transfer function.
Closed-Form Methods: The Kaiser Window. The most important class of closed-form methods to approximate a given frequency response using FIR filters is the one based on window functions.
A discrete-time frequency response is a periodic function of
, and, thus, can be expressed as a Fourier series given by
j ) =
H(e

Y (k) = H(k)X (k)

h(n)e jn

n=

where

and then,
y(n) = FFT1 {FFThn ]FFT[x(n)]}
Using this approach, we are able to compute the entire sequence y(n) with a number of arithmetic operations proportional to log2(L N), per output sample, as opposed to NL, as
in the case of direct evaluation. Clearly, for large values of N
and L, the FFT method is the more efficient one.
In the above approach, the entire input sequence must be
available to allow one to compute the output signal. In this
case, if the input is extremely long, the complete computation
of y(n) can result in a long input-output delay, which is objectionable in several applications. For such cases, the input signal can be sectioned, and each data block processed separately using the so-called overlap-and-save and overlap-andadd methods, as described in (3,4,16).
Approximation
As mentioned before, the approximation process searches for
the transfer function that best fits a complete set of specifications determined by the application in hand. There are two
major forms of solving the approximation problem: using
closed-form methods or using numerical methods. Closedform approaches are very efficient and lead to very straightforward designs. Their main disadvantage, however, is that
they are useful only for the design of filters with piecewiseconstant amplitude responses. Numerical methods are based
on iterative optimization methods, and, therefore, can be very
computationally cumbersome. Nevertheless, numerical methods often yield superior results when compared to closed-form
methods, besides being useful also for designing FIR filters
with arbitrary amplitude and phase responses.
A description of a low-pass filter is represented in Fig. 10,
where p is the passband maximum ripple, s is the stopband

h(n) =

1
2

/2
/2

j )e jn d
H(e

By making the variable transformation z ej, we have

H(z)
=

h(n)zn

n=

Unfortunately, however, this function is noncausal and of infinite length. These problems can be solved, for instance, by
truncating the series symmetrically for n (N 1)/2, with
N odd, and by multiplying the resulting function by z(N1)/2,
yielding

H(z)
H(z) =

(N1)/2

h(n)zn

N 1
2

(24)

n=(N1)/2

This approach, however, results in ripples known as Gibbs

oscillations appearing near transition bands of the desired
frequency response. An easy-to-use technique to reduce these
oscillations is to precondition the resulting impulse response
h(n) with a class of functions collectively known as window
functions. There are several members of this family of functions, including the rectangular window, the Hamming window, the Hanning (von Hann) window, the Blackman window,
the Adams window, the DolphChebyshev window, and the
Kaiser window. The rectangular window is essentially the approximation introduced in Eq. (24). Due to its importance, we
concentrate our exposition here solely on the Kaiser window.
Explanation of the other window functions can be found in
(16,17).
The most important feature of a given window function is
to control the transition bandwidth and the ratio between the

564

FIR FILTERS, DESIGN

ripples in the passband and stopband in an independent manner. The Kaiser window allows that control and is defined as
(4):

I0 ( )
w(n) = I0 ()

for |n| (N 1)/2

(25)

otherwise


1

2n
N1

and I0(.) is the zeroth-order modified Bessel function of the

first kind.
The ripple ratio resulting from the Kaiser window can be
adjusted continuously from the low value in the Blackman
window to the high value of the rectangular window by simply varying the parameter . In addition, the transition bandwidth can be varied with the filter length N. The most important property of the Kaiser window is that empirical formulas
are available relating the parameters and N to any specific
values of ripple ratio and transition bandwidth. In that manner, given the definitions in Eq. (24), a filter satisfying these
specifications can be readily designed based on the Kaiser
window as (4,6):

1. Determine h(n) using the Fourier series, assuming an

ideal frequency response

H(e

H(z) = z

N 1
2

(N1)/2

[w(n)h(n)] zn

n=(N1)/2

where is an independent parameter, is given by

=

7. Finally, compute

)=


1
0

High-pass, bandpass, or bandstop filters are designed in a

very similar manner. A few variables, however, must be redefined, as it is summarized in Table 2. For bandpass and bandstop filters, p1 and p2 are the passband edges with p1
p2, and s1 and s2 are the stopband edges with s1 s2.
Numerical Methods. Numerical methods are often able to
approximate the required frequency response using lower order filter than their closed-form counterparts. The design of
FIR filters using numerical methods is dominated in the literature by the Chebyshev and the weighted-least-squares
(WLS) approaches. The Chebyshev scheme minimizes the
maximum absolute value of a weighted error function between the prototypes transfer function and a given ideal solution. For that reason, Chebyshev filters are also said to satisfy
a minimax criterion. The universal availability of minimax
computer routines, has motivated their widespread use. The
WLS approach, which minimizes the sum of the squares of
the weighted error function, is characterized by a very simple
implementation. Its basic problem, however, results from the
well-known Gibbs phenomenon which corresponds to large error near discontinuities of the desired response.
To understand the basic problem formulation of the numerical methods for approximating FIR filters, consider the
transfer function associated to a linear-phase filter of length
N

for || c

H(z) =

for c ||

N1

h(n) zn

n=0

with c (p s)/2
2. Choose as the minimum of p and s.
3. Compute DBp and DBs with that value of in Eq. (24a)
and Eq. (24b), respectively.
4. Choose the parameter as follows:

0
for DBs 21

0.5842(DB 21)0.4 + 0.07886(DB 21)

s
s
=

for
21
< DBs 50

0.1102(DBs 8.7)
for DBs > 50
5. Choose the value of D as follows:

0.9222
D = DBs 7.95

14.36

for DBs 21
for DBs > 21

and then select the lowest odd value of the filter length
N such that
s D
N
+1
Bt
6. Determine w(n) using Eq. (25).

and assume that N is odd, and h(n) is symmetrical. Other

cases of N even or h(n) antisymmetrical can be dealt with in
a very similar way and are not further discussed here. The
frequency response of such filter is then given by
H(e j ) = e j

(N 1 )
2

H()

where

H()
=

0

a(n) cos(n)

(26)

n=0

with 0 (N 1)/2, a(0) h(0), and a(n) 2h(0 n), for

n 1, . . ., 0.
() is the desired frequency response, and W() is
If ej0H
a strictly-positive weighting function, consider the weighted
error function E() defined in the frequency domain as

E() = W ()[H()
H()]

(27)

The approximation problem for linear-phase nonrecursive

digital filters resumes to the minimization of some objective
function of E() in such a way that
|E()|

FIR FILTERS, DESIGN

565

Table 2. Filter Definitions to Use With the Kaiser Window

Type

Bt

H(e j)

low-pass

p s

p s
2

high-pass

s p

p s
2

min [(p1 s1), (s2 p2)]

bandpass

min [(s1 p1), (p2 s2)]

bandstop

1, for FF c
0, for c FF
0, for FF c
1, for c FF

Bt
2
Bt
c2 p2
2

W ()

By evaluating the error function defined in Eq. (27), with

() as in Eq. (26), on a dense frequency grid with 0 i
H
, for i 1, . . ., MN, a good discrete approximation of E()
can be obtained. For practical purposes, for a filter of length
N, using 8 M 16 is suggested. Points associated to the
transition band are disregarded, and the remaining frequencies should be linearly redistributed in the passband and
stopband to include their corresponding edges. Thus, the following vector equation results

Bt
2
Bt
c2 p2
2

E = [E(1 ) E(2 ) . . . E( MN )]T

(28a)

W = diag[W (1 ) W (2 ) . . . W ( MN )]

(28b)

A = [a(0) a(1) . . . a(0 )]

...

(28c)

cos(0 1 )
cos(0 2

(28d)
..

.
cos(0 MN )

(28e)

with M M, as the original frequencies in the transition

band were discarded.
The design of a lowpass digital filter as specified in Fig. 10,
using either the minimax method or the WLS approach, is
achieved making the ideal response and weight functions respectively equal to

1 for 0 p

H() =
0 for s

W () =

E() = min max [W ()|H () H()|]

A

With the discrete set of frequencies, in Eq. (28), this minimax

function becomes
H UA
A|]
E() min max [W|H
A

0 i

If we refer to Fig. 10, the minimax method effectively optimizes

This problem is commonly solved with the Parks-McClellan

algorithm (1820) or some variation of it (21,22). These methods are based on the Remez exchange routine, the solution of
which can be tested for optimality using the alternation theorem as described in (18). An important feature of minimax
filters is the fact that they present equiripple errors within
the bands, as can be observed in Fig. 11.
Numerical Methods: The Weighted-Least-Squares Approach. The weighted least-squares (WLS) approach minimizes the function


2

E()22 =
|E()|2 d =
W 2 ()|H()
H()|
d
0

For the discrete set of frequencies, in Eq. (28), this objective

function is estimated by
E()22 E T E
the minimization of which is achieved with
A = (U T W 2U )1U T W 2H
If we refer to Fig. 10, the WLS objective is to maximize the
passband-to-stopband ratio (PSR) of energies

and

1, for FF c1
0, for c1 FF c2
1, for FF

DB = 20 log10 min(p , s ) dB

where

...
...
..
.

c1 p1

H UA
A)
E = W (H

T
( ) H(

H = [H
1
2 ) . . . H( MN )]

cos(21 )
1
cos(1 )
1
cos(2 )
cos(22 )

U =
..
..
..
.
.
.
1 cos( MN ) cos(2 MN )

0, for FF c1
1, for c1 FF c2
0, for FF

c1 p1

Numerical Methods: The Chebyshev Approach. Chebyshev

filter design consists of the minimization over the set of filter
coefficients A of the maximum absolute value of E(); that is,

and then,

|H() H()|

1
p /s

for 0 p
for s

PSR = 10 log10

E 
p

Es

dB

566

FIR FILTERS, DESIGN

implementation of the latter. As applied to the nonrecursive

digital-filter design problem, the L2 Lawson algorithm is implemented by a series of WLS approximations using a timevarying weight matrix Wk, the elements of which are calculated by (23)

0
0.5

10

0
20
H( ) (dB)

0.5
30

2
Wk+1
() = Wk2 ()|Ek ()|

0.1

0.2

0.3

0.4

2.5

40
50
60
70
0

0.5

1.5

Convergence of the Lawson algorithm is slow, as usually 10

to 15 WLS iterations are required in practice to approximate
the minimax solution. Accelerated versions of the Lawson algorithm can be found in (2325).
FIR filters can be designed based solely on power-of-two
coefficients. This is a very attractive feature for VLSI implementations, as time-consuming multiplications are avoided.
This approach is a very modern research topic, and interested
readers are referred to (12,26,27).

(rad/s)
Figure 11. Equiripple bands (passband in detail) are typical for FIR
filters approximated with the Chebyshev approach.

where Ep and Es are the passband and stopband energies, respectively; that is,

Ep = 2

Es = 2

|H()|
d

|H()|
d

A typical lowpass nonrecursive digital filter designed with the

WLS method is depicted in Fig. 12, where the large ripples
near the band edges are easily identified.
In 1961, Lawson derived a scheme that performs a Chebyshev approximation as a limit of a special sequence of weighted
least-p (Lp) approximations with p fixed. The particular case
with p 2 thus relates the Chebyshev approximation to the
WLS method, taking advantage of the substantially simpler

0
0.5

10

0
20
H( ) (dB)

0.5
30

0.1

0.2

0.3

0.4

40
50
60
70
0

0.5

1.5

2.5

(rad/s)
Figure 12. Large errors near band discontinuities (passband in detail) are typical for FIR filters designed with the weighted-leastsquares approach.

BIBLIOGRAPHY
1. L. R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1975.
2. J. G. Proakis and D. G. Manolakis, Introduction to Digital Signal
Processing, New York: Macmillan, 1988.
3. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1989.
4. A. Antoniou, Digital Filters: Analysis, Design, and Applications,
2nd ed., New York: McGraw-Hill, 1993.
5. L. B. Jackson, Digital Filters and Signal Processing, 3rd ed., Norwell, MA: Kluwer, 1996.
6. D. J. DeFatta, J. G. Lucas, and W. S. Hordgkiss, Digital Signal
Processing: A System Design Approach, New York: Wiley, 1988.
7. S. M. Kay, Modern Spectral Estimation, Englewood Cliffs, NJ:
Prentice-Hall, 1988.
8. S. S. Haykin, Adaptive Filter Theory, 2nd ed., Englewood Cliffs,
NJ: Prentice-Hall, 1991.
9. B. Widrow and S. Stearns, Adaptive Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1985.
10. P. S. R. Diniz, Adaptive Filtering: Algorithms and Practical Implementation, Norwell, MA: Kluwer, 1997.
11. G. Strang and T. Nguyen, Wavelets and Filter Banks, Wellesley,
MA: Wellesley-Cambridge Press, 1996.
12. S. K. Mitra and J. E. Kaiser (eds.), Handbook for Digital Signal
Processing, New York: Wiley, 1993.
13. R. E. Crochiere and L. R. Rabiner, Multirate Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1983.
14. R. Boite and H. Leich, A new procedure for the design of high
order minimum phase FIR digital or CCD filters, Signal Process,
3: 101108, 1981.
15. Y. Kamp and C. J. Wellekens, Optimal design of minimum-phase
FIR filters, IEEE Trans. Acoust. Speech Signal Process., ASSP31: 922926, 1983.
16. E. O. Brigham, The Fast Fourier Transform and Its Applications,
Englewood Cliffs, NJ: Prentice-Hall, 1988.
17. J. W. Adams, A new optimal window, IEEE Trans. Signal Process., 39: 17531769, 1991.
18. T. W. Parks and J. H. McClellan, Chebyshev approximation for
nonrecursive digital filters with linear phase, IEEE Trans. Circuit
Theory, CT-19: 189195, 1972.
19. J. H. McClellan, T. W. Parks, and L. R. Rabiner, A computer
program for designing optimum FIR linear phase digital filters,
IEEE Trans. Audio Electroacoust., AU-21: 506526, 1973.

FIR FILTERS, WINDOWS

20. L. R. Rabiner, J. H. McClellan, and T. W. Parks, FIR digital filter
design techniques using weighted Chebyshev approximation,
Proc. IEEE, 63: 595610, 1975.
21. J. W. Adams and A. N. Wilson, Jr., On the fast design of highorder FIR digital filters, IEEE Trans. Circuits Syst., CAS-32:
958960, 1985.
22. D. J. Shpak and A. Antoniou, A generalized Remez method for
the design of FIR digital filters, IEEE Trans. Circuits Syst., 37:
161173, 1990.
23. J. R. Rice and K. H. Usow, The Lawson algorithm and extensions
Mathematics of Computation, in press.
24. Y. C. Lim et al., A weight least squares algorithm for quasi-equiripple FIR and IIR digital filter design, IEEE Trans. Signal Process., 40: 551558, 1992.
25. R. H. Yang and Y. C. Lim, Efficient computational procedure for
the design of FIR digital filters using WLS technique, IEE Proc.G, 140: 355359, 1993.
26. Y. C. Lim and S. R. Parker, Discrete coefficients FIR digital filter
design based upon an LMS criteria, IEEE Trans. Circuits Syst.,
CAS-30: 723739, 1983.
27. T. Saramaki, A systematic technique for designing highly selective multiplier-free FIR filters, Proc. IEEE Int. Symp. Circuits
Syst., 1991, pp. 484487.

SERGIO L. NETTO
GELSON V. MENDONCA
Federal University of Rio de Janeiro

567

FREQUENCY SYNTHESIZERS

775

FREQUENCY SYNTHESIZERS
Frequency synthesis is the engineering discipline dealing
with generation of a single or of multiple tones, all derived
from a common time-base, always a crystal oscillator.
Traditionally, frequency synthesis (FS) generated a single
tone with variable frequency or amplitude. There are new applications, especially for testing and simulation, that require
multitone generation and even arbitrary wave generation,
which relate to digital frequency synthesis. In the last two
decades, FS has evolved from mainly analog to a mix of analog, radio-frequency (RF), digital, and digital signal processing (DSP) technologies.
There are three major FS techniques:
1. Phase Lock Loop. Also known as indirect synthesis, the
most popular FS technique, based on a feedback mechanism that enables simplicity and economics via digital
division and analog processing.
2. Direct Analog. An analog technique using multiplication, division, and mix-filtering, offers excellent signal
quality and speed.
3. Direct Digital. DSP method that generates and manipulates the signal in the numbers (digital) domain and
eventually converts to its analog form via a digital to
analog converter.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

776

FREQUENCY SYNTHESIZERS

Table 1. Integrated Circuits Used in Phase Lock Loops

Fujitsu Semiconductors: MB15xx
National Semiconductors: 23xx
Philips: SA7025, SA8025, UMA1014
Motorola: MC145xxx
Plessey: SP55xx, SP56xx, SP88xx
Texas Instruments: TRF2020, 2050, 2052

L(fm)
AL 9.71 dBm
Attenuation 28 dB
10.00 dB/div

Test complete
Sample

Center frequency
1.675 006 24 GHz

Loop

Frequency synthesis is a mature technology yet evolving rapidly. The traditional analog designs are supplemented with
ever-increasing digital and DSP methods and technologies.
These allow a high level of integration, lower power, manufacturing uniformity (and thus yield uniformity), and low cost.
Though a novel technology only 20 years ago, FS and especially phase lock loop (PLL) are very popular, accessible, and
economical. Traditionally, FS started to enter the field of electronics as quite bulky and expensive instruments, using multiple crystals and complex analog processing functions such
as mixing, filtering, and division. Better architectures and
simpler designs have replaced these. Accelerating integrated
circuit (IC) technology and high-level integration silicon now
offer complete synthesizers, especially PLL and direct digital
synthesizers (DDSs) on a single chip and sometimes more
than one on a single dice.
In the engineering realm, all signals generated are amplified and filtered noise. There are no deterministic signals in
nature. The cardinal issue for FS is therefore how clean these
signals are and how close they come to a theoretical sin(t).
Such a theoretical signal will have all of its energy in a single
spectral line. In reality, signal spectra have a noise distribution caused by amplitude modulation (AM) noise and phase
perturbation, also known in FS as phase noise. Phase noise
can be described by its spectral properties, usually its noise
distribution designated in dBC/Hz, or its time equivalent,
also known as jitter. Spectral distribution L(fm) details the
exact spectral shape of the signals noise and is defined by the
single side-band energy level of the signal at a specific offset
from the carrier relative to the signals total energy. This detailed technique has become the de facto method to describe
and characterize phase noise (see Fig. 1).
For example, a 1000 MHz signal with a spectral noise
characteristic of 70 dBC/Hz (dB is used almost exclusively
because of the large ratios involved) at an offset of 1 kHz from
the carrier means that at 1 kHz from the carrier (either
1000.001 or 999.999 MHz), the single side-band noise power
contained in 1 Hz bandwidth is 107 compared with the signals total power. The function L(fm) that defines the noise
distribution spectrum is always measured in decibel of the
noise level. Note that the noise is part of the signal and that
the integral energy under the L(fm) curve is the signal total
power (Fig. 1).

VCO
VCO
70

Center 1.675 006 24 GHz

AB 110 Hz VB 300 Hz

Span 10.50 kHz

ST 2.773 fm

Figure 1. Phase noise of a typical synthesizer.

SYNTHESIZER PARAMETERS
Step Size
This is also known as resolution, and it measures the smallest
frequency increment the synthesizer can generate. As an example, an FS used in a North American cellular phone
(AMPSAmerican Mobile Phone Servicestandard), or
Time Division Multiple Access (TDMA), has 30 kHz resolution. In frequency modulation (FM) broadcasting radio, the
step is usually 100 kHz.
Phase Noise
This parameter was already mentioned before. The issue of
signal integrity, or otherwise the issue of the signals cleanliness, is the major challenge for FS designers. Long-term
noise deals mainly with the accuracy, drift, and aging of the
crystal, and short-term noise deals with rapid phase fluctuations.
Spurious Responses
These define the level of the discrete interferences, noise
sources that are periodic and therefore exhibit spectral lines
rather than a spectrum. These noise sources emerge from radiationfor example, line spurious responses at 60 Hz
(US)or from its multiples that always exist in the air and
power supplies, as well as from other radiated energy that
exists because of the enormous wireless traffic that is emerging and growing. Other sources are mixing products in the
radio or synthesizer, nonlinearities, and ground currents.
Switching Speed

Table 2. Integrated Circuits Used in Direct Digital Synthesis

Stanford Telecom: STEL-11xx and STEL-21xx
Analog Devices: AD7008, AD9830/9831, AD9720/9721
Sciteq Communications: SEI-432, SEI-631, DCP-1

This defines the amount of time it takes the synthesizer to

hop from a frequency F1 to another F2. This parameter is usually measured in two ways: by checking when the new frequency settles to within a frequency tolerance (say within 5

FREQUENCY SYNTHESIZERS

kHz), or (a more strict requirement) by checking the time it

takes to settle to within a phase tolerance, in most cases to
within 0.1 radian. The phase settling requirement can be as
much as three to five times longer than the frequency settling.
Phase Transient
This defines the way the signals phase behaves in transition
from frequency F1 to frequency F2. There are mainly three
ways to switch:
1. It might be a random parameter, so the phase is unknown after switching.
2. The phase can switch continuously, meaning that when
switching from F1 to F2, there will be no disturbance in
the phase. Such switching requirements are necessary
when generating linear FM signals or minimum shift
keying (MSK) modulation, or other phase modulation
waveforms.
3. In the case of phase memory, if switched from F1 to F2
and then back to F1, the signals phase will be as if the
switching did not occur. This is useful in coherent detection radars and frequency hop communications.
Frequency Range
This defines the frequency band the FS covers.
Other Parameters
Other parameters are not unique to FS; among them are output impedance, power flatness, size, power consumption, environment, and the like.
The main tools used in FS are as follows: multiplication by
comb generation; addition and subtraction by mix and filtering; and division (digital) and feedback for PLL. Another
cardinal principle in FS is as follows: Multiplication by N corrupts phase noise and spurious by N2 or 20 log(N) dB. Division improves by the same ratio.
SYNTHESIS TECHNIQUES
Direct Analog Synthesis
This method, the first to be used in FS, derives the signals
directly from the referenceas compared to PLL, which it
does indirectly. Direct analog uses building blocks such as
comb generators, mix and filter, and dividers as the main
tools. Many direct analog synthesizers use similar repeating
blocks for resolution. These blocks usually generate a 10 MHz
band in the ultrahigh frequency (UHF) range, in 1 MHz steps,
and after division (mostly by 10) they are used as an input
to the next similar stage. Every stage divides by 10, thereby
increasing the resolution arbitrarily by as many stages as the
designer chooses to use. Most direct analog synthesizers are
instruments and traditionally use binary coded decimal
(BCD) for control. This is losing importance because a computer controls all modern applications.
Signals are therefore very clean because they are derived
directly from the crystal; however, complexity is high and resolution comes at a high price. Direct analog synthesizers also
achieve fast switching speed, limited mainly by filters propa-

777

gation delay. Speed ranges from 1 s to 50 s. Because

there are no mechanisms to clean the signals at high offset
frequencies from carrier, their noise floorwhere the phase
noise levelsis comparatively (to PLL) high.
Direct analog synthesizers are available from dc to 26
GHz, are usually quite bulky and expensive, exhibit excellent
phase noise and switching speed, and found applications in
communications, radar, imaging, magnetic resonance imaging, simulators, and ATE.
Direct Digital Synthesis (DDS)
DDS is a DSP technology based on the sampling theorem. The
principle of its operation is based on storing the digital values
of sine wave amplitude in memory, then flushing these samples out by addressing the memory with an indexer. The indexer is always a digital accumulator, allowing the phase
ramp (memory address) to change its slope to any value (compared with a counter that can index the RAM or ROM memory only by increments of 1).
As a consequence, the accumulator output can be interpreted as a signal phase, t (actually nT, where T is clock time,
since it is sample data), with a variable slope given by the
accumulator control. For example, if a 32 bit binary accumulator, which performs the function
Sn = Sn1 + W

(Sn is the output of sample n, W is the input)

(1)

is addressed with W 0, the output will not change, signifying direct current (dc) signal. However, if W 1, the accumulator will take 232 clock ticks to come back to its original
state. So a complete cycle of the phase from 0 (accumulator is 0) to 2 (accumulator is full) takes 232 ticks. Generally,
a DDS output frequency is given by
Fo = FckW/ACM

(2)

where Fck is the clock frequency, W is the input control, ACM

is the accumulator size, and W ACM/2.
For ACM 232, Fck 20 MHz, and W 1, output frequency is given by 0.00465 . . . Hz, which is also the synthesizer resolution, its smallest step.
The read-only memory (ROM) output is connected to a digital-to-analog converter (DAC) which generates the analog
signal smoothed by the output filter (see Fig. 2). According to
the sampling theorem, the maximum output frequency is
Fck /2, also known as Nyquist frequency.
The various waveforms and modulation points are shown.
Because the accumulator output is the signal phase, phase
modulation can be applied; amplitude modulation can be applied at the output of the ROM, the amplitude point.
DDS is thus a numbers technology, related to frequency
only by the clock. The artifacts caused by sampling generate
many (mirror) frequencies as shown in the sampling theorem;
these are usually referred to as aliasing frequencies.
DDS offers simplicity, economy, integration, and very fast
switching speed. The digital nature of the technology offers
design flexibility and simplicity, low-cost manufacturing, and
very high density (small dice).
As sampled data, DDS suffers the common problems of
quantization. The level of accuracy determines the dynamic
range of the design, in most cases 10 to 12 bits. The most

778

FREQUENCY SYNTHESIZERS

Clock

Phase
accumulator

Sine map
in
ROM or RAM

Digital-toanalog
converter

Low-pass
filter

(a)

(b)

(c)

(d)

;;;;;;
;;;;;;

Frequency
control

On/off

FM

Digital
AM

Accumulator

Analog
AM/FM/ M

D/A
converter

Memory

Frequency
control

Output

Low-pass
filter

Deglitcher

Clock
Figure 2. Direct digital synthesizer block diagram and functionality.

significant weakness of DDS are limited bandwidth (clock frequencies are in the 400 MHz for CMOS devices and 1500
MHz for GaAs) and spurious response. Spurious responses
are generally limited to 6D, where D is the number of bits
used in the DAC. Thus a 10 bit DDS (using a 10 bit DAC)
usually be limited to 60 dBC spurious responses. These spurious responses are either periodicities generated in the quantization process or intermodulation products generated by the
DAC, the only analog part. As a rule of thumb, spurious performance deteriorates with increased output frequency or otherwise with decrease in samples per cycle. Arbitrary waveform generators (AWGs) are a superset of DDS. These enable
the memory to be loaded with arbitrary wave samples, and
then they sequentially flush the wave samples out. AWGs
found use in simulation and testing.

also known as indirect synthesis, is a negative feedback loop

structure that locks the phase of the output signal after division to the reference. Synthesis is simple because the variable
counter (divider) N allows the generation of many frequencies Fo
Fo = NFr

(Fo = output frequency, Fr = reference)

R2

C
Active

R1

Phase Lock Loop

PLL is the technology of choice for generating radio frequencies and microwave frequencies for radio applications. PLL,

R2

VCO
o

H(s)

Kv /s

R1

C
Passive

K d

Phase detector

= i o/N

1/N

i
Figure 3. Phase lock loop block diagram.

Figure 4. Second-order loop circuits.

(3)

FREQUENCY SYNTHESIZERS

by changing the division ratio N. Changing N is made easy

by the use of dual modulus devices, capable of dividing by two
(and sometimes more) ratios. For example, 64/65 or 128/129
are very common.
PLL chips are available in a great variety, in low power
and very low cost, and include all the functionality necessary
with the exception of an external crystal, voltage controlled
oscillator (VCO) and loop filter (mainly resistors and capacitors). Convenience, economy, simplicity, and ease of use made
PLL a household name used in television, radio, consumer
electronics, cellular phones, and Satcom terminals, practically
in almost any conceivable electronics radio (see Fig. 3).
When locked, PLL can be assumed to be a linear system,
and classical feedback theory can be applied for analysis. The
most common PLL structure is of second order, and there are
two poles in the transfer function denominator: one from the
VCO, with a Laplace domain transfer function given by Kv /s
(Kv is the VCO constant, phase is the integral of frequency)
and one from the loop filter having a memory device (capacitor). The loop transfer function is given by
o /i (s) =

s2

2 n s + n2
+ 2 n s + n2

(4)

n is the natural frequency and is the damping, both borrowed from classical control theory. n and are given by (for
the active loop structure shown, Fig. 4)
n = (K/T1 N)0.5

and = n T2 /2

(5)

T1 R1C, T2 R2C, K KvKp /N, Kv (Hz/V), and Kp (V/radian)

are VCO and phase detector constants.
Overall performance is controlled by noise sources from
phase detector, divider, and other active components within
the loop bandwidth and by the VCO outside. Within the loop

779

bandwidth, VCO noise is suppressed by the loop. PLL noise

sources within the loop are multiplied by 20 log(N), which can
be very significant when N is large. Typical phase detector
noise is in the 150 dBC/Hz range for well-designed circuits.
An advanced PLL technology known as fractional-n allows
lowering N and generating step size smaller than Fr (hence
fractional), thereby gaining phase noise performance. The
fractional principle requires dynamic changes in division ratio N, thereby causing spurious signals, which are compensated by either extra filtering, analog feed forward correction
(open loop), or digital waveshaping techniques.
BIBLIOGRAPHY
R. E. Best, Phase Lock Loops: Theory, Design and Applications, New
York: McGraw-Hill, 1984.
F. M. Gardner, Phaselock Techniques, New York: Wiley, 1980.
B.-G. Goldberg, Digital Techniques in Frequency Synthesis, New York:
McGraw-Hill, 1996.
V. Manassewitsch, Frequency Synthesizers: Theory and Design, New
York: Wiley, 1983.
B. Miller and B. Conley, A multiple modulator fractional divider,
IEEE Trans. Instrum. Meas., 40: 578583, 1991.
U. L. Rohde, Digital PLL Frequency Synthesizers: Theory and Design,
Englewood Cliffs, NJ: Prentice-Hall, 1983.
R. C. Stirling, Microwave Frequency Synthesis, Englewood Cliffs, NJ:
Prentice-Hall, 1987.
J. Tierney, C. M. Radar, and B. Gold, A digital frequency synthesizer,
IEEE Trans. Audio Electroacoust., AU-19: 4857, 1971.

BAR-GIORA GOLDBERG
Sciteq Electronics, Inc.

FRESNELS FORMULAE. See OPTICAL PROPERTIES.

632

HARMONIC OSCILLATORS, CIRCUITS

HARMONIC OSCILLATORS, CIRCUITS

In electronics a harmonic oscillator is an electronic circuit
that generates a sinusoidal signal. This signal can either be
a voltage, a current, or both. Harmonic oscillators are not restricted to electronics. They can be found in many other disciplines. However, they always can be described by similar
mathematical equations. A very familiar harmonic oscillator
is the harmonic pendulum, which is found in many high
school physics textbooks. It is a mechanical system consisting
of a mass suspended by a fixed length thread. Figure 1 illustrates this. When mass m is slightly separated from its equilibrium point (so that angle in Fig. 1 is sufficiently small)
and set free, the earths gravitational force will make it move
toward its resting point. When the mass reaches the resting
point it has gained some speed that will make it keep running
toward the other side of the equilibrium point, until it stops
and comes back. And so it will oscillate from one side of the
equilibrium point to the other. What happens is that by initially departing the mass from its equilibrium point, an external agent is increasing its potential energy. When it is set
free the action of the earths gravitational force, together with
the constraint imposed by the fixed length thread, will gradually change this initial increase of potential energy into kinetic energy. At the equilibrium point all potential energy
supplied initially by the external agent is in form of kinetic
energy and speed is maximum. At the points of maximum
elongation the kinetic energy (and speed) is zero and the original potential energy is recovered. The pendulum oscillates at
constant frequency and, if there is no friction, it keeps oscillating indefinitely with constant maximum elongation or amplitude. However, in practice friction cannot be completely
suppressed. Consequently, in order to have a pendulum oscillating permanently there must be a way of supplying the energy lost by friction.
In an electronic oscillator there is also a mechanism by
which energy of one type is changed into another type (energy
can also be of the same type but interchanged between differ-

m
Figure 1. The mechanical pendulum behaves as a harmonic oscillator in the limit of very small maximum angle deviations.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

HARMONIC OSCILLATORS, CIRCUITS

633

The solution to this second order time domain differential

equation is

vC (t) = vC (0) cos(t) iL (0) L/C sin(t)

+
iL

vC

(5)

where vC(0) is the capacitor voltage at time zero, iL(0) is the

inductor current at time zero and is the angular frequency
of the resulting oscillation whose value is
1
=
LC

Figure 2. An ideal capacitor connected in parallel with an ideal inductor form a harmonic oscillator.

(6)

Using Eqs. (3), (5), and (6) in Eq. (1) results in

ent devices). Figure 2 shows a capacitor connected in parallel
with an inductor. At equilibrium there is no voltage across
the capacitor and no current through the inductor. However,
if by some means, an initial voltage (or equivalently, charge)
is supplied to the capacitor, its stored energy increases. The
inductor provides a path to discharge the capacitor so that a
current builds up through the inductor. However, by the time
the capacitor has zero charge the current flowing through the
inductor is maximum and the inductor stores all the original
capacitor energy in the form of magnetic flux energy. The consequence is that the current keeps flowing through the inductor, charging now the capacitor oppositely, until the current is
zero. If there are no resistive losses this process will continue
indefinitely: capacitor and inductor keep interchanging their
stored energies. The voltage across the capacitor will be sinusoidal in time, and so will be the current through the inductor. The amplitude (or maximum elongation) of the voltage
oscillations is equal to the initial voltage supplied to the capacitor. In practice both capacitor and inductor have resistive
losses, so that in order to keep the system oscillating indefinitely there must be a way of supplying the energy being lost.

IDEAL RESONATOR MATHEMATICAL MODEL

In Fig. 2 the capacitor voltage vC and its current iC are related
mathematically by the expression
iC = C

dvC
dt

(1)

where C is the capacitors capacitance. For the inductor, its

voltage vL and current iL are related by
vL = L

diL
dt

(2)

where L is the inductors inductance. Besides this, the circuit

of Fig. 2 imposes the following topological constraints
vC = vL
iC = iL

(3)


iL (t) = iL (0) cos(t) + vC (0) C/L sin(t)

(7)

By means of basic trigonometric manipulations Eqs. (5) and

(7) can be rewritten as

vC (t) = Vmax cos(t + )


iL (t) = Vmax C/L sin(t + )

(8)


vC2 (0) + i2L (0)L/C


i (0) 
= arctan L
L/C
vC (0)

(9)

where,

Vmax =

Equation (8) reveals that vC(t) and iL(t) have a phase shift of
/2 radians. This is usually referred to as vC(t) and iL(t) being
in quadrature, and the resonator in Fig. 2 as being a quadrature resonator or oscillator. Note that the maximum oscillation amplitudes (Vmax or VmaxC/L, respectively) depend on
the initial conditions vC(0) and iL(0) C vC(0).
Usually, differential equations like Eq. (4) are not solved
directly in the time domain but in the frequency domain. For
this, let us take the Laplace transform of Eq. (4)
s2VC (s) svC (0) vC (0) +

VC (s)
=0
LC

(10)

where VC(s) is the Laplace transform of vC(t). Since iL(0)

C vC(0), Eq. (10) can be rewritten as
VC (s) =

s
1
iL (0)
v (0) 2
s2 + 1/LC C
s + 1/LC C

(11)

Taking the inverse Laplace transform of Eq. (11) results in

Eq. (5). Usually in circuits, the initial conditions involved in
the Laplace transform are ignored and Eq. (10) is simplified
to
s2 +

1
=0
LC

(12)

which has the following solutions

Solving Eqs. (13) yields

s1 = j, s2 = j

d vC
1
v =0
+
dt 2
LC C

(4)

1
=
LC

(13)

634

HARMONIC OSCILLATORS, CIRCUITS

Solutions s1 and s2 are called the poles of the system, and in

this case the two poles are complex conjugate and are purely
imaginary (their real part is zero). In circuits, people dont
take the inverse Laplace transform to know the solution.
They know that if a system has a pair of purely imaginary
poles the signals have a sinusoidal steady state whose amplitude depends on the initial conditions.
REAL RESONATOR MATHEMATICAL MODEL

A(t) = Vmax ebt/2

As mentioned earlier, the circuit of Fig. 2 is ideal. In practice

there will always be resistive losses in the capacitor, in the
inductor, or in both. Either introducing a small resistance RL
in series with the inductor, a large resistance RC in parallel
with the capacitor, or both can model this. Solving such a
circuit yields the following time domain differential equation
dv (t)
d 2 vC (t)
+ 2 vC (t) = 0
+b C
2
dt
dt

b=

(15)

(20)

would increase exponentially in time, assuming Vmax 0 (due

to noise Vmax cannot be exactly zero all the time). This would
yield an oscillator with initial startup but that would be unstable, because its amplitude would be out of control. What
circuit designers do to build oscillators with stable amplitude
is to make the term b in Eq. (18) depend on the instantaneous
oscillation amplitude A(t),

(14)

with

R
1
+ L
RCC
L
1
+
R
/R
L
C
2 =
LC

is negligible and one can consider that the system has stopped
oscillating. Consequently, in practice, the circuit of Fig. 2 is
not useful for building an oscillator.
Imagine that somehow we could make RL or RC (or both)
negative, so that b 0. A negative resistance behaves as an
energy source that replaces the energy dissipated by positive
resistances. In this case the poles would have a positive real
part and the amplitude of the oscillations

b(t) = b(A(t))

(21)

and in such a way that b increases with A, b is negative for

A 0 (to ensure initial startup), and b becomes positive above
a certain amplitude. This is called amplitude control. For instance, assume that by adding some special circuitry to Fig.
2 we are able to make
b(A) = b0 + b1 A

(22)

The solution to Eq. (14) is

vC (t) = Vmaxebt/2 cos(o t + )

(16)

where o2 2 (b/2)2. Parameters Vmax and can be found

from the initial conditions vC(0) and vC(0),

Vmax =

vC (0)
cos

= arctan

b
vC (0)

o vC (0)

vC (0) +

(17)

Ao =

However, circuit people prefer to solve Eq. (14) in the frequency domain by taking its Laplace transform,
s2 + bs + 2 = 0

(18)

The solution to this equation provides the following poles


 2
b
b
b
s1 = + j 1
= + jo
2
2
2

 2
b
b
b
s2 = j 1
= jo
2
2
2

where b0 and b1 are positive constants (note that A is always

positive). Initially, if A 0, b b0 is negative and the real
part of the poles is positive: amplitude A(t) increases exponentially with time. As A(t) increases b will eventually become
positive (poles with negative real part) and this will decrease
the amplitude A(t). The consequence of these two tendencies
is that a steady state will be reached for which b 0 and the
amplitude is constant. Solving Eq. (22) for b 0 yields the
value of the steady state oscillation amplitude Ao,

(19)

which are two complex conjugate poles with a negative real

part. Circuit people know that when a system has a pair of
complex conjugate poles with a negative real part, the system
oscillates in a sinusoidal fashion with an amplitude that vanishes after some time. This is what Eq. (16) shows. The amplitude of the oscillations A(t) Vmaxebt/2 decreases exponentially with time. After a few time constants 2/b the amplitude

b0
b1

(23)

Note that, as opposed to the ideal resonator, the steady state

amplitude is independent of any initial conditions.
In general, a harmonic oscillator does not have to be a second order system like the case of Eq. (14) or Eq. (18). It can
have any order. What is important is that it has a pair of
complex conjugate poles whose real part can be controlled by
the oscillation amplitude (so that the real part becomes zero
in the steady state), and that the rest of the poles (either complex conjugate or not) have negative real parts. The way b
depends on A does not have to be like in Eq. (22). Strictly
speaking, the conditions are

b(A = 0) = b0 < 0
b>0
db(A)
>0
dA

for initial startup

for some A

(24)

for stable amplitude control

This will ensure stable oscillator operation. In what follows

we will concentrate on second order systems and will provide
two different ways of performing amplitude control.

HARMONIC OSCILLATORS, CIRCUITS

AMPLITUDE CONTROL BY LIMITATION

635

Rn
Iin

A very widely used method for oscillator amplitude control is

by limitation. This method usually is simple to implement, so
simple that many times it is implicit in the components used
to build the resonator with initial startup. This makes practical circuits easy to build, although many times people dont
understand the underlying amplitude control mechanism.
Let us consider the ideal resonator of Fig. 2 with an additional resistor Rp in parallel to make it real. In order to assure
initial startup, let us put a negative resistor in parallel also.
Figure 3(a) shows a very simple way to implement one using
a real (positive) resistor and a voltage amplifier of gain larger
than one (for example, two). Current Iin will be

Vin
x2

(a)

Vin

Vo = 2 Vin

V
Iin = in
Rn

(25)

and the structure ResistorAmplifier behaves as a grounded

negative resistor of value Rn. Figure 3(b) shows how to build
the amplifier using an operational amplifier and resistors.
Connecting this negative resistor in parallel with a positive
one of value Rp Rn R (with R Rn), the equivalent parallel resistance would be

(b)

Rn

Req

R2
= n
R

(26)

Rn-R
R

which is a very high but negative resistance. Connecting this

equivalent resistor in parallel with the ideal resonator of Fig.
2 provides an oscillator with initial startup. This is shown in
Fig. 3(c).
Due to the fact that the operational amplifiers output voltage cannot go above its positive power supply VDD or below its
negative one VSS, the negative resistance emulator circuit just
described works as long as the amplifier output is below VDD
and above VSS, or equivalently voltage Vin is between VDD /2
and VSS /2. It is easy to compute the current through Req as a
function of Vin taking into account this saturation effect. Figure 3(d) shows the resulting curve. If VSS /2 Vin VDD /2 resistor Req behaves as a negative resistance of high value, but
if Vin is outside this range the slope of Iin versus Vin is that of
a positive resistance with much smaller value. In order to analyze what happens to the circuit of Fig. 3(c) when the oscillating amplitude increases beyond VDD /2 or VSS /2 (whichever
is smaller) the concept of describing function can be used.
Describing Function
Figure 4 shows a sinusoidal signal x(t) applied to a nonlinear
element f(x) that outputs a distorted signal y(t). Signal y(t) is
no longer sinusoidal, but it is periodic. Consequently, a Fourier series can describe it. The first (or fundamental) harmonic has the same frequency as the input sinusoid, while
the others have frequencies which are integer multiples of the
first one. If the block of Fig. 4 is used in a system such that
the end signals will be approximately sinusoidal (like in a
harmonic oscillator) then one can neglect all higher harmonics of the Fourier expansion of y(t) and approximate it using

(c)
Iin
2
Rn

VSS /2

Vin
2
Rn

VDD /2

Rn2

(d)
Figure 3. A real harmonic oscillator can be made by adding a negative resistor to a real resonator. (a) A negative resistor can be emulated using a resistor and a voltage amplifier of gain greater than
unity. (b) Implementation of negative resistor using an operational
amplifier and resistors. (c) Oscillator composed of capacitor inductor
and negative resistor. (d) Transfer characteristics of the negative resistor implementation of (b).

the first or fundamental harmonic only,

y(t) N(A)x(t)
x(t) = A sin(t)

2 /

N(A) =
f (x(t)) sin(t) dt
A 0

(27)

636

HARMONIC OSCILLATORS, CIRCUITS

where N(A) R /Rn2 for A VDD /2 and N(A) tends towards

2/Rn as it increases beyond VDD /2. Since N(A) is continuous
and monotonic, there will be a value of A (and only one) for
which N(A) 0. Let us call this value Ao. Note that Ao depends only on the shape of the nonlinear function f( ) of Fig.
3(d). Equation (29) is the equation of a resistor of value
Req 1/N(A). For small values of A, Req Rn2 /R (high resistance but negative) and the oscillator possesses exponentially
increasing amplitude. When A increases beyond VDD /2, Req
will become more and more negative until N(A) 0. At this
point A Ao, Req and we have the ideal resonator. If A
increases further, Req becomes positive and the oscillator presents exponentially decreasing amplitude. This represents a
stable amplitude control mechanism such that in the steady
state A Ao and Req .

x(t)

me
y(t)

x(t)
mc

me

General Formulation
y(t)

In general, the block diagram of Fig. 5 describes a harmonic

oscillator with amplitude control by limitation, where H(s) is
a linear block (or filter) and f(x) is the nonlinear element responsible for the amplitude control. Applying the describing
function method to the nonlinear block results in

y(t) = N(A)x(t)

(31)

for a time domain description. For a frequency domain description it would be

Y (s) = N(A)X (s)
Figure 4. A sinusoidal signal applied to a nonlinear element results,
in general, in a distorted output signal.

(32)

On the other hand, input and output of the linear block or

filter are related in the frequency domain by
X (s) = H(s)Y (s)

Note that this approximation makes y(t) to be linear with

x(t) so that the nonlinear block in Fig. 4 can be modeled by a
linear amplifier of gain N(A). Function N(A) is called the describing function of the nonlinear element f( ).
This approach is valid for any nonlinear function f( ), but
let us consider only piece-wise linear functions, like in Figs. 3
and 4, with three pieces: a central linear piece of slope mc and
two external linear pieces of slope me. When amplitude A is
small enough so that x(t) is always within the central piece
then N(A) mc. When A increases beyond the central piece
N(A) will change gradually towards value me. In the limit of
A the describing function will be N(A) me. Computing
the first Fourier term provides the exact expression (let us
assume VSS VDD for simplicity). If A VDD /2

N(A) = me 2



V
me mc 1 VDD
sin
+ DD

2A
2A


1

VDD
2A

2

(33)

Equation (32) and (33) result in

H(s)N(A) = 1

(34)

If H(s) is a second order block it can be described by

H(s) =

a 1 s2 + a 2 s + a 3
s2 + a 4 s + a 5

(35)

which together with Eq. (34) yields an equation of the form

s2 + sb + 2 = 0
a1 a2 N(A)
1 a1 N(A)
a3 N(A)
a
2 = 5
1 a1 N(A)
b=

(36)

(28)
H(s)

and if A VDD /2
N(A) = mc

Y(s)

y(t)

x(t)

X(s)

(29)
f(x)

Applying the describing function method to the nonlinearity

of Fig. 3(d) results in
Iin = N(A)Vin

(30)

Figure 5. A general block diagram of an oscillator with amplitude

control by limitation consists of a linear filter and a nonlinear amplitude controlling element connected in a loop.

HARMONIC OSCILLATORS, CIRCUITS

For small amplitudes N(A) is equal to some constant (for example n0) and Eq. (36) is called the characteristics equation.
It must be assured that b(A 0) 0. This is usually referred
to as the oscillation condition. For stable amplitude control it
should be
db(A)
>0
dA

C1

R1

v1

(37)

C2

and 2 must be kept always positive for all possible values of

A. In practice, it is desirable to make in Eq. (35) a1 a3 0,
which will make 2 and b not be coupled through a common
parameter. This way the oscillation amplitude and frequency
can be controlled independently.

637

v2

k0
R2

(a)

R1

C1

v+

A Practical Example: the Wien-Bridge Oscillator

In a practical circuit it is not convenient to rely on inductors
because of their limited range of inductance values, high
price, and, in VLSI (very large scale integration) design, they
are not available unless one operates in the GHz frequency
range. But it is possible to implement the filter function of
Fig. 5 without inductors. The Wien-Bridge oscillator of Fig. 6
is such an example. Figure 6(a) shows its components: two
resistors, two capacitors, and a voltage amplifier of gain k0.
Figure 6(b) illustrates an implementation using an opamp
and resistors for the voltage amplifier, and Fig. 6(c) shows its
piece-wise linear transfer characteristics. Using the describing function, the effective gain of the amplifier k(A) can be
expressed as a function of the sinusoidal amplitude A at
node v1,
k(A) = k0 N(A)

v1

C2

R2

Rm

(k01) Rm

(b)
v2
VDD

(38)
k0

where k0N(A) is the describing function for the function in

Fig. 6(c) and is given by Eq. (28) with mc k0, me 0, and
the breakpoint changes from VDD /2 to VDD /k0. Consequently,
the frequency domain description of the circuit in Fig. 6(a) is
V

s2 + sb + 2 = 0
1
k N(A) 1
1
+
0
R2C2
R1C1
R1C2
1
1
2 =
R1C1 R2C2
b=

v2

v1

DD

(c)

(39)

For initial startup it must be b 0 for A 0. The final amplitude A0 is obtained by solving b(A0) 0, and the frequency of
the oscillation is (in radians per second) or f /2 (in
hertz). Optionally, the diodes in Fig. 6(b), connected to voltage
sources v and v, can be added to control the oscillation amplitude. These diodes change the saturation voltage VDD of
Fig. 6(c), and hence will modify the describing function N(A).
In general, when using amplitude control by limitation, a
practical advice is to make b0 as close as possible to zero but
without endangering its sign. This way the nonlinear element
will distort very little the final sinusoid, because it needs to
use only a small portion of its nonlinear nature to make b(A)
become zero. If b0 is too large the resulting waveform will
probably look more like a triangular signal than a sinuoidal
one.

Figure 6. The Wien-Bridge oscillator is an example of an oscillator

that does not require an inductor. (a) It consists of two resistors, two
capacitors, and a voltage amplifier circuit. (b) The voltage amplifier
can be assembled using an opamp and two resistors. (c) The resulting
voltage amplifier has nonlinear transfer characteristics.

AMPLITUDE CONTROL BY AUTOMATIC GAIN CONTROL

Let us illustrate the amplitude control by AGC (automatic
gain control) using an OTA-C oscillator. An OTA (operational
transconductance amplifier) is a device that delivers an output current I0 proportional to its differential input voltage
Vin. Figure 7(a) shows its symbol and Fig. 7(b) its transfer
characteristics. The gain (slope gm in Fig. 7(b)) is called the
transconductance. This gain is electronically tunable through
voltage Vbias (depending on the technology and the design, the
tuning signal can also be a current). Using these devices, the
self-starting oscillator of Fig. 7(c) can be assembled. Note
that gm1, gm2, and C1 emulate an inductance of value L

638

HARMONIC OSCILLATORS, CIRCUITS

I0

+
gm

Vin

Vbias
(a)

I0
ISS
Vin

gm

ISS

(b)

Vb3
+

gm3

gm1

V0

Vbf
+

gm2

C1

gm4

C2

Stability of Automatic Gain Control Loop

Vb4

(c)

Vbf

To assure initial startup Vb3 and Vb4 must be such that gm3
gm4. By making gm3 (or gm4) depend on the oscillation amplitude A, an AGC for amplitude control can be realized. This is
illustrated in Fig. 7(d) where the box labeled oscillator is the
circuit in Fig. 7(c), the box labeled PD is a peak detector, the
large triangle represents a differential input integrator of
time constant AGC, the small triangle is an amplifier of gain
m necessary for stability of the AGC loop, and the circle is a
summing circuit. The output of the peak detector Apd(t) follows
(with a little delay) A(t), the amplitude of the sinusoid at V0.
The error signal resulting from subtracting Apd and Vref is integrated and used to control gm4. If Apd Vref gain gm4 will
increase (making b positive, thus decreasing A), and if Apd
Vref gain gm4 will decrease (making b negative, thus increasing A). In the steady state A Apd Vref and gm4 will automatically be adjusted to make b 0. Note that Vref must be such
that the node voltages are kept within the linear range of
all OTAs, otherwise amplitude control by limitation may be
taking place.
OTA-C oscillators are convenient for AGC because their
gain can be adjusted electronically. In order to do this for the
Wien-Bridge oscillator of Fig. 6, either a capacitor or a resistor must be made electronically tunable (using a varicap or a
JFET). Also, OTA-C oscillators are interesting because they
do not need resistors, and this is very attractive for VLSI in
CMOS technology where resistors have very bad electrical
characteristics and a limited range of values.

V0

Oscillator

An AGC loop for amplitude control, like the one in Fig. 7(d),
presents a certain dynamic behavior which can be analyzed
in order to (1) make sure it is a stable control loop and (2)
optimize its time response.
In Fig. 7(d) the peak detector output Apd(s) can be modeled
as a delayed version of A(s),
Apd (s) = A(s)(1 spd )

Vb4
m
+

where Apd(s) and A(s) are the Laplace transforms of the small
signal components of Apd(t) and A(t), respectively. Signal
Vb4(s) (the Laplace transform of small signal component of
Vb4(t)), according to Fig. 7(d) satisfies

Apd
PD
Vref

Vb4 (s) =

(d)
Figure 7. An oscillator with amplitude control by AGC can be made
easily with OTAs and capacitors (OTA-C). (a) An OTA delivers an
output current proportional to its differential input voltage. (b) It has
nonlinear transfer characteristics. (c) A self-starting OTA-C oscillator
can be made with four OTAs and two capacitors. (d) The amplitude
control by AGC requires an additional peak detector and integrator.

C1 /(gm1gm2), gm3 emulates a negative resistance of value R3

1/gm3, and gm4 emulates a positive one of value R4 1/gm4.
The characteristics equation of the OTA-C oscillator is

s2 + bs + 2 = 0
g gm3
b = m4
C2
gm1 gm2
2
=
C1 C2

(41)

(40)

1
sAGC

(1 + smAGC )Apd (s) Vref (s)

(42)

and controls parameter b in Eq. (40). Let us assume that b(t)

follows instantaneously Vb4(t) so that
b(s) = Vb4 (s)

(43)

Now what is left in order to close the control loop is to know

how the amplitude A(t) (or A(s) in the frequency domain) at
node V0 depends on b.
This dependence can easily be obtained from the time-domain differential equation (like Eq. (14)) in the following way:
assume b(t) is a time dependent signal that has small changes
around b 0 and keeps A(t) approximately constant around
A0. Then the solution to V0(t) (or vC(t) in Eq. (14)) can be written as
Vo (t) = A(t) cos(ot + )

(44)

HARMONIC OSCILLATORS, CIRCUITS

where A(t) A0 a(t) and a(t) A0. Substituting Eq. (44)

into vC(t) of Eq. (14) yields the following coefficients for the
cos( ) and sin( ) terms, respectively, which must be identically zero [if Eq. (44) is indeed a solution for Eq. (14)],

dA(t)
A(t)
d 2 A(t)
+ b2 (t)
=0
+ b(t)
dt 2
dt
4
dA(t)
2
+ A(t)b(t) = 0
dt

12 tt b(t )dt
0

(46)

When the AGC loop is in its steady state A(t) A0 a(t) and
the integral is a function that moves above and below zero
but is always close to zero. Consequently, the exponential can
be approximated by its first order Taylor expansion resulting
in
!
"


1 t
A(t) A(t0 ) 1
b(t) dt
2 t0
(47)



t
A
A(t0 ) t
b(t) dt 0
b(t) dt
a(t)
2
2 t0
t0
In the frequency domain this is
A(s)

A0
b(s)
2s

(48)

From Eqs. (4143) and (48) a loop equation for the AGC control can be written

Vref (s)
s2 k1 + sk2 + 1
2
k1 = AGC mAGC pd
A0
k2 = mAGC pd

R2
2r

s2

sn

2 nr

2 2r

2 nr

(45)

The first equation is not of much use, but from the second it
follows that
A(t) = A(t0 )e

s1
Digital
bus

639

A(s) =

(49)

This equation represents a stable control system if the poles

have negative real part. This is achieved if k1 0 and k2 0.
Parameters k1 and k2 can also be optimized for optimum amplitude transient response (for example, after a step response
in Vref (t)).
VOLTAGE CONTROLLED HARMONIC OSCILLATORS
An oscillator whose frequency can be electronically controlled
is required in many applications. Such an oscillator is called
a voltage controlled oscillator or VCO, although sometimes
the control parameter can also be a current.
In the case of the Wien-Bridge oscillator of Fig. 6 the frequency of oscillation is controlled by R1, R2, C1, and C2.
Changing one or more of these parameters would enable external control of the frequency. In order to have an electronic
control there are two options: (1) continuous or analog control,
and (2) discrete or digital control.
For analog control of the Wien-Bridge oscilator of Fig. 6
either a voltage controlled resistor (JFET) or a voltage con-

Figure 8. The frequency of the Wien-Bridge oscillator can be digitally controlled by replacing one of the resistors by a binarily
weighted resistor array controlled through a digital data bus.

trolled capacitor (varicap) is needed. Digital control can easily

be implemented by using a binary weighted array of resistors
or capacitors that are switched in and out of the circuit by
means of a digital bus. This is exemplified in Fig. 8 for resistor R2. Signals si are either 0 when the switch is open or 1
when it is closed. This yields

1
1
=
R2
r

n

si
1
+
n
i
2
2
i=1

"
=

1
dn
r

(50)

where dn is a number that ranges from 1/2n to 1 in steps of

1/2n. Number dn is represented in binary format by the bits
snsn1 . . . s2s1.
The OTA-C oscillator of Fig. 7 is much better suited for
analog or continuous control of frequency. If gm1 gm2 and
C1 C2, the frequency is equal to 2f gm1 /C1. Since
voltage Vbf in Fig. 7(d) controls simultaneously gm1 and gm2
(making them equal), this voltage can be used directly to control the frequency of the VCO.
Whether a VCO is made with OTAs and capacitors, or with
resistors, capacitors, and opamps, or uses some other technique, in general it turns out that the frequency does not have
a linear dependence on the control voltage. In practical circuits it also happens that if the control voltage is maintained
constant, the frequency may change over long periods of time
due to temperature changes which cause device and circuit
parameters (such as transconductance and resistance) to
drift. Both problems can be overcome by introducing a frequency control loop.
FREQUENCY CONTROL LOOP
Figure 9(a) shows the basic concept of a frequency control loop
for VCOs. It consists of a VCO (for example, the one in Fig.
7(d)), a differential input voltage integrator, and a frequency
to voltage converter (FVC) circuit. Voltage VCO is now the external control of the VCO frequency. The FVC circuit delivers
an output voltage VFVC that depends linearly on the frequency
f of its input signal VOSC,
VFVC = f + VF0

(51)

Parameters and VF0 must be constants and should not depend on temperature or technological parameters that change
from one prototype to another. If such an FVC is available,
the circuit in Fig. 9(a) would stabilize at VFVC VCO. According
to Eq. (51), this means that the resulting oscillation fre-

640

HARMONIC OSCILLATORS, CIRCUITS

t0

VOSC
Vbf

VOSC

VCO

VFVC

go

Vref

u(t)

Monostable

PD

g0
+

FVC

v(t)

+
VCO
(a)

(b)

v(t)
u(t)
Figure 9. A frequency control loop can provide a linear dependence between tuning
voltage and VCO frequency, and can also make this dependence temperature and prototype independent. (a) It can be made by adding a FVC and an integrator to a VCO.
(b) The FVC can be made with a calibrated monostable, a reference voltage, a peak
detector, two OTAs, a capacitor, and a switch. (c) After a transient the FVC output
stabilizes to a steady state voltage which depends linearly on the input signal frequency.

VCO VF0

(52)

which is linear and temperature independent.

A possible implementation with OTAs of the FVC is shown
in Fig. 9(b). It uses two OTAs of transconductance g0, a capacitor C, a peak detector, a switch, a temperature independent
voltage reference Vref , and a monostable triggered by the oscillating signal VOSC. During each period T 1/f of signal VOSC
the monostable delivers a pulse of constant width t0, which
must be temperature independent and well calibrated. Many
times it is convenient to add a sine-to-square wave converter
(and even a frequency divider) between VOSC and the monostable. The circuit of Fig. 9(b) uses three components that are
not temperature independent and may vary over time and
from one prototype to another: the two OTAs and the capacitor. However, provided that both OTAs have the same transconductance (which is a reasonable assumption for VLSI implementations), the resulting parameters and VF0 do not
depend on C nor g0. An example of the time waveforms of
u(t) and v(t) of Fig. 9(b) is shown in Fig. 9(c). During each
period T of VOSC the monostable is triggered once, turning the
switch ON during a time t0. While the switch is ON capacitor
C is charged by a constant current g0(Vref v(t)), and when
the switch is OFF a constant current of value g0v(t) discharges it. The output of the FVC v(t) changes from cycle to
cycle but is constant during each cycle. If vm is its value during one cycle and vm1 for the next one, it follows that
u(t + T ) = u(t) +

go vm+1
g0 (Vref vm )
to
(T t0 )
C
C

(c)

where u(t) is taken at one of the peaks: u(t) vm and u(t

T) vm1. Consequently,

quency f 0 depends on VCO as

fo =

t0

(53)

vm+1 =

vm (C g0t0 ) + Vref g0t0

C + g0 (T t0 )

(54)

In the steady state of the FVC vm1 vm. Applying this condition to Eq. (54) and calling VFVC the stabilized value of vm,
yields
VFVC =

Vreft0
= Vref t0 f
T

(55)

Consequently, the circuit of Fig. 9(b) implements a FVC with

Vref t0 and VF0 0, which both are temperature and prototype independent.
FURTHER CONSIDERATIONS
The different concepts and considerations mentioned so far
have been illustrated with practical circuits using either resistors, capacitors, and opamps, or using OTAs and capacitors. There are many other circuit techniques available that
can be used to implement the different blocks and equations
needed for stable harmonic oscillator circuits. Some of these
techniques could be continuous current mode, switched capacitor, switched current, digital circuit techniques, or even any
combination of these techniques.
Depending on the frequency range of the oscillator it may
be necessary to consider circuit parasitics that have not been
mentioned so far. For example, opams and OTAs both have
nonideal input and output impedances, leakage currents, and
most importantly gains which are frequency dependent. All
these parasitics result in modified characteristics equations.

HARMONIC OSCILLATORS, CIRCUITS

A very sensitive parameter to parasitics is the oscillation condition b0 required for initial startup. Since in practice it is
desirable to have b0 very close to zero but still guarantee its
negative sign, it is apparent that parasitics can result in either very negative (resulting in very distorted sinusoids) or
positive (resulting in no oscillation) values. Each circuit technique has its own parasitics, and depending upon the in-

V0

tended frequency range, they will have a different impact on

the final oscillator performance. Consequently, for good oscillator design the dominant parasitics need to be well known
and taken into account.
Another interesting and advanced issue when designing
oscillators is distortion. Both amplitude control mechanisms,
limitation and AGC, are nonlinear and will introduce some

+
Apd

CPD

Idischarge

V 01

Apd

t
V0

V01

(a)

V0

V 02

V0

V02

Apd

Apd
CPD

Idischarge

CPD

Idischarge

Apd

Apd

t
V0

V0
(b)

641

(c)

Figure 10. Possible implementations for a peak detector: (a) One phase based (or half wave
rectifier based), (b) Two phase based (or full wave rectifier based), and (c) Four phase based
peak detector.

642

HARTLEY TRANSFORMS

degree of distortion. Is there a way to predict how much distortion will render an oscillator?

where,
|xn | |x1 |

In an oscillator with AGC for amplitude control, like in Fig.

7(d), the element that introduces most of the distortion is the
peak detector. Figure 10 shows examples of peak detectors
based on one-phase or half-wave [Fig. 10(a)], two-phase or
full-wave [Fig. 10(b)], and four-phase [Fig. 10(c)] rectifying
principles. For the four-phase case, either the oscillator
should provide two phases with /2 shift, or an additional integrator is needed. Peak detectors with more phases can be
implemented by linearly combining previous phases. Increasing the number of phases in the peak detector results in
faster response [delay pd in Eq. (41) is smaller for more
phases] and less distortion. However, all phases have to present the same amplitude, otherwise distortion will increase.
In practice, as the number of phases increases it becomes
more difficult (due to offsets and component mismatch) to
keep the amplitude of the phases sufficiently equal.
In the peak detectors of Fig. 10, whenever one of the
phases becomes larger than Apd it slightly turns ON its corresponding P transistor injecting a current into CPD until Apd
increases sufficiently to turn OFF the P transistor. The discharge current ensures that Apd will follow the amplitude of
the oscillations if it decreases. Increasing Idischarge results in
faster response but higher distortion. Whatever peak detector
is used, waveform Apd(t) is not constant nor sinusoidal. It has
a shape similar to those shown in Fig. 10. Since Apd(t) is periodic its Fourier series expansion can be computed,
Apd (t) = A0 +

an cos(n0t + n )

(56)

(60)

|yn | |y1 |

Distortion for Amplitude Control by Automatic Gain Control

In general, this problem is solved numerically for a finite set

of harmonics. Let N be the highest harmonic to be computed.
Since f(x(t)) is also periodic, computing its Fourier series
expansion yields that of y(t). Therefore, given a set of parameters for x(t) x1, . . . xN, 2, . . . N the set of parameters y1,
. . . yN, 1, . . . N for y(t) can be obtained this way. By
applying each component of y(t) (characterized by yn and n)
to filter H(s) yields the corresponding component for x(t),
xn = yn |H( jn0 )|
n = n + phase(H( jn0 ))

(61)

By iterating this procedure until all values xn, yn, n, and n

converge, the distortion of x(t)

THD(x) =


2
N 

xn
n=2

x1

(62)

or y(t)

THD(y) =


2
N 

yn
n=2

y1

(63)

can be predicted.
Reading List

n=1

The high-order harmonic components a2, a3, . . . are those

which contribute to distortion at node V0 [in Fig. 7(d)].
Applying the filtering functions that go from node Apd,
through Vb4, to V0 [Eqs. (4143) and (48)] to these higherorder harmonics provides their amplitudes at node V0,
Ao
|A0n | =
|1 + jn0 mAGC ||1 jn0 pd ||an |
2AGC n2 o2

(57)

The total harmonic distortion at the output of the oscillator is

then defined as

THD(V0 ) =




A
n=2

2
0n

A0

(58)

K. K. Clarke and D. T. Hess, Communication Circuits: Analysis and

Design, Reading, MA: Addison-Wesley, 1978.
A. Gelb and W. Vander Velde, Multiple Input Describing Functions
and Nonlinear System Design, New York: McGraw-Hill, 1968.
E. J. Hahn, Extended harmonic balance method, IEE Proc. Part-G,
Circuits Devices Syst., 141: 275284, 1994.
B. Linares-Barranco et al., Generation, design and tuning of OTA-C
high-frequency sinusoidal oscillators, IEE Proc. Part-G, Circuits
Devices Syst., 139: 557568, 1992.
E. Vannerson and K. C. Smith, Fast amplitude stabilization of an RC
oscillator, IEEE J. Solid-State Circuits, SC-9: 176179, 1974.

BERNABE LINARES-BARRANCO
A NGEL RODRIGUEZ-VAZQUEZ
National Microelectronics Center
(CNM)

Distortion for Amplitude Control by Limitation

This problem is computationally complicated but can be
solved by harmonic balance. Consider the general block diagram of Fig. 5. In the steady state, periodic waveforms x(t)
and y(t) can be expressed by their respective Fourier series
expansions

x(t) = x1 cos(0t) +

xn cos(n0t + n )

n=2

y(t) =


n=1

yn cos(n0t + n )

(59)

HARMONICS. See POWER SYSTEM HARMONICS.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

HYSTERESIS IN CIRCUITS
Hysteresis, in simple terms, is the tendency of a system to resist change. This tendency may be created in a
variety of ways, and so we may observe hysteresis in many diverse kinds of systems: electrical, mechanical,
physical, biological, and others. Once a system with hysteresis is in one state, it requires a suitable amount of
energy to overcome this tendency in order to move the system to another state. Hysteresis can also describe how
a system remembers a past response. This memory may be considered a storage of energy, like a capacitor
or inductor, but is really a form of dynamic tension.
Hysteresis is a nonlinear phenomenon. Thus, it cannot be described using simple linear operations (addition, subtraction, multiplication, differentiation, etc.). The mathematical description of hysteresis has been
an intense area of research in recent years. However, hysteresis has been known and understood by electrical
engineers for many years and in numerous forms: as a cause of energy loss and heating in the ferrite cores of
transformers, as a fundamental building block in the design of some electronic oscillators, and so on.

The Hysteresis Function

The hysteresis function can best be illustrated by comparison using the transfer functions shown in Fig. 1.
The input to each function is given on the horizontal x axis, and the output is given on the vertical y axis. The
curve in Fig. 1(a) is a simple piecewise linear transfer function with gain A = y/x = 2 limited above and below
by 2. The three curves are identical, except that there exists a region in the domain of x for the curve in Fig.
1(b,c) for which there are two possible solutions in the range of y. In this example, the curve in Fig. 1(a) may
be expressed as

However, for the curve in Fig. 1(b), one must know something about the previous value of x in order to determine
the corresponding y:

The determination of y based on previous values of x is illustrated by the arrows in Fig. 1(b). If the first value
of x is larger than 2, then the output value of y begins at 2 and follows line segment A. If the following values
of x remain larger than 2, the resulting values of y follow the arrows around the curve to the left, along
1

HYSTERESIS IN CIRCUITS

Fig. 1. Comparison of (a) simple nonlinear transfer function with (b) positive hysteresis and (c) negative hysteresis. Note
that the directions of the arrows for (b) and (c) traverse the curve in opposite directions.

segments A and B. If, however, the value of x falls below 2, the resulting values of y will follow the arrows on
line segments C and D. This tracing of the hysteresis curve is known as positive hysteresis. There is one other
way to trace the curve, as shown in Fig. 1(c). This alternative path around the hysteresis curve is negative
hysteresis.

HYSTERESIS IN CIRCUITS

Hysteresis in Ferromagnetism
Ferromagnetic materials include the elements iron (Fe), cobalt (Co), and nickel (Ni), and many of their alloys
and composites, as discussed by Plonus (1). The use of ferromagnetic materials in electrical and electronic
systems can be found in transformers, motors, generators, inductors, and the like (see Magnetic Materials and
Induction Motor Drives).

Hysteresis in Electronic Systems

In addition to ferromagnetic systems, electronic systems may also exhibit hysteresis. In these instances, there
are usually two major contributing features: upper and lower limits, such as power supply voltages, and a
positive feedback loop. Hysteresis can be used effectively in electronic systems as a building block in oscillator
design, as an input amplifier to help reject noise, or as a delay function.
Example: An Opamp Hysteresis Function. One simple hysteresis design using operational amplifiers (see Operational Amplifiers) is given in Fig. 2. Note that opamp 1 and resistors R1 and R2 constitute the
actual hysteresis element. Resistor R2 connects the output of opamp 1 to its positive input. This large amount
of positive feedback will force the circuit voltage at vh to be either the positive supply voltage V D or the negative
supply voltage V S . If we sweep the input voltage vi , the hysteresis voltage vh will have the transfer function
shown at the top of Fig. 3. To find the values of input voltage vi for which the hysteresis voltage vh will switch,
we have

If we make V R = 0, the equation in Eq. (3) simplifies to

This gives for the upper and lower trip voltages V U and V L respectively

and for the hysteresis width V HW

Thus, the trip voltages for the hysteresis may be designed using a ratio of resistors and the power supply
voltages. However, it is usually undesirable to have a voltage in such a system that swings from rail to rail.
To prevent this we may use another opamp amplifier such that the hysteresis voltage vh is attenuated. This
is shown using opamp 2 at the top of Fig. 2. By making R3 much larger than R4 , the output voltage vo may
be designed so that its signal swing is well away from the power supply voltages, preventing the output of
the hysteresis from saturating any following stages. This attenuation is shown at the bottom of Fig. 3. Also
note that this second amplifier is in the inverting configuration. Thus the trip voltages for the hysteresis are

HYSTERESIS IN CIRCUITS

Fig. 2. An electronic hysteresis can be constructed using monolithic operational amplifiers. The opamp at the bottom of
the figure has positive feedback. The amplifier at the top is in the inverting configuration. The center of the hysteresis can
be adjusted using V R .

determined by V D , V S , R1 , and R2 , and the output limits are determined by V D , V S , R3 , and R4 . We may
construct an inverting hysteresis by exchanging V i with V R in Fig. 2.
Circuit Model. In some cases it is desirable to have a model of the hysteresis function for use in
a hierarchical design instead of a complete circuit, as shown by Varrientos and Sanchez-Sinencio (2). The
hysteresis function may then be modeled as shown in Fig. 4.
A circuit symbol for the hysteresis function is shown in Fig. 4(a). The underlying model is given in Fig.
4(b). The resistors ra and rb are used as a voltage divider, and resistor rd and capacitor cd constitute a high-pass
filter, such that the difference voltage va vb is an all-pass filtering of the differential input voltage vp vn .
This difference voltage is then converted to a current using the transconductance io . The transconductance
equation is given as

From this equation, one may note that this transconductance current io depends somewhat on the output
voltage vo across it, and that this dependence is positive. Therefore, the term vo va is positive feedback. Also,
note that the term va vb is a phase delay term, making the hysteresis element a function of the speed and/or
frequency of the input signal vp vn . Generally, this is the case for practical implementations.
The resistor ro and capacitor co at the output of the hysteresis element help determine the rise and fall
times, or slew rate, of the output voltage. The diodes dn and dp and voltages vn and vp define the limits of the
output voltage. For this model, the voltages vn and vp also give the trip voltages, like those illustrated in Fig.
3. Finally, this circuit model can be described using the circuit simulator SPICE. An example appears in Fig.
5. In this example, the diode model used gives a near-ideal diode, clamping the limit voltages at 0.5 V and the
trip voltages at twice the limit voltages, or 1 V.

HYSTERESIS IN CIRCUITS

Fig. 3. The transfer functions for the opamp hysteresis in Fig. 2. The output of the first opamp will have the transfer
function shown at the top. Note that it has limits at the power supply voltages. After attentuation using the second opamp,
the transfer function will look like the trace at the bottom of the figure. The trip voltages are given by the first opamp, and
the output limits are given by the second opamp.

Higher-Order Hysteresis
As was mentioned in the introduction, a hysteresis element may be thought of as a single energy storage unit.
The amount of storage is determined by the width and height of the hysteresis. It is then possible to increase
the order of the system in which the hysteresis appears, for example, by increasing the number of hysteresis
storage elements. To do this, we may add other hysteresis elements in a given system, or we may increase
the number of storage elements in a given hysteresis element. This latter method of increasing the order of a
hysteretic element gives higher-order hysteresis. Hysteresis of this type has uses in complex nonlinear systems
such as chaotic oscillators (3) (see Chaos, Bifurcation, and their control).

HYSTERESIS IN CIRCUITS

Fig. 4. The hysteresis symbol (a) can be modeled using the simple nonlinear circuit (b) shown at the bottom of the figure.
All the components are linear except for the diodes dp and dn . The trip voltages and output limits are a function of vp and
vn .

Linear Combination. By combing several hysteresis elements linearly using inverting and/or summing
amplifiers, higher-order hysteresis functions can be derived (2). A block diagram of a general design approach
for higher-order hysteresis is given in Fig. 6. The approach begins with the design of trip values for each
hysteresis by determining a reference value to shift the hysteresis either left or right and then amplifying (or
attenuating) the hysteresis output of each element. Continuing, we may then combine the outputs of several
such elements to construct a composite hysteresis with many storage regions. By example, we may combine
two hysteresis elements shown in Fig. 2 to construct a composite hysteresis with two nonoverlapping storage
regions. This result is shown in Fig. 7. The value of gives the hysteresis width, is the distance of the center
of each width from the origin, and D is the magnitude of the limit.
Differential Hysteresis. In addition to linear combinations, complex hysteresis functions can also be
constructed using cross-coupled feedback and nonlinear combinations as shown by Varrientos and SanchezSinencio (2). One example appears as Fig. 8. This hysteresis element is comprised of two hysteresis elements
and two comparators referenced to a common ground. Because of the finite response of each amplifier, this
hysteresis composite will have two hysteresis regions. The result is similar to the transfer function given for
linear combinations in Fig. 7. Note that by increasing the limit voltages on the comparator elements, we also
vary the reference voltage for each hysteresis. The result is that each storage region reduces in width and
increases in distance from common ground.

HYSTERESIS IN CIRCUITS

Fig. 5. This SPICE input file can be used to model the hysteresis shown in Fig. 4. The parameters given for the diode
model will make the diodes almost ideal.

Fig. 6. Higher-order hysteresis can be constructed using linear combinations of simpler hysteresis elements. Here the
elements are combined using amplifiers (multiplication) and summing nodes.

Mathematical Descriptions
Often, hysteresis is found in systems with steady-state sinusoidal solutions where the input to the hysteresis
is sinusoidal. The hysteresis, whether desirable or not, contributes to the solution, and as engineers we would
like to know the extent of the interaction between the linear and nonlinear portions of the system.
Describing Functions. One way of doing this is with the use of describing functions as shown by Gelb
and Vander Velde (4). A describing function is a nonlinear function in the steady-state s domain. Thus, we may,
using the describing function for a given nonlinearity, solve for the solution of a system using linear algebra.
Differential Model for Hysteresis. Often, however, we would like a time-varying, or transient, solution
for our system with hysteresis, where the s-domain description is not sufficient. In recent years, mathematicians
have been investigating the underlying fundamental dynamics of hysteresis as shown by Visintin (5). It remains
an active area of research because of the difficulty mathematicians and engineers have had in constructing
a sufficiently accurate differential expression for many types of common hysteresis, including the hysteresis
found in ferromagnetism.

HYSTERESIS IN CIRCUITS

Fig. 7. The transfer function of a second-order hysteresis function. Note that there are two hysteresis regions, one for
each simple hysteresis element. The value of D is the upper and lower limit, is the hysteresis width, and is the distance
from the center of each hysteresis width of the origin.

Fig. 8. Higher-order hysteresis can also be constructed using cross-coupling and nonlinear feedback. The output limits
of the comparators shown determine the width of the hysteresis and their offset from the origin.

However, several differential expressions exist. One of the most common is a variation on the differential
equation given by Rossler (6):

where x(t) is the time-varying input and y(t) is the output. The values of S and D are derived from the upper
and lower trip values; generally, S = 2.0/(V U V L ) and D = SV L + 1.0. Loss in the hysteresis is due to a variety
of sources in practical systems and is modeled with the damping factor . The value of is small so that the
hysteresis response reaches its saturation quickly.

HYSTERESIS IN CIRCUITS

Fig. 9. In CMOS design, is it possible to design hysteresis using currents as parameters? Here the upper and lower trip
input currents are determined by I1 and I2 .

Another popular hysteresis equation is the BoucWen differential equation used by Wong, Ni, and Lau
(7):

where the quantities , , , and n are system parameters that determine the shape and magnitude of the
hysteresis this equation produces. The parameters , , and n are positive real numbers, and may be a positive
or negative real number. Typical values are = 1.0, = 0.1, = 0.9, and n = 1.0.
Both of the equations above give hysteretic responses that are like those given for ferromagnetic materials
(see Magnetic Materials) and for the monolithic responses that follow. The difficulty in using such equations
is that, unlike the circuit model given above, they are sensitive to the speed of the input signal and will have
responses that vary widely for a given set of inputs. Generally, these equations work best with systems that
have well-behaved limit cycles as solutions, sinusoidal oscillations being one example .

Monolithic Implementations
In integrated circuit design, simple implementations of hysteresis elements can be constructed. One such
(8), is shown in Fig. 9. This hysteresis is performed
hysteresis element, proposed by Wang and Guggenbuhl
in the current mode, since the signals and the trip values are determined by currents rather than voltages. In
this circuit, the input current ii is mirrored through the current mirror M 5 , M 6 into the high impedance node
vo . If the input current ii is smaller than I1 , the voltage at vo will be near V D , turning on M 1 and turning off
M 2 . The total current flowing into vo from the current mirror M 3 , M 4 will now be I1 + I2 . Now, in order to lower
the voltage at vo , the input current ii must exceed I1 + I2 . Once this happens, the voltage at vo will be near V S ,
turning off M 1 and turning on M 2 , so that the current entering the node vo from the current mirror M 3 , M 4
will again be I1 . The upper and lower trip current values will be

10

HYSTERESIS IN CIRCUITS

Fig. 10. An input signal to a hysteresis element that is fast in comparison with the switching speed of the hysteresis will
cause the width of the hysteresis to increase. If the input signal is too fast, the phase of the hysteresis transfer function
will be inverted.

The hysteresis width IHW will be IH IL = I2 . Thus the hysteresis is easily adjustable using only two currents,
and is independent of the power supply voltages. However, matching between the transistors of each current
mirror and the slew rate of the output node vo may be critical for fast-moving input signals.
Speed Tradeoffs. As was mentioned earlier, the width of the storage region of the hysteresis element
will be affected by the speed and/or frequency of the input signal. This is because every practical implementation
has practical limits to how fast a signal or node can move. These limits are a function of the voltage swing, load
and parasitic capacitances, and bias currents. These effects are modeled in the hysteresis circuit model given
in Fig. 4. A transient response of this hysteresis for 1 kHz sinusoidal signal is given in the top trace of Fig. 10.
If we keep the frequency of the input signal constant, but increase the value of the capacitance cd in Fig. 4,
we will increase the response time (phase delay) of the hysteresis. The effect will be to slow the hysteresis down
with respect to its input signal. The effect of increasing the response time is shown in the second trace of Fig.
10. Even though we have not changed the value of the trip or limit voltages vp and vn , we have, nonetheless,
increased the width of the hysteresis. Parasitic capacitances will have the same effect if we try to make the
hysteresis go faster than its fundamental limits will allow it to go. However, the effect can be even more drastic
if we increase the amount of phase delay even further. This is shown in the third trace in Fig. 10. Note that a
further increase in phase delay has caused the hysteresis to actually become inverted. Also note that the width
of the hysteresis is smaller than its design value. Here the input signal is so much faster than the hysteresis
circuit than the magnitude of the phase delay has changed the sign of the hysteresis element.
Another effect of fast signals is in the speed at which the output voltage can change from a low value to
a high value. This effect is shown in Fig. 12. We may note that as we increase the capacitance co in Fig. 4,
the slope of the output voltages begins to reduce in magnitude, decreasing the slew rate of the output voltage
swing. This effect is caused by additional capacitive loading at the output of the hysteresis. Compare this
with Fig. 10 and note that there the voltage transitions are very steep in comparison. Also note that the two
phenomena have a similar effect on the width of the hysteresis; for both, an increase in capacitance increases
the hysteresis width.
Example: A Relaxation Oscillator. As an example of hysteresis design, consider the relaxation oscillator in Fig. 11 (see Relaxation Oscillator). This oscillator works by charging and discharging the capacitor
C through R3 at the limit voltages at the output of opamp 1. Recognize that opamp 1 and resistors R1 and

HYSTERESIS IN CIRCUITS

11

Fig. 11. A hysteresis-based relaxation oscillator. The first opamp is in the positive feedback configuration, and the second
opamp is a voltage buffer. Oscillations are caused by the charging and discharging of the capacitor.

Fig. 12. A large capacitance on the output of the hysteresis may cause it to slew. Large load capacitances will make the
width of the hysteresis increase.

R2 constitute a hysteresis element, that opamp 2 is in the voltage follower configuration, and that R3 and C
constitute an RC time constant.

BIBLIOGRAPHY
1. M. A. Plonus Applied Electromagnetics, New York: McGraw-Hill, 1978.
2. J. E. Varrientos E. Sanchez-Sinencio A 4-D chaotic oscillator based on a differential hysteresis comparator, IEEE Trans.
Circuits Syst. I, Fundam. Theory Appl., 45: 310, 1998.

12

HYSTERESIS IN CIRCUITS

3. T. Saito S. Nakagawa Chaos from a hysteresis and switched circuit, Phil. Trans. R. Soc. Lond. A, 352: 4757, 1995.
4. A. Gelb W. E. Vander Velde Multiple-Input Describing Functions and Nonlinear System Design, New York: McGraw-Hill,
1968.
5. A. Visintin Differential Models of Hysteresis, Berlin: Springer-Verlag, 1994.
6. O. E. Rossler The chaotic hierarchy, Z. Naturforsch., 38a: 788801, 1983.
7. C. W. Wong Y. Q. Ni S. L. Lau Steady-state oscillation of hysteresis differential model, J. Eng. Mech., 120: 22712298,
1994.
CMOS current Schmitt trigger with fully adjustable hysteresis, Electron. Lett., 25: 397398,
8. Z. Wang W. Guggenbuhl
1989.

JOSEPH E. VARRIENTOS
Dallas Semiconductor Corporation

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

IIR FILTERS
IIR or infinite-length impulse response digital filters have impulse responses of infinite length, which extend
over all time. FIR or finite-length impulse response filters do not. IIR filters are also called recursive filters,
or less frequently, ladder, lattice, wave digital, pole-zero, autoregression moving average (ARMA), and autoregression integrated moving average (ARIMA) filters. FIR filters are also called nonrecursive filters, as well as
moving average, delay line and tapped delay line, feedforward, all-zero, and transversal filters (1). From all
these names, we choose to classify digital filters as IIR or FIR.
Terms such as IIR are usually applied to digital filters rather than analog filters. Digital filters operate
in discrete time, and analog filters operate in continuous time (2). Digital filters are usually analyzed using
the z-transform (denoted Z[ ]), whereas analog filters are analyzed using the Laplace transform (denoted L[ ]).
There are very close analogies between the two filter types, and these are often exploited in design.
From a design standpoint, IIR and FIR filters compete with each other. IIR filters have many desirable
properties, which are listed in Table 1. Their design is easy if frequency transformations and other methods are
used. Well-known classical analog filters like Butterworth can be used. Low-order IIR filters can have gains
with sharp cut-off and high selectivity. IIR filters can be implemented using little storage, short delays, and a
small number of arithmetic computations.
IIR have several undesirable properties. They can be unstable. They are stable only if their poles lie inside
the unit circle (assuming causality). They can never have linear phase unlike FIR filters. They are generally
more difficult to design unless frequency transforms are used. Nevertheless, their desirable characteristics
generally far outweigh these undesirable properties, so IIR filters are the most widely used in industry.
IIR filters can be implemented using a variety of techniques. These are summarized in Table 2. The most
popular methods include numerical integration or digital transforms, several invariant time domain response
designs, and matched z-transform design. IIR filters can also be designed using FIR filter design techniques
(1).

Basic Description
A linear digital filter is characterized by its impulse response h(n). The impulse response relates the filter input
x(n) and output y(n) as

when the filter is time-invariant and represents the convolution operation. Taking the z-transform of both
sides gives

IIR FILTERS

If the filter is time-varying, then y(n) = h(n,m) x(m) and Y(z2 ) = H(z1 ,z2 )X(z2 ). In this case, h(n,m) and
H(z1 ,z2 ) are two-dimensional functions. Such digital filters will not be considered, but their analysis and design
is a direct extension of what will be presented here (3). The general time domain form [Eq. (1)] and frequency
domain form [Eq. (2)] of the digital filter are shown in Fig. 1.
IIR filters have transfer functions that can be expressed in the product form

The values of z where H(z) = 0 are called the zeros zk of the filter. The values of z where 1/H(z) = 0 are called
the poles pk of the filter. Any common terms in numerator and denominator are usually canceled out. The IIR
filter gain can also be expressed in the polynomial form

IIR FILTERS

As mentioned before, based on the form of Eqs. (3) and (4), such digital filters are classified in two broad groups
as IIR when the denominator D(z) = 1 and FIR when D(z) = 1.
Rearranging Eq. (4) as Y(z) = H(z)X(z), taking the inverse z-transforms of both sides, and solving for x(n)
gives

This is the time-domain equation used to generate the filter output y(n) from the input x(n). Because feedback
of the output (or so-called recursion) depends upon bk , Eq. (5) makes it clear that the digital filter is recursive
when bk = 0 and nonrecursive when bk = 0. The characteristics of the digital filter are controlled by its gain
H(z) and impulse response h(n).
We first describe some of the overall filter properties based on H(z) and h(n). A digital filter is causal or
nonanticipatory if its impulse response is zero for negative time,

IIR FILTERS

Fig. 1.

Block diagram of digital filter in (a) time domain form and (b) frequency domain form.

Most real-time filters are designed to be causal. Causality can also be tested using H(z) and the Paley-Wiener
criterion (1). Noncausal filters can often be made causal by delaying its impulse response and truncating its
negative time portion. This changes its gain H(z) very little if only a small portion is truncated.
Another important property is stability. A causal digital filter is stable if its impulse response decays to
zero as time approaches infinity,

Causality is easily tested by inspecting the poles of H(z). A causal digital filter is stable when all the poles
of H(z) lie inside the unit circle of the z-plane and any poles on the unit circle are simple or first-order. Most
digital filters are designed to be both causal and stable (4).
Digital filters are designed using frequency domain and time domain techniques. In the frequency domain
approach, an analog filter transfer function H(s) is directly converted into a digital filter transfer function H(z)
using some form of

g(z) is the desired digital transform. The resulting H(z) generally has frequency-domain and time-domain
responses that differ considerably from the analog filter responses from which they were derived.
A time-domain approach preserves a particular temporal response of the analog filter used to form the
digital filter as

where x(n) and y(n) are the sampled input and output, respectively, of the analog filter. Equivalently, H(z)
is the z-transform of h(n). When the sampling frequency f s = 1/T Hz is sufficiently high compared with the
stopband frequency of the analog filter, the frequency response characteristics are preserved. Otherwise, there
is noticeable aliasing distortion.
We should note a convention that is standard. The samples are taken at time t = nT. The input x(t) is
sampled to produce x(nT). To simplify notation, this is written in shorthand as x(n). This is true for all analog
filter variables when they are converted into digital filter variables.

IIR FILTERS

Frequency-Domain Algorithms
Digital transforms directly convert an analog transfer function H(s) into a digital transfer function H(z) using

g(z) is the desired digital or discrete transform. The resulting H(z) generally has frequency-domain and timedomain responses that differ considerably from those of the analog filter from which they were derived.
Only s-to-z mappings that map the imaginary axis of the s-plane onto the unit circle of the z-plane preserve
certain frequency-domain characteristics like the passband and stopband magnitude response ripples and
phase variations. Delay and time-domain responses are distorted.
Numerical Integration Transform Design. One especially simple way to obtain digital transforms
is to approximate continuous integrators by discrete integrators (5). Equating the continuous time transfer
function H(s) = 1/s to the discrete time equivalent H(z) = 1/g(z) results in s = g(z), which is the digital transform.
The digital transfer function H dmn (z) of the discrete integrator is chosen to equal

d is the number of zeros at the origin, m is the number of finite zeros including those at the origin, and n is the
number of finite poles in the z 1 plane. The ak and bk are selected so that H dmn well approximates the transfer
function of an analog integrator H(s) = 1/s when z = e sT =
k = 0 (sT)k /k!. This method generates an infinite
number of digital transforms (1).
Some of them and others are listed in Table 3. We have selected the backward and forward Euler, bilinear,
modified bilinear, lossless, and optimum transforms. These transforms involve a constant C, which is adjusted
so that the analog frequency = 1 rad/s maps into any desired digital filter frequency B rad/s, and normalized
frequency BT radians or 360 f /f s degrees. The bilinear transform, denoted as H 011 , is perhaps the most popular
and widely used where

and C = tan(BT/2). This transformation maps the imaginary axis of the s-plane describing the analog filter unto
the unit circle of the z-plane describing the digital filter. Therefore, except for frequency warping, the magnitude
and phase characteristics of the analog filter are preserved exactly. The delay, which is the derivative of the
phase, changes as does the step response. Of the many transforms available, the bilinear transform is the most
widely used because it has the desirable mapping property just mentioned.
An important comment should be made. Causal and stable analog filters are not always mapped into
causal and stable digital filters using these transforms. The backward Euler, bilinear, and optimum transforms
do produce causal and stable filters, but the forward Euler and lossless transforms do not (1). When using
general transforms, the poles of H(z) should always be verified to be inside or on the unit circle (assuming
causality).
Other Filter Types. The transforms of Table 3 are usually used to map analog filter transfer functions
into digital filter transfer functions. If the analog filter is lowpass, these transforms produce a digital highpass
filter. If the analog filter is bandpass, the transforms produce a digital bandpass filter.

IIR FILTERS

However, they can also be used to convert analog lowpass filters to the other types directly. If the reciprocals
of s are used in Table 3, digital highpass filters are produced. If the transforms in Table 4 are used, digital
bandpass filters are produced directly. If the reciprocals of s are used in Table 4, then digital bandstop filters
are produced directly. Thus analog lowpass filters can be converted directly into any of these other filter types
by using Tables 3 and 4.
These other filters can be obtained by a simpler and more direct scheme. After a lowpass digital filter H(z)
is obtained, it can be converted into a highpass filter using H(z) = H(zej ). It can be converted to a singlesideband bandpass filter using H(zej 0 T). Therefore, by simply rotating the pole-zero pattern of the lowpass
H(z) by degrees in the z-plane, other filter types can be obtained. These filters have the same arithmetic shape
but have different geometric shapes, the proper bandwidths, etc. The proper shape is always maintained by
using the transforms in Tables 3 and 4.

IIR FILTERS

IIR FILTERS

Time-Domain Algorithms
Time-domain algorithms preserve a particular temporal response of the analog filter used to form the digital
filter. Mathematically, the invariant time-domain transform uses

where h(n) is the sampled impulse response of the analog filter. Equivalently, H(z) is the z-transform of h(n)
(6). When the sampling frequency f s = 1/T Hz is sufficiently high compared with the stopband frequency of the
analog filter, the frequency response characteristics are preserved, and there is noticeable aliasing distortion.
Impulse-Invariant Transform Design. The impulse-invariant transform preserves the impulse response h(t) of the analog filter (7). Setting the input to be an impulse as x(t) = U 0 (t) in Eq. (13) gives X(z) = 1/T
and

If the analog transfer function H(s) is band-limited to || < s /2, then the digital filter has exactly the same
magnitude, phase, and delay responses of the analog filter for || < s /2. Otherwise, the frequency responses
are not identical because aliasing occurs. Nevertheless, the impulse responses are identical at the sample
times.
Suppose that H(s) is causal. Its transfer function can be expanded as a partial fraction as

assuming N > M. The impulse response of the analog filter equals

Taking the z-transform of h(t) and multiplying by T gives the impulse-invariant digital filter gain as

Modied Impulse-Invariant Transform Design. An interesting alternative the impulse-invariant

transform is the modified impulse-invariant transform (8). For an analog transfer function H(s) = N(s)/D(s),
its poles were preserved but its zeros were not in Eq. (17). However, the zeros can also be preserved using the

IIR FILTERS

following method. Express two new transfer functions as

which are all-pole low-pass filters. Their impulse-invariant response versions equal

Forming the ratio of these two transfer functions produces the modified impulse-invariant transform as

This is the product of the matched-z transform of the next section and a N 2 (z)/N 1 (z) compensator.
Because this method relies on closely approximating the frequency responses of both the numerator N(s)
and denominator D(s) of H(z) regardless of their orders, H(z) well approximates H(s) in ac steady state.
Matched-z Transform Design. One of the simplest design methods is the matched-z transform. It
uses the z-transform z = esT to map every analog pole pk and every analog zero zk into their equivalent
digital pole zp = e pkT and zero zz = e zkT , respectively. Using this approach, Eq. (15) maps as

We see that its transfer function has a related form to Eqs. (17) and (20). The impulse-invariant transform
Eq. (17) has the same denominator but a different numerator. The modified impulse-invariant transform Eq.
(20) has the same denominator and numerator but is multiplied by a compensator. The matched-z transform
does not preserve frequency-domain characteristics such as magnitude ripple and delay, nor does it preserve
time-domain responses. Its major advantage is ease of application.
Complementary Design. On a related topic, a complementary digital filter H c (z) can be obtained from
a digital filter H(z) using

The impulse responses of these two filters add to a step function U 1 (n) so the responses are said to be
complementary. Therefore, these two filters maintain their time domain impulse response characteristics such
as delay and rise (fall) times, overshoot (undershoot), etc. If one filter is low-pass, its complementary filter
is high-pass. If one filter is bandpass, its complementary filter is bandstop. This is an especially convenient
approach because it generates an additional filter with little additional computational cost (1).

10

IIR FILTERS

Fig. 2.

Magnitude gain response specification of (a) digital filters and (b) analog filters.

Filter Orders
Digital filters generally have frequency-domain specifications like that drawn in Fig. 2 where
f p = maximum passband frequency (Hz) for M p (dB) maximum ripple
f r = minimum stopband frequency (Hz) for M r (dB) minimum rejection
f s = sampling frequency (Hz) = 1/T seconds
These are usually converted to the normalized frequency form as where
p T = 360 f p /f s = maximum passband frequency in degrees
r T = 360 f r /f s = minimum stopband frequency in degrees
d = r T/p T = stopband/passband frequency ratio.
From such (M p ,M r ,r ) frequency specifications, the digital filter order n is determined from nomographs
using the following procedure. This can be easily done for classical analog filter transfer functions (like Butterworth and Chebyshev) combined with the digital transforms (like bilinear) discussed earlier (9).
Frequency Warping. Consider the bilinear transform of Table 3 and its associated frequency relation

where z = j and s = jv (after some manipulation). The analog filter frequencies v = (0,1,) map into the digital
filter frequencies T = (0,BT,). Therefore the bilinear transform compresses the high-frequency response of
the analog filter into frequencies approaching radians in the digital filter. Thus the digital filter order will be
less than the analog filter order, or at most equal, using this transform.
Other transforms have other constants. For example, the Euler transforms have vT = sin(T) or T =
sin 1 (vT). These transforms expand rather than compress the higher-frequency filter response. The digital
filter orders will be no less, and often greater, than the analog filter orders using the Euler transforms.
As the sampling frequency f s approaches infinity or the sampling interval T approaches zero, all properly
formulated discrete transforms produce digital filters whose transfer functions approach that of the analog
filter from which they were all derived. For example, the bilinear transform in Eq. (23) has frequencies that

IIR FILTERS

11

are related as

so that T
= vT at low frequencies. Therefore, the low-frequency responses of all the digital filters and the
analog filter must be identical. However, as T increases from zero, this is no longer true, and the frequencies
begin to warp or diverge. In addition, for most transforms the locus of z no longer remains on the unit circle
as s moves up the imaginary axis. The frequency responses cannot remain similar, and considerable distortion
begins to appear. This does not occur with the bilinear transform whose locus remains on the unit circle.
To make this important point, we refer to Table 5. The various transforms are listed with their frequency
mappings for small T. Across the top of the table are listed percentage errors in the T/vT ratios ranging from
1 to 20%. Also listed are the digital frequencies T required for the error to be below this limit. For the bilinear
transform, normalized frequencies less than 43 will be warped less than 5%. For the Euler transforms, this
normalized frequency is reduced to 32 .
Analog Filter Nomographs. Analog filter nomographs are well-known and readily available (9).They
can be used directly to determine digital filter orders easily. The digital filter frequencies must be converted into
their equivalent or warped analog filter frequencies. The necessary frequency ratios listed in Table 6 must be
computed. These ratios are then entered onto the nomograph as shown in Fig. 3. The digital filter frequencies
d are converted into their corresponding analog filter frequencies a . These analog filter frequencies are then
transferred onto the nomograph as usual, and the analog filter order is determined.
Digital Filter Design Procedure. The design procedure for digital filters using discrete transform is
straightforward. It consists of the following steps (1):

1a.Select a suitable analog filter type (e.g., Butterworth, Chebyshev, elliptic).

1b.Choose a particular sn -to-z transform from Tables 3 and 4.
2.Determine the required analog filter order from the nomograph. Use Table 6.
3.Write the analog transfer function H(s) having unit bandwidth and the desired magnitude.
4.Compute the normalization constant and the discrete transform from Tables 3 and 4.
5.Compute the digital transfer function H(z) by substituting the sn -to-z transform of step 4 into the analog
transfer function H(s) of step 3.
6.Implement the transfer function using one of the realization techniques discussed later.

12

IIR FILTERS

Fig. 3.

Use of analog filter nomograph for computing digital filter order.

Design Examples
Now that we have introduced and described IIR filters, presented their frequency- and time-domain algorithms,
and described their design procedure, we now will unify this using design examples. We will design a fourthorder elliptic lowpass filter with 0.28 dB in-band ripple, a minimum of 40 dB stopband rejection, and a 1 kHz

IIR FILTERS

13

bandwidth using a 10 kHz sampling frequency. Using tables, the analog transfer function equals

The scaling constant 0.1363 is selected so that the dc gain H(0) is 0.28 dB. The maximum in-band gain is
then 0 dB. Most digital filters are designed following the procedure [or some modified version (10)] described in
the previous section. We have chosen both the analog filter type (i.e., elliptic) and order (i.e., 4). Now we choose
the design method and will now demonstrate each of them as discussed previously (1).
Bilinear Transfer Design Example. We choose the bilinear transform of Table 3. Because the desired
0.28 dB bandwidth is 1 kHz and the sampling frequency is 10 kHz, the normalized digital filter bandwidth is
360 (1 kHz/10 kHz) = 36 . The necessary constant then equals C = tan(36 /2) = 0.3249 = 1/3.078. The bilinear
transform then equals

14

IIR FILTERS

Fig. 4.

Multiple feedback (1F) realization of fourth-order elliptic digital filter.

Substituting this into the analog transfer function Eq. (25) produces the digital transfer function

The bilinear transform preserves the magnitude and phase response behavior of H(s) but with frequency
warping.
Impulse-Invariant Transform Design. The impulse-invariant transform preserves the impulse response h(t) of the analog filter. Expressing the gain Eq. (25) as a partial fraction expansion gives

where sn = s/2(1 kHz). Taking the inverse Laplace transform, sampling the resulting impulse response h(t)
at T = 1 ms, and z-transforming the result gives

This transform tends to maintain the frequency domain shaping of H(s) but with some aliasing.

IIR FILTERS

Fig. 5.

15

Cascade (1F) realization of fourth-order elliptic digital filter.

Modied Impulse-Invariant Transform Design. We express the numerator and denominator of the
analog filter Eq. (25) as separate transfer functions where

We convert these using the impulse-invariant transform to

Forming the ratio H 02 /H 01 gives the digital filter as

16

IIR FILTERS

Fig. 6.

Parallel (1F) realization of fourth-order elliptic digital filter.

The modified impulse-invariant transform produces a digital filter that more closely approximates the magnitude response of the analog filter.
Matched-z Transform Design. The analog filter poles and zeros of Eq. (25) are converted to digital
filter poles and zeros using the z-transform z = esT . Converting the poles and zeros gives

IIR FILTERS

17

Grouping these terms together, the digital filter transfer function equals

This method is simple and gives fairly good responses.

IIR Filter Realizations

To implement an IIR digital filter H(z) in either hardware or software, usually one of the structures listed
in Table 7 must be chosen. These structures are multiple feedback, cascade, parallel, lattice, ladder, analog
simulation, and wave. Because each form has many variations, a wide variety of implementations exist. To
conserve space, some of these implementation forms are now shown by examples but with no discussion. These
filter structures implement the fourth-order 0.28 dB elliptic digital filter whose H(z) is given by Eq. (25) as

The different realizations or structures result by expressing H(z) in different forms as will now be shown (1).
Multiple Feedback Structure. The multiple feedback structure uses H(z) in the summation form Eq.
(4) as

The constant 0.01201 can be included in the numerator as was done here or treated as an external multiplier.
(See Fig. 4.)
Cascade Structure. The cascade structure uses H(z) in the product form of Eq. (3) with biquads as

The poles and zeros are paired. Better performance is usually obtained by selecting pole-zero pairs separated
by a relatively constant distance. (See Fig. 5.)

18

IIR FILTERS

Fig. 7.

Lattice realization of fourth-order elliptic digital filter.

Parallel Structure. The parallel structure uses H(z) in the partial fraction expanson form of Eq. (17)
with biquads as

Notice here the biquad does not use a z 2 term but instead a 0.02864 constant. This reduces complexity. (See
Fig. 6.)
Lattice Structure. The lattice structure uses H(z) in a chain matrix product form. The process is
standard but lengthy and involves the simultaneous solution of equations. (See Fig. 7.)
Ladder Structure. The ladder structure uses H(z) in the continued fraction expansion or repeated long
division form as

IIR FILTERS

Fig. 8.

19

(a) Cauer 1 and (b) Cauer 2 ladder realizations of fourth-order elliptic digital filter.

for Cauer 1 (see Fig. 8a) and

for Cauer 2 (see Fig. 8b). The // denotes the repeated long division operation.
Analog Simulation Structure. The analog simulation structure uses tabulated RLC analog filters
which implement standard H(s). This ladder is put into flow graph form in which the L and C terms involve
1/s. These analog integrator terms are replaced by digital transforms as found in Table 3. This produces H(z)
structures. (See Fig. 9.)
Wave Structure. The wave structure of H(z) is a more complicated form of tabulated H(s) RLC ladders
(1).

IIR Filter Properties

Some of the most important digital filter properties are (1):
(1)
(2)
(3)
(4)

Complexity Related to the total number of delays, multipliers, and summers.

Cost Proportional to complexity.
Speed/sampling rate Related to complexity.
Memory Determined by the total number of delay elements and filter coefficients.

20

IIR FILTERS

Fig. 9. Analog filter simulation realization of fourth-order elliptic filter showing (a) RLC analog filter, (b) block diagram
equivalent, and (c) digital filter.

(5) Sensitivity of pole/zero locations Controlled by word length and arithmetic used in computations (fixed- or
floating-point).
(6) Data quantization, coefficient truncation, and product roundoff noise Determined by word length.
(7) Limit cycles Low-level oscillation that continues indefinitely as a result of quantization effects.
(8) Dynamic range Determined by word length, arithmetic used, and filter structure.
A digital filter requires addition, multiplication, and delay z 1 elements. The complexity depends directly
upon the number of elements required. They are listed in Table 7. Complexity depends indirectly upon filter
type (low-pass, high-pass, etc.), the filter gain characteristic (Butterworth, etc.), and the arithmetic used for
computations. Table 7 shows that multiple feedback structures are the simplest and wave structures are the
most complex. Cost in the general sense is proportional to complexity.
Speed is determined by the speed of the adders, multipliers, and delay (write/read) operations. If these
three digital filter elements have about the same speed, then speed is proportional to total complexity. Parallel
processing techniques can be used to increase speed.
The memory requirements are dictated by the number of delay elements required (data storage) and the
number of filter coefficients used (the ak and bk ). Memory is minimized by using canonical forms having the
minimum number of z 1 terms. Almost all the filter forms are canonical. The 3F and 4F multiple feedback
forms should be avoided because they require twice the number of delay elements.
The sensitivity of the polezero locations of the filter and its response depends upon the word length (i.e.,
finite word size and coefficient truncation) and the type of arithmetic used in the computations. Generally
floating-point arithmetic and long coefficient lengths produce the lowest sensitivity.

IIR FILTERS

21

BIBLIOGRAPHY
1. C. S. Lindquist Adaptive & Digital Signal Processing with Digital Filtering Applications. Miami, FL: Steward & Sons,
1989.
2. A. V. Oppenheim A. S. Willsky Signals & Systems, 2nd ed., Chaps. 910. Englewood Cliffs, NJ: Prentice-Hall, 1997.
3. R. C. Gonzalez P. Wintz Digital Image Processing, 2nd ed. Reading, MA: Addison-Wesley, 1987.
4. S. J. Orfanides Introduction to Signal Processing, Chap. 3.5. Englewood Cliffs, NJ: Prentice-Hall, 1996.
5. J. G. Proakis D. M. Manolakis Digital Signal Processing, 3rd ed., Chap. 8.3. Englewood Cliffs, NJ: Prentice-Hall, 1996.
6. S. D. Stearns D. R. Rush Digital Signal Analysis, Chap. 11. Englewood Cliffs, NJ: Prentice-Hall, 1990.
7. A. V. Oppenheim R. W. Schafer Discrete-Time Signal Processing, Chap. 7.1. Englewood Cliffs, NJ: Prentice-Hall, 1989.
8. A. Antoniou Digital Filters: Analysis and Design, Chap. 7.4. New York: McGraw-Hill, 1979.
9. C. S. Lindquist Active Network Design with Active Filtering Applications. Miami, FL: Steward & Sons, 1977.
10. S. D. Stearns R. A. David Signal Processing Algorithms, Chap. 7. Englewood Cliffs, NJ: Prentice-Hall, 1988.

CLAUDE S. LINDQUIST
University of Miami

INTEGRATED CIRCUITS

INTEGRATED CIRCUITS
The invention of the transistor in 1947 by William Shockley
and his colleagues John Bardeen and Walter Brattain at Bell
Laboratories, Murray Hill, NJ, launched a new era of integrated circuits (IC). The transistor concept was based on the
discovery that the flow of electric current through a solid
semiconductor material like silicon can be controlled by adding impurities appropriately through the implantation processes. The transistor replaced the vacuum tube due to its
better reliability, lesser power requirements, and, above all,
its much smaller size. In the late 1950s, Jack Kilby of Texas
Instruments developed the first integrated circuit. The ability
to develop flat or planar ICs, which allowed the interconnection of circuits on a single substrate (due to Robert Noyce and
Gordon Moore), began the microelectronics revolution. The
substrate is the supporting semiconductor material on which
the various devices that form the integrated circuit are
attached. Researchers developed sophisticated photolithography techniques that helped in the reduction of the minimum
feature size, leading to larger circuits being implemented on
a chip. The miniaturization of the transistor led to the development of integrated circuit technology in which several hundreds and thousands of transistors could be integrated on a
single silicon die. IC technology led to further developments,
such as microprocessors, mainframe computers, and supercomputers.
Since the first integrated circuit was designed following
the invention of the transistor, several generations of integrated circuits have come into existence: SSI (small-scale integration) in the early 1960s, MSI (medium-scale integration)
in the latter half of the 1960s, and LSI (large-scale integration) in the 1970s. The VLSI (very large scale integration) era
began in the 1980s. While the SSI components consisted on
the order of 10 to 100 transistors or devices per integrated
circuit package, the MSI chips consisted of anywhere from
100 to 1000 devices per chip. The LSI components ranged
from roughly 1000 to 20,000 transistors per chip, while the
VLSI chips contain on the order of up to 3 million devices.
When the chip density increases beyond a few million, the
Japanese refer to the technology as ULSI (ultra large scale

361

integration), but many in the rest of the world continue to call

it VLSI. The driving factor behind integrated circuit technology was the scaling factor, which in turn affected the circuit
density within a single packaged chip. In 1965, Gordon Moore
predicted that the density of components per integrated circuit would continue to double at regular intervals. Amazingly,
this has proved true, with a fair amount of accuracy (1).
Another important factor used in measuring the advances
in IC technology is the minimum feature size or the minimum
line width within an integrated circuit (measured in microns).
From about 8 m in the early 1970s, the minimum feature
size has decreased steadily, increasing the chip density or the
number of devices that can be packed within a given die size.
In the early 1990s, the minimum feature size decreased to
about 0.5 m, and currently 0.3, 0.25, and 0.1 m technologies (also called as deep submicron technologies) are becoming increasingly common. IC complexity refers, in general, to
the increase in chip area (die size), the decrease in minimum
feature size, and the increase in chip density. With the increase in IC complexity, the design time and the design automation complexity increase significantly. The advances in IC
technology are the result of many factors, such as high-resolution lithography techniques, better processing capabilities, reliability and yield characteristics, sophisticated design automation tools, and accumulated architecture, circuit, and
layout design experience.
BASIC TECHNOLOGIES
The field of integrated circuits is broad. The various basic
technologies commonly known are shown in Fig. 1. The inert
substrate processes, further divided as thin and thick film
processes, yield devices with good resistive and temperature
characteristics. However, they are mostly used in low-volume
circuits and in hybrid ICs. The two most popular active substrate materials are silicon and gallium arsenide (GaAs). The
silicon processes can be separated into two classes: MOS (the
basic device is a metal oxide semiconductor field effect transistor) and bipolar (the basic device is bipolar junction transistors). The bipolar process was commonly used in the 1960s
and 1970s and yields high-speed circuits with the overhead of
high-power dissipation and the disadvantage of low density.
The transistor-transistor logic (TTL) family of circuits constitutes the most popular type of bipolar and is still used in
many high-volume applications. The emitter-coupled logic

Basic technologies

Inert substrate

Thin film

NMOS

Active substrate

Thick film

Silicon

MOS

Bipolar

PMOS

CMOS

BI-CMOS

Gallium arsenide

MESFET

TTL

Bipolar

I2 L

Figure 1. Overview of the basic technologies.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

ECL

362

INTEGRATED CIRCUITS

(ECL) devices are used for high-speed parts that form the
critical path delay of the circuit. The MOS family of processes
consists of PMOS, NMOS, CMOS, and BiCMOS. The term
PMOS refers to a MOS process that uses only p-channel transistors, and NMOS refers to a MOS process that uses only nchannel transistors. PMOS is not used much due to its electrical characteristics, which are not as good as the n-channel
field effect transistors (FET), primarily since the mobility of
the n-channel material is almost twice compared to the mobility of the p-channel material. Also, the NMOS devices are
smaller than the PMOS devices, and thus PMOS do not give
good packing density.
CMOS was introduced in the early 1960s; however, it was
only used in limited applications, such as watches and calculators. This was primarily due to the fact that CMOS had
slower speed, less packing density, and latchup problems although it had a high noise margin and lower power requirements. Thus, NMOS was preferred over CMOS, in general,
until the p-channel devices developed began to have similar
characteristics as the nMOS and both the p-channel and nchannel transistors started delivering close to equal amounts
of currents with similar transistor sizes. In the 1980s and the
1990s, the need for lower power consumption was the driving
factor, and thus CMOS emerged as the leading IC technology
(2). The BiCMOS technology combines both bipolar and
CMOS devices in a single process. While CMOS is preferred
for logic circuits, BiCMOS is preferred for input/output (I/O)
and driver circuits due to its low input impedance and high
current driving capability.
Since the 1980s, efforts have been directed toward designing digital ICs using GaAs devices. In many high-resolution
radar systems, space systems, high-speed communication circuits, and microwave circuits, the integrated circuits need to
operate at speeds beyond several gigahertz (GHz). In silicon
technology, it is possible to obtain speeds on the order of up
to 10 GHz using ECL circuits, which is almost pushing the
limits of the silicon technology. In GaAs technology, the basic
device is the metal semiconductor (Schottky gate) field effect
transistor, called the GaAs MESFET. Given similar condi-

tions, the electrons in n-type GaAs material travel twice

faster than in silicon. Thus, the GaAs circuits could function
at twice the speed than the silicon ECL circuits for the same
minimum feature size. The GaAs mateial has a larger bandgap and does not need gate oxide material, as in silicon, which
makes it immune to radiation effects. Also, the GaAs material
has very high resistivity at room temperatures and lower parasitic capacitances, yielding high-quality transistor devices.
However, the cost of fabricating large GaAs circuits is significantly high due to its low reliability and yield characteristics
(primarily due to the presence of more defects in the material
compared to silicon). The fabrication process is complex, expensive, and does not aid scaling. Also, the hole mobility is
the same as in silicon, which means GaAs is not preferable
for complementary circuits. Thus, the GaAs technology has
not been as successful as initially promised. Since CMOS has
been the most dominant technology for integrated circuits, we
examine the MOS transistor and its characteristics as a
switch in the next section.
THE MOS SWITCH
The MOSFET is the basic building block of contemporary
CMOS circuits, such as microprocessors and memories. A
MOSFET is an unipolar device; that is, current is transported
by means of only one type of polarity (electrons in an n type
and holes in a p type). In this section, we describe the basic
structure of MOSFETS and their operation and provide examples of gates built using MOS devices.
Structure
The basic structure of a MOSFET (n and p type) is shown in
Fig. 2. We describe the structure of an n-type MOSFET (3,4).
It consists of four terminals with a p-type substrate into
which two n regions are implanted. The substrate is a silicon
wafer that provides stability and support. The region between
the two n regions is covered by an insulator, typically polysilicon and a metal contact. This contact forms the gate of the

Gate oxide
Poly gate
Field oxide

n+

n+

Field oxide

Channel

P-type substrate
NMOS structure

NMOS symbol

Gate oxide
Poly gate
Field oxide

p+

p+
Channel

Field oxide
S

N-type substrate
Figure 2. Structure of n- and p-type
MOSFET.

PMOS structure

PMOS symbol

INTEGRATED CIRCUITS

transistor. The insulating layer is required to prevent the flow

of current between the semiconductor and the gate. The two
n regions form the source and the drain. Due to the symmetry of the structure, the source and the drain are equivalent.
The gate input controls the operation of the MOSFET. A bias
voltage on the gate causes the formation of a channel between
the n regions. This channel causes a connection between the
source and drain and is responsible for the flow of the current.
The MOSFET is surrounded by a thick oxide, called the field
oxide, which isolates it from neighboring devices. Reversal of
n and p types in the discussion will result in a p-type MOSFET. Typical circuit symbols for n-type and p-type MOSFETS
are also shown in Fig. 2.

363

Vgs1
Ids

Linear
region

Saturation
region
Vgs2
Vgs3
Vgs4
Vds

Figure 3. Output characteristics of a MOS transistor.

Operation
When no gate bias is applied, the drain and the source behave
as two pn junctions connected in series in the opposite direction. The only current that flows is the reverse leakage current from the source to the drain. When a positive voltage is
applied to the gate, the electrons are attracted and the holes
are repelled. This causes the formation of an inversion layer
or a channel region. The source and the drain are connected
by a conducting n channel through which the current can
flow. This voltage-induced channel is formed only when the
applied voltage is greater than the threshold voltage, Vt. MOS
devices that do not conduct when no gate bias is applied are
called enhancement mode or normally OFF transistors. In
nMOS enhancement mode devices, a gate voltage greater
than Vt should be applied for channel formation. In pMOS
enhancement mode devices, a negative gate voltage whose
magnitude is greater than Vt must be applied. MOS devices
that conduct at zero gate bias are called normally ON or
depletion mode devices. A gate voltage of appropriate polarity
depletes the channel of majority carriers and hence turns it
OFF.
Considering an enhancement mode n-channel transistor,
when the bias voltage is above the predefined threshold voltage, the gate acts as a closed switch between the source and
drain, the terminals of which become electrically connected.
When the gate voltage is cut off, the channel becomes absent,
the transistor stops conducting, and the source and the drain
channels get electrically disconnected. Similarly, the p-channel transistor conducts when the gate voltage is beneath the
threshold voltage and stops conducting when the bias voltage
is increased above the threshold. The behavior of the MOS
transistor as a switch forms the fundamental basis for implementing digital Boolean circuits using MOS devices.

the conducting channel. The channel acts like a resistance,

and the drain current is proportional to the drain voltage.
This is the linear region of operation. As the value of Vds is
increased, the channel charge near the drain decreases. The
channel is pinched off when Vds Vgs Vt. An increase in
Vds beyond the pinchoff value causes little change in the drain
current. This is the saturation region of operation of the MOS
device. The output characteristics of n- and p-type devices is
shown in Fig. 3. The equations that describe the regions of
operation can be summarized as follows:

0 If Vgs Vt (cutoff)
2
]
Ids = k/2[2(Vgs Vt )Vds Vds
If Vg > Vt , Vds (Vgs Vt ) (linear)
k/2(Vgs Vt )2 If Vg > Vt , Vds > (Vgs Vt ) (saturation)
where k is the transconductance parameter of the transistor.
A detailed analysis of the structure and operation of MOS
devices is described in Refs. 3, 5, 7, and 8.
CMOS Inverter
The basic structure of an inverter is shown in Fig. 4, and the
process cross section is shown in Fig. 5. The gates of both the
NMOS and the PMOS transistors are connected. The PMOs
transistor is connected to the supply voltage Vdd, and the
NMOS transistor is connected to Gnd. When a logical 0 is applied at the input Vin, then the PMOS device is on and the
output is pulled to Vdd. Hence the output is a logical 1. On the
other hand, when a logical 1 is applied at the input, then the
NMOS transistor is on and the output is pulled to the ground.
Hence we have a logical 0. The operating regions of the tran-

Output Characteristics
Vdd

We describe the basis output characteristics (5,6) of a MOS

device in this subsection. There are three regions of operation
for a MOS device:
1. Cutoff region
2. Linear region
3. Saturation region
In the cutoff region, no current flows and the device is said to
be off. When a bias, Vgs, is applied to the gate such that Vg
Vt, the channel is formed. If a small drain voltage, Vds, is applied, drain current, Ids, flows from source to drain through

In

Out

GND
Figure 4. Circuit schematic of an inverter.

364

INTEGRATED CIRCUITS

;;;
;;
;;
;;;;;;;;
; ;;;;
;;
;
;;
VDD

Input

Ground

n well

; ;
;

Output

p substrate

Figure 5. Process cross section of an nwell inverter.

Polysilicon

Field oxide

p diffusion

Metal (A1)

Gate oxide

n diffusion

sistor are shown in Fig. 6. In region I, the n device is off and

the p device operates in the linear region. Hence the output
is pulled to Vdd. In region II, the n and p devices operate in
the linear and saturation region depending on the input voltage. In region III, the p device is cut off and the n device is
operating in the linear region. The output is pulled to the
ground. In region II, when both the transistors are on simultaneously, a short is produced between Vdd and Gnd. This accounts for the short circuit power dissipation in CMOS logic.
Transmission Gate
Consider the device shown in Fig. 7, which represents an
NMOS or a PMOS device. By suitably controlling the gate
bias, the device can be made to turn on or off. It behaves
as an electrical switch that either connects or disconnects
the points s and d. An NMOS device is a good switch when
it passes a logical 0, and a PMOS is a good switch when it
passes a logical 1. In CMOS logic, both the NMOS and PMOS
devices operate together. In general, the NMOS transistor
pulls down the output node to logical 0, and the PMOS device
pulls up a node to logical 1. A transmission gate is obtained
by connecting the two in parallel, as shown in Fig. 8. The

Vdd

control signal (say, g) applied to the n-type device is complemented and applied to the p-type device. When g is high, both
the transistors are on and hence a good 1 or a 0 is passed.
When g is low, both the devices are off. This is also called a
complementary switch, or a C SWITCH (5).
NAND and NOR Gates

CMOS combinational gates are constructed by connecting the

PMOS and NMOS devices in either series or parallel to generate different logical functions. The structures for a two-input
NAND and NOR gate are shown in Fig. 9.
NAND Gate. The p devices are connected in parallel, and
the n devices are connected in series. When either of the inputs A or B is a logical 0, the output is pulled high to Vdd.
When both A and B are high, then the output is pulled to the
ground. Hence this structure implements the operation f
(A B).
NOR Gate. Similarly, in the NOR gate, the p devices are
connected in series and the n devices are connected in parallel. When either of the inputs A or B is a logical 1, then the
output is pulled to the ground. When both A and B are low,
then the output is pulled to Vdd. Hence this structure implements the operation f (A B). The p structure is the logical dual of the n structure. An n input NAND and NOR gate
can be constructed in a similar fashion.

Electrical equivalent
s

II

III

MOS
device

0
Vin
Figure 6. Operating regions of the transistor.

Appropriate gate bias

Figure 7. A MOS device as a switch.

INTEGRATED CIRCUITS

365

System-level specification and requirements

Functional design and description

Architectural design

Logic design

Circuit design
Physical design

Verification

Figure 8. Transmission gate.

Fabrication
Testing

IC DESIGN METHODOLOGY

Figure 10. IC design methodology.

To design and realize VLSI circuits, several factors play key

roles. The goal of an IC designer is to design a circuit that
meets the given specifications and requirements while spending minimum design and development time avoiding design
errors. The designed circuit should function correctly and
meet the performance requirements, such as delay, timing,
power, and size. A robust design methodology has been established over the years, and the design of complex integrated
circuits has been made possible essentially due to advances
in VLSI design automation. The various stages in the design
flow are shown in Fig. 10. The design cycle ranges from the
system-level specification and requirements to the end product of a fabricated, packaged, and tested integrated circuit.
The basic design methodology is briefly described here, and
the various stages are discussed in detail in the followiing
sections using simple examples.
The first step is to determine the system-level specifications, such as the overall functionality, size, power, performance, cost, application environment, IC fabrication process,
technology, and chip-level and board-level interfaces required.
There are several tradeoffs to be considered. The next step is

Vdd

Vdd

A
Out
Out

A
A

Gnd

Gnd

Two input NAND gate

Two input NOR gate

Figure 9. Two-input NAND and NOR gate.

the functional design and description, in which the system is

partitioned into functional modules and the functionality of
the different modules and their interfaces to each other are
considered. The issues to be considered are regularity and
modularity of structures, subsystem design, data flow organization, hierarchical design approach, cell types, geometric
placements, and communication between the different blocks.
Once the functionality of the various modules is determined, the architectural design of the modules is pursued.
Many design alternatives are considered toward optimization.
This stage also includes the design of any hardware algorithms to be mapped onto architectures. A behavioral-level
description of the architecture is obtained and verified using
extensive simulations, often with an iterative process. This
stage is critical in obtaining an efficient circuit in the end and
for simplifying the steps in some of the following stages. In
the logic design stage, the architectural blocks are converted
into corresponding gate-level logic designs, Boolean minimization is performed, and logic simulation is used to verify the
design at this level. In some design flows, the circuit could be
synthesized from the logic level by using gate-level libraries
(this is referred to as logic synthesis). The logic design usually
includes a conventioinal logic design approach and a nontraditional design, such as precharge logic. At this stage, gate
delays are considered and timing diagrams are derived to verify the synchronization of the various logic modules. The next
step is the circuit design stage, which essentially involves
converting the logic design modules into a circuit representation. At this stage, the essential factors considered are clocking, switching speeds or delays, switching activity and power
requirements, and other electrical characteristics (e.g., resistance, capacitance).
The most complex step in VLSI design automation is the
physical design, which includes floorplanning, partitioning,
placement, routing, layout, and compaction. This process converts the given circuit design or description into a physical
layout that is a geometric representation of the entire circuit.
Each step of the physical design by itself is complex and takes
significant amounts of iterations and time. The various types
of transistors, the interconnecting wires, and contacts between different wires and transistors are represented as different geometric patterns consisting of many layers placed ac-

366

INTEGRATED CIRCUITS

cording to several design rules that govern a given fabrication

technology and process. The floorplanning step involves
higher-level planning of the various components on the layout. The partitioning step converts the overall circuit into
smaller blocks to help the other steps. It is usually impractical to synthesize the entire circuit in one step. Thus, logic
partitioning is used to divide the given circuit into a smaler
number of blocks, which can be individually synthesized and
compacted. This step considers the size of the blocks, the
number of blocks, and the interconnections between the
blocks and yields a netlist for each block that can be used in
the further design steps.
During the next step, which is the placement of the blocks
on the chip layout, the various blocks are placed such that
the routing can be completed effectively and the blocks use
minimum overall area, avoiding any white spaces. The placement task is iterative in that an initial placement is obtained
first and evaluated for area minimization and effective routing possibility, and alternate arrangements are investigated
until a good placement is obtained. The routing task completes the routing of the various interconnections, as specified
by the netlists of the different blocks. The goal is to minimize
the routing wire lengths and minimize the overall area
needed for routing. The routing areas between the various
blocks are referred to as channels or switchboxes. Initially, a
global routing is performed in which a channel assignment is
determined based on the routing requirements, and then a
detailed routing step completes the actual point-to-point
routing.
The last step in the physical design is the compaction step,
which tries to compact the layout in all directions to minimize
the layout area. A compact layout leads to less wire lengths,
lower capacitances, and more chip density since the chip area
is used effectively. The compaction step is usually an interactive and iterative process in which the user can specify certain parameters and check if the compaction can be achieved.
The goal of compaction, in general, is to achieve minimum
layout area. The entire physical design process is iterative
and is performed several times until an efficient layout for
the given circuit is obtained.
Once the layout is obtained, design verification needs to be
done to ensure that the layout produced functions correctly
and meets the specifications and requirements. In this stage,
design rule checking is performed on the layout to make sure
that the geometric placement and routing rules and the rules
regarding the separation of the various layers, the dimensions
of the transistors, and the width of the wires are followed
correctly. Any design rule violations that occurred during the
physical design steps are detected and removed. Then circuit
extraction is performed to complete the functional verification
of the layout. This step verifies the correctness of the layout
produced by the physical design process. After layout verification, the circuit layout is ready to be submitted for fabrication, packaging, and testing. Usually, several dies are produced on a single wafer and the wafer is tested for faulty dies.
The correct ones are diced out and packaged in the form of a
pin grid array (PGA), dual in-line package (DIP), or any other
packaging technology. The packaged chip is tested extensively
for functionality, electrical and thermal characteristics, and
performance. The process of designing and building an integrated circuit (9) that meets the performance requirements

and functions perfectly depends on the efficiency of the design

automation tools.
CIRCUIT DESIGN
To create performance optimized designs, two areas have to
be addressed to achieve a prescribed behavior: (1) circuit or
structural design, and (2) layout or physical design. While the
layout design is discussed in a later section, this section focuses on the former.
A logic circuit must function correctly and meet the timing
requirements. There are several factors that can result in the
incorrect functioning of a CMOS logic gate: (1) incorrect or
insufficient power supplies, (2) noise on gate inputs, (3) faulty
transistors, (4) faulty connections to transistors, (5) incorrect
ratios in ratioed logic, and (6) charge sharing or incorrect
clocking in dynamic gates. In any design, there are a certain
paths, called critical paths, that require attention to timing
details since they determine the overall functional frequency.
The critical paths are recognized and analyzed using timing
analyzer tools and can be dealt with at four levels:
1.
2.
3.
4.

Architecture
RTL/logic level
Circuit level
Layout level

Designing an efficient overall functional architecture helps

to achieve good performance. To design an efficient architecture, it is important to understand the characteristics of the
algorithm being implemented as the architecture. At the register transfer logic (RTL)/logic level, pipelining, the type of
gates, and the fan-in and the fan-out of the gates are to be
considered. Fan-in is the number of inputs to a logic gate, and
fan-out is the number of gate inputs that the output of a logic
gate drives. Logic synthesis tools can be used to achieve the
transformation of the RTL level. From the logic level, the circuit level can be designed to optimize a critical speed path.
This is achieved by using different styles of CMOS logic, as
explained later in this section. Finally, the speed of a set of
logic can be affected by rearranging the physical layout. The
following techniques can be used for specific design constraints.
The various CMOS logic structures that can be used to implement circuit designs are as follows:
1. CMOS Complementary Logic. The CMOS complementary logic gates are designed as ratioless circuits. In
these circuits, the output voltage is not a fraction of the
Vdd (supply) and the gates are sized to meet the required
electrical characteristics of the circuits. The gate consists of two blocks, and n block and a p block, that determine the function of the gate. The p block is a dual of
the n block. Thus, an n-input gate will consist of 2n
transistors.
2. Pseudo-NMOS Logic. In this logic, the load device is a
single p transistor with the gate connected to Vdd (5,10).
This is equivalent to replacing the depletion NMOS load
in a conventional NMOS gate by a p device. The design
of this style of gate (11,12) involves ratioed transistor
sizes to ensure proper operation and is shown in Fig.

INTEGRATED CIRCUITS

367

Weak p device

Outputs

a
c

n-logic
block

Inputs

b
d

Clock
z = ab + cd
Figure 11. Pseudo-NMOS logic.

11. The static power dissipation that occurs whenever

the pull-down chain is turned on is a major drawback
of this logic style.
3. Dynamic CMOS Logic. In the dynamic CMOS logic
style, an n-transistor logic structures output node is
precharged to Vdd by a p transistor and conditionally
discharged by an n transistor connected to Vss (5). The
input capacitance of the gate is the same as the pseudoNMOS gate. Here, the pull-up time is improved by virtue of the active switch, but the pull-down time is increased due to the ground. The disadvantage of this
logic structure is that the inputs can only change during
the precharge phase and must be stable during the
evaluate portion of the cycle Figure 12 depicts this logic
style.
4. Clocked CMOS Logic. To build CMOS logic gates with
low power dissipation (13), this logic structure was proposed. The reduced dynamic power dissipation is realized due to the metal gate CMOS layout considerations.
The gates have larger rise and fall times because of the
series clocking transistors, but the capacitance is similar to the CMOS complementary gates. This is a recommended strategy for hot electron effects, because it
places an additional n transistor in series with the logic
transistors (14).

Figure 13. CMOS-domino logic.

5. CMOS Domino Logic. This is a modification of the

clocked CMOS logic, in which a single clock is used to
precharge and evaluate a cascaded set of dynamic logic
blocks. This involves incorporating a static CMOS inverter into each logic gate (15), as shown in Fig. 13.
During precharge, the output node is charged high and
hence the output of the buffer is low. The transistors in
the subsequent logic blocks will be turned off since they
are fed by the buffer. When the gate is evaluated, the
output will conditionally go low (10), causing the
buffer to conditionally go high (01). Hence, in a cascaded set of logic blocks, each state evaluates and
causes the next stage to evaluate, provided the entire
sequence can be evaluated in one clock cycle. Therefore,
a single clock is used to precharge and evaluate all logic
gates in a block. The disadvantages of this logic are that
(1) every gate needs to be buffered, and (2) only noninverting structures can be used.
6. NP Domino Logic (Zipper CMOS). This is a further refinement of the domino CMOS (1618). Here, the domino buffer is removed, and the cascading of logic blocks
is achieved by alternately composed p and n blocks, as
is shown in Fig. 14. When the clock is low, all the nblock stages are precharged high while all the p-block
stages are precharged low. Some of the advantages of

Clk

Clk

Clk

Inputs

n-logic
block

to p
blocks
Inputs

n-logic
block

p-logic
block

n-logic
block

Clock

Figure 12. Dynamic CMOS logic.

Other p
blocks

Other n
blocks

Figure 14. NP-domino logic.

368

INTEGRATED CIRCUITS

abstraction. A circuit can be simulated at the logic level, the

switch level, or with reference to the timing. Simulation is a
critical procedure before committing the design to silicon. The
simulators themselves are available in a wide variety of
types (22).
Output

Clock

Output

nMOS
combinational
network

Differential
inputs

Clock

Figure 15. Cascade voltage switch logic.

the dynamic logic styles include (1) smaller area than

fully static gates, (2) smaller parasitic capacitances, and
(3) glitch-free operation if designed carefully.
7. Cascade Voltage Switch Logic (CVSL). The CVSL is a
differential style of logic requiring both true and complement signals to be routed to gates (19). Two complementary NMOS structures are constructed and then
connected to a pair of cross-coupled p pull-up transistors. The gates here function similarly to the domino
logic, but the advantage of this style is the ability to
generate any logic expression involving both inverting
and noninverting structures. Figure 15 gives a sketch
of the CVSL logic style.
8. Pass Transistor Logic. Pass transistor logic is popular
in NMOS-rich circuits. Formal methods for deriving
pass transistor logic for NMOS are presented in Ref. 20.
Here, a set of control signals and a set of pass signals
are applied to the gates and sources of the n transistor,
correspondingly. From these signals, the truth table for
any logic equation can be realized.
9. Source follower pull-up logic (SFPL): This is similar to
the pseudo-NMOS gate except that the pull-up is controlled by the inputs (21). In turn, this leads to the use
of smaller pull-down circuits. The SFPL gate style reduces the self-loading of the output and improves the
speed of the gate. Therefore, it shows a marked advantage in high fan-in gates.
Using the various design styles, any circuit design can be
built in a hierarchical fashion. The basic gates are first built,
from which functional blocks like a multiplexer or an adder
circuit can be realized. From these basic blocks, more complex
circuits can be constructed. Once a design for a specific application has been designed, the functionality of the circuit
needs to be verified. Also, other constraints, like the timing
and electrical characteristics, have to be studied before the
design can be manufactured. The techniques and tools to
achieve this are the subject of the next section.
SIMULATION
Simulation is required to verify if a design works the way
it should. Simulation can be performed at various levels of

Logic-Level Simulation
Logic-level simulation occurs at the highest level of abstraction. It uses primitive models of NOT, OR, AND, NOR, and
NAMD gates. Virtually all digital logic simulators are event
driven (i.e., a component is evaluated based on when an event
occurs on its inputs). Logic simulators are categorized according to the way the delays are modeled in the circuit: (1)
unit delay simulators, in which each component is assumed
to have a delay of one time unit, and (2) variable-delay simulators, which allow components to have arbitrary delays.
While the former helps in simulating the functionality of the
circuit the latter allows for more accurate modeling of the
fast-changing nodes.
The timing is normally specified in terms of an inertial delay and a load-dependent delay, as follows:
Tgate = Tintrinsic + Cload Tload
where
Tgate delay of the gate
Tintrinsic intrinsic gate delay
Cload actual load in some units (pF)
Tload delay per load in some units (ns/pF)
Earlier, logic simulators used preprogrammed models for the
gates, which forced the user to describe the system in terms
of these models. In modern simulators, programming primitives are provided that allow the user to write models for the
components. The two most popular digital simulation systems
in use today are VHDL and Verilog.
Circuit-Level Simulation
The most detailed and accurate simulation technique is referred to as circuit analysis. Circuit analysis simulators operate at the circuit level. Simulation programs typically solve a
complex set of matrix equations that relate the circuit voltages, currents, and resistances. They provide accurate results
but require long simulation times. If N is the number of nonlinear devices in the circuit, then the simulation time is typically proportional to Nm, where m is between 1 and 2. Simulation programs are useful in verifying small circuits in detail
but are unrealistic for verifying complex VLSI designs. They
are based on transistor models and hence should not be assumed to predict accurately the performance of designs. The
basic sources of error include (1) inaccuracies in the MOS
model parameters, (2) an inappropriate MOS model, and (3)
inaccuracies in parasitic capacitances and resistances. The
circuit analysis programs widely used are the SPICE program, developed at the University of California at Berekely
(23), and the ASTAP program from IBM (24). HSPICE (25) is
the commercial variant of these programs. The SPICE program provides various levels of modeling. The simple models
are optimized for speed, while the complex ones are used to
get accurate solutions. As the feature size of the processes is
reduced, the models used for the transistors are no longer

INTEGRATED CIRCUITS

valid and hence the simulators cannot predict the performance accurately unless new models are used.
Switch-Level Simulation
Switch-level simulation is simulation performed at the lowest
level of abstraction. These simulators model transistors as
switches to merge the logic-level and circuit-level simulation
techniques. Although logic-level simulators also model transistors as switches, the unidirectional logic gate model cannot
model charge sharing, which is a result of the bidirectionality
of the MOS transistor. Hence, we assume that all wires have
capacitance, since we need to locate charge-sharing bugs.
RSIM (26) is an example of a switch-level simulator with timing. In RSIM, CMOS gates are modeled as either pull-up or
pull-down structures, for which the program calculates a resistance to power or ground. The output capacitance of the
gate is used with the resistance to predict the rise and the
fall times of a gate.
Timing Simulators
Timing simulators allow simple nonmatrix calculations to be
employed to solve for circuit behavior. This involves making
approximations about the circuit, and hence accuracy is less
than that of simulators like SPICE. The advantage is the execution time, which is over two orders of magnitude less than
for SPICE. Timing simulator implementations typically use
MOS-model equations or table look-up methods. Examples of
these simulators are in Ref. 27.
Mixed-Mode Simulators
Mixed-mode simulators are available commercially today and
merge the aforementioned different simulation techniques.
Each circuit block can be simulated in the appropriate mode.
The results of the simulation analysis are fed back to the
design stage, where the design is tuned to incorporate the
deviations. Once the circuit is perfected and the simulation
results are satisfactory, the design can be fabricated. To do
this, we need to generate a geometric layout of the transistors
and the electrical connections between them. This has been a
subject of intense research over the last decade and continues
to be so. The following section introduces this problem and
presents some of the well-known techniques for solving it.
LAYOUT
The layout design is considered a prescription for preparing
the photomasks used in the fabrication of ICs (5). There is a
set of rules, called the design rules, used for the layout; these
serve as the link between the circuit and the process engineer. The physical design engineer, in addition to knowledge
of the components and the rules of the layout, needs strategies to fit the layouts together with other circuits and provide
good electrical properties. The main objective is to obtain circuits with optimum yield in as small an area as possible without sacrificing reliability.
The starting point for the layout is a circuit schematic. Figure 2 depicts the schematic symbols for an n-type and p-type
transistor. The circuit schematic is treated as a specification
for which we must implement the transistors and connections
between them in the layout. The circuit schematic of an inverter is shown in Fig. 4. We need to generate the exact lay-

369

out of the transistors of this schematic, which can then be

used to build the photomask for the fabrication of the inverter. Generating a complete layout in terms of rectangles
for a complex system can be overwhelming, although at some
point we need to generate it. Hence designers use an abstraction between the traditional transistor schematic and the full
layout to help organize the layout for complex systems. This
abstraction is called a stick diagram. Figure 16 shows the
stick diagram for the inverter schematic. As can be seen, the
stick diagram represents the rectangles in the layout as lines,
which represent wires and component symbols. Stick diagrams are not exact models of the layouts but let us evaluate
a candidate design with relatively little effort. Area and aspect ratio are difficult to estimate from stick diagrams.
Design Rules
Design rules for a layout (28) specify to the designer certain
geometric constraints on the layout artwork so that the patterns on the processed wafer will preserve the topology and
geometry of the designs. These help to prevent separate, isolated features from accidentally short circuiting, or thin features from opening, or contacts from slipping outside the area
to be contacted. They represent a tolerance that ensures very
high probability of correct fabrication and subsequent operation of the IC. The design rules address two issues primarily:
1. The geometrical reproduction of features that can be reproduced by the mask-making and lithographical process
2. The interaction among the different layers
Several approaches can be used to descibe the design rules.
These include the micron rules, stated at some micron resolution, and the lambda ()-based rules. The former are given as
a list of minimum feature sizes and spacings for all masks in
a process, which is the usual style for the industry. MeadConway (29) popularized the -based approach, where is
process dependent and is defined as the maximum distance
by which a geometrical feature on any one layer can stray
from another feature. The advantage of the -based approach
is that by defining properly the design itself can be made
independent of both the process and fabrication house, and
the design can be rescaled. The goal is to devise rules that
are simple, constant in time, applicable to many processes,
standardized among many institutions, and have a small
number of exceptions for specific processes. Figure 17 gives
the layout of the inverter, with the design rules specified.
To design and verify layouts, different computer-aided design (CAD) tools can be used. The most important of these
are the layout editors (30), design rule checkers, and circuit
extractors. The editor is an interactive graphic program that
allows us to create and delete layout elements. Most editors
work on hierarchical layouts, but some editors, like Berekelys

Vdd
In
Vss

Out

Metal 2
Metal 1
Poly
n diff
pdiff

Figure 16. Stick diagram of the inverter.

370

INTEGRATED CIRCUITS

Metal 1-pdiff via

p-type
transistor
Tub tie

;;;;;
;;;
;;;;;;
;;;
;
;
;;;

Metal 1

VDD

Poly

a
Metal 1-poly via
n-type
transistor

Tub tie

ntub

reach the optimal. The modules are usually considered as

rectangular boxes with specified dimensions. The algorithms
then use different approaches to fit these boxes in a minimal
area or to optimize them to certain other constraints. For instance, consider a certain number of modules with specific dimensions and a given area in which to fit them. This is similar to the bin-packing algorithm. After the placement step,
the different modules are placed in an optimal fashion and
the electrical connections between them need to be realized.

Metal 1

Metal 1-ndiff via

ptub
Metal 1

Vss

Figure 17. Transistor layout of the inverter.

Magic tool (31), work on a symbolic layout. The latter include

somewhat more detail than the stick diagram but are still
more abstract than the pure layout. The design rule checker,
or DRC, programs look for design rule violations in the layouts. Magic has an on-line design rule checking. The circuit
extractor is an extension of the DRC programs. While the
DRC must identify transistors and vias to ensure proper
checks, the circuit extractor performs a complete job of component and wire extraction. it produces a netlist, which lists the
transistors in the layouts and the electrical nets that connect
their terminals.
Physical Design
From the circuit design of a certain application and the design
rules of a specific process, the physical design problem is to
generate a geometric layout of the transistors of the circuit
design conforming to the specified design rules. From this layout, photomasks can be generated that will be used in the
fabrication process. To achieve this, the different modules of
the design need to be placed first and then electrical connections between them realized through the metal layers. For
instance, a two-layer metallization would allow the designer
to lay out metal both vertically and horizontally on the floorplan. Whenever the wire changes direction, a via can be used
to connect the two metal layers. Due to the complexity of this
problem, most authors treat module placement and the routing between modules as two separate problems, although they
are related critically. Also, in former days, when designs were
less complex, design was done by hand. Now we require sophisticated tools for this process.
Placement. Placement is the task of placing modules adjacent to each other to minimize area or cycle time. The literature consists of a number of different placement algorithms
that have been proposed (3235). Most algorithms partition
the problem into smaller parts and then combine them, or
start with a random placement solution and then refine it to

Routing. Once the modules have been placed, we need to

create space for the electrical connections between them. To
keep the area of the floorplan minimal, the first consideration
is to determine the shortest path between nodes, although a
cost-based approach may also be used. The cost is defined to
include an estimate of the congestion, number of available
wire tracks in a local area, individual or overall wire length,
and so on. Since the problem is a complex one, the strategy is
to split the problem into global or loose routing and local or
detailed routing. Global routing is a preliminary step, in
which each net is assigned to a particular routing area, and
the goal is to make 100% assignment of nets to routing regions while minimizing the total wire length. Detailed routing
then determines the exact route for each net within the global
route. There are a number of approaches to both of these
problems.
Global Routing. Global routing (36) is performed using a
wire-length criterion, because all timing critical nets must be
routed with minimum wire length. The routing area itself can
be divided into disjoint rectangular areas, which can be classified by their topology. A two-sided channel is a rectangular
routing area with no obstruction inside and with pins on two
parallel sides. A switch box is a rectangular routing area with
no obstructions and signals entering and leaving through all
four sides (37). The focus in this problem is only to create
space between the modules for all the nets and not to determine the exact route. The algorithms proceed by routing one
net at a time, choosing the shortest possible path. Since there
is a lot of dependency among the nets, different heuristics are
used to generate the least possible routing space in which to
route the nets. Once space is created for all the nets, the exact
route of each net can be determined.
Detailed Routing. Detailed routing is usually done by either
a maze-search or a line-search algorithm. The maze-running
algorithm (38,39) proposed by Lee-Moore finds the shortest
path between any two points. For this, the layout is divided
into a grid of nodes, in which each node is weighted by its
distance from the source of the wire to be routed. The route
that requires the smallest number of squares is then chosen.
If a solution exists, this algorithm will find it, but an excessive amount of memory is required to achieve this. In the linesearch algorithm, vertical and horizontal lines are drawn
from the source and the target, followed by horizontal or vertical lines that intersect the original lines. This is repeated
until the source and target meet. There are also a number of
other heuristic algorithms that exploit different characteristics of the design to generate optimal routing solutions. Genetic algorithms and simulated annealing approaches to this
problem have gained importance in recent years.
An introduction to the various algorithms that have been
proposed for layouts can be found in Ref. 40. Once the layout

INTEGRATED CIRCUITS

has been determined and the photomasks made, the circuit

can go to the fabrication plant for processing.

FABRICATION
The section describes the approach used in building integrated circuits on monolithic pieces of silicon. The process involves the fabrication of successive layers of insulating, conducting, and semiconducting materials, which have to be
patterned to perform specific functions. The fabrication therefore must be executed in a specific sequence, which constitutes an IC process flow. The manufacturing process itself is
a complex interrelationship of chemistry, physics, material
science, thermodynamics, and statistics.
Semiconducting materials, as the name suggests, are neither good conductors nor good insulators. While there are
many semiconducting elements, silicon is primarily chosen for
manufacturing ICs because it exhibits few useful properties.
Silicon devices can be built with a maximum operating temperature of about 150C due to the smaller leakage currents
as a result of the large bandgap of silicon (1.1 eV). IC planar
processing requires the capability to fabricate a passivation
layer on the semiconductor surface. The oxide of silicon,
SiO2, which could act as such a layer, is easy to form and is
chemically stable. The controlled addition of specific impurities makes it possible to alter the characteristics of silicon.
For these reasons, silicon is almost exclusively used for fabricating microelectronic components.
Silicon Material Technology
Beach sand is first refined to obtain semiconductor-grade silicon. This is then reduced to obtain electronic-grade polysilicon
in the form of long, slender rods. Single-crystal silicon is
grown from this by the Czochralski (CZ) or float-zone (FZ)
methods. In CZ growth, single crystal ingots are pulled from
molten silicon contained in a crucible. For VLSI applications,
CZ silicon is preferred because it can better withstand thermal stresses (41) and offers an internal gettering mechanism
than can remove unwanted impurities from the device structures on wafer surfaces (42). FZ crystals are grown without
any contact to a container or crucible and hence can attain
higher purity and resistivity than CZ silicon. Most high-voltage, high-power devices are fabricated on FZ silicon. The single crystal ingot is then subjected to a complex sequence of
shaping and polishing, known as wafering, to produce starting material suitable for fabricating semiconductor devices.
This involves the following steps:
1. The single crystal ingot undergoes routine evaluation of
resistivity, impurity content, crystal perfection size, and
weight.
2. Since ingots are not perfectly round, they are shaped to
the desired form and dimension.
3. The ingots are then sawed to produce silicon slices. The
operation defines the surface orientation, thickness, taper, and bow of the slice.
4. To bring all the slices to within the specified thickness
tolerance, lapping and grinding steps are employed.

371

5. The edges of the slices are then rounded to reduce substantially the incidence of chipping during normal wafer handling.
6. A chemical-mechanical polishing (43) step is then used
to produce the highly reflective and scratch- and damage-free surface on one side of the wafer.
7. Most VLSI process technologies also require an epitaxial layer, which is grown by a chemical vapor deposition process.
The most obvious trend in silicon material technology is
the increasing size of the silicon wafers. The use of these
larger-diameter wafers presents major challengers to semiconductor manufacturers. Several procedures have been investigated to increase axial impurity uniformity. These include the use of double crucibles, continuous liquid feed (CLF)
systems (44), magnetic Czochralski growth (MCZ) (44,45),
and controlled evaporation from the melt.
Epitaxial Layer
The epitaxial growth process is a means of depositing a single
crystal film with the same crystal orientation as the underlying substrate. This can be achieved from the vapor phase, liquid phase, or solid phase. Vapor phase epitaxy has the widest
acceptance in silicon processing, since excellent control of the
impurity concentration and crystalline perfection can be
achieved. Epitaxial processes are used for the fabrication of
advanced CMOS VLSI circuits, because epitaxial processes
minimize latch-up effects. Also in the epitaxial layer, doping
concentration can be accurately controlled, and the layer can
be made oxygen and carbon free. Epitaxial deposition is a
chemical vapor deposition process (46). The four major chemical sources of silicon used commercially for this deposition are
(1) silicon tetrachloride (SiCl4), (2) trichlorosilane (SiHCl3), (3)
dichlorosilane (SiH2Cl2), and (4) silane (SiH4). Depending on
particular deposition conditions and film requirements, one of
these sources can be used.
Doping Silicon
The active circuit elements of the IC are formed within the
silicon substrate. To construct these elements, we need to create localized n-type and p-type regions by adding the appropriate dopant atoms. The process of introducing controlled
amounts of impurities into the lattice of the monocrystalline
silicon is known as doping. Dopants can be introduced selectively into the silicon using two techniques: diffusion and ion
implantation.
Diffusion. The process by which a species moves as a result
of the presence of a chemical gradient is referred to as diffusion. Diffusion is a time- and temperature-dependent process.
To achieve maximum control, most diffusions are performed
in two steps. The first step is predeposition (47), which takes
place at a furnace temperature and controls the amount of
impurity that is introduced. The second step, the drive-in step
(47), controls the desired depth of diffusion.
Predeposition. In predisposition, the impurity atoms are
made available at the surface of the wafer. The atoms of the
desired element in the form of a solution of controlled viscosity can be spun on the wafer, in the same manner as the photoresist. For these spin-on dopants, the viscosity and the spin

372

INTEGRATED CIRCUITS

rate are used to control the desired dopant film thickness.

The wafer is then subjected to a selected high temperature to
complete the predeposition diffusion. The impurity atoms can
also be made available by employing a low-temperature
chemical vapor deposition process in which the dopant is introduced as a gaseous compoundusually in the presence of
nitrogen as a diluent. The oxygen concentration must be carefully controlled in this operation to prevent oxidation of the
silicon surface of the wafer.
Drive-In. After predeposition the dopant wafer is subjected
to an elevated temperature. During this step, the atoms further diffuse into the silicon crystal lattice. The rate of diffusion is controlled by the temperature employed. The concentration of the dopant atoms is maximum at the wafer surface
and reduces as the silicon substrate is penetrated further. As
the atoms migrate during the diffusion, this concentration
changes. Hence a specific dopant profile can be achieved by
controlling the diffusion process. The dopant drive-in is usually performed in an oxidizing temperature to grow a protective layer of SiO2 over the newly diffused area.
Ion Implantation. Ion implantation is a process in which
energetic, charged atoms or molecules are directly introduced
into the substrate. Ion implantation (48,49) is superior to the
chemical doping methods discussed previously. The most important advantage of this process is its ability to control more
precisely the number of implanted dopant atoms into substrates. Using this method, the lateral diffusion is reduced
considerably compared to the chemical doping methods. Ion
implantation is a low-temperature process, and the parameters that control the ion implantation are amenable to automatic control. After this process the wafer is subjected to annealing to activate the dopant electrically. There are some
limitations to this process. Since the wafer is bombarded with
dopant atoms, the material structure of the target is damaged. The throughput is typically lower than diffusion doping
process. Additionally, the equipment used causes safety hazards to operating personnel.

micron features. The resolution is limited by a number of

factors, including (1) hardware, (2) optical properties of the
resist material, and (3) process characteristics (52).
Most IC processes require 5 to 10 patterns. Each one of
them needs to be aligned precisely with those already on the
wafer. Typically, the alignment distance between two patterns is less than 0.2 m across the entire area of the wafer.
The initial alignment is made with respect to the crystal lattice structure of the wafer, and subsequent patterns are
aligned with the existing ones. Earlier, mask alignment was
done using contact printing (53,54), in which the mask is held
just off the wafer and visually aligned. The mask is then
pressed into contact with the wafer and impinged with ultraviolet light. There is a variation of this technique called proximity printing, in which the mask is held slightly above the
wafer during exposure. Hard contact printing was preferred
because it reduced the diffraction of light, but it led to a number of yield and production problems. So the projection alignment and exposure system was developed, in which the mask
and wafer never touch and an optical system projects and
aligns the mask onto the wafer. Since there is no damage to
the mask or photoresist, the mask life is virtually unlimited.
VLSI devices use projection alignment as the standard production method.
Junction Isolation

Photolithography

When fabricating silicon ICs, it must be possible to isolate the

devices from one another. These devices can then be connected through specific electrical paths to obtain the desired
circuit configuration. From this perspective, the isolation
technology is one of the critical aspects of IC fabrication. For
different IC types, like NMOS, CMOS, and bipolar, a variety
of techniques have been developed for device isolation. The
most important technique developed was termed LOCOS, for
LOCal Oxidation of Silicon. This involves the formation of
semirecessed oxide in the nonactive or field areas of the substrate. With the advent of submicron-size device geometries,
alternative approaches for isolation were needed. Modified
LOCOS processes, trench isolation, and selective epitaxial
isolation were among the newer approaches adopted.

Photolithography is the most critical step in the fabrication

sequence. It determines the minimum feature size that can
be realized on silicon and is a photoengraving process that
accurately transfers the circuit patterns to the wafer. Lithography (50,51) involves the patterning of metals, dielectrics,
and semiconductors. The photoresist material is first spin
coated on the wafer substrate. It performs two important
functions: (1) precise pattern formation and (2) protection of
the substrate during etch. The most important property of the
photoresist is that its solubility in certain solvents is greatly
affected by exposure to ultraviolet radiation. The resist layer
is then exposed to ultraviolet light. Patterns can be transferred to the wafer using either positive or negative masking
techniques. The required pattern is formed when the wafer
undergoes the development step. After development, the undesired material is removed by wet or dry etching.
Resolution of the lithography process is important to this
process step. It specifies the ability to print minimum size
images consistently under conditions of reasonable manufacturing variation. Therefore, lithographic processes with submicron resolution must be available to build devices with sub-

LOCOS. To isolate MOS transistors, it is necessary to prevent the formation of channels in the field regions. This implies that a large value of VT is required in the field region, in
practice about 3 to 4 V above the supply voltage. Two ways to
increase the field voltage are to increase the field oxide thickness and raise the doping beneath the field oxide. Thicker
field oxide regions cause high enough threshold voltages but
unfortunately lead to step coverage problems, and hence thinner field oxide regions are preferred. Therefore, the doping
under the field oxide region is increased to realize higher
threshold voltages. Nevertheless, the field oxide is made 7 to
10 times thicker than the gate oxide. Following this, in the
channel-stop implant step, ion implantation is used to increase the doping under the field oxide. Until about 1970, the
thick field oxide was grown using the grow-oxide-and-etch approach, in which the oxide is grown over the entire wafer and
then etched over the active regions. Two disadvantages of this
approach prevented it from being used for VLSI applications:
(1) Field-oxide steps have sharp upper corners, which poses a
problem to the subsequent metallization steps; and (2) chan-

INTEGRATED CIRCUITS

nel-stop implant must be performed before the oxide is grown.

In another approach, the oxide is selectively grown over the
desired field regions. This process was introduced by Appels
and Kooi in 1970 (55) and is widely used in the industry. This
process is performed by preventing the oxidation of the active
regions by covering them with a thin layer of silicon nitride.
After etching the silicon nitride layer, the channel-stop dopant can be implanted selectively. The process, has a number
of limitations for submicron devices. The most important of
these is the formation of the birds beak, which is a lateral
extension of the field oxide into the active areas of the device.
The LOCOS birds beak creates other problems as junctions
become shallower in CMOS ICs. The LOCOS process was
therefore modified in several ways to overcome these limitations: (1) etched-back LOCOS, (2) polybuffered LOCOS, and
(3) sealed-interface local oxidation (SILO) (56).
Non-LOCOS Isolation Technologies. There have been nonLOCOS isolation technologies for VLSI and ultra-large-scale
integration (ULSI) applications. The most prominent of these
is trench isolation technology. Trench technologies are classified into three categories: (1) shallow trenches (1 m), (2)
moderate depth trenches (1 to 3 m), and (3) deep, narrow
trenches (3 m deep, 2 m wide). Shallow trenches are
used primarily for isolated devices of the same type and hence
are considered a replacement to LOCOS. The buried oxide
(BOX) (57) isolation technology uses shallow trenches refilled
with a silicon dioxide layer, which is etched back to yield a
planar surface. This technique eliminates the birds beak of
LOCOS. The basic BOX technique has certain drawbacks for
which the technique is modified.
Metallization
This subsection describes the contact technology to realize the
connections between devices, and how the different metal layers are connected to realize the circuit structure.
Contact Technology. Isolated active-device regions in the
single-crystal substrate are connected through high-conductivity, thin-film structures that are fabricated over the silicon
dioxide that covers the surface. An opening in the SiO2 must
be provided to allows contacts between the conductor film and
the Si substrate. The technology involved in etching these
contacts is referred to as contact technology. These contacts
affect the circuit behavior because of the parasitic resistances
that exist in the path between the metal to Si substrate and
the region where the actual transistor action begins. Conventional contact fabrication involves the fabrication of a contact
to silicon at locations where the silicon dioxide has been
etched to form a window. It involves the following steps:
1. In regions where contacts are to be made, the silicon
substrate is heavily doped.
2. A window or contact hole is etched in the oxide that
passivates the silicon surface.
3. The silicon surface is cleaned to remove the thin nativeoxide layer that is formed rapidly when the surface is
exposed to an oxygen-containing ambient.
4. The metal film is deposited on the wafer and makes contact with silicon wherever contact holes were created.
Aluminum is the most commonly used metal film.

373

5. After depositing the metal, the contact structure is subjected to a thermal cycle known as sintering or annealing. This helps in bringing the Si and metal into intimate contact.
Al is desired as an interconnect material because its resistivity, 2.7 -cm, is very low, and it offers excellent compatibility with SiO2. Al reacts with SiO2 to form Al2O3, through
which the Al can diffuse to reach the Si, forming an intimate
Al0Si contact. But using pure Al has certain disadvantages.
Since Al is polycrystalline in nature, its grain boundaries offer very fast diffusion paths for the Si at temperatures above
400C. Hence, if a large volume of Al is available, a significant
quantity of the Si can diffuse into Al. As a result, the Al from
the film moves rapidly to fill in the voids created by the migrating Si, which leads to large leakage currents or electrically shorting the circuit. This effect is referred to as junction
spiking (58). To prevent junction spiking, different techniques
are used:
1. Add approximately 1% of Si to Al.
2. Add a diffusion barrier to prevent Si from diffusing into
Al.
3. Decrease sintering temperature, but this increases contact resistance.
4. Add a barrier metal to the contact hole (59).
Of these techniques, the most commonly used is the barrier
metal. The idea is to block or hinder Al from intermixing with
Si. There are three main types of contact barrier metallurgies:
(1) sacrificial barrier, (2) passive barrier, and (3) stuffed
barrier.
The use of Al has its own problems, the most important
being its high resistivity and electromigration. There is also
the problem with hillock formation. Hillocks are formed due
to the thermal expansion mismatch among Al, SiO2, and Si.
As the wafer is cooled, thermal expansion mismatch forms
stresses (usually compressive), which forms these hillocks.
Therefore, copper metallization has been gaining importance.
Copper is preferred over Al because it has a low resistivity
(1.2 -cm) and is resistant to electromigration. In fact, copper is added in small quantities to Al to reduce the electromigration problem of Al. However, there are some real problems
with copper that need to be addressed before it can replace Al:
1. Cu is a terrible contaminant in Si. It has a very high
diffusivity in Si and causes junction leakage, which degrades the gate oxide integrity (GOI).
2. Cu diffuses and drifts easily through SiO2. Hence, Cu
needs to be encapsulated for use in metallization.
3. Cu oxidizes to CuO easily.
4. The etch chemistry for Cu is highly contaminated, and
the wafers need to be held at higher temperatures.
Typical process steps involved in the fabrication of a 0.8
m LOCOS n-well inverter are as follows:
1. Wafer: 1 1015 to 1 1016 CZ(p) with 100 crystal orientation. Epitaxial layer required because of latch-up.
The thickness is 2 m to 16 m with 5 1015.

374

INTEGRATED CIRCUITS

2. Grown screen oxide layer, with the thickness in the

range 400 to 1000.
3. Expose the n-well photo on the wafer.
4. n-well ion implant. Use 1 1013 /cm2 phosphorous. The
voltage used is 60 keV to 2 MeV.
5. n-well drive-in. This step is carried out at 1050 to
1100C for 2 to 6 h. This activates the dopant atoms.
The drive-in depth is around 1 m to 10 m.
6. Perform LOCOS process.
6.1. Strip wafer.
6.2. Pad oxide. Thickness is 100 to 400.
6.3. Pad nitride. Thickness is 1000 to 2000. LPCVD
silicon nitride is used.
6.4. Expose the diffusion photo on the wafer.
6.5. Etch the nitride layer.
6.6. Expose the block field (BF) photo. This is the inverse of the n-well photo and prevents the formation of the parasitic transistors between adjacent transistors.
6.7. Field ion implantation. 1 1013 /cm2 boron at 60
keV.
6.8. Strip the BF and the resist layer.
6.9. Grow the field oxide. The thickness is about
4000 to 6000 of SiO2. The process used is a pyro
process at 900 to 1050C for 3 to 6 h.
6.10. Strip the pad nitride layer by dipping the wafer
in H3PO4.
6.11. Strip the pad oxide layer by dipping the wafer in
50 : 1 HF.
7. Grow a sacrificial oxide layer and strip it. The thickness is about 600 to 1000. The sacrificial oxide layer
eats into the bare silicon, thus exposing fresh silicon
area on which the device can be grown.
8. Grow a sacrificial gate oxide layer. Here the thickness
is about 80 to 130. This layer protects the gate when
the VT implant is done.
9. VT implant. Two masks, one for the n region and one
for the p region, are used. The concentration is 1
1011 to 1 1012 /cm2 at 5 to 30 keV.
10. Strip the sacrificial gate oxide layer using a 50 : 1 HF
solution.
11. Grow the gate oxide layer. Typical thickness is 80 to
130. The gate oxide layer is grown at 800 to 900C for
20 min.
12. Polysilicon is deposited all over the wafer. LPCVD silane is used at 620C for a blanket deposition. The typical thickness is 2500 to 4000.
13. Polysilicon doping is done by ion implantation using
5 1015 phosphorous.
14. The polysilicon etch is a very critical photo/etch process.
14.1. Polysilicon photo is exposed on the wafer.
14.2. Reactive ion etch (RIE) is used to etch the polysilicon.
14.3. The resist is stripped.
15. Diffusion processing
15.1. Mask the p regions.

16.

17.
18.
19.
20.

21.
22.
23.
24.

15.2. Perform n source/drain ion implantation using

5 1015 /cm2 As75 at 40 keV. As is used because
it is slow and does not diffuse deep into the silicon substrate.
15.3. Perform n anneal at 900C for 15 min to activate the dopant.
15.4. Strip the resist.
15.5. Mask the n regions.
15.6. Perform p source/drain ion implantation using
1 1015 /cm2 BF2 /B11 at 5 to 20 keV.
15.7. Source/drain anneal at 900C for 30 min in an
oxidizing atmosphere. This is a rapid thermal
process.
15.8. Strip the resist off.
Interlevel dielectric. Boro-phospho silicon glass
(BPSG) is used because it flows well. Typical thickness
is 5000 to 8000. A 900C reflow anneal is also performed.
The contact photo is exposed on the wafer. This is critical to the layout density.
The contacts are etched using RIE.
After etching, the contact resist is stripped off.
Metallization. Ti barrier metallurgy is used. The actual contact is made with an alloy of Al/Cu/Si with
percentages 98%, 1%, and 1%, respectively. The Al
alloy is sputtered onto the wafer. The typical thickness
is about 1.2 m.
The Metal-1 layer photo is exposed.
Metal-1 etch.
Strip resist.
Foaming gas anneal is performed to improve the mobility of the electrons and relieve stress on the wafer.

The inverter is finally fabricated. Figure 5 describes the process cross section of this inverter after the various steps have
been performed.
TESTING
Testing is a critical factor in the design of circuits. The purpose of testing is to verify conformance to the product definition. To understand the complexity of this problem, consider
a combinational circuit with n inputs. A sequence of 2n inputs
must be applied and observed to test the circuit exhaustively.
Since the number of inputs are high for VLSI circuits, testing
the chip exhaustively is impossible. Hence, this becomes an
area of importance to circuit design. There are three main
areas that need to be addressed to solve this problem:
1. Test generation
2. Test verification
3. Design for testability
Test generation corresponds to the problem of generating a
minimum number of tests to verify the behavior of a circuit.
The problem of test verification, which is commonly gauged by
performing fault simulations, involves evaluating measures of
the effectiveness of a given set of test vectors. Circuits can
also be designed for testability.

INTEGRATED CIRCUITS

Test Generation
Test generation (60) involves the search for a sequence of input vectors that allow faults to be detected at the primary
device outputs. VLSI circuits are typically characterized by
buried flip-flops, asynchronous circuits, indeterminate states,
complex clock conditions, multiple switching of inputs simultaneously, and nonfunctional inputs. Due to these factors, an
intimate knowledge of the internal circuit details is essential
to develop efficient test strategies. The goal of a test generation strategy (61,62) is multifold: (1) chip design verification
in conjunction with the designer, (2) incorporation of the customers specification and patterns into the manufacturing test
program, and (3) fault detection by fault simulation methods.
Test Verification
Test verification (63) involves calculating measures for how
efficient the test vectors for a given circuit are. This is often
accomplished by using fault models (64). Fault simulation requires a good circuit simulator to be efficient and is hence
closely related to logic simulation and timing analysis. While
the logic simulator verifies the functionality of a design and
ensures that the timing constraints are met, the fault simulator tells the designer if enough analysis has been performed
to justify committing the design to silicon. In fault simulation,
the true value of a circuit and its behavior under possible
faults is simulated. The fault model is a hypothesis based on
an abstract model of the circuit, conformed to some precise
real physical defects. To begin with, the simulator generates
a fault list that identifies all the faults to be modeled. Then a
set of test vectors is simulated against the fault-free and
faulty models. Those faults that cause an erroneous signal at
an output pin are considered as detected faults. Now the fault
coverage of the test vector set can be computed as the number
of faults detected over the total number of faults modeled.
The most widely used fault model is the single stuck-at
fault model. This model assumes that all faults occur due to
the shorting of a signal node with the power rail. A number
of faults can be detected by this model, but a major disadvantage of this model is its assumption that all faults appear as
stuck-at faults. The limitations of this model have led to the
increased use of other models, like the stuck-open (65) and
bridging fault models (66). The former can occur in a CMOS
transistor or at the connection to a transistor. The bridging
faults are short circuits that occur between signal lines. These
represent a frequent source of failure in CMOS ICs. A majority of the random defects are manifested as timing delay
faults in static CMOS ICs. These are faults in which the increased propagation delay causes gates to exceed their rated
specifications. The statically designed circuits have a transient power supply that peaks when the gates are switching
and then settles to a low current value in the quiescent state.
The quiescent power supply current (67), known as IDDQ, can
be used as an effective test to detect leakage paths due to
defects in the processing. The measured IDDQ of a defect-free
CMOS IC is approximately 20 nA. Most physical defects will
elevate IDDQ by one to five orders of magnitude. Thus the IDDQ
testing approach can be used to detect shorts not detectable
by the single stuck-at fault model.
There are several other ways of applying logic and fault
simulation to testing:

375

1. Toggle Testing. This is the cheapest, simplest, and least

time-consuming method of applying simulation to testing. Toggle testing provides a testability measure by
tracking the activity of circuit nodes. From a set of vectors, the method identifies those parts of the network
that exhibit no activity. Since the test vectors do not
affect these nodes, faults occurring here cannot be detected by the fault simulator.
2. Fault Simulation of Functional Tests. The outputs of
the functional simulator can be used in the design process as an effective design analysis tool. The lists of detectable and undetectable faults generated by the simulator can be used to locate problems in the design and
correct them. This results in substantial savings in development and manufacturing.
3. Fault Simulation after New Test Vector Generation.
High-quality testing in a reasonable timeframe would
require an efficient test pattern generation system and
a fault simulator. Test vectors are first generated to detect specific faults, and the fault simulator determines
the quality of the vector set. In this scenario, it becomes
important to fault simulate after every new test vector
is generated in order to catch multiple faults. Accelerated fault simulation is faster than test pattern generation.
Design for Testability
Design for testability commonly refers to those design techniques that produce designs for which tests can be generated
by known methods. The advantage of these techniques are (1)
reduced test generation cost, (2) reduced testing cost, (3) highquality product, and (4) effective use of computer-aided design
tools. The key to designing circuits that are testable are two
concepts, controllability and observability. Controllability is
defined as the ability to set and reset every node that is internal to the circuit. Observability is defined as the ability to
observe either directly or indirectly the state of any node in
the circuit. There are programs like SCOAP (68) that, given
a circuit structure, can calculate the ability to control or observe internal circuit nodes. The concepts involved in design
for testability can be categorized as follows: (1) ad hoc testing,
(2) scan-based test techniques, and (3) built-in self-test
(BIST).
Ad Hoc Testing. Ad hoc testing comprises techniques that
reduce the combinational explosion of testing. Common techniques partition the circuit structure and add test points. A
long counter is an example of a circuit that can be partitioned
and tested with fewer test vectors. Another technique is the
use of a bus in a bus-oriented system for testing. The common
approaches can be classified as (1) partitioning techniques, (2)
adding test points, (3) using multiplexers, and (4) providing
for easy state reset.
Scan-Based Test Techniques. Scan-based approaches stem
from the basic tenets of controllability and observability. The
most popular approach is the level sensitive scan design, or
LSSD, approach, introduced by IBM (69). This technique is

376

INTEGRATED CIRCUITS

Inputs

Combinational
logic

Outputs

Shift register
latches

Clocks

Scan out

Figure 18. Level-sensitive scan design.

illustrated in Fig. 18. Circuits designed based on this approach operate in two modesnamely, normal mode and test
mode. In the normal mode of operation, the shift register
latches act as regular storage latches. In the test mode, these
latches are connected sequentially and data can be shifted in
or out of the circuit. Thus, a known sequence of data (controllability) can be input to the circuit and the results can be
shifted out of the circuit using the registers (observability).
The primary disadvantage of this approach is the increased
complexity of the circuit design and the increased external
pin count. The serial scan approach is similar to the LSSD,
but the design of the shift register latch is simplified to obtain
faster circuits. For most circuit designs, only the input and
output register need be made scannable. This technique
makes the designer responsible for deciding which registers
need to be scanned and is called the partial serial scan technique (70). The parallel scan (71) approach is an extension of
the serial scan in which the registers are arranged in a sort
of a grid, where on a particular column all the registers have
a common read/write signal. The registers that fall on a particular row have common data lines. Therefore, the output of
a register can be observed by enabling the corresponding column and providing the appropriate address. Data can also be
written into these registers in a similar fashion.
Built-In Self-Test. Signature analysis (72) or cyclic redundancy checking can be used to incorporate a built-in self-test
module in a circuit. This involves the use of a linear feedback
shift register, as depicted in Fig. 19. The value in the register
will be a function of the value and number of latch inputs and
the counting function of the signature analyzer. The good part
of the circuit will have a particular number or signature in
the register, while the faulty portion will have a different
number. The signature analysis approach can be merged with
the level-sensitive scan design approach to create a structure
called a built-in logic block observation, or BILBO (73). Yet
another approach to built-in test is called a design for autonomous test, in which the circuit is partitioned into smaller
structures that are tested exhaustively. The partitioning
method involves the use of multiplexers. The syndrome test-

ing method, in which all possible inputs are applied and the
number of 1s at the outputs is counted, is also a test method
that requires exhaustive testing. The resultant value is compared to that of a known good machine.
Other Tests
So far we have discussed techniques for testing logic structures and gates. But we need testing approaches at the chip
level and the system level also. Most approaches for testing
chips rely on the aforementioned techniques. Memories, for
instance, can use the built-in self-test techniques effectively.
Random logic is usually tested by full serial scan or parallel
scan methods. At the system level, traditionally the bed-ofnails testers have been used to probe points of interest. But
with the increasing complexity of designs, system designers
require a standard to test chips at the board level. This standard is the IEEE 1149 boundary scan (74) architecture. ICs
that are designed based on this standard enable complete
testing of the board. The following types of tests can be performed in a unified framework: (1) connectivity test between
components, (2) sampling and setting chip I/Os, and (3) distribution and collection of built-in self-test results.
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Reading List
A. Mukherjee, Introduction to nMOS and CMOS VLSI Systems Design,
Englewood Cliffs, NJ: Prentice-Hall, 1986.
L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI
Circuits, Reading, MA: Addison-Wesley, 1985.
M. Annaratone, Digital CMOS Circuit Design, Norwell, MA:
Kluwer, 1986.
M. Shoji, CMOS Digital Circuit Technology, Englewood Cliffs, NJ:
Prentice-Hall, 1988.
D. A. Pucknell and K. Eshraghian, Basic VLSI Design: Systems and
Circuits, Sydney: Prentice-Hall of Australia Lt., 1988.
W. Wolf, Modern VLSI Design: A System Approach, Englewood Cliffs,
NJ: Prentice-Hall, 1994.
J. Schroeter, Surviving the ASIC Experience, Englewood Cliffs, NJ:
Prentice-Hall, 1992.
J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Kluwer, 1996.
S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New
York: McGraw-Hill, 1996.
C. Y. Chang and S. M. Sze, ULSI Technology, New York: McGrawHill, 1996.
N. Sherwani, Algorithms for VLSI Physical Design Automation, Boston: Kluwer, 1993.
R. L. Gieger, P. E. Allen, and N. R. Strader, VLSI Design Techniques
for Analog and Digital Circuits, New York: McGraw-Hill, 1990.
L. J. Herbst, Integrated Circuit Engineering, London, Oxford University Press, 1996.
M. S. Smith, Application Specific Integrated Circuits, Reading, MA:
Addison-Wesley, 1997.

N. RANGANATHAN
RAJU D. VENKATARAMANA
University of South Florida

INTEGRATING CIRCUITS

INTEGRATING CIRCUITS

Since inductors tend to be bulky and expensive (except for

applications at frequencies higher than approximately 1
GHz), integrating circuits generally consist of a current signal
which is integrated onto a capacitor to form a voltage signal.
Cascading one integrating circuit to another requires that the
voltage signal be converted to a current signal. An integrating
circuit can be realized using an opamp, resistor, and capacitor. The input voltage is converted to an input current which
is directly proportional to the input voltage via Ohms Law.
This current is integrated onto the capacitor. The output voltage is produced at the output of the opamp.
The major applications of integrating circuits are in filters,
slow analog-to-digital converters, and image sensor circuits.
Integrating circuits are the basic building blocks used to synthesize frequency selective circuits, or filters. The complexity
of the filter function, in terms of the number of poles, determines the number of integrating circuits that must be included in the circuit. A high precision but low speed technique
for analog-to-digital conversion employs an integrating circuit, comparator, and a counter or timer. The integrating capacitor is charged for a specified amount of time by a current
which is proportional to the input signal. The capacitor is discharged by a fixed amount of current. The length of time required to fully discharge the capacitor determines the value
of the input signal. Another major application of integrating
circuits is in image sensing circuits. Incident light is converted to a photo-current which is integrated on a storage capacitor for a specified length of time. The final voltage on the
capacitor is directly proportional to the photocurrent.
Performance criteria for integrating circuits are cost and
dynamic range. In integrated circuits, cost is a nondecreasing
function of the silicon area occupied by the circuit and the
power consumed by the circuit. We measure dynamic range
as the ratio of the largest to the smallest signal level that the
circuit can handle. A tradeoff exists between these performance criteria; that is, the higher the dynamic range required, the higher the cost of the integrator.
INTEGRATING CIRCUITS
There are several means of realizing the mathematical function of integration using only resistors, transistors, amplifiers, and capacitors. The function we want to synthesize is of
the form:


vO (t) = A

vI (t) dt + B

(1)

The Inverting Integrator

The inverting integrator, also known as the Miller integrator,
is shown in Fig. 1(a). It is an inverting amplifier, where the
feedback element is the capacitor C. The input voltage, vI(t),
is converted to a current iI(t) vI(t)/R, since a virtual ground
exists at the negative input terminal of the opamp. This current is integrated on the capacitor, forming an output voltage
according to the relation,
vO (t) =

1
RC

t
0

433

vI (t) dt vC (0)

(2)

vI (t)

iI (t)

vo (t)

(a)
C

VG
vI (t)

vo (t)

+
(b)
vI (t)

io (t)

+
G

vo (t)

Vg

(c)
Figure 1. Integrating circuits: (a) the inverting integrator, (b) the
MOSFET-C integrator, and (c) the transconductance-C integrator.

where vC(0) is the initial voltage stored on the capacitor. Note

that even a small dc input voltage will eventually result in an
output voltage which is huge. A theoretically infinite output
voltage is prevented by the finite dc voltage supplies of the
opamp.
The integrator time constant of the Miller integrator is
RC, which has units of seconds.
The MOSFET-C Integrator
The MOSFET-C integrator is shown in Fig. 1(b). It is popular
in integrated circuit design, where the amplifier, capacitor,
and resistance are fabricated on the same substrate. An MOS
transistor operating in the triode region acts like a voltagecontrolled resistor, where the nominal conductance G 1/R
has units of 1/. Using the same analysis as for the Miller
integrator, we find that the integrating time constant is
C/G. The two main advantages of the MOSFET-C integrator
over the inverting integrator are: (1) an MOS transistor generally occupies less silicon area than an equivalent resistor,
and (2) the conductance is tunable via the gate voltage VG.
The latter property is particularly important in integrated
circuit design, where the tolerance on capacitors is approximately 10 to 50%.
The Transconductance-C Integrator
The transconductance-C integrator is shown in Fig. 1(c). It
consists of a transconductance amplifier which converts a differential input voltage to an output current via the relation
iO = G(v+ v )

(3)

In Fig. 1(c), we note that v vI(t), and v 0 V. Thus, the

output current is equal to the input voltage times the conductance. The current iO(t) is integrated on the capacitor, produc-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

434

INTEGRATING CIRCUITS

R
QR
C

C
r
R

Figure 2. The feedforward TowThomas

two-integrator-loop biquadratic circuit.

R1

vo (t)

+
R3

R2

C1

vI (t)

ing the output voltage, vO(t). The integrator time constant is

the same as that for the MOSFET-C integrator, namely,
C/G. The transconductance-C integrator is also used in integrated circuit design. Compared to the MOSFET-C integrator, the transconductance-C integrator has simpler circuits and is generally capable of operating at higher speeds.
On the other hand, the MOSFET-C integrator has a higher
maximum dynamic range at a given cost than the transconductance-C integrator.
Other Integrator Circuits
The switched-capacitor integrator employs a capacitor and at
least two MOS transistors operating as switches to emulate
the resistance R. A global clock signal, operating at a frequency much higher than the bandwidth of the input signal,
turns the switches on and off at a rate which is inversely proportional to the effective resistance seen by the input. The
switched-capacitor integrator is common in integrated circuit
design. Tuning the integrator time constant is straightforward since it depends on the clock frequency and the ratio of
capacitors. In integrated circuit design, the tolerance on the
ratio of capacitors can be lower than 1%. The cost of this design strategy is increased circuit complexity, power consumption, and noise due to the global clock signal.
If the input signal is a current, integration is easily
achieved using a single capacitor. During the reset phase of a
capacitor integrator, the capacitor voltage is set to a known
initial voltage, typically either 0 V or VDD. During the integration phase, the input current is integrated on the capacitor to
produce an output voltage which is proportional to the input
current. This output voltage is typically buffered and scaled
before it is sent off chip.

function is

VO (s)
=
VI (s)

s2

(4)

By a suitable choice of circuit components, Eq. (4) can be configured as a second-order low-pass, bandpass, high-pass,
notch, or allpass filter. Fourth and higher-order filter functions are constructed by cascading two or more biquads together.
Dual-slope Analog-to-digital Converter
The dual-slope analog-to-digital converter (ADC) is a highprecision but low speed ADC method. A block diagram is
given in Fig. 3(a). The dual-slope ADC consists of an inverting
integrator, a comparator, a high-speed counter, and control
logic. The charge on the capacitor is initially set to zero. During the integration phase, the input voltage vI(t) is converted
to an input current that is integrated on the capacitor C for a

C
vI (t)

VREF

vo (t) Comparator,
control logic,
and counter

(a)

VDD

MAJOR APPLICATIONS OF INTEGRATOR CIRCUITS

Three major applications of integrator circuits are in filters,
dual-slope analog-to-digital converters, and image sensor circuits.


1
r
1

+ 2
R1
RR3
C RR2
1
1
+
s2 + s
QCR C2 R2

1
C1
+s
C
C

VSET

vo
iI

The Biquadratic Filter

The two-integrator-loop biquadratic circuit, or biquad, is used
to synthesize an arbitrary second-order filter function in s,
where s j, and is the frequency in radians/s. The feedforward Tow-Thomas biquad is drawn in Fig. 2. It consists of two
inverting integrators and an inverting amplifier. Its transfer

(b)
Figure 3. Two applications of integrating circuits: (a) a dual-slope
analog-to-digital converter, and (b) a CMOS image sensor circuit.

INTEGRATING CIRCUITS

fixed length of time. During the discharge phase, current derived from a known reference voltage is used to discharge the
capacitor. The length of time, as measured in counts, required
to discharge the capacitor to 0 V is proportional to the input
voltage.
CMOS Image Sensor Circuits
CMOS image sensor circuits receive as input a photocurrent
which is proportional to the intensity of the incoming light.
The photocurrent is generated at a reverse-biased pn junction
in the silicon. A simplified diagram is shown in Fig. 3(b). A
description of its operation is as follows. The integrating capacitor is initially set to VDD. During the integrating time, the
photocurrent discharges the capacitor. The difference between VDD and the final voltage is proportional to the mean
value of the photocurrent.
PERFORMANCE CRITERIA

maximum dynamic power consumption is

2
PD = 4 f SVDD
C

Cost
In integrated circuit design, the cost of an integrator is a nondecreasing function of the area and power consumption. In
this analysis, we assume that the technology is fixed; that is,
the designer is unable to change all the parameters of the
devices, except their size.
Area. The silicon area of an integrator is generally dominated by the area of the capacitor. Define the capacitance per
unit area of a capacitor in a given fabrication technology as
COX, with units of F/m2. Then, the total area of the integrator
can be written as
A=

C
COX

(5)

where is an area factor that takes into account the portion

of silicon area used by the amplifier and conductor. This area
factor is always greater than unity.
Power. Static power consumption is the power supply voltage times the quiescent, or bias, current of the amplifier. Let
us denote the total amplifier bias current as IB, the positive
supply voltage as VDD, and the negative supply voltage as
VDD. Then the static power consumption is
PS = 2VDD IB

(6)

Dynamic power consumption results primarily from the

charging and discharging of the integrating capacitance. In
most designs, dynamic power consumption is much larger
than static power consumption. The maximum dynamic
power consumption occurs when the capacitor is fully charged
and discharged with each cycle of the input signal. Let the
input signal have amplitude VDD and frequency f S. Then, the

(7)

The factor 4 takes into account positive charging to VDD and

negative charging to VDD. Total power consumption is the
sum, PS PD.
Dynamic Range
Dynamic range (DR) is defined as the maximum input level
the circuit can handle divided by the noise level. By level, we
mean the mean-square value of the input or output voltage.
Dynamic range is generally expressed in dB.
Noise. Sources of noise in the integrator are found in the
conductance and the amplifier. Thermal noise associated with
each element gives rise to a power spectral density that has
a flat frequency power spectrum with one-sided density
STH = 4kTR

Two performance criteria that we consider are its cost, as

measured in its area and power dissipation, and dynamic
range. Other performance criteria may be relevant, such as
maximum bandwidth or minimum supply voltage.

435

(8)

where k is Boltzmanns constant, T is the absolute temperature, and the combined noise factors of the conductance and
amplifier. In general, is greater than unity.
Another major source of noise for integrators is 1/f, or
flicker, noise. Its power spectrum is proportional to the inverse of the frequency, hence, its name. Flicker noise becomes
dominant at low frequencies.
We now configure the integrator as a single-pole lowpass
filter by placing a conductance of value 1/R in parallel with
the capacitor. Its transfer function is given by
VO (s)
1
=
VI (s)
1 + s/RC

(9)

Considering thermal noise only, the noise level at the output

is found by integrating the product of the power spectrum in
Eq. (8) and the square magnitude of the lowpass filter in Eq.
(9) over all positive frequencies. In order to account for the
presence of two conductors, the noise level is found to be
VN2 = 2

kT

(10)

The expression Eq. (10) shows that the noise level does not
depend on the value of the resistor, but primarily on the value
of the capacitory.
Distortion. The sources of distortion in the integrator are:
(1) the capacitor, (2) the amplifier, and (3) the conductance.
Linear capacitors are available in CMOS fabrication processes suitable for analog and mixed-mode circuits. Linear capacitors are needed to obtain a high dynamic range integrator. In addition, an amplifier which operates over the full
voltage supply range is necessary to achieve low distortion for
large amplitude input signals. If we suppose that the conductance is implemented using an MOS transistor operating in
the triode region, there will be some range of input voltages
over which the effective resistance is nearly constant. One
measure of distortion that is mathematically tractable is the
maximum deviation of the effective resistance, expressed as a
percent of the nominal value. Then, the linear range is de-

436

INTEGRO-DIFFERENTIAL EQUATIONS

fined as the continuous set of input voltages over which the

maximum deviation of the effective resistance is less than
d% of the nominal value, where d% is the amount of distortion. Other distortion measures are possible, such as meansquare error; however, they can be much more complex to
compute, as they may require knowledge of the input signal
and the circuit topology.
The highest achievable linear range is limited by the voltage supplies. As such, the maximum input and output amplitude range for a sinusoidal signal is VDD. For an input signal
of maximum amplitude, the level is VDD2 /2. As a result, the
highest achievable dynamic range of the low-pass filter is

DR =

VI2
VN2

CV DD
4kT

(11)

Cost Versus Dynamic Range

Here, we relate the cost of the integrator to its dynamic
range. If we only consider dynamic power dissipation as found
in Eq. (7), we see that
P / fs
DR = D
16kT

PD
2 C
4VDD

BIBLIOGRAPHY
A. S. Sedra and K. C. Smith, Microelectronic Circuits, 4th ed., New
York: Oxford University Press, 1998.
P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated
Circuits, 3rd ed., New York: Wiley, 1993.
Y. Tsividis, The MOS Transistor, New York: McGraw-Hill, 1988.
E. Vittoz, Micropower techniques, in J. Franca and Y. Tsividis (eds.),
Design of Analog-Digital VLSI Circuits for Telecommunication and
Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1994.
G. Groenewold, Optimal dynamic range integrators, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 39: 614627, 1992.
P. M. Furth and A. G. Andreou, A design framework for low power
analog filter banks, IEEE Trans. Circuits Syst. I, Fundam. Theory
Appl., 42: 967971, 1995.

PAUL M. FURTH
New Mexico State University

ANDREAS G. ANDREOU

(12)

Both the numerator and the denominator in Eq. (12) have the
units of energy. Thus, the upper limit on the dynamic range
of the low-pass filter is directly proportional to the amount of
energy dissipated in the integrator. For example, in order to
achieve a dynamic range of 60 dB, we must dissipate at least
16 106 kT J per cycle of the input signal.
We can rearrange Eq. (7) to solve for frequency of the input
signal, as in
fS =

cluded, then, that the MOSFET-C integrator can approach

the dynamic range maximum in Eq. (11), whereas the best
transconductance-C integrator is at least several dB lower.

(13)

Thus, for fixed power supply voltage and power consumption,

the input frequency is constrained by the size of the capacitor.
The lower the frequency of the input, the larger the area of
the integrating capacitor. Values of integrated capacitors
range from as low as 10 f F to as high as 1 nF; however, the
area penalty of the largest value is not amenable to mixed
analog/digital circuits.
Differential Signaling
Differential signaling is a technique used primarily in integrated circuits to increase the maximum amplitude range of
the input and output signals by a factor of two. Differential
signaling has two other major benefits: even-order distortion
in the amplifier, conductor, and capacitor is cancelled, as are
common-mode sources of noise. The cost of using differential
signaling is increased circuit complexity, area, and static
power consumption due to common-mode feedback circuitry.
The MOSFET-C integrator is unable to take full advantage of
differential signaling since the capacitor must have a virtual
ground at one node. Thus, its maximum dynamic range is
given by Eq. (11). On the other hand, the transconductanceC integrator can employ a differential signal across the capacitor. Notwithstanding, the transconductance-C integrator
cannot operate at the maximum input amplitude. It is con-

Johns Hopkins University

INTEGRATION. See CALCULUS.

INTEGRATION OF DATABASES. See DATABASE
DESIGN.

INTERMEDIATE-FREQUENCY AMPLIFIERS

INTERMEDIATE-FREQUENCY AMPLIFIERS FOR AM AND

FM
The intermediate-frequency (IF) amplier is the circuitry
used to process the information-bearing signal between the
rst converter, or mixer, and the decision making circuit,
or detector. It can consist of a very few or a great many
component parts. Generally, it consists of an amplifying
stage or device to provide gain and a band-pass lter to
limit the frequency band to be passed. The signal to be
processed can be audio, video, or digital, using Amplitude
Modulation, Frequency Modulation, Phase Modulation or
combinations thereof. Several examples are shown in Figs.
13 through 19.
IF ampliers are also used in radio transmitters to limit
the occupied bandwidth of the transmitted signal. Certain
modulation methods create a very broad frequency spectrum which interferes with adjacent channels. Regulatory
agencies, such as the FCC, require that these out-of-band
signals be reduced below a certain permissible level, so
they must undergo processing through a bandwidth limiting lter and amplier.
For each application there are certain design restrictions or rules which must be followed to achieve optimum
results.
General IF Amplier Functions and Restrictions
1. Image Rejection The mixer stages in a receiver convert a frequency below or above the local oscillator
frequency to an IF frequency. Only one of these frequencies is desired. The IF frequency must be chosen so that undesirable frequencies or images are removed by the RF amplier lter and are rejected by
the mixer. This may mean that two or three different IF frequencies must be used within the same receiver. The IF frequencies in common use range from
0 Hz to approximately 2.0 GHz.
2. Selectivity Selectivity is required to reject as much
as possible of any adjacent channels interfering signal. Generally this means obtaining a band-pass lter characteristic as close to that of the ideal lter
as possible to pass the necessary Nyquist bandwidth
(the baseband bandwidth from 0 Hz to the highest
frequency to be passed) without introducing harmful
amplitude or phase distortion.
3. Gain Gain is required to amplify a weak signal to
a useful level for the decision making circuit. This
gain must be provided by a stable amplier that introduces a minimum of noise, so as not to degrade
the receiver noise gure. All circuit input and output
impedances should be properly matched for optimum
power transfer and circuit stability.
4. Automatic Gain Control The amplier gain must
vary automatically with signal strength so that the
decision making circuit receives a signal of as nearly
constant a level as possible. The stages of the IF am-

plier must not be overdriven or go into limiting until

after the last band-pass lter to prevent splattering
or broadening and distortion of the signal.
5. Linearity The amplier must be linear to prevent distortion of the recovered information. AM receivers
should be linear in amplitude, whereas FM or PM
receivers should be linear in phase.
Selecting the IF Frequency
Image rejection and signal selectivity are the primary reasons for selecting an IF frequency. Most currently manufactured band-pass lters of the crystal or resonator type are
standardized so that the designer can obtain off the shelf
components at reasonable cost for these standard frequencies. The standard AM broadcast receiver utilizes a 455
kHz IF lter because extensive experience has shown that
this rejects all but the strongest images. Assume that the
desired signal is at 600 kHz. A local oscillator operating
at 1,055 kHz has an image frequency at 1,510 kHz, which
the RF input lter easily rejects. Similarly, an FM receiver
operating at 90.1 MHz with an IF frequency of 10.7 MHz
has an image at 111.5 MHz, which is rejected by the RF
amplier. A single IF frequency is used in both of these
cases. A receiver operating at 450 MHz requires two IF
frequencies obtained by using rst and second mixers, as
in Fig. 16. The rst IF amplier may consist of a relatively
broadband lter operating at 10.7 or 21.4 MHz, followed
by a second converter and IF stage operating at 455 kHz.
The rst IF lter is narrow enough to reject any 455 kHz
images, and the second IF lter is a narrowband lter that
passes only the desired signal bandwidth. If the 455 kHz
lter had been used as the rst IF lter, the 450 MHz RF
lter, being relatively broad, would not have eliminated the
image frequency, which is 455 kHz above or below the local
oscillator frequency.
Television receivers use a video IF frequency of approximately 45 MHz, because this allows a relatively broad RF
lter to pass the broadband TV signal, while still rejecting
the images. The video signal from the IF amplier is AM
with an FM sound carrier riding on it. Television sound is
generally obtained from a beat, or difference frequency, between the video and sound carriers, which is at 4.5 MHz.
Satellite receivers use a broadband rst IF frequency covering a frequency block from 900 MHz to 2.1 GHz. This is
done by a Low Noise Block converter (LNB). The second
mixer is tunable so that any frequency in the block is converted to the second IF frequency, usually xed at 70 or
140 MHz. The second IF frequency, which drives the detector, has a narrower bandwidth to reduce noise and reject
adjacent channel interference.
Crystal, ceramic resonator and SAW lters are mass
produced at relatively low cost for the frequencies mentioned previously, so that most consumer products employ
one or more of these standard frequencies and standard
mass produced lters.
Selectivity
Carsons rule and the Nyquist sampling theorem, on which
it is based, state that a certain bandwidth is required to

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Intermediate-Frequency Ampliers

transmit an undistorted signal. The necessary bandwidth

for an AM signal is given as

Thus an AM broadcast receiver requires 10 kHz of bandwidth to pass a 5 kHz = fm audio tone. In data transmission
systems, the frequency fm corresponding to the data rate fb ,
is given by fm = fb . The data clock frequency is twice the
frequency of the data in ones and zeros. This means that a
baud rate fb of 9,600 bits per second requires a bandwidth
of 9.6 kHz.
For FM, the necessary bandwidth required for transmission is given by

A 15 kHz audio tone (= fm ) and an FM transmitter deviated with a modulation index of 5 requires 2 [15 + (15
5)] = 180 kHz of bandwidth.
f is (5 15) and fm is 15
kHz. Narrow band FM (with a modulation index less than
0.7) is somewhat different in that the bandwidth actually
required is the same as that for AM because the higher
Bessel products are missing (Eq. 1).
These values are for double-sideband transmission.
Single-sideband transmission requires half as much bandwidth. The required baseband bandwidth is the same as
the value for fm . This is also known as the Nyquist bandwidth, or the minimum bandwidth that carries the signal
undistorted at the baseband.
Ideally the IF lter, or the baseband lter, need pass
only this bandwidth and no more. This requires an ideal
band-pass or low-pass lter, which does not exist, but is
approached by various means. The lter must be as narrow as conditions permit to reduce the noise bandwidth and
any adjacent channel interference, because noise power increases linearly with increasing lter bandwidth.
Gain
The IF amplier must provide sufcient gain to raise a
weak signal at the RF input to the level required, or desired, by the decision making circuit or detector. This receiver gain varies from 0 up to 130 dB, most of which must
be provided by the IF amplier. The RF amplier and mixer
circuits preceding the IF amplier generally provide 20 or
more dB of gain so that the IF amplier generally contributes little to the receiver noise gure. See noise gure
elsewhere in this article.
Gain is provided by an amplifying device, such as a transistor or vacuum tube (in older equipment). These devices
have complex input and output impedances that must be
matched to the ltering circuits for best power transfer,
stability, and lowest noise. Current practice is to use a
gain stage which consists of multiple amplifying devices
in an integrated circuit package. These packages contain
the mixer stages and detectors.
Automatic Gain Control
Receivers must respond to a wide range of input levels
while maintaining a nearly constant level at the detector or
decision making circuit. The user or operator does not wish

to manually adjust the gain to obtain a constant sound or

picture level when changing stations. This function is performed by detecting the output level of the IF amplier and
correcting it by a feed-back circuit that adjusts the level
to keep it as constant as possible. Because this detected
level varies rapidly, it is passed through a low-pass lter
(usually an RC pair) to integrate or slow down the changes,
then amplied by a dc amplier, and applied to an IF amplier circuit or gain stage with variable gain characteristics.
Some receivers, such as those in an automobile, require
relatively rapid acting automatic gain control (AGC) circuits, whereas xed receivers use a much slower AGC time
constant. Dual-gate, eld-effect transistors use the second
gate to control the gain. Bipolar or single-gate, eld-effect
transistors vary the gain by a bias voltage or current applied to the input terminal along with the signal. Special
integrated circuit gain stages for IF amplication are available, such as the Motorola MC 1350, which amplify and
provide a variable gain control function.
Band-Pass Filters for IF Ampliers
Except for block conversions, which convert wide frequency
bandwidths, such as those used on satellite receivers, IF
ampliers generally use a narrow band-pass or a low-pass
lter to limit the bandwidth to the Nyquist bandwidth.
Block conversion, on the other hand, uses a high-pass/lowpass lter pair where the bandwidth to be passed is between the high and low cutoff frequencies.
The traditional band-pass lter requires a resonant element. Although the actual resonator may be a coil and
capacitor, ceramic resonator, or SAW lter, the principles
are basically the same. Digital lters which do not use
resonators have been employed more recently. These are
discussed later in brief. They are discussed in more detail
elsewhere in this encyclopedia.
The inductance/capacitor resonator was the rst used,
and is still a comparison standard. Figure 1(a) shows a series resonant circuit and Fig. 1(b) shows a parallel resonant
circuit. These circuits pass a signal at the resonant peak
and reject a signal off resonance. Rs and Rp are naturally
occurring losses that reduce the circuit efciency. Figure 2
shows the universal resonance curve which is applicable to
both series and parallel resonant circuits. It is important
to note that the signal rejection never goes to a zero level
in the area of interest, but reaches an asymptotic value of
about 0.2 or 15 dB. If it is necessary to reject a signal on
the shoulders of this curve by 60 dB, then four cascaded
stages of this lter must be used to obtain the necessary
rejection. Note also that there is a nonlinear phase shift
that reaches a maximum in the area of interest of about
70 . When stages are cascaded, this phase shift is multiplied by the number of stages. A nonlinear phase shift
causes distortion in FM receivers.
A frequency f0 , at which the response of a parallel resonant LC lter is a maximum, that is, the point at which the
parallel impedance is a maximum, is dened as a pole. A
frequency at which the impedance is a minimum, as in the
series LC circuit, is dened as a zero. Thus the previous assumed four cascaded stages above constitute a four-pole lter, because it contains four resonant poles. The frequency

Intermediate-Frequency Ampliers

Figure 1. Series and parallel resonant circuits. Rp and Rs are

loads that reduce the efciency of the circuit.

Figure 3. A typical transistor IF circuit with bandpass lter.

Tan =

Figure 2. The Universal Resonance Curve. The phase change

is shown for series resonance. The phase reverses for parallel resonance. = Q (Hz off resonance)/(Resonant frequency).

of resonance is given by Eq. (3). This is the frequency at

which Xc = 1/jC and XL = jL are equal.

The bandwidth that an analog LC lter passes is altered

by the circuit efciency, or circuit Q, given in Eqs. (4a),
(4b), and (4c). Generally the bandwidth is specied as the
bandwidth between the 3 dB points.

For simplicity in analyzing the following circuits, the Q

determining R is assumed to be a parallel resistance Rp
across the inductance.
The amplitude response of the resonant circuit is given
by Eq. (5a) and the phase response by Eq. (5b).
G( j) = A( j) =

1
1 + jQ(2
f/ fo )

Q(2
f/ fo )
1

Figure 3 shows a typical IF amplier stage used in earlier transistor radios. In this circuit R p (the total shunting resistive load) is actually three resistances in parallel,
one the equivalent Rp of the coil itself (representing the
coil losses), another the input resistance of the following
stage, as reected, and the third the output resistance of
the driving transistor, as reected. It cannot be assumed
that the resulting coil Q and, hence, the selectivity of the
circuit is that of the unloaded coil and capacitor alone.
Dual-gate, eld-effect transistors have the highest shunting resistance values, and bipolar transistors the lowest.
The gain is varied by increasing or decreasing the bias voltage Vb applied to the input terminal.
Manufacturers of amplifying devices often provide the
impedances, or admittances, of their products on their data
sheets. Formerly this was done in the form of h parameters.
The more common practice today is to provide the information in the form of S parameters. These values can be
converted to impedances and admittances, but the manual
process is rather complicated. An easier method is to use
the various software programs (see references) to make the
conversion. Matrix algebra and h and S parameters are
discussed elsewhere in this article and also in references
(3, 4). Unfortunately, S parameters for band-pass lters are
rarely available.
Figure 4(a) shows the equivalent circuit of the transistor
as the tuned LC sees it. The transistor amplies a current
which is passed through a relatively low driving resistance
Rs to the outside. At the same time, the attached LC sees
an equivalent shunting resistance Rc and capacitance Cc
which must be added in parallel to Rp , L, and C. The input
to the following stage, assumed to be an identical transistor, has a relatively low shunting resistance Ri , and capac-

Intermediate-Frequency Ampliers

Figure 5. Impedance step up or down using a transformer.

Figure 4. (a) The equivalent circuit of a transistor amplier. (b)

The equivalent circuit of Fig. 3 when all of the shunting loads are
included.

itance Ci which must be added. Unless the added capacitances are large compared to the resonant C, they merely
add to it without greatly detuning the circuit. When tuned,
the total C plus L determine the frequency and the resulting total R p determines the Q of the LC circuit, hence the
bandwidth. Thus the complex components are tuned out,
and the remaining design problem consists of matching the
real or resistive part of the input and output impedances
to the best advantage.
The desired result is to couple the output of the driving stage to the input of the following stage with the least
loss by matching the differing impedances. An additional
desired result is to narrow the band of frequencies passed
by a lter. These objectives are accomplished by transforming the input and output impedances to a higher or lower
shunting impedance that maintains the desired bandpass
characteristic of the lter. A low driving or load impedance
can be stepped up to a very high impedance which maintains the circuit Q at the desired value.
Impedance matching enables the designer to change the
actual impedance to a different apparent value which is optimum for the circuit. Figure 5 shows how impedances are
matched by transformer action. A transformer with a 3:1
turn ratio is shown as an example. The output impedance
relative to the input impedance is given by Eq. (6). Ni and
No are the input and output numbers of turns on the winding.

Thus 90  at the input is seen as 10  at the output. The

auto transformer [tapped coil in Fig. 5(b)] has the same
relationship.
When all of the reactances and resistances from the
tuned circuit and the transistor input and output, as modied by the step-up/step-down process of the impedance

Figure 6. Impedance matching utilizing capacitors.

matching networks are added, the network in Fig. 4(b) results. To calculate the resonant frequency and circuit Q
from these reactances and resistances in parallel is complicated unless they are converted to admittances. Software is
available at reasonable cost to perform these calculations.
See references.
Stock or mass produced IF transformers often do not
have the desired turns ratio to match the impedances. An
additional Z match circuit using capacitors enables the
available transformers to match almost any impedance.
This capacitor divider circuit is often used instead of a
tapped coil or transformer as shown in Fig. 6.
The formulas for calculating the matching conditions
with capacitors are more complex than those used for
transformer coupling, because there are more variables.
In this circuit Ri , is assumed to be lower than Rp . Although
Rp is the equivalent parallel resistance of the LC circuit in
Fig. 6, it could also be the reduced resistance or reected
Rp2 at a transformer tap. N in these equations is equal
to the loaded resonator Q, or to a lower arbitrary value if
total shunting Rp is lowered by transformer action as in
equation (6) or if the component ratios become unwieldy.

Intermediate-Frequency Ampliers

Figure 7. Double-tuned circuits coupled together.

Equations (8) and (9) calculate the reactances of the two

capacitors. Note that NXL is the same as QXL . Starting
with a value of N = Q, nd XC1 , then XC2 .
If Q is large in Eq. (7), the equations reduce to the approximate values in Eqs. (10) and (11). Unless Q is less than
10, these approximate equations are accurate enough for
general use. As an example, let Ri = 100  and Rp = 10,000
 with Q = 100. Then using Eq. (10), XC2 becomes 10 
and XC1 becomes 100 . C2 is approximately ten times as
large as C1 . Note the similarity of this ratio to Eq. (6). If a
transformer is involved, N becomes much smaller and the
full formulas Eqs. (7), (8), and (9) should be used.
Equations (7) through (9) apply for R1 < Rp , and N >
(Rp /R1 1)1/2 .
Double-Tuned Circuits
When two identical LC circuits are coupled together, as
in Fig. 7, a number of responses are possible as in Fig.
8. The amplitude response depends on the coupling coefcient K. Undercoupling results in a two-pole lter with the
sharpest selectivity. Critical coupling results in the narrowest bandwidth with the highest gain. Transitional coupling is slightly greater than critical coupling and results
in a at topped response with a wider bandwidth. Overcoupling results in a double-humped response with sharper
skirts and broad bandwidth. The coupling coefcient is calculated using Eqs. (5ad). Equation (12a) applies to mutual
inductive coupling and Eqs. (12bd) to capacitive coupling.

Equation (12a) calculates the coupling coefcient for two

identical LC tuned circuits that are coupled together by
leakage inductance [Fig. 7(a)], often obtained by using
shielded coils with holes in the sides of the shield cans to
allow the magnetic elds to interact. The size of the hole
determines the value of the mutual inductance M. Because
this is difcult to control, a coupling capacitor is often used
as shown in Fig. 7(b,c). The critical coupling value is given
by Eq. (12(b)). The coupling coefcients for Fig. 7(b,c) are
given in Eqs. (12 c,d).

Figure 8. The effects of various coupling coefcients.

The amplitude response curves in Fig. 8 do not yield any

information as to the phase shifts that take place through
the lter. In AM circuits, phase is generally of little concern,
and most attention is paid to the amplitude ripple and linearity. In FM circuits, nonlinear phase shift, or a related
term differential group delay, becomes more of a problem
and efforts are made to keep the phase shift as linear as
possible. In data transmission circuits using phase modulation, any nonlinearity must be avoided. For these reasons, the coupling coefcients are carefully adjusted, and
cascaded IF amplier stages are used to get the desired
transfer function for the IF amplier.
CASCADING IF AMPLIFIER STAGES AND FILTERS
All ltering actions between the RF receiver input and the
decision making circuit are parts of the IF amplier bandpass lter. Because the decision making circuit is at baseband, or 0 Hz, all ltering before the decision making circuit is part of the IF bandpass ltering, which should be
treated as a whole.
A single LC circuit seldom has the desired bandpass
characteristic for an IF amplier. Cascading IF amplier
stages with differing coupling and Q values enables the
designer to obtain the desired transfer response. One combination of LC lters uses an overcoupled, double-tuned
stage followed by a single tuned stage with a lower Q.
The result is a three-pole lter with relatively steep skirt
slopes. Cascading these stages results in lters with responses resembling Butterworth, Chebycheff, elliptical, or
equal-ripple lters which are noted for rejecting adjacent
channel interference. See Figs. 9 and 10.
When additional ltering is required at the baseband,
simple RC lters, low-pass LC lters, or digital FIR lters
are used. These and other lters are discussed in greater
detail elsewhere in this encyclopedia.
Crystal and Ceramic Filters
Figure 11(a) shows the equivalent circuit of a crystal or a
ceramic resonator. These devices have both a pole and a
zero whose frequencies are located relatively close to each
other. Quartz crystals have Q values from 2,000 to 10,000
or more depending on the mechanical loading of the crys-

Intermediate-Frequency Ampliers

Figure 9. Two amplier stages cascaded. The rst stage is overcoupled; the second stage with a lower Q is critically coupled.
Figure 12. The frequency response of the two-pole crystal resonator in Fig. 11(b).

Figure 10. The overall response of the two cascaded stages in

Fig. 9.

When using these devices, care must be taken to carefully match the specied impedance. Any impedance mismatch seriously alters the response curve of the lter. The
impedance matching techniques previously discussed enable the designer to obtain a very close match which optimizes the circuit performance. Typical input and output
impedances range from 50 to 4,000 . Crystal lter makers
often build in transformer or other tuned matching circuits
so that the user does not need to provide a matching circuit
outside the crystal lter.
Surface acoustic wave (SAW) lters utilize a crystal oscillating longitudinally with many ngers or taps placed
along the surface. They are made with very broad bandpass characteristics, which makes them well suited for TV
IF ampliers, spread-spectrum IF lters, and other uses requiring wide bandwidths. They have losses which are typically about 8 to 20 dB, so they must have ampliers with
adequate gain ahead of them if the receiver noise gure is
not to be degraded. They are not suitable for narrowband
or low-frequency applications.
Baseband IF Filtering

Figure 11. (a) The equivalent circuit of a crystal or ceramic resonator. (b) Two resonators are coupled together to form a bandpass
lter.

tal. Ceramic resonators usually have Q values between 100

and 400. The higher the Q, the narrower the lter bandpass. When two of these devices are connected as shown in
Fig. 11(b), the result is a band-pass lter with steep skirts,
as in Fig. 12. These devices are always used in pairs to
make a two-pole lter, which then is combined in a single
container with other pairs to create a lter with as many as
eight or more poles. They usually have excellent adjacent
channel rejection characteristics.

IF lters with specic response characteristics are sometimes very difcult to obtain, whereas the desired characteristic is easily and inexpensively obtainable at the baseband. This concept is often applied to transmitters where a
sharp cutoff lter is obtained with simple components, such
as the switched lter. An eight-pole equivalent at baseband
becomes a 16-pole lter at the modulation IF frequency. For
example, a sharp cutoff lter for voice with a 4 kHz audio
cutoff results in a bandpass lter 8 kHz wide at RF after
modulation, with the same sharp cutoff. The same cutoff
characteristics at RF are almost impossible to obtain in a
crystal lter, which is also very costly and beyond the budget for a low-cost transmitter, such as a cordless telephone.
By using baseband ltering, a poor-quality RF lter that
rejects only the opposite image is used. Similarly, a wideband or poor-quality IF lter is used ahead of a detector
if the undesired signal components are ltered off later at
baseband by a sharp cutoff lter.
Switched capacitor lters are available as packaged integrated circuits that are used at baseband and some lower
IF frequencies. They have internal operational ampliers
with a switched feedback capacitor, the combinations of

Intermediate-Frequency Ampliers

which determine the lter characteristics. Because they

depend on the speed of the operational ampliers and the
values of the feedback capacitors, they seldom function
much above 100 kHz. They can be congured as Bessel,
Equal-ripple and Butterworth lters. Typical of this type
of lter are the LTC 1060 family manufactured by Linear Technology Corporation and the MAX274 from Maxim.
As Bessel type lters, they perform well out to about 0.7
times the cutoff bandwidth, after which the phase changes
rapidly and the Bessel characteristic is lost.
Digital signal processing (DSP) at baseband is widely
used to reduce the component count and size for baseband
lters in very small radio receivers, such as cordless and
cellular telephones. Almost any desired lter response is
obtained from DSP lters without inductances and capacitors which require tuning. FIR lters have a at group
delay response and are the best choice for FM or PM ltering.

Figure 13. An integrated circuit with built-in IF amplier that

comprises an almost complete AM radio.

Amplifying Devices for IF Ampliers

Transistors in one form or another are the standard for
IF ampliers. The single, bipolar or eld-effect transistor
(FET) used as an individual component, was formerly the
preferred device. For very high Q circuits, the dual-gate
FET performs best, because it is the most stable and offers
the lowest shunt resistance. Single-gate, FET devices often
have too much drain-to-gate capacitance for good stability.
Modern bipolar transistors usually have good stability, but
higher shunt resistances than dual-gate FETs. Stability is
discussed later in this section.
MMIC devices are stable and have good gain, but the
shunt impedance is too low for any bandpass lter except
a crystal lter matched to 50 .
The most recent practice for IF ampliers is to use integrated circuit blocks containing more than one transistor
in a gain stage. These are then packaged together in an integrated circuit with other circuit components to form an
almost complete radio. Integrated circuits of this type are
shown later.
Typical Consumer IF Ampliers
Consumer radio and TV equipment is mass produced at
the lowest possible cost consistent with reasonable quality.
Manufacturers of integrated circuits now produce singlechip IF ampliers that are combined with mass produced
stock lters to produce a uniform product with a minimum
of adjustment and tuning on the assembly line. In the examples that follow, some circuit components inside and outside the IC have been omitted to emphasize the IF amplier
sections.
Figure 13 shows a single-chip AM receiver that uses the
Philips TDA 1072 integrated circuit and ceramic IF lters
at 455 kHz. The input impedance of the ceramic lter is
too low to match the output impedance of the mixer, so
that a tuned matching transformer is used to reduce the
passed bandwidth and to match the impedances. The input
impedance of the IF amplier was designed to match the
average impedance of the ceramic lters available. This
integrated circuit has a built-in automatic gain control that
keeps the received audio output level relatively constant at

Figure 14. An integrated circuit for FM use that comprises an

almost complete FM receiver.

250 mV as long as the input signal level to the chip exceeds

30 V.
Figure 14 shows a single-chip FM radio based on the
NXP (Phillips) NE605 integrated circuit that uses ceramic
IF lters at 10.7 MHz. The input and output impedance
of the IF amplier sections is approximately 1500  to
match the ceramic lter impedance, so that no matching
transformer is required. The audio output is maintained
constant at 175 mV for all signal levels at input levels from
110 dBm to 0 dBm. An automatic frequency control (AFC)
voltage is obtained from the quadrature detector output.
AGC is available from all FM integrated circuits so that
the gain of the mixer and RF stages is controlled at a level
that does not allow these stages to be saturated by a strong
incoming signal. Saturation or nonlinearity before ltering
results in undesirable signal spreading. The NE605 has a
Received Signal Strength Indicator (RSSI) output which
is amplied and inverted if necessary to provide an AGC
voltage or current for the RF amplier and Mixer.
Figure 15 shows a TV IF amplier using the Motorola
(Freescale) MC44301/2 Video IF integrated circuit with a
SAW lter at 45 MHz. The SAW lter band-pass is approximately 6 MHz wide to pass the video and sound. The
circuit has both AFC and AGC features built in. Unlike
the IF ampliers used for AM and FM audio broadcast

Intermediate-Frequency Ampliers

Figure 15. An integrated circuit for a TV IF amplier that detects

both the AM video and the FM subcarrier sound.

applications, the TV IF amplier includes a phase-locked

loop and a synchronous detector which locks the frequency
of an internal oscillator to the IF frequency. This locked,
or synchronous oscillator output is then mixed with the
information-bearing portion of the signal to create a baseband signal. This is one of a family of 0 Hz IF ampliers
which are becoming more popular in radio designs, because
they permit most or additional signal processing at baseband. In the TV case, the video and sound carriers are both
passed by the SAW lter. They beat together at 4.5 MHz in
the detector, providing a second IF stage with the sound information. This 4.5 MHz IF information is then ltered by
a ceramic lter approximately 50 kHz wide to remove any
video components, limited, and detected as a standard FM
signal to provide the TV sound. Then the video portion, consisting of signals from 15 kHz to approximately 4.25 MHz,
is further processed to separate the color information at
3.58 MHz from the black and white information. The video
output level is detected to provide the AGC voltage.
The phase-locked oscillator, operating at the IF frequency, also provides automatic frequency control to the
rst mixer stage local oscillator.
Figure 16 shows a dual conversion receiver for communications utilizing the Motorola (Freescale) MC13135 integrated circuit. When the receiver is operated at 450 MHz
or 850 MHz, as mentioned previously, single conversion IF
stages do not offer the necessary image rejection. This receiver is for narrowband AM or FM as opposed to wideband FM for entertainment purposes. The rst IF lter is
a low-cost ceramic lter at 10.7 MHz. The second lter is
a multipole crystal or ceramic lter with a band-pass just
wide enough to pass the audio with a small FM deviation
ratio. Radios of this type are used for 12.5 kHz and 25 kHz
channel spacings for voice-quality audio. Analog cellular
telephones, aircraft, marine, police, and taxicab radios are
typical examples.
Direct Conversion and Oscillating Filters
Direct conversion converts the RF frequency directly to the
baseband by using a local oscillator at the RF frequency.

The TV IF amplier with the detector circuit given in Fig.

15 illustrates some of the reasons. Conversion to baseband
occurs at the IF frequency or directly from the RF frequency.
There is a noticeable trend in integrated circuit design
to utilize synchronous detection and restore the carrier by
a phase-locked loop, as in Fig. 15, or by regenerative IF ampliers, to achieve several desirable features not obtainable
from classical circuits with square law detectors.
In the case of direct RF to baseband conversion, there
is no IF stage in the usual sense, and all ltering occurs at
the baseband. For this reason, direct conversion receivers
are referred to as zero Hz IF radios. Integrated circuits for
direct RF conversion are available that operate well above
2.5 GHz at the RF input.
It was discovered in the 1940s that the performance of
a TV receiver is improved by using a reconstructed synchronous or exalted carrier, as occurs in the TV IF amplier described in Fig. 15. The carrier is reduced by vestigial
sideband ltering at the transmitter and contains undesirable AM signal components. By locking an oscillator to, or
synchronizing it with the carrier, and then using it in the
detector, a signicant improvement in the received signal is
achieved. Before using circuits of this type, the intercarrier
sound at 4.5 MHz in earlier TV sets had a characteristic
60 Hz buzz due to the AM on the carrier. By substituting
the recovered synchronous carrier instead, this buzz was
removed. Figure 15 is an example.
The earliest direct conversion receivers using locked oscillators or synchronous detectors were built in the 1920s,
when they were known as synchrodyne or homodyne receivers. The theory is relatively simple. A signal from the
RF amplier is coupled to an oscillator causing a beat or
difference frequency. As the frequencies of the two sources
come closer together, the oscillator is pulled to match the
incoming signal. The lock range depends on the strength of
the incoming signal. Then the two signals are mixed to provide a signal at the baseband, which is further ltered by
a low-pass lter. In this way, a relatively broad RF lter is
used, whereas the resulting AM signal bandwidth after detection and baseband ltering is very narrow. The Q of the
oscillator tank circuit rises dramatically with oscillation,
so that Q values of 6,000 to 10,000 are not unusual and
selectivity is greatly improved. AGC is obtained from the
audio signal to maintain a constant input signal to insure a
good lock range. An undesirable characteristic is the whistle or squeal that occurs between stations. Later receivers
used a squelch circuit to make the signal audible only after
locking occurred. High-quality receivers for entertainment
and communications, which use this principle have been
produced in the 1990s. They offer higher sensitivity, better
delity and more controlled response. Integrated circuits
for receivers of this type (direct conversion) are now being
produced for paging, direct broadcast TV, and for cellular
and cordless telephones. The MAX 2101 and MAX 2102
integrated circuits are typical examples.
Oscillating lters and phase-locked loops are similar in
principle. An IF frequency is applied to a phase/frequency
detector that compares the IF carrier frequency with
the oscillator frequency. An error voltage is created that
changes the oscillator frequency to match or become co-

Intermediate-Frequency Ampliers

herent with that of the incoming IF carrier frequency. In

some cases the phase-locked loop signal is 90 out of phase
with the carrier, so that a phase shifter is used to restore
the phase and make the signal from the oscillator coherent with the incoming signal. See Figs. 15 and 19 where
phase-locked loops and phase shifters are employed.
Synchronous oscillators and phase-locked loops (PLL)
extend the lower signal to noise ratio, and they also have
a bandwidth ltering effect as well. The noise bandwidth
of the PLL lter is the loop bandwidth, whereas the actual
signal lter bandwidth is the lock range of the PLL, which
is much greater. Figure 17 shows the amplitude and linear phase response of a synchronous oscillator. The PLL
is not always the optimum circuit for this use because its
frequency/phase tracking response is that of the loop lter. The locked oscillator (6) performs much better than the
PLL because it has a loop bandwidth equal to the lock range
without sacricing noise bandwidth, although with some
phase distortion. Some authors hold that the synchronous
oscillator and locked oscillator are variations of the PLL
in which phase detection occurs in the nonlinear region of
the oscillating device and the frequency-change characteristic of the voltage-controlled oscillator (VCO) comes from
biasing of the oscillator. Both the PLL and the locked oscillator introduce phase distortion in the detected signal if
the feedback loop is nonlinear. A later circuit shown in Fig.
18 has two feedback loops and is considered nearly free of
phase distortion (5). This circuit has the amplitude/phase
response given in Fig. 17.
Phase-locked loops have been used for many years for
FM ltering and amplication. They are commonly used
with satellite communication links for audio and video
reception. A 74HC4046 phase-locked loop integrated circuit operating at 10.7 MHz (the FM IF frequency) is used
to make an FM receiver for broadcasting (7). The phaselocked loop extends the lower signal-to-noise limit of the
FM receiver by several dB while simultaneously limiting
bandwidth selectivity to the lock range of the PLL. The
detected audio signal is taken from the loop lter.

Figure 17. The ltering effect of a synchronous oscillator used as

a band-pass lter. The lter bandpass is the tracking range. The
noise bandwidth is limited by the Q of the oscillating circuit.

Figure 18. Schematic diagram of a synchronous oscillating bandpass lter.

AM STEREO (C-QUAM)
AM stereo radio is another application of the phase-locked
oscillator at the IF frequency. AM Stereo radio depends on
two programs transmitted at the same time and frequency.
They arrive at the receiver detector circuitry through a

Figure 16. A dual conversion integrated circuit use for

high-frequency voice communications.

10

Intermediate-Frequency Ampliers

Figure 20. Neutralization or unilateralization of a transistor amplier to prevent oscillation due to feedback.
Figure 19. An integrated circuit to detect AM Stereo (C-QUAM).
The L + R and L R signals are in quadrature to each other.

common IF amplier operating at 455 kHz. The normal

program heard by all listeners is the L + R program. The
stereo information (L R) is transmitted at the same frequency, but in quadrature phase to the L + R program.
Quadrature, or orthogonal transmission, is used because
the orthogonal channels do not interfere with one another.
Each program section requires a carrier coherent with its
own sideband data. The L + R program, which has a carrier, uses an ordinary square law detector or a synchronous
detector. This is the program heard over monaural radios.
To obtain the L R program which is transmitted without
a carrier, a phase-locked loop is used at the IF frequency
to lock a voltage-controlled oscillator to the carrier of the L
+ R program. This carrier is then shifted 90 in phase and
becomes the carrier for the L + R segment. The output of
the PLL has the proper phase for the L R detector, so that
phase shifting is not necessary. The L R detector is a coherent or synchronous detector that ignores the orthogonal
L + R information. By adding, and inverting and adding,
the left and right channels are separated. Figure 19 shows
a simplied block diagram of the C-QUAM receiver.
The Motorola (Freescale) MC1032X series of integrated
circuits is designed for AM Stereo use. The MC10322 and
MC10325 have most of the components required, including
the IF ampliers, for a complete AM Stereo receiver in two
integrated circuit packages.
Subcarriers
Subcarriers carry two or more signals on the same carrier.
They differ from the orthogonal signals used with C-QUAM
in that they are carried as separate signals superimposed
over the main carrier information, as in the video sound
carrier in Fig. 15. In Fig. 15, a frequency-modulated subcarrier at 4.5 MHz is carried on top of the main video signal information, which extends from 0 to 4.25 MHz. This
is an example of an AM/FM subcarrier. Nondigital satellites utilize a frequency-modulated video carrier with as
many as 12 subcarriers at frequencies ranging from 4.5
MHz to 8.0 MHz. Normal FM Stereo broadcasting utilizes
a FM/AM subcarrier at 38 kHz to carry the LR portion of
the stereo program. FM stations also frequently carry ad-

ditional subcarriers at 67 and 92 kHz. These FM/FM subcarriers carry background music, ethnic audio programs,
and digital data.
To detect a subcarrier, the signal is rst reduced to the
baseband, then a band-pass lter is used that separates
only the subcarrier frequencies. Then the subcarrier frequencies are passed to a second detector which is of the
proper type for the subcarrier modulation. This is seen in
Fig. 15 where a 4.5 MHz lter is used. This is followed by
a limiter and quadrature detector as is appropriate for an
FM signal. In the case of a 67 kHz FM/FM subcarrier, the
lter is 15 kHz wide at 67 kHz. Detection is accomplished
by a discriminator, quadrature detector, or PLL.
Cellular and Cordless Telephones
Analog cellular telephones employ the circuits shown in
Figs. 14 and 16. Digital telephones utilizing GMSK also
use these circuits. Digital telephones using QAM or PSK
employ circuits similar to that used for C-QUAM with digital ltering and signal processing instead of audio ltering at the baseband. The PLL for digital receivers is a more
complex circuit known as the Costas Loop, which is necessary to restore a coherent carrier for digital data recovery.
Some cellular phones are dual mode, that is, they transmit and receive analog voice or digital GMSK modulation
using circuits similar to Figs. 14 and 16.
Neutralization, Feedback, and Amplier Stability
Earlier transistors and triode vacuum tubes had considerable capacitance between the output element (collector or
plate) and the input side of the device. (See Fig. 4.) Feedback due to this capacitance is multiplied by the gain of
the stage so that enough signal from the output was often
coupled back to the input to cause the stage to oscillate unintentionally, as opposed to the planned oscillation of the
locked oscillator, synchronous oscillator, or PLL. To prevent
this, feedback of an opposite phase was deliberately introduced to cancel the undesired feedback. A neutralized IF
amplier is shown in Fig. 20. Transistors and integrated
circuits made since 1985 are rarely unstable and generally
do not require neutralization unless seriously mismatched.
A solution better than neutralization is usually to improve
the matching of the components and the circuit layout.

Intermediate-Frequency Ampliers

By carefully controlling the feedback, a regenerative IF

amplier that operates on the verge of oscillation can be
constructed. This greatly increases the Q of the tuned circuit, thus narrowing the IF bandwidth. Circuits of this type
were once used in communications receivers for commercial and amateur use where they were called Q multipliers.
The maximum stable gain (MSG) achieved from a potentially unstable amplier stage without neutralization
is obtainable from S parameters and is calculated from
Eq. (13). This equation assumes that the input and output
impedances are matched and that there is little or no scattering reection at either the input or output. The stability
factor K, usually given with the S parameters, must be >1.
A failure to match the impedances can result in an unstable amplier, but does not necessarily do so. A higher gain
is obtained, but at the risk of instability.

The most frequent cause of amplier instability or oscillation is poor circuit board layout or inadequate grounding and shielding, not the device parameters. The wiring,
whether printed or hand wired, forms inductive or capacitive coupling loops between the input and output terminals of the amplifying device. This is particularly noticeable when high gain ICs, such as the NXP SA636, are used.
These integrated circuits have IF gains of over 100 dB and
require very careful board layouts for best results. Undesirable feedback greatly decreases the usable gain of the
circuit.
Software Radio
Digital radios, or radios based on digital signal processing
(DSP), offer some technical advantages over their analog
predecessors. Digital radios are used for digital modulation, and also for AM and FM. One receiver simultaneously
detects both digital and analog modulation, thus they can
be used for cellular telephones in environments where multiple modulation standards are used. As a class, they belong
to the zero Hz IF frequency group.
The typical receiver consists of a conventional RF front
end and a mixer stage that converts the signal to a lower
frequency, as in the dual conversion radios discussed previously (Fig. 16). The signal at this stage is broadband, but
not broadband enough to include the image frequencies.
Then the signal is fed to an analog-to-digital (ADC) converter which is sampled at several times fm . This converts
the portion of interest of the signal to the baseband (or 0
Hz) instead of a higher IF frequency. The actual ltering
to remove unwanted interfering signals then takes place
at baseband by baseband by digital ltering. Digital signal processing and decimation are covered elsewhere in
this encyclopedia. The ADC performs the same functions
as the oscillating detectors shown previously.
Noise gure, amplication, and AGC considerations of
the rst IF amplier are the same as those for a conventional receiver. The ADC and the DSP lters function best
with a constant signal input level.
The term Software Radio has been adopted because
the tuning function is done in software by changing the
sampling frequency at the ADC. The sampling frequency is

11

obtained from a digitally controlled frequency synthesizer

instead of tuned LC circuits.
Spread-Spectrum Radios
The spread-spectrum receiver also uses a conventional
front end with a wideband rst IF stage. The same conditions apply as to software radios and dual conversion receivers. The rst IF stage must have the necessary bandwidth to accommodate the spread bandwidth to amplify
it with minimum added noise, and to match the output
to the despreading circuitry. Spread spectrum is covered
elsewhere in this encyclopedia. Although usually associated with digital reception, spread-spectrum technology is
also used for analog audio.
Computer-Aided Design and Engineering
For IF lter design, the admittances rather than the
impedances are easiest to use, because most components
are in parallel as shown in the equivalent circuit of Fig.
4(b). Unfortunately, most available data is in the form of
S parameters which are very difcult to convert manually
to impedances or admittances. Parameters for the lters
are rarely available, so that calculated values based on
assumed input and output impedances must be used unless test equipment capable of measuring return losses or
standing waves is available. Then the S parameters are
measured or calculated.
Smith and Linville charts have been used by some authors to design IF ampliers, but these methods are not
totally satisfactory for IF amplier design, because a high
Q circuit has its plot near the outer edge of the circle and
changes are difcult to observe. The network admittance
values shown in Fig. 4 would be used.
Computer programs that handle linear or analog designs, such as the various Spice programs, are readily
available. Other programs which concentrate on lter design can simplify lter design. They have outputs which
interface with the Spice programs if desired. Most semiconductor manufacturers provide scattering parameters (S
parameters) or Spice input data on disk for use with these
programs. Some design software sources are listed in the
bibliography.
BIBLIOGRAPHY
1. J. M. Petit M. M. McWhorter Electronic Amplier Circuits,
New York: McGrawHill, 1961.
2. W. T. Hetterscheid Transistor Bandpass Ampliers, Philips
Technical Library, N. V. Philips, Netherlands/Philips Semiconductors, 1964.
3. R. Hejhall RF Small Signal Design Using Two-Port Parameters, Motorola Applications Note AN 215A.
4. F. Davis Matching Network Designs With Computer Solutions,
Motorola Applications Note AN 267.
5. V. Uzunoglu M. White Synchronous oscillators and coherent
phase locked oscillators, IEEE Trans. Circuits Syst., 36: 1989.
6. H. R. Walker Regenerative IF ampliers improve noise bandwidth, Microwaves and RF Magazine, December 1995 and
January 1996.

12

Intermediate-Frequency Ampliers

7. R. E. Best Phase Locked Loops, 3rd ed., New York:

McGrawHill, 1997.
8. R. W. Goody MicroSim P-Spice for Windows. 2nd ed., Upper
Saddle River, NJ: PrenticeHall, 1998.
9. M. E. Herniter Schematic Capture with MicroSim P-Spice. 2nd
ed., Upper Saddle River, NJ: PrenticeHall, 1996.
10. W. Hayt, Jr. J. Kemmerly Engineering Circuit Analysis, 5th
ed., New York: McGrawHill, 1993.
11. W. K. Chen The Circuits and Filters Handbook, Piscataway,
NJ: IEEE Press 1995.
12. ARRL Handbook for the Radio Amateur, 65th ed., Newington,
CT: American Radio Relay League (Annual).
13. John Keown, Orcad PSpice and Circuit Analysis Upper Saddle
River, NJ: Prentice-Hall, 2001. (Includes Orcad P-Spice software).
14. (Note: Microsim P-Spice is no longer available. See www.webee.com, or Cadence to substitute Orcad P-Spice.)

Integrated Circuits and Semiconductors

AMD, One AMD Place, P.O. Box 3453; Sunnyvale, CA 94088
www.amd.com.
Analog Devices, One Technology Way, P.O. Box 9106, Norwood, MA
02062 www.analog.com
Freescale Semiconductor. www.freescale.com
Linear Technology Corporation. www.linear.com
Maxim Integrated Products, www.maxim-ic.com
Freescale, formerly Motorola, Semiconductors are now under
www.freescale.com
NXP, formerly Philips, www.NXP.com

Software
Ansoft/Compact Software, 201 McLean Blvd., Paterson, NJ 07504.
www.ansoft.com
Agilent.( Hewlett Packard ). Now combines Eagleware, Sysview
and eeSoft. www.eagleware.comEagleware Corp., 1750 Mountain Glen, Stone Mtn, GA 30087Elanix Inc., 5655 Lindero
Canyon Road, Suite 721, Westlake Village, CA 91362 ( SysView
)Hewlett-Packard Company, P.O. Box 58199, Santa Clara, CA
95052 ( eeSoft ).
Cadence. 2655 Seely Ave. San Jose CA.95134. www.cadence.com
Freescale Seminconductor. www.freescale.com
Intusoft, 879 W. 19th St, Suite 100, Gardena CA. 90248-4223
www.intusoft.com.
Linear Technology Corp. www.linear.com
Mathworks. 3 Apple Hill Drive, Nagick MA. 01760
www.mathworks.com
Electronic Design Magazine ( Internet ). www.web-ee.com

HAROLD R. WALKER
Pegasus Data Systems, Inc.,
Edison, NJ

LADDER FILTERS
Ladder filters are an important class of filter structures for
implementing highly selective magnitude frequency responses. If the ladder filter structure is used to implement or
simulate resistively terminated reactive LC filters, desirable
properties, such as the inherent stability and low sensitivity
with respect to parameter changes, can be retained.
The first LC ladder filters were implemented using inductors (Ls) and capacitors (Cs), operating in the continuoustime domain and embedded between resistive terminations.
They are referred to as analog or classical LC ladder filters.
These classical LC ladder filters perform remarkably well in
practice and are capable of realizing highly selective magnitude frequency responses. However, they are not suitable for
microelectronic integration because inductors are usually
bulky. To overcome this limitation, inductorless microelectronic filters, such as RC-active filters, switched capacitor
(SC) filters, and digital filters, have been developed. In the
early years of their development, these modern microelectronic filters were unfortunately found to be inferior to LC
ladder filters for a number of reasons. In particular, they did
not possess the desired inherent stability and low-parameter
sensitivity properties and, as a result, had poor performance in terms of stability and parameter sensitivity, especially for realizing highly selective magnitude frequency responses.
Fortunately, it has been found that the superior classical
LC ladder filter structure and its corresponding filter design
methodology can be simulated by modern microelectronic filters. For example, the desired properties of passivity and losslessness, as possessed by LC ladder filters, can be extended
to modern microelectronic filters in order to ensure stability
and to significantly improve the sensitivity performance of
the filter.
In this article, we are concerned with the design, synthesis, and implementation of ladder filters that conform to or
simulate the ladder structure. We shall explain the general
features of the ladder structure and its inherent advantages
as well as its most successful and widely used technological
implementations such as reactive LC, RC-active, SC, and digital filters. We begin with an overview of this subject and by
placing the subject in its historical context.
OVERVIEW OF LADDER FILTERS
The Historical Development of Classical LC Ladder Filters (1,2)
Filter theory was developed at a remarkable pace in the early
years of the twentieth century. By 1915, Campbell and
Wagner had developed the first LC filter, which not coincidentally was a ladder implementation. The first systematic LC
ladder filter design technique was facilitated by image parameter theory as introduced by Zobel in 1923. This theory was
further refined by Bode and Piloty in the 1930s. The resulting

classical ladder filter design technique was employed extensively until the 1960s when the digital computer made alternative filter design techniques practical.
The image parameter method helped to develop an intuitive approach to the filter design problem without requiring
a computer. However, it was an approximate method which
did not make effective use of the poles and zeros that are
provided by the filter transfer function, resulting in suboptimal designs in terms of the order of the filter. Therefore,
much research was devoted to finding an optimal solution for
the LC ladder filter design problem, including both the approximation of the filter transfer function and the synthesis
of the LC ladder filter network.
In 1924 and 1926, a major advance occurred when Foster
and Cauer invented canonical one-port LC networks, essentially solving the general one-port LC synthesis problem.
Later, in 1931, the general passive one-port synthesis problem was solved by Brune. His solution led to the fundamentally important concept of the positive real function, which
became the most important mathematical vehicle for the design of LC filters and which continues to be the basis of many
alternative techniques for designing high-performance RC-active, SC, and digital filters. In 1930, Butterworth and Cauer
introduced the maximally flat and Chebyshev approximations
of the filter transfer function, respectively, thereby solving the
approximation problem for an important class of filters. In
1937, Norton proposed a new filter design approach which
started from a prescribed insertion loss function. The general
reactance two-port synthesis problem, which was involved in
this new filter design method, was solved independently by a
number of researchers between 1938 and 1941. In particular,
Darlington and Cauers work led to optimal LC ladder filters
that are now widely known as elliptic filters. The insertion
loss theory of filter design was further developed by Belevitch
in 1948 using scattering matrix theory, which evolved to become the most important LC filter design method. However,
because of the extensive numerical computations that this
technique involved, it only found wide applications when powerful digital computers became available in the 1960s.
The Properties and Classical Implementations
of LC Ladder Filters
The classical LC filter is a two-port reactance (thus lossless)
network N that consists of ideal inductors and capacitors and
that is inserted between a voltage source E and two terminating resistors such as shown in Fig. 1(a), where the uppercase
voltages indicate steady-state voltages. If this two-port N is a
ladder structure, then it consists of alternating series and
shunt branches and is referred to as a double-resistively terminated ladder filter. For LC ladder filters, the series and
shunt branches are made up of simple inductors and capacitors or simple parallel and series resonant circuits. An example of a fifth-order LC ladder filter is shown in Fig. 1(a). This
filter structure is widely used to implement the elliptic filter
transfer function, whose typical attenuation response is
shown in Fig. 1(b).

183

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

184

LADDER FILTERS

L2

R1

L4

+
E

Zin

V1

C2
C1

R2

C4
C3

V2

been given by Fettweis (3) and Orchard (4) and is summarized in the following.
The filter transfer function of the reactance two-port N
such as shown in Fig. 1(a) is characterized by

C5

S21
N

2 R1 /R2V2
=
E

(1)

In the terminology of scattering matrix theory, S21 is called

the inputoutput transmittance or the transmission coefficient. The filter attenuation response , corresponding to S21,
is given by

(a)
( )
smin

a = 10 log(1/|S21|2 ) = 10 log(Pmax/P2 )

pmax

(b)
Figure 1. (a) A fifth-order ladder two-port N inserted between resistive terminations. (b) Attenuation response of a fifth-order elliptic
filter. The arrows indicate possible shifts of attenuation caused by
changes of filter parameter values.

The LC ladder filter structure is widely considered to be a

preferred filter structure because of its many inherently useful properties. Apart from the inherent advantages of the ladder topology, the properties of passivity and losslessness are
of particular significance. First, the individual inductor and
capacitor components of the embedded LC ladder network are
passive and lossless, implying (according to Kirchhoff s voltage and current laws) that the complete LC ladder filter is
passive and lossless. It is very important to note that the LC
ladder network actually satisfies a more stringent passivity/
losslessness definition, namely the internal passivity/losslessness. A Kirchhoff s network is internally passive/lossless if
and only if all the individual internal components are
passive/lossless. By proper design, the property of internal
passivity/losslessness guarantees stability and freedom from
parasitic oscillations for the filter realizations that are subject
to parasitic effects. Filters, in particular, RC-active, SC, and
digital filters, which do not simulate the internal passivity/
losslessness, are subject to (usually nonlinear) instability
problems that are caused by such parasitic effects as nonideal
phase shift, saturation, and lock-up of op-amps or quantization effects in digital filters. It is important to note that the
simulated internal passivity/losslessness must be retained
when internal filter parameters are parasitically perturbed
from their nominal values.
In the early years, the inductors and capacitors within LC
ladder filters were implemented using coils and condensers,
respectively, and could not be manufactured to the level of
precision that is achievalble today. However, the attenuation
responses of those early LC ladder filters did not show high
sensitivity with respect to the LC component values and the
filters performed surprisingly well in practice. The theoretical
explanation for this remarkable property, which may be explained in terms of the first-order sensitivity property, has

(2)

where Pmax E2 /4R1 is the maximum power available from

the voltage source and P2 V22 /R2 is the power delivered to
the load resistor. Because a reactance two-port is lossless and
therefore passive, we have P2 Pmax and therefore 0. Let
x be any internal component value such as an inductance or
capacitance inside the reactance two-port. If for a particular
value of x, say x0, we have 0 at a certain frequency 0,
the attenuation (0, x), which is a function of x with a fixed
parameter 0, has a minimum at x x0. This leads to (0,
x)/x 0 for x x0, and in general, /x 0 for 0 and
/x 0 for 0. This shows that, for a well-designed
lossless LC filter network (i.e., having an attenuation response with the maximum number of attenuation zeros at
real frequencies in the passband etc.), the first-order sensitivity of the attenuation response with respect to any LC component value is small everywhere in the passband; furthermore,
the closer the attenuation response is to its limiting value of
zero, the smaller the sensitivity of the attenuation to perturbations of x. Furthermore, this low passband-sensitivity property can be shown to lead to excellent noise immunity and
superior dynamic range.
In addition to the above-mentioned property of low sensitivity in the passband, LC ladder filters also exhibit superior
low-sensitivity performance in the stopband, compared with
many other lossless filter structures, such as lattice structures. Although the above lossless argument establishes the
low passband-sensitivity property, it does not apply to the
stopband; in fact, the low stopband sensitivity is a result of
the unique ladder topology, as explained in the following.
Let us consider the filter network in Fig. 1(a). In the passband, the transmitted power P2 closely approximates the maximum available power Pmax, and P2 indeed equals Pmax at the
attenuation zeros. This means that the input impedance Zin
equals R1 at those zeros. In the stopband, the attenuation
poles are attributed, in a one-to-one correspondence, to the
reactance poles in the series branches and susceptance poles
in the shunt branches. These poles disconnect the series
branches and short-circuit the shunt branches, respectively.
Therefore, the location of each attenuation pole is independently determined by a particular series reactance or shunt
susceptance. Furthermore, because the series reactance and
the shunt susceptance are usually either a single inductor/
capacitor or a simple resonant circuit, the reactance/susceptance and thus the locations of attenuation poles are easily
tuned. Furthermore, the deviation of poles with respect to
their ideal locations, due to perturbations of LC component
values, is small if the change of the component values is

LADDER FILTERS

small. In general, the series/shunt reactances/susceptances

are implemented using the Foster canonical forms, which
guarantee that the reactance/susceptance poles are independent of each other and are attributed to either a single
inductor/capacitor or to a single second-order resonant circuits. Therefore, the sensitivity of the locations of attenuation
poles with respect to changes of component values is low for
LC ladder filters. This leads to the low stopband sensitivity
for LC ladder filters, because the attenuation response in the
stopband is mainly determined by the number and the locations of attenuation poles.
The low stopband sensitivity of LC ladder filters is superior to that of other types of LC filters, such as LC lattice
filters. In LC lattice filters, the attenuation poles are achieved
by signal cancellation of two or more transmission paths,
causing the above-mentioned superior stopband sensitivity
property to be lost. As a result of this relatively poor stopband
sensitivity performance, classical LC lattice filters are used in
special cases where the problem can be contained. For example, modern digital techniques have revitalized LC lattice filter structures, because the high stopband-sensitivity may be
alleviated by means of appropriate discrete numerical optimization techniques.
Classical LC ladder filters are implemented by using discrete inductors and capacitors, usually mounted on printed
circuit boards. Continued advances in materials research
have led to small and inexpensive LC components of very
high quality. Filter designers can refer to practical guides,
such as Ref. 5, in order to select the LC values and parts and
to find information on testing and manufacturing.
Modern Implementations of Ladder Filters
The invention of transistors in the 1950s has played an important role in the integrated circuit revolution and, in particular, has fueled the pervasive growth of the modern computer
and telecommunications industries. In spite of the high demand for filter systems in microelectronic form and the abovementioned attractive properties of classical LC ladder filters,
the integration of the inductor has generally proven to be impractical, thereby preventing the application of classical LC
filters in microelectronic forms. This limitation of classical
LC filters led to much research on the topic of inductorless
filters.
In the 1950s, Yanagisawa and Linvill pioneered the field
of RC-active filters and showed that passive RC elements and
active controlled voltage or current sources could be combined
to realize general filter transfer functions. Sallen and Key
proposed a single-amplifier configuration for realizing secondorder transfer functions, which were very useful for implementing low-order low-sensitivity filter transfer functions.
Nevertheless, these early RC-active filters proved to be overly
sensitive with respect to changes of component values for applications involving high order and highly selective transfer
functions. Moreover, they also required impractically large
spreads of component values and had a tendency to be unstable due to parasitics.
In the 1960s, the availability of high-performance microelectronic operational amplifiers (op-amps) allowed single opamp RC-active filters to be used in many applications. In the
1970s and 1980s, the cost of op-amps declined dramatically
whereas the precision RC elements, as required by this type

185

of RC-active filters, remained expensive, thereby lending significant advantage to multiple-amplifier filter implementations that allowed low-cost RC elements to be used. The RCactive filters that are based on simulating classical LC ladder
filters possess this very property and thus have been rapidly
developed.
There are two basic LC ladder simulation techniques. One
technique is based on simulating the LC ladder signal flow
graphs (SFG) and is referred to as the operational simulation
technique. The other is based on simulating the inductors in
the LC ladders and is referred to as the component simulation
technique. The inductor simulation technique is best explained by using the concept of the two-port gyrator, which
was originally proposed by Tellegen in 1948 and led to the
invention of active generalized impedance converters (GIC) by
Riordan (6) and Antoniou. An alternative inductor simulation
technique is to use the so-called frequency-dependent negative resistance (FDNR) elements, which were invented by
Bruton. These methods are discussed later in this article,
along with other modern ladder filter implementations. In
Ref. 7, a historical review of the development of RC-active
filters and a large number of references are listed.
In the 1970s, the pervasive MOS technology offered new
opportunities for making microelectronic active ladder filters
because low-power amplifiers and highly accurate capacitor
ratios could be made at very low cost and at very high density
by using the same fabrication process. These technical advances led to the development of SC filters, where capacitors
and switches were initially used to replace the resistors in
RC-active filter configurations.
In general, the voltages in SC filters are ideally constant
except at the instants of time when switches are caused to
open or close. Thus, the voltages waveforms are sampled-data
staircase waveforms that are related to each other by the
same family of linear difference equations that describe the
relationships between the variables of digital filters. A historical review of the development of SC filters is given in Refs.
810.
While SC filters are analog sampled data systems, digital
filters are quantized sampled data systems. The widely
spread industrial applications of digital filters have been enabled by the invention of CMOS VLSI technology in the
1980s. Digital filters have the advantage over analog filters
that they do not suffer from manufacturing and temperature
variations and aging effects. This advantage of digital filters
provides an opportunity to exploit the higher-order low-passband-sensitivity property of classical LC filters (11) when designing digital filters to simulate classical lossless LC filters,
such as wave digital filters (WDF) which were invented by
Fettweis and lossless discrete integrator/differentiator (LDI/
LDD) digital filters which were invented by Bruton. A technical review of digital filters and a large number of references
can be found in Ref. 12.
The benefits of using high-order low passband sensitivity
are considerably greater than might be expected from the
first-order sensitivity property discussed in the previous section. To show this, let us consider the attenuation response of
the lossless filter (, x0) again, where x0 indicates any original digital filter coefficient value. If x0 changes to x0 x in
such a way that the losslessness is maintained, (, x0
x) 0 still holds for the resulting attenuation response. In
this case, the size of x does not have to be small and the

186

LADDER FILTERS

attenuation minima can only shift in the same upward direction [see Fig. 1(b)]. The resulting attenuation distortion is
predominantly determined by the differences of these shifts
and is therefore smaller, possibly substantially smaller, than
the individual changes of the minima. Because, once the filter
coefficients are determined, the attenuation responses of
digital filters do not change due to manufacturing process,
temperature, and aging, this higher-order low passband sensitivity can be used for the discrete optimization of filter coefficients to obtain extremely simple-valued coefficients, thus
minimizing the hardware complexity of digital filter implementations.
High-order direct-form recursive digital filters suffer from
poor sensitivity performance, limit cycle, and parasitic oscillatory problems, due to underflow/overflow and high noise distortion. However, due to the internal passivity property of
classical LC filters, digital filters that are properly derived
from LC ladder filters, such as WDFs, can be made free from
parasitic oscillations even under extremely difficult looped
conditions. It is noted that in order to obtain superior performance, passivity or losslessness must be maintained under
quantized conditions and considerable design effort may be
required to ensure that this is achieved.
The above-mentioned benefits of digital filters were often
offset by the requirement for relatively expensive analog-todigital and digital-to-analog converters (ADC and DAC) and
by the relatively high cost of digital filters. However, during
the 1990s, the advent of deep-submicron CMOS VLSI technology has virtually reversed the cost equation in favor of digital
filters. Moreover, the transition of the computer and telecommunications industries to entirely digital systems has eliminated the need for local ADCs and DACs and, in many cases,
has dictated the use of digital filters. The use of analog continuous-time filters, such as LC, RC-active, and SC filters,
may soon be restricted to ultrahigh-frequency applications
where sampling and digitization are not economical or feasible. For example, front-end analog radio-frequency (RF) filters in wireless systems are typically implemented as analog
circuits because small low-valued RF inductors may be made
at low cost. Furthermore, RF resonator-type ladder filters
such as surface acoustic wave (SAW) ladder filters find wide
applications in wireless systems. In this type of filters, the
ladder branches consist of (SAW) resonators, and the corresponding filter design procedure has many similarities to the
image parameter method.

ON THE DESIGN OF PASSIVE LC LADDER FILTERS

The design of modern microelectronic ladder filters is based
on the same underlying approximation theory and ladder synthesis methods that are used to design classical LC ladder
filters. The values of ladder elements for prototype low-pass
filters are tabulated in design handbooks (13,14). High-pass,
band-pass, and band-stop filters are often derived from prototype low-pass filters using frequency transformation techniques. Alternatively, the filter approximation and synthesis
can also be performed by filter design software packages. In
this section we will briefly discuss the underlining principles
of filter approximation theory and the ladder synthesis techniques that lead to optimal LC ladder filter structures. The
interested readers may consult related articles in this ency-

clopedia and Refs. 1519 for a more comprehensive treatment

of this topic.
The General Design Procedure
There are two steps in designing a filter. The first step is to
find a transfer function having a frequency response that satisfies the specified attenuation and/or phase response requirements. The second step is to synthesize a filter network that
realizes this transfer function. In the case of LC ladder filters,
the filter transfer function is realized using an LC ladder network. In the following, we review the method of determining
the filter transfer function and the ladder synthesis technique
for LC filters.
The double-resistively terminated filter network N in Fig.
1(a) possesses transmittance S21 as defined in Eq. (1) and reflectance (or the reflection coefficient) S11, which is defined as
S11 = (2V1 E)/E
For LC ladder filters, the embedded network N is lossless.
Therefore, no power is dissipated in the network N. Thus, the
two transfer functions S11 and S21 are complementary, implying that
|S11 ( j)|2 + |S21 ( j)|2 = 1

(3)

By introducing a new variable C S11 /S21 and by taking Eq.

(3) into account, the attenuation response given by Eq. (2) can
be rewritten as
a() = 10 log(1/|S21 ( )|2 ) = 10 log(1 + |C( j)|2 )

(4)

The function C( j) is the so-called characteristic function

having zeros and poles that correspond with those of the attenuation response (). This one-to-one correspondence of
zeros and poles between the characteristic function and the
attenuation response makes the characteristic function an
important and sufficient choice for approximating the filter
transfer function. It can be shown (18) that for lossless filters
the transmittance S21 and the reflectance S11 are rational
functions in the complex frequency s (s j) and that
S21 and S11 have the common denominator polynomial g,
where g is a Hurwitz polynomial. Let
S21 = f /g

(5a)

S11 = h/g

(5b)

The characteristic function C becomes

C = h/ f

(6)

which is also a rational function. It can be shown from Eqs.

(3) and (5) that the following fundamentally important relation holds between f, h, and g for the entire s domain:
f (s) f (s) + h(s)h(s) = g(s)g(s)

(7)

Furthermore, for LC filters, f(s) is either an even or an odd

function of s because of the reciprocity property of embedded
LC two-ports. Now, the transfer function approximation problem can be formulated so as to find the rational functions
h( j), f( j) and thereby C( j)2 h( j)h(j)/f( j)f(j)

LADDER FILTERS

such that the attenuation response (), as defined by Eq.

(4), satisfies the specified attenuation requirements. The fact
that g(s) is a Hurwitz polynomial, having its zeros in the left
half of the s plane, allows itself to be obtained by solving the
equation f(s)f(s) h(s)h(s) 0. Subsequently, the functions S21 and S11 are fully determined. Note that we have
omitted discussion of phase responses because the phase response requirements for a ladder filter are usually satisfied by
cascading an equalizing all-pass filter. Nevertheless, special
ladder filters may be designed to satisfy the phase response
requirements, such as the Thomson filter that is discussed in
the following.
The transfer function approximation problem, which is the
determination of the characteristic function C, was solved for
low-pass filters by Butterworth, Cauer, Thomson, and others
in the early years of filter design. In the next section, we discuss design examples for low-pass prototype filters where it is
understood that simple frequency transformations are used to
obtain high-pass, band-pass, and band-stop filters from lowpass prototype filters.
The synthesis of the double-resistively terminated two-port
N in Fig. 1(a) is facilitated by the LC one-port synthesis techniques as developed by Foster and Cauer. A reactance function, which is obtained as the input immitance of an LC
one-port, can always be realized in the Foster and Cauer canonical forms. The first and second Foster canonical forms
are based on the partial fraction expansion of the reactance
function, and the first and second Cauer canonical forms are
based on the continued fraction expansion. It can be shown
that a reactance function can be written in the following partial fraction form as the impedance function
Z(s) = B s + B0 /s +

n

2Bi s/(s2 + i2 )

i=1

or admittance function
Y(s) = D s + D0 /s +

n

2Di s/(s2 + i2 )

i=1

leading directly to the first and second Foster canonical forms

as shown in Fig. 2(a). Similarly, the reactance function can

(a)

(b)
Figure 2. (a) The first Foster canonical form. (b) The first Cauer
canonical form. The second canonical form is the dual network to the
first canonical form. The Foster canonical forms implement each
reactance/susceptance pole by a separate second-order resonant circuit. The Cauer canonical forms have a ladder structure.

187

also be written as continued fractions

Z(s) = L1 s +

(8a)

C2 s +
L3 s +

1
C4 s +

1
..
.

or

Z(s) =

1
1
+

C1 s
1
1
+
L2 s
1
1
+

1
1
C3 s
+

L4 s
..
.

(8b)

leading directly to the first and second Cauer canonical forms

shown in Fig. 2(b).
The Cauer canonical forms are reactance one-ports having
a ladder structure. The continued fraction expansion technique is especially useful for synthesizing resistively terminated two-port ladder network. It can be shown that the reflectance S11 can be written as
S11 = (Zin R1 )/(Zin + R1 )

(9a)

so that Zin can be written as

Zin = R1 (1 + S11 )/(1 S11 )

(9b)

However, Zin is an impedance function and thus a rational

positive real function which, according to Darlingtons theory,
can always be synthesized as a lossless two-port network terminated by a resistive load.
In general, the resulting two-port network involves the socalled Brune section, which is a second-order two-port network containing coupled inductors or ideal transformers, and
thus strictly does not have the LC ladder structure according
to our definition. However, in most cases, an LC ladder structure can be found for the input impedance Zin that results
from the reflectance S11 of a practical low-pass filter. This is
especially true if the resulting two-port is allowed to be a noncanonical network. In fact, the continued fraction expansion
technique, illustrated by Eq. (8), can be applied to Zin in order
to realize an LC ladder two-port that is terminated by a
resistor.
The continued fraction expansion technique is also referred to as the pole removal technique because it removes
the attenuation poles of the filter one by one during the
course of the fractional expansion. For low-pass filters, having
multiple attenuation poles at infinity, each step in fractional
expansion removes a full attenuation pole at infinity, resulting in a canonical implementation. For low-pass filters
that have attenuation poles located at finite frequencies, the
removal of a finite frequency pole has to be accompanied by a
partial removal of an infinity pole, in order to avoid the Brune
section and to obtain a ladder structure. Because of this partial pole removal, the resulting LC ladder two-port is a noncanonical network. We will consider examples for LC ladder
synthesis in the following section.

188

LADDER FILTERS

Low-Pass Prototype Filters

The most widely used low-pass prototype filters are the Butterworth, (inverse) Chebyshev, elliptic, and Thomson filters.
Each of these filters has particular characteristics that may
be preferred for a given application. We shall briefly discuss
each type of these filters.

the passband, the source terminating resistor, and the load

terminating resistor (where possible) are normalized to unity.
The LC element formula for the nth-order minimum inductor
Butterworth ladder filter is given by


Cm (m is odd)
= 2 1/n sin 2m1
Lm (m is even)

and m = 1, 2, . . ., n

Butterworth Filters. The nth order Butterworth low-pass

filter has the following characteristic function:
Chebyshev Filters. The characteristic function of the Chebyshev filter is a Chebyshev polynomial, which can be written
in a compact form as follows:

C(s) = (s/p )n
where p is the passband edge frequency and is the passband ripple factor related to the maximum attenuation in the
passband by pmax 10 log(1 2). The first n 1 derivatives
of the characteristic function are zero at the origin. For this
reason, the attenuation response has the special characteristic that it is maximally flat at the frequency origin. The Butterworth filter has all of its attenuation zeros and poles at the
frequencies zero or infinity. This leads to a less steep transition region from the passband to the stopband and results in
a high filter order that is required to satisfy the attenuation
requirements in both the passband and stopband. The polynomial characteristic function of the Butterworth filter leads to
a transfer function having a constant numerator. This type of
filters is called all-pole low-pass filters. For the Butterworth
filter, Eq. (7) can be solved analytically. Thus, S21 and S11 can
be written in analytical forms. In particular,

S11 = R1

( 1/n s/p )n

n

ai ( 1/n s/p )i

i=0

where the coefficients a0 1 and ai (i 1, 2, . . ., n) are

given by

ai =

i

cos k1
sin k
=1

with k = k/2n

According to Eq. (9b), the input impedance function Zin can be

readily determined and then expanded into a continued fraction at infinity according to the first Cauer canonical form
(8a). The resulting LC ladder filter is illustrated in Fig. 3,
where the minimum inductor structure is selected. It is noted
that the minimum capacitor structure is available as the dual
network to the minimum inductor structure. The LC values
of the resulting ladder filter can be determined either according to the continued fraction expansion of Eq. (8a) or by
using explicit formulas, which are available for all-pole filters
(15). Such formulas are especially simple for frequency and
impedance normalized filters, for which the edge frequency of


C(/p ) = Tn (/p ) = 

L2


h=
C1 =
C2m1 L2m =
C2m+1 L2m =

Ln =

Ln

Ln2

+
E

C1

C3

Cn3

Cn1

cosh(n cosh

for |/p | 1

/p ) for |/p | 1

where Tn() is the nth-order Chebyshev polynomial. Therefore, the Chebyshev filter is an all-pole low-pass filter, having
all attenuation poles at infinity. In the passband, however,
the Chebyshev filter has attenuation zeros at the finite frequencies and the attenuation function has an equiripple form.
Because of the optimally distributed attenuation zeros in the
passband, the Chebyshev filter has a steeper transition region
than the Butterworth filter so that the Chebyshev filter can
satisfy the same attenuation requirements with a much lower
filter order than the Butterworth filter. For example, an
eighth-order Chebyshev filter may satisfy the practical attenuation requirements that would require a 20th-order Butterworth filter. However, it is also noted that because of the maximum flat property, Butterworth filters have a much
smoother phase/delay response than Chebyshev filters, leading to lower time-domain distortion of passband signals.
The LC ladder synthesis of Chebyshev filters can be
achieved in the same way as for Butterworth filters and the
synthesized two-ports also have the same ladder structures
as illustrated in Fig. 3. The explicit formulas for LC ladder
component values of an nth-order Chebyshev filter are given
with help of two intermediate constants h and (15) as follows:

Cn =
R1

cos(n cos1 /p )


1/2 1/n
1
1
+ 1+ 2





1
and = h
h

4 sin 1
with m = m/2n
R1
16 sin 4m3 sin 4m1
,
m = 1, 2, . . ., n/2
2 + 4 sin2 4m2
16 sin 4m1 sin 4m+1
,
m = 1, 2, . . ., n/2
2 + 4 sin2 4m
4 sin 1
for odd n
R2
4R2 sin 1
for even n

R2

Figure 3. Minimum inductor ladder structure for all-pole filters. The

number of inductors is equal to (when Ln 0) or less than (when
Ln 0 and Cn1 0) the number of capacitors.

Inverse Chebyshev Filters. The inverse Chebyshev filters

have the reverse passband and stopband behavior with respect to the Chebyshev filters. The passband of the inverse
Chebyshev filter is maximum flat at the origin and the stop-

LADDER FILTERS

band has the equiripple form. The characteristic function for

inverse Chebyshev filters can be written as
C(s) = 1/Tn (p /)
where Tn is the nth Chebyshev polynomial. For the LC ladder
synthesis of the inverse Chebyshev filter, which has finitefrequency attenuation poles, the continued fraction expansion
technique can be generalized by allowing the removal of simple resonant circuit branches that have resonant frequencies
in one-to-one correspondence with the finite frequencies of attenuation poles. However, this poses a potential problem such
that, during the generalized continued fraction expansion, the
removal of a finite frequency pole requires shifting a zero of
the remaining input impedance/admittance to the same frequency as the attenuation pole that is to be removed. This socalled zero-shifting process can introduce a negative LC element value that can be absorbed into a Brune section after
the pole removal. Fortunately, there is a way around this
problem of physically unrealizable negative LC elements if
the filter has an attenuation pole at infinity, such as the oddorder inverse Chebyshev filter. In this case, the zero-shifting
can be achieved by the so-called partial removal of the infinity
attenuation pole. The resulting LC ladder two-port is no
longer a canonical network and no longer contains Brune sections.
A fifth-order inverse Chebyshev filter can have an implementation such as that shown in Fig. 1(a), where the two lefthand shunt capacitors only partially remove the attenuation
pole at infinity and the right-hand shunt capacitor finally removes this pole completely. For the even-order inverse Chebyshev filters, which do not have attenuation poles at infinity,
a frequency transformation, which will be discussed in the
next section, should be performed before the synthesis process
in order to introduce an attenuation pole at infinity.
Because LC ladder implementations of inverse Chebyshev
filters are not canonical networks, they require a larger number of LC elements than do Chebyshev filters of the same order. Furthermore, because the transition region of both types
of filters are similar with regard to their transition-band
steepness, the Chebyshev filter is usually preferred to its inverse version. However, the inverse Chebyshev filter has a
better phase/delay response due to its maximally flat passband. Therefore, it may be preferred if a smooth delay response is required.
Elliptic Filters. The elliptic filter has equiripple attenuation
in both the passband and stopband. It provides the lowest
filter order satisfying a given attenuation requirement. For
comparison, a sixth-order elliptic filter can satisfy the same
attenuation requirement that would require an eighth-order
Chebyshev filter. The characteristic function for the nth-order
elliptic filter is a Chebyshev rational function given by


m s2 + 2

0,2i

2 + 2
s
,2i
i=0
C(s) = d 
m s2 + 2

0,2i1

2
s2 + ,2i1
i=0

for n = 2m + 1

189

, j are calculated by means of the elliptic functions, which

are discussed in many filter design books (19). The attenuation zeros and poles of an elliptic characteristic function are
located symmetrically around a frequency t in the transition
band such that 0, j, j t2. This frequency t is a measure of
the selectivity of the filter. The synthesis process for elliptic
filters is very similar to that for inverse Chebyshev filters. In
particular, the LC ladder network in Fig. 1(a) can be used to
implement a fifth-order elliptic filter.
Thomson Filters. All of the above filter types are designed
to meet specified attenuation requirements. The Thomson filter, on the other hand, achieves maximally flat group delay
by maintaining the first n derivatives of the group delay to be
zero at the frequency origin. The transfer function of Thomson filters is an all-pole function with the Bessel polynomial
as the denominator:
S21 (s) =

Bn (0)
Bn (s)

where
Bn (s) =

n


(2n 1)!si
2ni i!(n i)!
i=0

The normalized group delay of the Thomson filter approximates unity in the neighborhood of the frequency origin. The
higher the filter order n, the wider the frequency band over
which a flat delay response is achieved. The time-domain responses of the Thomson filter are very smooth. For example,
the step response has no overshoot. The synthesis of Thomson
filters is similar to that for other all-pole filters.
It is noted that all the prototype filters discussed so far
allow a closed-form solution for the filter approximation problem. The filter approximation of more general filter types such
as filters with nonequiripple attenuation/phase behavior may
be solved in a satisfactory manner by using computer-aided
numerical methods.
Frequency Transformations
In the previous sections, we discussed various types of lowpass prototype filters. The approximation solutions and the
filter structures of these prototype filters can also be used to
obtain other filter types by means of appropriate frequency
transformations.
Frequency Scaling. Low-pass prototype designs are usually
obtained for normalized case so that the passband edge frequency is normalized to unity. This is especially the case
when the explicit design formulas are used. To denormalize
the passband edge to a specified value p, the following frequency transformation can be used:
p = s/p

for n = 2m

where d is a scaling constant such that the passband ripple

factor is once again and the attenuation zeros 0, j and poles

where p is the complex frequency before transformation. The

filter structure does not change after the denormalization, but
the LC element values of a given filter structure are scaled accordingly.

190

LADDER FILTERS

Low-Pass to High-Pass Transformation. A high-pass filter can

be obtained the following frequency transformation:
p = p /s
which results in replacing each inductor with a capacitor and
vice versa.
Low-Pass to Bandpass Transformation. The specification of a
bandpass filter is given by the two passband edges pl and
ph (pl ph) and the two stopband edges sl and sh (sl
sh). The bandpass characteristic can be thought of as a combination of a low-pass and a high-pass characteristic such as
p=

pl ph /(ph pl )
s
+
(ph pl )
s

Low-Pass to Band-stop Transformation. The band-stop filter

can be obtained from a bandpass filter by interchanging its
passband with its stopband frequency location. Therefore, the
band-stop characteristic can be obtained by performing a
bandpass transformation on a high-pass filter instead of a
low-pass filter, resulting in the low-pass to band-stop transformation

p=

pl ph/(ph pl )
s
+
(ph pl )
s

s2 = p2

p2

p2

02

p2 + 02
2
p2 +

(10)

The stopband edges sl and sh can be calculated using Eq.

(10) by setting p equal to the low-pass prototype stopband
edge. Because Eq. (10) is a second-order equation in s, it determines both stopband edges sl and sh. Therefore, these
stopband edges are not independent of each other but related
by plph slsh, resulting in a frequency-domain symmetrical bandpass filter. According to Eq. (10), a bandpass filter
structure is obtained from its low-pass prototype by replacing
each inductor with a series resonant circuit and each capacitor with a parallel resonant circuit.
A minor problem can arise from the direct application of
Eq. (10) to a parallel or series resonant circuit, such as the
parallel resonant circuit in Fig. 1(a), when transforming an
inverse Chebyshev or an Elliptic low-pass filter into the corresponding band-pass filter. The transformed resonant circuit,
which is a combination of a parallel and a series resonant
circuits, does not directly relate to the anticipated attenuation
poles, resulting in a less favorable stopband sensitivity. This
problem can be resolved by using network transformations
such that a parallel resonant circuit transforms into two parallel resonant circuits in series while a series resonant circuit
transforms into two series resonant circuits in parallel.

characteristic function that is not realizable as an LC ladder

two-port into a realizable one.
The even-order elliptic filter has the property that its attenuation has a nonzero value at the origin and a finite value
at infinity. However, a practical LC ladder implementation
requires an attenuation pole at infinity. Furthermore, it is
often desirable to have the zero attenuation at the dc level,
which also allows for a balanced load resistance equal to the
source resistance. In order to achieve these requirements, the
following transformation can be applied to the characteristic
function before the synthesis process:

1

Because of the similarity between the bandpass and bandstop transformations, the properties discussed above for the
band-pass transformation can be easily rewritten for the
band-stop transformation.
Other Frequency Transformations. The frequency transformations discussed so far are reactance transformations; that
is, they transform a reactance into another reactance.
Whereas reactance transformations are very useful, nonreactance transformations are often required to transform a

where 0, p, and are respective frequencies for the first

passband attenuation zero, the passband edge, and the last
finite-frequency attenuation pole. This transformation transforms the passband attenuation zero at 0 to the origin, the
stopband attenuation pole at to infinity, while retaining
the passband edge at p. In general, the transformed filter
has a poorer performance (especially in the transition region)
than the original elliptic filter, because the latter is the optimum solution. However, the transformed filter still has a better performance than an original elliptic filter of lower order.
The even-order Chebyshev filters do not have an attenuation zero at the origin while having attenuation poles at infinity. The above transformation can be modified to just move
the attenuation zero at 0 to the origin:

s2 =

p2
p2 02

( p2 + 02 )

Similarly, for even-order inverse Chebyshev filters, the attenuation pole at can be moved to infinity by the following
transformation:
2
s2 = (
p2 )

p2

p2
2
+

ACTIVE INTEGRATED CIRCUIT IMPLEMENTATIONS

OF LC LADDER FILTERS
In the following sections, we discuss various techniques for
the design of RC-active filters that are derived from LC ladder filters. However, the design details and parasitic effects
(primarily due to the finite gain and bandwidth of the opamps) are not discussed. Reference material on these topics
can be found in the related articles in this encyclopedia and
in Refs. 2024.
RC-Active Ladder Filters Based on Simulating Inductors
The RC-active filters in this category can be readily obtained
by replacing inductors with selected active circuits. Three basic types of active circuits are employed and discussed in the
following.
Gyrators. A classical approach to the replacement of inductors with active circuits is to use a two-port gyrator termi-

LADDER FILTERS

191

or
R
C

Zin2 =

Gyrator

Z2 Z4
Z
Z1 Z3 ld1

(11b)

Therefore, choosing
Z 1 = R1 ,

Z 2 = R2 ,

Z 3 = R3 ,

Z4 = 1/sC4 ,

(a)
R1

R2

(b)
Figure 4. (a) Grounded-inductor simulation as may be used in highpass filters. (b) Floating-inductor simulation as may be used in lowpass filters. Both inductor simulations use a gyrator, which is realized
by an active circuit.

leads to a simulated grounded inductance at port 1 with L

R1R3C4R5 /R2.
According to Eq. (11a), Z2 could be chosen as a capacitor
instead of Z4. However, for practical reasons the choice in Eq.
(12) has a better performance at high frequencies.
In general, we can define a conversion factor K(s)
Z1(s)Z3(s)/Z2(s)Z4(s), where Zi(s) can be any impedance functions. Thus, the GIC can perform more general impedance
conversion than the inductance simulation. In particular, if
port 1 is terminated in a capacitor Cld1, the input impedance
at port 2 is given by
Zin2 =

Zin = R2 /Zld
where R is the gyration resistance inherent to the gyrator
circuit. Therefore, the inductance seen from port 1 is given by
L R2C.
There are two types of topological situations involving the
use of inductors, namely grounded inductors and floating inductors, as shown in Figs. 4(a) and 4(b), respectively. To simulate a grounded inductor, a one-port grounded gyrator may
be employed; and to simulate a floating inductor, a two-port
grounded gyrator is needed. Note that because the active gyrator circuits involve complicated active circuitry, minimum
inductor implementations should be chosen in order to minimize the number of required gyrators.
In general, passive implementations of gyrators are not
available for many applications. In the RC-active filter application, small-signal active implementations of gyrators have
been specifically designed for converting a capacitor to an inductor (2527). When the gyrator is used as an impedance
converter, it may be considered as a special case of the generalized impedance converter (GIC), which is discussed in the
following.
Generalized Impedance Converters. The GIC is a two-port
circuit, usually employing two op-amps as shown in Fig. 5(a),
where the impedances Zi are usually either a resistor or a
capacitor. The impedance relations between the input and
terminating impedances of a GIC are given by
Zin1 =

Z1 Z3
Z
Z2 Z4 ld2

(11a)

R2
R1 R3C4Cld1 s2

which is a so-called frequency-dependent negative resistance

(FDNR). Applications of FDNRs are discussed in the next
subsection.
The GIC is used in a very similar way to that of a gyrator.
In particular, the gyrator simulating a grounded inductor, as
shown in Fig. 4(a), can be replaced with a GIC given by Eq.
(12). The GICs can also be used to simulate floating inductors
as shown in Fig. 5(b), which was first proposed by GorskiPopiel. It is noted that, unlike the gyrator, the GICs with the

K(s)
Z1

Z2
Z3

K(s) = Z1 Z3 / Z2 Z4

Z4

nated at one end with a capacitor C as shown in Fig. 4(a). In

general, the relationship between the input impedance at
port 1, Zin, and the terminating impedance, Zld, at port 2 of a
gyrator is given by

and Zld1 = R5
(12)

1
(a)
ks

R = L/k

ks

(b)
Figure 5. (a) Active implementation of GIC and its corresponding
symbol. K(s) is the conversion factor. (b) Floating-inductor simulation
using GIC. This simulation uses a resistor connecting two GICs. The
required capacitors are hidden in the GICs.

192

LADDER FILTERS

and a capacitor according to

Ld1
L1

L3

L5

Vout =
+
E

R1/s

L2

L4

FDNR
1/s2C2

FDNR
1/s2C4

R2/s

Ld2

Figure 6. A fifth-order RC-active filter using FDNRs. The dashed

resistors Ld1 and Ld2 are the add-on discharging resistors.

conversion factor k s (k is a constant) convert a floating inductor into a floating resistor whereas the required capacitors
are embedded in the GICs.
Frequency-Dependent Negative Resistors. All of the above
RC-active filters use minimum inductor implementations.
The minimum capacitor implementations can also be employed in an effective way if the concept of the FDNR is used.
The dimensionless filter transfer function of any LCR network is unaltered if each branch is scaled by a uniform function. Thus, impedance scaling all branches by 1/s converts all
inductors to resistors, all resistors to capacitors, and all capacitors to FDNR elements. An example of a RC-active filter
using FDNRs is given in Fig. 6, where the dual network to
the fifth-order filter in Fig. 1(a) is 1/s impedance-scaled. The
resulting FDNRs can be implemented using GICs. It is noted
that the filter network in Fig. 6 is no longer resistively terminated, which may cause a practical dc bias problem if the
source and/or load are not resistively coupled to ground. This
termination problem can be resolved by inserting two unitygain amplifiers between the source and the load, and the bias
current problem can be compensated for by connecting two
discharging resistors across the capacitors, as shown in Fig.
6. The values of these resistors are suggested to be chosen
such that the filter attenuation at the dc level remains equal
to unity, that is,

1
I
sC in

so that all the reactive components are represented as integrators within the SFG. The terminating resistors are represented by constant-valued analog multipliers within the SFG.
The physical interconnections of the LCR elements constrain
the voltage and current signals to obey Kirchhoff s laws and
are represented in the SFG by appropriate combinations of
analog inverters and adders. An example of an SFG for the
third-order low-pass filter in Fig. 3 (where n 3) is given in
Fig. 7(a), which is often referred to as the leapfrog structure.
It is noted that all inductors are simulated by noninverting
integrators, and all capacitors are by inverting integrators so
that all signals entering an adder have the same positive
sign. Furthermore, because all summations are performed immediately prior to integration, summation can be easily
achieved in the RC-active circuit by current-summing at the
virtual ground input terminals of the integrators op-amps.
Thus, no dedicated summing devices are required. In Fig.
7(b), the complete circuit corresponding to the SFG in Fig.
7(a) is given for the selected type of integrator implementations, where the circuit parameters can be determined by

R/R1

R/sL2

R/R1
1/sC1R

R/R2
1/sC3 R
V2

(a)
r1
e

r2

and that the insertion of Ld1 and Ld2 introduces the least distortion of the filter frequency response.

The design and implementation of RC-active filters based on

simulating the voltagecurrent signal flow graphs (SFGs) of
LC ladder prototype structures was proposed by Girling and
Good. An SFG can be derived for any given LC ladder filter,
where for the purpose of implementing RC-active filters, the
SFG should be arranged in such a way that it consists only
of inverting/noninverting integrators, analog multipliers, and
adders. An inductor is represented in the SFG according to
Iout =

1
V
sL in

r1

c1

RC-Active Filters Based on Simulating Ladder SFGs

r5

+
c3

Ld2 = Ld1 + L1 + L2

r6

c2
+
r3

r4

V2

(b)
Figure 7. (a) A third-order leapfrog SFG scaled by a constant R. (b)
The corresponding complete RC-active circuit, where c1r1 C1R1,
c1r2c2r3 C1L2, c2r5c3r4 L2C3, c3r6 C3R2. No dedicated summing
devices are needed.

LADDER FILTERS

comparing the loop gains between the circuit representations

in Figs. 7(a) and 7(b). Note that other types of integrator implementations may be chosen, depending on the frequency
range within which the circuit is intended to operate.
The SFG simulation method is very straightforward and
easy to use, especially when designing band-pass filters. However, it is noted that, when drawing the SFGs for LC ladder
network that contain a circuit of capacitors or a T circuit of
inductors, difficulties arise because two adjacent SFG blocks
have ports with the same orientation facing or leaving each
other. This problem can be solved perfectly by using network
transformations involving Brune sections in the same way as
it has been done for LDI/LDD digital filters (28). By now, it
is evident that the Brune section is a very useful building
block in RC-active and digital filter implementations, although it is, strictly speaking, not a ladder component.
DISCRETE-TIME SC AND DIGITAL IMPLEMENTATIONS
OF LC LADDER FILTERS
Both the SC filter and digital filter are sampled data (discrete-time) systems. The frequency response of a discretetime system is adequately described in the z domain with
z esT, where s is the complex frequency and T is the sampling period. The frequency-domain design methods for SC
filters and for digital filters have many similarities and often
have the same z-domain transfer functions, in spite of the fact
that SC filters are implemented as analog circuits whereas
digital filters employ the digital arithmetic operations of addition, multiplication, and delay and are implemented as computer programs or by dedicated hardware.
The frequency-domain design of discrete-time SC and digital filters can be performed directly in the z domain. However,
high-performance discrete-time filters may be designed by
simulating continuous-time LC ladder filters as discrete-time
filters. This is achieved in a way such that all of the abovementioned favorable stability and sensitivity properties of
LC filters are preserved. The transfer functions of the continuous-time LC ladder filter and its discrete-time counterparts
are related by the bilinear transformation
s = (z 1)/(z + 1)
In the following, we briefly discuss methods for converting
continuous-time LC ladder filters into their discrete-time
counterparts. The design details for SC and digital filter circuit components and the treatment of parasitic and other
nonideal effects are not considered here. Reference material
on these topics can be found in the related articles in this
encyclopedia and in Refs. 11 and 2832.

tween the transfer functions of the continuous-time LC ladder

filter and its discrete-time SC counterpart. An example of SC
resistor circuits is given in Fig. 8(a), which leads to the desired frequency-domain relationship given by the bilinear
transformation.
In many SC filters, the ideal circuit capacitances are not
significantly larger than the parasitic capacitances. In fact,
the latter is around 20% of the former. Therefore, it is extremely critical to only use those SC circuits that are not sensitive to parasitic capacitances. An example of a so-called
stray-insensitive SC resistor circuits is given in Fig. 8(b). This
circuit yields a different frequency transformation than the
bilinear transformation. In order to achieve the desired bilinear transformation using simple SC ladder circuits, a socalled predistortion technique may be used that adds a positive capacitance to one circuit component and subtracts an
equal-valued negative capacitance from another circuit component, along with an impedance-scaling technique (30). It is
noted that a similar technique is also used for LDI/LDD digital filters.
Another alternative approach for designing SC filters is to
directly simulate each inductor and each terminating resistor
in the LC ladder filter. In this method, the interconnections
of capacitors and simulated inductors/resistors are achieved
by the so-called voltage inverter switchs (VIS), which contain
active op-amps. This component simulation method guarantees the bilinear transformation between transfer functions of
the continuous-time LC ladder filter and its discrete-time SC
counterpart, which can be designed insensitive to parasitic
capacitances. Nevertheless, considerable design effort and/or
complicated switching signals may be required to achieve the
low-sensitivity property.
Digital Ladder Filters
In a way that is similar to the SC simulation of LC ladder
filters, there are two alternative approaches for the digital
simulation of LC ladder filters, namely the simulation of each
LCR component and the simulation of the SFG representation.
The component simulation method is achieved using wave
digital filters (WDF) (11), where the circuit components of the
LC ladder filter, such as inductors, capacitors and resistors,
are directly simulated by corresponding digital domain components, such as delay registers and inverters. The parallel
and serial interconnections of these digital components are
facilitated by so-called parallel and serial adapters that contain adders and multipliers. A distinguishable advantage of

ph0

ph1

Switched Capacitor Filters

SC filters that are based on LC ladder filters can be derived
from RC-active filters that are themselves derived from LC
ladder filters, preferably using the SFG simulation technique.
In fact, the resistors in RC-active ladder filters can be simulated by switched capacitors, leading directly to the SC filter.
There is a variety of different SC circuits for simulating the
resistors in RC-active ladder filters. Different SC resistor circuits, which are used to replace resistors in RC-active filters,
may result in different frequency-domain relationships be-

193

ph0

ph1 (ph0)
C

ph1
ph0

ph0 (ph1)

ph1

(a)

(b)

Figure 8. (a) Bilinear SC resistor circuit with two switching phases.

(b) Stray-insensitive SC resistor circuit which can be used to form
inverting or noninverting (switching scheme in parentheses) integrators.

194

LADDER FILTERS

WDFs is that internal passivity is maintained under both infinite and finite wordlength conditions. This leads to the suppression of parasitic oscillations that are caused by overflow
and underflow operations.
The SFG simulation of LC ladder filters employs lossless
digital integrators and/or lossless digital differentiators
(LDIs/LDDs) to replace the corresponding integration/differentiation operations in the continuous-time ladder SFG
(28,31,32), where the continuous-time SFG may first be predistorted and impedance scaled in such a way that delay-free
loops are avoided and all inductors and capacitors are individually and directly realized as discrete-time LDI/LDD elements. Each LDI/LDD element contains a delay register, a
multiplier, and an adder. This SFG simulation approach does
not require any special interconnection components and retains the one-to-one correspondence between the LC ladder
filter parameters and its LDI/LDD digital counterparts. A
distinguishing advantage of LDI/LDD ladder filters is that
all of the state variables of inductor-simulating or capacitorsimulating LDI/LDD elements are independent of each other,
thereby allowing concurrent implementation in parallel arithmetic schemes and flexible scheduling in bit-serial arithmetic
schemes. It is noted that the very useful Brune sections can
be perfectly implemented using the LDI/LDD method.
BIBLIOGRAPHY
1. V. Belevitch, Summary of the history of circuit theory, Proc. IRE,
50 (5): 848855, 1962.
2. S. Darlington, A history of network synthesis and filter theory
for circuits composed of resistors, inductors, and capacitors, IEEE
Trans. Circuits Syst., CAS-31: 313, 1984.
3. A. Fettweis, Filters met willekeurig gekozen dempingspolen en
Tschebyschewkarakteristiek in het doorlaatgebied, Tijdschrift
van het Nederlands Radiogenootschap, 25, sec. 8, no. 56, pp.
337382, 1960.
4. H. J. Orchard, Inductorless filters, Electron. Lett., 2, 224225,
1966.
5. E. Christian, LC Filters: Design, Testing, and Manufacturing, New
York: Wiley, 1983.
6. R. H. S. Riordan, Simulated inductors using differential amplifiers, Electron. Lett., 3 (2): 5051, 1967.
7. M. S. Ghausi, Analog active filters, IEEE Trans. Circuits Syst.,
CAS-31: 1331, 1984.
8. A. Fettweis, Switched-capacitor filters: From early ideas to present possibilities, Proc. IEEE Int. Symp. Circuits Syst., Chicago,
414417, April 1981.
9. G. C. Temes, MOS switched-capacitor filtersHistory and the
state of the art, Proc. Eur. Conf. Circuits Theory Design, Den
Haag, pp. 176185, Aug. 1981.
10. W. K. Jenkins, Observations on the evolution of switched capacitor circuits, IEEE Circuits Syst. Magazine, Centennial Issue, 22
33, 1983.
11. A. Fettweis, Wave digital filters: Theory and practice, Proc. IEEE,
74: 270327, 1986.
12. A. Fettweis, Digital circuits and systems, IEEE Trans. Circuits
Syst., CAS-31, pp. 3148, 1984.
13. R. Saal and W. Entenmann, Handbook of Filter Design, Berlin:
AEG Telefunken, 1979.
14. A. Zverev, Handbook of Filter Synthesis, New York: Wiley, 1967.
15. A. S. Sedra and P. O. Brackett, Filter Theory and Design: Active
and Passive, Champaign, IL: Matrix Publishers Inc., 1978.

16. W. K. Chen, Passive and Active Filters: Theory and Implementations, New York: Wiley, 1986.
17. G. C. Temes and J. W. LaPatra, Circuit Synthesis and Design,
New York: McGraw-Hill, 1977.
18. V. Belevitch, Classical Network Theory, San Francisco: HoldenDay, 1968.
19. R. W. Daniels, Approximation Methods for Electronic Filter Design, New York: McGraw-Hill, 1974.
20. G. C. Temes and S. K. Mitra (eds.), Modern Filter Theory and
Design, New York: Wiley, 1973.
21. G. S. Moschytz, Inductorless filters: A survey. I. Electromechanical filters. II. Linear active and digital filters, IEEE Spectrum, 7
(8): 3036, 1970; 7 (9): 6375, 1970.
22. S. K. Mitra (ed.), Active Inductorless Filters, New York: IEEE
Press, 1971.
23. L. P. Huelsman (ed.), RC-Active Filters: Theory and Application,
Stroudsburg: Dowden, Hutchinson and Ross, 1976.
24. W. E. Heinlein and W. H. Holmes, Active Filters for Integrated
Circuits, London: Prentice-Hall, 1974.
25. B. A. Shenoi, Practical realization of a gyrator circuit and RCgyrator filters, IEEE Trans. Circuit Theory, CT-12: 374380,
1965.
26. W. H. Holmes, S. Gruetzmann, and W. E. Heinlein, Direct-coupled gyrators with floating ports, Electron. Lett., 3 (2): 4647,
1967.
27. D. G. Lampard and G. A. Rigby, Application of a positive immitance inverter in the design of integrated selective filters, Proc.
IEEE, 55: 11011102, 1967.
28. X. Liu and L. T. Bruton, Improved LDI digital filters derived from
analog LC ladder filters, Signal Processing, 46: 147158, 1995.
29. G. S. Moschytz, MOS Switched-Capacitor Filters: Analysis and
Design, New York: IEEE Press, 1984.
30. M. S. Lee, G. C. Temes, C. Chang, and M. G. Ghaderi, Bilinear
switched-capacitor ladder filters, IEEE Trans. Circuits Syst.,
CAS-28: 811822, 1981.
31. L. T. Bruton, Low-sensitivity digital ladder filters, IEEE Trans.
Circuits Syst., CAS-22: 168176, 1975.
32. D. A. Vaughan-Pope and L. T. Bruton, Transfer function synthesis using generalized doubly terminated two-pair network, IEEE
Trans. Circuit Syst., CAS-24: 7988, 1977.

XIAOJIAN LIU
Gennum Corp.

LEONARD T. BRUTON
University of Calgary

LADDER NETWORKS. See LATTICE FILTERS.

LADDER STRUCTURES. See LADDER FILTERS.
LAMPS, FILAMENT. See PHOTOMETRIC LIGHT SOURCES.
LAMPS, INCANDESCENT AND HALOGEN. See FILAMENT LAMPS.

LANGUAGE, CONTEXT-SENSITIVE. See CONTEXTSENSITIVE LANGUAGES.

LANGUAGE IDENTIFICATION. See AUTOMATIC LANGUAGE IDENTIFICATION.

LANGUAGE ISSUES IN INTERNATIONAL COMMUNICATION. See INTERNATIONAL COMMUNICATION.

LANGUAGES. See CONTEXT-SENSITIVE LANGUAGES.
LANGUAGES, AI. See AI LANGUAGES AND PROCESSING.

LAPLACE TRANSFORMS

LANGUAGES, FUNCTIONAL PROGRAMMING.

See FUNCTIONAL PROGRAMMING.

LANS. See ETHERNET; LOCAL AREA NETWORKS.

LAPLACE TRANSFORM. See FOURIER TRANSFORM.

195

LATTICE FILTERS

257

(a)
i1

i2
ya

v1

v2
yb

yc

yd
(b)

u1

ta

tc
y1

y2

tb

td

u2

(c)

LATTICE FILTERS
This article discusses filters of a special topology called lattice
filters which can be very useful for system phase correction.
Here the focus is on the analog lattice described in terms of
admittance, scattering, and transfer scattering matrices. A
synthesis technique based on the constant-resistance method
that yields a cascade realization in terms of degree-one or degree-two real lattices is included. Also included is an example
to illustrate the technique.
DEFINITION
A lattice structure is one of the form of Fig. 1(a). In the case
of analog circuits, it is taken to be the two-port of Fig. 1(b)
with the port variables being voltages and currents, in which
case the branches are typically represented by their one-port
impedances or admittances. When the lattice is a digital lattice, the structure represents a signal flow graph where the
branches are transmittances and the terminal variables are
signal inputs and outputs, as shown in Fig. 1(c). Here we
treat the analog lattice only; a treatment of the digital lattice
can be found in Refs. 13.
ANALOG LATTICE
The analog lattices are most useful for the design of filters
based upon the principle of constant R structures. These are
especially useful for phase correction via all-pass structures

Figure 1. (a) Generic lattice structure. (b) Analog lattice two-port

with v1 and i1 being the input port variables and v2 and i2 the output
port variables. Here ya, yb, yc, and yd represent the one-port admittances of the four branches of the lattice. (c) Digital lattice signal
flow graph. Here the branches are transmittances and the terminal
variables are signal inputs (u1 and u2) and outputs (y1 and y2).

as we now show through the use of symmetrical constant R

lattices (4, Chap. 12; 5, p. 223; 6, Chap. 5).
We assume that the lattice branches are described by the
respective admittances, ya, yb, yc, yd in which case the two-port
admittance matrix Y has symmetry around the main and the
skew diagonals


y
Y = 11
y12

y12
y11


(1)

y11 =

(ya + yb )(yc + yd )
ya + yb + yc + yd

(2)

y12 =

yb yc ya yd
ya + yb + yc + yd

(3)

In the case where the lattice is symmetrical as well about an

horizontal line drawn through its middle, called a symmetrical lattice,
yd = ya

and

yc = yb

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

(4)

258

LATTICE FILTERS

we see by inspection


1 ya + yb
Y =
2 yb ya

yb ya
ya + yb

...
+

(5)

Vin

+
N(1)

V1

N(2)

From Eq. (5) we note that the mutual (off-diagonal) terms can
have zeros in the right half s-plane even when ya and yb may
not. Consequently, the lattice can give nonminimum phase
responses in which case it can be very useful for realizing a
desired phase shift, possibly for phase correction.

N(n) V
2

...

Figure 3. Cascade of n constant-R two-port lattices of the type

shown in Fig. (1b) terminated on an R-ohm resistance at the output
port.

SYNTHESIS BY THE CONSTANT-R LATTICE METHOD

Admittance Matrix
The constant-R lattice is defined by using dual arms. Specifically, writing G 1/R, we obtain
Ryb =

1
 ya yb = G2
Rya

From Eq. (6) we can obtain the lattice arm impedances ya and
yb G2 /ya since Eq. (9) gives

V2
V1
ya = G
V2
1
V1
1+

(6)

(11)

which results in


1 G2 + y2a
YR =
2ya G2 y2a

G2 y2a
G2 + y2a


(7)

The name of this structure results from its beautiful property

that if it is terminated at port 2 on an R-ohm resistor, the
input impedance is an R-ohm resistor, as calculated from the
input admittance

Yin =

det Y + Gy11
=
G + y22

ya yb 
G
=G
ya + yb + 2G

G ya + yb + 2

(8)

and as illustrated in Fig. 2. The transfer voltage ratio is given

by
yb ya
V2
ya G
y21
=
=
=
V1
G + y22
yb + ya + 2G
ya + G

(9)

Also we have
V1 =

Vin
2

(10)

Vin

V1

V2

yb

yb

ya

Re{ya (s)} 0

in

Re(s) > 0

Zin = R

Figure 2. Symmetric analog lattice terminated on an R-ohm resistance at the output port.

(12)

Translated into the voltage transfer function, after some algebra on Eq. (11), this is seen to be equivalent to
 
 V2 
 1
V 

in

Re(s) > 0

(13)

In other words, if the voltage transfer function is rational in

s and bounded in magnitude by 1 in the right-half plane, it is
guaranteed to be synthesized by a passive symmetrical constant-R lattice with an R-ohm termination.
However, this synthesis in one whole piece of V2 /V1 may
require rather complex lattice arms, in which case we can
take advantage of the constant-R property to obtain a cascade
of lattices. Toward this consider Fig. 3, which shows a cascade
of constant-R two-ports loaded in R. As is clear from Fig. 3
we obtain a factorization of the voltage transfer function into
the product of n voltage transfer functions, one for each section:
 
 
 
1 V2
V2
V
V2
=
... 2
Vin
2 V1 N (1) V1 N (2)
V1 N (n)

R
ya

In order for a passive synthesis to proceed, ya must be positive

real, the requirement for which is that ya(s) be analytic in the
right half s-plane, Re(s) 0, and

(14)

In order to synthesize a given realizable voltage transfer function, we can perform a factorization of V2 /V1 into desirably
simple factors and realize each factor by a corresponding constant-R lattice. The factorization can be done by factoring the
given transfer function into its poles and zeros and associating appropriate polezero pairs with the V2 /V1 terms of Eq.
(14). Usually the most desirable factors are obtained by associating the poles and zeros into degree-one or degree-two
real factors.

LATTICE FILTERS

Lossless Synthesis
A particularly interesting case is when the lattice is lossless,
which is expressed by
ya (s) = ya (s)

for a lossless lattice

(15)

from which we see by Eq. (9) that

V2 (s) V2 (s)
=1
V1 (s) V1 (s)

for a lossless lattice

V ( j) 
2

V1 ( j)

Vin

Im(N( j))
Re(N( j))

1
10 F

Example. For R 5, design a cascade of two lattices and

compare with an equivalent single lattice for the all-pass
function

1 s2 3s + 2
Vout (s)
=
Vin (s)
2 s2 + 3s + 2
=

= 2 arctan

R = 5

By placing the zeros of N(s) one can usually obtain a desirable

phase shift. In particular, maximally flat delay can be obtained by choosing N(s) to be a Bessel polynomial (7, p. 151).

(16)

In this lossless case we see that for s j the magnitude of

the voltage transfer function, from port 1 to 2, is unity; the
circuit is all-pass and serves to only introduce phase shift for
phase correction and for the design of constant time-delay
networks (7, pp. 144152). If V2 /V1 is written as the ratio of
a numerator polynomial, N(s), over a denominator polynomial, D(s), then in the all-pass case we have N(s) D(s),
in which case the phase shift becomes twice that of the numerator, which is then

259

1 (s 2)(s 1)
2 (s + 2)(s + 1)

(18)

For the first lattice of a cascade of two, using Eqs. (11) and
(6) with V2 /V1 (s 2)/(s 2), this gives
ya =

s
sG
=
2
10

and yb =

1
2G
=
s
2.5s

(19)

and for the second lattice, with V2 /V1 (s 1)/(s 1), we

obtain


(17)

ya = Gs =

s
5

and yb =

1
G
=
s
5s

(20)

1
5 F

R = 5
2.5H

2.5H

5H

1
10 F

5H

1
5 F
(a)
15
2 H
1
5F

R = 5

Vin

3
H
5

R = 5

3
H
5

3
10 F

3
10 F
1
5 F
15
H
2
(b)

Figure 4. Lossless lattice synthesis of an allpass transfer function of degree two. (a) Synthesis using a cascade of two lattices of degree
1 Arms. (b) Equivalent realization using a single lattice of degree 2 Arms.

260

LATTICE FILTERS

In the case of a single lattice, for V2 /V1 twice the first expression of Eq. (18), we have

G(s2 + 2)
=G
ya =
3s

1
s
+ 3
3
s
2

The entries s12 and s21 are calculated in terms of ya and G

using Eq. (11):


G
3Gs
=
and yb = 2
1
s
s +2
+ 3
3
2s
(21)

s12 = s21 = 2

S=

1
2R

(23)

1
=0
2R

(24)

yaug11 = yaug22 = yin =

and thus
s11 = s22 = 1 2R

i1

e1

R
+

V1

V2

i2

e2

Yaug
(a)
R
+

(25)

0
ya G
ya + G

ya G
ya + G

(26)

T (s) =

1
s12

1
s11

y

s22
det S

+G
ya G
a

0
Ya G
ya + G

(27)

When working with the digital lattices of Fig. 1(c), the transfer scattering matrix is particularly convenient since its factorization is readily carried out using Richards functions extractions of degree-one and degree-two sections [see (3) for
details].
TRADE-OFFS AND SENSITIVITY

e 2 =0

Vout
V
ya G
= 2 =
Vin
V1
ya + G

The zeros on the diagonal of S indicate that the constant-R

lattice is matched to its terminations. Since cascade synthesis
can proceed via factorization of the transfer scattering matrix
(3), it is of interest to note that the transfer scattering matrix, T(s), is given by

(22)

where I2 is the 2 2 identity matrix. By symmetry, we have

from Fig. 5(b)

=2

Scattering Matrix

S = I2 2RYaug

The above results give the following scattering matrix:

The final cascade of lattices and equivalent lattice are given

in Fig. 4(a) and Fig. 4(b), respectively.

It is also of interest to look at the scattering matrix referenced

to R, S, for the constant-R lattice which can be found from
the augmented admittance matrix, Yaug, of the lattice filter as
illustrated in Fig. 5(a):

V2
e1

Despite its versatility, the lattice structure presents several

disadvantages of a practical nature. As seen in Fig. 4, there
is no possibility of a common ground between the input and
the output terminals of a lattice circuit. Although generally it
is difficult to obtain a transformation of the lattice to a circuit
with common inputoutput ground, a Darlington synthesis
can be undertaken with the desired result (8, Chap. 6). The
lattice also uses at least twice the minimum number of components required since the upper arms repeat the lower arms.
Furthermore, since the transmission zeros are a function of
the difference of component values as seen by Eq. (5), small
changes in these may distort the frequency response, the
phase in particular, considerably (6, p. 148). However, if corresponding arm components simultaneously change in a lossless lattice, so that the constant-R property is preserved, then
the sensitivity of V2( j)/V1( j) is zero since it is identically 1.

R Vout

Vin

BIBLIOGRAPHY

yin =

1
2R

1. W. Chen (ed.), The Circuits and Filters Handbook, Boca Raton, FL:
CRC Press, 1995, pp. 26572661.
2. C. F. N. Cowan and P. M. Grant, Adaptive Filters, Englewood
Cliffs, NJ: Prentice-Hall, 1985, chap. 5.

R
(b)

Figure 5. (a) Network pertinent to the interpretation of the scattering parameters. (b) The R-terminated two-port used to evaluate the
input admittance yin. This two-port configuration is obtained from Fig.
(5a) by setting e2 0 and applying an input voltage Vin.

3. L. Sellami and R. W. Newcomb, Synthesis of ARMA filters by real

lossless digital lattices, IEEE Trans. Circuits Syst. II, 43: 379
386, 1996.
4. E. S. Kuh and D. O. Pederson, Principles of Circuit Synthesis, New
York: McGraw-Hill, 1959.

LAW ADMINISTRATION
5. G. C. Temes and J. W. LaPatra, Introduction to Circuit Synthesis
and Design, New York: McGraw-Hill, 1977.
6. D. S. Humphreys, The Analysis, Design, and Synthesis of Electrical
Filters, Englewood Cliffs, NJ: Prentice-Hall, 1970.
7. D. E. Johnson, Introduction to Filter Theory, Englewood Cliffs, NJ:
Prentice-Hall, 1976.
8. H. Baher, Synthesis of Electrical Networks, Chichester: Wiley,
1984.

ROBERT W. NEWCOMB
University of Maryland at College
Park

LOUIZA SELLAMI
University of Maryland at College
Park
US Naval Academy

LAW. See CONTRACTS; LAW ADMINISTRATION; SOFTWARE MANAGEMENT VIA LAW-GOVERNED REGULARITIES.

261

LOGIC DESIGN

557

LOGIC DESIGN
The purpose of a design process is to develop a hardware system that realizes certain user-defined functionalities. A hardware system is one constructed from electronic components.
Signals enter and leave the system. They are either analog or
digital. Information carried by an analog signal is continuous,
whereas information carried by a digital (binary) signal is discrete, represented as 1 and 0. Input signals are processed by
the hardware system which produces the output signals. Signals are also generated internally, and can be either digital
or analog. Digital subsystems can be combinational or sequential. There are two types of digital sequential systems;
synchronous systems and asynchronous systems. A synchronous system is one whose elements change their values only
at certain specified times determined clock changes. Inputs,
states, and outputs of an asynchronous system can change at
any time.
A design process develops a hardware system capable of
performing some predefined functionality. The functionality
of a digital hardware system can be realized by two processes:
using logic circuits that are implemented with logic gates
and/or using software to drive the system. The former process
is referred to as hardware implementation, and the latter as
software implementation. The use of the software is related
to the use of microprocessors. If microprocessors are used in
a design, the design is referred to as a microprocessor-based
design.
In a microprocessor-based design, the functionalities are
implemented partially by hardware and partially by software.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

558

LOGIC DESIGN

The designer needs to divide the tasks between hardware and

software, which is sometimes referred to as software-hardware co-design. The hardware portion includes the microprocessor, memory, peripheral integrated circuits (IC), and glue
logic (glue logic are circuits that glue digital components together). The software is a set of computer programs stored in
the memory.
Logic circuits for digital hardware systems may be combinational or sequential. A combinational circuit is one whose
output values depend only on its present input values. A sequential circuit is one whose outputs depend not only on its
present inputs but also on its current (internal) state. In other
words, the present outputs are functions of present and previous input values. The input history is remembered by memory elements (e.g., registers). A register is a set of flip-flops.
The control unit of a digital system is normally implemented by a sequential circuit. The data path can be implemented by either a sequential circuit or a combinational circuit (and usually, also some registers). The data path may
consist of logic, arithmetic, and other combinational operators
and registers, as well as counters, memories, small state machines, interface machines, and other sequential blocks. Logic
design research develops procedures for efficient design of
digital circuits. Various technologies and related design methodologies as well as computer tools are used to transform high
level system characterizations to working devices.
Complex modern systems include subsystems that require
both digital hardware design and microprocessor-based design. To design such systems, the designers need to be familiar with both the co-design methodologies and co-design tools.
MATHEMATICAL CHARACTERIZATION
The mathematical characterization is concerned with mathematical specification of the problem as some kind of transformation, equation solving, and so on. In the case of digital
circuit/system applications, the mathematical characterizations include, for example, the following models: regular expressions, extended regular expressions, data flow graphs, Petri nets, finite state machines, Boolean functions, timed
Boolean functions, and physical design models. The physical
design models can only be realized in hardware. All of the
other models mentioned above can be realized either in hardware or in software or in both.
The goal of mathematical characterizations is to provide
the ability to investigate formally the problems of equivalence, optimization, correctness, and formal design correct
from specification, by transformational methods.
Nowadays, most of the design is done automatically by
electronic design automation (EDA) tools. The logic and system designers not only use the EDA tools, but also often design their own tools or adapt and personalize the existing
tools. That is why the problems of logic representation and
mathematical characterization are unseparable from the logic
design, and will be devoted here due attention.
High-Level Behavioral Specifications
Regular expressions are an example of high-level behavioral
specification of a sequential circuit. They describe the input
sequences accepted by a machine, output sequences generated by a machine, or input-output sequences of a machine.
Regular expressions are used in digital design to simplify de-

scription and improve optimization of such circuits as sequence generators or language acceptors. They use some finite alphabet of symbols (letters) and the set of operations.
The operations are concatenation, union, and iteration. Concatenation E1 E2 means subsequent occurrence of events E1
and E2. Union E1 E2 means logical-OR of the two events.
Iteration E* of event E means repetition of the event E an
arbitrary finite number of times or no occurrence of this
event. The simplest event is an occurrence of a single symbol.
Extended regular expressions generalize Regular Expressions
by adding the remaining Boolean operations. All the Boolean
operators can be used in an extended regular expression. For
instance, negation or Boolean product.
Petri nets are concurrent descriptions of sequential processes. They are usually converted to finite state machines or
directly converted to sequential netlists. Because they are
also used in concurrent system specification, verification, and
software design, Petri nets are increasingly used in softwarehardware codesign and to specify hardware (25).
Finite State Machines
Finite state machines (FSMs) are usually of Mealy or Moore
types. Both Moore and Mealy machines have the following:
the set of input symbols, the set of internal states (symbols),
and the set of output symbols. They also have two functions:
the transition function and the output function . The transition function specifies the next internal state as a function
of the present internal state and the present input state. The
output function describes the present output state. Moore
machines have output states which are functions of only the
present internal states. Mealy machines have output states
which are functions of both present internal states and present input states. Thus state machines can be described and
realized as composition of purely combinational blocks and
with registers that hold their states.
Parallel state machines are less commonly used compared
to Moore machines and Mealy machines. In a parallel state
machine several states can be successors of the same internal
state and input state. In other words, the parallel state machine is concurrently in several of its internal states. This is
similar in principle to concurrently having many tokens in
places of the Petri net graph description.
Nondeterministic state machines are another model. In a
nondeterministic state machine, there are several transitions
to next internal states from the same present input state and
the same present internal state. From this aspect, nondeterministic state machines are syntactically similar to parallel
state machines. However, the interpretation between these
two machines is different. In a nondeterministic state machine, the several transitions to a next internal state is interpreted that any of these transitions is possible, but only one
is actually selected for next stages of design. The selection
may occur at the state minimization, the state assignment,
the state machine decomposition, or the circuit realization of
the excitation and output logic. The transition is selected in
order to simplify the circuit at the next design stage, or to
improve certain property of the circuit. The above selection is
done either automatically by the EDA tools, or manually by a
human. Nondeterminism expands the design space, and thus
gives the designer more freedom to improve the design. However, this can also lead to a more complex or a longer design
process.

LOGIC DESIGN

There are several other generalizations of FSMs, such as

Buechi or Glushkov machines, which in general assume more
relaxed definitions of machine compatibility. For instance,
machines can be defined as compatible even if their output
sequences are different for the same starting internal states
and the same input sequences given to them, but the global
inputoutput relations of their behaviors are equivalent in
some sense. All these machines can be described in tabular,
graphical, functional, HDL language, or netlist forms, and realized in many listed below technologies.
Boolean Functions Characterizations
Boolean functions are characterized usually as truth tables,
arrays of cubes, and decision diagrams. Representations can
be canonical or noncanonical. Canonical means that the representation of a function is unique. If the order of the input
variables is specified, then both truth tables and binary decision diagrams are canonical representations. Cube representations are not canonical, but can be made canonical under
certain assumptions (for instance, all prime implicants of a
completely specified function). In a canonical representation
the comparison of two functions is simple. This is one of the
advantages of canonical representations. This advantage has
found applications in the verification and synthesis algorithms.
Good understanding of cube calculus and decision diagrams is necessary to create and program efficient algorithms
for logic design, test generation and formal verification.
Truth Tables and Karnaugh Maps
A truth table for a logic function is a list of input combinations and their corresponding output values. Truth tables are
suitable to present functions with small numbers of inputs
(for instance, single cells of iterative circuits). Truth tables
can be easily specified in hardware description languages
such as VHSIC hardware description language (VHDL).
Table 1 shows the truth table of a full adder. A full adder
is a logic circuit with two data inputs A and B, a carry-in
input Cin, and two outputs Sum and carry-out Cout.
Karnaugh maps are two-dimensional visual representations of truth tables. In a Karnaugh map, input variables are
partitioned into vertical and horizontal variables, and all
value combinations of input variables are expressed in Gray
codes. The Gray code expressions allow the geometrically adjacent cells to become combinable using the law AB AB
A. For instance, cells abcd and abcd are combined as a product acd. For functions with large numbers of inputs, the corresponding truth tables or Karnaugh maps are too large.

Table 1. Truth Table of Full Adder

A

Cin

Sum

Cout

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
1
0
0
1

0
0
0
1
0
1
1
1

559

Cube Representation. An array of cubes is a list of cubes,

which is usually interpreted as a sum of products of literals,
where a cube corresponds to a product of literals. A (binary) literal is a variable or a negated variable. In binary logic, symbol
0 corresponds to a negated variable, symbol 1 to a positive (affirmative, nonnegated) variable, symbol X to the absence of a
variable in the product, and symbol to a contradiction. A cube
is a sequence of symbols 0, 1, X, and , corresponding to their
respective ordered variables. For instance, assuming the order
of variables: x1, x2, x3, x4, the cube 01X1 corresponds to the product of literals x1x2x4, and the cube 0X0 is an intermediate data
generated to show contradiction or a nonexisting result cube of
some cube operation. A minterm (a cell of a Karnaugh map and
a row of a truth table) is thus a sequence of symbols 1 and 0.
Arrays of cubes can also correspond to exclusive sums of products, products of sums, or others. For instance, the array of
cubes {01X1, 11XX} describes the sum-of-products expression
x1x2x4 x1x2 called also the cover of the function with product
implicants (usually, with prime implicants). Depending on the
context, the same array of cubes can also describe the exclusive-sum-of-products expression x1x2x4 x1x2, or a product-ofsums expression (x1 x2 x4) (x1 x2). The correct meaning of
the array is taken care of by applying respective cube calculus
operators to it.
An algebra of cube calculus has been created with cubes
and arrays of cubes and operations on them. The most important operators (operations) are negation of a single cube or
nondisjoint sharp, disjoint sharp, consensus, crosslink, intersection, and supercube of two cubes. The cube operators most
often used in EDA programs are presented briefly below. The
nondisjoint sharp, A#B, creates a set of the largest cubes in
function A B. Disjoint sharp, A#dB, creates a set of disjoint
cubes covering function A B. Sharp operations perform
graphical subtraction and can be used in algorithms to remove part of the function that has been already taken care
of. Consensus of cubes A and B is the largest cube that includes part of cube A and part of cube B. Supercube of cubes
A and B is the smallest cube that includes entirely both cubes
A and B. Consensus and supercube are used to create new
product groups. Intersection of cubes A and B is the largest
common subcube of cubes A and B. It is perhaps the most
commonly used cube calculus operation, used in all practically
known algorithms. These operations are used mostly in the
inclusive (ANDOR) logic. Crosslink is the chain of cubes between two cubes. The chain of cubes covers the same minterms as the two cubes, and does not cover the minterms not
covered by the two cubes. Since A A 0, an even number
of coverings is treated as no covering, and an odd number of
coverings is treated as a single covering. It is used mostly in
the exclusive (ANDEXOR) logic, for instance, in exclusivesum-of-products minimization (21). Positive cofactor f a is
function f with variable a substituted to 1. Negative cofactor
f a is function f with variable a substituted to 0.
Cube calculus is used mostly for optimization of designs
with two or three levels of logic gates. It is also used in test
generation and functional verifications. Multivalued cube calculus extends these representations and operations to multivalued variables. In multivalued logic, each variable can have
several values from a set of values. For a n-valued variable,
all its literals are represented by n-element binary vectors
where value 0 in the position corresponds to the lack of this
value in the literal, and value 1 to the presence of this value.
For instance, in 4-valued logic, the literal X0,1,2 is represented

560

LOGIC DESIGN

as a binary string 1110, which means the following assignment of values: X 0 1, X 1 1, X 2 1, X 3 0. It means, the
literal X 0,1,2 is a 4-valued-input binary-output function defined as follows: X 0,1,2 1 when X 1, or X 2, or X 3,
X 0,1,2 0 when X 4. Such literals are realized in binary
circuits by input decoders, literal generators circuits, or small
PLAs. Thus, multivalued logic is used in logic design as an
intermediate notation to design multilevel binary networks.
For instance, in 4-valued model used in programmable logic
array (PLA) minimization, a 4-valued set variable corresponds to a pair of binary variables. PLA with decoders allow
to decrease the total circuit area in comparison with standard
PLAs. This is also the reason of using multivalued logic in
other types of circuits. Well known tools like MIS and SIS
from the University of California at Berkeley (UC Berkeley)
(23) use cube calculus format of input/output data.
A variant of cube calculus representation are the factored
forms (for instance, used in MIS), which are multilevel compositions of cube arrays (each array specifies a two level logic
block). Factored form is thus represented as a multi-DAG (directed acyclic graph with multiedges). It has blocks as its
nodes and logic signals between them as multiedges. Each
component block specifies its cube array and additionally its
input and output signals. Input signals of the block are primary inputs of the multilevel circuit, or are the outputs from
other blocks of this circuit. Output signals of the block are
primary outputs of the multi-level circuit, or are the inputs
to other blocks of this circuit. Initial two-level cube calculus
description is factorized to such multi-level circuit described
as a factored form. Also, a multilevel circuit can be flattened
back to a two level cube representation.
Binary Decision Diagrams. Decision diagrams represent a
function by a directed acyclic graph (DAG). In the case of the
most often used binary decision diagrams (BDDs), the nodes
of the graph correspond to Shannon expansions (realized by
multiplexer gates), controlled by the variable a associated
with this node: F a Fa a Fa. Shared BDDs are those in
which equivalent nodes of several output functions are
shared. Equivalent nodes g and h are those whose cofactor
functions are mutually equal: ga ha and ga ha. Ordered
BDDs are those in which the order of nodes in every branch
from the root is the same. A diagram can be obtained from
arbitrary function specifications, such as arrays of cubes, factored forms, expressions, or netlists. The diagram is obtained
by recursive application of Shannon expansion to the function, next its two cofactors, four cofactors of its two cofactors,
and so on, and by combination of any isomorphic (logically
equivalent) nodes. The function corresponds to the root of the
diagram. There are two terminal nodes of a binary decision
diagram, 0 and 1, corresponding to Boolean false and true. If
two successor nodes of a node Si point to the same node, then
node Si can be removed from the DAG. There are other similar reduction transformations in those diagrams which are
more general than BDDs. Decision diagrams with such reductions are called reduced ordered decision diagrams.
In addition, negated (inverted) edges are introduced in
BDDs. Such edges describe negation of its argument function.
In Kronecker decision diagrams (KDDs) three types of expansion nodes exist: Shannon nodes (realizing function f
a f a a f a), positive Davio nodes [realizing function f
a ( fa f a) f a], and negative Davio nodes [realizing function
f a ( fa f a) f a]. All of the three possible canonical expan-

sions of Boolean functions are thus included in KDD. Other

known decision diagrams include zero-suppressed binary decision diagrams (ZSBDDs) and moment diagrams. They are
used primarily in verification or technology mapping. Multivalued decision diagrams have more than two terminal nodes
and multivalued branchings with more than two successors
of a node. These diagrams allow one to describe and verify
some circuits (such as large multipliers) that are too large to
be described by standard BDDs. Some diagrams may also be
better for logic synthesis to certain technologies.
There are two types of decision diagrams: canonical diagrams and noncanonical diagrams. Canonical diagrams are
used for function representation and tautology checking.
ZSBDDs and KDDs are examples of canonical representations. An example of noncanonical decision diagrams is a free
pseudo-Kronecker decision diagram. In this type of diagram,
any types of Shannon and Davio expansions can be mixed in
levels and all orders of variables are allowed in branches.
Free pseudo-Kronecker decision diagrams are used in synthesis and technology mapping (21,22). Decision diagrams can be
also adapted to represent state machines. By describing a
state machine as a relation, the (logic) characteristic function
of the machine can be described by a decision diagram.
Level of Design Abstraction
A design can be described in different levels of abstraction, as
shown in Fig. 1.
Architecture level (also called behavioral level). At this
level, the designer has the freedom to choose different
algorithms to implement a design (for instance, different
digital filtering or edge detection algorithms). The emphasis is on inputoutput relations. Different implementations for the same function can be considered. For instance, for a given function, one can chose between two
logic implementations: sequential and parallel combinational (arithmetic adder, comparator or multiplier being
good examples).
Register transfer level (RTL). At this stage, the design is
specified at the level of transfers among registers. Thus,
the variables correspond to generalized registers, such as

Architectural level

Register transfer
level

Logic gate level

Circuit level
Figure 1. The abstraction levels of a logic design.

LOGIC DESIGN

shifters, counters, registers, memories, and flip-flops.

The operations correspond to transfers between registers
and logical, arithmetical and other combinational operations on single or several registers. Examples of operations on a single register are shift left, shift right, shift
cyclically, add one, subtract one, clear, set, negate. An
example of more general register-transfer operations is
A B C, which adds the contents of registers B and
C and transfers the result to register A. A register-transfer description specifies the structure and timing of operations in more detail but still allows for transformations
of data path, control unit, or both. The transformations
will allow improved timing, lower design cost, lower
power consumption, or easier circuit test.
Logic level (gate level). At this level every individual flipflop and logic bit is specified. The timing is partially fixed
to the accuracy of clock pulses. The (multioutput) Boolean functions with certain number of inputs, outputs,
and certain fixed functionality are specified by the user
or obtained by automatic transformations from a register-transfer level description. These functions are specified as logic equations, decision diagrams, arrays of
cubes, netlists, or some hardware description language
(HDL) descriptions. They can be optimized for area,
speed, testability, number of components, cost of components, or power consumption, but the general macropulses of the algorithms execution cannot be changed.
Physical level. At this level a generic, technology-independent logic function is mapped to a specific technologysuch as electronically programmable logic devices
(EPLD), complex programmable logic devices (CPLD),
field programmable gate arrays (FPGA), standard cells,
custom designs, application specific integrated circuits
(ASIC), read only memory (ROM), random access memory (RAM), microprocessor, microcontroller, standard
small scale integration (SSI)/medium scale integration
(MSI)/large scale integration (LSI) components, or any
combinations of these. Specific logic gates, logic blocks,
or larger design entities have been thus defined and are
next placed in a two-dimensional area (on a chip or
board) and routed (interconnected).
Logic Design Representations
A logic function can be represented in different ways. Both
behavioral (also called functional) representations and structural representations are used in logic designs. The representations can be used at all different levels of abstraction: architecture level, register-transfer level, and logic level.
Waveforms. Waveforms are normally used for viewing simulation results and specifying stimulus (input) to the simulator. Recently they are also being used increasingly as one possible input data design specification, especially for designing
asynchronous circuits and circuits that cooperate with buses.
Figure 2 shows the waveforms of a full adder.

arithmetic datapath operations, EXOR based logic can decrease area, improve speed and power consumption, and improve significantly the testability. Such circuits are thus used
in design for test. Other gate models include designing with
EPLDs, which realize ANDOR and ORAND architectures,
corresponding to sum-of-products and product-of-sums expressions, respectively. In standard cell technologies more
powerful libraries of cells are used, such as ANDOR
INVERT, or ORANDINVERT gates. In FPGAs different
combinations of multiplexers, cells that use positive Davio
(ANDEXOR) and negative Davio (NOTANDEXOR)
expansion gates, or similar cells with a small number of inputs and outputs are used. The lookup-table model assumes
that the arbitrary function of some small number of variables
(3, 4, or 5) and small number of outputs, usually 1 or 2, can be
realized in a programmable cell. Several design optimization
methodologies have been developed for each of these models.
Boolean Expressions. Boolean expressions use logic functors
(operators) such as AND, OR, NOR, NOT, NAND, EXOR, and
MAJORITY, as well as literals, to specify the (multioutput)
function. In order to specify netlists that correspond to DAGs,
intermediate variables need to be introduced to the expressions. Every netlist or decision diagram can be specified by a
set of Boolean expressions with intermediate variables. Boolean expressions can use infix (or standard), prefix (or Polish),
or postfix (or reverse Polish) notations. Most modern specification languages use infix notation for operators such as AND
or OR. Operator AND can sometimes be omitted, as in standard algebraic notations. In conjunction with operators such
as NAND, both infix and prefix notations are used. For instance, (NAND a b c) in prefix and (a NAND b NAND c) in
infix. Care is recommended when reading and writing such
expressions in hardware description languages and input formats to tools. It is always good to use parentheses in case of
doubt about operators precedence. In some languages, arbitrary operators can be defined by users and then can be used
in expressions on equal terms with well-known operators. Expressions can be created for SOP (sum-of-products), POS
(product-of-sums), factorized SOPs and POSs, and other representations as a result of logic synthesis and optimization
algorithms. Some of these algorithms will be described in the
section on combinational logic design.
Behavioral Descriptions. A logic system can be described by
hardware description languages (HDL). The most popular
ones are Verilog and VHDL. Both Verilog and VHDL can describe a logic design at different levels of abstraction, from
gate-level to architectural-level representations. Both are now
industrial standards, but VHDL seems to gain its popularity
faster, especially outside the United States. In recent years

A
B
Cin

Logic Gate Networks. Standard design uses basic logic

gates: AND, OR, NOT, NAND, and NOR. Recently EXOR and
XNOR gates were incorporated into tools and designs. Several
algorithms for logic design that take into account EXOR and
XNOR gates have been created. For certain designs, such as

561

Sum
Cout
Time
Figure 2. Waveforms for the full adder.

562

LOGIC DESIGN

several languages at higher level than VHDL have been proposed, as well as preprocessors to VHDL language from these
new representations, but so far none of them enjoyed wide
acceptance (e.g., State Charts, SpecCharts, SDL, and VAL).
State Charts and SpecCharts are graphical formalisms that
introduce hierarchy to state machines. SDL stands for the
Specification and Description Language. It is used mainly in
telecommunication. VHDL Annotation Language (VAL) is a
set of extensions to VHDL to increase its capabilities for abstract specification, timing specification, hierarchical design,
and design validation. Other known notations and corresponding data languages include regular expressions, Petri
nets, and path expressions.
Design Implementation
A design can be targeted to different technologies: full custom
circuit design, semicustom circuit design (standard cell and
gate array), FPGAs, EPLDs, CPLDs, and standard components.
In the full custom circuit designs, the design effort and cost
are high. This design style is normally used when high-quality circuits are required. Semicustom designs use a limited
number of circuit primitives, and therefore have lower design
complexity and may be less efficient when compared to the
full custom designs.
Design Verification
A design can be tested by logic simulation, functional testing,
timing simulation, logic emulation, and formal verification.
All these methods are called validation methods.

another level, or when the design functionality has changed

at the same level. Equivalence checking can verify if the original design and the modified design are functionally equivalent. For instance, two Boolean functions F1 and F2 are equivalent when they constitute a tautology F1 F2, 1, which
means the function G F1 F2 is equal to 1 (or function
F1 F2 is equal to zero) for any combination of its input variable values. A more restricted version of tautology may involve equality only on combinations of input values that actually may happen in actual operation of the circuit (thus dont
care combinations are not verified). Verification of state machines in the most narrow sense assumes that the two machines generate exactly the same output signals in every
pulse and for every possible internal state. This is equivalent
to creating, for machines M1 and M2 with outputs z1 and z2,
respectively, a new combined machine with output zcom
z1 z2 and shared inputs, and proving that output zcom 0
for all combinations of state and input symbols (9). A more
restricted equivalence may require the identity of output signals for only some transitions. Finally, for more advanced
state machine models, only inputoutput relations may be required to be equivalent in some sense. Methods based on automatic theorem proving in predicate calculus and higher order logic have been also developed for verification and formal
design correct from specification, but are not yet much used
in commercial EDA tools. Computer tools for formal verification are available from EDA companies and from universities
(e.g., VIS from UC Berkeley (5), and HOL (10) available from
the University of Utah).
Design Transformation

Logic Simulation. Logic simulation is a fast method of analyzing a logic design. Logic simulation models a logic design
as interconnected logic gates but can also use any of the
mathematical characterizations specified previously (for instance, binary decision diagrams). The simulator applies test
vectors to the logic model and calculates logic values at the
output of the logic gates. The result of the logic simulation
can be either logic waveforms or truth tables.
Timing Simulation. Timing simulation is similar to logic
simulation, but it also considers delays of electronic components. Its goal is to analyze the timing behavior of the circuit.
The results from the timing simulation can be used to achieve
target circuit timing characteristics (e.g., operational frequency).
Formal Verification. While simulation can demonstrate
that a circuit is defective, it is never able to formally prove
that a large circuit is totally correct, because of the excessive
number of input and state combinations. Formal verification
uses mathematical methods to verify exhaustively the functionality of a digital system. Formal verification can reduce
the search space by using symbolic representation methods
and by considering many input combinations at once. Currently, there are two methods that are widely used: model
checking and equivalence checking. Model checking is used at
the architectural level or register-transfer level to check if the
design holds certain properties. Equivalence checking compares two designs at the gate level or register-transfer level.
It is useful when the design is transformed from one level to

High-level design descriptions make it convenient for designers to specify what they want to achieve. Low-level design
descriptions are necessary for design implementation. Design
transformations are therefore required to convert a design
from a higher level of abstraction to lower levels of abstraction. Examples of design transformations include removal of
dead code from the microcode, removal of dead register variables, minimization of the number of generalized registers,
cost minimization of combined operations units (SUM/SUBTRACT, MULTIPLY, etc.), Mealy-to-Moore and Moore-toMealy transformations of state machines (which can change
the systems timing by one pulse), transformation of a nondeterministic state machine to an equivalent deterministic machine, transformation of a parallel state machine to an equivalent sequential machine, and mapping of a BDD to a netlist
of multiplexers.
Logic Design Process
A logic design is a complex process. It starts from the design
specification, where the functionality of the system is specified. Design is an iterative process involving design description, design transformation, and design verification. Through
each iteration, the design is transformed from a higher level
of abstraction to a lower level. To ensure the correctness of
the design, verification is needed when the design is transformed from one level to another level. Each level may involve
some kind of optimization (for instance, the reduction of the
description size). The logic design process is shown in Fig. 3.

LOGIC DESIGN

Design specification

Description

Transformation

Verification

Implementation
Figure 3. The logic design process.

COMBINATIONAL LOGIC DESIGN

A combinational logic design involves a design of a combinational circuit. For instance, the design may assume two levels
of logic. A two-level combinational logic circuit consists of two
levels of logic gates. In the sum-of-products two-level form,
the first (from the inputs) level of gates are AND gates and
the second level of gates are OR gates. In the product-of-sums
two-level form, the first level of gates are OR gates and the
second level of gates are AND gates.
The reason of logic minimization is to improve the performance and decrease the cost by decreasing the area of the
silicon, decreasing the number of components, increasing the
speed of the circuit, making the circuit more testable, making
it use less power, or achieving any combination of the above
design criteria. The optimization problem can be also specified to minimize certain weighted cost functions under certain
constraints (for instance, to decrease the delay under the constraint of not exceeding certain prespecified silicon area).
There are usually two logic minimization processes; the
first one is generic and technology-independent minimization,
the next one is technology-dependent minimization, called
also technology mapping. This second stage may also take
into account some topological or geometrical constraints of
the device.
Two-Level Combinational Logic
There are two types of programs for two-level logic minimization. Exact programs minimize the number of product implicants, the number of literals, or some weighted functions of
the two. Heuristic or approximate programs attempt to minimize these cost functions but do not give assurance of their
minimum values. Usually, the exact programs generate all
prime implicants or a subset of them, which can be proven to
include at least one minimal solution. The prime implicant is
a product of literals from which no literal can be removed.

563

These implicants are then the largest products-of-literals

groups of true minterms in a Karnaugh map that imply the
function. Next, an exact program creates a covering table and
find its best covering with prime implicants. Such a table has
true minterms as columns and prime implicants (or their subset) as rows (or vice versa). If an implicant covers (includes)
a minterm, it is denoted by an entry 1 at the intersection of
the row corresponding to the implicant and the column corresponding to the minterm. The exact solution (minimum, product-wise) is the subset of rows that cover (have minterms in)
all columns and that has the minimum number of rows. The
minimum solution (literal-wise) is the subset of rows that
cover (have minterms in) all columns and has the minimum
total number of literals in product terms (or that minimizes
another similar cost function). Some algorithms use the concept of essential prime implicants. An essential prime is a
prime that includes a certain minterm that is covered only by
this prime. A redundant prime is an implicant that covers
only minterms covered by essential primes. Redundant
primes can thus be disregarded. A secondary essential prime
is a prime that becomes essential only after previous removal
of some redundant primes.
The essential primes found are taken to be the solution
and the minterms covered by them are removed from the
function (using for instance sharp operator of cube calculus).
This causes some primes to become redundant and results in
origination of the secondary essential primes. This process of
finding essential and secondary essential primes is iterated
until no further minterms remain in the functionthus the
exact solution is found without creating and solving the covering table. Functions with such a property are called noncyclic functions. Most of real-life functions are either noncyclic
or have large noncyclic cores, which is the reason for the relative efficiency of such algorithms.
Approximate algorithms try to generate primes and find
primes cover at the same time; thus they reshape the current
cover by replacing some groups of primes with other primes,
applying cube operations such as consensus.
Program Espresso from UC Berkeley (4) is a standard for
two-level logic functions. The original program was next extended to handle multivalued logic to allow for PLAs with
decoders, function generators, and preprocessing PLAs.
EspressoMV is useful for sequential machine design, especially state assignment and input/output encodings. Its ideas
help also to develop new programs for these applications. Although heuristic version of Espresso does not guarantee the
exact solution, it is close to minimum on several families of
practical functions. Its variant, EspressoExact, finds the
minimum solution, and program Espresso-Signature can find
exact solutions even for functions with extremely large number of prime implicants. This is due to a smart algorithm that
can find exact solutions without enumerating all the prime
implicants. There are some families of practical functions for
which Espresso does not give good results and which are too
large for EspressoExact or Espresso-Signature. Programs
such as McBoole or other internally designed programs are
combined with Espresso as user-called options in some commercial tools. Two-level minimization is used in many programs for multilevel synthesis, EPLD-based synthesis, and
PLD/CPLD device fitting. These algorithms constitute the
most advanced part of todays EDA theory and practice.

564

LOGIC DESIGN

Topics close to sum-of-products minimization are productof-sums design, three-level design (ANDORAND or OR
ANDOR), four-level design (ANDORANDOR), and other
designs with a few levels of ANDOR logic. Algorithms for
their solution usually generate some kind of more complex
implicants and solve the set-covering or graph-coloring problems, either exactly or approximately. Such approaches are
used for PLD and CPLD minimization.
Another two-level minimization problem is to find, for a
given function, the exclusive-sum-of-products expression with
the minimum gate or literal cost. Several algorithms have
been created for this task (21,22). Tools for circuits that have
few, usually three, levels and have levels of gates AND,
EXOR and OR, in various orders, have been also recently designed (21,22).
Many concepts and techniques used in two-level minimization (for instance, essential implicants or covering tables) are
also used in multilevel synthesis. Similar techniques are used
in sequential synthesis (for example, a binate covering problem is used in both three-level design and state minimization,
and clique covering is used in creating primes and in several
problems of sequential design).
An important stage of the logic design involves finding the
minimum support of a function, which means the minimum
set of input variables on which the given function depends.
This can be used for logic realization with EPLDs (because of
the limited number of inputs) or in ROM-based function realization.
Many efficient generic combinatorial algorithms have been
created for logic synthesis programs. They include: unate covering (used in SOP minimization, decomposition and minimum support problems), binate covering (used in state machine minimization and three-level design), satisfiability (is
F 0? if yes, when?), tautology (is F G?), and graph coloring (used in SOP minimization and functional decomposition).
All these algorithms can be used for new applications by EDA
tool designers.
Multilevel Combinational Logic
Factorization. A multilevel combinational logic circuit consists of more than two levels of logic gates. There are several
design styles that are used to obtain such circuits. The first
method is called factorization. It recursively applies factoring
operations such as ab ac a(b c) and (a b) (a c)
a (bc). Some factoring algorithms also use other transformations as well, such as ab ac abc, and abcd ababcd
abacd. Efficient factoring algorithms based on kernels and
rectangle covering have been created (11). They are used in
many commercial tools, and are still being refined and improved to add special functionalities (for instance, improved
testability). They are also being adapted for state assignment
or reduced power consumption of the circuit. Another advantage of factorization is that it allows representation of large
circuits. A high-quality multi-level program, SIS, based
mostly on factorization, can be obtained from UC Berkeley
(23).
Functional Decomposition
The second group of multilevel synthesis methods are those
based on functional decomposition. Such methods have originated from early research of Ashenhurst (2), Curtis (7), and
Roth/Karp (20). Functional decomposition methods do not as-

sume any particular type of gates: rather they just decompose

a larger function to several smaller functions. Both functions
can be specified as tables, arrays of cubes, BDDs, netlists, or
any other aforementioned logic representations, both binary
and multivalued. Functional decompositions can be separated
into parallel and serial decompositions. Parallel decomposition decomposes multioutput function [F1(a, b, c, . . ., z),
F2(a, b, c, . . ., z), . . ., Fn1(a, b, c, . . ., z), Fn(a, b, c, . . .,
z)] to several, usually two, multioutput functions, called
blocks. For instance, [F1(a, b, c, . . ., z), F2(a, b, c, . . ., z),
. . ., Fn1(a, b, c, . . ., z), Fn(a, b, c, . . ., z)] is decomposed
into [Fi1(a, . . ., x), . . ., Fir(c, . . ., z)] and [Fir1(a, b, . . ., y),
. . ., Fin(c, . . ., x)], such that each component function depends now on fewer variables (thus the support set of each is
decreased, often dramatically). This problem is similar to the
partitioning of a PLA into smaller PLAs.
Serial decomposition is described by a general formula:
F (A, B, C) = H(A C, G(B C))

(1)

where the set of variables A C is called the set of free variables (free set), the set of variables B C is called the set of
bound variables, and the set of variables C is called the
shared set of variables. If C 0
, the decomposition is called
disjoint, otherwise it is called nondisjoint. Function G is
multioutput (or multivalued) in Curtis decomposition, and
single-output in classical Ashenhurst decomposition. Function G can be also multivalued. Every function is nondisjoint
decomposable, and many practical functions are also disjoint
decomposable. The more a function is unspecified (the more
dont cares it has), the better are the decompositions and
higher the chances of finding disjoint decompositions with
small bound sets.
It was shown that practical benchmark functions are well
decomposable with small or empty shared sets, in contrast to
randomly generated completely specified functions, for which
such decompositions do not exist. Most of the decomposition
methods decompose recursively every block G and H, until
they become non-decomposable. What is defined as nondecomposable depends on any particular realization technology (for instance, any function with not more than four
variables is treated as non-decomposable, assuming the
lookup-table model with four input variables in a block). In a
different technology, the decomposition is conducted until every block becomes a simple gate realized in this technology
(for instance, a two-input AND gate, a MUX, or a three-input
majority gate). Important problems in decomposition are
finding good bound sets and shared sets and the optimal encoding of multivalued functions G to binary vectors, in order
to simplify concurrently both functions G and H.
Designing combinational logic using ROMs or RAMs is another important area. Because of the limited width of industrial chips, one has to create additional combinational address
generator circuits, or other circuits that collaborate with the
memory chip. Some of these techniques are quite similar to
decomposition.
Decomposition methods are not yet used in many industrial tools, but their importance is increasing. A universal
functional decomposer program can be obtained from Portland State University (19).
Decision Diagrams. Finally, the last group of multilevel
synthesis methods is based on various kinds of decision dia-

LOGIC DESIGN

grams. In the first phase the decision diagram such as a BDD,

KFDD, or ZSBDD, is created, and its cost (for instance, the
number of nodes), is minimized. An important design problem
is to find a good order of input variables (i.e., one that minimizes the number of nodes). For synthesis applications these
diagrams are not necessarily ordered and canonical, because
the more general diagrams (with less constraints imposed on
them) can correspond to smaller or faster circuits. A universal
Decision Diagram package PUMA that includes BDDs,
KFDDs, and ZSBDDs, is available from Freiburg University
(8). Free BDDs, with various orders of variables in branches,
or noncanonical PseudoKronecker decision diagrams with
mixed types of expansions in levels, are used in technology
mapping (22). In the next phase, certain rules are used to
simplify the nodes. Among these rules, the propagation of
constants is commonly used. For instance, a Shannon node (a
MUX) realizing a function a 0 a b is simplified to AND
gate a b. MUX realizing ab a is simplified to OR gate a
b. All rules are based on simple Boolean tautologies. For instance, a positive Davio node realizing a function a b a is
simplified to an AND gate a b. The heuristic algorithms that
apply these transformations are iterative, recursive, or rulebased. They are usually very fast.
For some technologies, the stage of generic multilevel optimization is followed by the technology-related phase (called
technology mapping), in which techniques such as DAG covering, or tree covering by dynamic programming are applied
(11). At this stage, the particular technological constraints of
a given target technology are taken into account by redesigning for particular cell libraries, fitting to certain fan-in or
fan-out constraints, minimizing the number of cells to fit the
IC device, or decreasing the number of connections to fit the
routing channel width.

SEQUENTIAL LOGIC DESIGN

Sequential logic design involves designing sequential circuits.
A sequential circuit contains flip-flops or registers. A good understanding of flip-flops behavior is necessary to design sequential circuits. A flip-flop is an elementary register with a
single bit. Flip-flops are synchronous and asynchronous. An
example of an asynchronous flip-flop is a simple latch that
changes its state instantly with the change of one of its inputs; it is set to state ON with logic value 1 on input S (set)
and reset to state OFF with logic value 1 on input R (reset).
The disadvantage of such a latch is a nonspecified behavior
when both set and reset inputs are active at the same time.
Therefore, synchronization signals are added to latches and
more powerful edge-triggered or master-slave circuits are
built, called the synchronized flip-flops. The most popular flipflop is a D-type flip-flop. It has a clock input C, a data input
D, and two outputs, Q and Q. Output Q is always a negation
of Q. The present state of input D (i.e., the excitation function
D of the flip-flip) becomes the next state of output Q upon
a change of the flip-flops clock. Therefore, we can write an
equation, Q D, where Q is the new state of the flip-flop.
The state changes may occur at the raising slope or the falling
slope of the clock. The moment of change is irrelevant from
the point of view of design methodologies, and modern methods assume that all change moments are of the same type. It
is not recommended to design a sequential circuit that
changes its states with both leading and falling slopes. A T-

565

type flip-flop triggers its state from 0 to 1 and from 1 to 0

whenever its input T is 1 during the change of clock. It remains in its current state if the input T is 0 during the
change. A JK flip-flop has two inputs; J is the setting input,
K is the resetting input. Thus, with J 1 and K 0 the flipflop changes to state 1 (with the clocks change). If both inputs
are equal to 1, the flip-flop toggles, thus working as a T flipflop. If they are both 0, it remains in its present state. Various
procedures have been created to design special machines
(such as counters or registers), general Finite State Machines,
or other sequential mathematical models, with these flipflops.
Standard FSM Design Methodology
Sequential logic design typically includes three phases. In the
first phase a high-level description is converted into a state
machine or equivalent abstract description. For instance, a
regular expression is converted into a regular nondeterministic graph. The graph is converted into an equivalent deterministic graph, and finally into a Moore or Mealy machine
state table. In some systems this table is then minimized.
State minimization always attempts to reduce the number of
internal states, and sometimes, also the number of input symbols. In some algorithms the numbers of output bits are also
minimized. After minimization, the machine has a smaller table size but is completely equivalent, with accuracy of the
clock pulses, to the initial table. The next design stage is the
state assignment, in which every present and next state symbol in the table is replaced with its binary codes. In this way
the encoded transition table is created, which functionally
links the encoded present internal states, present input
states, present output states, and next internal states. Now
combinational functions and have been uniquely determined. They are usually incompletely specified. In some systems, the encoding (state assignment) is also done for input
and/or output symbols. Assignment of states and symbols is
done either automatically or manually. Good assignment
leads to a better logic realization in terms of the number of
product terms, literals, speed, etc. Several good assignment
programs, KISS, MUSTANG, and NOVA, are available in the
SIS system from UC Berkeley. DIET encoding program is
available from University of Massachusetts, Amherst (6).
State minimizer and encoder STAMINA is available from the
University of Colorado. In general, much information about
public domain or inexpensive programs for state machine design is available on the World Wide Web (WWW).
Because the minimized table is not necessarily the best
candidate for state assignment, in some systems the phases
of state minimization and state assignment are combined into
a single phase and only partial state minimization results as
a byproduct of state assignment of a nonminimized table (15).
This means that some compatible states may be assigned the
same code. This is done to minimize some complex cost functions, which may take into account all kinds of optimizations
of logic realizing this machine: area, speed, power consumption, testability, and so on. State assignment is a very important design phase that links the stages of abstract and structural synthesis of state machines. It can influence greatly the
cost of the solution [for instance, in FPGA or programmable
array logic (PAL) technologies]. It can improve dramatically
the testability of designs, and n out of k codes are used for

566

LOGIC DESIGN

this task. For FPGAs good results are usually achieved by

encoding machines in 1 out of k (or, one-hot) codes.
State Machine Decomposition
Another methodology of designing sequential circuits is decomposition. There are basically two methods of decomposition. Formal decomposition of state machines is a generalization of functional decomposition of Boolean and multivalued
functions. Most of the decomposition methods are based on
the partition theory (12), a mathematical theory also used in
state assignment. This theory operates on groups of states
that have some similar properties and groups of states to
which these states transit under a given input. Other decomposition methods operate on state graphs of machines, as
on labeled graphs in the sense of graph theory. They use
graph-theoretical methods to partition graphs into smaller
subgraphs that are relatively disconnected. Yet another decomposition method decomposes the given state table into two
tables: one describes a state machine, such as a counter or
shift register, and the other describes a remainder machine.
For instance, methods have been developed to decompose a
state machine to an arbitrary counter and the remainder
machine. Another method decomposes a FSM into a special
linear counter (that uses only D flip-flops and EXOR gates)
and a remainder machine. Yet another decomposition type
uses two counters, shift registers, fixed preprocessor or postprocessor machines, and many other variants as one of the
blocks of the decomposition. Each of these methods assumes
that there is some kind of elementary component machine
that can be realized more inexpensively, can be realized in a
regular structure, or has a small delay. Finally, methods have
been developed to decompose a machine into several small
machines, each of them realizable in some technology (for instance, as a logic block of a CPLD or a FPGA, or in a single
PAL integrated circuit).
In addition to formal decomposition methods that operate
on state tables, there are many informal and specialized decomposition methods that are either done by hand by the designer or are built into VHDL compilers or other high-level
synthesis tools. For instance, many tools can recognize registers, counters, adders, or shifters in a high-level specification
and synthesize them separately using special methods. Most
of the existing approaches for sequential logic design assume
the use of specific types of flip-flops, typically D flip-flops.
There are, however, methods and algorithms, especially used
in EPLD environments, that take into account other types of
flip-flops, such as JK, RS, and T.
To directly convert and decompose high-level descriptions
such as Petri nets, SpecCharts, or regular expressions to netlists of flip-flops and logic gates, or registers/shifters and logic
equations, special methods have been also created, but are
not yet very popular in commercial systems.
If a sequential circuit does not meet the requirements,
there are postprocessing steps such as retiming, re-encoding,
re-synthesis, speed-up, etc. (16,17), which can improve the design to achieve a higher performance. For instance, retiming
allows shifting of registers through logic without changing its
functionality but affecting the timing. This method is applied
at many description levels of synchronous circuits: behavioral,
register-transfer, architectural, logic, etc. It is most often used
as a structural transformation on the gate-level, where it can
be used for cycle-time minimization or for register minimiza-

tion under cycle-time constraints (18). It has also been used

for low power design and as a general optimization technique
in architectural and logic synthesis.
Finally, approaches have been created that combine these
different synthesis and decomposition methods, with the technology for which they are applied, such as EPLD, FPGA, PLA,
ROM, or custom design. Design methods have also been created to realize finite state machines with RAMs, ROMs, and
content addressable memories (CAM).
MICROPROCESSOR-BASED DESIGN
A microprocessor-based design involves a design of a digital
system which contains one or more microprocessors.
What Is a Microprocessor?
A microprocessor is a general-purpose digital circuit. A typical
microprocessor consists of a data path and a control unit, as
shown in Fig. 4. The data coming from the systems input is
manipulated in the data path and goes to the systems output.
The data path contains registers to hold data and functional
units to perform data-processing operations. These operations
include arithmetic operations, logic operations, and data
shifting. The control unit contains a program counter, an instruction register, and the control logic. The control unit controls the data path with regard to how to manipulate the data.
The microprocessor is operated under the control of software. The software is stored in standard memory devices. The
software enables the same microprocessor to perform different functions.
A computer system is a combination of hardware and software designed for general-purpose applications. The microprocessor is the major component of a computer. Besides the
microprocessor, a computer system hardware includes memory (RAM and ROM) and input/output devices. Memory can
be a main memory and a microcode memory. Additional circuits, contained in FPGAs or special ASICs, and designed using the previously outlined techniques, can be also incorporated.
What Is a Microprocessor-Based System?
The fundamental microprocessor-based system structure contains microprocessor, memory, and input/output devices with
address, data, and control buses (24). A microprocessor-based
system is shown in Fig. 5.
The functionalities performed by a microprocessor are determined by the programs. These programs, commonly called
software, are stored in the memory or off-line storage devices
(e.g., hard drives). There are different technologies used in
memory: static random-access memory (SRAM), dynamic random-access memory (DRAM), read-only memory (ROM), elec-

Microprocessor
Datapath

Control
unit

Figure 4. A simple microprocessor consisting of a datapath and a

control unit.

LOGIC DESIGN

Microprocessor

Memory

Input/output
Figure 5. A microprocessor-based system.

trically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM),
and flash memory. A program stored in a read-only memory
is called a firmware.
The basic operation of all microprocessor-based systems is
the same. The program in the memory is a list of instructions.
The microprocessor reads an instruction from the memory,
executes that instruction, and then reads the next instruction.
Logic Design Using a Microcontroller
A microcontroller is a complete computer system on a chip.
Like the microprocessor, a microcontroller is designed to fetch
and manipulate the incoming data, and generate control signals. A microcontroller contains a microprocessor, input/output (I/O) ports, timer/counter, and interrupt-handling circuit.
A typical microcontroller (e.g., 8051) contains both serial and
parallel I/O ports (3). Microcontrollers are widely used in applications like motor control, remote access, telephones and
so on. The same microcontroller (e.g., 8051), running different
software, can be used for different applications. Consequently, the overall product cost of a microcontroller-based
design is much lower than an ASIC-based design.
While microcontrollers are commonly used in control applications, microprocessors are often used for applications requiring large amounts of I/O, memory, or high-speed processing. Such applications include data processing and
complex control applications. For instance, personal computers mainly perform data processing.
Hardware Software Tradeoffs
A logic function can be realized in hardware, as discussed in
the previous sections, or in software. In most cases, however,
the required functionalities are realized partially by specially
designed hardware and partially by software.
If the hardware is used more than the software, or vice
versa, the designs are referred to as a hardware-intensive design or a software-intensive design, respectively. A designer
can make a tradeoff between the hardware- and softwareintensive realizations. Performance is usually better with
hardware implementations than with software implementations for a variety of reasons. The microprocessor is a generalpurpose device, and some speed is sacrificed for generality.
Microprocessors perform tasks in sequential fashion. Logic
circuits can be designed to perform operations in parallel.
Most logic functions occur in tens of nanoseconds. A microprocessor instruction execution time ranges from several hundred nanoseconds to tens of microseconds.
A hardware-intensive design requires more hardware in
the system and therefore increases the production cost. The

567

performance is usually higher, and the cost for software development is reduced. Software-intensive approaches, on the
other hand, require more software development and are
slower. In return, the flexibility may be enhanced and the production cost is reduced.
Microprocessor Selection
There are many different microprocessor product families on
the market. The number of bits processed in parallel inside
the microprocessor is a primary criterion with which to evaluate the performance of a microprocessor. The low-end products are 4-bit or 8-bit ones. Typical microprocessors are 16 or
32 bits wide. The 64-bit products are currently entering the
market. There are two factors that should be considered in
microprocessor selection: architecture and development tools.
There are two types of microprocessor architectures: complex instruction set computer (CISC) and reduced instruction
set computer (RISC). A CISC architecture has a larger instruction set than a RISC architecture. Besides the instruction sets, other considerations regarding architecture include
on-chip and off-chip peripherals, operating frequency, and
prices.
Development tools for microprocessor-based systems include in-circuit emulators, logic analyzers, and on-chip debuggers. In-circuit emulators are specially designed hardware
that emulate the microprocessor operations in the target system. An in-circuit emulator has its own microprocessor and
its own memory. During debugging, the tasks are run on an
emulators microprocessor and memory. The breakpoint can
be set by the user through software to trace the systems operations. The emulator is connected to a workstation or a PC.
Thus the user can monitor the systems performance in real
time. Logic analyzers are devices that can monitor the logic
values of a target system. They can be used to monitor any
bus, control line, or node in the system, and they monitor the
microprocessor passively. On-chip debuggers are software
programs that can monitor a microprocessors on-chip debugging registers.
Design Process
A microprocessor-based system can be as simple as a liquid
crystal device (LCD) controller and can be as complex as a
modern network management system. In spite of the diversity in the system complexity, the design of a microprocessorbased system always starts with a system-level specification.
After the system-level functions are clearly defined in the system specification, the overall function is divided into different
functional blocks. The hardware/software implementation
and the selection of the components for each functional block
will be determined at this stage. At this point, the tradeoff
between hardware and software implementation and the
advantage/disadvantage of each component need to be evaluated.
The system design activity is typically divided into hardware design and software design. Depending on the complexity of interaction between hardware and software, the two designs may need to be tested together in an integrated
environment. The most commonly used tool for the integrated
debugging is the in-circuit emulator, often referred to as ICE.
An in-circuit emulator can run the software in the target microprocessor and provide the capability of monitoring the internal registers. As a result, an in-circuit emulator is an effi-

568

LOGIC DESIGN

Design specification

System design

Hardware design

Software design

Hardware
implemation

Software coding

Hardware testing

Software testing

requirements are evolving constantly, the flexibility is an important design consideration.

On the other hand, while hardware designs are less flexible, they usually have better performance. Furthermore, microprocessor-based designs normally require additional devices, including program memory, data memory, and glue
logic. Consequently, the requirements for board space and
power consumption may be increased.
BIBLIOGRAPHY

System integration

System testing
Figure 6. The process of a microprocessor-based design.

cient tool for debugging the software in real time. It can also
interface with the hardware to provide the real application
environment. This hardware-software co-verification is increasingly important in complex system design. A logic analyzer is also used to trace the signals in a real-time operation.
This signal tracing involves the data storage and manipulation of the signal waveforms. Many in-circuit emulators have
this capability built into the system.
A real-time design involves processing of the events at the
speed at which the events occur. A popular example is the
display of image data coming from the network. The image
processing includes image data decompression and displaying
onto the monitor window with a specified location and dimension. A real-time design is often performance demanding and
needs to coordinate different event flows. Interrupt handling
can also be complicated. In most cases, the design contains
hardware circuit design and one or more processors. The
hardware-software co-design and/or co-verification become
imperative in a complex real-time design.
In summary, a microprocessor-based system design includes the following design activities: design specification,
system design, hardware/software tradeoffs, microprocessor
selection, other IC selection, software design and implementation, hardware design and implementation, hardware testing,
hardware/software integration, hardware and software coverification, and system testing. Figure 6 shows the stages of
the microprocessor-based system design process.
Comparing Microprocessor-Based Design and Hardware Design
Microprocessor-based designs have several benefits. Software
control allows easier modification and allows complex control
functions to be implemented far more simply than with other
implementations. A hardware design implementation is forwarded to the manufacturer and needs to be fully tested. A
software implementation is more flexible than a hardware implementation. It has the ability to revise the design quickly
and easily. Since the standards, specifications, and customer

1. P. Ashar, S. Devadas, and A. R. Newton, Sequential Logic Synthesis, Boston: Kluwer, 1992.
2. R. L. Ashenhurst, The Decomposition of Switching Functions,
Proc. of the Symposium on the Theory of Switching, April 25,
1957, Ann. Computation Lab., Harvard University, 29, pp. 74
116, 1959.
3. K. J. Ayala, The 8051 Microcontroller, Architecture, Programming, and Applications, West Publishing Company, 1991.
4. R. K. Brayton et al., Logic Minimization Algorithms for VLSI Synthesis, Boston: Kluwer, 1984.
5. R. K. Brayton et al., VIS: A System for Verification and Synthesis, in Computer-Aided Verification, July 1996.
6. M. Ciesielski and J. Shen, A Unified Approach to Input-Output
Encoding for FSM State Assignment, Proc. Design Automation
Conf., 176181, 1991.
7. H. A. Curtis, A New Approach to the Design of Switching Circuits,
Princeton, 1962.
8. R. Drechsler et al., Efficient Representation and Manipulation
of Switching Functions Based on Ordered Kronecker Functional
Decision Diagrams, Proc. of the Design Automation Conference,
San Diego, CA, June 1994, 415419.
9. A. Ghosh, S. Devadas, and A. R. Newton, Sequential Logic Testing
and Verification, Boston: Kluwer, 1992.
10. M. J. C. Gordon and T. F. Melham (eds.), Introduction to HOL: A
theorem proving environment for higher order logic, Cambridge,
UK: Cambridge University Press, 1993.
11. G. D. Hachtel and F. Somenzi, Logic Synthesis and Verification
Algorithms, Boston: Kluwer, 1996.
12. J. Hartmanis and R. E. Stearns, Algebraic Structure Theory of Sequential Machines, Upper Saddle River, NJ: Prentice-Hall, 1996.
13. R. H. Katz, Contemporary Logic Design, Menlo Park, CA:
Benjamin/Cummings Publishing Company, 1994.
14. Z. Kohavi, Switching and Finite Automata Theory, New York:
McGraw-Hill, 1970.
15. E. B. Lee and M. Perkowski, Concurrent Minimization and State
Assignment of Finite State Machines, Proc. IEEE Conference on
Systems, Man and Cybernetics, Halifax, Canada, Oct. 1984, pp.
248260.
16. C. Leiserson, F. Rose, and J. Saxe, Optimizing Synchronous Circuitry by Retiming, Third Caltech Conference on VLSI, 1983, pp.
87116.
17. G. De Micheli, Synchronous Logic Synthesis: Algorithms for CycleTime Optimization, IEEE Trans. on CAD, 10: (1), Jan. 1991, pp.
6373.
18. G. De Micheli, Synthesis and Optimization of Digital Circuits, New
York: McGraw-Hill, 1994.
19. M. Perkowski et al., Decomposition of Multiple-Valued Relations,
Proc. ISMVL 97, Halifax, Nova Scotia, Canada, May 1997, pp.
1318.
20. J. P. Roth and R. M. Karp, Minimization over Boolean Graphs,
IBM Journal Res. and Develop., No. 4, pp. 227238, April 1962.
21. T. Sasao (ed.), Logic Synthesis and Optimization, Boston: Kluwer,
1993.

LOGIC PROGRAMMING
22. T. Sasao and M. Fujita, Representations of Discrete Functions, Boston: Kluwer, 1993.
23. E. M. Sentovich et al., SIS: A System for Sequential Circuit Synthesis, Tech. Rep. UCB/ERL M92/41, Electronics Research Lab.,
Univ. of California, Berkeley, CA 94720, May 1992.
24. M. Slater, Microprocessor-Based Design, A Comprehensive Guide
to Effective Hardware Design, Englewood Cliffs, NJ: PrenticeHall, 1989.
25. M. C. Zhou, Petri Nets in Flexible and Agile Automation, Boston:
Kluwer, 1995.

NING SONG
Lattice Semiconductor Corp.

MAREK A. PERKOWSKI
Portland State University

STANLEY CHEN
Lattice Semiconductor Corp.

LOGIC DESIGN. See also NAND CIRCUITS; NOR CIRCUITS.

LOGIC DEVICES, PROGRAMMABLE. See PROGRAMMABLE LOGIC DEVICES.

LOGIC, DIODE-TRANSISTOR. See DIODE-TRANSISTOR

LOGIC.

LOGIC, EMITTER-COUPLED. See EMITTER-COUPLED

LOGIC.

LOGIC EMULATORS. See EMULATORS.

LOGIC, FORMAL. See FORMAL LOGIC.
LOGIC, FUZZY. See FUZZY LOGIC.
LOGIC GATES. See INTEGRATED INJECTION LOGIC.
LOGIC, HORN CLAUSE. See HORN CLAUSES.
LOGIC, MAGNETIC. See MAGNETIC LOGIC.
LOGIC, MAJORITY. See MAJORITY LOGIC.
LOGIC NETWORKS. See COMBINATIONAL CIRCUITS.
LOGIC OPTIMIZATION. See LOGIC SYNTHESIS.
LOGIC PROBABILISTIC. See PROBABILISTIC LOGIC.

569

LOW-PASS FILTERS

619

LOW-PASS FILTERS
A low-pass filter suppresses the high-frequency components
of a signal, leaving intact the low-frequency ones. A low-pass
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

620

LOW-PASS FILTERS

Attenuation (dB)
As

RC

Ap
f1

Frequency (Hz)

f2

Figure 3. Pole-zero diagram of the first-order low-pass filter.

Figure 1. Low-pass filter requirements.

Next, compute the quantity

filter specification can be expressed as shown in Fig. 1. In the
stopband (above f 2 Hz), the attenuation is at least As dB. In
the passband (below f 1 Hz), the attenuation is at most Ap dB.
The band from f 1 to f 2 is called the transition band.
A first-order low-pass filter is shown in Fig. 2. The transfer
function is

Vout (s)
R1 R2C1C2

1

=
1
1
1
Vin (s)
s2 +
+
+
s+
R1C1
R2C1
R2C2
R1 R2C1C2

(1)

where 1 r2 /r1. The pole-zero diagram is shown in Fig. 5.

An approach to design a circuit (a low-pass filter) whose
frequency response satisfies the low-pass requirements shown
in Fig. 1 consists of two steps: approximation of the requirements by a transfer function and synthesis of the transfer
function.
There are several approximation methods, for instance,
Butterworth, Chebyshev, inverse Chebyshev, and Cauer approximations. A transfer function obtained by one method is
different from those obtained by the others, and has different
properties. However, the frequency response of each of the
transfer functions satisfies the low-pass requirements. The
Butterworth approximation method is described below.
Compute the scaling factor k given by the equation below:
10

kf 
2

2 log10

f1

(1)n S2n + 1 = 0

The pole-zero diagram is shown in Fig. 3.

An active second-order low-pass filter is shown in Fig. 4.
The circuit is known as the Sallen and Key low-pass circuit.
The transfer function is

k=

100.1 As 1 

Choose the order, n, of the filter to be the smallest integer not

smaller than the above quantity. Solve for all the left-halfplane roots, Zis, of the equation

1
Vout (s)
RC
=
1
Vin (s)
s+
RC

log10

The Butterworth low-pass transfer function is formed as follows:



1


i=1 (S Zi ) s=k 1/n s/2 f

TLP (s) = n

Example. Find the Butterworth transfer function for a lowpass filter with As 15 dB, Ap 0.5 dB, f 1 1 kHz, and f 2
5 kHz.

k=
log10

100.1(0.5) 1 = 0.35

100.1(15) 1 

0.352
 5k 
2 log10
1k

= 1.72

Choose n 2. The left-half-plane roots of the equation

(1)2 s2(2) + 1 = 0

C1
0.1 A p

R1

R2

Vin

Vout

C2
R
+
Vin

+
C

r1

r2

Vout

Figure 2. First-order low-pass filter.

Figure 4. Sallen and Key low-pass circuit.

LOW-POWER BROADCASTING

621

R. W. Daniels, Approximation methods for electronic filter design, New

York: McGraw-Hill, 1974.

G. Morchytz and P. Horn, Active filter design handbook, New York:

Wiley, 1981.

CHIU H. CHOI
University of North Florida

Figure 5. Pole-zero diagram of the Sallen and Key low-pass filter.

are 1/ 2(1 j). Therefore, the Butterworth transfer function is





1


TLP (s) = 


s2 + 2s + 1 s= 0.35s/2 (1000)
which simplifies to
TLP (s) =

1.128 108
s2 + 1.502 104 s + 1.128 108

The above calculations have all been performed before, and

the results are available in tabular and computer program
forms.
The Sallen and Key low-pass circuit can be used to realized
a second-order low-pass transfer function of the form
T (s) =

K
s2 + as + b

Compare T(s) with Eq. (1)

K=

R1 R2C1C2

a=

1
1
1
+
+
R1C1
R2C1
R2C2

b=

1
R1 R2C1C2

Since there are more unknowns than equations, one can assign values to certain unknowns and then solve for the remaining unknowns. As an example, choose C1 1, C2 1,
2. Then
K = 2b

R1 =

1
a

R2 =

a
b

The impedance-scaling method can be used to scale the values

of Rs and Cs into the practical ranges.
In general, a higher-order low-pass transfer function obtained by Butterworth and Chebyshev approximations can be
factorized into a product of biquadratic functions and possibly
one first-order expression. Each of the biquadratic functions
can be synthesized by using the Sallen and Key or other lowpass circuits. The first-order transfer function can be realized
by an active or passive circuit. By cascading all the biquad
and first-order circuits together, the low-pass filter is realized.
Reading List
G. Daryanani, Principles of Active Network Synthesis and Design, New
York: Wiley, 1976.
M. E. Van Valkenburg, Analog Filter Design, New York: Holt, Rinehart, and Winston, 1982.

MAJORITY LOGIC
Majority Logic is used to implement a majority decision
mechanism. In particular, an Majority Logic Block (MLB)
can be regarded as a black box that receives possibly different data values at its inputs, and gives, at its output,
the data value present on the majority of its inputs. For instance, if a MLB receives the three input data 1, 1 and
0, it gives the output data 1.
MLBs are generally used as component blocks of digital electronic systems devoted to critical operations, like
control systems of nuclear plants, ight control systems of
aircrafts, speed control systems of trains, onboard control
systems of satellites, etc. The correct uninterrupted operation of these systems is mandatory because their malfunction could cause catastrophic consequences, such as loss of
human life or huge economical loss. To avoid such losses,
the system must be designed to guarantee its correct behavior (that is, the behavior expected in the fault-free case)
despite the occurrence of internal faults.
In fact, electronic systems are prone to faults. Faults occur during the systems manufacturing process and during
its operation. For instance, in the presence of a high electrical eld, high current density within a circuit metal line
might cause the line to break. This might make the faulty
circuit provide an output datum different from the correct
one, for example, a 0 rather than a 1. If the faulty signal,
for instance, is a signal that activates the alarm device of
a trains speed control system when equal to 1, it is obvious that a faulty 0 may cause the whole system to become
ineffective with possible catastrophic consequences.
Unfortunately, faults of this kind (and faults of a different kind) might occur within a digital electronic system. The likelihood of their occurrence is reduced by using
proper electronic components, but ensuring that they never
occur is impractical.
Hence, if the correct operation of a system is crucially
important, some precautions must be taken to avoid the
catastrophic consequences that faults might produce. The
techniques used to reach this goal are generally called
fault-tolerant techniques.
In particular, to guarantee that a system tolerates its
possible internal faults (that is, to ensure that no system
malfunction occurs because of such faults), redundancy is
used. As an example, to guarantee that a trains speed control system tolerates faults in the circuit activating the
alarm device, redundant copies of such a circuit are used.
If these redundant copies are properly isolated from one
another, a single fault during the system operation affects
only one copy, hence only this copy provides incorrect (or
faulty) output data, whereas the other copy (or copies) gives
correct output data.
However, it should be obvious that redundancy alone is
not sufcient to ensure that a system tolerates its possible internal faults. To reach this goal, we need some decision criterion that allows us to determine which data value,
among those present at the output of the redundant copies,
can be regarded as correct, and which one(s) as incorrect.
This decision criterion normally is the majority criterion,
implemented by an MLB.

Of course, three is the minimum number of copies of the

same circuit (or, more generally, module) that we must have
to allow the MLBs selection of the majority data value.
The use of MLBs and redundant copies of the same module characterize the fault-tolerant N-Modular Redundancy
(NMR) systems where, as previously introduced, N must be
3. The idea to use N-Modular Redundancy and majority
logic blocks (also called majority voting blocks, or voters) to achieve fault-tolerance was rst introduced in (2)
and has been adopted for several critical applications, such
as space exploration missions and nuclear reactor protection (3, 4).
In the particular case where N = 3, these systems are
called Triple Modular Redundancy (TMR) systems. Hence
a TMR system consists of: (1) three copies of the original,
non fault-tolerant module, that concurrently process the
same information (where a module is simply a circuit, a
gate, or even a microprocessor, depending on systems related choices), (2) n MLBs (where n is the number of outputs of the replicated module), each comparing bit-by-bit
the corresponding outputs of the three replicated modules,
and producing at its output the majority data value among
those at its inputs (Figure 1). Moreover, suitable techniques
are generally adopted at the system level to avoid exhausting all of the systems redundancy as modules get successively faulty.
Obviously, MLBs play a critical role in the fault-tolerant
systems described. In fact, the correct operation of the
whole system is compromised if an MLB becomes faulty.
For instance, it is obvious that, if the output of an MLB is
affected by a stuck-at 1 fault (for instance, because of a
short between an output line and the circuit power supply),
the faulty MLB always gives an output 1, regardless of
the data values at its inputs (that is, also when the data
value on the majority of its inputs is a 0). Similar problems may occur because of different kinds of faults possibly
affecting the input (5), internal and output lines/nodes of
a MLB.
In the remainder of this article we consider the problem
of designing MLBs for TMR and NMR systems and the case
of faulty MLBs.

MAJORITY LOGIC FOR TRIPLE MODULAR

REDUNDANCY SYSTEMS
As previously introduced, an MLB can be regarded as a
black box that must produce at its output the datum value
present on the majority of its inputs. To distinguish such
a majority datum value, an MLB must have at least three
inputs. When this is the case, the MLB must satisfy the
truth table shown in Table 1, where Z denotes the output
of the MLB, and X = (X1 , X2 , X3 ) is the MLB input vector.
Hence, the MLB can be implemented (at the logic level)
by a two-level NAND-NAND (Figure 2) or NOR-NOR (Figure 3) circuit. Equivalently, a two level AND-OR, or ORAND implementation can be considered (6).
Of course, the electrical level implementations of these
MLBs depend on the technology adopted. As a signicant
example, if the Complementary MOS (CMOS) technology
is used, the NAND-NAND majority logic block can be im-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Majority Logic

Figure 1. Representation of a Triple

Modular Redundancy (TMR) system.

Figure 2. NAND-NAND logical implementation of a majority logic

block for a TMR system.

Figure 3. NORNOR logical implementation of a majority logic

block for a TMR system.

plemented by means of the circuit shown in Figure 4. Alternatively, the circuit shown in Figure 5, for instance, can
be used (6). Other possible electrical implementations of
MLBs for TMR systems (Figure 6 and Figure 7) were proposed in (7, 8). Different from the conventional MLB re-

alizations considered up to now, these MLBs produce an

output error message in case of internal faults that make
them give an incorrect majority output datum value. The
behavior of these circuits is described later while dealing
with the problems due to faults affecting MLBs.

Majority Logic

Figure 4. Example 1 of a possible CMOS implementation of the NANDNAND majority logic block in Figure 2.
Table 1. Truth Table of a Three-Input Majority Logic Block
X1 X2 X3
000
001
010
011
100
101
110
111

Z
0
0
0
1
0
1
1
1

As regards the number of errors in X tolerated by a general TMR system, it is evident that, if only one of the MLB
input data is incorrect (that is either X1 , X2 , or X3 ), the MLB
produces the correct output datum value. Instead, if two
input data are incorrect, the MLB produces the incorrect
output datum value. Hence, a TMR system tolerates only a
single error on the corresponding outputs of the replicated
modules. If a higher number of errors must be tolerated (because of system level requirements) an NMR system with
n MLBs (where n is the number of outputs of the replicated
module), each with N inputs (N > 3), must be used.

MAJORITY LOGIC FOR N MODULAR REDUNDANCY

SYSTEMS
Tto tolerate E errors in the vector X = (X1 , X2 ,. . . , XN ) given
to the input of an MLB of an NMR system, N and E must
satisfy the following equation (9):
N 2 E + 1.
In fact, when this is the case, the number of erroneous bits
E is smaller than the number of correct bits (N E).
Barbour and Wojcik (6) added an upper bound to the
value of N of an NMR system tolerating E errors. In particular, they transformed Eq. (1) into:
2 E + 1 N (E + 1)2 .
Moreover, they proposed possible two-level implementations of MLBs for NMR systems, whose values of N and E
satisfy Eq. (2). These are the implementations most widely
used for MLBs of general NMR systems.
In particular, the rst level of the proposed MLBs conN
sists of ( ) AND (or OR, or NAND, or NOR) gates, where
K
K is a parameter [called a grouping parameter (6)] that

Majority Logic

Figure 5. Example 2 of a possible CMOS implementation of the NAND-NAND majority logic block in Figure 2.

Figure 6. Electrical implementation of the majority logic block

giving an output error message in case of internal faults affecting
its correct operation proposed in (7).

must satisfy the following condition:

E + 1 K N E.
N
) combinaK
tions of K elements out of the N elements of the MLB input
vector X.
The second level of the proposed MLBs consists of a
simple OR (or AND, or NAND, or NOR) gate, depending
on whether AND (or OR, or NAND, or NOR, respectively)

The inputs to these rst level gates are the (

gates are used at the rst level.

As an example, the general NAND-NAND implementation of such an MLB, with generic grouping parameter K,
is shown in Figure 8. We can easily verify that, if N = 3 and
K = 2, this implementation equals that reported in Figure
2.
The derived electrical level implementations of these
MLBs are straightforward.
An alternative implementation of MLBs for NMR systems was proposed in (10). These MLBs (Figure 9) are suit-

Majority Logic

Figure 7. Electrical implementation of

the majority logic block giving an output
error message in case of internal faults affecting its correct operation proposed in (8).

Figure 8. NAND-NAND logical implementation of a majority logic block for an NMR system with grouping parameter = K.

able for NMR dynamic systems, that is, in systems where,

differing from the conventional cases considered until now,
the number of processed replicated modules (hence the
number of inputs of the MLBs) can be dynamically changed
during the systems operation.

PROBLEMS IN CASE OF FAULTY MAJORITY LOGIC

As previously mentioned, if the MLB of a TMR (NMR) system becomes faulty, it might produce at its output an incorrect majority datum value, hence making the adoption
of the TMR (NMR) fault-tolerant technique useless.
To deal with this problem, MLBs can be themselves
replicated (11), as schematically shown in Figure 10 for

a TMR system. Note that in this and in the following gures, we use a common symbol to represent n MLBs, and
the n outputs of the replicated modules, respectively. It is
obvious that, if this scheme is adopted, faults affecting one
of the replicated MLBs that make it produce incorrect output data can be tolerated. However, similar to the case of
replicated modules only, in this case the problem of distinguishing the datum value provided by the majority of
the replicated MLBs also arises. Of course, if other MLBs
(receiving the outputs of the replicated MLBs) are used to
fulll this purpose, the problem discussed here is simply
translated to these nal MLBs.
An alternative strategy for dealing with this problem is
to renounce the fault-tolerance requirement of the MLBs

Majority Logic

To reduce these costs in TMR systems, the MLB introduced in (7) or (8) can be adopted.
The electrical structure of the MLB in (7) is shown in
Figure 6, where CKS and CKS denote a periodic signal
whose period is T and an opposite waveform, respectively.
This MLB provides an output error message when internal faults occur that make it give an output incorrect
majority datum value. This behavior is guaranteed for all
MLB node stuck-at, transistor stuck-on, transistor stuckopen and resistive bridging faults (whose values of the connecting resistance are in the range 0
to 6 k
).
In the fault-free case, this MLB gives as its output: (1)
a signal equal to CKS if the majority of its input signals is
equal to 0; (2) a signal equal to CKS if the majority of its
input signals is equal to 1 (Table 2). Hence, in the faultfree case, this MLB gives at its output a signal assuming
both high and low logic values within the same period T. In
particular, the logic value produced when CKS = 1 is equal
to the majority datum value (MV in Table 2) among those
given to its input during such a period T.
Figure 9. Majority logic block suitable to NMR dynamic systems
introduced in (11).

and to require only that the MLBs give an output error

message in case of internal faults making them produce
incorrect output data. Such an error message can be exploited at the system level to avoid the dangerous consequences possibly resulting from incorrect MLB operation.
For instance, if an error message is received by one of the
MLBs of a trains speed control system, a system level recovery procedure can be automatically started, eventually
making the train stop.
MLBs of this kind can be found in (18).
In particular, in (1), the MLBs are duplicated (Figure
11), and their outputs are given to the inputs of a comparator that veries whether or not such outputs are equal to
one another. In the case of a disagreement, the comparator gives an output error message. It is obvious that this
strategy guarantees that, in case of faults affecting an MLB
that make it produce erroneous majority output data, the
comparator gives an output error message.
However, compared with the case where single MLBs
are used, this solution implies an inevitable increase of the
area overhead and power consumption costs of the faulttolerant system.

Table 2. Truth Table of the Majority Logic Block in (6), and Corresponding
Majority Datum Value

X1 X2 X3
000
001
010
011
100
101
110
111

Z
CKS
CKS
CKS
CKS
CKS
CKS
CKS
CKS

MV
0
0
0
1
0
1
1
1

Instead, in case of an internal fault of the kind previously reported, either the MLB is not affected by the fault
(that is it continues providing the correct majority output
data), or it produces an output error message (in particular a signal that does not change logic value within T).
If a fault does not affect the MLB and following internal
faults occur, either the MLB is not affected by these internal faults or it provides an output error message. This
condition holds for all possible sequences of internal faults
under the general assumptions that internal faults occur
one at a time during the operation of an integrated circuit
and that the time interval elapsing between two succeed-

Figure 10. Triplicated MLB scheme proposed in

(12). In priciple, triplication of the MLB allows faults
that could possibly affect one of the replicated MLBs
to be tolerated. In practice, problems arise in correctly
discriminating the value given by the majority of the
replicated MLBs.

Majority Logic

Figure 11. Duplicated MLB scheme presented in (1). Faults affecting one of the duplicated MLBs
can not be tolerated, but can be detected by the output comparator.

Figure 12. Detecting scheme possibly adopted to avoid the exhaustion of a TMR system redundancy. The detectors (DTRi , i = 1, 2, 3) reveal the disagreement between the outputs of the replicated
modules and the majority output data given by the MLBs.

ing faults is long enough to allow the fault-free modules to

produce both high and low output data values.
The presence of an error message at the output of this
MLB can be simply revealed. For instance a ip-op sampling the MLB output on both the CKS rising and falling
edges (12) can be used.
This MLB implementation can also be extended to NMR
systems (13). In this case, compared with the electrical
structure shown in Figure 6: (1) the number of parallel pull3
N
up/pull-down branches changes from ( ) to (
), (2)
2
(N + 1)/2
each branch consists of (N + 1)/2 series transistors, rather
than of 2. Obviously these conditions may limit the maximal value of N for which this implementation can be conveniently used.
The electrical structure of the MLB in (8) is shown in
Figure 11, where CKS and CKS denote a periodic signal
with period T, and an opposite waveform, respectively.
Similarly to the MLB in (7), also this MLB provides
an output error message in case of the occurrence of internal faults making it give an output incorrect majority

data value. This behavior is guaranteed for all MLBs node

stuck-at, transistor stuck-on, transistor stuck-open and resistive bridging faults (with values of the connecting resistance in the range 0
to 6 k
), but for the bridging
fault between its two outputs, which should consequently
be avoided, for instance by proper design of the circuit layout.
In the fault-free case, this MLB gives as its output: (1)
(Z1i , Z2i ) = (1, 1), if the majority of its input signals is equal
to 0; (2) (Z1i , Z2i ) = (0, 0), if the majority of its input signals
is equal to 1.
In case of internal faults of the kind previously reported,
this MLB behaves as the MLB in (7), with the difference
that the provided error message is an output word with
Z1i = Z2i , rather than a a signal that does not change logic
value within T (as for the MLB in (7)).
Compared to the MLB in (7), the MLB in (8) features
the advantage of being faster (offering a reduction of the
input/output propagation delay of approximately the 80%),
thus being more suitable to high speed, high reliability systems, while requiring comparable power consumption. This

Majority Logic

is achieved at the cost of a small increase in area overhead

(14). Additionally, as proven in (14), the MLB in (8) continues to work properly (i.e., either it continues to provide the
correct majority vote, or it produces an output error message) even when affected by high leakage currents, which
are expected to become a major concern for dynamic CMOS
circuits.
As previously introduced, suitable techniques must be
also adopted to avoid exhausting the TMR (NMR) systems
redundancy because modules become successively faulty.
To fulll this purpose, detectors that reveal the disagreement between the outputs of the MLBs and of the replicated modules can be used (15), as shown schematically in
Figure 11. A possible electrical implementation of detectors of this kind, suitable for use together with the MLBs
described, can be found in (13).
Voters operating on a word basis, rather than the traditional bit-by-bit basis, have also been proposed (16), which
are able to provide an output error message, should the
words produced by the three replicated modules of a TMR
system differ from each other.
Finally, several critical applications require that the
MLBs of the used TMR (NMR) systems provide fail-safe
outputs; that is, signals whose value is either correct or
safe (where, as an example, the red color is the safe value
for trafc control lights). Possible implementations of this
kind of MLBs can be found in (17).

BIBLIOGRAPHY
1. K. G. Shin and H. Kim, A Time Redundancy Approach to TMR
Failures Using Fault-State Likelihoods, IEEE Trans. Comput.,
vol.43,pp. 11511162,October 1994.
2. J. V. Neumann, Probabilistic logics and the synthesis of reliable organisms from unreliable components, Automata Studies, Ann. of Math. Studies, no. 34,pp. 4398, 1956.
3. C. E. Stroud and A. E. Barbour, Testability and Test Generation for Majority Voting Fault-Tolerant Circuits, J. of Electronic Testing: Theory and Applications, Vol.4,pp. 201214,
1993.
4. D. Audet, N. Gagnon, and Y. Savaria, Quantitative Comparisons of TMR Implementations in a Multiprocessor System,
in Proc. of 2nd IEEE Int. On-Line Testing Work.,pp. 196199,
1996.
5. M. Favalli, and C. Metra, TMR Voting in the Presence of
Crosstalk Faults at the Voter Inputs, IEEE Trans. on Reliability, pp. 342348,September 2004.
6. A. E. Barbour and A. S. Wojcik, A General, Constructive Approach to Fault-Tolerant Design Using Redundancy, IEEE
Trans. Comput., pp. 1529,January 1989.
7. C. Metra, M. Favalli, and B. Ricc`o, Compact and Low Power
Self-Checking Voting Scheme, in Proc. of IEEE Int. Symp.
on Defect and Fault Tolerance in VLSI Systems,pp. 137145,
1997.
8. J.-M. Cazeaux, D. Rossi, C. Metra, New High Speed CMOS
Self-Checking Voter, IEEE Proc. of the 10th IEEE International On-Line Testing Symposium,pp. 5863, 2004.
9. W. H. Pierce, Failure-Tolerant Computer Design, New York:
Academic, 1965.
10. N.-E. Belabbes, A. J. Guterman, and Y. Savaria, Ratioed Voter
Circuit for Testing and Fault-Tolerance in VLSI Processing

11.
12.

13.

14.

15.

16.

17.

Arrays, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.,

vol.43,pp. 143152,February 1996.
P. K. Lala, Fault Tolerant and Fault Testable Hardware Design,
Englewood Cliffs, NJ: Prentice-Hall International, 1985.
M. Afghahi and J. Yuan, Double edge triggered D ip-op for
high speed CMOS circuits, IEEE J. of Solid State Circuit,
vol.SC-26,pp. 11681170,August 1991.
C. Metra, M. Favalli, and B. Ricc`o, On-Line Self-Testing Voting
and Detecting Schemes for TMR Systems, J. of Microelectronic
Systems Integration, vol.5, no. 4,pp. 261273, 1997.
J.-M. Cazeaux, D. Rossi, C. Metra, Self-Checking Voter for
High Speed TMR Systems, J. of Electronic Testing: Theory and
Applications, pp. 377389, 2005.
N. Gaitanis, The Design of Totally Self-Checking TMR
Fault-Tolerant Systems, IEEE Trans. Comput., vol.37,pp.
14501454,November 1988.
S. Mitra, E. J. McCluskey, Word-Voter: A New Voter Design for
Triple Modular Redundant Systems, IEEE Proc. of the 18th
IEEE VLSI Test Symposium,pp. 465470, 2000.
M. Nicolaidis, Fail-Safe Interfaces for VLSI: Theoretical Foundations and Implementation, IEEE Trans. Comput., vol.47,pp.
6277,January 1988.

CECILIA METRA
D.E.I.S. University of Bologna,
Viale Risorgimento 2,
Bologna, Italy

410

MATCHED FILTERS

MATCHED FILTERS
The history of the matched filter can be traced back to more
than half a century ago. In 1940s, due to World War II, radar
became a very important detecting device. To enhance the
performance of radar, D. O. North proposed an optimum filter
for picking up signal in the case of white-noise interference
(1). A little bit later, this technique was called matched filter
by Van Vleck and Middleton (2). Dwork (3) and George (4)
also pursued similar work. The filter has a frequency response function given by the conjugate of the Fourier transform of a received pulse divided by the spectral density of
noise. However, the DworkGeorge filter is only optimum for
the case of unlimited observation time. It is not optimum if
observations are restricted to a finite time interval. In 1952,
Zadeh and Ragazzini published the workOptimum filters for
the detection of signals in noise (5), where they described a
causal filter for maximizing the signal-to-noise ratio (SNR)
with respect to noise with an arbitrary spectrum for the case
of unlimited observation time, and second for the case of a
finite observation interval. Since then, extensive works on
matched filters were done in 1950s. A thorough tutorial review paper called An introduction to matched filters (6) was
given by Turin.
In the 1960s, due to rapid developments of digital electronics and digital computers, the digital matched filter has appeared (79). Turin gave another very useful tutorial paper
in 1976, entitled An introduction to digital matched filters
(10), in which the class of noncoherent digital matched filters
that were matched to AM signals was analyzed.
At this time, matched filters have become a standard technique for optimal detection of signals embedded in steadystate random Gaussian noise. The theory of matched filter
can be found in many textbooks (1113).
In this article, we will briefly discuss the theory and application of matched filters. We will start with a continuous input signal case. Then, we will look at the discrete input signal
case. Finally, we will provide some major applications of
matched filters.
THE MATCHED FILTER FOR CONTINUOUS-TIME
INPUT SIGNALS
As mentioned previously, the matched filter is a linear filter
that minimizes the effect of noise while maximizing the signal. Thus, a maximal SNR can be achieved in the output. A
general block diagram of matched-filter system is described
in Fig. 1. To obtain the matched filter, the following conditions and restrictions are required in the system:
1. The input signal consists of a known signal si(t) and an
additive random noise process ni(t) with continuous pa-

Input
si(t) + ni(t)

Matched filter
h(t)

Output
so(t) + no(t)

Figure 1. The block diagram of the matched filter in continuous

time.

rameter t. The corresponding output signal and noise

are so(t) and no(t), respectively.
2. The system is linear and time invariant.
3. The criterion of optimization is to maximize the output
signal-to-noise power ratio. Since noise no(t) is random,
its mean squared value Eno2(t) is used as the output
noise power.
Mathematically, this criterion can be written as
SNRo =

s2o (t)
= maximum
E{n2o (t)}

(1)

at a given time t. The form of the matched filter can be derived by finding the linear time-invariant system impulse response function h(t) that achieves the maximization of Eq. (1).
The mathematical derivation process can be described as
follows.
Since the system is assumed to be linear and time invariant, the relationship between input signal si(t) and output signal so(t) could be written as

so (t) =

si ( )h(t ) d

(2)

Similarly, the relationship between input noise ni(t) and output noise no(t) could also be expressed as

no (t) =

ni ( )h(t ) d

(3)

Substituting Eqs. (2) and (3) into Eq. (1), the output power
SNR can be shown to be

SNRo = 






2

si ( )h(t ) d 

(4)

Rn ( , )h(t )h(t ) d d

where Rn(, ) is the autocorrelation function of the input

noise ni(t) and is given by
Rn ( , ) = E{ni ( )no ( )}

(5)

Now the unknown function h(t) can be found by maximizing

Eq. (4). To achieve this goal from Eqs. (4) and (5), one can see
that the optimum h(t) (i.e., the matched-filter case) will depend on the noise covariance Rn(, ). Since h(t) is required to
be time invariance [i.e., h(t ) instead of h(t, )], the noise
at least has to be wide-sense stationary [i.e., Rn(t, ) Rn(t
)]. To obtain the optimum filter, based on the linear system
theory (13), Eq. (4) can be rewritten as


2


it 0

H( f )S( f )e df 

SNRo = 
|H( f )|2 Pn ( f ) df

(6)

where H( f) F [h(t)] is the Fourier transform of the impulse

response function h(t) (i.e., the transfer function of the sys-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

MATCHED FILTERS

tem), S( f) F [s(t)] is the Fourier transform of the known

input signal s(t), 2f is angular frequency, to is the sampling time when SNRo is evaluated, and Pn( f) is the noise
power spectrum density function. To find the particular H( f)
that maximizes SNRo, we can use the well-known Schwarz
inequality, which is





2 

A( f )B( f ) d f 


|A( f )|2 df

|B( f )|2 df

(7)

where A( f) and B( f) may be complex functions of the real variable f. Furthermore, equality is obtained only when
A( f ) = kB ( f )

(8)

where k is any arbitrary constant and B*( f) is the complex

conjugate of B( f). By using the Schwarz inequality to replace
the numerator on the right-hand side of Eq. (6) and letting
A( f) H( f)Pn( f) and B( f) S( f)eit0 / Pn( f), Eq. (6) becomes


|S( f )|2
df
|H( f )|2 Pn ( f ) df
Pn ( f )
SNRo

|H( f )|2 Pn ( f ) df

(9)

In addition, because Pn( f) is a non-negative real function, Eq.

(9) can be further simplified into

SNRo

|S( f )|2
df
Pn ( f )

(10)

The maximum SNRo is achieved when H( f) is chosen such

that equality is attained. This occurs when A( f) kB*( f), that
is,

kS ( f )eit 0
H( f ) Pn ( f ) =

Pn ( f )

(11)

Based on Eq. (11), the transfer function of the matched filter

H( f) can be derived as
S ( f ) it
0
e
H( f ) = k
Pn ( f )

In the matched-filter case, the output SNRo is simply expressed as



|S( f )|2
df
Pn ( f )

(14)

For the case of white noise, the Pn( f) N0 /2 becomes a constant. Substituting this constant into Eq. (13), the impulse
response of the matched filter has a very simple form
h(t) = Csi (t0 t),

where C is an arbitrary real positive constant, t0 is the time

of the peak signal output. This last result is one of the reasons
why h(t) is called a matched filter since the impulse response
is matched to the input signal in the white-noise case.
Based on the preceding discussion, the matched filter theorem can be summarized as follows: The matched filter is the
linear filter that maximizes the output signal-to-noise power
ratio and has a transfer function given by Eq. (12).
In the previous discussion, the problem of the physical realizability is ignored. To make this issue easier, we will start
with the white-noise case. In this case, the matched filter is
physically realizable if its impulse response vanishes for negative time. In terms of Eq. (15), this condition becomes

0,
t<0
h(t) =
(16)
si (t0 t), t 0
where t0 indicates the filter delay, or the time between when
the filter begins receiving the input signal and when the maximum response occurs. Equation 16 also implies that s(t) 0,
t t0, i.e., the filter delay must be greater than the duration
of the input signal. As an example, let us consider the following signal corrupted by additive white noise. The known input
signal has the form


si (t) =

Bebt , t < 0, B, b > 0

t0

0,

(17)

Substituting Eq. (17) into Eq. (16), the impulse response of

matched filter h(t) is

h(t) =

 b(t t )
Be 0 , t t0
0,

t < t0

(18)

The physical realizability requirement can be simply satisfied

by letting t0 0. The simplest choice is t0 0 so that h(t) has
a very simple form

h(t) =

 bt
Be , t 0
0,

t<0

(19)

(12)

The corresponding impulse response function h(t) can be easily obtained by taking the inverse Fourier transform of Eq.
(12), that is,


S ( f ) iw(tt )
0 df
e
h(t) =
H( f )eit df =
k
(13)

Pn ( f )

max{SNRo } =

411

(15)

The output signal so(t) of the system can be obtained by substituting Eqs. (17) and (19) into Eq. (2). The calculated result
of so(t) is

B2 bt

2b e , t < 0
so (t) =
(20)

B2 bt

e , t>0

2b
To give an intuitive feeling about the results above, Figs.
2(a)2(c) illustrate the input signal si(t), matched filter h(t),
and output signal so(t). From Fig. 2(c), indeed, one can get the
maximum signal at time t t0 0. Note that, in Fig. 2, we
have assumed the following parameters: B b 1. The physical implementation of this simple matched filter can be
achieved by using a simple RC circuit as illustrated in Fig. 3,
in which the time constant of the RC circuit is RC 1.
In many real cases, the input noise may not be white noise
and the designed matched filter may be physically unrealiza-

412

MATCHED FILTERS

ble. Now, let us look at another example with color noise (11).
We assume that the input signal si(t) has a form of

et/2 e3t/2 , t > 0
si (t) =
(21)
0,
t<0
and the input noise is wide-sense stationary with power spectral density
Pn ( f ) =

4
1 + 4(2 f )2

(22)

To obtain the matched filter, first, we take the Fourier transform of input signal si(t). Based on Eq. (21), the spectrum of

Input
si(t) + ni(t)

Output
C so(t) + no(t)

Figure 3. Implementation of the discussed example in text using a

RC circuit. This figure shows that the continuous time matched filter
can be physically implemented by using a simple RC circuit.

input signal can be shown to be

Si (2f ) =

4
(1 + i4f )(3 + i4f )

(23)

Substituting Eqs. (22) and (23) into Eq. (12), the transfer
function of matched filter H( f) can be derived as
Input signal

S ( f ) it
0
e
Pn ( f )
1 + i4f it
0
e
=k
3 i4f

H( f ) = k

1
Si (t)

0.8
0.6
0.4
0.2
4

(25)

where u(t) is the unit step function. Note that this filter is not
physically realizable because it has a nonzero value for t
0. To solve this problem, one method is to take a realizable
approximation by letting h(t) 0 for t 0. In this case, the
approximated matched filter ha(t) can be expressed as

Matched filter
1
0.8
h (t)

To simplify the expression, we let the arbitrary constant

k 1 for the later derivations. By taking the inverse Fourier
transform of Eq. (24), the impulse response of the matched
filter is
h(t) = (t t0 ) + 2e(tt 0 )3/2 u(t0 t)

(a)

(24)

0.6

ha (t) = h(t)u(t)
= (t t0 ) + 2e(tt 0 )3/2 u(t0 t)u(t)

0.4

(26)

0.2
4

Then, the output spectrum So( f) of the output signal so(t) due
to this approximated matched filter is

So ( f ) = Si ( f )Ha ( f )

(b)

where Ha( f) is the Fourier transform of ha(t). Again, by taking

the inverse Fourier transform of Eq. (27), the output signal
so(t) can be derived as

Output signal
1

so (t) = e3t 0 /2 et/2 u(t) + 23 e3(t 0 +t )/2 u(t)

0.8
So (t)

(27)

13 e3(t 0 t )/2 u(t) + 13 e3(t 0 t )/2

0.6

(28)

0.4
0.2
4

(c)
Figure 2. A simple matched-filter example for white noise and continuous time. (a) Input signal. (b) Matched filter. (c) Output signal.
This figure provides an intuitive feeling about using matched filter
for continuous time signal processing.

Again, to have an intuitive feeling about this example, Fig. 4

illustrates the input signal si(t), the ideal physically unrealizable matched filter h(t), approximated realizable matched filter ha(t), and the output signal so(t) obtained with the approximated filter.
For the purpose of convenience, we assume that t0 1 for
these plots. From Fig. 4(d), one can see that, indeed, the output signal has a maximum value at t t0 1. However, there
is no guarantee that this approximated filter is the optimum
filter. In fact, it is shown that, a better output SNR can be

MATCHED FILTERS

achieved for this problem if the prewhitening technique is employed for the signal detection (11).
Before the end of this section, we want to point out that,
in practical terms, it is impossible to design an optimal
matched filter for any signal which has an infinite time duration because it requires infinite delay time. However, the
above examples are very fast exponential decaying signal, for
which one can make the delay time long enough so that optimality can be approached to any desired degree. In other
words, the practically realizable matched filter only exists
for a time limited function. From this point of view, mathematically speaking, the above two examples both have infinite
time duration. Thus, even for the second example, it becomes
unrealizable. However, since there are extremely fast exponentially decaying signals, optimality can be achieved to any
desired degree. In this sense, example 2 can be treated as
realizable matched filter. Finally, since t0 represents the delay time of the filter in the above examples, in practice, it
must be selected longer than the time duration of the target
signal. For the sole purpose of simplicity, in the above examples, the simple values (that are not strict in the mathematical sense) of t0 are selected.

Input signal
1
Si(t)

0.8
0.6
0.4
0.2

h(t)

0
t
(a)

Ideal matched filter

3
2
1
0
1
2
3
4
4

0
t

ha(t)

(b)

3
2
1
0
1
2
3
4

THE MATCHED FILTER FOR DISCRETE-TIME INPUT SIGNALS

Approximated matched filter

0
t
(c)

In recent years, with rapid developments of the digital computers, digital signal processing becomes more and more powerful. Some major advantages of using digital signals as compared to their analog forms are the high accuracy, high
flexibility, and high robustness. Right now, the matched filter
can be easily implemented with the digital computer in real
time. To implement the filter with digital computer, one has
to deal with the discrete signal instead of continuous signal.
In this case, for the same linear time invariant system as described in Fig. 1, the relationship between the output signal
so(t) and input signal si(t) has changed from the continuoustime form Eq. (2) to the following discrete time form (11):

so j =

Output signal by ha(t) filter

413

j


h jk sik

(29)

k=

So(t)

0.8
0.6
0.4
0.2
4

0
t

(d)
Figure 4. Example of a matched filter with color noise for a continuous-time signal. (a) Input signal. (b) Ideal matched filter. (c) Approximated matched filter. (d) Output signal with approximated matched
filter. This figure illustrates how to deal with color noise with
matched filter.

where sik represents the input signal at time k (k 0, 1, 2,

. . .), hk is the discrete impulse response function of the linear, time-invariant matched filter, and soj is the corresponding
discrete output signal at time j. In other words, the integration in Eq. (2) has been replaced by the summation in Eq.
(29). Similarly, in the discrete-time case, the Eq. (3) is rewritten as

no j =

j


h jk nik

(30)

k=

Again, our objective is to find the optimum form of matched

filter so that the output signal-to-noise power ratio will be
maximum at some time q. Mathematically, it can be written
as

SNRo =

s2oq
E{n2oq }

= maximum

(31)

414

MATCHED FILTERS

To find hk, we let maximim SNR, symbolized as SNRomax, equal

a constant 1/. Since SNRomax represents the maximum power
ratio, it has to be larger than 0, i.e., 0. Substituting this
assumption into Eq. (31), one can obtain

s2oq

1
SNRomax =
SNRo =
E{n2oq }

The input noise is additive white noise with autocorrelation

function

No
= 1, k = 0
Rn (k) =
2
0,
k=

(32)

(41)

Substituting Eqs. (40) and (41) into Eq. (39), we have

Equation (32) can be rewritten as
E{n2oq }

s2oq

=C0

where C is a positive real constant and the equality holds

only for the optimum matched filter. To find this matched filter, one can substitute Eqs. (29) and (30) into Eq. (33). Then,
one can get
q
q



Rn (k j)hqk hq j

k= j=


2
q
 




sik hqk  = C 0
k=

(34)

where Rn(k j) is the autocorrelation function of the input

noise ni and C is another positive constant. Note that, in the
process of deriving Eq. (34), we already assume that the input
noise is at least wide-sense stationary. Under this assumption, the following condition holds:
Rn (k j) = Rn ( j k) = E{nk n j }

Rn (k j)hq j = sik

0,

kq
k<q

so j =

1
e| j| ,
1 e2

j = 0, 1, 2, . . .

Rn (k j)hq j = sik

In Eq. (44), we have replaced the limit q by . To get the

general form of a discrete matched filter for nonwhite noise,
we take the z transform on both size of Eq. (44) and use the
convolution theorem for z transforms. Then, Eq. (44) can be
shown to be (14)

(36)

To make our discussion easy to be understood, we start with

the simple white-noise case. In this case, the autocorrelation
function can be simply written as

No /2, k = 0
Rn (k) =
(37)
0,
k
= 0

(38)

To get a simpler expression of hk, we let l q k. Then, Eq.

(38) can be rewritten as
(39)

Comparing Eq. (39) with Eq. (15), one can see that Eq. (39) is
exactly the discrete form of Eq. (19).
As an example, let us consider a discrete input signal sik to
be given by

ek , k 0
(40)
sik =
0, k > 0

(45)

where

Pn (z) =
H(z) =

Substituting Eq. (37) into Eq. (36), we obtain

2
s
No i(ql)

(44)

j=

zq Pn (z)H(1/z) = Si (z)

h1 =

(43)

Again, to have an intuitive feeling about this result, Figs.

5(a), 5(b), and 5(c) illustrate the discrete input signal sik, the
discrete matched filter hk, and the discrete output signal soj.
To get the simplest form in Fig. 5, we assumed q 0.
Equation (36) only deals with the physically realizable
case. In general, Eq. (36) will be written as (11)

j=

N0
h
= sik
2 qk

(42)

Substituting Eqs. (40) and (42) into Eq. (29), the output signal soj can be derived as

(35)

Since the equality holds in Eq. (34) when hk is an optimum

matched filter regardless of the detail forms of input signal
and noise, it can be shown that the following equation can be
derived under this condition (11):
q


hk = si(qk) =

(33)


eqk ,

Si (z) =

k=


k=

Rn (k)zk
hk zk

(46)

sik zk

k=

represent the power density spectrum, z transform of a discrete matched filter, and z transform of discrete input signal.
To obtain the z transform of a discrete matched filter H(z),
Eq. (45) is rewritten as
H(z) =

Si (1/z) q
z
Pn (z)

(47)

In deriving Eq. (47), we have used a property of power density

spectrum, that is, Pn(z) Pn(1/z). Theoretically speaking, the
discrete matched filter in the time domain (that is, the impulse response function of discrete matched filter) can be obtained by taking the inverse z transform of Eq. (47) (14), that

MATCHED FILTERS

is

Discrete input filter

hk =

Sik

0.8
0.6
0.4
0.2

0
k

(a)

1
2i




H(z)zk1 dz =




Si (1/z) q k1
z z
dz
Pn (z)

where represents a counterclockwise contour in the region

of convergence of H(z) enclosing the origin. Note that, similar
to the continuous-time case, the discrete matched filter defined by Eqs. (47) and (48) may not be realizable for arbitrary
input signal and noise because hk will not vanish for negative
values of the index k.
To implement the color noise effectively, the prewhitening
technique is used (11). In this approach, the input power density spectrum Pn(z) is written as the multiplication of two
facts Pn(z) and Pn(z), that is,

0.8

Pn+ (z) = Pn (1/z)

0.6
0.4
0.2

0
k

(48)

(49)

where Pn(z) has all of the poles and zeros of Pn(z) that are
inside the unit circle and Pn(z) has all the poles and zeroes of
Pn(z) that are outside the unit circle. By this definition, it is
easy to show that

hk

1
2i

Pn (z) = Pn+ (z)Pn (z)

Discrete matched filter

415

(50)

Note that, in the time domain, Pn(z) corresponds to a discretetime input signal that vanishes for all times t 0. Similarly,
Pn(z) corresponds to a discrete-time input signal that vanishes for all time t 0. This property can be easily proven in
the following way. Assume that nk is a discrete-time function
that vanishes on the negative half-line; that is,
nk = 0, k < 0

(51)

(b)

If nk is absolutely summable, that is, if

Discrete output signal


k=

1
Normalized Soj

| fk | =

| fk | <

(52)

k=0

then, the z transform of this discrete function nk becomes

0.8

N(z) =

0.6

nk zk =

k=

nk zk

(53)

k=0

0.4
0.2

0
j

(c)
Figure 5. An example
crete time. (a) Discrete
Discrete output signal.
using matched filter for

of matched filter for the white noise in disinput signal. (b) Discrete matched filter. (c)
This figure gives an intuitive feeling about
discrete time signal processing.

From Eq. (53), one can see that the function N(z) exists everywhere when z 1. Hence, the poles of N(z) will all be inside
the unit circle. Thus, Pn(z) corresponds to a discrete-time input signal that vanishes for all time t 0. Similarly, it can
be shown that Pn(z) corresponds to a discrete-time input signal that vanishes for all time t 0. Assume Hpw(z) is the
prewhitening filter. Based on the definition of prewhitening
filter, Hpw(z) for the noise power spectrum Pn(z) must satisfy
(11)
 +


Pn (z)Hpw (z) Pn (z)Hpw (1/z) = 1

(54)

From Eq. (54), one can conclude that the prewhitening filter
is
Hpw (z) =

1
Pn+ (z)

(55)

416

MATCHED FILTERS

ing about the time signal detection by a matched filter, let

us consider the following simple example. For the purpose of
convenience, the ideal input signal is assumed to be a normalized sinc function, that is, sinc(t) sin(t)/t, as shown in
Fig. 7(a). This ideal signal is embedded into an additive
broadband white noise. The corrupted signal is shown in Fig.
7(b). Figure 7(c) shows the system output when this corrupted

iy
Unit
circle
1
x
x

e e

Figure 6. Pole locations of the power spectrum density.

Because Pn(z) corresponds to a discrete-time input signal that

vanishes for all time t 0, the impulse response hpwk of this
prewhitening filter will vanish for k 0. Hence, the prewhitening filter Hpw(z) is physically realizable. For example, let us
consider a color noise with power density spectrum
>0

(56)

2.5
2
1.5
Si (t)

N
e2
,
Pn (z) = 0
2 (e z1 )(e z)

Ideal input sinc signal

1
0.5
0

Equation (56) shows that Pn(z) contains poles both inside and
outside the unit circle. As discussed in the early part of this
section, this Pn(z) can be written as the multiplication of
Pn(z) and Pn(z). For the purpose of convenience and symmetry, we let

0.5
4

No
e
=
2 e z1

No e
Pn (z) =
2 e z

0
t

(a)

Pn+ (z)

(57)

2.5
2
Si (t) + ni (t)

Based on Eq. (57), it is easy to show that Pn(z) has a pole at

z e (11). Since 0, z e 1. In other words, this
pole is inside the unit circle. Similarly, Pn(z) has a pole at
z e that is a real number greater than unity. Figure 6
illustrates these pole locations of above power spectral density Pn(z) in the complex plane. In the figure, we assume that
z x iy. For this particular example, the poles are on the
real axis.
When applying this prewhitening technique to the discrete
matched filter, Eq. (47) will be rewritten as


Si (1/z) q
1
z
H(z) = +
(58)
Pn (z) Pn (z)

Input signal with noise

1.5
1
0.5
0

0.5
4

0
t

(b)
Matched filter output

3
2.5
2
So (t) + no (t)

Equation (58) is the multiplication of two terms. The first

term is the prewhitening filter and the second term is the
remainder of the unrealizable matched filter. Note that this
multiplication is equivalent to put two linear systems in tandem. Similar to the continuous-time case, this remaining unrealizable filter can be made realizable by throwing away the
part that does not vanish for negative time.

1.5
1
0.5
0

APPLICATIONS OF A MATCHED FILTER

As mentioned in the first part of this article, the major application of the matched filter is to pick up the signal in a noisy
background. As long as the noise is additive, wide-sense stationary, and the system is linear and time invariant, the
matched filter can provide a maximum output signal-to-noise
power ratio. The signal can be a time signal (e.g., radar signal) or spatial signals (e.g., images). To have an intuitive feel-

0.5
4

0
t

(c)
Figure 7. Results of the matched filter acting on an input signal
with sinc function embedded in white noise. (a) Ideal input signal. (b)
Signal with noise. (c) Matched-filter output.

MATCHED FILTERS

signal passes through the matched filter. From Fig. 7(c), one
can see that the much better signal-to-noise power ratio can
be achieved by applying matched filter for the signal detection
as long as the noise is additive at least wide-sense stationary noise.
Besides applying matched filters for the time-signal detection (such as the radar signal previously mentioned), they can
also be used for spatial signal detection (1517). In other
words, we can use a matched filter to identify specific targets
under the noisy background. Thousands of papers have been
published in this field. To save space, here, we just want to
provide some basic principles and simple examples of it. Since
spatial targets, in general, are two-dimensional signals, the
equations developed for the one-dimensional time signal
needs to be extended into the two-dimensional spatial signal.
Note that when matched filter is applied to the 2-D spatial
(or image) identification, this filtering process can be described simply as a cross-correlation of a larger target image
(including the noisy background) with a smaller filter kernel.
To keep the consistency of the mathematical description, a
similar derivation process (used for the 1-D time-signal case)
is employed for the 2-D spatial signal. Assume that the target
image is a two-dimensional function s(x, y) and this target
image is embedded into a noisy background with noise distribution n(x, y). Thus, the total detected signal f(x, y) is
f (x, y) = s(x, y) + n(x, y)

(59)

Similar to the one-dimensional time signal case, if f(x, y) is a

Fourier-transformable function of space coordinates (x, y) and
n(x, y) is an additive wide-sense stationary noise, the matched
filter exists. It can be shown that H(p, q) has a form of (15)
H(p, q) = k

S (p, q)
N(p, q)

(60)

where S*(p, q) is the complex conjugate of the signal spectrum, N(p, q) is the spectral density of the background noise,
k is a complex constant, and (p, q) are corresponding spatial
angular frequencies. Mathematically, S(p, q) and N(p, q) are
expressed as


S(p, q) =
N(p, q) =
F (p, q) =

 +

 +

s(x, y)ei( px+qy) dx dy

n(x, y)ei( px+qy) dx dy

(61)



s(x, y) + n(x, y) ei( px+qy) dx dy

= S(p, q) + N(p, q)
For the purpose of simplicity, we assume that the input
noise n(x, y) is white noise. In this case, Eq. (60) is reduced to
the simpler form
H(p, q) = k S (p, q)

put in the spectrum domain, that is, (p, q) domain, becomes

T (p, q)H(p, q) = K  T (p, q)S (p, q)

(63)

Assume that the final system output is g(x, y), where (x,
y) are the spatial coordinates in the output spatial domain.
Based on the discussion in the section titled The Matched
Filter for Continuous-Time Input Signals, g(x, y) can be obtained by taking the inverse Fourier transform of Eq. (63),
that is,
g(x , y ) =

T (p, q)S (p, q)ei( px +qy ) dp dq

(64)

In Eq. (64), if the input unknown function t(x, y) is the same

as the prestored function s(x, y), Eq. (64) becomes

g(x , y ) =

S(p, q)S (p, q)ei( px +qy ) dp dq

(65)
|S(p, q)|2 ei( px

 +qy  )

dp dq

In this case, the system output g(x, y) is the Fourier

transform of the power spectrum S(p, q)2, which is an entirely positive real number so that it will generate a big output at the original point (0, 0). Notice that, in recent years,
due to the rapid development of digital computers, most 2-D
filtering can be carried out digitally at relatively fast speed.
However, to have an intuitive feeling about 2-D filtering, an
optical description about this filtering process that was widely
used in the earlier stage of image identification (15) is provided. Optically speaking, the result described by Eq. (65) can
be explained in the following way. When the input target t(x,
y) is same as the stored target s(x, y), all the curvatures of
the incident target wave are exactly canceled by the matched
filter. Thus, the transmitted field, that is, T(p, q)S*(p, q), in
the frequency domain, is a plane wave (generally of nonuniform intensity). In the final output spatial domain, this plane
wave is brought to a bright focus spot g(0, 0) by the inverse
Fourier transform as described in Eq. (65). However, when
the input signal t(x, y) is not s(x, y), the wavefront curvature
will in general not be canceled by the matched filter H(p, q)
in the frequency domain. Thus, the transmitted light will not
be brought to a bright focus spot in the final output spatial
domain. Thus, the presence of the signal s(x, y) can conceivably
be detected by measuring the intensity of the light at the focal
point of the output plane. If the input target s(x, y) is not located at the center, the output bright spot simply shifts by a
distance equal to the distance shifted by s(x, y). Note that this
is the shift-invariant property of the matched filter. The preceding description can also mathematically be shown by
Schwarzs inequality. Based on the cross-correlation theorem
of Fourier transform (17), Eq. (64) can also be written in the
spatial domain as

(62)

where k is another constant. Now, assume that there is an

input unknown target t(x, y). Then, the corresponding spectrum is T(p, q). When this input target passes through the
matched filter H(p, q) described by Eq. (62), the system out-

417

g(x , y ) =

t(x, y)s (x x , y y ) dx dy

(66)

which is recognized to be the cross-correlation between the

stored target s(x, y) and the unknown input target t(x, y). By

418

MATCHED FILTERS

intensity function is defined as

 + 
2







t(x,
y)s
(x

x
,
y

y
)
dx
dy



 + 
 + 
|t(x, y)|2 dx dy
|s(x, y)|2 dx dy

(70)

Based on Eq. (69), we obtain

 + 
2






t(x, y)s (x x , y y ) dx dy


1
 + 
 + 
|t(x, y)|2 dx dy
|s(x, y)|2 dx dy

Figure 8. Autocorrelation results of the matched filter application to

pattern recognition. (a) Stored training image. (b) Absolute value of
the matched filter. (c) Unknown input target. (d) Autocorrelation intensity distribution. (e) Three-dimensional surface profile of autocorrelation intensity distribution. This figure shows that there is a sharp
correlation peak for autocorrelation.

(71)

with the equality if and only if s(x, y) t(x, y). Thus, one can
conclude that the normalized correlation intensity function
has a maximum value 1 when the unknown input target t(x,
y) is same as the stored target s(x, y). In other words, if there
is a 1 detected in the normalized correlation intensity function, we know that the unknown input target is just our
stored target. Therefore, this unknown target is recognized.
Again, to have an intuitive feeling about the pattern recognition with matched filter, let us look at the following example. Figure 8(a) shows a triangle image that is used to construct the matched filter. Mathematically speaking, this
image is s(x, y). Then, the matched filter S*(p, q) is synthe-

applying Schwarzs inequality into Eq. (66), we have






2

t(x, y)s (x x , y y ) dx dy

|t(x, y)|2 dx dy

|s(x x , y y )|2 dx dy
(67)

with the equality if and only if t(x, y) s(x, y). Because the
integral limit is in Eq. (67), by letting x x x, y
y y, we have

|s(x x , y y )|2 dx dy =

|s(x, y)|2 dx dy
(68)

Substituting Eq. (68) into Eq. (67), we have






2

t(x, y)s (x x , y y ) dx dy

 +

|t(x, y)|2 dx dy|

|s(x, y)|2 dx dy

(69)

with the equality if and only if t(x, y) s(x, y). To recognize

the input target, we can use the normalized correlation intensity function as the similarity criterion between the unknown
input target and the stored target. The normalized correlation

Figure 9. Cross-correlation results of the matched filter applied to

pattern recognition. (a) Stored training image. (b) Absolute value of
the matched filter. (c) Unknown input target. (d) Cross-correlation
intensity distribution. (e) Three-dimensional surface profile of crosscorrelation intensity distribution. This figure shows that there is no
sharp correlation peak for cross correlation.

MATHEMATICAL PROGRAMMING

sized based on this image. Figure 8(b) shows the absolute

value of this matched filter. When the unknown input target
t(x, y) is the same triangle image as shown in Fig. 8(c), Fig.
8(d) shows the corresponding autocorrelation intensity distribution on the output plane. Figure 8(e) depicts the corresponding three-dimensional surface profile of the autocorrelation intensity distribution. From this figure, one can see that,
indeed, there is a sharp correlation peak in the correlation
plane. However, if the unknown input target t(x, y) is not the
same image used for the matched-filter construction, the correlation result is totally different. As an example, Figs. 9(a)
and 9(b) show the same stored image and matched filter. Figure 9(c) shows a circular image used as the unknown input
target. Figures 9(d) and 8(e) illustrate the cross-correlation
intensity distribution and corresponding three-dimensional
surface profile. In this case, there is no sharp correlation
peak. Therefore, from the correlation peak intensity, one can
recognize the input targets. In other words, one can tell
whether the unknown input target is the stored image or not.
Before the end of this section, we would like to point out that,
besides the 2-D matched filter, in recent years, 3-D (spatialspectral) matched filters were also developed. Due to space
limitations, we can not provide a detail description about this
work. Interested readers are directed to papers such as the
one written by Yu et al. (19).
CONCLUSION
In this article, we have briefly introduced some basic concepts
of the matched filter. We started our discussion with the continuous-time matched filter. Then we extended our discussion
to the discrete-time input signals. After that, some major applications of the matched filters such as the signal detection
and pattern recognition were addressed.

419

11. J. B. Thomas, An Introduction To Communication Theory and

System, New York: Springer-Verlag, 1988, p. 202.
12. J. H. Karl, An Introduction to Digital Signal Processing, New
York: Academic Press, 1989, p. 217.
13. L. W. Couch, Digital and Analog Communication Systems, New
York: Macmillan, 1990, p. 497.
14. L. B. Jackson, Digital Filters and Signal Processing, Boston:
Kluwer Academic Publishers, 1989, p. 34.
15. A. Vander Lugt, Signal detection by complex spatial filtering,
IEEE Trans. Inf. Theory, IT-10, 139145, 1964.
16. SPIE Milestone Series on Coherent Optical Processing, edited by
F. T. S. Yu and S. Yin (eds.), Bellingham, WA: SPIE Optical Engineering Press, 1992.
17. S. Yin, et al., Design of a bipolar composite filter using simulated
annealing algorithm, Opt. Lett. 20: 14091411, 1995.
18. F. T. S. Yu, Optical Information Processing, New York: WileyInterscience, 1983, p. 10.
19. X. Yu, I. Reed, and A. Stocker, Comparative performance analysis
of adaptive multispectral detectors, IEEE Trans. Signal Process.,
41, 2639, 1993.

SHIZHUO YIN
FRANCIS T. S. YU
University Park, PA

MATCHING. See BROADBAND NETWORKS.

MATERIALS. See FUNCTIONAL AND SMART MATERIALS.
MATERIALS, CONDUCTIVE. See CONDUCTING MATERIALS.

MATERIALS EVALUATION. See EDDY CURRENT NONDESTRUCTIVE EVALUATION.

MATERIALS, FUNCTIONAL. See FUNCTIONAL AND

SMART MATERIALS.

MATHEMATICAL LINGUISTICS. See COMPUTATIONAL

BIBLIOGRAPHY
1. D. O. North, Analysis of the factors which determines signal/
noise discrimination in radar, Technical Report No. PtR-6C,
Princeton, NJ: RCA Laboratories, 1943.
2. J. H. Van Vleck and D. Middleton, A theoretical comparison of
visual, aural and meter reception of pulsed signals in the presence of noise. J. Appl. Phys., 17: 940971, 1946.
3. B. M. Dwork, Detection of a pulse superimposed on fluctuation
noise, Proc. IRE, 38: 771774, 1950.
4. T. S. George, Fluctuations of ground clutter return in air-borne
radar equipment, J. IEE, 99: 9299, 1952.
5. L. Z. Zadeh and J. R. Ragazzini, Optimum filters for the detection
of signals in noise, Proc. IRE, 40: 11231131, 1952.
6. G. L. Turin, An introduction to matched filters, IRE Trans. Inf.
Theory, IT-6: 311329, 1960.
7. C. R. Cahn, Performance of digital matched filter correlation with
unknown interference, IEEE Trans. Commun. Technol. COM-19:
Part II, 11631172, 1971.
8. D. J. Gooding, A digital matched filter for signals of large timebandwidth product. Technical Report No. 16, Waltham, MA: Sylvania Communications System Laboratory, February 1969.
9. K. Y. Chang and A. D. Moore, Modified digital correlator and its
estimation errors, IEEE Trans. Inf. Theory, IT-16: 699700, 1970.
10. G. L. Turin, An introduction to digital matched filters, Proc.
IEEE, 64: 10921112, 1976.

LINGUISTICS.

MATHEMATICAL OPTIMIZATION. See MATHEMATICAL PROGRAMMING.

324

MIXER CIRCUITS

MIXER CIRCUITS
A frequency mixer inputs two frequenciesa radio frequency
(RF) and a local oscillator (LO) frequencymixes them, and
produces their difference frequency and sum frequency. The
output signal is tuned by a filter, and one of the two output
frequencies is selected: the difference or the sum. When the
output difference frequency is an intermediate frequency (IF),
the mixer is usually called a downconversion frequency mixer,
and when the output sum frequency is a high frequency, it is
usually called an upconversion frequency mixer.
A frequency mixer is fundamentally a multiplier, because
the analog multiplier outputs a signal proportional to the
product of the two input signals. Therefore, a frequency mixer
is represented by the symbol for the multiplier, as shown in
Fig. 1.

RF

IF

LO
Figure 1. A symbol for a frequency mixer. The symbol for a multiplier is used.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

MIXER CIRCUITS

The transfer function of a nonlinear element is expressed

as

Multiplier
A(t) cos( st)

f (u) = a0 + a1 u + a2 u + a3 u + + an u +
2

325

A(t) cos[( s p)t]

Filter

(1)
A(t) cos( pt)

The product xy of the two input signals x and y can be derived

from only the second-order term: a2u2, where u x y, and
x and y are the two input signals. The product of the two
input signals is produced by a nonlinear element, such as a
diode or transistor. For example, single-diode mixers, singly
balanced diode mixers, doubly balanced diode mixers, singletransistor mixers, singly balanced transistor mixers, and doubly balanced transistor mixers are usually used as frequency
mixers.

APPLICATION TO RECEIVERS
Mixers are used to shift the received signal to an intermediate
frequency, where it can be amplified with good selectivity,
high gain, and low noise, and finally demodulated in a receiver. Mixers have important applications in ordinary lowfrequency and microwave receivers, where they are used to
shift signals to frequencies where they can be amplified and
demodulated most efficiently. Mixers can also be used as
phase detectors and in demodulators, and must perform these
functions while adding minimal noise and distortion.
Figure 2 shows, for example, the block diagram of a VHF
or UHF communication receiver. The receiver has a singlestage input amplifier; this preamp, which is usually called an
RF amplifier, increases the strength of the received signal so
that it exceeds the noise level of the following stage; therefore,
this preamp is also called a low-noise amplifier (LNA). The
first IF is relatively high (in a VHF or UHF receiver, the
widely accepted standard has been 10.7 MHz); this high IF
moves the image frequency well away from the RF, thus
allowing the image to be rejected effectively by the input filter. The second conversion occurs after considerable amplification, and is used to select some particular signal within the
input band and to shift it to the second IF. Because narrow
bandwidths are generally easier to achieve at this lower frequency, the selectivity of the filter used before the detector is
much better than that of the first IF. The frequency synthesizer generates the variable-frequency LO signal for the first
mixer, and the fixed-frequency LO for the second mixer.

A(t) cos( st) cos( pt) = A(t) cos[( s p)t] + cos[( s + p)t]
2

Figure 3. A mixer is fundamentally a multiplier. The difference frequency in the IF results from the product of sinusoids.

Figure 3 illustrates an ideal analog multiplier with two sinusoids applied to it. The signal applied to the RF port has a
carrier frequency s and a modulation waveform A(t). The
other, the LO, is a pure, unmodulated sinusoid at frequency
p.
Applying some basic trigonometry to the output is found to
consist of modulated components at the sum and difference
frequencies. The sum frequency is rejected by the IF filter,
leaving only the difference.
Fortunately, an ideal multiplier is not the only device that
can realize a mixer. Any nonlinear device can perform the
multiplying function. The use of a nonideal multiplier results
in the generation of LO harmonics and in mixing products
other than the desired one. The desired output frequency
component must be filtered from the resulting chaos.
Another way to view the operation of a mixer is as a
switch. Indeed, in the past, diodes used in mixers have been
idealized as switches operated at the LO frequency. Figure
4(a) shows a mixer modeled as a switch; the switch interrupts
the RF voltage waveform periodically at the LO frequency.
The IF voltage is the product of the RF voltage and the
switching waveform.
Another switching mixer is shown in Fig. 4(b). Instead of
simply interrupting the current between the RF and IF ports,

S(t)
S(t)
VRF

VIF

(a)
S(t)

Input

First mixer
Filter

First IF

Second mixer

S(t)

Filter

t
First
LO
Frequency
synthesizer

Second LO

VIF

Second IF
Filter

Frequency
set commands

VRF

Demod
Output

Figure 2. Double superheterodyne VHF or UHF communication receiver.

(b)

Figure 4. Two switching mixers: (a) a simple switching mixer: (b)

a polarity-switching mixer. The IF is the product of the switching
waveform s(t) and the RF input, making these mixers a type of multiplier.

326

MIXER CIRCUITS

the switch changes the polarity of the RF voltage periodically.

The advantage of this mixer over the one in Fig. 4(a) is that
the LO waveform has no dc component, so the product of the
RF voltage and switching waveform does not include any voltage at the RF frequency. Thus, even though no filters are
used, the RF and LO ports of this mixer are inherently isolated. Doubly balanced mixers are realizations of the polarityswitching mixer.

SEMICONDUCTOR DEVICES FOR MIXERS

Only a few devices satisfy the practical requirements of mixer
operation. Any device used as a mixer must have strong
nonlinearity, electrical properties that are uniform between
individual devices, low noise, low distortion, and adequate
frequency response. The primary devices used for mixers are
Schottky-barrier diodes and field-effect transistors (FETs). Bipolar junction transistors (BJT) are also used occasionally,
primarily in Gilbert-cell multiplier circuits [see Fig. 6(d)], but
because of their superior large-signal-handling ability, higher
frequency range, and low noise, FET devices such as metal
oxidesemiconductor FETs (MOSFET), gallium arsenide
(GaAs) metalsemiconductor FETs (MESFET), and highelectron-mobility transistors (HEMTs) have been usually preferred.
The Schottky-barrier diode is the dominant device used in
mixers. Because Schottky-barrier diodes are inherently capable of fast switching, have very small reactive parasitics, and
do not need dc bias, they can be used in very broadband mixers. Schottky-barrier-diode mixers usually do not require
matching circuits, so no tuning or adjustment is needed.
Although mixers using Schottky-barrier diodes always exhibit conversion loss, transistor mixers are capable of conversion gain. This helps simplify the architecture of a system,
often allowing the use of fewer amplifier stages than necessary in diode-mixer receivers.
Since the 1950s, bipolar transistors have dominated mixer
applications as single-transistor mixers in AM radio and communication receivers. In particular, an analog multiplier consisting of a doubly balanced differential amplifier, called the
Gilbert cell, was invented in the 1960s. Since then, the Gilbert-cell mixer has been used as a monolithic integrated circuit (IC) for AM radio receivers and communication equipment. Silicon BJTs are used in mixers because of their low
cost and ease of implementation with monolithic ICs. These
bipolar devices are used as mixers when necessary for process
compatibility, although FETs generally provide better overall
performance. Silicon BJTs are usually used in conventional
single-device or singly and doubly balanced mixers. Progress
in the development of heterojunction bipolar transistors
(HBT), which use a heterojunction for the emitter-to-base
junction, may bring about a resurgence in the use of bipolar
devices as mixers. HBTs are often used as analog multipliers
operating at frequencies approaching the microwave range;
the most common form is a Gilbert cell. Silicongermanium
(SiGe) HBTs are a new technology that offers high performance at costs close to that of silicon BJTs.
A variety of types of FETs are used in mixers. Since the
1960s, silicon MOSFETs (often dual-gate devices) have dominated mixer applications in communication receivers up to
approximately 1 GHz. At higher frequency, GaAs MESFETs

are often used. The LO and RF signals can be applied to separate gates of dual-gate FETs, allowing good RF-to-LO isolation to be achieved in a single-device mixer. Dual-gate devices
can be used to realize self-oscillating mixers, in which a single
device provides both the LO and mixer functions.
Although silicon devices have distinctly lower transconductance than GaAs, they are useful up to at least the lower microwave frequencies. In spite of the inherent inferiority of silicon to GaAs, silicon MOSFETs do have some advantages. The
primary one is low cost, and the performance of silicon MOSFET mixers is not significantly worse than GaAs in the VHF
and UHF range. The high drain-to-source resistance of silicon
MOSFETs gives them higher voltage gain than GaAs devices;
in many applications this is a distinct advantage. Additionally, the positive threshold voltage (in an n-channel enhancement MOSFET), in comparison with the negative threshold
voltage of a GaAs FET, is very helpful in realizing low-voltage
circuits and circuits requiring only a single dc supply. Mixers
using enhancement-mode silicon MOSFETs often do not require gate bias, and dual-gate MOSFETs offer convenient LOto-RF isolation when the LO and RF are applied to different
gates.
A MESFET is a junction FET having a Schottky-barrier
gate. Although silicon MESFETs have been made, they are
now obsolete, and all modern MESFETs are fabricated on
GaAs. GaAs is decidedly superior to silicon for high-frequency
mixers because of its higher electron mobility and saturation
velocity. The gate length is usually less than 0.5 m, and may
be as short as 0.1 m; this short gate length, in conjunction
with the high electron mobility and saturation velocity of
GaAs, results in a high-frequency, low-noise device.
HEMTs are used for mixers in the same way as conventional GaAs FETs. Because the gate IV characteristic of a
HEMT is generally more strongly nonlinear than that of a
MESFET, HEMT mixers usually have greater intermodulation (IM) distortion than FETs. However the noise figure (NF)
of an HEMT mixer usually is not significantly lower than that
of a GaAs FET. An HEMT is a junction FET that uses a heterojunction (a junction between two dissimilar semiconductors), instead of a simple epitaxial layer, for the channel. The
discontinuity of the bandgaps of the materials used for the
heterojunction creates a layer of charge at the surface of the
junction; the charge density can be controlled by the gate voltage. Because the charge in this layer has very high mobility,
high-frequency operation and very low noise are possible. It
is not unusual for HEMTs to operate successfully as low-noise
amplifiers above 100 GHz. HEMTs require specialized fabrication techniques, such as molecular beam epitaxy, and thus
are very expensive to manufacture. HEMT heterojunctions
are invariably realized with IIIV semiconductors; AlGaAs
and InGaAs are common.
Passive Diode Mixers
Figure 5 shows the most common form of the three diodemixer types: a single-device diode mixer, a singly balanced
diode mixer, and a doubly balanced diode mixer. Conversion
loss of 6 to 8 dB is usually accepted in these passive mixers.
Active Transistor Mixers
Active transistor mixers have several advantages, and some
disadvantages, in comparison with diode mixers. Most sig-

MIXER CIRCUITS

Because transistors cannot be reversed, as can diodes, balanced transistor mixers invariably require an extra hybrid at
the IF. This can be avoided only by using a p-channel device
instead of an n-channel device, or vice versa; however, this is
possible only in silicon circuits, and even then the characteristics of p- and n-channel devices are likely to be significantly
different.

IF IF

RF RF

LO
LO
(a)

RF
IF

LO
(b)

LO

D2

D3

D1

D4

327

IF

RF
(c)
Figure 5. The three most common diode-mixer types: (a) single-device, (b) singly balanced, (c) doubly balanced.

nificantly, an active mixer can achieve conversion gain, while

diode and other passive mixers always exhibit loss. This
allows a system using an active mixer to have one or two
fewer stages of amplification; the resulting simplification is
especially valuable in circuits where small size and low cost
are vital. A precise comparison of distortion in diode and active transistor mixers is difficult to make because the comparison depends on the details of the system. Generally, however,
it is fair to say that distortion levels of well-designed active
mixers are usually comparable to those of diode mixers.
It is usually easy to achieve good conversion efficiency in
active mixers. Thus, active transistor mixers have gained a
reputation for low performance. Nevertheless, achieving good
overall performance in active transistor mixers is not difficult.

Bipolar Junction Transistor Mixers. Figure 6 shows BJT mixers: a single-device BJT mixer, a singly balanced BJT mixer,
a differential BJT mixer, and a doubly balanced BJT mixer.
In a single-device BJT mixer [Fig. 6(a)], the input signals
are introduced into the device through the RF LO diplexer,
which consists of an RF bandpass filter, an LO bandpass filter, and two strips, /4 long at the center of the RF and LO
frequency ranges; the square-law term of the devices characteristic provides the multiplication action. A single-device
BJT mixer achieves a conversion gain of typically 20 to 24 dB,
a noise figure of typically 4 to 5 dB (which is about 3 dB more
than that of the device in the amplifier at the RF), and a third
intercept point near 0 dBm. The IM product from this type of
single-device BJT mixer usually depends on its collector current, but when the supplied collector-to-emitter voltage, VCE,
is not enough (typically, below 1.2 V), the IM product increases as VCE decreases.
A singly balanced BJT upconversion mixer [Fig. 6(b)] consists of two BJTs interconnected by a balun or hybrid. The
two collectors are connected through a strip, /2 long at the
center of the LO frequency range, for reducing the LO leakage. This upconversion mixer exhibits 16 dB conversion gain
and 12 dB LO leakage suppression versus the wanted RF output level at 900 MHz.
A singly balanced BJT differential mixer [Fig. 6(c)] consists of an emitter-coupled differential pair. The RF is superposed on the tail current by ac coupling through capacitor
C2, and the LO is applied to the upper transistor pair, where
capacitive degeneration and ac coupling substantially reduce
the gain at low frequencies. Note that the circuit following
C2 is differential and hence much less susceptible to evenorder distortion.
A multiplier circuit [Fig. 6(d)] conceived in 1967 by Barrie
Gilbert and widely known as the Gilbert cell (though Gilbert
himelf was not responsible for his eponymy; indeed, he has
noted that a prior art search at the time found that essentially the same ideaused as a synchronous detector and
not as true mixerhad already been patented by H. Jones)
is usually used as an RF mixer and sometimes as a microwave mixer.
Ignoring the basewidth modulation, the relationship between the collector current IC and the base-to-emitter voltage
VBE for a BJT is



VBE
IC = IS exp
(2)
VT
where VT kT/q is the thermal voltage, k is Boltzmanns constant, T is absolute temperature in kelvin, and q is the charge
of an electron. IS is the saturation current for a graded-base
transistor.
Assuming matched devices, the differential output voltage
of the Gilbert cell is






VLO
VRF
VIF = RL IEE tanh
tanh
(3)
2VT
2VT

328

MIXER CIRCUITS

Matching
network
LO

Matching
network

RF

Q1

RF

4
LO

LPF

Matching
network

BPF

IF
IF

Q1

Q2

BPF

(b)

(a)

VCC

VCC

RL

RL

Vo
VIF

Q3

Q4
VLO

Q1

Q2

Q3

Q4

VLO

C2
VRF

Q1
Q5

Q5

VRF

C1
IO

(c)

(d)

Figure 6. BJT mixers: (a) a single-device BJT mixer, (b) a singly balanced BJT upconversion
mixer, (c) a singly balanced BJT differential mixer, (d) a doubly balanced BJT mixer consisting
of a Gilbert cell.

For small inputs,

VIF

RL IEE
V V
4VT2 RF LO

(4)

The product VRFVLO is obtained by the Gilbert cell at small

signals.
FET Mixers. Figure 7 shows FET mixers: a single-device
FET mixer, a dual-gate FET mixer, a singly balanced FET
mixer, a differential FET mixer, and a doubly balanced FET
mixer.
In a single-device FET mixer [Fig. 7(a)], the RFLO
diplexer must combine the RF and LO and also provide
matching between the FETs gate and both ports. The IF filter

must provide an appropriate impedance to the drain of the

FET at the IF and must short-circuit the drain at the RF and
especially at the LO frequency and its harmonics.
The configuration of a dual-gate mixer [Fig. 7(b)] provides
the best performance in most receiver applications. In this
circuit, the LO is connected to the gate closest to the drain
(gate 2), while the RF is connected to the gate closest to the
source (gate 1). An IF bypass filter is used at gate 2, and an
LORF filter is used at the drain. A dual-gate mixer is usually realized as two single-gate FETs in a cascade connection.
A singly balanced FET mixer [Fig. 7(c)] uses a transformer
hybrid for the LO and RF; any appropriate type of hybrid can
be used. A matching circuit is needed at the gates of both
FETs. The IF filters provide the requisite short circuits to the
drains at the LO and RF frequencies, and additionally pro-

MIXER CIRCUITS

329

IF bypass
IF
matching

RF

LO RF
diplexer

IF
filter

IF

LO

LO
matching

G2

RF

RF
matching

G1

IF

D
LO & RF
bypass
S

LO
(a)

(b)
IF

IF LPF
MC

IF
balun
IF

LO
LO

LO
balun
RF

MC
RF
(d)

(c)
IF
IF
balun

LO

LO
balun

RF

RF
balun
(e)

vide IF load impedance transformations. The singly balanced

mixer of Fig. 7(c) is effectively two single-device mixers interconnected by hybrids.
In a differential FET mixer [Fig. 7(d)], the RF is applied to
the lower FET, and the LO is applied through a balun or hybrid to the upper FETs. This mixer operates as an alternating
switch, connecting the drain of the lower FET alternately to
the inputs of the IF balun. An LO matching circuit may be
needed. Because the RF and LO circuits are separate, the
gates of the upper FETs can be matched at the LO frequency,
and there is no tradeoff between effective LO and RF matching. Similarly, the lower FET can be matched effectively at
the RF. An IF filter is necessary to reject LO current.
A doubly balanced FET mixer [Fig. 7(e)] is frequently used
as an RF or microwave mixer. Like many doubly balanced

Figure 7. FET mixers: (a) a single-device FET mixer, (b) a dual-gate

FET mixer, (c) a singly balanced FET mixer, (d) a differential mixer,
(e) a doubly balanced mixer.

mixers, this mixer consists of two of the singly balanced mixers shown in Fig. 7(d). Each half of the mixer operates in the
same manner as that of Fig. 7(d). The interconnection of the
outputs, however, causes the drains of the upper four FETs
to be virtual grounds for both LO and RF, as well as for evenorder spurious responses and IM products.

IMAGE-REJECTION MIXERS
The image-rejection mixer (Fig. 8) is realized as the interconnection of a pair of balanced mixers. It is especially useful for
applications where the image and RF bands overlap, or the
image is too close to the RF to be rejected by a filter. The LO
ports of the balanced mixers are driven in phase, but the sig-

330

MIXER CIRCUITS
RF

IF

90
RF

LO

90
hybrid

90
hybrid

LO

LO

90
hybrid

USB
LSB

0
RF

IF

Figure 8. Image-rejection mixer.

nals applied to the RF ports have 90 phase difference. A 90

IF hybrid is used to separate the RF and image bands. A full
discussion of the operation of such mixers is a little complicated.
The most difficult part of the design of an image-rejection
mixer is the IF hybrid. If the IF is fairly high, a conventional
RF or microwave hybrid can be used. However, if the mixer
requires a baseband IF, the designer is placed in the problematical position of trying to create a Hilbert-transforming filter,
a theoretical impossibility. Fortunately, it is possible to approximate the operation of such a filter over a limited bandwidth.
MIXING
A mixer is fundamentally a multiplier. An ideal mixer multiplies a signal by a sinusoid, shifting it to both a higher and a
lower frequency, and selects one of the resulting sidebands. A
modulated narrowband signal, usually called the RF signal,
represented by
SRF (t) = a(t) sin(st) + b(t) cos(st)

+ 12 b(t) cos[(s + p )t] + cos[(s p )t]

Mixers using Schottky-barrier diodes are passive components

and consequently exhibit conversion loss. This loss has a
number of consequences: the greater the loss, the higher the
noise of the system and the more amplification is needed.
High loss contributes indirectly to distortion because of high
signal levels that result from the additional preamplifier gain
required to compensate for this loss. It also contributes to the
cost of the system, since the necessary low-noise amplifier
stages are usually expensive.
Mixers using active devices often (but not always) exhibit
conversion gain. The conversion gain (CG) is defined as
CG =

IF power available at mixer output

RF power available to mixer input

(8)

High mixer gain is not necessarily desirable, because it reduces stability margins and can increase distortion. Usually,
a mixer gain of unity, or at most a few decibels, is best.
Noise

(6)

to obtain the IF signal

SIF (t) = 12 a(t) sin[(s + p )t] + sin[(s p )t]}

Conversion Efficiency

(5)

is multiplied by the LO signal function

f LO (t) = cos(pt)

the types of mixers we shall examine inherently reject images, it is possible to create combinations of mixers and hybrids that do reject the image response.
It is important to note that the process of frequency shifting, which is the fundamental purpose of a mixer, is a linear
phenomenon. Although nonlinear devices are invariably used
for realizing mixers, there is nothing in the process of frequency shifting that requires nonlinearity. Distortion and
spurious responses other than the sum and difference frequency, though often severe in mixers, are not fundamentally
required by the frequency-shifting operation that a mixer performs.

(7)

In the ideal mixer, two sinusoidal IF components, called

mixing products, result from each sinusoid in s(t). In receivers, the difference-frequency component is usually desired,
and the sum-frequency component is rejected by filters.
Even if the LO voltage applied to the mixers LO port is a
clean sinusoid, the nonlinearities of the mixing device distort
it, causing the LO function to have harmonics. Those nonlinearities can also distort the RF signal, resulting in RF harmonics. The IF is, in general, the combination of all possible mixing products of the RF and LO harmonics. Filters are usually
used to select the appropriate response and eliminate the
other (so-called spurious) responses.
Every mixer, even an ideal one, has a second RF that can
create a response at the IF. This is a type of spurious response, and is called the image; it occurs at the frequency
2f LO f RF. For example, if a mixer is designed to convert 10
GHz to 1 GHz with a 9 GHz LO, the mixer will also convert
8 GHz to 1 GHz at the same LO frequency. Although none of

In a passive mixer whose image response has been eliminated

by filters, the noise figure is usually equal to, or only a few
tenths of a decibel above, the conversion loss. In this sense,
the mixer behaves as if it were an attenuator having a temperature equal to or slightly above the ambient.
In active mixers, the noise figure cannot be related easily
to the conversion efficiency; in general, it cannot even be related qualitatively to the devices noise figure when used as
an amplifier. The noise figure (NF) is defined by the equation
NF =

input signal-to-noise power ratio

output signal-to-noise power ratio

(9)

The sensitivity of a receiver is usually limited by its internally generated noise. However, other phenomena sometimes
affect the performance of a mixer front end more severely
than noise. One of these is the AM noise, or amplitude noise,
from the LO source, which is injected into the mixer along
with the LO signal. This noise may be especially severe in a
single-ended mixer (balanced mixers reject AM LO noise to
some degree) or when the LO signal is generated at a low
level and amplified.
Phase noise is also a concern in systems using mixers. LO
sources always have a certain amount of phase jitter, or phase
noise, which is transferred degree for degree via the mixer to
the received signal. This noise may be very serious in communications systems using either digital or analog phase modu-

MIXER CIRCUITS

RF in

RF
filter

LNA

Image
rejection
filter

Mixer

S(f )
IF
filter

IF
stage

LO

f2 f1

Figure 9. RF front end.

NG2 1 NF3 1
NFn 1
+
+ + n
G1
G1 G2
1 Gn

f1 f2
2f1 f2

lation. Spurious signals may also be present, along with the

desired LO signal, especially if a phase-locked-loop frequency
synthesizer is used in the LO source. Spurious signals are
usually phase-modulation sidebands of the LO signal, and,
like phase noise, are transferred to the received signal. Finally, the mixer may generate a wide variety of intermodulation products, which allow input signalseven if they are not
within the input passbandto generate spurious output at
the IF. These problems must be circumvented if a successful
receiver design is to be achieved.
An ideal amplifier would amplify the incoming signal and
incoming noise equally and would introduce no additional
noise. From Eq. (9) such an amplifier would have a noise figure equal to unity (0 dB).
The noise figure of several cascaded amplifier stages is
NF = NF1 +

331

(10)

where NF is the total noise figure, NFn is the noise figure of

the nth stage, and Gn is the available gain of the nth stage.
From Eq. (10), the gain and noise figure of the first stage
of a cascaded chain will largely determine the total noise figure. For example, the system noise figure (on a linear scale)
for the downconverter shown in Fig. 9 is


NFLNA 1
1
1
1
NF =
+
+
1
LRF
LRF
LRF GLNA LIM



1
NFM LI
NFM 1
+ =
+
NFLNA +
+
LRF GLNA LI
LRF
GLNA LI
(11)

2f1

2f2

f2 + f1

2f1 f1

3f1

3f2

2f1 + f2 2f2 + f1

Figure 10. IF spectrum of intermodulation products up to third order. The frequencies f 1 and f 2 are the excitation.

nents, however, mixers often employ strongly nonlinear devices to provide mixing. Because of these strong nonlinearities, mixers generate high levels of distortion. A mixer is
usually the dominant distortion-generating component in a
receiver.
Distortion in mixers, as with other components, is manifested as IM distortion (IMD), which involves mixing between
multiple RF tones and harmonics of those tones. If two RF
excitations f 1 and f 2 are applied to a mixer, the nonlinearities
in the mixer will generate a number of new frequencies, resulting in the IF spectrum shown in Fig. 10. Figure 10 shows
all intermodulation products up to third order; by nth order,
we mean all n-fold combinations of the excitation tones (not
including the LO frequency). In general, an nth-order nonlinearity gives rise to distortion products of nth (and lower)
order.
An important property of IMD is that the level of the nthorder IM product changes by n decibels for every decibel of
change in the levels of the RF excitations. The extrapolated
point at which the excitation and IMD levels are equal is
called the nth-order IM intercept point, abbreviated IPn. This
dependence is illustrated in Fig. 11. In most components, the
intercept point is defined as an output power: in mixers it is
traditionally an input power.

10

Bandwidth
The bandwidth of a diode mixer is limited by the external
circuit, especially by the hybrids or baluns used to couple the
RF and LO signals to the diodes. In active mixers, bandwidth
can be limited either by the device or by hybrids or matching
circuits that constitute the external circuit; much the same
factors are involved in establishing active mixers bandwidths
as amplifiers bandwidths.
Distortion
It is a truism that everything is nonlinear to some degree and
generates distortion. Unlike amplifiers or passive compo-

Intercept
point

0
POUT dBm

where LRF and LI are the insertion losses of the RF filter and
the image-rejection filter, respectively, NFLNA and NFM are the
noise figures of the LNA and the mixer, respectively, and
GLNA is the power gain of the LNA. This equation assumes
that the noise figures of the filters are the same as their insertion losses.

10

Linear output
level
IM output
level

20

30
20 Pl

10

PI 0

IPn 10

20

Pin, dbm
Figure 11. The output level of each nth-order IM product varies n
decibels for every decibel change in input level. The intercept point is
the extrapolated point at which the curves intersect.

332

MIXER CIRCUITS

Given the intercept point IPn and input power level in decibels, the IM input level PI in decibels can be found from
PI =




1
1
P1 + 1
IPn
n
n

V( ), I( )

(12)
0

where Pl is the input level of each of the linear RF tones

(which are assumed to be equal) in decibels. By convention,
Pl and PI are the input powers of a single frequency component where the linear output level and the level of the nthorder IM product are equal; They are not the total power of
all components. For example, Pl is the threshold level for a
receiver. The fluctuation of the IMD level is rather small in
spite of the fluctuations of Pl and IPn.
Spurious Responses
A mixer converts an RF signal to an IF signal. The most common transformation is
f IF = f RF f LO

(13)

although others are frequently used. The discussion of frequency mixing indicated that harmonics of both the RF and
LO could mix. The resulting set of frequencies is
f IF = m f RF nf LO

(14)

where m and n are integers. If an RF signal creates an inband IF response other than the desired one, it is called a
spurious response. Usually the RF, IF, and LO frequency
ranges are selected carefully to avoid spurious responses, and
filters are used to reject out-of-band RF signals that may
cause in-band IF responses. IF filters are used to select only
the desired response.
Many types of balanced mixers reject certain spurious responses where m or n is even. Most singly balanced mixers
reject some, but not all, products where m or n (or both) are
even.
Harmonic Mixer
A mixer is sensitive to many frequencies besides those at
which it is designed to operate. The best known of these is
the image frequency, which is found at the LO sideband opposite the input, of the RF frequency. The mixer is also sensitive
to similar sidebands on either side of each LO harmonic.
These responses are usually undesired; the exception is the
harmonic mixer, which is designed to operate at one or more
of these sidebands.
When a small-signal voltage is applied to the pumped diode at any one of these frequencies, currents and voltages are
generated in the junction at all other sideband frequencies.
These frequencies are called the small-signal mixing frequencies n and are given by the relation
n = 0 + np

(15)

where p is the LO frequency and

n = , 3, 2, 1, 0, 1, 2, 3, . . .

(16)

1 p 1

2 2p 2

Figure 12. Small-signal mixing frequencies n and LO harmonics

np. Voltage and current components exist in the diode at these frequencies.

These frequencies are shown in Fig. 12. The frequencies are

separated from each LO harmonic by 0, the difference between the LO frequency and the RF.
MODULATION AND FREQUENCY TRANSLATION
Modulation
Modulation is the process by which the information content
of an audio, video, or data signal is transferred to an RF carrier before transmission. Commonly, the signal being modulated is a sine wave of constant amplitude and is referred to
as the carrier. The signal that varies some parameter of the
carrier is known as the modulation signal. The parameters of
a sine wave that may be varied are the amplitude, the frequency, and the phase. Other types of modulation may be applied to special signals, e.g., pulse-width and pulse-position
modulation of recurrent pulses. The inverse process
recovering the information from an RF signalis called demodulation or detection. In its simpler forms a modulator
may cause some characteristic of an RF signal to vary in direct proportion to the modulating waveform: this is termed
analog modulation. More complex modulators digitize and encode the modulating signal before modulation. For many applications digital modulation is preferred to analog modulation.
A complete communication system (Fig. 13) consists of an
information source, an RF source, a modulator, an RF channel (including both transmitter and receiver RF stages, the
antennas, the transmission path, etc.), a demodulator, and an
information user. The system works if the information user
receives the source information with acceptable reliability.
The designers goal is to create a low-cost working system
that complies with the legal restrictions on such things as
transmitter power, antenna height, and signal bandwidth.
Since modulation demodulation schemes differ in cost, bandwidth, interference rejection, power consumption, and so
forth, the choice of the modulation type is an important part
of communication system design.
Modulation, demodulation (detection), and heterodyne action are very closely related processes. Each process involves
generating the sum and/or difference frequencies of two or
more sinsuoids by causing one signal to vary as a direct function (product) of the other signal or signals. The multiplication of one signal by another can only be accomplished in a
nonlinear device. This is readily seen by considering any network where the output signal is some function of the input
signal e1, for example,
e0 = f (e1 )

(17)

MIXER CIRCUITS

RF source

Modulator

RF channel

Information
user

Demodulator

Information
source

Figure 13. Conceptual diagram of a communication system.

In any perfectly linear network, this requires that

e0 = ke1

(18)

and, assuming two different input signals,

e0 = k(Ea cos at + Eb cos bt)

(19)

where k is a constant. In this case the output signal contains

only the two input-signal frequencies. However, if the output
is a nonlinear function of the input, it can, in general, be represented by a series expansion of the input signal. For example, let
e0 = k1 e1 + k2 e22 + k3 e33 + + kn enn

(20)

When e1 contains two frequencies, e0 will contain the input

frequencies and their harmonics plus the products of these
frequencies. These frequency products can be expressed as
sum and difference frequencies. Thus, all modulators, detectors, and mixers are of necessity nonlinear devices. The principal distinction between these devices is the frequency differences between the input signals and the desired output signal
or signals. For example, amplitude modulation in general involves the multiplication of a high-frequency carrier by lowfrequency modulation signals to produce sideband signals
near the carrier frequency. In a mixer, two high-frequency
signals are multiplied to produce an output signal at a frequency that is the difference between the input-signal frequencies. In a detector for amplitude modulation, the carrier
is multiplied by the sideband signals to produce their different frequencies at the output.
To understand the modulation process, it is helpful to visualize a modulator as a black box (Fig. 14) with two inputs
and one output connected to a carrier oscillator producing a
sinusoidal voltage with constant amplitude and frequency
f RF. The output is a modulated waveform
F (t) = A(t) cos[st + (t)] = A(t) cos (t)

Oscillator
( fRF)

Modulator

333

F(t)

Modulated
signal

vm(t)
Modulating voltage
Figure 14. Black-box view of a modulator.

(21)

whose amplitude A(t) or angle (t), or both, are controlled by

vm(t). In amplitude modulation (AM) the carrier envelope
A(t) is varied while (t) remains constant; in angle modulation A(t) is fixed and the modulating signal controls (t).
Angle modulation may be either frequency modulation (FM)
or phase modulation (PM), depending upon the relationship
between the angle (t) and the modulation signal.
Although the waveform (21) might be called a modulated
cosine wave, it is not a single-frequency sinusoid when modulation is present. If either A(t) or (t) varies with time, the
spectrum of F(t) will occupy a bandwidth determined by both
the modulating signal and the type of modulation used.

Amplitude Modulation. Amplitude modulation in the form

of onoff keying of radio-telegraph transmitters is the oldest
type of modulation. Today, amplitude modulation is widely
used for those analog voice applications that require simple
receivers (e.g., commercial broadcasting) and require narrow
bandwidths.
In amplitude modulation the instantaneous amplitude of
the carrier is varied in proportion to the modulating signal.
The modulating signal may be a single frequency, or, more
often, it may consist of many frequencies of various amplitudes and phases, e.g., the signals constituting speech. For a
carrier modulated by a single-frequency sine wave of constant
amplitude, the instantaneous signal e(t) is given by
e(t) = E(1 + m cos m t) cos(ct + )

(22)

where E is the peak amplitude of unmodulated carrier, m is

the modulation factor as defined below, m is the frequency of
the modulating voltage (radians per second), c is the carrier
frequency (radians per second), and is the phase angle of
the carrier (radians).
The instantaneous carrier amplitude is plotted as a function of time in Fig. 15. The modulation factor m is defined for
asymmetrical modulation in the following manner:

m=

Emax E
E

(upward or positive modulation)

m=

E Emin
E

(downward or negative modulation)

(23)

(24)

The maximum downward modulation factor, 1.0, is reached

when the modulation peak reduces the instantaneous carrier
envelope to zero. The upward modulation factor is unlimited.

334

MIXER CIRCUITS
e(t)
Emax

Emin

e(t) = Ec cos

Modulation envelope

Figure 15. Amplitude-modulated carrier.

The modulation carrier described by Eq. (22) can be rewritten as follows:

e(t) = E(1 + m cos m t) cos(ct + )

= E cos(ct + ) +

mE
cos[(c + m )t + ]
2

Angle Modulation. Information can be transmitted on a

carrier by varying any of the parameters of the sinusoid in
accordance with the modulating voltage. Thus, a carrier is
described by

where ct .
This carrier can be made to convey information by modulating the peak amplitude Ec or by varying the instantaneous
phase angle of the carrier. This type of modulation is known
as angle modulation. The two types of angle modulation that
have practical application are phase modulation (PM) and frequency modulation (FM).
In phase modulation, the instantaneous phase angle of
the carrier is varied by the amplitude of the modulating signal. The principal application of phase modulation is in the
utilization of modified phase modulators in systems that
transmit frequency modulation. The expression for a carrier
phase-modulated by a single sinusoid is given by

(25)

mE
cos[(c m )t + ]
+
2
Thus, the amplitude modulation of a carrier by a cosine wave
has the effect of adding two new sinusoidal signals displaced
in frequency from the carrier by the modulating frequency.
The spectrum of the modulated carrier is shown in Fig. 16.

e(t) = Ec cos(ct + +  cos m t)

Em
2

1 d
2 dt

m m

m
c
Frequency

m + m

(a)

(29)

where f is the peak frequency deviation introduced by modulation. The instantaneous total phase angle is given by

= 2 f dt + 0
(30)
= 2 f RFt +

(28)

When the carrier is frequency-modulated by a single sinusoid,

f = f RF +  f cos mt

(27)

where is the peak value of phase variation introduced by

modulation and is called the phase deviation, and m is the
modulation frequency (radians per second).
In frequency modulation, the instantaneous frequency of
the carrier, that is, the time derivative of the phase angle
, is made to vary in accordance with the amplitude of the
modulating signal. Thus,
f =

Em
2

(26)

f
sin 2 f m t + 0
fm

(31)

The complete expression for a carrier that is frequency-modulated by a single sinusoid is


f
e(t) = Ec cos tc +
sin 2 f mt + 0
fm

0
Spectrum of
modulating signal

Frequency

Spectrum of modulated carrier

(b)

Figure 16. Frequency spectrum of an amplitude-modulated carrier:

(a) carrier modulated by a sinusoid of frequency m, (b) carrier modulated by a complex signal composed of several sinusoids.

(32)

The maximum frequency difference between the modulated carrier and the unmodulated carrier is the frequency
deviation f. The ratio of f to the modulation frequency f m
is known as the modulation index or the deviation ratio. The
degree of modulation in an FM system is usually defined as
the ratio of f to the maximum frequency deviation of which
the system is capable. Degree of modulation in an FM system
is therefore not a property of the signal itself.
In digital wireless communication systems, Gaussianfiltered minimum-shift keying (GMSK) is the most popular,
and four-level frequency-shift keying (4-FSK) and /4-shifted

MIXER CIRCUITS

335

differential encoded quadriphase (or quadrature) phaseshift keying (/4-DQPSK) are also used. GMSK and 4-FSK
are both frequency modulation, but /4-DQPSK is phase modulation.
Pulse Modulation. In pulse-modulated systems, one or more
parameters of the pulse are varied in accordance with a modulating signal to transmit the desired information. The modulated pulse train may in turn be used to modulate a carrier
in either angle or amplitude. Pulse modulation provides a
method of time duplexing, since the entire modulation information of a signal channel can be contained in a single pulse
train having a low duty cycle, i.e., ratio of pulse width to interpulse period, and therefore the time interval between successive pulses of a particular channel can be used to transmit
pulse information from other channels.
Pulse-modulation systems can be divided into two basic
types: pulse modulation proper, where the pulse parameter
which is varied in accordance with the modulating signal is a
continuous function of the modulating signal, and quantized
pulse modulation, where the continuous information to be
transmitted is approximated by a finite number of discrete
values, one of which is transmitted by each single pulse or
group of pulses. The two methods are illustrated in Fig. 17.

Modulation of
pulse parameter

Modulating signal

Quantized pulse code groups

Figure 18. Example of a quantized pulse-modulation system.

In quantized pulse modulation systems, the input function

can be approximated with arbitrary accuracy by increase of
the number of discrete values available to describe the input
function. An example of a quantized pulse modulation system
is shown in Fig. 18: the information is transmitted in pulse
code groups, the sequence of pulses sent each period indicating a discrete value of the modulating signal at that instant.
Typically, the pulse group might employ a binary number
code, the presence of each pulse in the group indicating a 1
or 0 in the binary representation of the modulating signal.
The principal methods for transmitting information by
means of unquantized pulse modulation are pulse-amplitude
modulation (PAM; see Fig. 19), pulse-width modulation
(PWM), and pulse-position modulation (PPM).
Frequency Translation

Instantaneous
modulating signal

The most common form of radio receiver is the superheterodyne configuration shown in Fig. 20(a). The signal input, with
a frequency s, is usually first amplified in a tunable bandpass amplifier, called the RF amplifier, and is then fed into a
circuit called the mixer along with an oscillator signal, which
is local to the receiver, having a frequency p. The LO is also

Modulating signal

(a)

Pulse train

Modulation of
pulse parameter
(a)

Instantaneous
modulating signal

0
fm

(b)
Figure 17. Input versus output relationships of quantized and unquantized pulse-modulation systems: (a) unquantized modulation
system, (b) quantized modulation system.

1
T

2
T

3
T

4
T

5
6
7
T T T
Frequency

8
T

9
T

10 11
T T

(b)
Figure 19. Pulse-amplitude modulation: (a) amplitude-modulated
pulse train, (b) frequency spectrum of the modulated pulse train.

336

MIXER CIRCUITS

RF
amp.

Mixer

s p

IF
amp.

Demod.

Audio
amp.

s
Coupled
tuning

Local
oscill.
(a)

fm
Figure 20. (a) The superheterodyne configuration; frequency spectra of (b) the input and (c) the multiplier output.

fRF fm fRF fRF + fm

Vs = Es cos(st)
Vp = Ep cos(pt)

(33)
(34)

If the multiplier (mixer) has a gain constant K, the output is

Vo =

K
Es Ep [cos(s p )t + cos (s + p )t]
2

(35)

The difference frequency, s p, is denoted by if .

If the input is a modulated signal, the modulation also is
translated to a band about the new carrier frequency, if . For
example, if the input is amplitude-modulated,

Vs = Es (1 + m cos mt) cos st

m
= Es cos(st) + Es cos(s m )t
2
m
+ Ep cos (s + m )t
2

(36)

fm

fRF fLO

fm

fRF + fLO
(c)

(b)

tunable and is ganged with the input bandpass amplifier so

that the difference between the input signal frequency and
that of the LO is constant.
In operation, the mixer must achieve analog multiplication. With multiplication, sum and difference frequency components at s p are produced at the output of the mixer.
Usually, the sum frequency is rejected by sharply tuned circuits and the difference frequency component is subsequently
amplified in a fixed-tuned bandpass amplifier. The difference
frequency is called the intermediate frequency (IF), and the
fixed-tuned amplifier is called the IF amplifier. The advantage of this superheterodyne configuration is that most amplification and outband rejection occurs with fixed-tuned circuits, which can be optimized for gain level and rejection.
Another advantage is that the fixed-tuned amplifier can provide a voltage-controlled gain to achieve automatic gain control (AGC) with input signal level. In high-performance and/
or small-size receivers, the filtering in the IF amplifier is obtained with electromechanical crystal filters.
To formalize the mixer operation, assume that both the
input signal and the local oscillator output are unmodulated,
single-tone sinusoids:

fm

The input can be represented as in Fig. 20(b), with the carrier

frequency term and an upper and a lower sideband, each sideband containing the modulation information.
For a linear multiplier, each of the input components is
multiplied by the LO input, and the output of the multiplier
contains six terms, as shown in Fig. 20(c): the difference-frequency carrier with two sidebands and the sum-frequency
carrier with two sidebands. The latter combination is usually
rejected by the bandpass of the IF amplifier.
ANALOG MULTIPLICATION
An analog multiplier can be used as a mixer. A multiplier
inputs two electrical quantities, usually voltages but sometimes currents, and outputs the product of the two inputs,
usually currents but sometimes voltages. The product of two
quantities is derived from only the second-order term of the
transfer characteristic of the element, because the product
xy can be derived from only the second term of (x y)2. The
second-order term is, for example, obtained from the inherent
exponential law for a bipolar transistor or the inherent
square law for a MOS transistor.
There are three methods of realizing analog multipliers:
the first is by cross-coupling two variable-gain cells, the second is by cross-coupling two squaring circuits, and the third
is by using a multiplier core. Block diagrams of these three
multiplication methods are shown in Fig. 21(ac). For example, the bipolar doubly balanced differential amplifier, the socalled Gilbert cell, is the first case, and utilizes two-quadrant
analog multipliers as variable-gain cells. The second method
has been known for a long time and is called the quartersquare technique. The third method is also based on the quarter-square technique, because a multiplier core is a cell consisting of the four properly combined squaring circuits.
Multipliers Consisting of Two Cross-Coupled Variable-Gain Cells
The Gilbert Cell. The Gilbert cell, shown in Fig. 22, is the
most popular analog multiplier, and consists of two cross-coupled, emitter-coupled pairs together with a third emitter-coupled pair. The two cross-coupled, emitter-coupled pairs form
a multiplier cell. The Gilbert cell consists of two cross-coupled

MIXER CIRCUITS
I
I+
+

ogies. The operating frequency of the Gilbert cell was 500

MHz at most in the 1960s.
The series connection of the two cross-coupled, emittercoupled pairs with a third emitter-coupled pair requires a
high supply voltage, more than 2.0 V. Therefore, many circuit
design techniques for linearizing the low-voltage Gilbert cell
have also been discussed.

+
+
Variable
gain cell

Vx

Vy

+
+
Variable
gain cell

(a)
+

I+

X2

Vx

+
Vy

+
X2

(b)
+
Vx

+
Vy

Modified Gilbert Cell with a Linear Transconductance Amplifier. The modified Gilbert cell with a linear transconductance amplifier in Fig. 23 possesses a linear transconductance
characteristic only with regard to the second input voltage
Vy, because it utilizes a linear transconductance amplifier for
the lower stage. Low-voltage operation is also achieved using
the differential current source output system of two emitterfollower-augmented current mirrors. The general structure of
the mixer is a Gilbert cell with a linear transconductance amplifier, since the cross-coupled emitter-coupled pairs that input the LO signal possess a limiting characteristic. To achieve
the desired low distortion, the differential pair normally used
as the lower stage of the cell is replaced with a superlinear
transconductance amplifier. In practice, the linear input voltage range of the superlinear transconductance amplifier at a
1.9 V supply voltage is 0.9 V peak to peak for less than 1%
total harmonic distortion (THD) or 0.8 V for less than 0.1%
THD.
The differential output current of the modified Gilbert cell
with a linear transconductance amplifier is

I = I + I = (IC1 + IC3 ) (IC2 + IC4 )


Vx
= 2GyVy tanh
2VT

I+

+
Four-transistor
multiplier core

Input stage

337

(38)

(c)

VCC

Figure 21. Multiplier block diagrams: (a) built from two cross-coupled variable-gain cells, (b) built from two cross-coupled squaring circuits, (c) built from a multiplier core and an input system.

RL

variable-gain cells, because the lower emitter-coupled pair

varies the transconductance of the upper cross-coupled, emitter-coupled pairs.
Assuming matched devices, the differential output current
of the Gilbert cell is expressed as

I = I + I = (IC13 + IC15 ) (IC14 + IC16 )





Vx
Vy
= F2 I0 tanh
tanh
2VT
2VT

Q1

RL

Q2

Q3

Q4

Vx

(37)

where F is the dc common-base current gain factor.

The differential output current of the Gilbert cell is expressed as a product of two hyperbolic tangent functions.
Therefore, the operating input voltage ranges of the Gilbert
cell are both very narrow. Many circuit design techniques for
linearizing the input voltage range of the Gilbert cell have
been discussed to achieve wider input voltage ranges.
In addition, the Gilbert cell has been applied to ultra-highfrequency (UHF) bands of some tens of gigahertz using GaAs
heterojunction bipolar transistor (HBT) and InP HBT technol-

Q5

Q6

Vy

Io

Figure 22. Gilbert cell.

338

MIXER CIRCUITS
VCC

Io

Io

Q8

RL

RL

Q11

Q5

Q6

Q1

Q2

Q4

Vy

Vx

Ry

Q7

Q10

RE

Q12

RE

RE

Q9

RE

Figure 23. Modified Gilbert cell with a

linear transconductance amplifier.

where Gy 1/Ry and the dc common-base current gain factor

F is taken as equal to one for simplification, since its value
is 0.98 or 0.99 in current popular bipolar technology.
The product of the hyperbolic tangent function of the first
input voltage and the second input voltage of the linear transconductance amplifier is obtained.
Quarter-Square Multipliers Consisting
of Two Cross-Coupled Squaring Circuits
To realize a multiplier using squaring circuits the basic
idea is based on the identity (x y)2 (x y)2 4xy or
(x y)2 x2 y2 2xy. The former identity is usually expressed as
1
[(x +
4

y)2 (x y)2 ] = xy

(39)

The quarter-square technique based on the above identity has

been well known for a long time.
The two input voltage ranges and the linearity of the
transconductances of the quarter-square multiplier usually
depend on the square-law characteristics of the squaring circuits and sometimes depend on the linearities of the adder
and subtractor in the input stage. A quarter-square multiplier does not usually possess limiting characteristics with regard to both inputs.
Four-Quadrant Analog Multipliers with a Multiplier Core
The multiplier core can be considered as four properly combined square circuits. The multiplication is based on the identity

 2



1
y
(ax + by)2 + (a c)x + b
c
(40)
 2



1
2
y = 2xy
[(a c)x + by] ax + b
c
where a, b, and c are constants.

If each squaring circuit is a square-law element with another parameter z, the identity becomes


2



1
y+z
(ax + by + z)2 + (a c)x + b
c
[(a c)x + by + z]2

2



1
y + z = 4xy
ax + b
c

(41)

In Eqs. (40) and (41), the parameters a, b, c, and z can be

canceled out.
MOS transistors operating in the saturation region can be
used as square-law elements. Four properly arranged MOS
transistors with two properly combined inputs produce the
product of two inputs in accordance with Eq. (22). Also, four
properly arranged bipolar transistors with two properly combined inputs produce the product of the hyperbolic functions
of the inputs. A cell consisting of four emitter- or source-common transistors biased by a single cell tail current can be
used as a multiplier core.
Bipolar Multiplier Core. Figure 24(a) shows a bipolar multiplier core. The individual input voltages applied to the bases
of the four transistors in the core can be expressed as V1
aVx bVy VR, V2 (a 1)Vx (b 1)Vy VR, V3 (a
1)Vx bVy VR, V4 aVx (b 1)Vy VR. The differential
output current is expressed as

I = I + I = (IC1 + IC2 ) (IC3 + IC4 )





Vx
Vy
= F I0 tanh
tanh
2VT
2VT

(42)

The parameters a and b are canceled out. The transfer function of the bipolar multiplier core is expressed as the product
of the two transfer functions of the emitter-coupled pairs. The
difference between Eq. (42) and Eq. (38) is only in whether
the tail current value is multiplied by the parameter F or by

MIXER CIRCUITS

I
I+

Q1

Q2

Q3

Q4

aVx bVy

aVx + (b 1)Vy

(a 1)Vx + (b 1)Vy

(a 1)Vx + bVy

Io

VR

(a)
VCC
RL

RL

VM1

VM2

Q1

Q2

Q3

Q4

Vx + Vx

Vx

Vy

Io

VR

(b)
I
I+

Vx

R
Q1

Vy

Q2

Q3

Q4
R

VR

Io

(c)
Figure 24. Bipolar multiplier: (a) general circuit diagram of core, (b) the core with the simplest
combination of the two input voltages, (c) the bipolar multiplier consisting of a multiplier core
and resistive dividers.

339

I
I+

I
M3

M1
aVx + bVy
Vx

(a c)Vx + (b

V1
1
c

M1
V2

)Vy

M2 M3

M4
V3

V4

(a c)Vx + bVy
aVx + (b

Vy

1
c )V y

Io

Input system

Multiplier core
(a)
I
I+

I
M4

M1
M2 M4
Vx + Vx

Vx
Vy
VR

Io

(b)
VDD
M9

M10
M11

M12
I

M4

M5

M6

M3

M1

M2

M8

M7

Vx

Vx

VR

Ioo

Io

Ioo

(c)

Figure 25. MOS multiplier: (a) general circuit diagram of core (b) the core with the simplest
combination of the two input voltages, (c) MOS multiplier consisting of the multiplier core and
an active voltage adder.
340

MIXER CIRCUITS

Transmit

Info.
source

Baseband
data
signal

Receive

Data
modulator

Data
modulator

Frequency
synthesizer

341

Info.
source

Frequency
synthesizer

Figure 26. Block diagram of communications system, showing modulation and demodulation.

its square. Therefore, a bipolar multiplier core consisting of a

quadritail cell is a low-voltage version of the Gilbert cell.
Simple combinations of two inputs are obtained when a
b 
, a 
and b 1, and a b 1 as shown in Fig. 24(b).
In particular, when a b 1, resistive voltage adders are
applicable because no inversion of the signals Vx and Vy is
needed [Fig. 24(c)].
MOS Multiplier Core. Figure 25(a) shows the MOS fourquadrant analog multiplier consisting of a multiplier core. Individual input voltages applied to the gates of the four MOS
transistors in the core are expressed as V1 aVx bVy
VR, V2 (a c)Vx (b 1/c)Vy VR, V3 (a c)Vx
bVy VR, V4 aVx (b 1/c)Vy VR. The multiplication is
based on the identity of Eq. (41).
Ignoring the body effect and channel-length modulation,
the equations for drain current versus drain-to-source voltage
can be expressed in terms of three regions of operation as
ID = 0

(43a)

for VGS VT, the off region,




V
ID = 2 VGS VT DS VDS
2

(43b)

for VDS VGS VT, the triode region, and

ID = (VGS VT )2

(43c)

for VGS VT and VDS VGS VT, the saturation region, where
(CO /2)(W/L) is the transconductance parameter, is the
effective surface carrier mobility, CO is the gate oxide capacitance per unit area, W and L are the channel width and
length, and VT is the threshold voltage.
The differential output current is expressed as

I = I + I = (ID1 + ID2 ) (ID3 + ID4 )

= 2VxVy

(Vx2 + Vy2 + |VxVy | 5 I0 /2 )

produce the product of two input voltages. Simple combinations of two inputs are obtained when a b 
and c 1,
a 
and b c 1, and a b c 1 as shown in Fig. 25(b).
Figure 25(c) shows a CMOS four-quadrant analog multiplier consisting of only a multiplier core and an active voltage adder.
In addition, a multiplier consisting of the multiplier core
in Fig. 25(a) and a voltage adder and subtractor has been
implemented with a GaAs MESFET IC, and a useful frequency range from dc to UHF bands of 3 GHz was obtained
for a frequency mixer operating on a supply voltage of 2 or
3 V.
RADIO-FREQUENCY SIGNAL AND LOCAL OSCILLATOR
Figure 26 shows a block diagram of a communication system,
showing modulation and demodulation. A wireless communication system will usually consists of an information source,
which is modulated up to RF or microwave frequencies and
then transmitted. A receiver will take the modulated signal
from the antenna, demodulate it, and send it to an information sink, as illustrated in Fig. 26. The rate at which information can be sent over the channel is determined by the
available bandwidth, the modulation scheme, and the integrity of the modulationdemodulation process.
Frequency synthesizers are ubiquitous building blocks in
wireless communication systems, since they produce the precise reference frequencies for modulation and demodulation
of baseband signals up to the transmit and/or receive frequencies.
A simple frequency synthesizer might consist of a transistor oscillator operating at a single frequency determined by a
precise crystal circuit. Tunable transistor frequency sources

Va
Vamp
Frequency
synthesizer

Time

(44)

The parameters a, b, and c are canceled out. Four properly

arranged MOS transistors with two properly combined inputs

Figure 27. Block diagram of frequency synthesizer producing singletone sinusoidal output.

342

MIXER CIRCUITS

Reference
oscillator

Phase
detector

Loop
filter

VCO

Output

Figure 28. Indirect frequency synthesizer using a phase-locked loop.

rely on variations in the characteristics of a resonant circuit

to set the frequency. These circuits can then be embedded in
phase-locked loops (PLLs) to broaden their range of operation
and further enhance their performance.
A representative view of a frequency synthesizer is given
in Fig. 27 which shows a generic synthesizer producing a single tone of a given amplitude that has a delta-function-like
characteristic in the frequency domain.
Indirect frequency synthesizers rely in feedback, usually in
the form of the PLL, to synthesize the frequency. A block diagram of a representative PLL frequency synthesizer is shown
in Fig. 28. Most PLLs contain three basic building blocks: a
phase detector, an amplifier loop filter, and a voltage-controlled oscillator (VCO). During operation, the loop will acquire (or lock onto) an input signal, track it, and exhibit a
fixed phase relationship with respect to the input. The output
frequency of the loop can be varied by altering the division
ratio (N) within the loop, or by tuning the input frequency
with an input frequency divider (Q). Thus, the PLL can act
as a broadband frequency synthesizer.

modulation of the carrier signal, and resolved into AM and

FM components. The AM portion of the signal is typically
smaller than the FM portion.
FM noise power is represented as a ratio of the power in
some specified bandwidth (usually 1 Hz) in one sideband to
the power in the carrier signal itself. These ratios are usually
specified in dBc/Hz at some frequency offset from the carrier. The entire noise power can be integrated over a specified
bandwidth to realize a total angular error in the output of the
oscillator, and oscillators are often specified this way.

FREQUENCY SYNTHESIZER FIGURES OF MERIT

Frequency Stability

An ideal frequency synthesizer would produce a perfectly

pure sinusoidal signal, which would be tunable over some
specified bandwidth. The amplitude, phase, and frequency of
the source would not change under varying loading, bias, or
temperature conditions. Of course, such an ideal circuit is impossible to realize in practice, and a variety of performance
measures have been defined over the years to characterize the
deviation from the ideal.
Noise
The output power of the synthesizer is not concentrated exclusively at the carrier frequency. Instead, it is distributed
around it, and the spectral distribution on either side of the
carrier is known as the spectral sideband. This is illustrated
schematically in Fig. 29. This noise can be represented as

;yy;
Ps

Sideband
noise

Pssb
Ps

Power

Signal

Pssb

fm

f0

Frequency

1 Hz

Figure 29. Phase noise specification of frequency source. The noise

is contained in the sidebands around the signal frequency at f 0.

Tuning Range
The tuning range of an oscillator specifies the variation in
output frequency with input voltage or current (usually voltage). The slope of this variation is usually expressed in megahertz per volt. In particular, the key requirements of oscillator or synthesizer tuning are that the slope of the frequency
variation remain relatively consistent over the entire range of
tuning and that the total frequency variation achieve some
minimum specified value.

Frequency stability of an oscillator is typically specified in

parts per million per degree centigrade (ppm/C). This parameter is related to the Q of the resonator and the frequency
variation of the resonator with temperature. In a free-running system this parameter is particularly important,
whereas in a PLL it is less so, since an oscillator that drifts
may be locked to a more stable oscillator source.
Harmonics
Harmonics are output from the oscillator synthesizer that occur at integral multiples of the fundamental frequencies.
They are typically caused by nonlinearities on the transistor
or other active device used to produce the signal. They can be
minimized by proper biasing of the active device and design
of the output matching network to filter out the harmonics.
Harmonics are typically specified in dBc below the carrier.
Spurious Outputs
Spurious outputs are outputs of the oscillator synthesizer
that are not necessarily harmonically related to the fundamental output signal. As with harmonics, they are typically
specified in dBc below the carrier.
BIBLIOGRAPHY
1. A. A. Abidi, Low-power radio-frequency ICs for portable communications, Proc. IEEE, 83: 544569, 1995.
2. L. E. Larson, RF and Microwave Circuit Design for Wireless Communications, Norwood, MA: Artech House, 1996.

MOBILE COMMUNICATION
3. N. Camilleri et al., Silicon MOSFETs, the microwave device technology for the 90s. In 1993 IEEE MTT-S Int. Microw. Symp. Dig.,
June 1993, pp. 545548.
4. C. Tsironis, R. Meierer, and R. Stahlman, Dual-gate MESFET
mixers, IEEE Trans. Microw. Theory Tech., MTT-32: 248255,
March 1984.
5. S. A. Maas, Microwave Mixers, 2nd ed., Norwood, MA: Artech
House, 1993.
6. J. M. Golio, Microwave MESFETs & HEMTs, Norwood, MA: Artech House, 1991.
7. F. Ali and A. Gupta (eds.), HEMTs & HBTs: Devices, Fabrication,
and Circuits, Norwood, MA: Artech House, 1991.
8. D. Haigh and J. Everard, GaAs Technology and its Impact on
Circuits and Systems, London: Peter Peregrinus, 1989.
9. D. O. Pederson and K. Mayaram, Analog Integrated Circuits for
CommunicationPrinciples, Simulation and Design, Norwell,
MA: Kluwer Academic, 1991.
10. W. Gosling, R A D I O Receivers, London: Peter Peregrinus,
1986.
11. K. Murota and K. Hirade, GMSK modulation for digital mobile
telephony, IEEE Trans. Commun., COM-29: 10441050, 1981.
12. Y. Akaiwa and Y. Nagata, Highly efficient digital mobile communications with a linear modulation method, IEEE J. Selected
Areas Commun., SAC-5 (5): 890895, June 1987.
13. J. Eimbinder, Application Considerations for Linear Integrated
Circuits, New York: Wiley, 1970.
14. H. E. Jones, Dual output synchronous detector utilizing transistorized differential amplifiers, U.S. Patent No. 3,241,078, March
15, 1966.
15. B. Gilbert, A precise four-quadrant analog multiplier with subnanosecond response, IEEE J. Solid-State Circuits, SC-3 (4): 365
373, 1968.
16. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, New York: Wiley, 1977, pp. 667681.
17. K. W. Kobayashi et al., InAlAs/InGaAs HBT X-band double-balanced upconverter, IEEE J. Solid-State Circuits, 29 (10): 1238
1243, 1994.
18. F. Behbahani et al., A low distortion bipolar mixer for low voltage
direct up-conversion and high IF frequency systems. Proc. IEEE
1996 Bipolar Circuits Technol. Meet., Sept. 1996, pp. 5052.
19. H. Song and C. Kim, An MOS four-quadrant analog multiplier
using simple two-input squaring circuits with source-followers,
IEEE J. Solid-State Circuits, 25 (3): 841848, 1990.
20. K. Kimura, A unified analysis of four-quadrant analog multipliers consisting of emitter and source-coupled transistors operable
on low supply voltage, IEICE Trans. Electron., E76-C (5): 714
737, 1993.
21. K. Bult and H. Wallinga, A CMOS four-quadrant analog multiplier, IEEE J. Solid-State Circuits, SC-21 (3): 430435, 1986.
22. K. Kimura, An MOS four-quadrant analog multiplier based on
the multitail technique using a quadritail cell as a multiplier
core, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 42:
448454, 1995.
23. Z. Wang, A CMOS four-quadrant analog multiplier with singleended voltage output and improved temperature performance,
IEEE J. Solid-State Circuits, 26 (9): 12931301, 1991.
24. K. Kimura, A bipolar very low-voltage multiplier core using a
quadritail cell, IEICE Trans. Fundam., E78-A (5): 560565,
May 1995.
25. K. Kimura, Low voltage techniques for analog functional blocks
using triple-tail cells, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 42: 873885, 1995.
26. R. Siferd, A GaAs four-quadrant analog multiplier circuit, IEEE
J. Solid-State Circuits, 28 (3): 388391, 1993.

343

27. B. Razavi, Challenges in the design of frequency synthesizers for

wireless applications. Proc. IEEE 1997 Custom Integrated Circuits
Conf., May 1997, pp. 395402.

KATSUJI KIMURA
NEC Corporation

MIXERS. See MULTIPLIERS, ANALOG; MULTIPLIERS, ANALOG

CMOS.

MMIC AMPLIFIERS. See MICROWAVE LIMITERS.

MOBILE AGENTS. See MOBILE NETWORK OBJECTS.

674

MULTIPLIERS, ANALOG

MULTIPLIERS, ANALOG
The multiplication of continuous-time continuous-amplitude
analog signals has been of fundamental importance since the
earliest days of electronic systems, notably in computing and
nonlinear control systems, modulation, correlation, the determination of signal power, variable-gain amplifiers, and other
signal management functions. Many ingenious multiplier
methods have been devised during the past fifty years, most
of which have fallen into obsolescence (1,2).
In contemporary electronics, two-variable analog multiplication, and the closely related function of division, are invariably implemented by inexpensive monolithic integrated circuits whenever cost, low power consumption, small size,
accuracy, and high speed are essential requirements. By far
the largest proportion of current commercial products utilize
bipolar junction transistor (BJT) technologies and invoke
translinear principles (3), providing dependable, accurate,
complete solutions that are easy to use. When optimized for
accuracy, using special circuit techniques and laser trimming,
static errors may be 0.05% full scale (FS) or better, with
nonlinearity errors (deviation from the ideal function) as low
as 0.01%. Translinear multipliers may also be optimized for
very high speed, which can extend up to the limits of the technology; a 3 dB bandwidth of over 30 GHz is nowadays possible
in special applications such as wideband variable-gain cells.

In principle, monolithic multipliers can provide both very

high static accuracy and very high bandwidth in a single device, but such a need is rare, and products providing this capability are not generally available. A typical integrated circuit (IC) four-quadrant multiplier (one that generates the
true algebraic product for inputs of either polarity) usually
provides a compromise solution, with accuracybandwidth
combinations of the order of 0.1% and 10 MHz (found, for example, in the Analog Devices AD734), or 3% and 1 GHz
(AD834).
Analog multiplier techniques are widely used in gain-control applications. Two-quadrant multipliers often serve this
function, with careful optimization to meet difficult and conflicting performance objectives. Occasionally, dual-channel
operation is provided, as in the 60 MHz AD539. The voltagecontrolled amplifier (VCA) function is often better addressed
by a different class of circuits, particularly those that provide
an exponential relationship between the control variable and
the resulting gain, thus providing a linear-in-dB control law.
Other multiplier applications require a response only to
inputs of one polarity. These are called one-quadrant multipliers. Many of the cells proposed in contemporary research papers are in this class and need considerable elaboration with
auxiliary circuitry to permit operation in two or four quadrants. The careful choice and optimization of the root structure is therefore of critical importance, and a few solutions
have gained preeminence.
A mixer is sometimes regarded as an analog multiplier,
optimized by close attention to noise and intermodulation for
use in frequency-translation applications. While this view is
useful in thinking about the basic function, mixer designs differ markedly. For example, the response to one of its two inputs (the signal at the local oscillator port) desirably approximates a binary (switching) function, and the mixer ideally
performs only the sign-reversal (or phase-alternation) function on the other input (the carrier). This can also be viewed
as the multiplication of the analog input signal by all the
terms in the Fourier expansion of a square wave.
While the time-domain and amplitude-domain behavior of
analog multipliers are usually of greatest interest, mixers are
more often assessed by their performance in the frequency
and power domain, with a strong emphasis on two dominant
imperatives: the minimization of spurious intermodulation
terms, and the minimization of noise. Thus, from a practical
perspective, it is unwise to view mixers in the same terms as
analog multipliers. The term modulator is often used, though
modulators (and demodulators) may be fully linear multipliers.
Multiplication of two binary variables is implemented by
the exclusive-OR logic function, and this operation is at the
heart of a modern digital multiplieraccumulator cell. With
the advent of inexpensive analog-to-digital and digital-to-analog converters and the microprocessor, many applications formerly solved in the analog domain have migrated to digital
implementations. The benefits include greater stability, reconfigurability and increased flexibility, and easy integration
into a software-governed hierarchy. Modern digital signal processing (DSP), using specialized very large scale integration
(VLSI) multiplication algorithms, has taken this trend a step
further. However, the time quantization of DSP approaches
precludes operation at high speeds.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

MULTIPLIERS, ANALOG

MULTIPLIER BASICS
An ideal multiplier generates the product of two time-varying
input variables (rarely more), historically identified as X and
Y. In most practical multipliers, the inputs and output (here
labeled W) are voltages. Occasionally the exterior variables
are in the form of currents; however, the interior variables
are very often in this form. The function is described by the
equation
VW =

VX
V
VU Y

(1)

where VW is the output, VX and VY are the two inputs, and

VU will here be called the scaling voltage. VU is of critical importance in establishing the accuracy of the function. Equation (1) is written in a way which emphasizes that VX is the
variable whose voltage range is determined by VU. A more
useful multiplier structure allows the addition of a further
variable, VZ, to the output:
VW =

VX
V + VZ
VU Y

(2)

VU may also be varied from an input interface in some IC

multipliers. Thus, in its most general implementation, Eq. (2)
describes a versatile multiplierdivideradder element. Its
practical value depends on the speed and accuracy with which
it implements this function, the noise levels at input and output, the harmonic distortion under various drive conditions,
and detailed practical issues such as the impedance at its interfaces (often differential), its ability to drive a load, the supply voltage and current-consumption requirements, its size,
its cost, and the like.
A basic consideration relates to the number of quadrants
in which a multiplier can operate (Fig. 1). Some multipliers
provide operation in only one quadrant, that is, all variables
are unipolar. These are useful in specialized embedded analog
computing applications; for example, in certain temperaturecompensation applications (4), a unipolar output VC(T) must
be proportional to absolute temperature (PTAT) as well as to
the primary controlling variable VC, which is independent of
temperature:
(+)VC (T ) =

(+)VC
T
V
(+)VR 0 T0

(3)

where VR is a reference voltage that scales the controlling (input) function while V0 is a second reference voltage that scales
the output, T is the system temperature, and T0 is a reference
temperature, often taken as 300 K (27C). The robust design
of all nonlinear analog circuits is characterized by the need
for careful consideration of such detailed scaling attributes.
In a two-quadrant multiplier, commonly used in gain-control applications, one of the two inputs is unipolar, that is,
constrained to a single polarity, while the other input and the
output are bipolar, as is the case for a VCA. This functional
restriction does not represent a concession to structural complexity, but rather has as its objective the improvement of
performance in gain-control applications.
In a four-quadrant multiplier, the sign of VW is algebraically correct for all sign combinations of VX and VY, that is,
for the quadrants ( ), ( ), ( ), and ( ).
This may appear to be the most versatile case and could be
used in any application, but in practice it will not perform
optimally in all of them. For example, a two-quadrant multiplier, used as a VCA, can provide output-referred noise and
distortion that is proportional to the magnitude of the unipolar input, while in a four-quadrant type these remain almost
constant for a given magnitude of input on the bipolar (signal) channel.
Equation (1) indicated that the input VX is associated with
a divisor VU, and the full-scale value of VX will be determined
by this denominator. When VU is arranged to be controllable
from an interface, analog division is implemented. In some
practical IC products, the range of allowable values for VU
may be quite large. For example, the AD734 provides a
1000 : 1 range (10 mV to 10 V) at its high-impedance VU
interface. As a fixed-scale multiplier a high-precision reference voltage, generated by a buried zener, laser-trimmed to
0.01%, provides VU. As well as its utility in contemporary analog computing applications, where the value lies in the measurement of a ratio of voltages over a wide range of absolute
values, the division function may also be used in gain-control
applications, where VX represents the signal and VU is the
(one-quadrant) gain-control voltage, providing a gain range of
over 60 dB.
Many monolithic multipliers use a differential cell topology,
and can process differential signals at their X and Y interfaces, with high common-mode rejection. These versatile devices add features normally only found in instrumentation
(differencing) amplifiers, by implementing the even more general function
VW =

+Y

1Q
X

+X
4Q

2Q

Y
Figure 1. Multiplier operating quadrants.

675

VX 1 VX 2
(VY 1 VY 2 ) + VZ
VU

(4)

In the most versatile IC dividers, the VU input interface would

also be differential, and allow this voltage to change sign
(that is, support four-quadrant division). Because of its limited utility and the basic problem of the singularity at VU
0, this capability is generally not provided in commercial
products. However, the function is practicable, and a method
will later be shown for its implementation and use in filterless demodulation.
During the 1970s and 1980s, the supply voltages for analog
multipliers invariably were 15 V, the voltage ranges for VX,
VY and VW were 10 V FS, and VU was 10 V. During recent
years, supply voltages have dropped, first to 5 V, heralding

676

MULTIPLIERS, ANALOG

FS input and output voltages of typically 2 V (with a VU of

1 V to 2 V) and more recently to single supplies of either 5
V or 3 V, necessitating some modification in the approach
to full four-quadrant operation, for example, by providing a
differential output as well as differential inputs. Currentmode interfaces for the signals are sometimes used to cope
with these limitations.
Contemporary analog multiplier developments are moving
away from generic, textbook objectives toward system-specific
embodiments, with increasing emphasis on extending the
high-frequency accuracy, lowering spurious nonlinearities,
and reducing noise levels. The development of high-performance analog multipliers remains a specialized art; only a
few IC companies have the skills to cope with the numerous
arcane design details. Cell developments being reported in
the professional journals, particularly those promoting the
use of complementary metaloxidesemiconductor (CMOS)
technologies, are often not fully in touch with the imperatives
of modern systems and their challenging requirements.

MULTIPLIER ERRORS
The absolute accuracy of analog multipliers has traditionally
been defined in terms of the error between the actual and
ideal output relative to the FS value of the output. This is
invariably a more optimistic metric than the error specified
in terms of the actual output. Further, it is common practice
to emphasize the static accuracy, obtained under dc or lowfrequency conditions. The dynamic errors at realistic operating frequencies are then layered over the static specifications, using similar metrics to those for linear amplifiers,
such as 3 dB bandwidth, rise and fall times, slew rate, etc.
These practices came about largely because of the context
within which high-accuracy multipliers were historically developed: in analog simulators, in military applications, and in
industrial plant control and various types of instrumentation,
prior to the advent of the microprocessor. The FS static accuracy remains a key parameter in defining the performance of
a multiplier.
The most accurate monolithic multipliersusing translinear techniques and high-performance complementary bipolar
(CB) processes with silicon-on-insulator (SOI) fabrication,
temperature-stable thin-film resistors, and laser trimming for
precise calibration against NBS-traceable standards
achieve a guaranteed absolute accuracy of 0.1% FS, with
80 dBc harmonic distortion. Selected components can maintain a short-term accuracy of 0.02% FS, which is practically
the state of the art in analog multiplication, using any
known technique.
Errors arise from many mechanisms, and are of several
types. Some, such as the linear errors, can usually be attributed to component mismatches; nonlinear errors can be
caused by mismatches in device size and in current density;
dynamic errors are due to the finite response time of these
devices and to parasitic signal coupling across them. While
these may be captured in mathematical expressions, little insight is gained from such, and they become particularly enigmatic when the modeling of all of the nonlinear and dynamic
effects is attempted. A more useful approach is to consider
the linear, nonlinear, and dynamic errors separately.

Analog
multiplier

VXO
VX

VX

VY

VY

VW
VYO

VW
VWO

V U = VU + VUO
Embedded reference

Figure 2. Linear error sources in a multiplier.

LINEAR ERROR SOURCES

There are four linear error sources in an analog multiplier,
identified in Fig. 2. First is the uncertainty, VUO, in the scaling
voltage VU, equivalent to a gain error. Contemporary monolithic multipliers often use a bandgap reference to provide
VU. Without trimming, these can achieve an absolute accuracy
of 2% and a temperature coefficient of 50 106 /C. Using
trimming, the initial and long-term accuracy may be as high
as 0.1% or better, with a temperature coefficient of under
5 106 /C. For higher accuracies, some type of breakdown
device is used; their use is limited to applications in which at
least one supply voltage is available that exceeds the breakdown voltage of the reference element (about 8 V). Monolithic
circuits may use a buried-zener reference, whose voltage can
be adjusted to within 0.01% using laser-wafer trimming in
high-volume production, with commensurate temperature
stability and long-term stability.
The second linear error is the dc offset at the output of the
multiplier, VWO. Consider a multiplier having VU 10 V and
full-scale X and Y inputs of 10 V. When both inputs are 1 V
(that is, 10% of FS), the output should be 100 mV. While an
output offset of VUO 10 mV is only 0.1% of the FS output, it
is 10% of the actual output. Some applications of multipliers
are severely affected by this output-referred dc error. However, in a VCA, where the output will invariably be ac-coupled, this offset is inconsequential. In considering the specifications of a multiplier, one must pay careful attention to all of
the many detailed requirements of each specific application.
The two remaining linear errors are those due to the input
offsets, VXO and VYO. An input applied to one of the two inputs
will generate a spurious output when the second input is
nominally zero. Thus, if a 10 V sinusoid is applied to the X
input, and the Y input is set to zero but exhibits an internal
offset of VYO 10 mV, there will be a residual sine output of
amplitude 10 mV when VU 10 V. This is called static feedthrough and is commonly specified either in fractional or decibel terms. In the above case, the feedthrough of 10 mV is
0.1%, or 60 dB below the potential full-scale output of 10 V.
It is important, however, to make a distinction between the
feedthrough due to dc offsets and that due to parasitic signal
coupling at actual operating frequencies. Residual nonlinearities in the multiplier may also cause signal feedthrough.
NONLINEAR ERRORS
When all linear errors have been eliminated by exact calibration of the scaling voltage VU and by nulling the offsets associ-

MULTIPLIERS, ANALOG

Slow time scale

+10 V
+5 V
5 V
10 V

VX
Y

Analog
VW1
multiplier W
being
tested
+

Oscilloscope
in XY mode

VY
Y

Accurate
reference W
VW2
multiplier

VX = 3.5 V

VX = 3.0 V

VX = 2.5 V

0.025%
+2.0 V

+3.0 V
VY

Figure 4. Typical multiplier crossplot.

of the reference multiplieris displayed on an oscilloscope,

generating an insight-rich real-time display. Using a high
vertical sensitivity, errors as small as 0.01% of FS are readily
visible. One of the two inputs is swept linearly over its full
range; this input also provides the horizontal sweep voltage
for the oscilloscope. The other input is stepped through several spot values (typically 100%, 50%, zero, 50% and
100% of FS) by automatically incrementing one step for
each sweep of the first input. The sweep times are chosen to
ensure a flicker-free display, but not much faster, since dynamic errors quickly become dominant, even in a 1 MHz
bandwidth multiplier. The X and Y inputs can then be
swapped for a different view of the errors. Insight into interpreting the multiplier errors displayed in a crossplot can be
acquired rapidly after a little practice.
In contemporary production practice, when multipliers of
the highest accuracy are to be characterized, the input voltages are generated by computer-programmable sources traceable to NBS standards, and the output is measured by a highgrade digital voltmeter. The error is then calculated in the
host computer, which may generate a crossplot as a graphical
entity. Figure 4 shows a typical result for a state-of-the-art
laser-trimmed multiplier; the peak error is seen to be within
0.02% over the range of X and Y input values (6).

Vert.

DYNAMIC ERRORS

+0.025%

Absolute error

ated with VX, VY, and VW, some errors will remain. These may
be called irreducible errors, to the extent that they are difficult for the user to eliminate in most practical applications.
However, there are many ways by which these may be lowered in a production context, using careful design and IC layout techniques, laser trimming, and special packaging. They
are sometimes addressed using a multiplexed analog-to-digital converter (ADC) for VX and VY, followed by digital multiplication in a microprocessor and digital-to-analog conversion
back to the voltage domain, in which case the residual nonlinearities will usually be less than a least-significant bit (LSB).
This approach is appealing for low-frequency instrumentation-grade multiplication, but not in applications where bandwidth, power consumption, size, and cost are dominant considerations.
The IC multiplication method most widely used today is
based on the translinear principle, and the following comments regarding residual nonlinear errors are with this implementation in mind. It is found that, for the commonly used
two- and four-quadrant types, one error is essentially quadratic in form, while another is essentially cubic. Quadratic
errors can be largely traced to VBE matching errors in the core
of the four-quadrant multiplier. Cubic errors arise due to mismatches in current density and are minimized by the optimal
choice of topology, device sizes, and bias conditions. High-volume production experience over a period of more than two
decades shows that residual nonlinearities of under 0.1% of
FS can be routinely achieved without trimming.
Since an analog multiplier has two independent inputs,
the output and the error generate surfaces, formally requiring
three-dimensional representation. Here again, no special insights are gained by using such in examining the behavior of
a multiplier. Instead, an excellent practical assessment of
static accuracy is provided by a crossplot (5). The term arose
in a testing context, in which a multiplier of unknown quality
was compared with one of impeccable credentials.
In the classical crossplot technique (Fig. 3), both multipliers are excited by the same inputs (whose precise calibration
is unimportant), and the difference in the outputs of the two
unitsthat is, the error relative to the internal calibration

677

Horiz.

+10 V
10 V
Fast time scale
Figure 3. Typical crossplot measurement technique.

The errors discussed so far relate to slowly varying inputs.

Dynamic errors arise when the inputs are varying rapidly and
may be generated in the input interfaces of the multiplier, in
the core, or in the output stage. Since multipliers may exhibit
different response times on the X and Y input channels (that
is, different phase angles), their dynamic errors need to be
measured separately. When a high degree of phase matching
is required in the response from the X and Y inputs, two mul-

678

MULTIPLIERS, ANALOG

tipliers can be used (either in cell form or as complete ICs)

with their two pairs of input interfaces cross-connected and
their outputs summed. The key dynamic property of a multiplier is its small-signal bandwidth, the frequency at which
the output amplitude is 3 dB below its midband value. The
measurement should be made with one of the input channels
receiving the ac test signal, while the other receives a fixed
dc level. For modern commercial IC multipliers, values range
from 1 MHz to 1 GHz, but operation of bipolar multiplier cells
at 13 GHz (7) and 32.7 GHz (8) is currently feasible in automatic gain control (AGC) applications.
The individual bandwidths of the input circuits, the multiplying core, and the output stage are often different, and design optimization depends on the requirements. Consider a
signal-squaring application being implemented by a fourquadrant multiplier, with the two input channels connected
in parallel and sinusoidally excited. This generates an output
from the multiplier core at twice the input frequency, plus a
dc component. To extract the ac component, as in a frequency
doubler, the output bandwidth must be at least twice that of
the input frequency; however, if we wish to determine the
mean squared value, as in a power measurement application,
the output bandwidth must be much lower, requiring a postmultiplication low-pass filter to perform averaging.
It is often found that the ac response from one of the two
multiplier inputs depends in some complex way on the dc
value of the other input, due to another type of dynamic error,
namely, high-frequency (HF) feedthrough. This occurs when
the effective gain of a multiplier is low, and results in the ac
output being (usually) larger than the dc gain value would
predict. Two-quadrant multipliers may show this problem
more noticeably, because they are sometimes designed to provide a very high gain-control range (as much as 80 dB) and
will therefore be operating in an attenuation mode for much
of this range. Even minute parasitic capacitances can lead to
large feedthrough errors at, say, 100 MHz and above. The
solution lies in the use of special cell topologies for HF multiplication.
The notion of vector error arose in computing applications.
This is only another way of describing errors due to the finite
bandwidth of the device, but taking phase lag into account.
In a system characterized by a single-pole response, a dynamic error of 1% will occur at a frequency of 1% of the 3
dB bandwidth, and is closely proportional below this frequency. Thus, a multiplier having a 10 MHz bandwidth exhibits a 0.1% vector error at 10 kHz, while the output magnitude is in error by only 0.005%. Practical wideband
multipliers rarely conform to a simple one-pole response,
however, and this metric is not often invoked in contemporary
applications of multipliers.
In multipliers based on pulse-averaging methods, there is
a residual periodic ripple on the output, and vector errors are
large, due to the use of multipole filters. Further types of dynamic error will be found in multipliers implemented using
hybrid analogdigital techniques, due to time quantization.
Slew-rate (dV/dt) limitations generate dynamic errors under
large-signal conditions, and increase settling time. Overloadrecovery effects may also arise: a well-designed multiplier will
not fold over when the inputs greatly exceed the nominal
FS value, and will recover quickly when the overdrive condition is removed.

Finally, multiplier noise needs consideration. This is usually specified in terms of the output noise spectral density (so
many nV/Hz1/2). In translinear multipliers, the dominant
wideband noise source is the core: because of the high effective gain to the output, multiplier noise will invariably be
much higher than in typical IC amplifiers. In multipliers using MOS technologies, there is a significant increase at low
frequencies, due to 1/f mechanisms. In a multiplier used for
gain-control purposes, this may cause modulation noise.

HISTORICAL TECHNIQUES
The earliest analog multipliers were electromechanical (1). In
a servomultiplier (Fig. 5) one of the two inputs, VX, determined the relative angular position X of a shaft. A first potentiometer, P1, on this shaft, biased by a dc voltage, which can
be equated to the denominator voltage VU in Eq. (1), generated the voltage VX XVU. Thus, the shaft angle X was proportional to VX /VU. A second potentiometer, P2, whose excitation was provided by VY, generated the output (VX /VU)VY. The
static accuracy was determined by VU and the matching of the
X and Y potentiometers. The response time to the X input,
typically 100 ms to 1 s, was determined by the inertia of the
mechanical system. The response bandwidth of the Y input
was limited by the ac behavior of the potentiometers (which
were often wire-wound resistance elements, and thus very inductive) and associated circuitry; it extended to at most a
few megahertz.
Mechanical servomultipliers are essentially obsolete, but
in 1975 Gilbert (9) described a novel solid-state realization, in
which the position of a rotating shaft was mimicked by the
angular position of a carrier domain, a narrow region of
highly localized minority carrier injection from a semicircular
emitter of a bipolar semiconductor structure. The track of the
mechanical potentiometer was replaced by the resistive collector region. Smith described a second-generation rotational
design (10). In more recent BiCMOS embodiments of this
principle the domain moves linearly, in a long, narrow n-type
emitter, in response to the X input. Its position 0 X LE is
precisely determined by a parabolic voltage profile induced in
the p-type base-region, which also serves as a resistor and as
the drain of the superintegrated PMOS devices, as shown in

Shaft

Motor

VY

VU

Error
amp

P2

P1

Output
buffer

VX
Ground

Figure 5. Electromechanical servomultiplier.

VXVY/VU

MULTIPLIERS, ANALOG
L/R base
contacts

L/R collector
contacts

p-type region acts

n-type
as PMOS source
emitter
PMOS gate (poly-Si)

n-type
buried
layer

p-type region simultaneously serves as the

npn base, the PMOS drain, and a resistor
(a)

Carrier
domain
= slider

Domain can be moved

by voltage control
from left to right

Current flow
into extended
collector region
CL

CR
Buried layer forms resistive track
(b)

Figure 6. Solid-state servomultiplier: (a) upper regions; (b) detail of

subcollector.

Fig. 6(a). An n-type buried-collector layer beneath the emitter

corresponds to the track of the output potentiometer. The domain, whose current magnitude is controlled by the Y input,
is analogous to the slider; Fig. 6(b) shows just the collector
region.
Two domains may readily be integrated into a single device
to realize a four-quadrant multiplier. The response time to
the position-controlling X input is typically nanoseconds; the
Y input is even faster, since the extended npn transistor behaves essentially as a grounded-base stage. While the performance of these carrier-domain multipliers is excellent, the
use of superintegrated structures is deprecated in a commercial context, since they are not amenable to standard modeling and simulation techniques.
With the increased need for speed in analog computers
during the mid-1940s, electromechanical multipliers were replaced by vacuum tube circuits. A popular technique of this
time was based on cells that generated a square-law function,
used in conjunction with summing and differencing circuits
to implement a quarter-square multiplier (5), so named because of the algebraic identity
XY = 14 [(X + Y )2 (X Y )2 ]

(5)

A generic implementation is shown in Fig. 7. The squaring

circuits are here presumed to be transconductance (gm) elements and able to handle X and Y inputs of either polarity
(although in practice it is often necessary to include an absolute-value circuit to allow the use of single-quadrant squar-

679

ers). The effective value of VU is determined by these gms, the

load resistors RL, and A, the voltage gain of the buffer amplifier. Note that the squaring function implies an embedded
voltage reference VR, a fundamental requirement, since the
basic scaling demands of Eq. (1) must be met. The source of
this voltage, which dominates the accuracy, is not always
made clear in some descriptions of circuit operation.
MOS transistors are said to exhibit a square-law relationship between the channel current and the gatesource voltage, when operating in the saturation region. Many of the analog multiplier cells devised for CMOS implementation
during the 1980s depended on this notion. Here, the denominator VU is traceable to device parameters that are not accurately known or well controlled. Furthermore, the basic relationship is far from square-law for modern short-channel
transistors, which have other error sources (for example,
back-gate channel modulation). Other problems arise in MOS
cells based on operation in the triode region.
Analog multipliers have also been based on the use of
squaring cells made with bipolar transistors, whose practical
value is questionable, since they perform only indirectly what
can be more efficiently achieved using direct translinear multiplier implementations. Indeed, the appeals to the quartersquare approach in a contemporary context seem to overlook
the historical reasons for invoking this principle in the first
place, at a time when bipolar transistors and their highly advantageous translinear properties were not yet available.
In an attempt to push the static accuracy to fundamental
limits, the use of nonlinear device behavior has often been set
aside to explore what might be done using little more than
analog switches (11). Invariably, the accuracy of these multipliers is limited more by the auxiliary circuitry required to
support the core function, as is true of most practical multipliers, and any theoretical benefits that might be possible using
switching techniques are often lost in this way. A more serious limitation, for all but a few specialized low-frequency applications (for example, power measurement at line frequencies), is that the output must be derived from averaging a
pulse train whose duty cycle and amplitude vary with the two
multiplicands. A considerable time is required to determine
the average value, even using an optimal filter.

RL
+
VX + VY
2

+
x2

VY

VR
R

VX

VX VY
2

VW
+

x2

2R

R
VR
Figure 7. Quarter-square multiplier.

Output
buffer

680

MULTIPLIERS, ANALOG

S2

+VY
VY

Low-pass
filter

VW

VX

+VU

A
S1

VU

output current that ideally, is proportional to the product,

and is converted back to a voltage using a simple resistive
load. While space precludes a discussion of true gm-mode multipliers, the underlying device-modeling issues are crucial to
the operation of modern multipliers using translinear-loop
techniques.
A bipolar junction transistor exhibits an accurate and reliable exponential relationship between its collector current IC
and baseemitter voltage, VBE:
IC = AE JS (T ) exp

Figure 8. Pulse-averaging multiplier.

An illustrative embodiment of this principle is shown in

Fig. 8. The hysteretic comparator, which operates the changeover switch S1, and the low-pass filter RC constitute an asynchronous delta modulator. This loop generates a pulse sequence whose duty cycle is forced to a value such that the
average voltage appearing at node A is equal to the input
VX, which is assumed to be varying only slowly compared to
the oscillation period of the loop, which is determined by the
hysteresis band of the comparator, VH, the reference voltages
VU, and the time constant RC. It is easily shown that
the duty cycle is
P =

thi
V + VU
= X
tlo + thi
2VU

(6)

varying from 0 when VX VU to 100% when VX VU,

independent of VH, which must be considerably less than VU.
The comparator is arranged to operate a second switch, S2, to
which the Y input voltage is applied, and whose output at
node B is a voltage of VY and VY, also having the duty cycle
P . This is averaged in a multipole low-pass filter to generate
the output

VW = ave{P VY (1 P )VY }
=

VX
V
VU Y

(7)

A clocked comparator may be used to provide synchronous

operation. This multiplier offers very high accuracy, arising
from a fundamentally sound architecture, which does not depend on any device nonlinearity, such as vacuum tube or
MOS square-law behavior, or the exponential junction law. It
is well suited to CMOS implementation, where the chief
sources of error will be the offset voltage in the comparator
(which can be eliminated using doubly correlated sampling)
and in the output filter. The fundamental need for averaging,
however, severely limits the response bandwidth to the high
kilohertz region; if higher oscillation periods are used in the
delta modulator, second-order effects due to inaccurate
switching eventually become troublesome.
VARIABLE-TRANSCONDUCTANCE MULTIPLIERS
Analog multipliers may be implemented in a true transconductance mode, that is, using cells accepting voltage-mode
signals at their input interfaces, and generating a differential

V

BE

VT

AE JS (T ) exp

V 
BE

VT

(8)

AE is the effective emitter area (never exactly equal to the

physical junction area, because of edge effects, though exactly
proportional when using replicated unit devices). The factor
JS(T) is the saturation current density, a characteristic of the
doping in the transistors base region; it is highly temperature-dependent. The product AEJS is usually called IS, the saturation current, and is a key scaling parameter. VT is the thermal voltage kT/q, where k is Boltzmanns constant, 1.38
1023 C V/K, T is the absolute temperature, and q is the electron charge, 1.60 1019 C. VT evaluates to 25.85 mV at T
300 K, which temperature is assumed unless otherwise
stated.
Equation (8) is essentially Shockleys junction law, stated
in transistor terms, with some concessions to simplicity, inconsequential for most practical purposes. First, the approximation of the quantity exp(VBE /VT) 1 by the simpler
exp(VBE /VT) is readily justified: even at VBE 360 mV, the
exponential term is over a million. Second, VT should be
multiplied by a factor, called the emission coefficient, which is
very close to, but not exactly, unity. Finally, the forward
Early voltage VAF and the reverse Early voltage VAR, which do
not appear in Eq. (8), have an effect on the IC VBE relationship. These and other device effects are of importance in the
detailed analysis of high-performance analog multipliers.
However, they are truly second-order effects, and the design
of practical, robust, and manufacturable multipliers can ignore many of them, or utilize simple compensation techniques
to lessen or eliminate their effect on accuracy.
The dual equation is
VBE = VT log(IC /IS )

(9)

Using IS 3.5 1018 A, typical for a modern small transistor, VBE evaluates to 800 mV at 100 A, and varies by a factor
VT log 10, or 59.5 mV, per decade. These equations describe
the most important characteristics of a bipolar junction transistor (BJT), which operates as a voltage-controlled current
source (VCCS), having an exponential form in its collectorcurrent response to an applied base-emitter voltage, or as a
current-controlled voltage source (CCVS), having a logarithmic
form in its base-emitter-voltage response to its collector current. The accurate logantilog properties of bipolar transistors are the basis of innumerable nonlinear circuits, not available from CMOS devices.
An important outcome of Eq. (8) is that the small-signal
transconductance gm is accurately related to the collector current:
gm =

IC
I (T ) exp(VBE /VT )
I
= S
= C
VBE
VT
VT

(10)

MULTIPLIERS, ANALOG

that is, the transconductance is an exactly linear function of

the collector currentthe origin of the term translinear. Even
more remarkably, this equation holds true for all bipolar
transistors, on any technology (including heterojunction bipolar transistors (HBT) in SiGe, GaAs, etc.) and is independent
of IS, thus being unaffected by doping levels or device size.
These transconductance multipliers are best viewed as a
subset of the larger class of translinear circuits, and are
widely used in contemporary practice where linearity and accuracy are less important than extreme simplicity. It is instructive to review the history from this broader perspective.
Regrettably, some confusion has arisen in the nomenclature,
and what should be called translinear multipliers, whose
internal operation can be analyzed entirely in the current
mode, are often mistakenly classified as transconductance
types, which properly have at least one input in voltage form
and generate a current output.

IX

IY

During the period 1960 to 1970, the planar fabrication process for bipolar junction transistors was being perfected, and
it became possible to produce a large number of integrated
circuits on a 1 in. (2.5 cm) wafer, each having many transistors with excellent analog characteristics and closely matching parameters. In particular, the base-emitter voltages, for
a given device geometry and collector current, were closely
matched, partly due to operating at near-identical temperatures. These and other aspects of monolithic fabrication
opened the floodgates to stunning new design techniques,
hitherto quite impracticable using discrete-transistor implementations. In fact, many related cell concepts were generated within a short period of time. The translinear technique
for analog multiplication was one such development.
We will begin with a discussion of cells using loops of junctions, called strictly translinear, and identified here as TL
(translinear loop) cells. TL multipliers can be readily understood by considering first a simple one-quadrant cell (Fig. 9)
using four identical, isothermal transistors (12, p. 51). The
collector currents of Q1, Q2 and Q3, which are here assumed
to have the same size, are forced to values IX, IY, and IU respectively. This cell does not, in principle, place any restrictions on the values of these currents, but they are restricted
to a single polarity. Summing the VBEs around the four-tran-

IC1

IC3

IC4
= IW
Q3

Q2

Q1

Q4
IY

IW

Q5

Q6

Q7

Q3

Q2

Q4

Q1

Q8

Q9

sistor loop and assigning a value IW to the current in Q4, we

obtain the equation
VT log(IX /IS ) + VT log(IY /IS ) = VT log(IU /IS ) + VT log(IW /IS )
(11)
It is immediately apparent that the thermal voltages VT may
be eliminated from this equation, leaving sums of logarithms.
These may be converted to products:
I I
IX IY
= U W
IS IS
IS IS

IU

Figure 9. Translinear one-quadrant multiplierdivider cell.

(12)

The saturation currents IS may also be eliminated, leaving

IW =

IX IY
IU

(13)

The most important observations about this result are: (1)

temperature sensitivity has been completely eliminated; (2)
the product IW is exactly proportional to IX and IY; (3) the cell
also provides analog division; (4) the actual VBEs are of no
interest; that is, we have realized a pure current-mode cell.
This is a simple demonstration of the power of the
translinear-loop principle (TLP), which describes the relationship between all the currents in a loop of transistors, as in
this example, and allows complex nonlinear functions to be
synthesized with ease. The TLP states:




IC =
IC
(14)
cw

IC2

IU

Figure 10. Elaborated current-mode multiplier cell.

TRANSLINEAR MULTIPLIERS

IX

681

ccw

which reads: The product of the collector currents in the

clockwise direction around a translinear loop is equal to the
product of the counterclockwise collector currents, times a factor that allows for the possibility that the transistors emitter areas AE may differ. For present purposes, we will generally assume 1, except when discussing certain distortion
mechanisms. Note that this condition may be achieved using
devices of different emitter area, arranged in balanced pairs
of equal area, or in many other ways. Any number of loops
may overlap, and thus interact, but each loop will independently satisfy this equation.
Figure 10 shows a practical development of the basic cell
that retains the pure current-mode operation and can provide

682

MULTIPLIERS, ANALOG

logarithmic relationship to IC IX over a very wide dynamic

range, specifically, VBE VT log(VX /RXIS); accordingly, this cell
may also be used as a logarithmic element (see LOGARITHMIC
AMPLIFIERS). RC and CC are necessary to ensure that the OPA
loop remains stable.
Figure 12 shows a complete one-quadrant multiplier based
on this approach. It is traditionally called a log-antilog multiplier, because of the reliance on the dual log-exp relationships
of Eqs. (8) and (9). Its function is not, however, predicated on
the small-signal transconductance given by Eq. (10), which
is also temperature-dependent, but is accurately linear with
respect to the X or Y input under large-signal conditions, and
temperature-stable. A simpler view is therefore that it is a
translinear multiplier, following the principle stated in Eq.
(14), aided by operational amplifiers to accurately force the
collector currents.
OPA1 to OPA3 provide the input interfaces (the HF compensation has been omitted for clarity). OPA4 converts the
current IC3 IW to a voltage VW IWRW. The op-amps hold the
collector voltages of all transistors at ground potential, eliminating Early-voltage errors. From inspection,

CC
S
RC
RX

Q1

VX
IX

IC

Figure 11. Method for forcing IC IX VX /RX using an OPA.

very accurate operation. Transistors Q5 to Q9 ensure that the

collector currents are forced to the desired value, even when
the dc current gain 0 is low; all of the above equations remain accurate in this eventuality. The main sources of static
error in this multiplier are (1) emitter-area uncertainties in
Q1 to Q4, which cause a simple scaling error, but do not generate nonlinearity; (2) the base and emitter resistances, rbb
and ree, which will cause nonlinearity, but only at high currents, when the voltage drops across them are a significant
fraction of VT; (3) the modulation of IW by the collectorbase
voltage VCB of Q4, due to finite Early voltage.
Many further improvements in current-mode multipliers
are possible, and have been developed, but it is generally necessary for a multiplier to receive and generate voltage-mode
variables. Special-purpose high-bandwidth interface cells can
be designed for high-bandwidth voltage-to-current (VI) and
current-to-voltage (IV) conversion. However, in moderatespeed applications operational amplifier (OPA) interfaces can
provide these functions. Figure 11 shows a rudimentary
structure for forcing a collector current (5).
The low input offset voltage of the OPA serves two functions. First, it places the current-summing node S close to
ground potential (under static conditions), which allows the
input current IX to be generated from a voltage VX with high
accuracy, scaled by RX, thus: IX VX /RX. Assuming the OPA
has very low input current, all of IX flows in the collector of
the transistor. Second, it forces the VCB of Q1 to be zero, eliminating modulation effects due to VAF. The VBE of Q1 bears a

VW =

RU RW VX VY
RX RY VU

(15)

The linear errors are determined by the offset voltages of the

amplifiers (a 1 mV offset represents a 0.01% error for a FS
input or output of 10 V), by element matching, and by the
voltage reference. Nonlinear errors are mainly determined by
the junction resistances in Q1 to Q4. The dynamic errors are
dominated by the op-amps. This remains a one-quadrant multiplierdivider, useful in specialized contemporary applications. Incidentally, this drawing hints at the care which must
be taken in a practical realization with regard to the placement of the current-forcing connections.
More often, multipliers are used as gain-control elements,
which require two-quadrant (bipolar) operation of the signal
path, with single-polarity operation of the other multiplicand
and the divisor. However, a one-quadrant cell can be adapted
for two- or four-quadrant operation. The rearrangement
shown in Fig. 13 shows the extension to two quadrants; further rearrangements of this same core allow operation in all
four quadrants.

VX

RX

VY

IX

RY

VU

IY

RU

VW

IU

RW

IW
+

+
Q2

OPA1

OPA2
Q1

Figure 12. One-quadrant logantilog multiplier having voltage interfaces.

Q3
OPA3
Q4

OPA4

MULTIPLIERS, ANALOG

VP

RW

Voltage inverter

RL
+

OPA4

RX

RU

Q1

VX
V
+VU Y

RW

RX

OPA1

+VU

VW

R
VX

683

Q4

Q2

Q3

OPA2

RU

OPA3

IY

HIGH-FREQUENCY TRANSLINEAR MULTIPLIERS

The bandwidth of the preceding circuits is severely limited
by the operational amplifiers. Some improvement in a fully
monolithic design is possible using specialized amplifiers, but
in order to realize the full potential of the translinear core,
other types of interfaceoften, though not necessarily, using
open-loop rather than feedback techniques, are used. Note
that moderately accurate conversion back to voltage mode in
a wideband current-mode multiplier may be achieved by the
use of simple load impedances.
The first translinear multipliers, described by Gilbert in
1968 (13), achieved a response from dc to 500 MHz, and exhibited a large-signal rise time of 0.7 ns. Two-quadrant types
were originally developed for use in oscilloscope vertical deflection amplifiers, to provide interpolation between the
1 : 2 : 5 step attenuator settings that determine the sensitivity,
replacing the use of potentiometers, which were formerly used
in the signal path. Four-quadrant types were also developed
during that period, for use in modulation and demodulation;
optimized low-noise mixer cells, including the widely used topology known as the Gilbert mixer, were developed for use
in frequency translation applications, though prior art using
discrete devices (14) was discovered in patent searches.
The immediate combination of monolithic simplicity, accuracy, speed, and low cost was unprecedented at that time, and
remains unimproved on even to this day. These classic circuit
cells have undergone little change in design, and have become
the dominant technique for analog multiplication across a
broad front.
Numerous commercial products are nowadays available
providing one-quadrant, two-quadrant and four-quadrant operation, sometimes supporting the division function. Absolute
accuracies may be as high as 0.05%, nonlinear errors as low
as 0.01% (roughly corresponding to harmonic distortion levels
of 80 dBc) and bandwidths extend from dc, through audio,
ultrasonic, IF, RF, and microwave ranges, and as high as 40
GHz in advanced optical receiver AGC applications. No other

Figure 13. Two-quadrant multiplier/divider.

multiplier technique provides such broad coverage of the applications domain.

To illustrate the principles, Fig. 14 shows a practical twoquadrant translinear multiplier. The bandwidth of the TL
core extends from dc to a substantial fraction of the fT of the
transistors, which for a modern BJT process is commonly 25
GHz, and as high as 100 GHz using advanced SiGe heterojunction technologies. The chief practical limitation to overall
bandwidth is usually the support circuitry, notably the VI
conversion cell at the X input and in the conversion of the
differential current-mode outputs to a voltage output.
The input voltage VX is first converted to a pair of differential currents (1 X)IX and (1 X)IX by the VI cell; these
currents are applied to the diode-connected outer pair of transistors, Q1, Q2. Assume that the VI interface is perfectly
linear, that is, X VX /IXRX. For the case of the pnp-style interface shown here, X runs from 1 when the value of VX is

IX

IX

VX/RX

VX

(1 Y) IY

(1 + Y) IY
VBB

(1 X) IX

Q1

ccw

Q2

(1 + X) IX

+
Q3

cw

Q4
ccw

cw

2IY

Figure 14. Two-quadrant wideband multiplier cell (type A).

684

MULTIPLIERS, ANALOG

at, or more than, its FS negative limit of IXRX, to 1 at the

other extreme, when VX IXRX.
The variable X, called a modulation factor, is frequently
useful in describing the operation of these cells. A feature of
this multiplier cell (and unique to TL cells) is that operation
remains linear up to the extremities of the FS range, in other
words, for all values 1 X 1. In practice, a moderate
peak value of XFS of about 0.75 is generally used, first, to
ensure that at FS drive, the current densities remain above
the point where the instantaneous bandwidth, that is, f T(IC,
VCB), is jeopardized during portions of the signal cycle, and
second, to reduce the incidental nonlinearity in the VI cell.
Since the peak input voltage is VXFS XFSIXRX, it follows that
the bias current must be raised to IX VXFS /XFSRX to provide
this overrange capacity. For XFS 0.75 and a FS input of 1
V, the product IXRX must be 1.333 V.
To analyze the operation of this Type A multiplier cellso
named because the junction polarities alternate around the
loop, cwccwcwccwwe can assign a similar modulation
index Y to describe the currents in the driven pair Q3, Q4
and then apply the TLP. To gain rapid insight, we will ignore
for the moment the effects of junction resistance, finite base
currents, and device mismatches. While these may appear to
be naive simplifications, the performance capabilities of TL
multipliers are well proven, and the practical errors can in
fact be held to very low levels. Applying the TLP, from Eq.
(14), we have
IC2 IC4 = IC1 IC3
cw

(16)

ccw

Inserting the actual currents, we have

(1 Y )IX (1 + X )IY = (1 X )IX (1 + Y )IY

(17)

Y X

(18)

Thus

independent of IX and IY. That is, the modulation factor in the

outer pair has been exactly replicated in the inner pair, and
the current-gain is simply IY /IX.
This is a very important result. Note the simplicity of the
analysis that results from direct application of the TLP,
which completely bypasses considerations involving VBE, its
exponential nature, and the temperature-dependent saturation current IS and thermal voltage kT/q. Equation (18) holds
over all temperatures, for all bias currents (from nanoamperes to milliamperes), any device size, either device polarity
(pnp or npn), for any material (Si, Ge, SiGe, GaAs), and for
any bipolar technology (homojunction or heterojunction).
For this striking reason, the TLP was originally named
the pervasive principle. It is as fundamental a result for
translinear circuits as that for gm stated in Eq. (10) is for a
single transistor. Of course, when implementing the principle
in robust, high-performance products, many detailed issues
need consideration. The differential output current is just
IW = IC3 IC2 = (1 + X )IY (1 X )IY
= 2X IY

The differential voltage VBB has the magnitude

VBB = VT log

1+X
1X

(20)

and while this voltage, having a peak value of 50 mV for

Xmax 0.75, is of only incidental interest, it provides a useful way to assess the wideband noise of a translinear multiplier. For example, when IX IY 1 mA, the total voltage
noise spectral density (NSD) of this four-transistor cell evaluates to about 1.3 nV/Hz1/2. Thus, if the FS output is raised to
1 Va factor of 20 times VBB the lowest possible NSD at
this node will be 26 nV/Hz1/2. Assuming a 1 MHz signal bandwidth, this amounts to 26 V rms, providing a dynamic range
of 88.7 dB for a 707 mV rms sine-wave output.
More detailed analysis shows that this particular cell is
beta-immune, that is, finite base currents do not affect the
basic operation, provided that the current gain IC /IB is
substantially independent of current over the X range. This
can be understood by noting that the fractional loss of current
in the outer transistors due to the base currents IB3 and IB4 of
the inner pair bears a constant-ratio relationship to IC3 and
IC4; thus, the modulation factor X is unaffected by the base
currents, and Y continues to have the same modulation factor
as generated by the input VI converter. Even when the base
currents are almost equal to the available drive currents, and
Q1, Q2 are operating under starved conditions, the multiplier
remains lineara unique property of this particular circuit.
The scaling error due to IC /IE can be considered as a separate mechanism, even though arising from the same device
limitations. Highly refined design techniques address such
matters of scaling stability and robustness in mass production.
The most serious nonlinear error sources in this cell are (1)
small mismatches in the emitter areas and (2) finite junction
resistances. These and other causes of errors in translinear
multipliers were fully quantified in the seminal papers published in 1968 (15,16). Mismatches between the ratios
AE1 /AE2 and AE3 /AE4 cause even-order nonlinearities (essentially quadratic), and also linear offsets. The factor used in
Eq. (14) is here given by
=

Q1
ccw

AE1AE4
AE2 AE3

(1 Y) IY

(1 + X) IX

Q2

(21)

(1 + Y) IY

(1 X) IX

Q3

cw

Q4
cw

ccw

VX
VX/RX

IX

2IY

IX

(19)
Figure 15. Alternative two-quadrant multiplier cell (type B).

MULTIPLIERS, ANALOG

Q1

IW

Q4
Q2

(1 + X) IX

(1 X) IX

Q3

Q5

(1 Y) IY

Q6

(1 + Y) IY

VX

VY
RX

RY

IX

IX

IY

IY

Figure 16. Wideband four-quadrant multiplier cell.

The VBE mismatch around the loop Q1Q2Q3Q4 is VT log

. While this voltage is a function of temperature, the effects
of emitter-area mismatches in translinear circuits are temperature-independent, and the voltage view is irrelevant.
For Xmax 0.75, it is found that the peak quadratic error
is 0.1% of FS output when 1.002 (VBE mismatch of 52 V).
To minimize this error the transistors should be arranged in
a common-centroid manner in the IC layout. This level of
quadratic error is routinely achieved in untrimmed multipliers, and may be reduced by a factor of at least ten by using
laser trimming to null the second harmonic distortion. This
error is independent of device size and bias currents.
Errors due to junction resistance, on the other hand, are
dependent on device size (mostly because of the effect on the
base resistance rbb) and operating currents. These cause oddorder nonlinearity errors (essentially cubic), but no offsets.
This source of nonlinearity is particularly troublesome in twoquadrant VCA cells, where current densities vary widely.
However, when certain simple criteria are met (16), this distortion can be eliminated in four-quadrant cells, and for this

RL

Q1

IW = IC3 IC2 + IC6 IC5

= (1 X )(1 Y )IY /2 (1 + X )(1 Y )IY /2
+ (1 + X )(1 + Y )IY /2 (1 X )(1 + Y )IY /2

(22)

= 2XY IY
The conversion of the differential currents back to the voltage
domain can be accomplished in several ways, depending
largely on accuracy and bandwidth considerations. In highfrequency applications, a balanced-to-unbalanced transformer
(balun) can be employed, with the working load impedance
RW determining the overall scaling factor.
Substituting the full expressions for X and Y into Eq. (22),
we can write
VW = 2XY IY =

VX VY IY RW
V V R
= X Y W
IX RX IY RY
VU RY

(23)

V 0
+

AO

Q2

VX

Q3

Q5

Q6

VZ

VY
RX

IX

reason they are often used even where only two-quadrant operation is required.
A four-transistor multiplier has only one other topological
form, shown in Fig. 15, called a Type B (balanced) cell. The
junctions occur in pairs, cwcwccwccw. It can be shown
that this circuit does not enjoy the beta immunity of the Type
A multiplier, since the currents in the driven transistors Q2,
Q3 are now out of phase with those in the input transistors
Q1, Q4; the base currents subtract from the drive currents in
antiphase. It is nonetheless widely used, because it can be
easily driven from all-npn interfaces (VI converters), which
until recently were the only available high-speed transistors
in a bipolar IC process.
A four-quadrant multiplier is formed by adding a further
pair of transistors Q5, Q6, also having their bases driven from
Q1, Q2, as shown in Fig. 16, and their outputs connected in
parallel antiphase. The common-emitter nodes are driven
from a second VI, handling the Y input and generating a
complementary pair of currents (1 Y)IY and (1 Y)IY, where
Y VY /IYRY.
The operation is an extension of that analyzed for the twoquadrant cell. Elaborating Eq. (19), we have

IW

Q4

685

RY

IX

IY

RZ

IY

IZ

IZ
Figure 17. Versatile four-quadrant structure using active feedback.

686

MULTIPLIERS, ANALOG

+
VX

V XV Y
X

VU

R1

V Z1

+
VY

Figure 18. Four-quadrant

with gain.

R2
V Z2

multiplier

where VU IXRX in this implementation. It follows that the

biasing arrangements for IX should be traceable to an accurate, temperature-stable voltage reference. In a complete multiplier, this current will also include compensation for finite
beta. The AD834 is a dc to 1 GHz four-quadrant multiplier
having essentially this structure, having open-collector outputs; special techniques are employed to linearize the X and
Y interfaces.
In low-frequency (300 MHz) applications, it is possible to
provide a more versatile output interface based on feedback
around a closed loop. Of particular interest here is the use of
active-feedback techniques (17) to improve linearity. Figure
17 shows the general structure: a third VI cell has been
added to handle the feedback path; its differential output is
VZ /RZ. Note that while the currents IY and IZ do not enter into
the scaling of this multiplier, they nevertheless affect the FS
capacity of the Y and Z interfaces. Resistive loads RL are used
at the collectors of the core, but the high open-loop gain of the
output amplifier ensures that the differential voltage swing is
very small. The output currents of the Z cell are attenuated
by a scaling factor ; the purpose of this will become clear in
a moment.
The output can be expressed as
VW = AO

V

VZ RL
X VY IY RL

IX RX IY RY
RZ

(24)

ing on one of the inputs, by a feedback connection, but it does

not have to be the Z input. We will show that in addition to
four-quadrant multiplication, this versatile IC structure can
be used for two-quadrant squaring, simple one-quadrant
square-rooting, absolute-value extraction, two-quadrant
square-rooting (with very few external components), twoquadrant division, four-quadrant division (using two ICs),
and N-dimensional vector summation (using N multiplier
ICs).
The active-feedback structure can also easily generate an
accurate bipolar current output having a very high impedance, and thus also provide exact time integration using a
capacitor. This structure was first used in the highly successful AD534, a fully calibrated laser-trimmed monolithic multiplier introduced by Analog Devices in 1975, and since then in
the AD633, AD734, and AD835, and IC multipliers from other
manufacturers. It has become a classic form, having been designed into thousands of systems.
To complete the theory of this multiplier form, we will rewrite the general solution found by nulling the bracketed
terms in Eq. (24):
VZ
VX VY
=
IX RX RY
RZ

(25)

which can be simply cast as

As before, the IY factors cancel, and when the effective resistance AORL is very high, the two terms inside the brackets
must be equal. This condition will always be forced by VW act-

VX VY = VZVU

(26)

where the scaling voltage is

VX

VU = IX RX RY /RZ

W
This current is
proportional
to the product
VW across RI

(27)

RI

+1

Vout

CI

Figure 19. Rmsdc converter using difference-of-squares technique.

It was previously noted that the product IXRX needed to be

1.333 times the FS input to result in a FS modulation factor
XFS of 0.75. For a FS X input of 10 V, this requires IXRX to
evaluate to 13.33 V (though no such explicit voltage may arise
in the IC). Further, it is desirable that RZ RY, so that the
nonlinearity arising in the feedback (Z) cell exactly cancels
that of the Y-input cell; this is an important advantage of the
active feedback scheme. Finally, we wish the scaling voltage
to be exactly 10 V. Solving Eq. (27), this requires that the
factor must be set to 0.75.
These multipliers also provide fully differential, high-impedance X, Y, and Z interfaces, implementing a more compre-

MULTIPLIERS, ANALOG
V1
X1

O/P

100 pF

10 k

KW

X2

KW

OPA1

Z1

Y1
+

687

VW

Z2

Y2

KVW
V2
X1

O/P

R
+

KW

OPA2
R

X2

Z1

Y1

KW

+
KVW
Z2

Y2

N stages

VN
X1

O/P
+

KW

VW =

X2

Z1

Y1

KW

Y2

V12 + V22 + ... + VN2

when r = ( N 1)R

Z2

Figure 20. N-dimensional vector summation.

hensive function, which can be expressed in terms of the balance equation

(VX 1 VX 2 )(VY 1 VY 2 ) = VU (VZ1 VZ2 )

(28)

While many general purpose multipliers support 10 V FS inputs and utilize a denominator voltage VU of 10 V (such as
the AD534, AD633, and AD734), the 250 MHz AD835 has 2
V FS inputs, with a VU that is readily trimmed to 1 V, thus
providing a 4 V FS output; the node VZ1 is internally connected to VW, but access to VZ2 allows many useful extra functions based on summing at the output. The 1 GHz AD834
provides differential current outputs.
MULTIPLIER APPLICATIONS
The balance equation can be used to implement numerous
functions: modulation, demodulation, mean-square and rootmean-square extraction, power measurement, gain control;
filterless demodulation, correlation (using the multiply-and-

add feature), and many more nonlinear/linear operations,

such as trigonometric-function synthesis, rmsdc conversion,
and programmable filters. The availability of this Z interface
is of great practical value, and is used in many of the application examples which follow (18), in most of which either the
low-cost AD633 or the AD534 can be used.
Figure 18 shows the basic symbol for versatile multipliers
of this class, and demonstrates how one may be connected for
basic four-quadrant multiplication. With VW simply connected
to VZ1, the balance equation (28) becomes
(VX 1 VX 2 )(VY 1 VY 2 ) = VU (VW VZ2 )

(29)

thus
VW =

VX VY
+ VZ2
VU

(30)

In this case, however, only a fraction of VW is returned to the

Z interface, invoking familiar feedback techniques, which
raises the output gain by the factor G (R1 R2)/R2, and

688

MULTIPLIERS, ANALOG
O/P

X1
+

X2

V
010 V

u =
u cos + v sin

+
10 k

Z1

Y1

Y2

Z2

X1

O/P

10 k

= 2 tan1(V /20)
(rads)

X2

v =
v cos + u sin

+
10 k

Z1

Y1

Y2

Figure 21. Vector rotation circuit.

10 k

Z2

thus the effective value of the denominator voltage is VU /G. A

voltage at the lower end of R2 adds directly to the output, with
a scaling factor of unity.
The output may be taken in current-mode form from the
VZ2 node by a resistor placed from VW to VZ2 since the product
voltage VXVY /VU is forced across this resistor, whatever its
value and for any load voltage (for both within a wide range);
the output impedance is very high (megohms), being determined by the common-mode rejection ratio of the Z interface.
When this current is applied to a grounded capacitor, the
time-integration function can be implemented. This is used in
the rmsdc converter based on a difference-of-squares tech-

VM

nique (19), shown in Fig. 19. This scheme generates the product
2
V 2 Vout
Vin + Vout
(Vin Vout ) = in
2
2

the long-term average of which is forced to zero by the action

of the loop including the integrator, which also serves to average the signal at the multiplier output, VW. It follows that
Vout = ave(Vin2 )

W
(1 +

Figure 22. AM modulator.

(32)

E sin t

(31)

Carrier feedforward

VM
) E sin t
VU

MULTIPLIERS, ANALOG

V XV U

It is sometimes required to rotate a pair of signals representing a two-dimensional vector, for example, in image presentation systems. Figure 21 shows how just two multipliers
may be used. The vector (u, v) is turned through an angle
controlled by the V input, to generate

VZ

u  = u cos + v sin

Negative feedback

+
VY

VZ

in other words, the rms value of Vin has been generated. Using
an integration time constant CIRI of 16 s, the loop settles to
within 1% of the final value after 123 s for a 10 V sine-wave
input, and within 305 s for a 4 V input. With the capacitor
omitted, the circuit provides the absolute-value function.
A further example of the utility of the summation feature
is provided by the N-dimensional vector-summing circuit (Fig.
20), where this function is provided by daisy-chaining the
multiplier outputs. The inputs V1 through VN may have either
polarity, and the loop seeks to null the sum of the N independent difference-of-the-squares components. When the factor K
is set to 1/ N, the overall scaling from the inputs is unity,
that is

V

2
1

+ V22 + + VN2

y = VY /VU ;

w = VW /VU ;

x2

O/P
+

X2
Y1

Y2

O/P

X1

X2
Y1

+
Y2

x1 x2
y1 y2

+
Z1

Z2

VZ1 VZ2
+ VX 2
VY 1 VY 2

x1

+
Z2

y1
y2

(36)

(37)

A high-impedance summing input is again available. To

maintain negative feedback around the output amplifier, the
denominator must be positive, but the numerator may have
either polarity. The circuit therefore provides two-quadrant
division, with the added advantage of differential signal processing available at both the numerator and denominator
inputs.
The determination of the ratio of two voltages, both of
which have indeterminate polarity, calls for a divider capable

etc.

Z1

(35)

VW = VU

w=
X1

2 arctan(V /20)

thus

(33)

z = VZ /VU ;

(34b)

(VW VX 2 )(VY 1 VY 2 ) = VU (VZ1 VZ2 )

The integration time, provided by the 10 k resistor and the

100 pF capacitor, will normally be chosen to ensure stable
loop operation, but when large enough to implement averaging, the circuit performs the root-mean-sum-of-squares operation.
The use of normalized variables is often valuable in analyzing and synthesizing multiplier applications. Thus:
x = VX /VU ;

v = v cos + u sin

Using AD534 or AD633 multipliers, the rotation scaling is

5.725 deg/V and is 60 at V 11.55 V; the relative error
is 2% at V 5 V ( 28). The length of the vectors is
unchanged. A related scheme for cathode-ray tube (CRT) geometry and focus correction was described in Ref. 18.
In a more commonplace application, the Z interface is also
used in the AM modulator shown in Fig. 22, where the carrier
E sin t is fed forward to the output (which responds as a
voltage follower to the Z2 input) and thus added to the product
of the modulation voltage VM and this carrier.
The Z interface is especially useful in analog division (Fig.
23), since it presents a high-impedance, fully differential input port. From Eq. (28), with VX1 now being the output VW, we
have

Figure 23. Two-quadrant division.

VW =

(34a)

where

689

Figure 24. Four-quadrant division.

690

MULTIPLIERS, ANALOG

O/P

X1
+

R1 =
10.0 k

R2 =
18.0 k

X2

u
w = sin
R3 =
2
4.70 k
0<u<1

Z1
R4 =
4.30 k

Y1
+

Y2

Z2

Figure 25. Sine-function synthesis.

of accepting a bipolar denominator input. This is the fourquadrant division function. Commercial products that perform this function are not in demand, but it is easily implemented using two of these general-purpose multipliers, as
shown in Fig. 24. The behavior is benign through the singularity where the denominator is zero, though of course significant errors arise for small values. This circuit is unusual
in being able to divide one sine wave by another. In a test in
which a 400 Hz, 10 V amplitude sine wave was applied to
both numerator and denominator inputs, the output was essentially constant at 10.03 V, with a ripple of only 50 mV
at the zero crossings.
These versatile multipliers allow the implementation of arcane and often complicated nonlinear functions. For example,
the sine function can be approximated by
sin

R5 =
3.00 k

1.0468 0.4278 2
1 0.2618

(38)

over the range 0 /2. The theoretical error is 0.4% of

FS. While the synthesis requires considerable elaboration,
Fig. 25 shows how simple the implementation becomes, using
a single, low-cost multiplier. A better approximation, providing a theoretical error of only 0.01%, and 0.2% in practice,
can be implemented with just two such multipliers and five
resistors (18). Cosine synthesis needs only one multiplier and
two resistors (18), with a peak error of 2% at 22 and 73,

and the useful arctangent function may be approximated with

a peak error of 0.46 as shown in Fig. 26.
Many further examples could be provided. These generalpurpose voltage-in, voltage-out translinear multipliers cover
a very broad range of applications, and their structure is practicable for operation from dc to at least 1 GHz. Contemporary
wideband translinear multipliers, implemented using very
fast complementary bipolar silicon-on-insulator (CB-SOI) processes and aided by advances in noise and distortion reduction, calibrated to high accuracy using laser-wafer trimming
and presented in tiny surface-mount packages, represent the
epitome of the analog nonlinear art, while squarely meeting
the pragmatic ongoing requirements for a wide variety of nonlinear continuous-time signal-processing tasks, which go far
beyond the basic task of multiplication.
All manner of special-purpose multiplier cells, of either
transconductance or translinear types, have found their way
into numerous IC systems: as gain-control elements, often implementing the AGC function; as power detectors and power
controllers; in correlation applications; in analog-programmable filters; as modulators and demodulators, for example, synchronous detectors; and much else. Their simplicity, completeness (no external components are usually required), very
high speed combined with excellent accuracy, low supply voltage requirements, and low power, coupled with low cost and
very small size, ensure the continued use of these ubiquitous
elements.
BIBLIOGRAPHY

O/P

X1
+

X2
+

Y2

Z1

Y1
u

R3 =
4.70 k

R2 =
5.10 k

+
Z2

Figure 26. Arctangent synthesis.

w=

tan1u
45

(+10 V output
for +10 V input)
R1 =
3.60 k

1. S. Fifer, Analogue Computations, New York: McGraw-Hill, 1961.

2. G. A. Korn and T. M. Korn, Electronic Analog Computers, New
York: McGraw-Hill, 1956.
3. B. Gilbert, Translinear circuits: An historical overview, Analog
Integrated Circuits Signal Proc., 9 (2): 95118, 1996.
4. B. Gilbert, Adavnces in BJT techniques for high-performance
transceiver, Eur. Solid-State Circuits Conf. Rec., Sept. 1997, pp.
3138.
5. D. Sheingold (ed.), Nonlinear Circuits Handbook, 2nd ed., Analog
Devices, Norwood, MA: 1976.
6. B. Gilbert and B. Sam, 4-quadrant analog multiplication to
/0.025% accuracy needs few parts, Electron. Design, June 23,
1997, pp. 7072.

MULTIPLIERS, ANALOG CMOS

7. M. Moller et al., 13 Gb/s Si-Bipolar AGC amplifier IC with high
grain and wide dynamic range for optical-fiber receivers, IEEE J.
Solid-State Circuits, 29: 815822, 1994.
8. T. Masuda et al., 40 Gb/s analog IC chipset for optical receiver
using SiGe HBTs, 1998 IEEE ISSCC Techn. Dig., 1998, pp.
314315.
9. B. Gilbert, A new technique for analog multiplication, IEEE J.
Solid-State Circuits, SC-10: 437447, 1975.
10. J. Smith, A second-generation carrier domain four-quadrant multiplier, IEEE J. Solid-State Circuits, SC-10: 448457, 1975.
11. J. G. Holt, A two-quadrant multiplier integrated circuit, IEEE J.
Solid-State Circuits, SC-8: 434439, 1973.
12. B. Gilbert, Current-mode circuits from a translinear viewpoint: A
tutorial, in C. Toumazou, F. J. Lidgey, and D. G. Haigh (eds.),
Analogue IC Design: The Current-Mode Approach, IEE Circuits
and Systems Series, Vol. 2, Stevenage, UK: Perigrinus, 1990.
13. B. Gilbert, A dc-500 MHz amplifier/multiplier principle, ISSCC
Tech. Dig., IEEE, Feb., 1968, pp. 114115.
14. H. E. Jones, Dual output synchronous detector utilizing transistorized amplifier, March 15, 1996, US Patent 3,241,078.
15. B. Gilbert, A new wideband amplifier technique, IEEE J. SolidState Circuits, SC-3: 353365, 1968.
16. B. Gilbert, A precise four-quadrant multiplier with subnanosecond response, IEEE J. Solid-State Circuits, SC-3: 365373, 1968.
17. B. Gilbert, A high-performance monolithic multiplier using active
feedback, IEEE J. Solid State Circuits, SC-9: 364373, 1974.
18. B. Gilbert, New analogue multiplier opens way to powerful function-synthesis, Microelectronics, 8 (1): 2636, 1976.
19. B. Gilbert, Novel technique for rms-dc conversion based the difference of squares, Electron. Lett., 11 (8): 181182, 1975.

BARRIE GILBERT
Analog Devices Inc.

691

62

MULTIVIBRATORS

ri

MULTIVIBRATORS
A multivibrator is a device which transitions (vibrates) between several (multi) fixed output levels. Besides their use for
timing, they are commonly used either for storage or for clocking of data in digital computers using binary numbers where
the number of levels is generally two. There are several types
of multivibrators and several classification schemes. One classification is (1) triggered or (2) free-running. Another more
frequent classification method uses their stability properties
for which, in the two-level case, there are (1) monostable, (2)
bistable, or (3) astable multivibrators. The bistable multivibrator has an output that remains in either of its two stable
states until a trigger occurs, which forces a transition to the
other stable state; consequently, the name flip-flop is frequently ascribed to it. The monostable multivibrator remains
in its one stable state until triggered into its unstable state,
from which it eventually returns, usually after a fixed transition time, to the stable state; an alternate name of one-shot
is frequently used for it. The astable multivibrator acts as a
nonlinear oscillator as it oscillates periodically between its
two unstable states, often in an asymmetrical manner and
giving different resting times for each state. Most standard
electronic circuits texts contain some material on multivibrators, as, for example, Refs. 1 and 2 as well as Refs. 3 to 6.

ri

Trigger
(a)
y
Xwid

Yhi

Xmid

Xlo

Xhi
x

Ylo

(b)

GENERICBINARY HYSTERESIS MULTIVIBRATOR

A generic form of binary multivibrator is obtained by combining a nonlinearity that is binary hysteresis with a linear load
line, a single capacitor for dynamics, and a possible trigger
input; the type of multivibrator depends upon the position of
the load line on the hysteresis curve. Such a circuit is illustrated in Fig. 1(a), where all signals are taken as voltages
referenced to ground; the hysteresis is illustrated in Fig. 1(b).
A circuit for the hysteresis is given in Fig. 5, but here we
assume infinite input impedance and zero output impedance.
If at time t we take u(t) to be the multivibrator (trigger) input, y(t) its output, and x(t) its internal state signal, which is
input to the hysteresis h(x), we can write
C

dx
= gi (u x) + gf (y x)
dt
y = h(x)

if Xlo x

Yhi

if x Xhi

Xmid

(5)

By considering Eq. (1) at DC we obtain the (untriggered, that

is, with u 0) load line for the hysteresis as given by

1+

gi
gf

x = Lx

(6)

which defines the slope L [1 (gi /gf )], with L 1. Depending upon this slope L the hysteresis mid-point and the
hysteresis width, we have three basic types of intersections of
the load line with the hysteresis as discussed in the next sections and shown in Fig. 2(ac).
Monostable Multivibrator

(3)

where the constants Xlo and Xhi are the low and high transition points of the hysteresis, satisfying Xlo Xhi; Ylo and Yhi
are the two output values of the binary hysteresis. The x-axis
mid-point of the hysteresis is given by
X + Xhi
X Xlo
= lo
= Xlo + hi
2
2

Xwid = Xhi Xlo

(1)

in which the constants are the capacitance C, input conductance gi 1/ri, and feedback conductance gf 1/rf . The binary
hysteresis is characterized by

y = h(x) =

and is seen to represent an offset of the hysteresis curve along

the x axis. Of similar importance is the hysteresis width given
by

y=

(2)


Ylo

Figure 1. (a) Generic multivibrator using hysteresis. (b) Binary hysteresis. Gives philosophy for all multivibrator types. Hysteresis generated as per Fig. 7(a).

(4)

The monostable multivibrator results from the situation

shown in Fig. 2(a), where in the absence of an input trigger
(that is, u 0), there is one intersection, at the Q point,
XQ =

Yhi
L

(7)

which is stable. In this case the system remains at the intersection point Yhi until there is an input trigger: thus the monostable output Yhi. If a positive input trigger impulse is ap-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

MULTIVIBRATORS

y
y = L(x Utrig)

y = Lx
Yhi

63

Yhi

xhi

xlo

Utrig

xa

Ylo

Ylo

(a)

(b)

Utrig
t

Utrig
Xlo

XQ

+
Yhi

ri

ttrans

ri

Ylo
t

Ylo

(c)

(d)

Figure 2. (a) Monostable Q point. (b) Triggered effective load line. (c) Equivalent circuit for
transient, Xinitial Utrig Xhi. (d) Triggered response. Shows operation of the monostable multivibrator.

plied of peak value Utrig [u(t) Utrig(t) with ( ) the unit

impulse], which is larger than needed to move the capacitor
voltage x past the value Xhi (Utrig Xhi) then, as shown in Fig.
2(b), this effectively moves the load line to intersect the x axis
of the hysteresis at the capacitor initial value (which is the
peak trigger voltage value Utrig). On removal of the trigger
peak, a transient transition is made from the output Ylo back
to Yhi. The (minimum) value of this input trigger is seen to be
just Xhi. The transient return is governed by a time constant
determined by C and the Thevenins equivalent resistor seen
by C, that is, with time constant
tcnst

C
=
gi + gf

heads toward the low asymptotic value

Xasymlo = Ylo

gf
gi + gf

(9)

as determined from the voltage division of Ylo between rf and

ri. Consequently, assuming that the trigger impulse is applied
at t 0, the state for this transition is given as a first order
response by

x(t) = Xasymlo + [Utrig Xasymlo] exp

t
tcnst

(10)

(8)

The transition time will be the time to go from the maximum

value of x, as determined by the trigger, to Xlo with this time
constant. An equivalent circuit for determination of this transition time is shown in Fig. 2(c), in which it is seen that x

From Eq. (10) the transition time is found, by setting

x(ttrans) Xlo, to be

ttrans = tcnst ln

Xlo Xasymlo
Utrig Xasymlo

(11)

64

MULTIVIBRATORS

where we naturally assume that the asymptotic value is

smaller than the jump point value, Xasymlo Xlo, so that the
transition point Xlo can actually be reached. The output y at
this transition time jumps back to Yhi. A typical response of
this monostable multivibrator to an impulse trigger is shown
in Fig. 2(d).
In this case, as illustrated by Fig. 2(a), the output remains
at the high level Yhi until a positive input trigger occurs, at
which time the output immediately falls to the low level Ylo,
where it remains until the signal of the state x falls below
Xlo as determined by the time constant. A similar situation
clearly holds if the load line intersects just the lower branch
of the hysteresis curve; but here the transition occurs with a
negative impulse input trigger rather than a positive one, and
the asymptotic value heads toward the positive value of
Xasymhi = Yhi

gf
gi + gf

(12)

Equation (11) remains valid when this asymptotic value is

used. In either case, since only one output pulse occurs per
input trigger, the monostable multivibrator is often called a
one-shot.
Bistable Multivibrator
In the case where the load line intersects both the upper and
lower branches of the hysteresis, as shown in Fig. 3, then a
bistable multivibrator results, since both intersection points
serve as stable rest points. As in the monostable case, an impulse trigger input of sufficiently large amplitude to shift the
load line off of one of the hysteresis branches will transition
the system to the other stable point. The time constant will
again be C/(gi gf ), and the system will remain in the state
to which it transitioned until another appropriate input trigger makes it transition again. The equations governing the
transitions are essentially those developed for the monostable
multivibrator with substitutions of the appropriate levels.

y
h(x)
y = Lx

Figure 4. Load line on hysteresis for astable multivibrator operation.

governed by the time constant C/(gi gf ), which generally

leads to symmetrical output pulses.
To obtain equations for the transition times and the period, we begin by assuming that the multivibrator has just
switched from one to the other of its two output levels, taken
here for convenience to be from Yhi to Ylo. At that time, normalized to t 0, we again have the equivalent circuit of Fig.
2(c), except that now the initial condition on C is given by x
at the switching point, this being Xhi. Consequently, the capacitor value heads toward a low value with the mentioned
time constant, stopping when x reaches Xlo, at which time another transition (from low to high) is initiated. Substitution
of the correct initial condition and asymptotic value in Eq.
(11) gives the time for transition from the high to the low
output, thilo, as
thilo = tcnst ln

lo

Xasymlo


(13)

Xhi Xasymlo

By changing hi to lo and vice versa, this formula serves to

give the transition time from lo to hi as

Astable Multivibrator
Figure 4 illustrates the astable situation in which the load
line intersects the jump lines of the hysteresis. As these intersections are unstable, the system will not rest at either intersection but will transition between them with no input required to cause the transition. Again the transitions are

X

tlohi = tcost ln

X

hi

Xasymhi


(14)

Xlo Xasymhi

Consequently the period of oscillation of this astable multivibrator is given by

tper = tlo=hi + thilo

(15)

y
h(x)

Note that in the symmetric case where Xlo Xhi and Ylo
Yhi we have tlohi thilo, in which case the period is given by

y = Lx

Figure 3. Load line on hysteresis for bistable multivibrator operation.

tpersym = 2

C
ln
gi + gf

gf
gi + gf
gf
Xhi + Yhi
gi + gf

Xhi + Yhi

(16)

Should asymmetrical output pulses be desired, then a different time constant can be obtained for the rise as compared to
the fall by replacing ri or rf by a parallel combination of two
resistors in series with inverted diodes, as shown in Fig. 5(a

MULTIVIBRATORS

65

rhf

ra
r

Rhi

rb

(a)

Vbias

v+

+
x

y = Lx

(a)

y = (1 + a) v+ aVbias
Vdd

(b)

v+

Figure 5. (a) Replacement of ri or rf for asymmetrical output. (b)

Piecewise linear load line using ri or rf replacement. Resistor diode
circuit for generation of nonsymmetrical outputs.

Vss

b). In fact one of the diodes can be omitted, depending upon

which of the two slopes is the biggest. An alternate means of
obtaining asymmetry is via hysteresis asymmetry, which will
show up inside the logarithmic terms of Eqs. (13) and (14).

(b)

y
Vdd

Trigger Generation
Since an impulse trigger is desired for triggering the monostable and bistable multivibrators, the standard way to obtain
it is by differentiation of a step pulse. Figure 6 shows a typical
means of generating a trigger impulse from a step pulse of
amplitude Vp. Here the terminals a and b are those of the
trigger input u in Fig. 1(a). However, one could alternatively
apply the terminals a and b through a diode directly to the
multivibrator capacitor (and replace u by a short) to better
insure the direct application of desired initial values. This
method is most useful in the monostable case, while in the
bistable case one would need to switch between two differently directed diodes.

xlo

xhi

Vss
(c)
Figure 7. (a) Hysteresis generation circuit using an op-amp. (b)
Loading for the generic multivibrator. The op-amp characteristic
moves with x to intersect the fixed load line. (c) Resulting hysteresis.

Hysteresis Generation
Figure 7(a) shows an op-amp circuit that generates the binary
hysteresisin essence this is a Schmitt trigger. In Fig. 7(b)
we illustrate the means of calculating the hysteresis with the

y(v+ ) = Vdd 1(v+ x) + Vss 1(x v+ )

Ct
a

hysteresis curve shown in Fig. 7(c). For Fig. 7(b) we describe

the op-amp as a function of v, the positive op-amp input terminal voltage with respect to ground, with x as a parameter
by

rt

V = Vp1(t)
Step input

b
Impulse output

Figure 6. Differentiation circuit for impulse trigger.

(17)

where 1( ) is the unit step function and Vdd and Vss are the
upper and lower power supply voltages. The resistor portion
of Fig. 7 acts as a load line on the op-amp characteristic and
is described by
y(v+ ) = (1 + a)v+ aVbias
a=

ghi
ghf

(18)
(19)

66

MULTIVIBRATORS

As seen in Fig. 7(b), when we increase x the op-amp jump

moves to the right and eventually the intersection of the two
curves remains at Vss, while as we decrease x the op-amp
jump moves to the left and eventually the intersection is at
Vdd. For intermediate values of x there are two intersections.
The second one starts, as seen by moving the op-amp curve
left, at v x, where y Vdd for both curves. This gives the
geometry of Fig. 7(b)
Xhi =

Vdd + aVbias
1+a

Vdd

(a)

(20)
R

and the value for moving right starts at

Vss + aVbias
Xlo =
1+a

(21)
(b)

These two values give the hysteresis jump values as indicated

on the hysteresis curve of Fig. 7(c) to jump between the hysteresis values of Vdd and Vss.
In summary, the Schmitt trigger circuit of Fig. 7(a) gives
the hysteresis needed for the generic multivibrator of Fig.
1(a), with the hysteresis parameters given in terms of the circuit parameters of Fig. 7 by

(c)

Vdd + aVbias
1+a
(22)

Figure 8. NAND realization of (a) monostable multivibrator, (b)

astable multivibrator, and (c) bistable multivibrator.

Because we have four values (a, Vbias, Vdd, Vss) to set the hysteresis and four circuit parameters available, we can obtain
reasonable multivibrators using the circuits developed to
this point.
It should be noted that transistorized versions of the
Schmitt trigger exist and can be used in place of the op-amp
circuit as shown in Fig. 7(a). See Ref. 2, p. 317 for a BJTResistor type Schmitt trigger and Ref. 2, p. 321 for a CMOS
type. However, it is to be pointed out that these lack the
sharpness and flexibility for design of the op-amp Schmitt
trigger. An operational transconductance amplifier (OTA) version of the Schmitt trigger can be found in Ref. 7.

ers again can be made with NOR or NAND gates. The inverter on the right of Fig. 9 is used to square up the signal
generated by the crystal, which acts as a second-order system
to produce sinusoidal oscillations. Setting s jw in the characteristic equation found from Kirchhoff s laws, we see that
the inverter gains need to be set to 2 to force the real part
of the characteristic equation to zero; this is done by the
choice of equal resistors. From the imaginary part, the square
of the radian frequency of oscillations of such an oscillator is
1/LC, where L and C are the equivalent inductance and capacitance of the crystal; consequently the period of the output
pulses is 2LC. A commonly used inverter comes in a package of six and is known as the 74LS04 (9, p. 779).

Yhi = Vdd ,

Ylo = Vss ,

Xlo =

Vss + aVbias
,
1+a

Xhi =

LOGIC GATE CIRCUITS

It is also possible to construct multivibrators using digital
gates; in fact this is probably the most frequently used
method. Most books on digital circuits cover these multivibrators (see, for example, Ref. 8 as well as Ref. 4). Using only
two-input NOR gates, Fig. 8(a) shows a monostable, Fig. 8(b),
an astable, and Fig. 8(c) a bistable multivibrator. Throughout
Fig. 8 the NOR gates, with their inputs tied together, act as
inverters, so that they can be replaced to advantage by inverters. Figure 8(c) is an SR (set-reset) flip-flop with its S and R
inputs made complementary to force the bistable state determinations. Also, throughout Fig. 8, the NOR gates can be replaced by NAND gates and similar behavior obtained by using triggers inverse to those used for the NOR gates.
Although the use of standard gates makes these gate-constructed multivibrators attractive, and they work at relatively
high pulse rates, their characteristics are not as sharp as
those obtained from the op-amp Schmitt trigger circuits.
An astable circuit often used for precision clocks and using
crystal control is shown in Fig. 9 (6, p. 930), where the invert-

THE 555 TIMER

A standard commercial package that can be used to make any
of the multivibrators is the 555 timer, for which a full circuit
Crystal

Figure 9. Astable multivibrator using crystal pulse repetition rate

control and inverters.

MULTIVIBRATORS

diagram can be found in Ref. 10, pp. 9-33 through 9-38, along
with settings and applications. This is useful for printed circuit board designs using standard components. Because of its
common use, the 555 timer is treated in most standard electronic circuits textbooks, such as Ref. 4, pp. 975979 and Ref.
11, pp. 683688, 767. It comes in an eight-pin package (or as
the 556 14-pin dual set), these pins being 1 ground, 2
trigger, 3 output, 4 reset, 5 control voltage, 6 threshold, 7 discharge and 8 Vcc bias. It can set the timing from
microseconds to hours, and can source or sink up to 200 mA
at the output. Depending upon the external circuitry used,
the 555 can serve many functions, including that of a bistable,
monostable, or astable multivibrator with an adjustable duty
cycle. Basically, the 555 is a set-reset flip-flop (a bistable
multivibrator) surrounded by circuitry in the package that
allows it to take on various uses depending upon external circuitry. Its voltage at the output pin, Q of the SR flip-flop, is
set (to Vcc) when the threshold pin voltage falls below Vcc /3
and is reset (to ground) when the threshold pin voltage rises
above 2Vcc /3. Thus, by simple control on the threshold pin, a
bistable multivibrator results. By controlling the threshold
voltage with the external circuitry one readily obtains other
behavior. For example, Fig. 10 shows the connections for the
555 as an astable multivibrator. Here the capacitor C charges
from Vcc /3 to 2Vcc /3 through R78 R67, and discharges from
2Vcc /3 to Vcc /3 through R67 at times independent of Vcc, given
respectively by
tcharge = 0.693(R78 + R67 )C (output ending high)
tdischarge = 0.693R67C (output ending low)

(23)

Using these formulas with the three parameters available it

is quite easy to design the 555 to give any reasonable duty
cycle and oscillation frequency for a square wave going between ground (low) and Vcc (high). Data sheets show how to
use it for such applications as frequency division, ramp generation, pulse width modulation, and pulse position modulation.

THE VAN DER POL OSCILLATOR

A robust astable multivibrator is obtained by using small
damping in the van der Pol oscillator. The robustness results
from the van der Pol oscillator being structurally stable,
which makes it both practically and mathematically important. The van der Pol oscillator is described by the secondorder differential equation
dy
d2y
+y=0
+ (y2 1)
dt 2
dt

d y df(y)
+y=
+
dt 2
dy

Tperiod = 0.693(R78 +2R67 )C, f =

1
Tperiod

(27)

where is a parameter that determines the nature of the relaxation oscillation ( small gives close to a sine wave, while
large gives close to a square wave). Observing Eq. (27) we
see that if y2 1 then we have positive damping and the
signal decays, while if y2 1 there is negative damping and
the signal grows; consequently the signal heads toward y2
1. To set up a means to realize this multivibrator we first
obtain the equivalent state variable description by rewriting
Eq. (27) as

(24)

for a period and frequency of

67

1.44
(R78 +2R67 )C
(25)

f (y) = 

dy
dt

1
3

+ f (y)
dt


+y=0

(28)

y3 y

(29)

Then by setting
and a duty cycle of
x1 = y
R67
Duty cycle =
R78 + 2R67

(26)

x2 =

dx1
dy
+ f (y) =
+ f (x1 )
dt
dt

(30)
(31)

and rewriting (30) and (31), upon using (28), we get

1
2
3
RL

GND

Vcc

Trigger

555
7
Discharge

Output

Threshold

Reset

Control

R7-8
R6-7

6
5

+
Vcc

Cbias

Figure 10. 555 Timer connected as an astable multivibrator.

dx1
= f (x1 ) + x2
dt

(32)

dx2
= x1
dt

(33)

Figure 11(a) shows a circuit realization of these equations using capacitors to form the derivatives, voltage-controlled current sourcesmade via transistors as differential pairs (12,
p. 431) to realize the cross coupling, and a nonlinear (voltagecontrolled) resistor to realize f( ). By changing the time scale
and by multiplying the equations by constants, circuit components and waveform frequencies of interest can be obtained.
However, this design is predicated on obtaining the cubic law
nonlinear resistor, which is inconvenient. Fortunately, the
equations are structurally stable and allow for similar results

MULTIVIBRATORS

R1

i
+

+
C1

x1

i = f(x1)

Vdd

i = x1

Vdd

+
+

x2

C2

R2

R
+

i = x2
(a)

(b)
van der Pol PWL nonlinearity and limit cycle
6
4
2
x2 and f(x1)

68

LPQ

Q
x1

f(x1)

6
0.6

0.4

0.2

0
x1

0.2

0.4

(d)

(c)
Limit cycle vs time
6
4
2
x1
x

0
2
x2
4
6

10

15

20
t

25

30

35

40

(e)
Figure 11. (a) A van der Pol oscillator constructed with voltage-controlled current. (b) Op-amp
piecewise linear circuit to approximate cubic law of Eq. (29). (c) Limit cycle construction in state
space. (d) Limit cycle obtained from Matlab runs of Eqs. (32) and (33) with piecewise linear
f(x1). (e) Waveforms obtained from Matlab runs. x1(t) is a square wave and x2(t) is a triangular
wave.

0.6

MULTIVIBRATORS

for a piecewise linear function approximation to the cubic. For

this the cubic can be replaced by

ax b for x d
f (x) = cx
(34)
for d x d

ax + b for d x




b  (a + c) 
b 
(a + c) 
(35)
= ax
x + a + c  +
x a + c 
2
2

Vcc
R2

R1
1.0k
C1

R3

100k

R4

100k

1.0k
C2

Q1

Q2

R2
,
R1 R

d=

Vdd
R
1+ 2
R

5.0 V

The van der Pol oscillator finally results by inserting the circuit of Fig. 11b into Fig. 11a.
To see the multivibrator nature of the van der Pol oscillator, we look at the limit cycle in state space. Figure 11(c)
shows a plot of f(x1) inserted into the state space plane x1 x2.
Trajectories in this state space are determined by Eqs. (32)
and (33), for which we find, by simple division
dx2
x1
=
dx1
x2 f (x1 )

(a)

(36)

V(1)

c=

0V
5.0 V

V(2)

Vdd
,
R1

(37)

Consequently, the slope of the trajectory at any point is well

determined, and we can construct the trajectory by determining this slope graphically as follows: Choose a point P of interest and drop a perpendicular to the x1 and x2 axes; that gives
x1 and x2 at P, x1P, and x2P. Next drop a perpendicular from
f(x1P) to the x2 axis, intersecting at Q, and draw a line LPQ
from P to Q. The slope of LPQ is 1/(dx1 /dx2) by (37), and by
trigonometry the slope of the line perpendicular to LPQ is the
negative inverse of this, which is dx1 /dx2. Connecting nearby
points on this line gives the trajectory. From this construction
we can see that there is one limit cycle toward which all trajectories converge (except the [unstable] one at the origin).
We also easily see that if the slope of the negative conductance portion is small in magnitude, then the limit cycle is
close to a circle giving sinusoidal-like oscillations. But if the
slope of the negative conductance portion of f( ) is large, then
the oscillations are close to a square wave, as desired for a
multivibrator. Figures 11(d)(e) show a typical phase-plane
plot of a limit cycle and waveforms obtained from Matlab
runs.
By using an f(v) which is odd, f(v) f(v), with multiple
negative resistance regions, one can obtain many different
limit cycles and consequently make a multivibrator that has
more than two vibration levels.
TRANSISTORIZED CIRCUITS
Figures 12(a)(b) show an astable BJT (Bipolar Junction
Transistor) circuit (13, pp. 285289) along with typical waveforms. Noting these waveforms, we see that transitions result
at the end of the first-order exponential rises in the baseemitter voltages v2 and v3. If we take T1 to be the time when
v1 is high, then T1 R3C2 ln 2, which is found by equating

0V
5.0 V

V(3)

b=

5V

10p

0V
5.0 V

V(4)

1
,
R1

+
4

50p

We can design this piecewise linear current vs voltage law,

i f(v), via the op-amp circuit of Fig. 11(b), which results in
the parameters

a=

69

0V

6
Time ( s)

10

(b)
Figure 12. (a) BJT astable multivibrator. (b) Waveforms for the
astable multivibrator obtained from PSpice runs.

the current in R3 at T1, of value 2Vcc /R3, to its exponentially

decaying value from the previous transition, (2Vcc /R3)
exp(T1 /(R3C2)). For the value T2 for which v4 remains high,
we similarly find T2 R2C1 ln 2. Consequently, the period is
independent of Vcc and is given by
Tperiod = T1 + T2 = 0.7(R2C1 + R3C2 )

(38)

with various duty cycles possible.

Figures 13(a)(b) show a bistable BJT multivibrator circuit (2, p. 300) with its node voltages. One of the two stable
states is triggered by a positive pulse Vin1, of amplitude Vcc, at
the left input, and the other by a similar pulse Vin2 applied at

70

MULTIVIBRATORS

R2
5k

R1
20k

R3
20k

R4
20k

R5
5k

R6
20k
+

Vcc

Q1
Vin1

Q4
Q2

5V

Q5

Q3

Q6

Q7

Q8
Vin2

(a)

5.0 V
V(in1)
V(in2)
0V
5.0 V
V(1)
0V
2.0 V
V(2)
0V
2.0 V
V(3)
0V
10 V
V(4)
0V
0s

0.5

1.0
Time (ms)
(b)

1.5

2.0
Figure 13. (a) BJT bistable multivibrator. (b) Voltage waveforms for the
bistable multivibrator obtained from PSpice runs.

the right. As can be seen from the waveforms, a pulse at the

right, on the emitter of Q8, is transmitted through Q8 to raise
the base voltage of Q7, which by its increased collector current
causes v4 to drop. In turn this drop is fed through Q4, lowering
the base-emitter voltage of Q3 and decreasing the current in
R2 to raise v1, which is fed back to the base of Q6 via Q5 to
reinforce the lowering of v4. The result of the positive feedback is a very sharp rise. Thus the risetime is limited only by
the transition delays of the transistors.
Figures 14(ab) show a BJT monostable multivibrator (13,
pp. 290292) along with typical waveforms. Essentially this
is the multivibrator of Fig. 12(a), with C2 replaced by a resistor and a voltage divider, including R5 and Vss, to insure that
the base of Q1 will be biased to bring the transition consistently to the same stable state. As can be verified from the

waveforms, the pulse width is determined by the time constant that determines the rise of v3. Since during the pulse
transition, the transistor Q1 (being saturated) acts as a short
between collector and emitter, the time constant is just R2C1.
Roughly, during the pulse, v3 rises from Vcc to Vcc and stops
when it reaches 0 (actually at Vbe(on) of about 0.7 V). Because
v3(t) Vcc 2Vcc exp(t/(R2C1) we calculate
Tpulsewidth = R2C1 ln 2

(39)

The most frequent means of making multivibrators using

MOS transistors are through the logic circuits shown in the
logic gate circuits section above, where the gates are constructed in CMOS form, but others are described in the literature (1416).

MUSICAL INSTRUMENTS

R1
3k

R2
50k

R4
1k

R3 50k
1
C1

5n

4
+

Q1
Iin

Q2

R5
100k

Vcc
5V

Vss
5 V

(a)

0A
I(in1)
100 A

10 V
V(1)
0V

1.0 V

3. T. F. Schubert, Jr. and E. M. Kim, Active and Non-Linear Electronics, New York: Wiley, 1996, Chap. 13.
4. M. N. Horenstein, Microelectronic Circuits and Devices, 2nd ed.,
Upper Saddle River, NJ: Prentice-Hall, 1996, Sect. 15.2.
5. R. Boylestad and L. Nashelsky, Electronics: A Survey, 3rd ed.,
Englewood Cliffs, NJ: Prentice-Hall, 1989, Sect. 12.5.
6. S. D. Ferris, Elements of Electronic Design, Minneapolis, MN:
West Publishing Company, 1995, Chap. 12.
7. B. Linaras-Barranco, E. Sanchez-Sinencio, and A. Rodriguez-Vazquez, CMDS circuit implementation for neuron models, Proc.
IEEE Int. Symp. Circuits Syst., New Orleans, LA, pp. 2421
2424, 1990.
8. J. M. Rabaey, Digital Integrated Circuits, Upper Saddle River,
NJ: Prentice-Hall, 1996, Chap. 6.
9. A. J. Tocci, Digital Systems, Principles and Applications, 6th ed.,
Upper Saddle River, NJ: Prentice-Hall, 1995.
10. National Semiconductor, Linear Databook, Santa Clara, CA:
1982.
11. C. J. Savant, Jr., M. S. Roden, and G. L. Carpenter, Electronic
Circuit Design, An Engineering Approach, Menlo Park, CA:
Benjamin/Cummings, 1987.
12. R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Techniques for Analog and Digital Circuits, New York: McGraw-Hill,
1990.
13. P. H. Beards, Analog and Digital Electronics, 2nd ed., New York:
Prentice-Hall, 1991.
14. I. M. Filanovsky and I. G. Finvers, A simple nonsaturated CMOS
multivibrator, IEEE J. Solid-State Circuits, 23(1): 289292, 1988.
15. D. J. Comer, Electronic Design with Integrated Circuits, Reading,
MA: Addison-Wesley, 1981, Chap. 3.
16. G. M. Blair, Comments on new single-clock CMOS latches and
flip-flops with improved speed and power savings, IEEE J. Solid
State Circuits, 32(10): 16101611, 1997.

V(2)

ROBERT W. NEWCOMB

1.0 V

University of Maryland, College

Park

LOUIZA SELLAMI

4.0 V

U.S. Naval Academy

V(3)

MULTIVIBRATORS. See VARIABLE-FREQUENCY OSCIL-

4.0 V

LATORS.

5.0 V

MUSCLE SIGNALS. See ELECTROMYOGRAPHY.

V(4)
0V
0s

0.5

1.0
Time (ms)

1.5

2.0

(b)
Figure 14. (a) BJT monostable multivibrator. (b) Voltage waveforms
for the monostable multivibrator obtained from PSpice runs.

BIBLIOGRAPHY
1. A. S. Sedra and K. C. Smith, Microelectronic Circuits, New York:
Oxford Univ. Press, 4th ed., 1997, Chap. 12.
2. D. A. Hodges and H. G. Jackson, Analysis and Design of Digital
Integrated Circuits, 2nd ed., New York: McGraw-Hill, 1988,
Chap. 8.

71

NETWORK PARAMETERS

The Laplace transform is commonly used to solve network

equations. However, the mere computation of the solution
of network equations is one of the many important applications for this elegant tool of network analysis. Our purpose here is to use this transform to dene network function and to study the different ways of its representation,
the superposition theorem, the characterizations and representations of one-port and two-port networks (13).
NETWORK PARAMETERS

same pair of terminals, it is referred to as the driving-point

or input function; and for different pairs of terminals, the
transfer function. Since the input and the response may either be a current or a voltage, the network function may be
a driving-point impedance, a driving-point admittance, a
transfer impedance, a transfer admittance, a transfer voltage ratio, or a transfer current ratio. Our objective here
is to obtain some general and broad properties of network
functions, recognizing that each of the network functions
mentioned has its own distinct characteristics.
Example. We write the nodal equations for the network
of Fig. 1 for t 0 after the switch S is closed and compute
the input impedance Zin facing the current source I and the
transfer current ratio relating the transform current I6 to
the transform current source I.
The nodal equations are found to be

We begin by considering a system of differential equations

associated with an electrical network, most conveniently
written in matrix notation as

where W(p), x(t), and f(t) are used to represent the coefcient matrix of the differential operator p, the unknown
vector x(t) and the known forcing or excitation vector f(t).
On taking the Laplace transform on both sides, we obtain
a system of linear algebraic equations

where X(s) and F(s) denote the Laplace transforms of x(t)

and f(t), respectively, and h(s) is a vector that includes the
contributions due to initial conditions. The coefcient matrix W(s) in the complex frequency variable s is obtained
from W(p), with s replacing p. An analysis of Eq. (2) is often
referred to as analysis in the frequency domain, in contrast
to the analysis of Eq. (1), which is called analysis in the time
domain.
Network Functions
The unknown transform vector X(s) can be obtained immediately by inverting the matrix W(s):

provided that det W(s) is not identically zero.

Consider a linear time-invariant network that contains
a single independent voltage or current source as the input
with arbitrary waveform. Assume that all initial conditions
in the network have been set to zero. Let the response be
either a voltage across any two nodes of the network or a
current in any branch of the network. Such a response is
known as the zero-state response. Then, the network function H(s) is dened by

Network functions generally fall into two classes depending on whether the terminals to which the response relates
are the same or different from the input terminals. For the

By using Cramers rule, the nodal voltage V1 can be expressed in terms of the source current I as

Principle of Superposition
The principle of superposition is intimately tied up with the
concept of linearity, and is applicable to any linear network,
whether it is time invariant or time varying. It is fundamental in characterizing network behavior and is very useful in solving linear network problems. For our purposes,
we shall restrict ourselves to the class of linear time invariant networks.
Consider an arbitrary linear time-invariant network
with many input excitations describable by a system of linear algebraic equations:

where

and the prime denotes matrix transpose. Suppose that the

kth row variable Xk of X(s) is the desired response. By appealing to Cramers rule, we obtain from Eq. (8)

Observe that Fi (s) (i = 1, 2, . . . , n) are due to the contributions of independent sources. Therefore, to compute the
complete response transform Xk , we may consider each of
the transform sources Fi one at a time and then add the partial responses so determined to obtain Xk . If Fi represents a

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Network Parameters

Figure 1. A network used to illustrate network functions.

linear combination of many sources, each source can again

be considered separately, one at a time, and then add these
partial responses to obtain the complete response. This is
in essence the superposition principle.
Superposition Theorem. For a linear system, the zerostate response due to all the independent sources acting
simultaneously is equal to the sum of the zero-state responses due to each independent source acting one at a
time. If, in addition, the system is time invariant, the same
holds in the frequency domain.
Two aspects of superposition are important to emphasize. The rst is the additivity property. The other is the
homogeneity property, which states that if all sources are
multiplied by a constant, the response is also multiplied by
the same constant.
Different versions of the superposition principle can be
advanced. It states that in a linear time-invariant system
the zero-input response is a linear function of the initial
state, the zero-state response is a linear function of the input, and the complete response is the sum of the zero-input
response and the zero-state response. Thus, the complete
response of a linear network to a number of excitations
applied simultaneously is the sum of the responses of the
network when each of the excitations is applied individually. This statement remains valid even if we consider the
initial capacitor voltages and inductor currents themselves
to be separate excitations. Of course, the controlled sources
cannot be considered as separate excitations. In the case
of linear time-invariant networks, the same holds in the
frequency domain or in the transform network.
We apply the principle of superposition to compute the
inductor current i2 in the network of Fig. 2. When the voltage source is short-circuited, the inductor current i2 (t) is
found to be

When the current source is removed, the inductor current

i2 (t) is obtained as

Figure 2. A network used to illustrate the principle of superposition.

The inductor current i2 (t) is the algebraic sum of these two

currents:

Two-Port Networks
A network is a structure comprised of a nite number of
interconnected elements with a set of accessible terminal
pairs called ports at which voltages and currents can be
measured and the transfer of electromagnetic energy into
or out of the structure can be made. The situation is similar
to ships leaving or entering the ports. Fundamental to the
concept of a port is the assumption that the instantaneous
current entering one terminal of the port is always equal
to the instantaneous current leaving the other terminal of
the port. This assumption is crucial in subsequent derivations and resulting conclusions. If it is violated, the terminal pair does not constitute a port. A network with one
such accessible port is called a one-port network or simply
a one-port, as represented in Fig. 3(a). If a network is accessible through two such ports as shown in Fig. 3(b), the
network is called a two-port network or simply a two-port.
The nomenclature can be extended to networks having n
accessible ports called the n-port networks or n-ports.
Figure 4 is a general representation of a one-port that
is electrically and magnetically isolated except at the port
with sign convention for the references of port voltage and
current as indicated. Likewise, Fig. 5 is a general representation of a two-port that is electrically and magnetically
isolated except at the two ports with sign convention for
the references of port voltages and currents as indicated.
By focusing attention on the ports, we are interested in the
behavior of the network only at the ports. Our discussion
will be entirely in terms of the transform network, under
the assumption that the one-port or two-port is devoid of

Network Parameters

Figure 6. Representation of a two-port in terms of its shortcircuit admittance parameters yij .

Figure 3. Symbolic representations of a one-port network (a), a

two-port network (b), and an n-port network (c).

Figure 7. Networks used to compute the short-circuit admittance

parameters yij of a two-port.

Figure 4. A general representation of a one-port with port voltage

and current shown explicitly.

Figure 8. A small-signal network model of a transistor.

Figure 5. A general representation of a two-port with port voltages and currents shown explicitly.

culate these parameters, we set either V1 or V2 to zero and

obtain

independent sources inside and has zero initial conditions.

Short-Circuit Admittance Parameters. Refer to Fig. 5.

There are four variables associated with the two ports: V1 ,
V2 , I1 , and I2 . Suppose that we choose port voltages V1 and
V2 as the independent variables. Then, the port currents
I1 and I2 are related to the port voltages V1 and V2 by the
equation

The choice of the name short circuit becomes obvious.

In computing y11 and y21 , the port V2 is short-circuited,
whereas for y12 and y22 , the port V1 is short-circuited, as
depicted in Fig. 7.
Example. Consider the equivalent network of a transistor amplier shown in Fig. 8. Applying Eq. (16) yields

or, in matrix form,

where I(s) = [I1 I2 ] is the port-current vector and V(s)

= [V1 V2 ] is the port-voltage vector. Equation (13) can be
represented equivalently by the network of Fig. 6. The four
admittance parameters yij (i, j = 1, 2) are called the shortcircuit admittance parameters or simply the y-parameters.
The coefcient matrix Y(s) is referred to as the short-circuit
admittance matrix or simply the admittance matrix. To cal-

giving the short-circuit admittance matrix as

Open-Circuit Impedance Matrix. Instead of choosing the

port voltages V1 and V2 as the independent variables, sup-

Network Parameters

Figure 9. Representation of a two-port in terms of its open-circuit

impedance parameters zij .

Figure 10. Networks used to compute

impedance parameters zij of a two-port.

the

Figure 11. Representation of a two-port in terms of its hybrid

parameters hij .

open-circuit

pose that we choose port currents I1 and I2 as the independent variables. Then, V1 and V2 are related to I1 and I2 by
the equation

or, in matrix form,

Equation (18) can be represented equivalently by the network of Fig. 9. The four impedance parameters zij (i,j =
1,2) are called the open-circuit impedance parameters or
simply the z parameters. The coefcient matrix Z(s) is referred to as the open-circuit impedance matrix or simply
the impedance matrix. Obviously, if Z(s) is not identically
singular, its inverse is the short-circuit admittance matrix
or

and vice versa. To calculate these parameters, we set either

I1 or I2 to zero and obtain

The choice of the name open circuit becomes obvious. In

computing z11 and z21 , the port I2 is open-circuited, whereas
for z12 and z22 , the port I1 is open-circuited, as depicted in
Fig. 10.
Example. Consider the equivalent network of a transistor amplier shown in Fig. 8. Applying Eq. (21) yields

Figure 12. Networks used to compute the hybrid parameters hij

of a two-port.

giving the open-circuit impedance matrix as

The Hybrid Parameters. Suppose that we choose port

variables I1 and V2 as the independent variables. Then,
the remaining port variables V1 and I2 are related to I1
and V2 by the equation

or, in matrix form,

where y(s) = [V1 I2 ] and u(s) = [I1 V2 ] . Equation (24)

can be represented equivalently by the network of Fig. 11.
The four immittance parameters hij (i,j = 1,2) are called
the hybrid parameters or simply the h parameters. The
coefcient matrix H(s) is referred to as the hybrid matrix.
To calculate these parameters, we set either I1 or V2 to zero
and obtain

In computing h11 and h21 , the port V2 is short-circuited,

whereas for h12 and h22 , the port I1 is open-circuited, as
depicted in Fig. 12. Thus, h11 is the short-circuit input
impedance, h21 is the short-circuit forward current ratio,
h12 is the open-circuit reverse voltage ratio, and h22 is the
open-circuit output admittance. These parameters are not
only dimensionally mixed but also under a mixed set of
terminal conditions. For this reason they are called hybrid
parameters.

Network Parameters

ones to use in a cascade, tandem, or chain connection of twoports. We remark that there is a negative sign associated
with I2 , being a consequence of our choice of reference for
I2 in Fig. 5. To calculate these parameters, we set either V2
or I2 to zero and obtain
Figure 13. Representation of a two-port in terms of its inverse
hybrid parameters gij .

Example. Consider the equivalent network of a transistor amplier shown in Fig. 8. Applying Eq. (27) yields
Example. Consider again the equivalent network of a
transistor amplier shown in Fig. 8. Applying Eq. (34)
yields
giving the hybrid matrix as

Inverse Hybrid Parameters. Suppose now that we choose

V1 and I2 as the independent variables. Then I1 and V2 are
related to V1 and I2 by the equation

or, in matrix form,

Equation (30) can be represented equivalently by the network of Fig. 13. The four immittance parameters gij (i,j =
1,2) are called the inverse hybrid parameters or simply the
g parameters. The coefcient matrix G(s) is referred to as
the inverse hybrid matrix. To calculate these parameters,
we set either V1 or I2 to zero and obtain

giving the transmission matrix as

By interchanging the roles of the excitation and the response in Eq. (33), we obtain yet another set of parameters
called the inverse transmission or inverse chain parameters, and their corresponding matrix the inverse transmission or inverse chain matrix, the details of which are
omitted.
Interrelations Among the Parameters Sets
The various ways of representing the external behaviors of
a two-port are presented in the foregoing. Each nds useful applications, depending on the problem on hand. Table
1 gives the interrelationships among the different sets of
parameters.
Interconnection of Two-Ports

If G(s) is not identically singular, its inverse is the hybrid

matrix or

Transmission Parameters. Another useful set of parameters is formed by choosing V2 and I2 as the independent
variables. Then V1 and I1 are related to V2 and I2 by the
equation

Simple two-ports are interconnected to yield more complicated and practical two-ports. Two two-ports are said to be
connected in cascade or tandem if the output terminals of
one two-port are connected to the input terminals of the
other, as depicted in Fig. 14. This type of connection is
most conveniently described by the transmission parameters. From Fig. 14 we have for the two-port Nb

and for two-port Na

The four immittance parameters A, B, C, and D are called
the transmission parameters, which are also known as the
chain parameters or the ABCD parameters. The coefcient
matrix is referred to as the transmission matrix. The rst
two names come from the fact that they are the natural

where the subscripts a and b are used to distinguish the

transmission parameters of Na and Nb . Combining Eqs.

Network Parameters

(37) and (38) gives

showing that the coefcient matrix, being the product of

two matrices, is the transmission matrix of the composite
two-port N. Thus, the transmission matrix of two two-ports
connected in cascade is equal to the product of the transmission matrices of the individual two-ports:

Figure 14. Symbolic representation of two two-ports connected

in cascade.

Another useful connection is depicted in Fig. 15 where the

input terminals and output terminals of the individual
two-ports are connected in parallel, and is called a parallel
connection. This connection forces the equality of the terminal voltages of the two-ports, and is most conveniently described by the short-circuit admittance parameters. From
Fig. 15 we have
Figure 15. Symbolic representation of two two-ports connected
in parallel.

showing that the short-circuit admittance matrix of the

composite two-port N is the sum of those of the component
two-ports Na and Nb .
We remark that the validity of Eq. (41) is based on the
assumption that the instantaneous current entering one
terminal of a two-port is equal to the instantaneous current
leaving the other terminal of the two-port after the interconnection. If this condition is violated, the statement that
when two two-ports are connected in parallel, their admittance matrices add is no longer valid. To ensure that the
nature of the ports are not altered after the connection, we

employ the Brunes test as shown in Fig. 16: the voltage

marked V is zero. If Brunes test is not satised, an ideal
transformer with turns ratio 1:1 is required, and this transformer needs to be inserted either at the output or input
port of one of the two-ports.
Example. Figure 17 is a simple RC twin-Tee used in the
design of equalizers. This two-port N can be considered as
a parallel connection of two two-ports Na and Nb of Fig.
18. It is easy to verify that the Brunes test is satised and
the short-circuit admittance matrix Y(s) of the twin-Tee is
simply the sum of those Ya (s) and Yb (s) of the component

Network Parameters

Figure 16. Brunes test for parallel connection of two two-ports.

Figure 19. Symbolic representation of two two-ports connected

in series.

Figure 17. A twin-Tee used in the design of equalizers.

Figure 20. Brunes test for series connection of two two-ports.

Figure 18. The parallel connection of two two-ports to form the

twin-Tee of Fig. 17.

two-ports Na and Nb :

Two two-ports Na and Nb are said to be connected in series if they are connected as shown in Fig. 19. This connection forces the equality of the terminal currents of the
two-ports, and is most conveniently described by the opencircuit impedance parameters. From Fig. 19 we have

showing that the open-circuit impedance matrix of the

composite two-port N is the sum of those of the component
two-ports Na and Nb .
Note again that the validity of Eq. (43) is based on the
assumption that the instantaneous current entering one
terminal of a two-port is equal to the instantaneous current leaving the other terminal of the two-port after the

Figure 21. Symbolic representation of two two-ports connected

in series-parallel.

Figure 22. Symbolic representation of two two-ports connected

in parallel-series.

interconnection. If this condition is violated, the previous

statement is no longer valid. To test to see if this condition
is satised, we employ the Brunes test as shown in Fig. 20:
the voltage marked V is zero. If Brunes test is not satised,
an ideal transformer with turns ratio 1:1 is required, and
this transformer needs to be inserted either at the output
or input port of one of the two-ports.
Combinations of the parallel and series connections are
possible such as the series-parallel and parallel-series connections shown in Figs. 21 and 22.

Network Parameters

available average power P1a at the source:

Gp =

P2a
P1a

(48)

Therefore, it is a function of the two-port parameters and

the source impedance Z1 , being independent of the load
impedance Z2 .
Finally, the third and most useful measure of power ow
is known as the transducer power gain G dened as the
ratio of average power P2 delivered to the load to the maximum available average power P1a at the source:

Figure 23. A feedback network N.

G=

Figure 24. A decomposition of the feedback network N into three

two-ports Na , Nb , and Nf .

Example. Consider the feedback network N of Fig. 23.

To compute its short-circuit admittance matrix Y(s), it is
advantageous to consider N as being composed of two twoports Na and Nb connected in cascade and then in parallel
with another Nf as depicted in Fig. 24. The transmission
matrix of the two two-ports Na and Nb connected in cascade, being the product of their transmission matrices, is
given by

P2
P1a

Clearly, it is a function of the two-port parameters and the

source and load impedances Z1 and Z2 . It is important because it compares the average power delivered to the load
with the average power that the source is capable of supplying under the optimum terminations, thereby making
this the most meaningful description of the power transfer
capabilities of a two-port network. Notice that the three
power gains can only be meaningfully dened on the realfrequency axis s = j. In other words, we have substituted
s = j in all the equations, even though they are not explicitly shown.
To show how these power gains can be expressed in
terms of the two-port parameters of Fig. 5 and Z1 and Z2 ,
we substitute V2 = I2 Z2 in Eq. (18) and solve for I1 and
I2 , yielding
I2
z21
=
I1
z22 + Z2

where yija are the y-parameters of Na and
y = y11a y22a

y12a y21a . The corresponding admittance matrix of Eq. (44)
is found from Table 1 as

The short-circuit admittance matrix Y(s) of the overall twoport N of Fig. 23 is obtained as

(49)

(50)

The average power P1 entering the input port and the average power P2 delivered to the load Z2 are given by
P1 = |I1 |2 Re Z11

(51)

P2 = |I2 |2 Re Z2

(52)

where Z11 is the impedance looking into the input port with
the output port terminating in Z2 .
The maximum available average power P1a at the input
port is attained, when the source impedance Z1 and the

input impedance Z11 are conjugately matched, or Z11 = Z1 ,

the complex conjugate of Z1 , giving
P1a =
Power Gains
Refer to the two-port network of Fig. 5. The simplest measure of power ow in N is the power gain Gp dened as the
ratio of the average power delivered to the load P2 to the
average power entering the input port P1 :
Gp =

P2
P1

(53)

where Vs is the voltage source at the input port.

To express Z11 in terms of the two-port parameters zij
and Z2 , we substitute V2 = I2 Z2 in Eq. (18) and solve for
I1 , yielding
Z11 =

(47)

which is a function of the two-port parameters and the load

impedance Z2 , being independent of the source impedance
Z1 . For a passive and lossless two-port network, G p = 1.
The second measure of power ow is called the available power gain Ga dened as the ratio of the maximum
available average power P2a at the load to the maximum

|Vs |2
4 Re Z1

V1
z12 z21
= z11
I1
z22 + Z2

(54)

Combining Eqs. (51)(55) obtains

Gp =

P2
|z21 |2 Re Z2
|z21 |2 Re Z2
=
=
P1
|z22 + Z2 |2 Re Z11
|z22 + Z2 |2 Re(z11
G=

4|z21 |2 Re Z1 Re Z2
P2
=
P1a
|(z11 + Z1 )(z22 + Z2 ) z12 z21 |2

z12 z21 (55)

)
z22 +Z2

(56)

Network Parameters

For the available power gain, we rst compute Thevenin

equivalent voltage Veq and impedance Zeq looking into the
output port of Fig. 5, when the input port is terminated
in a series combination of a voltage source Vs and source
impedance Z1 :
z12 z21
(57)
Zeq = z22
z11 + Z1
Veq =

z21 Vs
z11 + Z1

(58)

Using this Thevenin equivalent network, the maximum

available average power at the output port is attained

when Z2 = Zeq , the complex conjugate of Zeq , obtaining

P2a =

|z21 |2 |Vs |2
4|z11 + Z1 |2 Re Zeq

(59)

The available power gain is found to be

Ga =

P2a
|z21 |2 Re Z1
=
P1a
|z11 + Z1 |2 Re Zeq

(60)

which in conjunction with Eq. (57) gives

Pa =

P2a
|z21 |2 Re Z1
=
P1a
|z11 + Z1 |2 Re(z22

z12 z21
)
z11 +Z1

(61)

Likewise, we can evaluate the three power gains in terms

of other two-port parameters as follows:
Gp =

P2
P1

=
=

G=

P2
P1a

Pa =

P2a
P1a

|z21 |2 Re Z2
|z22 + Z2 |2 Re(z11
|h21 |2 Re Y2

z12 z21
)
z22 + Z2

|y21 |2 Re Y2
|y22 + Y2 |2 Re(y11

y12 y21
)
y22 + Y2

(62)

h12 h21
)
h22 + Y2
2
4|z21 | Re Z1 Re Z2
4|y21 |2 Re Y1 Re Y2
=
=
|(z11 + Z1 )(z22 + Z2 ) z12 z21 |2
|(y11 + Y1 )(y22 + Y2 ) y12 y21 |2
(63)
4|h21 |2 Re Z1 Re Y2
=
|(h11 + Z1 )(h22 + Y2 ) h12 h21 |2
|y21 |2 Re Y1
|z21 |2 Re Z1
=
=
z
y12 y21
z
12
21
|z11 + Z1 |2 Re(z22
|y11 + Y1 |2 Re(y22
)
)
z11 + Z1
y11 + Y1
(64)
2
|h21 | Re Z1
=
h12 h21
|h11 + Z1 |2 Re(h22
)
h11 + Z1
|h22 + Y2 |2 Re(h11

BIBLIOGRAPHY
1. W. K. Chen Linear Networks and Systems: Algorithms and
Computer-Aided Implementations, Vol. 1 Fundamentals, 2nd
ed., Singapore: World Scientic, 1990.
2. M. E. Van Valkenburg, Network Analysis, 3rd ed., Englewood
Cliffs, NJ: Prentice-Hall, 1974.
3. W. K. Chen Active Network Analysis, Singapore: World Scientic, 1991.

WAI-KAI CHEN
University of Illinois at Chicago,
Chicago, IL

NOISE GENERATORS
GENERATION OF NOISE

second-order statistics do not change over time, the process

is called wide-sense stationary (4).
Power spectral density, a standard measure used to describe a wide-sense stationary process, is dened as the
Fourier transform of the autocorrelation function RX () (4):

APPLICATIONS OF NOISE

Noise is a broadbanded signal generated by environmental effects, such as lightning, or by man-made electrical
devices. Two common categories of noise are thermal noise
and shot noise. Looney (1) describes thermal noise as an
electromotive force generated at the open terminals of a
conductor due to the charges bound to thermally vibrating
molecules. This type of noise is often referred to as Johnson noise in recognition of the rst observations of the phenomenon (2). On the other hand, shot noise is associated
with the passage of current across a barrier. For instance,
a circuit or an appliance that produces electric arcing produces noise. Shot noise was rst described by Schottky using the analogy of a small shot patterning into a container
(3). Noise can be felt in audio systems as a crackle. Noise
appears as white or black spots on a television screen.
Noise is generally characterized as a source of corruption of information and therefore is treated as an undesired
signal. Noise contaminates informational signals to a certain extent by superimposing extrasignal uctuations that
assume unpredictable values at each instant. Noise has
been studied extensively in the literature because noise
reduction is one of the major goals. A more compelling reason for the study of noise is its potential application in real
life. These applications encompass biomedical engineering,
electronic circuits, communication systems, cryptography,
computers, electroacoustics, geosciences, instrumentation,
and reliability engineering. This article addresses the various noise generation techniques and implementing them
in analog and digital circuit technology and concludes with
a discussion of typical applications.
MODELING OF NOISE
A mathematical model of a phenomenon, such as noise, allows us to understand its generation, characteristics and
application well. We start with the observation that the
structures of thermal and shot noise are similar, although
their sources are different. Both types of noise can be represented as a random wave form consisting of a sequence
of peaks randomly distributed in time. A noise signal can
be modeled by a random process X(t) with a probability
distribution for the values of x it assumes. Any particular
set of outcomes {(t, xt )} of the random variable Xt is called
a realization of the noise process. An adequate characterization of such a random process can be often made with
rst- and second-order statistics. The rst-order statistic
of X(t) is the expected value E[X(t)] and the second-order
statistic is the autocorrelation function RX () = E[X(t)X(t +
)], where E is the expectation operator. When the rst- and

With this modeling, we can analyze the spectra of noise.

White noise is a wide-sense stationary process with zero
mean. It has constant power spectral density over all frequencies. Stated another way, white noise is a process
that is uncorrelated over time. The most mathematically
tractable noise is the Gaussian wide-sense stationary process, where at each time t the probability distribution for
the random variable Xt = X(t) is Gaussian.
Colored noise is a variation of white noise which arises
from the fact that actual circuits attenuate signals above
certain frequencies. Therefore it makes sense to truncate
the white noise spectral density at both extremes. Noise
with this spectral characteristic is termed pink noise.
Apart from thermal noise and shot noise, a third category of noise observed in electronic systems is the 1/f noise.
It is so called because the power spectral density of this
noise varies with frequency as |f| , where takes values between 0.8 and 1.2. This type of noise is exhibited by
biological and musical systems in addition to electronics
(3). 1/f noise is variously called current noise, excess noise,
icker noise, semiconductor noise, and contact noise. It is
applied in medical treatment and also in engineering, justifying the need for inclusion in our study.
NOISE GENERATION TECHNIQUES
Noise can be generated in many different ways. A diode
tube operating at its saturation point produces broadband
noise. A semiconductor diode is an inexpensive source of
noise generation. When operated in the fully conducting
region, the diode produces broadband noise. A currentcarrying resistor produces thermal noise. It is necessary
to condition noise signals by proper amplication, modulation, and ltering to suit ones application at a desired
bandwidth. In our discussion of noise generation, we concentrate only on semiconductor techniques because approaches based on vacuum tubes are antiquated now.
The noise generation schemes range from simple mechanical techniques to electronic methods employing both
analog and digital circuits. Inexpensive noise generators
can be realized with discrete components and basic building blocks available in the IC market. We classify the noise
generators into two categories, namely, analog and digital,
based on their implementation.
Analog Techniques
Under this category, we discuss three different approaches:
(1) a mechanical scheme, (2) amplifying inherent noise in
op-amps, (3) oscillator method, and (4) using the chaotic
behavior of deterministic systems.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Applications of Noise

erate a noise of 50 nV/

. Op-amp AD829 is used in the
circuit which features at voltage noise in the range of 100
Hz to 10 MHz.

Figure 1. A simple analog noise generator based on amplication

of op-amp input noise.

Mechanical Approach. For audio-frequency noise, a very

simple scheme can be devised at home or in the laboratory
without any sophisticated circuits or components. Dunn (5)
uses just a linen-covered phonograph and a foam-covered
microphone. A piece of linen cloth is tied to the turntable
and a foam-covered microphone is used to pick up the signal. As the turntable rotates, the microphones foam cover
rubs along the surface of the linen, producing sound with
a nearly at spectral density in the audio-frequency range
of 20 Hz to 20 kHz. Dunn shows that by using a good hi-
microphone and a broadband amplier, the output signal
closely approximates white noise over the audio-frequency
range. Other mechanical approaches include the use of
gears and radioactive decay (6).
Amplication of Inherent Noise. The schematic of a relatively simple op-amp noise generator is shown in Fig.
1, which uses a single bipolar input amplier and some
discrete components. The principle used here to generate
wideband noise is to amplify its own input noise in a decompensated op-amp (7). Many op-amps have large 1/f input noise components. A bipolar input op-amp is chosen
because bipolar devices exhibit much less 1/f noise than
MOSFET devices.
In the gure, the op-amp is used as a xed-gain stage
amplier with a closed-loop gain factor:

If the input resistors R2 and R3 are chosen small, the thermal noise of the amplier is forced to a small value. This
choice of low values for the resistors also helps keep the
ampliers current noise component negligibly small when
it is converted to voltage noise. Thus, the dominant noise
of the circuit is the input voltage noise of the amplier.
The choice of a single gain stage amplier of the type
shown in Fig. 1 results in a frequency-independent noise.
This contrasts with multistage ampliers which may have
peaks in the output noise response caused by frequency
compensation effects. The values for resistors R1 and R2
can be designed by knowing the typical noise of the op-amp
from data sheets and the required level of noise across the
load RL . The output is coupled through a blocking capacitor
C1 which removes any amplied dc value at the output of
the amplier. However, the value of this capacitor should
be large enough to pass the lowest noise frequencies of interest. Interested readers may refer to Ref. 7 for a detailed
circuit diagram and typical component values used to gen-

Oscillator Method. A popular analog class of noise generators is the oscillator method (8), which samples the frequency noise or instability of free-running oscillators. In
this scheme, the output of a fast oscillator is sampled on
the rising edge of a slower clock using a D ip-op. Oscillator jitter causes uncertainty in the exact sample values,
ideally producing a random bit for each sample. For further
details, readers may refer to 9.
Using Chaos in Deterministic Systems. Another elegant
way of generating white noise is based on the observation
that certain simple deterministic systems exhibit chaotic
behavior (10). The chaos or noise is generated by iterating a map either electronically or in a software program.
A simple and most widely studied system for generating
chaos is the logistic map (10) given by:

The asymptotic behavior of the system described by the

parabolic transfer function of Eq. (3) depends on the value
of . McGonigal and Elmasry (11) show that values of
between 0.89 and 1.0 result in oscillations without any detectable period. In fact, this is the region of chaotic behavior
leading to power spectral density corresponding to white
noise.
A noise generator can be implemented in hardware to
test actual instruments or in software for simulation. McGonigal and Elmasry (11) use a multiplier and a difference amplier to realize the term xi x2i of the parabolic
transfer function of Eq. (3). A variable-gain amplier connected to the output of the differential amplier, as shown
in Fig. 2, allows variation of . The iteration of the transfer function is realized by the feedback of the xi+1 signal
as the next xi input. The clock-driven multiplexer and the
storage capacitors shown in the gure separate the impulses at the output of the circuit. During clock signal ck,
the voltage on capacitor C1 provides the input xi whereas
the resulting output xi+1 is stored on C2 . During <overline>ck</overline>, the roles of the capacitors are reversed
leading to two iterations of the parabolic function in every clock cycle. The IC numbers and typical values of the
discrete components are shown in the gure to generate a
power spectrum from dc to 1 kHz. Experimental study in
11 conrms that the signal is uncorrelated in the chaotic
region and that the power spectral density remains at in
this region. Interested readers may refer to 11 for further
details of the circuit and a trace of the power spectrum.
The software implementation of the deterministicchaotic, variably colored, noise generator is shown in Fig. 3.
Colored noise is generated by organizing chaotic elements
into a hierarchy and coupling them (12). Each element of
the hierarchy is modeled as a recursive loop whose output
is a sequence of impulses. The unit delay element shown in
the gure separates the instances of impulses of varying
amplitude at the output. The gain unit and the nonlinear
amplier implement the map xi+1 = gn f(xi ). The output at

Applications of Noise

Figure 2. A low-frequency noise generator

based on logistic map (from 11, courtesy of IEEE,
1987 IEEE).

Figure 4. Structure of a programmable noise generator.

Figure 3. Block schematic of a software-based, deterministicchaotic, variably colored noise generator.

any instant becomes the input at the next instant. The initiator block is used only to set the amplitude of the rst impulse and is then disconnected. This software setup yields
sequences of impulses which are essentially aperiodic and
hence noiselike from a practical point of view (12).
Researchers have used discrete, nonlinear, onedimensional maps (13) that yield a transition between
regions of chaotic motion to produce 1/f noise. The circuits used to implement such discrete maps are usually
switched-capacitor type because discrete maps are described by nonlinear, nite-difference equations and they
can be easily and accurately implemented by switchedcapacitor circuits. DelgadoRestituto et al. (14) build a
programmable prototype to generate colored noise to test
systems with spectral density proportional to 1/f. They
use op-amps and switched capacitors to realize a chaotic,
one-dimensional, piecewise-linear discrete map that yields
a hopping transition between regions of chaotic motion.
Murao et al. (15) propose a simple switched-capacitor
circuit that realizes a one-dimensional, nonlinear, discrete
map as opposed to a piecewise-linear approximation. With
an IC and a couple of logarithmic and antilogarithmic
ampliers, they can synthesize a simple 1/f noise generator over a wide range of frequencies compared with the
previous method of DelgadoRestituto et al. (14).

Of the four techniques of noise generation based on

chaotic behavior of deterministic systems discussed here,
the rst is used for white noise generation, whereas the
next three implementations generate colored noise. Although colored noise is derived by properly ltering the
output of white noise sources (16), the direct methods described here are simpler and lend themselves to easy VLSI
implementation. Some other simple IC-compatible chaos
generators are found in 17 and 18.
Programmable Noise Generators. It is often desirable to
have a programmable noise generator. The variability is
achieved by multiplying the noise signal by a factor K and
then passing the signal through a noise lter, as shown in
Fig. 4. A linear phase lter passes frequencies between F1
and F2 , thus band-limiting the lter output noise. In the
simulated noise generator of (19), the output is sampled at
a particular rate and stored in a data array. The statistics of
the output data, such as mean, variance, min, and max are
stored in another data array. This kind of programmable
noise generator produces uniform Gaussian noise whose
output noise power is set by adjusting the K factor shown
in the gure.
Digital Techniques
The rst generation digital noise generators utilized random waveforms based on telegraph signals to obtain random noise (20). For application in modern digital circuits,
however, pseudorandom number sequence generators provide a better basis. Pseudorandom numbers are generated
with linear congruent algorithms (21). If noise is needed

Applications of Noise

Figure 5. Block schematic of a basic digital noise generator.

in analog form, the numbers generated in binary form are

converted to analog quantity. The analog output at the converter is essentially Gaussian white noise. This signal can
be ltered appropriately to obtain colored noise. Figure 5
shows the block schematic of a digital noise generator.
Linear Feedback Shift Register as Random Number
Generator. The digital circuitry implementing the pseudorandom number generator can be realized using a linear
feedback shift register (LFSR). An LFSR consists of two basic digital building blocks, D-type ip-ops and exclusive-or
gates. The LFSR draws theory from cyclic error-detecting
codes (22) where all algebraic manipulations on polynomials are done in GF(2), that is, Galois eld-modulo-2 addition, subtraction, multiplication, and division of binary
vectors. A k-stage LFSR generates at most (2k 1) distinct
binary patterns which then repeat on itself. In general, the
length of the sequences generated depends on the size of
the LFSR and the polynomial representing it. If the polynomial representing the LFSR is primitive (22), the LFSR
generates a maximal length sequence [(2k 1) vectors]. If
the polynomial is irreducible but nonprimitive, then the
length of the sequence is not maximal and depends on the
initial contents of the LFSR, called the seed. The presence
of internal memory in the LFSR makes the choice of the
seed critical for nonprimitive case. In the primitive case,
the seed does not affect the statistical properties of the
output. However, if all of the ip-ops are set to zero, the
LFSR remains dormant and is useless.
The upper block of Fig. 6 shows an LFSR implementation of a primitive polynomial of degree six:

where is the exclusive-or operator. In this implementation of LFSRs, the output and selected internal stages of
the LFSR corresponding to the nonzero terms of the polynomial are exclusive-ored and fed back to the input. The
pseudorandom digital output sequence is plotted in Fig.
7. A clock frequency of 1 MHz is used to run the LFSR.
Because a six-stage LFSR is used, the period of the pseudorandom output waveform is 63 s. For clarity the gure
shows a couple of periods of the waveform.
In the following, we describe several implementations of
digital noise generators. They all have LFSRs as the basis
for random number generation and use low-pass ltering
to obtain the analog noise signal.
Analog Conversion by Time Integration. Alspector et al.
(23) use a low-pass lter to convert the digital waveform at
the outputs of the LFSR to a voltage signal. The cutoff frequency of the lter is kept at just a few percent of the clock
frequency used to drive the LFSR. This arrangement has
the effect of performing a time integration over many bits.
If each bit is equally likely (i.e., a 0 or 1 with equal probability) as is the case in LFSRs, the value of this integration

follows a binomial distribution that approaches Gaussian

for a large number of bits. This creates a Gaussian pseudorandom noise source whose statistical properties are analogous to thermal or shot noise. A variable amplier with
gains low enough to avoid any coupling is used at the output.
Analog Conversion by a Resistive Network. DAlvano and
Badra (24) use a resistive network to convert the digital signal to an analog signal, as shown in the lower block of Fig.
6. The shift register outputs are linearly combined through
the resistive network which also plays the role of the coefcient set of a discrete-time FIR lter. These weights provide
a low-pass transfer function with a raised-cosine impulse
response. The output level at the lter is adjusted through
a 1 k trimmer.
The probability density function of the noise signal at
the output can be predicted because of the random nature of the binary sequence generated at each of the shiftregister outputs. The random binary variables added to
form the noise signal are statistically independent from
one another. From the central limit theorem (4), it follows
that the probability density function of the signal at the
output is asymptotically Gaussian.
To illustrate noise generation, we have performed a simulation using commercial software produced by MicroSim
Corporation, USA. Figure 8 shows a trace of analog noise
observed at the output of the op-amp (see Fig. 6). What
is shown in Fig. 8 is repetitive noise. The periodicity in
the noise is an undesirable feature, yet inevitable when
small-size LFSRs are used for pseudorandom number sequence generation. The periodicity can be broken by randomly changing the seed of the LFSR. The periodicity can
also be improved by lengthening the shift register. Interested readers may refer to (24) for details of the circuit
which produces truly random noise.
High-Frequency Noise Generation. A shift-register-based
noise generator can be realized for RF noise power metrology (25). Superconducting rapid, single-ux, quantum
(RSFQ) logic (26) is used to meet the requirements of low
noise and fast switching necessary to generate noise in the
gigaHertz range. In the RSFQ logic, the binary information is coded by ux quanta with the value 0 = h/2e in superconducting interferometers and is transmitted and processed as very short voltage pulses V(t) of quantized area.
The active circuit components are overdamped Josephson
junctions (JJ) which need only dc bias currents set to values slightly below their critical currents. With these elements, SFQ pulses can be created, transmitted, reproduced, amplied, processed, and detected (25). The basic
RSFQ logic elements for constructing complex digital circuits are available in current technology. Superconducting
microstrip lines together with JJ technology allow transmitting picosecond waveforms with very low attenuation
and dispersion. In a pseudorandom noise generator of this

Applications of Noise

Figure 6. A six-stage linear feedback shift register with a resistive network for digital-to-analog
conversion.

type, the logic enables the generation of pseudostatistical SFQ pulse sequences, operating as quasi-shot noise
sources.
Arrays of Noise Generators. It is often necessary to have
an array of noise generators, especially in neural networks
(25). Although such noise generators can be designed with
LFSRs, one should be careful to avoid any correlation
among the outputs of these noise generators. Alspector et
al. (23) accomplish this by tapping the outputs from various
stages of the LFSR and processing them using exclusiveor gates and low-pass lters. A cellular automaton is used
by Dupret et al. (27) to generate arrays of Gaussian white
noise sources. Cellular automata feature regular structure
leading to compact VLSI layouts.
APPLICATION OF NOISE GENERATORS
Noise generators are used in a variety of testing, calibration, and alignment applications especially with radio receivers. Some of the other applications are in digital communication, analog integrated circuit diagnosis, and learn-

ing processes of stochastic neural networks. In digital communication, noise is added as an uncertainty to a cryptographic exchange to confuse the information and to prevent
unauthorized use or forgery. This is increasingly important
in todays electronic-commerce society. Random signals are
also used for dithering in analog electronic circuits, forcing
a signal to use the entire dynamic range of an analog system, one which reduces distortion. These applications can
be classied into four categories: noise used as a broadband random signal, measurements in which noise is used
as a test signal, measurements in which noise is used as a
probe into microscopic phenomena, and noise as a conceptual tool. This categorization of applications was rst made
by Gupta (28) and is used here. We include some examples
and illustrations.
Noise as a Broadband Random Signal
This kind of signal is widely used in electronic countermeasures, microwave heating, simulation of random quantities, stochastic computing, and generation of random numbers. Noise generators are used to simulate random vibrations in mechanical systems. The combination of a random

Applications of Noise

Figure 7. The waveform of the digital sequence at the output of LFSR.

noise generator and a shake table is widely used to test the

response of mechanical structures to random vibrations.
A well-known application of a high-power broadband
noise generator is active jamming of radar and communication equipment. Radar jamming is called active if the
jammer radiates a signal at the operating frequency of
the radar system, as distinguished from passive jamming
which employs nonradiating devices like chaff. The broadband jamming signal can be generated either by a noise
generator centered at the carrier frequency or by noise
modulating a continuous wave signal.
An interesting medical application is inducing sleep or
anesthesia and suppressing dental pain in a technique
called audio-analgesia. A dental patient listens to relaxing
music via earphones, and switches to ltered random noise
on feeling pain, increasing the intensity of noise as necessary to suppress pain. It is reported that audio-analgesia
has about the same level of effectiveness as morphine (29).
In modern musical instruments, white or color noise
generators are successfully used to generate the sound effect of desert wind, ocean surf, thunderstorm, lightning,
and even the virtual cosmic background sound.

Noise as a Test Signal in Measurements

There are several cases of measurements where one needs
a broadband signal with known properties like amplitude
probability density and an autocorrelation function. Random noise is one such source and is ideal for measuring impulse response, insertion loss, linearity and intermodulation of communication equipment, and in noise-modulated
distance-measuring radar.
It is well known (4) that if a random signal X(t) with
autocorrelation function RX () is applied at the input of
a linear system with an impulse response H(t), the crosscorrelation between the input and the resulting output Y(t)
is given by the convolution integral

This relationship can be used to calculate the impulse response H(t) if RX and RXY are known. For causal, lumped,
linear, time-invariant systems, this calculation can be carried out algebraically. However, solving the integral equation for H(t) is greatly simplied by using white noise as
the input signal. If the bandwidth of the input signal is

Applications of Noise

Figure 8. A simulation trace of an

analog noise signal.

much larger than that of the system under test, RX () is

effectively the impulse function (), and the equation simplies to

Thus the impulse response is directly measured without

involved calculation.
Spina and Upadhyaya (30) use the previous observation
on impulse response measurement in testing and diagnosing analog VLSI. Here, a white noise generator is used as
input stimuli to the analog chip. At the output of the circuit
under test, a pattern classier which is usually an articial neural network does the signature analysis and hence
fault diagnosis. Alspector et al. (23) study application of
noise as input to facilitate learning in parallel stochastic
neural networks.
Noise is used in measuring linearity and intermodulation in a communication channel as follows. When a large
number of telephone channels are to be carried by a coaxial cable or a broadband radio link, any existing nonlinear
distortions in the system introduce unwanted intermodulation products of the various components of the multiplexed signal. Calculation of the intermodulation noise so
introduced is very difcult because of the large number of
channels. Because statistical properties of white noise are
similar to those of a complex multichannel signal with a
large number of intermittently active channels, white noise
is used to simulate such a signal. A band-limited Gaussian
white noise is introduced at the input into the system under test. The noise power in a test channel is measured
rst with all channels loaded with white noise and then
with all but the test channel loaded with white noise. The
ratio of the rst to the second measurement is called the

noise power ratio from which the channel noise due to intermodulation can be calculated. The spectral density of
input noise can be shaped to match the signal under actual operating conditions.
The use of noise generators for checking system performance in manufacturing or in the laboratory is commonly known. The procedure can be extended to in-service
monitoring of radar and communication equipment in the
eld because of the development of solid-state noise generators which have smaller power consumption, weight, volume, radio-frequency interference, turn-on time, and turnoff time, but higher noise power output and reliability than
gas-discharge noise generators. As a result, the need for retuning or servicing the equipment is recognized before its
performance becomes unacceptable. As the noise signal is
very small and unrelated to all other signals, the monitoring can be carried out while the equipment is in operation,
thus reducing the downtime due to checkups.
Noise is specically used in the noise immunity test
of several digital systems and TV pictures (31). High frequency noise generators are needed in RF noise-power
calibration. The shift-register-based noise generator using
RSFQ logic can function at frequencies up to 45 GHz (25)
and can be used for this purpose. Digital, pseudorandom
numbers are also used to test a random collection of input
possibilities with test circuits built on-chip.
Noise as a Probe into Microscopic Phenomena
Noise measurements can be used for estimating physical parameters related to microscopic phenomena, such as
emission, recombination, or ionizing collision. Noise can
also be used in testing semiconductors for uniformity and
for estimating the reliability of semiconductor devices. Us-

Applications of Noise
Table 1. Commercial noise generators and their characteristics
Designation
TSC-300
DNG 7500
K4301
ANG
CNG-70/140
AM700
3024
SMT02
SMT03, 06
IE-20B
PNG-2000
DS345
DS360
NG-1
PNG-7000
UFX7000

Function
White Noise
Generator
Digital Noise
Generator
Pink Noise
Generator
Automated Noise
Generator
Carrier to Noise
Generator
Mixed Signal Audio
Measurement Set
Very Random noise
Generator
Signal Generator

Name of Manufacturer
Marpac

Pink and White

Ivie Technologies,
Inc.
Research
Electronics, Intl.
Stanford Research
Systems
Stanford Research
Systems
Audio Technologies,
Inc.
Noise/Com

Portable Noise
Generator
Waveform Generator
Low Distortion
Function Generator
Audible Noise
Generator
Precision Noise
Generator
Programmable Noise
Generator

QualityKits

Noise Type and Range

Sound Generator
White noise
White
Gaussian noise
Pink Noise

Micronetics

Truly Gaussian

dBm

White Noise
(50-180 MHz)
Shaped Noise
White & Pink
White & Pink
(1.6 Hz to 39 kHz)
500 kHz bandwidth

Noise/Com

Tektronix
ACO Pacic, Inc.
Rohde & Schwarz

Noise/Com

ing noise in device reliability prediction has several advantages over conventional lifetime tests. Noise testing is
nondestructive and does not take up a considerable fraction of the life of the device being tested. It also allows
testing a specic individual device rather than measuring
an average lifetime for a lot.
There are many ways in which measuring the noise in
a device can be used to make reliability predictions. For
instance, transistors with low 1/f noise exhibit longer life
spans, and reverse-biased pn junction diodes having a
noise power spectral density with multiple peaks undergo
rapid degradation. It has been found experimentally that
the low-frequency 1/f noise output of a transistor increases
by two or three orders of magnitude shortly before failure
(28).

Noise as a Conceptual Tool

Noise is the motivating cause for developing new disciplines like information theory, the statistical theory of communication, and circuit theory. It is also useful as a vehicle
for theoretical investigations and for modeling other physical systems. For example, the concepts and principles developed with electrical noise have been used as guides in
working with thermodynamics. Noise has been used as a
tool for interpreting impedance in circuit theory. It has also
led to the development of some analogies between quantum
mechanics and the analyses of noisy circuits and systems
and has helped simplify the concept of the quantum me-

1.

Technique Used
Electronic
Digital
Pseudorandom
(Digital noise)
Analog
Not available
Analog
Digital
(pseudorandom)
Not Available

Pink & White

Digital

Audio frequency
(300 Hz to 3 kHz)
White Noise
Wideband (10 MHz)
White and Pink

Not Available

White & Pink

Not Available

Gaussian White Noise

Not Available

Broadband Noise
(10 Hz to 40 GHz)

Digital
Digital

Microprogram controlled

chanical uncertainty principle. For further details, readers

may refer to (28).

COMMERCIAL NOISE GENERATORS

A number of companies sell noise generators either as separate instruments or as part of an apparatus, such as a
function generator. Table 1 lists the model numbers and the
names of the manufacturers along with various features
of the instruments including noise range, the technique
used in the design, and application areas where known.
Some of the instruments are portable and battery-powered,
whereas others are somewhat bulky. This list is not exhaustive and is provided only as a quick reference. The address
of each company is provided in Table 2 as a ready reference.
Although the internal circuitry of these noise generators is
not available, the reader may refer to other guidebooks on
electronics circuits, such as (32) which contains the circuit
diagram of digital white noise generators, thermal noise
generators using incandescent lamp, and a simple diode
noise generator.

ACKNOWLEDGMENTS
The author acknowledges Yi-Hao Wang, Shu Xia, and Arshad Nissar for their help in the simulation effort.

Applications of Noise

Table 2. Companies that make noise generators

Marpac Corporation
P.O. Box 560
Rocky Point, NC 28457 USA
QKits Limited
49 McMichael St.
Kingston, ON K7M 1M8, Canada
Micronetics
26 Hampshire Drive
Hudson, NH 03051 USA
dBm
6 Highpoint Drive
Wayne, New Jersey 07470 USA
Tektronix, Inc.
1500 North Greenville Avenue
Richardson, TX 75081 USA
ACO Pacic, Inc.
2604 Read Avenue
Belmont, CA 94002, USA
Rohde & Schwarz
Muhldorfstrasse 15
81671 Munchen (Munich), Germany
Ivie Technologies, Inc.
1605 N West State St.
Lehi, UT 84043-1084 U.S.A.
Research Electronics International
455 Security Place
Algood, TN 38506, USA
Stanford Research Systems
1290-D Reamwood Avenue
Sunnyvale, California 94089, USA
ATI - Audio Technologies, Incorporated
154 Cooper Rd. # 902
West Berlin, NJ 08091 USA
Noise Com
25 Eastmans Road
Parsippany, New Jersey 07054-3702 USA
Tundra Semiconductor Corporation
603 March Road
Kanata, Ontario, K2K 2M5, Canada

BIBLIOGRAPHY
C. Looney Noise, in R. Dorf (ed.), The Electrical Engineering
Handbook, 2nd ed., Boca Raton, FL: CRC Press, 1997, pp.
16421653.
2. J. Johnson Thermal agitation of electricity in conductors, Nature, 119: 5051, 1927.
3. M. Buckingham Noise in Electronic Devices and Systems, New
York: Wiley, 1983.
4. A. Papoulis Probability, Random Variables, and Stochastic
Processes, 3rd ed., New York: McGraw-Hill, 1991.

5. J. Dunn White-noise generator, Electron. Design, 44: 90, 1996.

6. B. Schneier Applied Cryptography, New York: Wiley, 1994.
7. W. Jung Simple wideband noise generator, Electron. Design,
44: 102, 1996.
8. L. Letham et al. A 128K EPROM using encryption of pseudorandom numbers to enable read access, IEEE J. Solid State
Circuits, 21: 881889, 1986.
9. C. S. Petrie J. A. Connelly A noise-based random bit generator
IC for applications in cryptography, Proc. Int. Symp. Circuits
Systems, 197201, June 1998.

10

Applications of Noise

10. R. May Simple mathematical models with very complicated

dynamics, Nature, 261: 459467, 1976.
11. G. McGonigal M. Elmasry Generation of noise by electronic
iteration of the logistic map, IEEE Trans. Circuits Syst., CAS34: 981983, 1987.
12. R. Bates A. Murch Deterministic-chaotic variably-colored
noise, Electron. Lett., 23 (19): 995996, 1987.
13. R. Devaney An Introduction to Chaotic Dynamical Systems,
Menlo Park: Benjamin/Cummings, 1986.
14. M. DelgadoRestituto et al. A chaotic switched-capacitor circuit for 1/f noise generation, IEEE Trans. Circuits Syst. I, 39:
325328, 1992.
15. K. Murao et al. 1/f noise generator using logarithmic and
antilogarithmic ampliers, IEEE Trans. Circuits Syst. I, 39:
851853, 1992.
16. G. Corsini R. Saletti A 1/f power spectrum noise sequence
generator, J. Solid State Circuits, 37: 615619, 1988.
17. M. Delgado-Restituto et al. Nonlinear switched-current
CMOS IC for random signal generation, Electronics Lett., 29:
21902191, 1993.
18. J. T. Bean P. J. Langlois A current-mode analog circuit for tent
maps using piece-wise linear functions, Proc. Int. Symp. Circuits Syst., 125128, 1994.
19. F. Vitaljic Programmable noise generator, Electron. Design, 44:
122, 1996.
20. H. Sutcliffe K. Knott Standard LF noise sources using digital
techniques and their application to the measurement of noise
spectra, Radio Electron. Eng., 40: 132136, 1970.
21. D. Knuth The Art of Computer Programming: Seminumerical
Algorithms, Reading, MA: Addison-Wesley, 1981, Vol. 2.
22. W. Peterson E. Weldon Error correcting codes, 2nd ed., Cambridge, MA: MIT Press, 1972.
23. J. Alspector et al. A VLSI efcient technique for generating
multiple uncorrelated noise sources and its application to
stochastic neural networks, IEEE Trans. Circuits Syst., 38:
109123, 1991.
24. F. Dalvano R. Badra A simple low-cost laboratory hardware
for noise generation, IEEE Trans. Educ., 39: 280281, 1996.
25. W. Kessel, et al. Development of a rapid single-ux quantum
shift register for applications in RF noise power metrology,
IEEE Trans. Instrum. Meas., 46: 477480, 1997.
26. K. Likharev V. Semenov RSFQ logic/memory family: A
new Josephson-junction technology for sub-terahertz-clockfrequency digital systems, IEEE Trans. Appl. Supercond., 1:
328, 1991.
27. A. Dupret E. Belhaire P. Garda Scalable array of Gaussian
white noise sources for analogue VLSI implementation, Electron. Lett., 31: (N17): 14571458, 1995.
28. M. Gupta Applications of electrical noise, Proc. IEEE, 63:
9961010, 1975.
29. K. Kryter The Effects of Noise on Man, New York: Academic
Press, 1970.
30. R. Spina S. Upadhyaya Linear circuit fault diagnosis using
neuromorphic analyzers, IEEE Trans. Circuits Syst. II, Analog
Digit. Signal Process., 44: pp. 188196, 1997.
31. T. Takagi Composite noise generator as a noise simulator and
its application to noise immunity test of digital systems and
TV picture, IEICE Trans. Commun., 78B (N2): 127133, 1995.
32. J. Markus Guidebook of Electronic Circuits, New York:
McGraw-Hill, 1974.

SHAMBHU J. UPADHYAYA

Department of Computer
Science & Engineering, State
University of New York at
Buffalo, Buffalo, NY, 14260

570

NONLINEAR FILTERS

NONLINEAR FILTERS
Numerous linear and nonlinear digital filters have been developed for a wide range of applications. Linear filters enjoy
the benefits of having a well-established and rich theoretical
framework. Furthermore, real-time implementation of linear
filters is relatively easy since they employ only standard operations (multiply and add) and can also be implemented using
fast Fourier transforms. In many cases, however, the restriction of linearity can lead to highly suboptimal results. In such
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

NONLINEAR FILTERS

cases, it may be desirable to employ a nonlinear filter (1,2).

Furthermore, as digital signal processing hardware becomes
ever more sophisticated and capable, complex nonlinear operations can be realized in real time. For these reasons, the field
of nonlinear filters has grown and continues to grow rapidly.
While many applications benefit from the use of nonlinear
methods, there exist broad classes of problems that are fundamentally suited to nonlinear methods and which have motivated the development of many nonlinear algorithms. Included in these classes of problems are the following:
1. Suppression of Heavy-Tailed Noise Processes. Simplifying approximations and the Central Limit Theorem
often lead to the assumption that corrupting noise processes are Gaussian. However, many noise processes
are decidedly heavy-tailed, or impulsive, in nature (i.e.,
have probability density functions with relatively high
valued tails). Linear filters often do a poor job suppressing such noise, necessitating the use of robust nonlinear methods.
2. Processing of Nonstationary Signals. Linear filters tend
to be sensitive to nonstationarities (changes in local signal statistics), which are common in images and biomedical signals, for example. In images and video sequences, nonstationarities in the form of edges and
scene changes are abundant. Linear processing of such
data for restoration or enhancement may produce
blurred edges and/or ringing artifacts, which can seriously degrade visually important features.
3. Super-resolution Frequency Extension. Frequency analysis shows that linear methods can be designed to either amplify or attenuate signal power at selected frequencies. However, linear filters are incapable of
restoring frequency content to a signal from which it
has been completely eliminated. Such frequency content
extension requires nonlinear methods and is important
in applications such as the restoration of high-resolution broad-band images from low-resolution narrowband realizations.
4. Modeling and Inversion of Nonlinear Physical Systems.
Signals are generally acquired through physical systems (such as transducers or optics) that are inherently
nonlinear. Both the accurate modeling of such systems
and the inversion of their effects on acquired signals
necessitate the use of nonlinear methods.
Here we describe a variety of nonlinear filters and identify
some current areas of research on nonlinear methods. An extensive treatment of nonlinear filters can be found in the
books by Astola and Kuosmanen (1) and by Pitas and Venetsanopoulos (2). The fact that nonlinear methods lack a unifying framework makes presenting a general overview difficult.
However, we organize the presented filters into two general
methodologies:

571

ming operations. We refer to all filters that form an estimate through linear combinations in this way as
weighted sum filters.
2. Selection Filters. Combining samples to form an estimate, especially in a weighted sum fashion, can lead to
cases where corrupted samples have a disproportionate
influence on the estimate. Moreover, the output of a
weighted sum estimate is generally an intermediary
sample that is not equal to any of the observed samples,
which is undesirable in some applications. These issues
are addressed by a broad class of nonlinear filters (referred to as selection filters) that restrict their output
to be one of input samples.
Weighted sum filters combine the benefits of linear filters
with some strategically designed nonlinearity to provide the
desired result. Selection filters tend to offer robustness from
outliers, provided that a proper selection rule is implemented.
That is, as long as an outlier is not selected to be the output,
the outlier is effectively removed and generally has little impact on the filter output. Furthermore, selection filters generally do not blur edges in signals since the output is forced to
be one of the input samples and no intermediate transition
samples are created by the filter. In the following analysis,
we show that many useful nonlinear filters can be placed into
these two broad categories. Signal and image processing examples are included at the end of this article to illustrate the
performance of selected filtering methods. Also, numerous references are provided to allow the reader to pursue the study
of the filters described in greater detail.
The organization of the remainder of this article is as follows. In the section entitled The Filtering Problem, the filtering problem is described and much of the notation is defined. The general class of nonlinear weighted sum filters is
described in the section entitled Nonlinear Weighted Sum
Filters. The family of selection filters is described in the section entitled Selection Filters. Illustrative filtering examples are provided in the section entitled Filtering Examples,
where selected filters are applied to the restoration of an image embedded in Gaussian noise, to the restoration of an image contaminated by impulsive noise, and, finally, to edge enhancement. Some conclusions are provided in the section
entitled Conclusions.
THE FILTERING PROBLEM
The goal in many filtering applications is to transform an observed signal into an approximation of a desired signal, where
the transformation is designed to optimize some fidelity criterion. This scenario is illustrated in Fig. 1, where x(n) and
y(n) represent the observation (input) and approximation
(output) sequences, respectively. In this representation,

{ d(n)}

1. Weighted Sum Filters. The output of a linear filter is

formed as a linear combination, or weighted sum, of observed samples. Nonlinearities can be introduced into
this general filtering methodology by transforming the
observation samples, through reordering or nonlinear
warping for instance, prior to the weighting and sum-

{ y(n)}

{ x(n)}
Filter

{ e(n)}

Figure 1. The filtering problem where an observed signal is transformed by the filtering operation to approximate a desired signal.

474

OVERVOLTAGE PROTECTION

OVERVOLTAGE PROTECTION
Most semiconductor devices are intolerant of overvoltage
transients in excess of their voltage ratings. Even a microsecond overvoltage transient can cause a semiconductor to fail
catastrophically or may result in severe stress, reducing the
useful life of the equipment. Overvoltage transients in electrical circuits result from the sudden release of previously stored
energy. Some transients may be created in the circuits by inductive switching, commutation voltage spikes, and so on.
Other transients may be created outside the circuit and then
coupled into it. These can be caused by lightning, capacitorbank switching at the substation, or similar phenomena. This
article discusses overvoltage protection in terms of the following three categories:
1. Overvoltage transients
2. Overvoltage protection devices
3. Overvoltage protection for switch-mode power supplies
OVERVOLTAGE TRANSIENTS
Overvoltage transients in a low-voltage (600 V or less) ac
power circuit originate from two major sources: system
switching transients and direct or indirect lightning strikes
on the power system. A sudden change in the electrical condition of any circuit will cause a transient voltage due to the
stored energy in the circuit inductance or capacitance.
Switching-induced transients are a good example of this; the
rate of change of current (di/dt) in an inductor (L) will generate a voltage
V = Ldi/dt

(1)

The transient energy is equal to

E = 1/2Li2

(2)

This energy exists as a high-power impulse for a relatively

short time (J Pt). Consider an example as shown in Fig. 1.
If load 2 is shorted, load 1 and/or the diode rectifier will be
subjected to a voltage transient. As load 2 is shorted, the fuse
will open and interrupt the fault current. The power supply
will produce a voltage spike equal to Eq. (1) with an energy
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

OVERVOLTAGE PROTECTION

475

Fuse
Power
supply

A
Load
1

Short
across
Load 2

Load
2

VAB

Figure 1. Overvoltage transient due to

change of current in an inductor.

content of Eq. (2). This transient may be beyond the voltage

limitations of the diode rectifiers and/or load 1. Switching out
a high-current load will have a similar effect.
Energizing a Transformer Primary. When a transformer primary is energized at the peak of the supply voltage, the coupling of this voltage step function to the stray capacitance and
inductance of the secondary winding can generate a transient
voltage with a peak amplitude up to twice the normal secondary voltage. Figure 2 shows a circuit in which the secondary
side is a part of the capacitive divider network in series with
the transformer interwinding capacitance (CS). This stray capacitance has no relation to the turns ratio of the transformer, and it is possible that the secondary circuit may see
a substantial fraction of the applied primary peak voltage.
Deenergizing a Transformer Primary. The opening of the primary circuits of a transformer generates extreme voltage
transients in excess of ten times the normal voltage. Interrupting the transformer magnetizing current, and the re-

sulting collapse of the magnetic flux in the core, couples a

high-voltage transient into the transformers secondary winding, as shown in Fig. 3. Unless a voltage-limiting device is
provided, this high-voltage transient appears across the load.
Switch Arching. When the current in an inductive circuit,
such as a relay coil or a filter reactor, is interrupted by a
contactor, the inductance tries to maintain the current by
charging the stray capacitance. Similar behavior can occur
during closing if the contacts bounce open after the initial
closing, as shown in Fig. 4. During the opening and closing of
the electromechanical switches, the bouncing action of contacts can result in high-frequency overvoltage transients.

Closing
switch
+

CS

Closing
switch

VP

VS
IM
L

VP

VS
C

L
CS

Line
voltage
Vp

Load

;;;;
;; ;;
;
;
;
Load

Line
voltage
Vp

Magnetizing
current iM
and flux

Switch
closed

Secondary
voltage Vs

Vs-PK

Figure 2. Voltage transient caused by energizing transformer

primary.

Secondary
voltage
Vs

Switch
opened
Voltage
transient

Figure 3. Voltage transient caused by interruption of transformer

magnetizing current.

476

OVERVOLTAGE PROTECTION
VCAP

VLINE
Solid-state
equipment

VSUPPLY

Figure 4. Voltage transients caused by switch arcing.

Random Transients
Overvoltage transients create the most confusion because it
is difficult to define their amplitude, duration, and energy
content. In general terms, the anticipated surge voltage level
depends on the location of the equipment to be protected.
When it is inside a building, the stress depends on the distance from the electrical service entrance to the equipment,
the size and length of the connection wires, and the complexity of the branch circuits. IEEE Std. 587-1980 proposes three
location categories for low-voltage ac power circuits that are
representative of a majority of locations from the electrical
service entrance to the most remote wall outlet. These categories are shown in Fig. 5 and described as follows:
1. Category A: Outlets and Long Branch Circuits. This is
the lowest-stress category in which outlets and branch
circuits are long distance from electrical service entrance. This category includes all outlets more than 10
m (30 ft) from category B with #14 to #10 AWG wires.
It also includes all outlets more than 20 m (60 ft) from
service entrance with #14 to #10 wires. In category A,
the stress voltage may be of the order of 6 kV, but the

(a)

(b)

(c)

stress current is relatively low, of the order of 200 A

maximum.
2. Category B: Major Feeders and Short Branch Circuits.
This category covers the highest-stress conditions likely
to be subjected to an equipment power supply. It applies
to distribution panel boards, bus and feeder systems in
industrial plants, heavy appliance outlets with short
connections to the service entrance, and lightning systems in commercial office buildings. Note that category
B locations are closer to the service entrance, so stress
voltage of the order of 6 kV and stress current level of
up to 3000 A may be expected.
3. Category C: Electrical Service Entrance and Outdoor Locations. This location is defined as the power line between pole and electrical service entrance of a building.
Very high stress conditions can occur. Since most of the
sensitive electronic equipment will be in category A and
B, within a partially protected environment inside the
building, only protection to categories A and B is normally required.
Rate of Occurrences
The rate of occurrence of voltage transients varies over a wide
range, depending on a particular power system, although lowlevel surges are more prevalent than high-level transients.
Prediction of the rate of occurrence for a particular system is
always difficult and frequently impossible. Data collected
from various sources are the basis of the curves shown in
Fig. 6.
1. Low Exposure. These are systems with little loadswitching activity, which are located in geographical
areas of light lightning activity.
2. Medium Exposure. Medium-exposure systems are in
areas of frequent lightning activity and severe switching transients problems.
3. High Exposure. These are rare but real systems supplied by overhead lines and subject to reflections at line

Figure 5. Location categories. (a) Outlets and Long Branch Circuits:

All outlets at more than 10 m (30 ft) from Category B with wires #14
to #10; All outlets at more than 20 m (60 ft) from Category C with
wires #14 to #10. (b) Major Feeders and Short Branch Circuits: Distribution panel devices; Bus and feeder systems in industrial plants;
Heavy appliance outlets with short connections to the service entrance; Lighting systems in commercial. (c) Outside and Service Entrance: Service drop from pole to building entrance; Run between meter and distribution panel; Overhead line to detached buildings;
Underground lines to well pumps.

Surge per year in excess

of crest kV of abscissa

103

10

High
exposure

Medium
exposure
101

1
Sparkover of
clearances
(note)

101
Low
exposure
102
0.3

0.35

2
5
Surge crest (kV)

10

20

Figure 6. Rate of surge occurrence versus voltage level at unprotected locations. Note: In some locations, sparkover of clearances may
limit the overvoltages.

OVERVOLTAGE PROTECTION

477

Table 1. Surge Voltages and Current Deemed to Represent the Indoor Environment and Suggested for Consideration in
Designing Protective Systems
Energy (Joules) Deposited
in a Suppressor c
with Clamping Voltage of

Impulse
Comparable
to IEC 664
Category

Location Category
A. Long branch circuits and
outlets
B. Major feeders short branch
circuits, and load center

Waveform

II

0.5 ms100 kHz

III

1.2/50 s
8/20 s
0.5 ms100 kHz

MediumExposure
Amplitude
6
200
6
3
6
500

Type of Specimen
on Load Circuit

500 V
(120 V System)

1000 V
(240 V System)

0.8

40

1.6

80

High impedance a
Low impedance b
High impedance a
Low impedance b
Low impedance a
High impedance b

kV
A
kV
kA
kV
A

a
For high-impedance test specimens or load circuits, the voltage shown represents the surge voltage. In making simulation tests, use that value for the opencircuit voltage of the test generator.
b
For low-impedance test specimens or load circuits, the current shown represents the discharge current of the surge (not the short-circuit current of the power
system). In making simulation tests, use that current for the short-circuit current of the test generator.
c
Other suppressors which have different damping voltages would receive different energy levels.

ends, where the characteristics of the installation produce high sparkover levels of the clearances.
These data were taken from unprotected (no limiting voltage devices) circuits, meaning that the transient voltage is
limited only by the sparkover distance of the wires in the distribution system.
Overvoltage Transient Waveforms
The definition of a transient waveform is critical for the design of overvoltage protection circuitry. An unrealistic voltage
waveform with long duration of the voltage or very low source
impedance requires a high-energy protection device, resulting
a cost penalty to the end-user. IEEE Std. 587 defines two overvoltage current waveforms to represent the indoor environment recommended for use in designing protection devices.
Table 1 describes the waveforms, open circuit voltage, source
impedance, and energy stored in the protection circuitry.

sentative of category I indoor low-voltage (ac lines less

than 600 V) system transients. This 100 kHz ring wave
has a rise time of 0.5 s (from 10% to 90% of its final
amplitude), with oscillatory decay at 100 kHz, each
peak being 60% of the previous one. The rapid rate of
rise of the waveform can cause dv/dt problems in the
semiconductors. The oscillating portion of the waveform
produces voltage polarity reversal effects. Some semiconductors are sensitive to polarity changes or can be
damaged when unintentionally turned on or off.

0.5 VPEAK

0.3 VPEAK

1. Category I. The waveform shown in Fig. 7 is defined as

0.5 s100 kHz ring wave. This waveform is repre-

0.9 VPEAK

VPEAK

0.9 VPEAK

T1

50 s
T1 1.67 = 1.2 s

VPEAK

T = 10 s (F = 100 kHz)

IPEAK

0.9 IPEAK

0.5 IPEAK

0.1 VPEAK
0.5 s

0.1 IPEAK
T2

60% of VPEAK

Figure 7. 0.5 s to 100 kHz ring wave (open-circuit voltage).

20 s

T2 1.25 = 8 s

Figure 8. Unidirectional waveshapes.

478

OVERVOLTAGE PROTECTION

2. Category II. In this category, close to the service entrance, much larger energy levels are encountered. Both
oscillatory and unidirectional transients have been recorded in this outdoor environment. IEEE Std. 587 recommends two unidirectional waveforms and an oscillatory waveform for category II. These two waveforms are
shown in Fig. 8. The various stress conditions are computed in Table 1.

ZS

ZV

VOC

VZV = (

ZV
ZV + ZS

( VOC

Figure 9. Voltage-clamping device.

OVERVOLTAGE PROTECTION DEVICES

There are two major categories of transient suppressors: (1)
those that attenuate transients, thus preventing their propa-

Table 2. Characteristics and Features of Transient Voltage Suppressor Technology

VI Characteristics

Device Type

Leakage

Follow
on I

Clamping
Voltage

Energy
Capability

Capacitance

Response
Time

Cost

Ideal device

Zero to
low

No

Low

High

Low or high

Fast

Low

Zinc oxide varistor

Low

No

Moderate to
low

High

Moderate to
high

Fast

Low

Zener

Low

No

Low

Low

Low

Fast

High

Crowbar (Zener
SCR combination)

Low

Yes
(latching
holding I )

Low

Medium

Low

Fast

Moderate

Spark gap

Zero

Yes

High ignition
voltage
Low clamp

High

Low

Slow

Low to
high

Triggered spark gap

Zero

Yes

Lower ignition
voltage
Low clamp

High

Low

Moderate

High

Selenium

Very
high

No

Moderate to
high

Moderate
to high

High

Fast

High

Silicon carbide
varistor

High

No

High

High

High

Fast

Relative
low

Clamping voltage
Working voltage
I

Transient current

V
Working
voltage
I

V
Max I limit
Working
voltage
I

Peak voltage
(ignition)
Working
voltage
I

Peak voltage
(ignition)
Working
voltage
I

Peak voltage
(ignition)
Working
voltage
I

V
Working
voltage
I

V
Working
voltage
I

OVERVOLTAGE PROTECTION
Line

device as the voltage tends to rise. The apparent clamping

of the voltage results from the increased voltage drop in the
source impedance due to the increased current. It must be
clearly understood that the device depends on the source impedance to produce clamping. One is seeing a voltage divider
action at work, where the ratio of the division is nonlinear
(Fig. 9). The voltage-clamping device cannot be effective with
zero source impedance. Table 2 lists various types of voltageclamping devices and their features and characteristics.

Fuse
+

Ac
input

R
Switch mode
power supply

Rectifier

IC

479

Load
SCR

Figure 10. SCR crowbar overvoltage protection circuit for switching

power supplier.

Crowbar Devices. Crowbar-type devices involve a switching action, either the breakdown of a gas between electrodes
or turn-on of a thyristor. After switching on, the crow-bar device offer a very low impedance path which diverts the transient away from the parallel-connected load. These crowbar
devices have two limitations. The first is their delay time, typically microseconds, which leaves the load unprotected during
initial voltage rise. The second limitation is that a power current from the steady-state voltage source will follow the transient discharge current (called follow current or powerfollow).

gation into the sensitive circuit; and (2) those that divert
transients away from sensitive loads and so limit residual
voltages. Attenuating a transient, that is, keeping it from
propagating away from the source or keeping it from impinging on a sensitive load, is accomplished with series filters
within a circuit. The filter, generally of low-pass type, attenuates the transients (high-frequency) and allows the signal or
power flow (low-frequency) to continue undisturbed. Diverting
a transient can be accomplished with a voltage-clamping device or with a crowbar type device.

OVERVOLTAGE PROTECTION FOR SWITCH-MODE

POWER SUPPLIES

Filters. The frequency of a transient is several orders of

magnitude above the power frequency (50/60 Hz) of an ac circuit. Therefore, an obvious solution is to install a low-pass
filter between the source of transients and the sensitive load.
The simplest form of filter is a capacitor placed across the
line. The impedance of the capacitor forms a voltage divider
with the source impedance, resulting in attenuation of the
transients at high frequencies. This simple approach may
have undesirable effects, such as (1) unwanted resonance
with inductive components located in the circuit resulting in
high-peak voltages; (2) high capacitor in-rush current during
switching, and (3) excessive reactive load on the power system
voltage. These undesirable effects can be minimized by adding a series resistor (RC snubber circuit).

During fault conditions, most power supplies have the potential to deliver higher output voltages than those normally
specified or required. If unprotected, the higher output voltage can cause internal and external equipment damage. To
protect the equipment under these abnormal conditions, it is
common practice to provide some means of overvoltage protection within the power supply. Overvoltage protection techniques for switch-mode power supplies fall broadly into
three categories:
1. Simple SCR crowbar overvoltage protection
2. Overvoltage protection by voltage-clamping techniques
3. Overvoltage protection by voltage-limiting techniques

Voltage-Clamping Devices. A voltage-clamping device is a

component having variable impedance depending on the current flowing through the device or on the voltage across its
terminal. These devices exhibit nonlinear impedance characteristics. Under steady-state, the circuit is unaffected by the
presence of the voltage-clamping device. The voltage-clamping action results from increased current drawn through the

SCR Crowbar Overvoltage Protection

Figure 10 shows the principle of a SCR (silicon-controlled rectifier) crowbar overvoltage protection circuit connected to
the output of a switch-mode power supply. If the output voltage increases under a fault condition, the SCR is turned on
and a short-circuit is imposed at the output terminals via the

Voltage (VH )
Q1
FS1
(fuse)
Ac
input

Q2

A1
+

R5
Load

C0
RIF, V

Transformer
rectifier
and shooting
circuit

ZD1

R1

Series regulator
circuit

R2

R3

R4
C1

Simple crowbar
circuit

SCR

Figure 11. A simple SCR crowbar circuit

for linear regulators.

480

OVERVOLTAGE PROTECTION

+Output

Zener diode
voltage clamp

Dc
supply

Figure 12. Shunt regulator type voltage

clamp circuits.

+Output

Shunt regulator
voltage clamp

Dc
supply

(a)

resistor R, and the overvoltage condition is prevented. With

linear regulator-type dc power supplies, SCR crowbar overvoltage protection is the normal protection method, and the simple circuit shown in Fig. 11 is often used. The linear regulator
and crowbar operate as follows:
The dc output voltage, VH, is regulated by a series transistor, Q1, to provide a lower but regulated output voltage, Vout.
Amplifier A1 and resistors R1 and R2 provide the regulator
voltage control, and transistor Q2 and current-limiting resistor R1 provide the current-limiting protection. The worst case
overvoltage condition would be a short-circuit of the seriesregulating device Q1 so that the higher unregulated voltage,
VH, is now presented to the output terminals. Under such
fault conditions, both voltage control and current limiting actions are lost, and the crowbar SCR must be activated to
short-circuit the output terminals.
In response to such a fault condition, the overvoltage protection circuitry in Fig. 11 responds as follows: As the voltage
across the output terminals rises above the voltage-limiting
threshold of the circuit, or zener diode ZD1 conducts the driving current via R4 into SCR gate C1. After a short delay defined by the values of C1, R4, and the applied voltage, C1
charges will reach gate firing voltage (0.6 V), and SCR will
conduct to short-circuit the output terminals via low-value
limiting resistor R5. However, a large current now flows from

Dc
input

(b)

the unregulated dc input voltage through the shunt-connected

SCR. To prevent overdissipation in the SCR, it is necessary
to use a fuse, FS1, or circuit-breaker in the unregulated dc
supply. If the series regulator device Q1 has failed, the fuse
or circuit breaker now clears to disconnect the source from
the output before the SCR is destroyed. This approach is popular for many noncritical applications. Although this circuit
has the advantage of low cost and circuit simplicity, it has
ill-defined operating voltage, which can cause large operating
spreads. Design modifications can be incorporated to overcome these limitations.
Overvoltage Clamping Technique
In low-power applications, overvoltage protection may be provided by a simple clamp action. In many cases, a shunt-connected zener diode is sufficient to provide the required overvoltage protection [see Fig. 12(a)]. If higher current capability
is required, a more powerful transistor shunt regulator may
be used [Fig. 12(b)]. It should be noted that when a voltage
clamp device is employed, it is highly dissipative, and the
source resistance must limit the current to acceptable levels.
Hence, shunt clamping action can be used only where the
source resistance (under failure conditions) is large. In many
cases, shunt protection of this type relies on the action of a

Converter

Opto
coupler

ZD1
Ramp
comparator

Figure 13. Typical overvoltage shutdown

protection circuit for switch mode power
supplier.

SCR2

Overvoltage
protection cct
Voltage
control cct

OVERVOLTAGE PROTECTION

separate current
performance. An
there is no delay
does not require
dition.

or power-limiting circuit for its protective

advantage of the clamp technique is that
in the voltage clamp action, and the circuit
resetting upon removal of the voltage con-

481

plications, where independent secondary limits or regulators

are provided, the voltage limit circuit may act upon the current limit circuit to provide the overvoltage protection. Once
again, the criterion is that a single component failure should
not result in an overvoltage condition. Many techniques are
used solid are beyond the scope of this article.

Overvoltage Clamping with SCR Crowbar Backup

For low-power application, an SCR crowbar circuit can be
used in parallel with a zener clamp diode. In that case, the
advantage of the fast-acting voltage clamp can be combined
with the more powerful SCR crowbar. With this design, the
delay required to prevent spurious operation of the SCR will
not compromise the protection of the load, as the zener clamp
diode will provide protection during the SCR delay period.
Overvoltage Protection by Voltage-Limiting Technique
Figure 13 shows a typical example of a voltage-limiting circuit
used in switch-mode power supplies. In this circuit, a separate optocoupler is energized in the event of an overvoltage
condition. This triggers a small-signal SCR on the primary
circuit to switch off the primary converter. The main criterion
for such protection is that the protection loop is entirely independent of the main voltage control loop. This may be impossible to achieve if a single IC is employed for voltage control
and shut-off. Additional design modifications may become
necessary.
Voltage-limiting circuitry may either latch, requiring cycling of the supply input to reset, or be self-recovering, depending on application requirements. In multiple output ap-

Reading List
K. H. Billings, Switch Mode Power Supply Handbook, New York:
McGraw-Hill.
M. Brown, Practical Switching Power Supply Design, Motorola Semiconductor, Inc. Series in Solid State Electronics.
S. Cherniak, A Review of Transients and Their Means of Suppression,
Motorola Application Note AN843, Motorola Semiconductor, Inc.
A. Greenwood, Electrical Transients in Power Systems, 2nd ed., New
York: Wiley, 1991.
IEEE Recommended Practice on Surge Voltages in Low-Voltage AC
Power Circuits, IEEE C62.41-1991.
Transient Voltage Surge Suppression Devices, DB 450.4, Harris
Semiconductor, 1995.

ASIF JAKWANI
Current Technology, Inc.

P. ENJETI
Texas A & M University

OXIDE RAMP DIODES. See SCHOTTKY OXIDE RAMP

DIODES.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

PHASE-LOCKED LOOPS, APPLICATIONS

Phase-locked loops (PLLs) are used for a variety of functions, all of which may be incorporated in a generic
PLL form. The fundamentals of PLL systems are actually rather straightforward, but are typically enshrouded
in mystery. This mystery stems in part from the difficulty of identifying the basic signal components in the
loop and of understanding the unit as a feedback system with the peculiarities related to its phase-detector
properties. This article provides a foundation of principles, including those of tracking and acquisition. From
this foundation, several applications will be explored with the intent of providing an approach toward extending
the concepts and not simply being able to replicate the analysis and design discussed.
The PLL has wide application. The majority of its applications fall into the four main categories frequency
synthesis, frequency (FM) and phase (PM) modulation and demodulation, data and carrier recovery, and
tracking filters. Applications for each category will be considered.

The Generic Phase-Locked Loop

Denition. The basic PLL is rather simple in concept. However, we extend it a bit to include most
of the features of interest in a loop. The generic loop is shown in Fig. 15. Features that have been included
are frequency synthesis, frequency offset, and modulation and detection. The phase detector is shown as
a multiplier, since many classic phase detectors actually use the process of multiplication to extract phase
information about a nominal phase shift of 90 . Many of the loop effects may be absorbed into the simpler
model of Fig. 1 without any loss of generality. This basic PLL includes all the behavioral blocks needed for
analysis of loops. The components of the basic loop are a phase detector (PD), a low-pass filter (LPF), and a
voltage-controlled oscillator (VCO). In reality, the oscillator may be current-controlled and may be preceeded
by an amplifier to adjust the range of performance of the oscillator or make a filter active. It is not uncommon
to have to allow for additional delays and for low-pass filter effects at the input of the oscillator. Such delays
and filtering increase the need for adequate phase and amplitude margins of the open-loop gain compared to
unity at 180 , in order to prevent oscillation of the feedback system. The latter would cause either a highly
undesired frequency modulation of the VCO or a total loss of frequency lock in the loop.
An aspect that causes much grief for newcomers to PLL systems is the varied notation. We will use typical
notation and explain the meaning of each item as we proceed through the concepts. Many of the terms lend
themselves to approximations that offer excellent predictions of system results.
A PLL is generally analyzed as a linear, feedback-control system with a transfer function H(s) representing
the relationship between the input phase s and the VCO phase o . This transfer function is one of the most
confusing features of PLL analysis to the newcomer. In the signal sense, we have phase as a signal, not voltage
or current amplitude. Thus, the frequency response is that of a time-varying phase, not of the amplitude
variations in a typical input signal. Once this dual-frequency concept is understood, the analysis of a PLL is
1

PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 1. Basic PPL, offering the most basic structure of a PLL needed for analysis, and consisting of a VCO, phase detector,
loop filter, and possible amplifier.

rather straightforward. The transfer function just mentioned is written as

This transfer behavior is typically written in terms of the linear transfer characteristics of the controlsystem open-loop transfer function G(s). From Fig. 1 we have

where the VCO is modeled as an integrator (the VCO converts the control voltage V c into an instantaneous
frequency, which is then integrated to obtain the phase). The gain terms provide the appropriate conversion,
such as voltage to frequency for the VCO. The overall gain K is found with a variety of subscripts in the
literature, which we have chosen not to use. In the control-theory context, the phase detector acts as a difference
blockcomparing the phase of the incoming signal with that of the VCO. The units used throughout the loop
are the radian and the volt. In some cases, the ampere is appropriate for a particular device, simply requiring
a change of the appropriate terms.
The filter used in a PLL is basically a low-pass filter designed to reject harmonics and spurious frequencies
generated in the phase-detection process, a design requirement not typically found in control systems. This
cutoff of the filter should be greater than the bandwidth of the PLL. However, additional filter shaping may also
used to enhance the bandwidth and performance of the PLL. A simple laglead filter may be used to narrow
the loop bandwidth, followed by a lag (or low pass) to provide the out-of-band low-pass filtering. In discussing
filters, we will generally neglect this latter out-of-band lag filter, which should always be added to a PLL.
The use of integrators in the filter facilitates tracking of velocity and acceleration signals (velocity signals
have a constant offset frequency, while acceleration signals have a changing offset frequency over time, typical
of the Doppler shift in a low-earth-orbit satellite system). These integrators allow the steady-state phase error
to be zero for specific applications, an important feature for many phase-demodulation processes.

PHASE-LOCKED LOOPS, APPLICATIONS

Since the filters and the loop VCO response are generally monotonically decreasing in amplitude with
increasing frequency, it is obvious that H(s) may be simply approximated in two separate ranges as

where  is the bandwidth of the loop. A major problem in PLL design is ensuring that G(s) does not approach
1 near the bandwidth of the loop. If the latter occurs, then substantial ringing or possible instability of the loop
should be expected. To avoid this stability difficulty, the loop is specified with a sufficient damping factor, phase
margin, or gain margin at = . The analytical treatment of the stability must take account of possible stray
delays in the system caused by low-pass coupling of oscillator control lines and related connections needed
for circuit isolation. It is common to simply add some extra margin to allow for common stray effects, but
such actions should be taken carefully, since they may add substantial switching delays and performance
degradation in an operational system. It should be noted that the PLL bandwidth  is not the bandwidth
of a filter inserted in the loop, but rather comes from an interaction of the loop filter with the entire loop,
particularly the feedback filter effects of the VCO.
A secondary transfer function that is important for evaluating the limitations of the system is the error
transfer function relating the phase error to the input phase. This function may be written as

This error function is critical in the determination of the limits beyond which the signal may cause the
loop to lose lock, or simply to exceed the linear range of the components of the loopmost commonly the
phase detector or active filters. Additional transfer functions may be defined to describe the modulation and
demodulation processes of both FM and PM systems, as will be considered with specific applications. For
FM, the product of the modulation signal and the error transfer function tends to peak at . This peak
substantially increases the probability of the phase range of the detector being exceeded, causing a loss of lock
in the vicinity of . This peaking suggests that  would be a good frequency to be check during loop testing.
Simple Phase-Locked-Loop Analysis. The simple linear analysis of a PLL starts with Eq. (2) written
as

Thus the basic analysis and design stem from the choice of the open-loop gain K and the filter function F.
It is common to assume that F is monotonically decreasing in frequency, though this need not be the case. If
F = 1, then the transfer function is simply a low-pass filter defined by a radian bandwidth of K. In practice, an
additional filter pole is added above the loop bandwidth for rejection of spurious signals created by the phasedetector process (generally a form of multiplication) and will only increase the rejection of higher frequencies
in the loop, not having a substantial effect on the in-lock performance. If this additional filtering is not used
with multivibrator VCOs, the resultant output of the VCO will have a duty cycle related to the phase error.

PHASE-LOCKED LOOPS, APPLICATIONS

Let us consider the poor choice of a lag filter to control the bandwidth by adjusting the filter bandwidth
relative to K. In this case we would have

The new transfer function is commonly written as

where n is called the natural frequency and is the damping factor. In controls, takes on an important role
in the stability of the system. Generally speaking, should not be chosen any smaller than about 1/ . That
exact value leads to optimal coupling for the system, in the sense that smaller coupling values lead to transient
ringing, while larger values lead to longer transient times or slower responses. Actual choices of must also
allow for spurious delays in the system. The corresponding response of such a transfer function to a step change
in phase is easily obtained using Laplace transforms and is given by Blanchard (1) as

where o represents the transient phase equivalent of the output phase, o . For < 0.707, substantial oscillatory
behavior near n is created that dies out at the rate 1/ ( being the filter time constant), slower than K. For
larger , the trigonometric functions become hyperbolic and the solution becomes a double exponential in 1/
and K. This connection with the actual parameters being selected is sometimes scaled out of the problem,
leaving the designer in a bit of a quandary about how to make some of the choices. In this case, it is clear that
the decay at the rate of K is the limiting feature of the loop. If K is not adjustable, the only consideration with
a lag filter is setting for good rejection of the spurious output frequencies created by the detector outside of
the bandwidth of K.
A laglead filter offers a reasonable alternative to adjustment of the loop gain constant. The laglead
filter and response are given by

The step response for this loop is similar to the last case and is given by Blanchard as (1)

PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 2. Bode plot of a second-order filter and the associated G and H magnitudes. The laglead properties of the filter
are seen in the two breakpoints of the filter response |F|. The filter behavior produces |G| as |F/s|, resulting in a transfer
function H with response of unity within the passband and G outside the passband.

where n =
and = (1 + K2 ) / (2
). This response has a key 1 that was missing with the
simple lag filter. As 1 is increased to narrow the filter response, the zero of the filter may also be changed. In
essence, the effective gain of the loop is changed to K2 /1 , with a fundamental pole at K2 /1 and a second
pole at about 1/2 as long as the response of F changes almost entirely within the bandwidth of the loop. This
is easily seen in a Bode plot of H along with the plots of |F| and |G|, as in Fig. 2 with 1 = 0.1 s, 2 = 1 s, and
K = 500 rad/s. In this instance, the bandwidth of the loop has been reduced to 50 rad/s, from 500 rad/s with no
filter. The inclusion of an additional pole in the filter at 200 rad/s (3 = 0.005 s) helps to filter out the spurious
output frequencies of the detector without much change to the in-band response of the PLL, as shown in Fig. 3.
There is a slight increase in the bandwidth due to the proximity of the pole to the 50-rad/s bandwidth, but with
improved rejection. The values of the other filter parameters may be adjusted slightly to bring the bandwidth
back to the desired value.
This Bode-plot viewpoint has been provided to emphasize the design information that is directly available
from the Bode plot for many PLL situations. The Bode plot often provides a faster approach to the design needs
while still maintaining reasonable accuracy. Evaluating the phase margin (phase of G relative to 180 when
|G| = 1) is an alternate method for estimating the stability of the loop. With the extra pole, the margin in this
example becomes 65.8 rather than 80 . The advantage to this approach is a quick look at a design based on
the physical system rather than the scaled control system variables. In addition, once the Bode-plot approach
is adopted, the extension to higher-order systems is straightforward, not requiring information for Nyquist or
root-locus plots. The latter are useful tools, but do not substantially speed the design of a well-designed PLL.
The criteria for the Bode design is that the slope of G about the bandwidth should be approximately
20 dB/decade, similar to a simple integrator. A phase margin of 90 is desirable to minimize peaking in the
, often
passband response. A 65.6 phase margin corresponds to a damping factor of 1/
found to give the fastest settling of transient responses with no ringing. A damping factor of 1/2 creates a phase
margin of 52 with a peaking at the band edge of about 1.2 dB above the nominal passband response. This
slight peaking in the response is often a reasonable compromise for faster transient response times, though
with some damped ringing. Additional filtering may be added above the bandwidth to reject spurious detector

PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 3. Bode plot of the second-order filter with an additional rejection pole. The performance within the passband is
equivalent to the filter of Fig. 2, but with additional rejection for higher frequencies.

output. Such filtering may even include notch filters. With the additional filtering design guidelines placed
above the loop bandwidth, the transient response of the system approaches that of a simple low-pass filter with
a bandwidth set from the Bode analysis. If a designer hedges on the phase margin by bringing these higherfrequency filter poles closer to the passband, the PLL response peaks at the bandwidth limit as suggested.
Such a slight peak was seen in the response of Fig. 3 and is considered acceptable for many applications if kept
below 1 dB. A large collection of typical transient response plots is provided by Blanchard (1).

Components
Phase Detector. The critical component of a PLL is the phase detector. In control theory, it becomes
simply a difference block as previously suggested. However, the difference in phase between the two incoming
signals or frequencies is typically obtained by multiplying the two signals together and filtering the resulting
frequency-difference product. A multiplier is an ideal mixer that produces a phase detector whose output
voltage is proportional to the sine of the phase difference e . The multiplier-type phase detector is one of four
basic forms. The basic detector forms give error output voltages as

which are depicted graphically in Fig. 4. The arrows in Fig. 4(d) emphasize that the transitions at the voltage
extremes are directed back to the zero value as a one-way transition, not to the opposite extreme as with

PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 4. Phase detector characteristics: (a) sinusoidal, (b) triangular, (c) ramp, and (d) extended ramp. The arrows of (d)
are to emphasize the one-way transition to the zero output state rather than the opposite extreme of the output.

the two-way transition of the ramp detector. The one-way transition of the extended ramp is critical to the
development of a dc offset level to aid in acquisition when the loop is out of lock.
How are these results obtained? They are obtained through basic mixing processes creating a product of
the two signals in question. Consider the input frequencies to be given by

where has been used to represent the phase difference from a reference oscillator at frequency f . This
frequency f is often called the free-running frequency and is indeed just that for several of the detectors. For
the other detectors, which use integrating filters, it is typically chosen as the center of the frequency range.

PHASE-LOCKED LOOPS, APPLICATIONS

The corresponding input signals are

If we use an ideal multiplier followed by a low-pass filter, we obtain

Using a low-pass rejection filter for the second harmonic, we take the output as

To obtain the sinusoidal form we have to include a /2 phase shift, offset . Thus if we define s = s and
o = o /2, we have the sinusoidal error form. An important aspect of the sinusoidal detector is the need for
amplitude control of the input signals to avoid gain variations due to the signal amplitude changes. The needed
product may be obtained using a variety of mixer configurations. See Egan (2) for an analysis of the various
types of mixers used as phase detectors.
The simplest way of considering the triangular detector is to replace the cosine inputs of the sinusoidal
detector with pure square waves. Then the phase-detector response is simply the convolution of two square
waves, providing the triangular response after filtering. Due to the multiplication process, the same /2 phase
shift is required as used for the sinusoidal detector. A simple square-wave phase detector is a logic AND, OR, or
exclusive-OR gate. If we filter the output of the gate, we obtain the logical product with a dc voltage offset, the
latter describing the linear variation of the two waves from in phase to totally out of phase. For the AND gate,
the dc offset is 14 the maximum output voltage, the variation between between 0 and one-half the maximum
output voltage. The OR gate simply raises the average voltage of the AND gate to three-fourths the maximum
output voltage of the gate. Relative to the center of this voltage variation, we have triangular-wave performance
of the offset voltage with respect to the phase difference of the two signals.
A ramp detector has a phase offset of 180 ( rad). This form of detector is obtained by using the two input
signals to set and reset an edge-triggered RS flip-flop, followed by appropriate low-pass filtering.
The extended ramp requires no phase offset and obtains its output from a tristate logic circuit that has a
cycle memory to extend the range beyond a single cycle. This detector is one of the most commonly used phase
detectors in integrated systems. The extended ramp is simply a transient-logic combination of ramp-type
detectors and is commonly called a phasefrequency detector. A fundamental problem that has been overcome
in recent years is its zero-phase residual error. The transition through the zero-phase crossing involves several
state changes, which may cause random behavior. The frequency-detection properties of the detector occur
when the PLL is not in lock, creating a high or low triangular waveform with one-way transitions shown by
the arrows of Fig. 4(d). This highlow feature causes an additional dc offset that aids in frequency acquisition.
The detector is generally followed by an integrating low-pass filter in order to reach a zero steady-state error
with no frequency or phase error. Further information on these detectors are given by Egan (2), Best (3), and
Rohde (4).

PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 5. Filter for spurious-output rejection. This simple low-pass filter is the minimum filtering that should be used with
a PLL to rejected unwanted frequency products produced in the phase-detection process.

A final phase detector that should be noted is the sample-and-hold. The classic sample-and-hold extracts a
sample of an oscillator signal and holds it until the next sample, at which time the hold is simply updated. This
technique operates much like a sinusoidal detector for a sinusoidal input signal, having the digital equivalent
of a D flip-flop phase detector. The sample-and-hold can offer a major advantage in feedthrough reduction for
the pulsed phasefrequency detector. To take advantage of such a use in a synthesizer, the sample is held
off one or more clock cycles of the VCO frequency. Thus, the sample is taken after the integrated output of
the phasefrequency detector has settled. In so doing, the feedthrough signal is reduced to a correction step
rather than a short pulse, substantially reducing the sideband generation in the system. The sample-and-hold
detector is not restricted to following another detector, but may be used directly as the phase detector. It is
sometimes advantageous in a synthesizer application to cascade two sample-and-hold phase detectors to obtain
even further sideband reduction. Further filtering should still be used, but with reduced rejection requirements
on the filter.
A second significant use of the sample-and-hold detector is in microwave frequency synthesis and stabilization. For this application, the sample is taken on every N th cycle of an input sinusoidal waveform from the
VCO. The result is to effectively treat the input signal as though it were N times smaller, acting as a synthesizer
with a frequency that is N times the reference frequency. For many applications, the primary purpose of this
multiplying loop is to stabilize a microwave oscillator that may otherwise drift in frequency with temperature
and power.
Filters. The filters of the phase-locked loop provide two vital functions. First, the PLL filter provides the
necessary feedback frequency response to control the gain and bandwidth of the system. An additional low-pass
characteristic that should always be included provides the needed spurious rejection of mixing products that
result from the phase-detector operation. In frequency synthesis applications, the feedthrough of the spurious
frequencies of the phase detector is the major cause of sideband modulation components in the oscillator output.
These sidebands are usually severely restricted by governmental regulation to prevent interference with other
spectrum users. Thus the regulatory issue is a major concern that must be added to the problem, where the
spurious products usually have little effect on the PLL performance other than the sideband generation. On
reception, interference rejection of adjacent-channel signals, produced by the conversion with the spurious
sidebands generated in the VCO, is also a potential problem.
It is a good rule to make the filter only as sophisticated as needed for the particular application. If no
bandwidth control is needed, then a simple low-pass filter for eliminating the spurious frequencies may be all
that is used. In such a case, the filter bandwidth will be above the PLL bandwidth and may be obtained with
a simple RC low-pass filter. In such a case, the PLL operates in a first-order mode within the bandwidth of
operation.
The filters used in the PLL define the system type and order. The order refers to the degree of the system
polynomial in the denominator of the transfer function, while the type refers to the number of integrators in
the loop. By default, a PLL is at least a type-I loop. An ideal first-order loop would have no filter. In reality,
we use a filter (Fig. 5) to eliminate the spurious outputs of the phase detectors. However, as long as the filter
bandwidth is much greater that the loop bandwidth (which is K for this case), the linear system analysis of the
loop is closely approximated by a first-order loop with no filter.

10

PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 6. Laglead passive filter with spurious-frequency rejection. The lead produced by R2 returns the filter response to
a constant for transition through the bandwidth limit, reducing the potential instability due to a small phase margin. The
capacitor C3 is added to provide high-frequency rejection of the undesired phase-detection products.

The laglead filter is easily implemented in discrete form with the addition of a single resistor as shown
in Fig. 6. The extra capacitor, C3 , provides the spurious-sideband rejection and is not directly a part of the
laglead circuit. This filter is described by

where the approximation occurs when the extra capacitor is ignored. A second laglead filter may be cascaded
with this filter to obtain an approximation to a double-pole, double-zero filter for use in a third-order system.
Third-order systems find use in tracking of low-earth-orbit satellites, which have an acceleration profile that
causes a continuously changing frequency. The third-order system is necessary to minimize the steady-state
phase error in the received signal and is typically implemented as a type-II loop.
Active filter systems are useful for implementing many filter functions. A major advantage of active filters
is their ability to make the denominator of the filter function a simple s and thus yield an integrator. Such a
configuration is shown in Fig. 7, giving

The new difficulty added by active filters is a phase inversion in the path that must be correctly taken
into account in the feedback analysis. An additional filter is simply cascaded if needed.
One must take care that the high-frequency response of the operational amplifier used does not allow
undesired pulse streams through the device. It is often wise to add passive rejection filters within the activefilter design to guard against such problems. In practice, the frequency response of the operational amplifier
limits the ability to reject the transmission of the higher-frequency spurious signals, for which C3 is added. To
aid in the rejection and reduce the potential for overdrive of the operational amplifier, C3 may be relocated as
part of an input T network as shown in Fig. 8, giving

Additional factors that must often be adjusted in practical systems are offset voltages within the filters
and other components.

PHASE-LOCKED LOOPS, APPLICATIONS

11

Fig. 7. Integrating operational-amplifier filter with spurious-signal rejection, providing the desired zero to control the
phase margin while still providing high-frequency rejection with C3 .

Fig. 8. Modified filter for improved spurious-signal rejection. This filter is a modified version of Fig. 7, designed to reduce
possible high-frequency feedthrough in the filter due to inadequate operational-amplifier performance and to also avoid
overdrive of the amplifier.

Oscillators. The type of oscillator depends strongly on the application at hand. For low-frequency
applications, the oscillator that forms the VCO in the loop is often a simple multivibrator, typically constructed
with a balanced pair of devices and current-controlled in frequency. As frequencies are increased into the radio
and microwave realms, the oscillators are generally tuned circuits (resonant LC combination, cavity, or YIG
structure) with varactor frequency adjustment. The circuits are often balanced to reduce harmonic content, and
varactors are often used in pairs to reduce noise effects. Care must be used in providing the bias to varactors.
These units are part of a tuned circuit that effectively forms a low-pass filter with the bias resistor to the
control signal, producing an unwanted lag filter in the loop. In addition, the resistor must be sufficiently large
not to reduce the Q (or bandwidth) of the tuned circuit and yet not so large as to become a substantial noise
source in the loop. Noise is a critical item of concern in the design of synthesizer systems.
The tuning of the VCO is often nonlinear, even with some multivibrators. It is sometimes desirable
to linearize the voltage-to-frequency response, improving the linear system performance of the loop. Such
linearization is generally done with a diode switching network for selective loading that creates a piecewise
compensation of the VCO transfer function to obtain an effective linearization of the transfer. One drawback
to such piecewise loading systems is the inherent noise that may be created in the process.
In power and related applications, the oscillator may not always be obvious. The effective oscillator may
be a variable-speed motor that must be controlled or be a fully mechanical system such as the combustion
engine of an automobile with a speed sensor on the shaft. The specific design of oscillators is not the goal of

12

PHASE-LOCKED LOOPS, APPLICATIONS

this section, but rather a brief consideration of the types of units that might compose an oscillator in a PLL
system. For the purposes of analysis, the oscillator, frequency divider, and offset oscillator to be considered in
the applications may be considered as a single oscillator. Keep your mind open, and you may be surprised at
the systems that might be considered as oscillators in a PLL.

Acquisition
Analytic Approach. The first step in the operation of a PLL is the acquisition phase. In the previous
sections we considered the PLL as a linear system, always in lock. We begin the consideration of achieving
this locked state by assuming the VCO is running at a free-running frequency and the input is offset from the
free-running frequency by an amount 0 . The analysis that follows provides a basic viewpoint of acquisition
for the generic loop with a sinusoidal phase detector. If the detector is a triangular or ramp type, the same
basic mechanism occurs with a slight increase in the effective detector gain for the beat-frequency component
of the system. The analysis for the phase-frequency detector is a bit simpler due to the built-in offset voltage
when the frequencies are different. Other considerations must also be taken if the filter is an integrator that
is likely sitting on a power-supply rail when out of lock.
This analytical derivation is approximate, but gives surprisingly useful guidelines to the acquisition
process of phase-locked loops with laglead filters. We assume that only a sinusoidal term plus a slowly
varying offset need be considered at the control terminal of the VCO. With this in mind, we will look at the
operation of the loop for frequency differences in the various frequency ranges of the loop filter in order to
obtain limits on acquisition as well as an estimate of the time for acquisition.
For the nonintegrating laglead filter used with nearly all but the phasefrequency detector, the output of
the detector will be dominated by a beat frequency between the two detector inputs and a small low-frequency
(approximately dc) part that provides the locking mechanism. For such an output, we may write the control
voltage of the loop as approximately

From this voltage we may write the output of a sinusoidal detector as

PHASE-LOCKED LOOPS, APPLICATIONS

13

The quantity is an unknown phase offset of the VCO. We have chosen to use simple Taylor expansions
of the trigonometric functions rather than taking the additional step of using Bessel functions before taking a
Taylor series.
For the analysis we will assume the first term of Eq. (20) is above the filter breakpoints and is simply
reduced in amplitude by the high-frequency response of 2 /1 of the filter. The second term is considered slowly
varying and is the term we shall consider for the filter interaction. Thus we have

where the denotes convolution in time. Assuming the second term is a low-frequency term as previously
mentioned, we can determine coefficients by comparison with the original vc to give

Thus we may write a summary equation as

Rather than work with the full f (t), we may consider each frequency range of the filter separately. The
purpose of checking each region to search for a possible solution and or limit on the operation. First, consider
f (t) 2 / 1 (the high-frequency response). Equation (23) becomes

with solution

There are two cases of interest. First, if o

K 2 /1 , the solution provides
for a constant difference frequency as well as a low-frequency term at zero frequency, not above 1/2 , which
is an invalid solution. If o

K 2 /1 , the solution is nonphysical and we have

14

PHASE-LOCKED LOOPS, APPLICATIONS

chosen the wrong region of the filter for the analysis. Thus this frequency range of operation is not possible
within the constraints of the model.
For the second low-frequency, unity-transmission region, we have

or

Again there are two cases of interest. First, if o

, the solution is
a constant difference frequency along with a low-frequency term at zero frequency, an out-of-lock condition.
This limit becomes our basic limit of frequency pull-in, p , the range within which the PLL is able to lock
, the solution is nonphysical and we have again chosen
eventually. If o
the wrong region of the filter for the analysis.
The third midrange frequency region gives an integration of the detector output that is needed for
acquisition as

with a solution given by

In this analysis we have used the smallness restriction that

At the limit of this restriction, the PLL has reached the system bandwidth and ceases the pull-in process
of acquiring lock we have just identified, locking in without further cycle slippage. This latter process is the
basic transient response of the system and is referred to as lock-in; it occurs over a range L . The time it
takes for this process to move the VCO from the starting offset frequency to the loop bandwidth comes from
Eq. (29) as

PHASE-LOCKED LOOPS, APPLICATIONS

15

The pull-in transient occurs in about 2 seconds, giving a total acquisition time of

Thus 2 has a major role in setting the acquisition time of a loop. For the largest frequency of pull-in,
called the pull-in range, we have

If the frequency difference of the loop is within this range, the loop will eventually pull in to the locked
condition. After the pull-in process error reaches the loop bandwidth, the transient effects of a well-designed
loop will take over and complete the locking process with no further cycle slippage. The smaller range over
which this occurs is the lock-in range; it is approximately equal to the loop bandwidth and given by

The integrating filter does not have a low-frequency, unity-gain region. Thus the pull-in range for the
integrating filter is not limited by the detector, but rather by the filter, amplifier, or VCO. Unfortunately, an
integrator also tends to send an unlocked PLL to a supply limit of one of the components rather than to the
free-running frequency for an initial value, so that it requires an acquisition-process initialization. With active
filters, the initialization may simply be a Schmidt trigger arrangement that reverses the bias voltage on the
reference terminal to begin integration back across the active region of the device. As long as the desired
frequency is within the tuning range, this integration process should pick up the locking process. In the case
of the phasefrequency detector, the detector has a built-in bias that is added to the loop-filter input if the
frequencies of the inputs differ. This bias results from the phasefrequency detector being reset to the center
of the phase range rather than the opposite phase limit when the range is exceeded [refer to Fig. 4(d)].
Phase-Plane Approach. In the phase-plane approach, it is desired to relate the time derivative of
the phase error to the instantaneous phase error. In relating these two properties, a plot may be made of the
phase error versus time. In a numerical sense, you would simply start with the current phase error, determine
the time derivative, and estimate the new phase error at the next time step. In stepping through the process,
acquisition will occur if the process converges to smaller phase errors as time progresses and the phase error
cycles through multiple cycles. These plots are interesting, and the reader is referred to Blanchard (1) for
further information.

Noise Fundamentals
Noise can be a problem in PLL systems, though it can be alleviated by the proper use of PLLs. Slightly
different problems are encountered for low and for high signal-to-noise ratios. For the small-signal case, many
of the small-signal approximations relating amplitude and phase may be used. For the large-signal case, the
nonlinearities of the system must often be considered, particularly with respect to the the potential for loss

16

PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 9. Simple noise model of a PLL, with a generic noise being added at a single point just after the detector. This location
is most suited to the analysis of the noise in a PLL used as a receiving system, yet represents the fundamental concepts of
general noise analysis.

of lock and cycle slipping. This overview of noise will provide a basic knowledge of the noise effects in PLL
systems, and further comments will be made in other sections.
A Simple Noise Model. The basic model typically adds a noise source in summation with the output
of the phase detector as shown in Fig. 9. Both Gardner (5) and Blanchard (1) discuss the case of additive
Gaussian noise at the model input. Rohde (4) adds substantial information on noise sources within the PLL
itself. Manassewitsch (6) concentrates on the determination of noise bandwidth. Approaches to high-level noise
are built around nonlinear system descriptions, often incorporating Monto Carlo techniques for analysis of the
noise statistics and determination of the potential for loss of lock. We refer the reader to the classic papers by
La Frieda and Lindsey (7) and by Viterbi (8) for details on high-level noise problems.
The level of noise in the model is determined by the translation of the input statistics due to the additive
noise conversion in the detector process and by the noise figures of the remaining components in the loop,
referenced to the detector output. We may typically treat the noise as a broadband noise voltage and simply
evaluate the transfer of this noise to the appropriate point of the loop. This explanation is slightly oversimplified,
but contains all of the basic analysis needs of the problem. If we consider the output point of interest to be the
o at the output of the VCO, the appropriate transfer function is simply H(s)/K d . Thus the noise properties are
determined by the amplitude of the noise-source power density times the noise bandwidth. The latter is not
necessarily the 3 dB bandwidth; is often found to be 1.5 times larger than the 3 dB bandwidth, and is obtained
through integration of the transfer function.
A major source of noise is semiconductor junctions, which create partition and shot noise. Any resistive
component in the loop is a source of wideband thermal noise proportional to kTB (k being Boltzmanns constant,
1.38 10 23 J/K; T being the absolute temperature, often taken as 290 K; and B being the bandwidth in hertz).
Such thermal noise was mentioned in connection with the choice of the isolation resistor used with varactors.
The spurious output of the detector may also be treated as noise, though by no means Gaussian. Other
low-frequency noise results from active device flicker (a low-frequency noise particularly important in the
phase detector, filter, and amplifier) and poorly chosen feedback levels in the VCO. Stability and microphonics
(frequency variations due to mechanical vibrations of the VCO components) are also critical aspects of the
VCO. People often forget that a VCO is mounted in a hostile environment where it may be subject to severe
vibration, particularly in the 1000 Hz range for automobiles and aircraft. Such periodic noise can cause havoc
through unwanted modulation on the VCO and is not corrected by the PLL for higher frequencies.

PHASE-LOCKED LOOPS, APPLICATIONS

17

Fig. 10. PLL with a frequency divider in the feedback loop, forming a basic, divider-type frequency synthesizer.

All of these sources, as suggested, may typically be lumped together as a single source at the output of
the detector and the noise analysis done by simply considering each of them as independent and feeding the
system transfer function. Improvement in noise performance involves improving the noise filtering properties
of the transfer function or reducing the noise contribution of individual components to the system. Though
simple in concept, this noise reduction process is often tedious and is considered by many to be an art.
Though this noise discussion has been brief, it should point to the potential sources of noise and the
fundamental analysis process for determining their contributions to the system noise. It is also wise to remind
the reader that the uncorrelated noise power adds, not the noise voltage. Pure random noise has zero correlation
with other noise sources. A few comments are offered on noise throughout the applications, but to only suggest
the correct path to consider in design.

Applications of Phase-Locked Loops

The PLL has wide application. The majority of its applications fall into four main categories:

Frequency synthesis
Frequency (FM) and phase (PM) modulation and demodulation
Data and carrier recovery
Tracking filters

Frequency Synthesis. Frequency synthesis is one of the most widely used applications for PLLs. The
local oscillators in most cell phones, land mobile radios, television sets, and broadcast radios are built around
PLLs. Frequency-synthesizer integrated circuits are available from a number of manufacturers (3). The basic
topology of the PLL frequency synthesizer is shown in Fig. 10.
The phase difference between a reference signal, ref , and a divided sample of the output frequency,  o ,
is measured at the phase detector. In a synthesizer, the signal frequency previously used is replaced by a
frequency standard referred to as the reference signal. When phase lock is achieved, the output frequency from
the divider must be equal to

where N is the divider ratio and ref is the reference frequency. The basic frequency synthesizer acts as a
frequency multiplier. Since the phase comparison is done at the reference frequency, the effective VCO gain is

18

PHASE-LOCKED LOOPS, APPLICATIONS

given by

A synthesizer loop can be analyzed as a conventional loop where the VCO gain above is substituted into
the calculations.
The value of N is often made programmable. N is an integer; so changing it has the effect of increasing or
decreasing the output frequency,  o , in steps that are a multiple of ref . It is also important to recognize that
changing the value of N has the effect of changing the loop dynamics. Since the VCO gain K o is a function of N
in a synthesizer, changing N will change the critical parameters n and in second-order loops and the phase
margin in third and higher-order loops.
The value of N influences the loop transfer function H(s). Consider the situation where s = jm and m is
a modulating frequency:

or

Any phase or frequency deviation on the reference is multiplied N times for the output by the synthesizer.
Figure 10 shows a simple synthesizer with a divider in the loop. It is also possible to put a mixer in the
loop. This configuration is called an offset loop, and it is shown in Fig. 11. In order for the loop to be locked, the
following must be true:

or

The offset oscillator can operate either above or below the output oscillator frequency, and the filter can
select either the sum or the difference of the two oscillator frequencies. In the case of the offset loop, the loop
gain is unaffected by the frequency translation, expect for a possible phase inversion. The divider in Fig. 11
can be bypassed. In such a case N is set to one.
In most synthesizers, the reference frequency ref must be significantly higher than the loop bandwidth.
The reason for this requirement is that the output of most phase detectors is not a pure dc signal. The signal
is pulses whose duty cycle and/or polarity are proportional to the phase difference. The loop filter not only sets
loop dynamics, but it must reject the ac component of the phase-detector output, passing only the dc value to the
VCO. The attenuation of the loop filter is finite, so some of the ac component does make its way to the VCO. The

PHASE-LOCKED LOOPS, APPLICATIONS

19

Fig. 11. Offset-loop frequency synthesizer. The offset oscillator is often used to lower the frequency requirements on the
divider.

result is undesired phase modulation sidebands at the reference frequency on the output signal. Narrow-band
loop filters provide better suppression of this reference feedthrough, but narrow-band filters exact a cost. Notch
filters are also used to filter out the reference frequency components.
Consider this example: The channel spacing in the FM broadcast band is 200 kHz. A synthesizer with a
reference frequency of 200 kHz will produce steps at the channel spacing. A second-order type-II synthesizer
loop, = 1, n = 2 (200 Hz), will settle in approximately 10 ms to within 100 Hz of its target frequency after a
200 kHz step. A similar loop with a reference frequency of 200 Hz will produce 200 Hz steps but, everything
else being the same, will require that n = 2 (0.2 Hz) to produce the same level of reference suppression. This
loop will take almost 8 s to settle to the same accuracy after being commanded to change frequency by 200
kHz.
Most cell-phone, television, and broadcast radio receivers employ simple offset or divider-type synthesizers. For these applications, the required step size is usually much greater then the loop bandwidth required
for the desired dynamics. In order to produce small steps and at the same time obtain acceptable reference
suppression and settling time, it is often necessary to resort to multiloop synthesizers.
An example of a multiloop synthesizer is shown in Fig. 12. It was designed for an upconverting HF (0 to
30 MHz) in a communications receiver with a 75 MHz IF (4). This synthesizer will produce 10 Hz steps, but it is
much more complex than a simple offset or divider-type synthesizer. Loop 1 in Fig. 12 is a simple divider-type
synthesizer. It tunes from 50 MHz to 60 MHz in 1 kHz steps. The output of this loop is divided by 100, and
the resulting 0.5 MHz to 0.6 MHz output changes by 10 Hz each time the divider in loop 1 is incremented or
decremented by 1. Loop 2 is also a divider synthesizer, but it tunes from 75.5 MHz to 106.5 MHz in 100 kHz
steps. Loop 3 is an offset loop without a divider. This loop forces the difference between the loop-3 VCO and
the loop-2 VCO to be equal to the divided output of loop 1. Loop 1 can tune loop 3 over a 100 kHz range in
10 Hz steps, while loop 2 tunes loop 3 from 75 MHz to 105 MHz in 100 kHz steps. By proper choice of divider
programming, it is possible to continuously tune the loop-3 VCO from 75 MHz to 105.1 MHz in 10 Hz steps.
The multiloop synthesizer in Fig. 12 employs a combination of divider and offset loops. Another technique,
called fractional N, permits a synthesizer to produce steps smaller than the reference frequency. Details on
fractional-N synthesizers can be found in Refs. 9 and 10. A particularly simple implementation of a fractional-N
synthesizer can be found in Ref. 11.
The design of frequency synthesizers is often a careful balancing act that requires minimizing the lock
time, the reference feedthrough, and the spurious outputs generated by mixing and dividing, while at the same

20

PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 12. This triple-loop frequency synthesizer of Rohde can tune from 75 MHz to 105.1 MHz in 10 Hz steps (4). Loop 1
is used to obtain a stable 10 Hz step interval for use in locking loop 3 to 10 Hz steps.

Fig. 13. PLL configured as a frequency or phase demodulator. The outputs at u1 and u2 offer tracking alternatives for
demodulation, allowing output for frequencies both above and below the loop bandwidth.

time meeting power, size, frequency, and step-size requirements. The literature contains additional information
on these design tradeoffs (4,9,10,12).
Modulation/Demodulation. A PLL can be used for phase or frequency modulation and demodulation.
Before presenting the analysis, it maybe valuable to obtain an intuitive understanding of the modulation
demodulation process.
Figure 13 contains the block diagram of a PLL configured as a demodulator. If the modulating frequency
m is inside the loop bandwidth, the loop follows the phase and frequency of the incoming signal with little
error. The phase (and thus the instantaneous frequency) of the VCO follows that of the input signal. The VCO
control voltage u2 must be an exact replica of the modulating voltage for this to be true. It is generally assumed
that there is a linear relation between the control voltage and the VCO frequency. If the relation is nonlinear,
the VCO will still track the input frequency, but the control voltage will be a distorted replica of the modulation
voltage.

PHASE-LOCKED LOOPS, APPLICATIONS

21

Fig. 14. PLL configured as a frequency/phase modulator. As in Fig. 13, this configurations offers alternative modulation
inputs for modulation frequencies both above and below the loop bandwidth.

When the modulation frequency is outside the loop bandwidth, the VCO phase will no longer track the
instantaneous input signal phase. The loop can only track the average frequency of the incoming signal. This
causes the average VCO phase to remain constant. The instantaneous output voltage of the phase detector will
be a function of the difference between the applied phase modulation and the average VCO phase. Thus, the
phase-detector output voltage will be a replica of the source modulating voltage.
The output voltage for a FM demodulator is given by

Here s (m ) is the frequency deviation of the input signal and m is the modulating frequency. Recall
that H(jm ) 1 for m less than the loop bandwidth. For the phase demodulator, the output voltage can be
obtained at u1 as

where s (m ) is the phase deviation of the input signal. Note that

The situation is reversed for the PLL modulator shown in Fig. 14. Here a modulating voltage is added to
the loop. In the case of frequency modulation, the VCO control voltage is the sum of the voltage from the loop
filter, F(s), and the modulating voltage, u2 . If the modulating frequency is less than the loop bandwidth, the
loop will interpret any change of frequency due to u2 as an error and produce an equal and opposite correction
voltage at the loop filter output. The result is no change in the output frequency. If, however, the modulating
frequency is greater then the loop bandwidth, the loop can only follow the average frequency. The instantaneous
frequency will be controlled by u2 , and frequency modulation will result.
Phase modulation can be generated by introducing the modulation voltage at u1 . When the modulating
frequency is less than the loop bandwidth, the modulating voltage will cause a phase change at the VCO, which
the loop will track. The VCO phase must be adjusted to produce a phase difference at the phase detector that
cancels u1 . The VCO phase is now forced to track u1 ; thus the VCO output is phase-modulated. Beyond the
loop bandwidth, the loop can no longer track the error introduced by u1 and no modulation will occur.

22

PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 15. Generic phase-locked loop with options. The options include frequency offset, frequency division, and modulation
and demodulation terminals.

The output deviation of the FM modulator is given by

Here o (m ) is the frequency deviation of the input signal and f m is the modulating frequency. We have

For the phase modulator, the output phase deviation can be obtained by

where o (m ) is the phase deviation of the output signal and H(jm ) 1 for m less than the loop bandwidth.
For FM the loop acts as a high-pass filter, and for PM the loop acts as a low-pass filter. Loop-bandwidth
considerations driven by loop dynamics and reference suppression may prevent FM at low modulating frequencies or PM at high modulating frequencies. It is possible to overcome some of this limitation by applying the
modulating voltage at both u1 and u2 . Low-frequency FM can be generated by applying the modulating signal
to u2 in the conventional manner and applying an integrated version of the modulating voltage to u1 . Details
of this process can be found in Ref. 2.
It is also possible to obtain low-frequency FM by modulating the reference. For frequencies less than the
loop bandwidth the instantaneous phase and frequency are transferred to the output. This technique is used

PHASE-LOCKED LOOPS, APPLICATIONS

23

Fig. 16. The Costas loop for BPSK demodulation specifically locks to the carrier so that the modulation data may be
recovered. In this role, it is a carrier recovery loop.

in land mobile and cellular phone transmitters in conjunction with divider-type synthesizers. The synthesizer
acts as a multiplier, and a small amount of modulation applied to the reference is multiplied at the output.
All real oscillators are phase-modulated with noise. This noise modulation results from the finite-Q
resonators in the oscillators and the inherent noise of the active devices used in oscillators. While a full noise
analysis is beyond the scope of this article, combining the multiplier effect with the loop modulation response
gives insight into the noise performance of synthesizers. A more complete analysis can be found in the literature
(6,10,13).
Phase noise in oscillators is often described by a single-sided power spectral density L . Below the loop
bandwidth, the loop follows a multiplied replica of the noise on the reference signal. The phase noise on the
VCO is suppressed, as the VCO phase is forced to follow the reference phase. Beyond the loop bandwidth, the
VCO phase no longer follows the reference phase, the error between the VCO and the reference increases, and
the noise output becomes the noise of the VCO. This effect can be expressed by

A careful choice of loop bandwidth can minimize the total noise output. An example of this can be seen
in many microwave synthesizers. Well-designed microwave oscillators such as YIG oscillators have very low
phase noise at large offsets m from the center frequency, but close to the center frequency their phase noise

24

PHASE-LOCKED LOOPS, APPLICATIONS

Fig. 17. Earlylate data synchronizer that offers the ability to synchronize with a data stream in order to have reliable
recovery of the data stream in a sampled detection system.

is relatively high. Crystal oscillators multiplied into the microwave region, on the other hand, have very low
noise close to the center frequency, but the multiplication process tends to bring up the noise far removed from
the center frequency. The loop bandwidth can be chosen so the crystal-oscillator noise dominates close to the
center and the microwave oscillator noise dominates at large offsets from the center frequency. Such a loop is
referred to as a cleanup loop.
Data and Carrier Phase Recovery. Synchronization is probably one of the oldest applications for the
PLL. The timing and phase synchronization of 60 Hz power generating plants can be analyzed as a kind of
PLL. Television, and particularly color TV, would not be possible without PLLs to extract timing and phase
information from the TV signal. The growth of digital systems that employ various types of phase and phasedifference modulation has brought renewed interest in PLLs to extract phase and timing information from a
data stream.
An example of a carrier phase recovery loop is the Costas loop. A Costas loop is shown in Fig. 16. The
Costas loop can coherently demodulate binary phase-shift keying (BPSK) signals. With a BPSK signal, a phase
shift of /2 or /2 rad represents a data 0 or 1.
The input to the loop is 2 cos(c + i /2) = 2 sin(c + i ), where c is the carrier frequency and
i is the carrier phase. The /2 represents the data modulation. The input is equally split and multiplied
by the quadrature of a locally generated carrier, cos (c t + o ), in multipliers A and B. The low-pass filters
extract the difference signals from the product. The result is a quadrature of the phase difference between the
locally generated carrier and the incoming signal, cos(i o ) and sin (i o ). These quadrature outputs
are multiplied together in multiplier C. The result is a doubling of the quadrature component arguments as
0.5 sin [2 (i o )]. The modulation disappears, and the resulting phase difference between the input and the
output is used to steer the VCO. While this example is for simple BPSK, it is possible to design similar loops
for N-phase modulation (5).
Another data synchronizer is the earlylate gate (5). The circuit works well for rectangular pulses. Figure
17 contains a block diagram of an earlylate gate synchronizer. Figure 18 shows the timing.
Integration from + T bit /4 to the data transition is controlled by the late timing. This integration will
produce an equal and opposite value for the integration controlled by the early timing from T bit /4 to the data
transition only if the data transition occurs halfway between + T bit /4 and T bit /4. The VCO is steered to this
point by the difference of the absolute values of the integration products.

PHASE-LOCKED LOOPS, APPLICATIONS

25

Fig. 18. Earlylate data synchronizer timing, showing the balance of the early and late pulses used to center the data
stream.

Fig. 19. Bandpass and low-pass representation of a PLL, emphasizing the relationship between the transmitted signal
and the baseband representation of the signal used for detection.

Tracking Filters. Tracking filters are another early application for the PLL. The early space program
used PLL receivers to track weak satellite signals that were accompanied by changing Doppler shift.
The loop transfer function, H(jm ), is almost always represented by its baseband representation, but
phase measurement is actually accomplished at some carrier frequency. The loop appears as a bandpass filter
centered at c with bandwidth twice that of H(jm ). See Fig. 19. The unique property of this filter is that it can
track c as it changes. A signal with large frequency excursions can be passed through a filter that would be
otherwise too narrow to accommodate the frequency changes by using PLL tracking-filter technology.
Since it is desired to follow Doppler-shifted signals or signals that change frequency, loop dynamics
are an important consideration. The loop dynamics are related to the loop order and loop type. Loop type is
determined by the number of poles at zero in the open-loop transfer function. Table 1 shows the dynamic
behavior of various loops. The table shows the loop phase error after the loop reaches steady state following
a phase step, a frequency step, or a frequency ramp. The frequency ramp can be used to describe the loops
performance in tracking a satellite signal as the satellite passed from horizon to horizon.

26

PHASE-LOCKED LOOPS, APPLICATIONS

Conclusions
This article has provided the fundamentals of PLL analysis and several examples to illustrate typical applications. There are many extensions that may be made to a PLL for a particular application. The emphasis of
this article has been to highlight the process of the analysis and operation so that such extensions are easily
handled. The examples of frequency synthesis, frequency and phase modulation and demodulation, data and
carrier recovery, and tracking filters have provided extensions to suggest the variety of configurations that may
be considered. In all cases, the extensions may be brought back to the form of the basic PLL for analysis, giving
the reader the fundamental tools needed to design effective phase-locked systems.

BIBLIOGRAPHY
1.
2.
3.
4.
5.
6.
7.

8.
9.
10.
11.
12.
13.

A. Blanchard Phase-Locked Loops: Application to Coherent Receiver Design, New York: Wiley, 1976.
W. F. Egan Phase-Lock Basics, New York: Wiley, 1998.
R. E. Best Phase-Locked Loops: Theory, Design, and Applications, 3rd ed., New York: McGraw-Hill, 1997.
U. L. Rohde Digital PLL Frequency Synthesizers: Theory and Design, Englewood Cliffs, N J: Prentice-Hall, 1983.
F. M. Gardner Phaselock Techniques, 2nd ed., New York: Wiley, 1979.
V. Manassewitsch Frequency Synthesizers: Theory and Design, 3rd ed, New York: Wiley, 1987.
J. R. La Frieda W. C. Lindsey Transient analysis of phase-locked tracking systems in the presence of noise, IEEE
Trans. Inf. Theory, IT-19: 155165, 1973; in Lindsey and Simon (eds.), Phase-Locked Loops & Their Application, New
York: IEEE Press, 1978.
A. J. Viterbi Phase-locked loop dynamics in the presence of noise by FokkerPlanck techniques, Proc. IEEE, 51,
17371753, 1963; in Lindsey and Simon, (eds.), Phase-Locked Loops & Their Application, New York: IEEE Press, 1978.
W. F. Egan Frequency Synthesis by Phase Lock, 2nd ed., New York: Wiley, 2000.
U. L. Rohde Wireless and Microwave Frequency Synthesizers, Englewood Cliffs, N J: Prentice-Hall, 1997.
S. D. Marshall Extending the flexibility of a RFIC transceiver through modifications to the external circuit, MS Thesis,
Virginia Tech, Blacksburg, VA, 1999; http://scholar.lib.vt.edu/theses/available/etd-052599-165152/
J. A. Crawford Frequency Synthesizer Design Handbook, Boston: Artech House, 1994.
W. P. Robins Phase Noise in Signal Sources, IEE Telecommunications Series 9, London: Peregrinus, 1982.

WILLIAM A. DAVIS
DENNIS G. SWEENEY
Virginia Tech

200

PHASE SHIFTERS

The attenuation of the microwave signal due to the presence

of the phase shifter can be calculated from its S parameters,
and it is expressed in decibels as
(Insertion loss)1 = 20 log |S21 |

(3)

(Insertion loss)2 = 20 log |S12 |

(4)

The subscripts 1 and 2, respectively, refer to the phase shifter

when the input signal is at port 1 or port 2. The mismatch is
expressed as standing wave ratio (VSWR) at each port and is
given by

PHASE SHIFTERS
A microwave phase shifter is a two-port device capable of producing a true delay of a microwave signal flowing through it.
The produced time delay can be fixed or adjustable, and the
phase shifter is accordingly called fixed phase shifter or tunable phase shifter. The geometry of the phase shifter is intimately related to the guiding structure which is used to design it and is also related to the operational frequency. Most
phase shifters are realized in waveguides or in planar structures. Electrically, a phase shifter can be characterized by its
scattering parameters matrix. The scattering matrix for an
ideal phase shifter (see Fig. 1) takes the form


0
e j 1
S = j
(1)
e 2
0
The signal arriving at port 1 will appear at port 2 with a
phase shift 1 without being reflected at port 1 and with no
attenuation, while the signal arriving at port 2 will appear at
port 1 with phase shift 2 and without reflection or attenuation.
In general, 1 2 and the phase shifter is called nonreciprocal, and if 1 2 the phase shifter is called reciprocal. In
practice it is impossible to achieve perfect matching at the
two ports (no reflection) and to avoid some attenuation while
the signal flows through the phase shifter. For these reasons
the scattering matrix of a real phase shifter can be written in
general as


|S21 |e j 1
S11
(2)
S=
|S12 |e j 2
S22

b1 = S11a1 + S12a2

a2
S11 S12
S21 S22

a1
Port 1

b2 = S21a1 + S22a2
Port 2

Figure 1. Phase shifter viewed as a two-port device.

(VSWR)1 =

1 + |S11 |
1 |S11 |

(5)

(VSWR)2 =

1 + |S22 |
1 |S22 |

(6)

In order to evaluate the performance of a phase shifter, it is

necessary to introduce a quality factor. For a phase shifter
operating at a specific frequency we can define a figure of
merit as the ratio between the maximum phase shift (in degrees) and the corresponding attenuation in dB at that frequency. This parameter can be expressed as
figure of merit =

(phase S21 )
|S21 |

(7)

The performance of a phase shifter can be measured using a

standard S parameter setup, including a network analyzer
and a test-set of calibration standards suitable for the specific
guiding structure (1).
PHASE SHIFTER CLASSIFICATION
A first classification of a phase shifter can be based on its
phase shifting capability, according to which it can be identified as fixed or adjustable. A fixed phase shifter will provide
a constant phase change between the two ports, while an adjustable phase shifter will provide a phase change between
the ports which can be controlled mechanically or electrically.
Further classification for the adjustable type is based on electrical performance and operational principle. Within the adjustable phase shifters we can distinguish between those
where the phase change is achieved through a mechanical
tuning and those where the change is obtained with an electrical signal. Furthermore, for the electrically tunable type we
can distinguish between those where the phase can be
changed continuously (analog) and those where the phase can
only be changed by discrete steps (digital). Figure 2 shows a
graphical classification of different types of phase shifters.
PHASE SHIFTER PERFORMANCE
In the evaluation of a phase shifter performance, besides the
quantities derived from its S parameters such as insertion
loss, quality factor, and VSWR, other quantities are important for practical design. Below we discuss such parameters
and their corresponding meaning.
Operational Bandwidth. This is defined as the 3 dB
bandwidth (2), which is expressed as the frequency range

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

PHASE SHIFTERS

201

Phase shifters

Tunable

Fixed

Mechanical

Waveguide Coaxial Planar

Electrical

Waveguide Coaxial Planar

Digital

Ferrite

Waveguide

Analog

Semiconductor

Planar

Planar

Ferrite

Waveguide

Semiconductor

Planar

Planar

Ferroelectric

Monolithic Waveguide

Planar

Figure 2. Phase shifter classification chart.

in which the insertion loss is contained within 3 dB

change.
Power Handling Capabilities. This is expressed as the
maximum power which can flow in the phase shifter
without overheating its components or without introducing nonlinear phenomena due to the amplitude of the microwave field. This second limitation is particularly important for phase shifters which employ discrete devices
such as field-effect transistors (FETs) or diodes.
Switching Speed. This is the time needed by the phase
shifter to switch between two different states, usually at
the two ends of the achievable phase shift (larger allowable jump).
Temperature Sensitivity. This expresses the sensitivity
in terms of degree of phase shift degradation per C
change. This parameter should be small to avoid the necessity to adopt thermal compensation.
Physical Size. This parameter can be very important, especially when the phase shifter is employed in a radar
system where thousands of units are required. Physical
dimensions and weight must be minimized even at the
cost of other parameters. As an example, think of a radar
system which needs to be mounted on the front side of a
jet fighter.

FIXED PHASE SHIFTERS

A fixed phase shifter must provide a constant phase change
between its two ports. Theoretically any transmission line
would be suitable for producing such a function as illustrated
in Fig. 3. For instance, in the X band (1) a coaxial cable could

be used as a fixed phase shifter, while in the Ku band a waveguide can be employed for the same purpose. In many applications, it is desirable to achieve a differential phase shift between two lines having the same length. For this purpose,
lines with different time delay must be used. A possible approach to this problem is to change the propagation constant
of the line, loading it with lumped or distributed elements. So
if 1 is the propagation constant of the unloaded line and 2
is the propagation constant of the loaded one, the achieved
differential phase shift will be given by (3)

= (1 2 )x

where x is the length of the line. So the basic idea in the

realization of this type of phase shifter is to change the propagation constant of the transmission line by properly loading
it. As an example, consider the realization of a fixed phase
shifter in circular waveguide geometry. The waveguide is
loaded with metal inserts as shown in Fig. 4. The equivalent
circuits for the loaded and unloaded cases, assuming that the
guide is operating with the fundamental mode TE11 (4), are
reported in Fig. 5. Both lines have the same length, and the
differential phase shift between the two TE11 modes is related

;;
;;
;;;;
E

V1

V2 = V1ej x

45

Port 1

Port 2

Figure 3. Transmission line acting as a phase shifter.

(8)

Unloaded line

Loaded line

Figure 4. Loaded circular waveguide.

202

PHASE SHIFTERS

Y0
Figure 5. Equivalent circuits for loaded
and unloaded circular waveguides operating with the fundamental mode.

Port 1

jBA

Y0
Port 2

Port 1

BB =

BB
sin 2x sin(2x +
)
=
Y0
sin2 x

BA =

BA
sin
cos x (1 cos
) sin x
=
Y0
sin x sin(2x +
)

(9)

jBA

Y0
Port 2

Unloaded

to the normalized susceptance of the loads (5) by the following

equations:

jBB

Loaded

parts. The specific geometry depends on the operational frequency and on the guiding structure. As an example, three
classical implementationsa coaxial cable, a waveguide, and
a microstrip line, respectivelyare outlined below.
Coaxial Cable Phase Shifter

(10)

The use of Eqs. (9) and (10) allows one to design the loads
necessary to achieve a desired phase shift. Using a similar
concept, depending on the transmission line geometry, different type of loads can be devised as shown in Fig. 6. A quarterwave transformer is used to avoid reflection at the load interface. Figures 6(a) and 6(b) show realization in circular
waveguide geometry using dielectric or metallic loads, while
Figs. 6(c) and Fig. 6(d) are rectangular waveguide geometry
using dielectric loads.
MECHANICALLY TUNED PHASE SHIFTERS

In a coaxial cable the dominant mode is TEM (see ELECTROMAGNETIC FIELD MEASUREMENT) (6) so the phase of the signal
propagating over a length between two cable ends points is
given by
=

r
x
c

(11)

where x is the cable length, is the operating frequency, r is

the dielectric constant of the inner core of the cable, and c is
the speed of light in free space. A x change in its length will
produce a change in phase () between the two cable points
end expressed by

;;;;;;
;;;;
;;
;;
yy
;;
yy
;;;
;;yy
yy
;;

=

Mechanically tunable phase shifters are capable of varying

the signal delay in a transmission line using some moving

r

x
c

(12)

Figure 7 illustrates a section view of this type of phase

shifter. To allow for the stretch, the coaxial cable has concentric air lines which can slide one into another, maintaining
the characteristic impedance of the cable constant while
changing length.
Waveguide Phase Shifter

Dielectric
slab
Impedance
transformer
(a)

Metal
plates

In waveguide geometry, one way of obtaining a tunable phase

shift without changing its length is to change the effective
dielectric constant in some region of the guide, inserting a
movable dielectric slab. Figure 8 illustrates one version of this
mechanical tunable phase shifter. The insertion of the flap in

Impedance
transformer

(b)

Z0

Z0

Z0

Movable part

Sided in

Dielectric
Impedance slab
transformer
(c)

Section view

Dielectric load

Coaxial section

(d)

Figure 6. Different types of loaded transmission line.

Coaxial section

Side view

Figure 7. Mechanically tuned coaxial phase shifter.

yy
;;
Dielectric slab

Narrow slot

TE10

Figure 8. Mechanically tuned waveguide phase shifter.

the center of the waveguide, where the electric field is maximum assuming that the fundamental mode is propagating,
will delay the signal, producing a phase shift. This type of
device is only usable with some restrictions, since the thickness of the flap and its dielectric constant must be calculated
to avoid the propagation of higher-order modes (i.e., TE30). A
simple equation for the design of this type of phase shifter,
which avoids higher modes, was proposed by Gardiol (7) and
leads to the following relation:

r tan[ (a d)/c ] = cot( r d/c )

(13)
Based on the same concept, it is possible to have a movable
dielectric inside a rectangular waveguide operating with the
fundamental mode TE10 as shown in Fig. 9, where the interaction of the field with the dielectric will be maximum when the
plate is in the center of the guide (maximum delay corresponding to maximum phase shift) and minimum when it is
on the side walls. Proper design of the /4 transformer (8) is
necessary to avoid reflections at the phase shifter interface.
Microstrip Phase Shifter
For the microstrip geometry a mechanically tuned phase
shifter was proposed by Joines (9). In this geometry it is possible to achieve a phase shift by changing the dielectric constant of the substrate above and below the strip as depicted
in Fig. 10.
The change in the dielectric constant will induce a change
in the propagation constant, and consequently different phase
shifts will be achieved. This structure is attractive because it
yields a continuous phase shift while maintaining the characteristic impedance constant. If we observe its section view depicted in Fig. 10, we notice that by a proper design of the
thicknesses t1 and t2, accordingly with the dielectric constant
(9), it is possible to keep the characteristic impedance of the
strip constant while changing its propagation constant.

yy
;;
;;
yy

Moving screw

Movable slab

Figure 9. Dielectric loaded rectangular waveguide phase shifter.

PHASE SHIFTERS

203

These are just a few examples of mechanically tunable

phase shifters; of course, many others are possible, but the
basic concept on which they operate is the same and can be
summarized as follows. In order to obtain a phase shift, it is
necessary to delay the electric signal independently from the
type of guiding structure used. This can be achieved in two
ways: One way is to change the physical length of the transmission line x which produces a delay of the signal at the
output port, inducing a phase shift change given by
x. In the second case, a change of the wave propagation
velocity obtained by changing the propagation constant of the
line will produce a phase shift at the output port given by
x.
ELECTRICALLY TUNED PHASE SHIFTERS
In electrically tuned phase shifters the phase change is controlled by an electric signal (driving signal) such as a voltage
or a current. Since no moving parts are involved in the phase
control process, electrically controlled phase shifters can
achieve faster phase shift compared to mechanical ones. They
can be subdivided into two major categoriesdigital and analogdepending on the type of control on the phase shift they
provide. One of the most important application of electrically
tuned phase shifters is the so-called phased array system. A
phased array system is an array of antennas of which by electronically controlling the phase of the electromagnetic signal
at each antenna element one can change its pointing direction. As an example, let us consider a linear array of antenna
as illustrated in Fig. 11. If all the elements are excited with
the same phase signal, the radiated signal adds coherently
and forms a wave front parallel to the array direction (line
joining all the elements). The beam pointing direction is perpendicular to the wave front, so the radiated beam will point
in a broadside direction. In a phased array, this direction is
adjustable by acting on the phase of the electromagnetic signal at the aperture of each radiating element. In a linear
array with equispaced elements the beam can be steered by
introducing a progressive phase shift between successive elements. If 0 is the scan angle with respect to the broadside
direction, then the phase delay to be introduced between adjacent antenna apertures can be calculated from

=

d sin 0
c

(14)

where d is the element spacing, and c is the free space light

speed. For scanning the beam continuously, is varied by
analog phase shifters; and for switching the beam from one
scan angle to another, is varied in discrete steps by digital
phase shifters. The same principle applies to planar array for
achieving three-dimensional scanning and switching.
Digital Phase Shifters
Digital phase shifters use electronic devices such as pin diodes or FETs as switching elements; this allows the digital
phase shifter to direct the microwave signal through paths of
different length, obtaining in this way the phase shift. The
use of a pin diode as a switching circuit allows biasing of the
diode forward (to obtain a trough) or reverse (to obtain a open
circuit) by means of a dedicated bias circuitry. In a similar

204

PHASE SHIFTERS

;;
;;
;
;;
;;;
;;
t

C'

GND

Section CC'

B'

t2

r2

A
r(2)
r2
r(1)
r1

A'

Rotating
dielectric
disk

Dielectric slab

Figure 10. Microstrip mechanical tuned

phase shifter.

Microstrip line

Top view

way, an FET channel can be switched on or off by proper bias

(10). The use of FETs and diodes allows four basic designs.
The simplest one is shown in Fig. 12, where the shift is obtained by switching the signal between two different length
transmission lines; Fig. 12 also shows a microstrip implementation of this type. The phase shift is proportional to the difference between the length of the two lines and is given by
x. In a similar way, as shown in Fig. 13, the use of
different loads on the transmission lines, which are switched
on and off by the diodes, allows a phase change between the
biased and unbiased condition () related to the impedance
of the line (Z0) and to the susceptance of the loads (B) according to the relation (5)

= 2 arctan

Bn
1 B2n /2

(15)

where Bn Z0B. A microstrip implementation of this circuit

is also shown in Fig. 13; the reactive and inductive loads are
obtained using open stubs of different length, and their values
can be calculated for a given susceptance using (11)
B = ZS cot

2 f 
c

lS

Rotation axis

(16)

where Zs is the stub impedance, f is the operation frequency,

r is the relative dielectric constant, ls is the stub length, and
c is the speed of light in free space. Another design using a
pin diode in combination with a 90 hybrid circuit is illus-

Rotation disk

r1

Section AA'

t2

Rotation axis

r2

Rotation disk

r1

Section BB'

Side view

trated in Fig. 14. In this case the differential phase shift obtained between the biased and unbiased condition is given by

=

x
2

(17)

The bias circuit must be designed carefully here, in order to

avoid degradation of performance and direct-current (dc)
leaks. The bias circuit must allow biasing of all the active
devices independently, while insulating the dc biasing signal
from the radio-frequency (RF) signal. A simple design for a
microstrip topology is illustrated in Fig. 15. The two dc blocks
are acting as series capacitors for the RF signal, allowing the
RF to go through the diode while stopping the dc component
from the rest of the circuit. The two /2 high-impedance microstrip lines are operating as an open stub (11). At the microstrip junction they will result in an open circuit transparent to the microwave signal while allowing the dc signal to
provide the necessary bias for the diode. The high impedance
of the open stub makes it look like an open circuit for a larger
bandwidth (11).
The use of FETs as a switching element is similar to that
of the pin diode: The source and drain are grounded (only for
the dc signal). In the off state, the gate-source and the gatedrain capacitances are equal. Because of this, the drain is not
isolated from the gate terminal. In real circuits, the bias network is configured so as to provide high impedance for the RF
at the gate terminal. This is achieved by using a low-pass
filter such that it presents an effective RF open at the gate.
This arrangement is shown in Fig. 16.

PHASE SHIFTERS

205

Beam direction

00

Equiphase front

Antenna

Phase
shifter
Power
splitter

RF signal
input

Figure 11. Beam-steering concept using

a phase shifter at each radiating element.

x1
Bias line

;;;
;;;;;;
;;;;

RF input

RF output

x2

x1

x2

Pin diode

Bias line

RF output

Figure 12. Pin diode type of electrically

controlled digital phase shifter.

206

PHASE SHIFTERS

/4

Common bias

;;;; ;;
;;;;;
;;;;;
Bias line

RF input

RF output

jB

jB

jB

jB

Bias line

Pin diode

RF input

Figure 13. Loaded pin diode electrically

tuned digital phase shifter.

RF output

/4

Dc blocking
capacitor

Common bias

3 dB, 90
Hybrid coupler

RF input

x/2

0
0

Bias line

RF GND

90
x/2

90

;;
;;
;;;
;;;;

RF output
Figure 14. Pin diode and 90 hybrid circuit type of electrically controlled digital
phase shifter.

Bias line

RF GND

Pin diode

RF input

RF output

/2

Dc block

2 k

Figure 15. Bias circuit for pin diode type

of phase shifter.

Bias

2 k

;;;;
RF input

RF output

Low-pass
filter

Bias
Figure 16. Bias circuit for an FET type of phase shifter.

PHASE SHIFTERS

207

Analog Phase Shifters

Analog phase shifters allow time delay control of a microwave
signal by using an electric driving signal. They differ from
digital phase shifters due to their capability to provide continuous phase delay control. This characteristic is very attractive
when a fixed phase resolution is impractical to use. Consider
as an example the received signal coming from a broadcast
TV, as illustrated in Fig. 18. Because a multiple reflection
path exist, a double image is received. One possible solution
to overcome the problem is to use two receiving antennas and
by proper adjustment of the phase difference between them
eliminate the reflected signal. Because of the random nature
of the delay, only a continuous adjustable phase shifter can
be employed.
Electrically analog tunable phase shifters can be subdivided in three major subcategories as illustrated in Fig. 2. A
description of the operational principle for each of them is
provided below.
Ferrite Phase Shifters

Because digital phase shifters only allow discrete phase

jumps, a cascade of them must be used when high resolution
in the phase change is desired. Figure 17 shows a typical arrangement and the corresponding phase shift states for a
4-bit phase shifter, capable of giving phase jumps with an
increment of 22.5 and a maximum phase shift of 360. By
increasing the number of phase shifters, higher resolution is
achievable. The maximum achievable resolution will obviously depend on the number of phase shifters and is expressed by the relation

min

2
= n
2

(18)

where n is the number of discrete phase shifters.

22.5

Input
signal

MO + Fe2 O3

90

180

0
S3

Switch state
S1 S2 S3 S4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Output
signal

0
S2

(19)

where M is a divalent metal such as manganese, magnesium,

nickel, or iron. They exhibit a hysteresis BH dependence as
reported in Fig. 19. To explain how ferrites are used in phase
shifters, it is not necessary to describe in detail the material
properties which are well documented in Refs. 12 and 13. The

45

S1

Ferrite phase shifters are employed in a waveguide or a planar structure. They operate using the ferrite property of nonlinear dependence between magnetization (B) and magnetic
field (H). Ferrites are nonlinear and nonreciprocal magnetic
materials composed of a mixture of divalent metal and iron
oxide having the general chemical structure

0
S4

Phase shift
0
22.5
45
67.5
90
112.5
135
157.5
180
202.5
225
247.5
270
292.5
315
337.5

Figure 17. Diagram of 4-bit phase shifter and corresponding switching scheme.

S2

208

PHASE SHIFTERS

Broadcast TV

Direct ray

;;
;

Magnetic
field lines

Multiple path
reflection

Single image

Figure 18. Phase shift recovering for a multiple path reflected

signal.

nonlinear H dependence will be exhibited as shown in Fig.

19. The permeability at specific magnetization value (H*) can
therefore be calculated as
= 0 +

B
B
H
H

Biasing
wire

Figure 20. Nonreciprocal waveguide ferrite phase shifter.

Multiple image

Ferrite
slabs

(20)
H=H

achieved using a current loop around the ferrite slab (with

the aid of a biasing wire). The ferrite is placed in the waveguide in such a way to maximize the interaction with the existing magnetic field in the guide. For waveguide operating
with the fundamental mode (TE10), the magnetic field will be
maximum at 
and  of the longitudinal section of the guide
(6) as illustrated in Fig. 20. Because the magnetic field has
opposite direction at those sections, an asymmetrical bias (see
Fig. 20) will be necessary in order to obtain a phase shift.
This is done using a current flowing in the two wires in opposite direction. Another concept is to use different geometries
as illustrated in Fig. 21. The cross section depicted in Fig.
21(a) is an extension of the one shown in Fig. 20, with the
difference being that the ferrite is placed where the maximum
magnetic field exists at the bottom and top of the guide. This
allows a reduction of the mismatch with the empty waveguide, making easier the design of the matching circuit. Also
in this case as illustrated in the figure, a differential bias of
the ferrite must be used. Figure 21(b) is also based on a simi-

;;
yy
yy
;;
;;
yy
;;
yy
Ferrite

In general the ferrite permeability takes the form of a tensor

because of the nonreciprocal behavior. The elements of this
tensor are a function of the applied magnetic field. When the
magnitude or direction of the magnetic field is changed, the
permeability of the ferrite changes, thereby changing the
propagation constant of the electromagnetic wave. Phase shift
is a consequence of the change in the propagation constant
brought about by electronically controlling the applied magnetic field. For a more extensive and complete treatment of
ferrite properties at microwave frequencies, see Refs. 14 and
15. As direct application of this concept, a waveguide ferrite
loaded phase shifter is described. The geometry of the device
is shown in Fig. 20, the magnetization of the ferrite is

External
magnetization

(a)

Ferrite

(b)

* = 0 +

B
H

Ferrite

H = H*

H*

H*

(c)

Figure 19. Nonlinear BH dependence and correspondent H dependence.

Figure 21. Different types of nonreciprocal waveguide ferrite phase

shifter.

yy
;;
;;
yy
;y;y
yyy
;;;
Biasing wires

Ferrite
rod

Dielectric
support

Impedance
transformer

Ferrite rod

Biasing wires

Dielectric support

Figure 22. ReggiaSpencer reciprocal ferrite phase shifter.

lar concept; but the asymmetrical bias is replaced by an

asymmetric geometry, so the ferrite is only placed on one side
of the guide. Further improvement toward the matching for
this structure is obtained in the case of Fig. 21(c). Several
versions of a planar structure which employ ferrites as tunable elements have been proposed (1618). Even though in
principle those structures work, most ferrite phase shifters
currently constructed use waveguide geometry.
Another operational principle for the ferrite reciprocal
phase shifters is to use Faraday rotation to produce time delay of microwave signal. This type of phase shifter was at first
proposed by Reggia and Spencer (19) and is illustrated in Fig.
22. Several modifications of the original form were proposed
later, but the basic operative principle remains the same. In
this phase shifter a longitudinal ferrite toroid is placed in the
longitudinal section of a rectangular waveguide (see Fig. 22).
The magnetic biasing field is produced by an external magnetization circuit. It is well known that when a linearly polarized wave propagates in a ferromagnetic rod, the plane of polarization of the wave in the rod rotates. Now if the rod is
placed inside a rectangular waveguide with one of its dimension at cut-off, then the rotational effect is suppressed (for
small size rod). Reggia and Spencer have demonstrated large
changes in insertion phase with external magnetic field bias
for the transmitted power. They also demonstrated that the
phase variations are independent of the propagation direction. Many other authors investigated the theory beyond this
effect (20,21). Practical design of the ReggiaSpencer phase
shifter is mostly based on approximate equations (22) which
consider the phase shift as a consequence of a small perturbation in the effective permeability.
Ferroelectric Phase Shifters
In ferroelectric phase shifters the phase-shift capability of ferroelectric materials results from the fact that if we are below
their Curie temperature (23,24) (see FERROELECTRICS), the dielectric constant of such a material can be modulated under
the effect of an electric bias field. Particularly, if the electric

PHASE SHIFTERS

209

field is applied perpendicularly to the direction of propagation

of the electromagnetic signal, the propagation constant (
2/ ) of the signal will depend upon the bias field since
2r / 0 and r r(Vbias). The total wave delay will become a
function of the bias field, and therefore this will produce a
phase shift l, where l is the length of the line. Two
major implementations of a ferroelectric phase shifter have
been used: waveguide geometry and planar structures. In
waveguide geometry the ferroelectric material is placed inside
a waveguide as illustrated in Fig. 23. A voltage is applied to
the center conductor, creating a vertical electric field to the
grounded flange. The matching layer must be placed on either
side of the sample to couple the RF energy in and out of the
material. These rectangular layers of dielectric are needed in
the design of the phase shifter because of the impedance mismatch between air and the high permittivity ferroelectric.
One problem in the use of this type of setup is the high bias
required (typically 1 kV to 2 kV) due to the thickness of the
material. Ferroelectrics require a bias voltage of the order 2
V/m to 4 V/m in order to change significantly their dielectric constant (25,26).
Use of the planar type of ferroelectric material in microstrip geometry avoids this problem as demonstrated in Ref.
27. The geometry is illustrated in Fig. 24. The active part of
the device consists of a microstrip line printed on a ferroelectric substrate whose dielectric constant is changed by bias.
The length of the strip determines the maximum phase shift
achievable for a fixed change of the propagation constant
(), associated with the maximum bias voltage. The complete design of this type of phase shifter is reported in Ref.
28. To reduce the required bias the ferroelectric material has
a thickness of the order of 0.1 mm to 0.2 mm, allowing bias
voltage of a few hundred volts. As in the case of the pin diode
phase shifter, attention must be dedicated to the design of
the biasing circuit, to avoid leakage of the dc voltage in the
RF circuit.
Varactor Diode Phase Shifter
In varactor diode phase shifters a varactor diode is used as
a variable-capacitance element. This variable capacitance is
obtained through a voltage-tuned capacitance of the diode under a reverse-bias condition (24). The varactor diode is used
in combination with a hybrid coupled circuit as illustrated in
Fig. 25(a). The 3 dB 90 hybrid circuit is symmetrically terminated with the diodes. If X is the reactance of the diode, the
reflection coefficient can be calculated as (11)

jX /Z0 1
jX /Z0 + 1

(21)

and the corresponding phase of the reflection coefficient is

given by
= 2 arctan(X /Z)

(22)

where Z0 is the characteristic impedance of the transmission

line (50 typically). We notice that in order to obtain a phase
variation in the range going from 0 to 2, the reactance of the
diode must go from to 0 to and the maximum change
of phase is obtained when X 0. Hence, in order to obtain a
maximum phase shift, the diode must be connected in series
with an inductive load to allow resonance (X 0); this can be

210

yyy
;;;
;;;
yyy
;;;yyy
yyy
;;;

PHASE SHIFTERS

Ferroelectric
Biasing
material
electrode
Section view

Figure 23. Waveguide ferroelectric type

of analog phase shifter.

achieved with a stub as illustrated in Fig. 25(b) for a microstrip realization. The impedance of the reflecting termination
(diode and stub) is given by

Z = Rd + j ZS tan lS

1
Cd

1
1

Cdmin
Cdmax

X 
2Z0

Top view

(27)

1 Rd /Z0

|
|deg

(28)

dB

A possible improvement of the presented structure can be obtained using two series varactor diodes as presented in Ref.
29. The operational principle remains the same, but a larger
change in the capacitance is obtained.

RF output

jX

(26)

;;
yy
;y;yy
y;;
Connection
pads

The figure of merit (F) for the analyzed structure is calculated

as

3 dB, 90
Hybrid coupler

Ferroelectric
substrate

jX

RF input

(a)

Side view

Ferroelectric
material

d /Z0

(25)

For such change of X the correspondent phase change can be

obtained as

Microstrip line

1 + R

(24)

As the bias voltage changes from 0 to a negative value, Cd

goes from Cdmax to Cdmin, giving a change of X expressed by

|
| = 4 arctan

dB = 20 log10

F=

R Z0 + jX

= d
Rd + Z0 + jX

X =

Side view

Also at X 0 (resonance condition) a maximum insertion loss

due to Rd will occur. The corresponding attenuation in this
circumstance is

(23)

where Rd and Cd are the equivalent parameters of the diode,

and Zs and ls are the stub characteristic impedance and
length, respectively. The associated reflection coefficient is
calculated from

Matching
layer

RF output

jX

lS

Ground plane

Bottom view

Figure 24. Microstrip ferroelectric type of analog phase shifter.

ZS
3 dB, 90
Hybrid coupler

RF input
(b)
Figure 25. Varactor-based tunable phase shifter.

PHASE SHIFTERS

RF input

RF output

Figure 26. Active FET type of phase shifter.

Active Phase Shifter

Use of FET in an analog phase shifter (30) allows one to take
advantage of the gain of the FET at microwave frequencies,
while producing the time delay at the same time. Figure 26
shows the topology of this kind of phase shifter. The phase
variation in the transmission coefficient (S21) is achieved by
controlling the bias voltage at the gate of the FET. The bias
voltage is applied on the second gate of the FET, while a fixed
inductive load is connected to it. The bias voltage will change
the capacitance between the first gate (G1) and the source,
and this will change the amplitude and phase of the S21. One
limitation of this topology is the narrow bandwidth which is
achieved. Use of more complicated topologies as reported in
Ref. 31 will allow larger bandwidth and larger phase shifting capabilities.

ACKNOWLEDGMENTS
The author wishes to thank Professor N. G. Alexopoulos of
the Electrical and Computer Engineering Department at the
University of California, Irvine, for useful suggestions.

BIBLIOGRAPHY
1. M. Sucher and J. Fox, Handbook of Microwave Measurements,
New York: Polytechnic, 1963.
2. G. D. Vendelin, A. M. Pavio, and U. L. Rohde, Microwave Circuit
Design Using Linear and Nonlinear Techniques, New York:
Wiley, 1990.
3. R. E. Collin, Foundations for Microwave Engineering, New York:
McGraw-Hill, 1966.
4. R. E. Collin, Field Theory of Guided Waves, 2nd ed., New York:
IEEE Press, 1991.
5. R. Winnery and V. Durez, Campi e Onde nell Elettronica per le
Comunicazioni, Milan: 1984.
6. C. A. Balaniis, Advanced Engineering Electromagnetics, New
York: Wiley, 1989.
7. F. E. Gardiol, Higher order modes in dielectrically loaded rectangular waveguides, IEEE Trans. Microwave Theory Tech., MTT16: 919924, 1969.

211

10. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, New York: Wiley, 1993.
11. G. Gonzalez, Microwave Transistor Amplifiers, Englewood Cliffs,
NJ: Prentice-Hall, 1984.
12. G. P. Rodrigue, Magnetic materials for millimeter wave applications, IEEE Trans. Microw. Theory Tech., MTT-11: 351356,
1963.
13. J. Smith and H. P. J. Wijn, Ferrites, New York: Phillips Technical Library, 1959.
14. G. L. Matthaei, L. Young, and E. M. T. Jones, Microwave Filters,
Impedance Matching Networks, and Coupling Structures, Dedham, MA: Artech House, 1980.
15. J. J. Green and F. Sandy, Microwave characterization of partially
magnetized ferrites, IEEE Trans. Microw. Theory Tech., MTT-22:
641645, 1974.
16. R. R. Jones, A slow-wave digital ferrite strip transmission line
phase shifter, IEEE Trans. Microw. Theory Tech., MTT-14: 684
687, 1966.
17. L. R. Whicker and R. R. Jones, A digital latching ferrite strip
transmission line phase shifter, IEEE Trans. Microw. Theory
Tech., MTT-13: 781784, 1965.
18. W. M. Libbey, Characteristic of a microstrip two meander ferrite
phase shifter, IEEE Trans. Microw. Theory Tech., MTT-21: 483
487, 1973.
19. F. Reggia and E. G. Spencer, A new technique in ferrite phase
shifting for beam scanning of microwave antennas, Proc. IRE, 45:
15101517, 1957.
20. P. A. Rizzi and B. Gatlin, Rectangular guide ferrite phase shifter
employing longitudinal magnetic fields, Proc. IRE, 47: 1130
1137, 1959.
21. W. E. Hord, F. J. Rosenbaum, and C. R. Boyd, Theory of the
suppressed-rotation reciprocal ferrite phase shifter, IEEE Trans.
Microw. Theory Tech., MTT-16: 902910, 1968.
22. K. J. Button and B. Lax, Perturbation theory of the reciprocal
ferrite phase shifter, Proc. IRE, 109B: 1962.
23. M. E. Lines and A. M. Glass, Principles and Applications of Ferroelectrics and Related Materials, Oxford, UK: Clarendon Press,
1977.
24. C. Kittel, Introduction to Solid State Physics, New York: Wiley,
1986.
25. T. Mitsui and S. Nomura, LandoltBornstein: Numerical data
and functional relationship in science and technology, Ferroelectr.
Related Substances, 16: 1981.
26. R. Pepinsky, Physics of Electronic Ceramics, New York: Dekker,
1972.
27. F. De Flaviis et al., Ferroelectric materials for microwave and
millimeter wave applications, Proc. SPIE, Smart Structures and
Materials, 2448: 921, 1995.
28. F. De Flaviis, O. M. Stafsudd, and N. G. Alexopoulos, Planar microwave integrated phase shifter design with high purity ferroelectric materials, IEEE Trans. Microw. Theory Tech., 45: 963
969, 1997.
29. B. T. Henoch and P. Tamm, A 360 reflection type diode phase
modulator, IEEE Trans. Microwave Theory Tech., MTT-29: 103
105, 1971.
30. C. Tsironis and P. Harrop, Dual gate GaAs MESFET phase
shifter with gain at 12 GHz, Electron. Lett., 16: 553554, 1980.
31. M. Kumar, R. J. Menna, and H. Huang, Broadband active phase
shifter using dual-gate MESFET, IEEE Trans. Microw. Theory
Tech., MTT-29: 10981102, 1981.

8. N. Marcuvitz, Waveguide Handbook, London: Peregrinus, 1986.

FRANCO DE FLAVIIS

9. W. T. Joines, A continuously variable dielectric phase shifter,

IEEE Trans. Microw. Theory Tech., MTT-19: 729732, 1971.

University of California at Los

Angeles

212

See

PHASE SHIFT KEYING

also

SHIFTERS.

FERRITE

PHASE

SHIFTERS;

MICROWAVE

PHASE

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

PREAMPLIFIERS
The essential task of sensors, detectors, and transducers is to convert the characteristics of the physical
world (e.g., light, sound, pressure, displacement, temperature) into electrical signals, which are then suitably
processed for the required application. Before being processed, these electrical signals must be conditioned by
appropriate electronic circuitry.
Despite the improvements carried out in recent years, all sensors have a common characteristic: a weak
signal delivered and a limiting noise level. Therefore, the front end of the sensor-associated electronic system
must be an amplifier, usually called a preamplifier. Two main requirements must be satisfied for preamplifiers.
First, they must raise the signal level adequately over a certain frequency range (linear amplification is very
often requested). Second, they must contribute only a minimum amount of additional noise. Depending on
the specific application, other features such as high linearity, large output swing, wide-band operation, and
large output drive capability may be needed, but these requirements do not differ substantially from those of
normal amplifiers. What is specifically important for preamplifiers is to optimize their noise performance. This
is because, although the noise performance of a generic electronic system [which is made up of a preamplifier,
signal conditioning and processing circuitry, and output interface (Fig. 1)] depends on the noise behavior of all
these subsystems, in practice, in a well-designed system the noise performance is entirely dominated by the
noise characteristics of the front-end circuit (preamplifier). This is true if the preamplifier gain is sufficiently
high to allow the subsequent processing to be performed with negligible degradation in the signal-to-noise
ratio. Hence, low-noise system design is mainly focused on low-noise preamplifier design.

Basic Concepts Related with Preampliers

Some basic concepts useful in analyzing preamplifiers from the noise standpoint, namely, equivalent input
noise, noise factor and noise figure, and noise matching, are introduced in this section.
Equivalent Input Noise. In the characterization of many nonideal electrical quantities, which are
generated by a plurality of sources or mechanisms within a circuit, it is a common practice to replace all by one
equivalent input source. This equivalent source has the same effect at the circuit output as the global effect of
all the individual internal sources and, therefore, the circuit can be considered free of such mechanisms (1),
which greatly simplifies circuit analysis and design. Offset voltage and noise are representative examples of
what has been discussed.
A network, such as an amplifier, is made up of many components. Any electrical component has its own
internal mechanisms of noise generation. As a result, the output of any real amplifier exhibits noise, which
depends on factors such as internal noise sources, circuit topology, gain, and measurement bandwidth. The
amplifiers output noise power spectral density can be found by multiplying the noise power spectral density of
each source by the squared module of its particular transfer function and then superposing all the individual
noise contributions. This procedure must be followed for any frequency of interest.
1

PREAMPLIFIERS

Fig. 1. The electronic chain associated with a sensor includes a preamplifier, signal conditioning and processing circuitry,
and output interface. The stages cascaded to the preamplifier may provide additional gain.

Rather than by the noise measured at its output, an amplifier is best characterized by the minimum
signal applied to its input, which is still detectable at the output of the signal processor. This signal may be
conveniently regarded as equivalent to a virtual noise source located at the input. This is known as equivalent
input noise or input-referred noise of the amplifier, and allows one to easily compare the total noise generated
by the amplifier with the input signal. From the above considerations, the equivalent input noise power of an
amplifier coincides with the output noise power divided by the squared module of the amplifier gain (2).
A similar idea is applied to the noise model of a generic sensor. Starting from its small-signal equivalent
circuit, including all impedances and current/voltage signal generators, a noise equivalent circuit is derived
by including the noise sources associated with resistances (or, better, with the real parts of impedances) and
signal generators. From this equivalent noise circuit, an expression for small-signal gain and equivalent input
noise is derived.
Figure 2(a) represents the equivalent noise circuit of a generic system consisting of a sensor and a
preamplifier. The sensor is described by its signal voltage generator V s , its internal series impedance Zs , and
a noise voltage generator, V n,s , which includes the contributions by all sensor noise sources. The preamplifier,
having voltage gain Av and input impedance Zi , is represented from the noise point of view, by a noise voltage
generator V n,a and a noise current generator In,a placed in series and in parallel, respectively, with the input
port. These noise generators, whose magnitude is specified in units of V/(Hz)1/2 and A/(Hz)1/2 , respectively,
are in general, frequency dependent, and are very often represented in terms of their mean square voltage,
V 2 n,a (V 2 /Hz), and mean square current, I2 n,a (A2 /Hz). The two generators can be statistically correlated or
not, depending on the specific case. For example, they are practically 100% correlated and totally uncorrelated,
respectively, when modeling a metal-oxide-semiconductor (MOS) field-effect transistor or a bipolar junction
transistor (BJT) in the mid-frequency range (3). When combining the effects of different noise sources, one
must remember that noise is a random signal. Therefore, when summing two noise variables An and Bn , the
result is C2 n = A2 n + B2 n + 2 Re{A n Bn }, where Re{A n Bn } represents the real part of the cross-correlation
spectrum of An and Bn . For ease of use, the correlation effect between two variables is very often expressed
by using the so-called correlation coefficient , which is a normalized factor having a value between 0 (no
correlation) and 1 (100% correlation). Using this approach, one has C2 n = A2 n + B2 n + 2An Bn .
Although the number of noise sources in Fig. 2(a) has been reduced to three, further simplifications are
usually carried out to represent them just by one equivalent input noise voltage generator, V n,eq , at the signal
source location (2). To derive an expression for the equivalent input noise, the total noise at the amplifier

PREAMPLIFIERS

Fig. 2. A generic system noise model (a) can be reduced to an equivalent circuit with an equivalent input noise voltage
generator (b), or to an equivalent circuit with an equivalent input noise current generator (c).

output, V n,o , must be first derived. Assuming V n,a and In,a to be statistically uncorrelated, one obtains:

The system gain from the signal source location is

PREAMPLIFIERS

Therefore, the equivalent input noise voltage, V n,eq , which is equal to the total output noise divided by the
squared module of the system gain, is given by;

After combining and reflecting all noise sources to the signal source location, the resulting equivalent circuit
is shown in Fig. 2(b). The noise source V n,eq will generate exactly the output noise given by Eq. (1).
V 2 n,eq can also be obtained from Fig. 2(a) by disconnecting the noiseless amplifier and evaluating the
voltage across the noise generator In,a , which results in Eq. (3). This operation corresponds to finding the
equivalent dipole connected at the input of the noiseless amplifier (Thevenin theorem). In practice, the dipole
in Fig. 2(a) constituted by V s , V n,s , Zs , V n,a , and In,a , is exactly equivalent to the dipole in Fig. 2(b) constituted
by V s , V n,eq , and Zs .
Observe that, as indicated in Eq. (3), the equivalent input voltage noise does not depend on the amplifier
gain and input impedance, although the effect of any noise generated at Zi is implicit in In,a . However, V n,eq
depends on the impedance of the signal source, as well as on the noise generated by the sensor (hence, the
design approach for noise optimization will also depend on the kind of sensor impedance, that is resistive,
capacitive, inductive, as will be shown below). Output noise will obviously depend on both the gain and the
input impedance of the amplifier.
Following similar steps, an equivalent noise circuit of the system can also be derived in terms of an
equivalent input noise current generator In,eq [Fig. 2(c)]:

where I2 n,s = V 2 n,s /|Zs |2 .

Either equivalent noise circuit can be used, however, it is generally more appropriate to characterize the
system noise in the same terms as the source signal (voltage or current).
If the amplifier noise voltage and current generators V n,a and In,a are not statistically independent, as
occurs when they contain some components arising from a common phenomenon, the scheme of Fig. 2(b) must
include another noise voltage generator in series with V n,eq . The power spectral density of this generator is
a function of their correlation coefficient: V 2 n = 2|V n,a In,a Zs |. In the same way, an additional noise current
generator I2 n = 2|V n,a In,a /Zs | has to be placed in parallel with In,eq in the scheme of Fig. 2(c).
Equivalent Input Noise in Cascaded Stages. Consider the network in Fig. 3, which consists of n
cascaded stages having respective voltage gains Av1 , Av2 , . . ., Avn and equivalent input noise voltage sources
V n,eq1 , V n,eq2 , . . ., V n,eqn . It should be pointed out that a stage in this figure can be a complex circuit or even a
single active device. Moreover, for each stage i (i = 1, 2, . . ., n), Avi and V n,eqi are evaluated taking the value of
input and output impedances into account. Assuming that noise sources of different stages are uncorrelated,
as is the usual case, the total output noise power is

PREAMPLIFIERS

Fig. 3. Schematics for evaluating the noise performance of an n-stage voltage amplifier.

which corresponds to an equivalent input noise for the whole network equal to

From this equation, one concludes that the noise behavior of the whole network can be dominated by the first
stage, provided that its voltage gain is large enough. In this case, in fact, noise contributions by the following
stages can be neglected. The same conclusion also holds when considering current noise, obviously referring to
the current gain rather than to the voltage gain of the stages.
Noise Factor and Noise Figure. Noise factor F is one of the most traditional parameters used to
characterize the noise performance of an amplifier. It is defined as the ratio of the total available output noise
power per unit bandwidth to the portion of that output noise power caused by the noise associated with the
sensor, measured at the standard temperature of 290 K (4). To emphasize that this parameter is a point
function of frequency, the term spot noise factor may be used. Since the noise factor is a power ratio, it can
be expressed in decibels. In this case, the ratio is referred to as noise figure (NF). That is, taking Fig. 2 and Eq.
(3) into account,

An alternative expression for the noise figure can be derived from Eq. (7), obtaining

where (SNR)i is the signal-to-noise ratio (SNR) available at the sensor output, and (SNR)o is the SNR at the
output of the real (i.e., noisy) amplifier. The above result indicates that NF accounts for the signal-to-noise
power degradation caused by the preamplifier. Thus, for an ideal amplifier, which does not add any noise, the

PREAMPLIFIERS

output signal-to-noise ratio is kept equal to its input counterpart, and NF = 0 dB. Alternatively, an NF of 3 dB
means that half the output noise power is due to the amplifier.
As will be shown later, NF by itself is not always an appropriate figure of merit to characterize the
noise performance of an amplifier. As stated above, NF is only valid to indicate how much noise is added by a
preamplifier to a given input source resistance, and is therefore useful to compare noise behavior of different
preamplifiers with a determined signal source. However, it is not a useful tool for predicting noise performance
with an arbitrary source.
Noise Matching. Let us consider now the particular case where the internal impedance of the signal
source is a resistor Rs . This corresponds to one of the most frequently used types of sensors, which can be
represented by a signal source generator V s in series with its internal resistance and a thermal noise generator
V n,s , whose power spectral density is:

where K is Boltzmanns constant (1.38 10 23 Ws/K) and T is the absolute temperature (K). According to Eq.
(7), the noise figure for this resistive signal source is given by

By differentiating this expression with respect to Rs , one obtains the so-called optimum source resistance, for
which NF is minimum:

From Eqs. (10) and (11), NF can be written as

in which M = Rs /Ropt is the matching factor. For a given V n,a In,a product, NF is minimum for M = 1.
The effect of the source resistance variation on NF for amplifiers having different values of the noise
sources product V n,a In,a , is illustrated in Fig. 4 [p. 46 in Ref. 2.]. The minimum value of the noise figure,
NFopt , occurs at Rs = Ropt . As the product V n,a In,a increases, the noise figure also increases and is more
sensitive to source resistance variations.
In the more general case where the correlation factor, , is different from zero, the optimum value, F opt ,
of the noise factor corresponding to the optimum source resistance is easily calculated as

F opt defines the best performance obtainable when the source resistance can be selected to match Ropt . Eq. (13)
also clearly shows that, for any given source resistance and temperature, the best noise performance, obtained
when perfect matching is achieved, depends on the product V n,a In,a of the amplifier (5,6).

PREAMPLIFIERS

Fig. 4. NF reaches its minimum value for Rs = Ropt . NF increases with increasing value of the product V n,a In,a .

Noise matching is based on the idea of modifying the amplifier equivalent input noise sources as seen at
the signal source location, to meet the condition Rs = Ropt , so as to minimize the total equivalent input noise
(5). This condition, which indicates that the preamplifier input stage is matched to the sensor, is considered as
the essence of low-noise design. Of course, to keep the noise low, the rest of the amplifier must also be designed
so that its noise contributions are low compared with those of the input stage.
A very simple and illustrative way to modify the amplifier equivalent input noise consists of coupling the
sensor to the amplifier by means of a transformer with a primary-to-secondary turns ratio of 1:N (Fig. 5 shows

this for the case of a resistive sensor). The amplifier noise sources are reflected to the primary as V n,a = V n,a /N

and I n,a = NIn,a . The ratio of these reflected parameters is:

Matching R s to Rs , one can derive the turns ratio required in the coupling transformer:

When this condition is met, the amplifier sees the optimum source resistance and, hence, the equivalent input
noise is minimized. It has to be pointed out that a real transformer has its own internal noise sources and
stray impedances, which have to be taken into account in an accurate low-noise design. Moreover, the use of a
transformer requires a suitable shield to external electromagnetic fields, which can induce spurious currents
in the transformer itself.
According to the above results, it appears that the noise figure NF can be alternatively improved by
adding a series or shunt resistance to a given source resistance Rs (or, by correspondingly changing the sensor
resistance), to make its final value equal to Ropt . However, due to the addition of an extra resistor, the signal-tonoise ratio gets worse. On the other hand, for Rs = 0, NF goes to infinity, although the actual output noise is less
than that corresponding to any other value of source resistance, including Ropt . This contradictory situation
arises from the fact that reducing NF improves the output SNR only if the SNR at the source remains constant.

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Fig. 5. Noise matching by coupling transformer minimizes the total equivalent input noise.

This condition is not met when matching is achieved by modifying the source resistance, but it is satisfied
when using a coupling transformer. For the same reason, only when increasing sensor resistance increases
the signal proportionally, it should be modified so as to match the amplifier optimum noise source resistance.
When choosing or designing a preamplifier, the best noise performance is obtained by achieving the minimum
equivalent input noise rather than the lowest noise figure.
Noise matching can also be achieved in the case of narrow-band signal sources. By exploiting the resonance
of a suitable LC group, the amplifier equivalent input noise as seen at the signal source location, can be
optimized at the required center frequency. It is possible to follow this approach for both resistive and reactive
narrow-band sources (6).
Since transformers, as well as other coupling techniques using discrete components, are not compatible
with solid-state circuits, noise matching for monolithic preamplifiers has to be obtained by appropriate choice of
transistor sizes and bias conditions (7). In particular, when V n,a is the dominant noise source of the preamplifier,
noise matching can be obtained by using n input transistors connected in parallel rather than a single input
transistor. Indeed, this technique reduces input noise voltage by a factor of
and increases input noise
current by the same factor, which from the noise standpoint, is equivalent to using a coupling transformer with
a turns ratio of 1:
(5). Similar techniques can also be adopted for discrete preamplifiers, even though much
less flexibility is obviously available.

Design Considerations for Preampliers

Designing or selecting a preamplifier for a specific application involves many specifications and choices. The
procedure starts by considering sensor characteristics, such as signal source type, noise, impedance, and
frequency response. As a function of that, the preamplifier must be designed so as to achieve the lowest value
of equivalent input noise.
According to the above discussion, the ultimate limit of equivalent input noise is determined by the sensor
impedance Zs and the amplifier noise generators, V n,a and In,a , where all these parameters may generally be
frequency dependent. Therefore, the signal source impedance and frequency range are decisive when choosing
the type of preamplifier input device, as in a well-designed amplifier, noise performance is heavily affected by
this element. To assist in this task, Fig. 6 [p. 210 in Ref. 2] can serve as a general guide. In this figure, the
different ranges of source impedance values are covered by the different types of active or coupling devices.
Low values of source resistance usually require the use of a coupling transformer for noise matching, while, for

PREAMPLIFIERS

Fig. 6. Guide for selection of input devices.

matching the highest source resistance range, the extremely low noise current In,a of field-effect transistors is
exploited.
With respect to the frequency range, in the simplest case of a resistive source, matching the amplifier
optimum source resistance Ropt to the source resistance, minimizes the equivalent input noise at a given
frequency. However, if the preamplifier must operate over a large frequency band, the designers task is to
minimize the noise integrated over this interval. Then, if the source impedance is reactive and/or the equivalent
amplifier noise sources are functions of frequency, the use of a circuit simulator is often necessary to perform
this integration over the whole bandwidth and optimize noise performance. With respect to this, it is important
to note that the preamplifier bandwidth has to match, as much as possible, the signal spectrum needed in
the specified application, since increasing the bandwidth increases the integrated output noise. Once the low
and high amplifier cutoff frequencies of the preamplifier have been adjusted, the computer analysis may show
that noise requirements are not fullfilled and, then, another operating point or different device sizes must be
chosen. In extreme cases, different amplifiers or circuit topologies must be used.
Finally, needless to say, any noise injection from external sources must be minimized. For example, in
case electrical and/or magnetic shielding has to be provided against electromagnetic interference, power supply
filtering can be required to ensure a quiet supply voltage, ground connections have to be carefully studied, noise
injection from digital sections has to be minimized. However, these considerations regard general system design,
and are not specific to preamplifier design.
Next, the above design considerations are particularized for three types of source impedances (i.e., resistive, capacitive, and inductive), with emphasis in amplifiers for monolithic implementations. For this reason,
mainly bipolar and MOS transistors will be considered as amplifier devices.
Preampliers with Resistive Sources. The simplest type of source impedance is a resistance. Among
sensors with this type of source impedance, some (i.e., voltaic sensors, such as thermocouples, thermopiles,
infrared detectors, etc.) generate a voltage signal, while others (e.g., photoconductive detectors used in optoelectronic applications) produce a current signal. Figure 7 shows two generic preamplifiers with a resistive
source (the noise sources, i.e., the resistor thermal noise generators and the equivalent amplifier input noise
generators, are also included in both schemes). In Fig. 7(a), a sensor voltage source is coupled to a voltage amplifier by means of a coupling capacitor Cc , while a resistor Rb is added for biasing the amplifier input device,
which corresponds to a very usual situation. Instead, a resistive sensor, which provides a current signal, has
been assumed in Fig. 7(b). In this case, a transimpedance amplifier is used to amplify the signal from the high
impedance source. The transimpedance gain of the amplifier, V o /Is , is determined by the feedback resistor Rf ,
provided that the loop gain is high enough.
Referring to the voltage amplifier in Fig. 7(a), a high-pass response is caused by the coupling capacitor
Cc along with the equivalent series resistance of the input network. Cc must be chosen in such way that its
reactance can be neglected in the frequency range of interest. Thus, the voltage gain in the input network is
substantially independent of frequency. Moreover, the contribution of In,a to the equivalent input noise voltage
V 2 n,eq [see Eq. (3)] results equal to (In,a Rs )2 .

10

PREAMPLIFIERS

Fig. 7. Preamplifiers with resistive sources: (a) voltage amplifier with coupling capacitor; (b) wide-band transimpedance
preamplifier.

Assuming a much higher amplifier input impedance than Rs and Rb , the equivalent input noise voltage
of the system turns out to be:

PREAMPLIFIERS

11

In the remainder of this article, the generally accepted assumption that the amplifier noise is dominated by its
input device will be adopted. In addition, single-ended input stages, which as a general rule allow the designer
to minimize the noise contribution of the amplifier, will also be assumed.
First consider the case when the input transistor is a bipolar device. Neglecting 1/f noise and frequencydependent terms in the frequency band of interest, the equivalent input noise sources can be approximated as
(6):

where rb is the base resistance, q is the electron charge, IE , IB , and IC are the dc emitter, base and collector
currents, respectively, and = IC /IB is the dc current gain. This operating region of the BJT is known as
shot noise region (2), since the shot noise mechanisms are the dominant ones. In this operating region, the
correlation effects between the input voltage and current noise sources can be usually neglected (
= 0). Here
and in the following, it shall also be assumed that the noise contribution by the base resistance is negligible,
as can be achieved with adequate layout, that is by making rb sufficiently small. The optimum noise resistance
can be expressed as a function of the design parameters of the input transistor:

The equivalent input noise of the system is minimum when the noise matching condition is fulfilled, that is
when Ropt as from Eq. (18) is made equal to the equivalent resistance of the input network, Rs Rb . This is
achieved for the following biasing collector current:

Obviously, the same result is achieved by differentiating V n,eq with respect to IC for V n,eq , as given by Eq. (16).
Replacing Eq. (19) into Eq. (16), the total equivalent input noise for the optimum biasing collector current
can be derived:

The first term, 4KTRs (1 + Rs /Rb ), is due to the thermal noise contribution of the source and biasing resistances,
while the second term, 4KTRs (1 + Rs /Rb ) 1/2 , arises from the amplifier noise. It is apparent that the noise
contributed by the amplifier is lower than the thermal noise by a factor of 1/2 . Also, the noise contribution
of the biasing resistor can always be kept lower than that of Rs , by choosing Rb > Rs . Therefore, the noise
performance of voltage amplifiers with bipolar input devices and resistive sources can be made to be dominated
by the resistive source itself, if IC can be chosen equal to IC,opt . An alternative interpretation of Eq. (19) consists
in considering the term (1 + 1/2 ) as the factor by which the preamplifier increases the thermal noise of the
source and biasing resistances. In other words, this term is the lowest value of the optimum noise factor, F opt ,

12

PREAMPLIFIERS

of a BJT working in the shot noise region used as the input device of an amplifier, which is obtained when the
value of IC,opt corresponds to a sufficiently small collector current density (2).
Very similar conclusions are obtained when considering transimpedance amplifiers with resistive sources
(3)see Fig. 7(b). Following the above procedure, one finds that the bias collector current of the input bipolar
transistor for minimum noise is IC,opt = (KT/q)1/2 /(Rs Rf ), and that the corresponding total equivalent input
noise current is I2 n,eq = [4KT/(Rs Rf )] (1 + 1/2 ). Again, in a well-designed bipolar preamplifier, noise performance can be made to be dominated by the resistive source, if Rf can be chosen sufficiently large. The choice of
the feedback resistor Rf will result as the best trade-off between noise, transimpedance gain, and bandwidth
requirements.
Now refer to the case when an MOS transistor is used as the input device of the preamplifier in Fig. 7(a).
The equivalent input noise generators of an MOS device in the mid-frequency range can be approximated as
(3):

where Af is a suitable technology-dependent constant, W and L are the width and length, respectively, of the
transistor, gm is its transconductance, and Ci its input capacitance. As the noise voltage source is placed in series
with the signal source, the only way to minimize its contribution to the total equivalent input noise voltage
V 2 n,eq is to minimize the noise source itself. To reduce thermal noise, a large transistor transconductance must
be used, which means a large aspect ratio and a large bias current. To reduce the 1/f term, a large gate area is
required. The contribution of the noise current source to V 2 n,eq is equal to V 2 n,a [(Rs Rb )Ci ]2 , and is, therefore,
negligible with respect to V 2 n,a in the frequency band of interest { < [(Rs Rb )Ci ] 1 }.
When transimpedance amplifiers in MOS technology are considered, the contribution of the term V 2 n,a
to the total equivalent input noise current is given by V 2 n,a /(Rs Rf )2 . This should be compared with the
noise current 4KT/(Rs Rf ) contributed by the source and feedback resistances. Therefore, in the presence of
a very large source resistance, the noise contribution of the amplifier can be made negligible provided that a
sufficiently large feedback resistor is used. In this case, MOS amplifiers should be preferred to bipolar ones (3).
By contrast, in the case of a small source resistance, the source V 2 n,a must be minimized to ensure low-noise
performance of the preamplifier. This can be obtained with the same techniques as seen above for the case of
the voltage amplifier. Again, the contribution due to the amplifier input current noise can be neglected in the
frequency band of interest.
Preampliers for Optical Receivers. A very popular preamplifier application is for optical receivers.
An optical receiver is a circuit able to detect and process a signal coming from an optical source. Basically,
it is made up of an optical sensor followed by a preamplifier and a processing section. The optical sensor
(photodetector), which in its simplest form, is a reversed-biased diode, converts the optical signal into an
electrical current. The photodetector is modeled as a current source with an ideally infinite output resistance
and a capacitance in parallel. As the input electrical signal can be very small (e.g., down to the nA range), it
must be amplified with a preamplifier to a level suitable for the following processing. Therefore, low noise, high
gain and, in many cases, high bandwidth and adequate dynamic range, are key amplifier requirements in this
kind of application.
The basic principle of a preamplifier for optical receivers is to convert the current signal provided by the
photodetector, Is , into a voltage signal having a suitable amplitude. The most popular configuration consists of
a transresistance amplifier, as illustrated schematically in Fig. 8(a) (8), where noise generators are not shown.
The current Is generated by the photodetector flows through the feedback resistor Rf which, in turn, produces
an amplifier output voltage V o = Is Rf , provided that the loop gain is large enough. The required current-to-

PREAMPLIFIERS

13

Fig. 8. Preamplifiers for optical receivers: a transresistance preamplifier (a) is generally preferred to the use of a grounded
resistor followed by an active stage (b).

voltage conversion can also be achieved by feeding the signal current directly to a grounded resistor Rg [Fig.
8(b)] (9). A suitable active stage is cascaded to provide decoupling between the input section and the following
stages and, in this case, additional voltage gain. The choice of Rg results as a tradeoff between gain (V o /Is ) and
low thermal noise added to the signal current (4KT/Rg ) on the one hand, and bandwidth, which is limited to
1/(2Rg Cp ), on the other, where Cp includes the photodetector capacitance in parallel with the amplifier input
capacitance. For this reason, an equalizer stage (substantially, a parallel group RC) is very often cascaded to
the active stage when Rg has a large value (9). The use of a large Rg also causes a limited input dynamic range,
as the whole voltage signal Rg Is , is applied to the input of the active stage.
The transresistance configuration of Fig. 8(a) provides the best trade-off in terms of noise and gain on
the one hand and bandwidth on the other, and also gives no problems regarding input dynamic range. The
achievable signal bandwidth (assuming that the amplifier has an ideal frequency behavior) is now equal to
1/[2Rf (Cf + Cp /A)], where Cf is the parasitic capacitance around the amplifier (Cf  Cp ). The actual bandwidth
of the system is limited either by parasitic capacitances in the feedback network or by the bandwidth of the
amplifier. The former is a common case in high-gain applications, when a large value of Rf is used, while the
latter is more typical in lower-gain applications. In any case, attention must be paid to achieving frequency
stability, as a closed-loop configuration is adopted. Neglecting the feedback parasitic capacitance, the equivalent
input current noise of the system in the frequency band of interest is

where In,s and In,d account for shot noise of signal and dark currents of the photodetector, respectively. From
the above equation, one can observe that the contribution of V n,a to the total equivalent input noise increases
at high frequencies, even though at low frequencies, it can be negligible if V n,a is sufficiently small [noise gain
peaking effect (8)]. However, at very high frequencies, the contribution of V n,a is limited by the ratio Cp /Cf and
then rolls off due to the amplifier open-loop response.
Preampliers with Capacitive Sources. A capacitive sensor source can be modeled, in its useful
frequency range, as a voltage source in series with a capacitor or as a current source in parallel with a

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PREAMPLIFIERS

capacitor (the case where the sensor signal is delivered in the form of a charge packet will be briefly addressed
at the end of this section). The output signal of the sensor is taken either as the open-circuit voltage or the
short-circuit current, respectively. Sensor capacitance and signal frequency depend on the application, and can
vary by several orders of magnitude (from picofarad up to nanofarad and from hertz to megahertz ranges,
respectively). Typical examples are capacitive antennas (e.g., for radio receivers), electret microphones, some
piezoelectric sensors such as hydrophones, optical detectors, and so forth. In this section, wide-band monolithic
preamplifiers, specifically, will be considered. In the case of narrow-band applications, noise optimization can
be achieved by adding a suitable series or parallel inductance in the input network, using a technique very
similar to that used for narrow-band preamplifiers with inductive sources (6) (see the next section). The basic
principle is to determine a proper resonance which ideally makes the effects of the amplifier input current or
voltage noise source disappear at the frequency of interest, thereby minimizing the system equivalent input
noise.
Two basic topologies of wide-band preamplifiers for capacitive signal sources are depicted in Fig. 9,
where the voltage source representation is used for the sensor, and equivalent input noise generators are also
shown. Notice that, ideally, no noise is generated in the signal source, due to its reactive nature. In Fig. 9(a),
a biasing resistor Rb has been included. This resistor must be large enough so that, in the frequency band
of interest, the pole generated by the group Rb Cc roughly cancels out the effects of the zero located in the
origin, which arises due to Cc . Thus, the preamplifier gain is independent of frequency, as required in most
wide-band applications. This is a typical situation in preamplifiers for electret microphones, where, in the
case of monolithic implementations, an active biasing resistor is generally used to avoid excessive silicon area
occupation due to the large resistance value required (10,11). Noise considerations for this topology are very
similar to those for voltage amplifiers with resistive sources, although in the present case the source resistance
is assumed to be negligible, and obviously the dominant noise source is the amplifier.
In the capacitive-feedback structure of Fig. 9(b), no dc feedback or biasing element has been drawn,
although generally dc stabilization is required (this can be obtained, e.g., with a very large feedback resistor,
and will be neglected in the following noise considerations). In this scheme, the feedback capacitor Cf sets the
mid-frequency voltage gain equal to Cs /Cf . Also in this case, therefore, the gain is substantially independent
of frequency. Moreover, it shows no dependence upon the parasitic capacitance Cp associated to the input line,
which is very useful in applications requiring long cable connections between the sensor and the amplifier (12).
Choosing the best value of Cf derives from two contrasting requirements. On the one hand, a small capacitor Cf
should be chosen, so that the minimum input signal must be amplified to a level adequate to drive the cascaded
stages, while on the other hand, capacitor Cf should not be so small that the amplifier output saturates in the
presence of the maximum allowed input signal.
Again, regardless of the application, the noise performance of the preamplifier is of paramount importance,
as it generally determines the sensitivity of the overall system. From Fig. 9(b), the equivalent input noise voltage
is

For the best noise performance, the most straightforward choice is again the use of single-ended input stages,
although fully differential amplifier solutions are also used for this kind of sensors (12,13). As pointed out
above, in this section we consider mainly bipolar and MOS input devices, as currently JFET circuits are used
only in specific applications (e.g., in charge-sensitive amplifiers for nuclear physics experiments; see below). In
the case of a bipolar input transistor, taking into account its equivalent input sources given in Eqs. (17) and

PREAMPLIFIERS

15

Fig. 9. Preamplifier with capacitive sources: (a) voltage amplifier with biasing resistor; (b) voltage amplifier with capacitive
feedback.

neglecting the correlation factor , the total equivalent input noise turns out to be:

It is apparent that a small base resistance rb and a high large current gain are needed for low noise. Moreover,
one can see that, for any given value of IC , the base current shot-noise contribution [second term in Eq. (24)]
is dominant at low frequencies, while voltage noise [first term in Eq. (24)] dominates at high frequencies. To
achieve noise minimization, noise matching must be achieved by a suitable choice of the collector bias current

16

PREAMPLIFIERS

IC . Indeed, increasing IC has opposite effects on the two noise contributions. The optimal value of IC can be
easily calculated by taking the derivative of Eq. (24) with respect to IC , obtaining (3,7):

Notice that Eq. (25) is formally identical to Eq. (19): (Cs + Cp + Cf ) represents the module of the admittance to
the input network. As observed, IC,opt depends on the frequency. As a consequence, when required, wide-band
noise optimization with bipolar input stages is not possible. Obviously, when choosing the value of IC , other
features such as gain and operation speed must also be taken into account.
In the case of an MOS input transistor, using the noise sources in Eqs. (21), the equivalent input voltage
noise source turns out to be:

where the term Ci results from the presence of the input noise current, taking also in account the 100%
correlation existing between V n,a and In,a .
It should be emphasized that noise transfer gain does not depend on frequency. The term V 2 n,a includes
a flicker as well as a thermal component. Both these contributions should be reduced to a minimum to achieve
low-noise performance. To reduce input-referred noise, capacitances Cp and Cf must be minimized, even though
they are noiseless elements. As far as Ci is concerned, it is worth pointing out that its value is strictly related to
the input transistor size. Changing its value has two opposite effects on noise performance. On the one hand,
increasing the aspect ratio W/L of the input device leads to a decrease in both flicker and thermal noise, as a
result of the corresponding increase in its gate capacitance and transconductance, respectively. On the other,
from Eq. (26), increasing Ci will also degrade noise performance. An optimized value of the input transistor
capacitance and, hence, of its size, is therefore necessary, which is determined by taking the derivative of Eq.
(26) with respect to Ci . The gate length should be set to the minimum to maximize amplifier performance
in terms of thermal noise and gain-bandwidth product. Noise optimization results are different when flicker
and thermal components are considered, as a consequence of the different dependence of their noise spectral
density upon Ci . In the case of flicker noise, the best capacitance matching is obtained by setting Ci = Cs + Cp
+ Cf , while for thermal noise, the best value is Ci = (Cs + Cp + Cf )/3. When both flicker and thermal noise
contributions are important, a trade-off value of Ci is chosen, for example, the average of the two optimal values
(3). An analytical derivation of the optimum Ci value in the presence of both thermal and flicker series noise
can be found in (14). A suitably large bias current is also required to maximize the transconductance of the
input transistor and, hence, reduce its thermal noise. An n-channel input device also helps to this end. On the
contrary, flicker noise is generally smaller for p-channel devices (15,16,17).
It has been shown (3) that, for a capacitive source, an MOS input device offers better noise performance
than a bipolar one. Obviously, a suitable design is needed to minimize noise contributions by the other components and following stages in the circuit (for the latter purpose, e.g., some gain should be introduced in the first
stage of the amplifier). Depending on the application, high linearity, large load drive capability, and wide output
dynamic range can also be required of the preamplifier, these features being related mainly to an optimized design of its output stage. Moreover, due to the presence of the feedback loop, adequate frequency stability must be
provided. Bipolar technology offers inherent advantages for such requirements, however, CMOS preamplifiers
meeting all the specifications needed can be developed using adequate circuit design approaches. These include
using a three-stage topology, a noninverting class A-B output stage, and suitable compensation techniques (3),

PREAMPLIFIERS

17

Fig. 10. Basic scheme of a charge-sensitive preamplifier.

and employing parasitic bipolar transistors (12). When possible, CMOS technology is the preferred choice as it
allows the designer to integrate the preamplifier together with the cascaded processing section at low cost.
BiCMOS technology has also been proposed to implement the preamplifier (3). BiCMOS technology
provides both CMOS and bipolar devices on the same chip. This allows the designer to take advantage of
the superior noise performance of a CMOS transistor used as the input device and, at the same time, to exploit
the excellent features of bipolar transistors to achieve the other requirements with simpler circuits with respect
to fully CMOS solutions. The main disadvantage of BiCMOS technology is its increased process complexity
and, hence, its higher cost.
Charge-Sensitive Preampliers. In some very important applications using a capacitive source, the
input signal is delivered as a charge packet Qi . The signal source can be generally represented as a deltalike current source Qi (t). Popular examples are detector systems for elementary-particle physics experiments
(18,19) and spectrophotometers and vision systems based on photodiodes operating in the storage mode (20).
The basic scheme (Fig. 10) is substantially the same as the previous one. The readout amplifier, generally
referred to as a charge-sensitive amplifier, produces an output voltage step with an amplitude equal to Qi Cf in
response to an input charge packet Qi ; dc stabilization is generally obtained either with a very large feedback
resistor or with a feedback switch SR , which is turned on during suitable reset time intervals.
The above noise-matching considerations still apply (in particular, the relationships obtained for the
optimal input capacitance of the amplifier). In these applications, noise performance is usually expressed in
terms of equivalent noise charge (ENC). This is defined as the charge which the detector must deliver to
the amplifier input in order to achieve unity signal-to-noise ratio at the output, and is usually expressed in
electrons.
Detectors for nuclear physics experiments represent a very critical application of charge-sensitive amplifiers. Here, the amplifier is generally followed by a noise-shaping filter (or pulse shaper), which has the
purpose of optimizing the overall signal-to-noise ratio of the detector system. This is required as, in general,
electronic noise sets the limit to the accuracy of these systems. The best achievable value of ENC increases,
with a substantially linear relationship, with increasing detector capacitance Cs (in fact, a larger Cs leads to a
larger equivalent noise charge for the same equivalent input noise). The obtained values of ENC ranges from

18

PREAMPLIFIERS

few electrons for Cs < 1 pF (pixel detectors), to hundreds of electrons for microstrip detectors, up to thousands
of electrons for calorimeter detectors (Cs in the order of several hundred or even more than 1000 pF).
In some applications, junction field-effect transistors (JFET) are preferred in front-end electronics for
ionization detectors of capacitive nature, mainly because they show better radiation tolerance with respect to
MOS devices and much smaller input current as compared to BJTs (21,22). Nevertheless, under particular
operating conditions, such as very short shaping time (<50 ns) and low-power constraints, BJTs can offer
superior performance (23,24). CMOS solutions have also been developed for readout electronics to exploit the
capability of CMOS technology for very high integration density and low power consumption (3,25). In fact, as a
huge number of read-out channels are needed in modern detector systems, small size and low power dissipation
are also important requirements, which make the monolithic approach the most appealing solution. CMOS
technology is very attractive, especially for detectors that are placed not very close to the radiation environment
and use a pulse shaper with a very fast response (i.e., short peaking time), so that flicker noise is negligible with
respect to thermal noise. A BiCMOS solution implementing a low-power high-gain transresistance amplifier
has also been presented (26).
Preampliers for Inductive Sources. An inductive sensor source can be generally modeled as a
current source in parallel with an inductance. An internal resistance can also be present, to account for
the real part of the sensor impedance. Examples of inductive sensors include magnetic heads (e.g., for tape
and video cassette recorders), inductive pick-ups, dynamic microphones, ferrite antennas, and so forth. The
operation principle of such sensors is to convert the information, received in the form of an electromagnetic
field, into an electrical signal by means of an inductive coil. In most cases, very weak signals are generated and,
therefore, very severe noise specifications have to be met by the preamplifier. Obviously, the reactive elements
in the circuit do not contribute any noise directly, however, their presence affects the noise behavior of the
circuit.
Very different situations occur when narrow-band and wide-band applications are considered. A typical
preamplifier topology for narrow-band inductive signal sources is illustrated in Fig. 11, where equivalent input
noise generators are also shown. Lp is the source inductance, Rs is the sensor resistance, Rb can be a biasing or
a load resistor, and Cp is a shunt capacitance (including both parasitic and, in this case, added capacitances).
Cc is a dc decoupling capacitor (Cc  Cp ), and will be regarded as a short circuit in the frequency band of
interest. The voltage signal at the amplifier input turns out to be equal to:

where RT = Rb Rs . The presence of the resonance due to the group Lp Cp is apparent.
For this configuration, one can choose a suitable size of the shunt capacitance Cp to obtain the best noise
matching (6). In fact, the expression of the equivalent input noise current for the circuit in Fig. 11 is easily
calculated as:

Each noise current source reflects unchanged to the input at any frequency. By contrast, the coefficient of the
noise voltage contribution is frequency dependent, and turns out to be minimum at the resonant frequency
o = 1/(Lp Cp )1/2 . This behavior obviously derives from the large impedance shown by the parallel group Lp Cp

PREAMPLIFIERS

19

Fig. 11. Basic topology of a preamplifier for a narrow-band inductive source (shunt capacitance Cp includes both parasitic
and, in this case, added capacitances).

at the resonance frequency. Neglecting the correlation effect between V n,a and In,a , the resulting equivalent
input noise current is given by I2 n,eq = I2 n,s + I2 n,b + I2 n,a + V 2 n,a /R2 T . It should be pointed out that no reactive
element appears in the expression for minimum noise.
Let us now turn our attention to wide-band applications, where a flat response is required for the signal.
The amplifier configuration in Fig. 11 can no longer be used, as the resonant group inherently provides narrowband signal response. To overcome this limitation, a constant transimpedance topology can be used, as shown
in Fig. 12. The voltage across the group Lp Cp is ideally maintained constant, regardless of signal amplitude
and frequency, thereby preventing any resonance effect. The current Is delivered by the sensor is injected into
Rf , thus achieving the desired frequency-independent transfer gain: V o /Is = Rf . The equivalent input noise
current in this topology turns out to be:

The noise contributed by the amplifier is represented by the terms including In,a and V n,a . The use of a large
inductance Lp reduces the contribution of V 2 n,a . This is especially true at low frequencies, where 2 Lp Cp  1.
By contrast, at high frequencies, a small value of Cp helps to achieve low noise.
For practical cases, when very low noise is required, the term I2 n,f = 4KT/Rf due to the feedback resistor
can result too high, thus setting too large a noise floor to the structure. To reduce this contribution, a combined
capacitive and resistive feedback configuration has been proposed, as shown in Fig. 13 (27). The transimpedance
gain of this structure is equal to [1 + j(C1 + C2 )Rf ]/jC1 , which for the frequency range  1/[(C1 + C2 )Rf ]
can be approximated by Rf (C1 + C2 )/C1 and, hence, achieves the required frequency independence. Obviously,
a careful stability analysis is required when designing the amplifier for this feedback configuration. The inputreferred noise current due to the feedback network turns out to be I2 n,f [C1 /(C1 + C2 )]2 , and is, therefore, reduced
by a factor of (1 + C2 /C1 )2 , with respect to the noise generated by the feedback resistor. To obtain a substantial
noise reduction, C2 is set much larger than C1 and, hence, the reduction factor becomes (C2 /C1 )2 . In practice,
to achieve any given transimpedance gain, we now use a resistor which is C2 /C1 times smaller than in the
case of a conventional transimpedance topology using a purely resistive feedback. Its current noise I2 n,f is,
therefore, larger by the same factor, however, its input-referred contribution is divided by a factor of (C2 /C1 )2

20

PREAMPLIFIERS

Fig. 12. A transimpedance configuration for an inductive source ensures frequency-independent gain.

Fig. 13. The use of a combined resistive and capacitive feedback in a transimpedance amplifier minimizes the noise
contribution of the feedback network.

and, therefore, a substantial improvement (by a factor of C2 /C1 ) is achieved. It should be noted that with this
assumption (C2  C1 ), the resonance frequency in the input network is approximately equal to LC = 1/[Lp (Cp
+ C1 )]1/2 .
When a bipolar input transistor is used in the amplifier, the correlation term in Eq. (29) can be neglected,
and noise minimization requires a small base resistance rb and a large current gain . Moreover, as in the
case of a capacitive signal source, the collector current IC must be set to an optimal value, as a consequence
of its opposite effects on input voltage and current noise components. Again, this optimal current is frequency

PREAMPLIFIERS

21

dependent, and therefore noise optimization cannot be obtained in a wide frequency range (3,27), leading to
the choice of a trade-off current for any given application.
When using CMOS technology, no noise contribution due to the gate current is present, thus removing
the basic limiting factor to the noise performance in bipolar preamplifiers (i.e., the base shot noise component).
As for the case of capacitive signal sources, it can be shown that noise optimization is achieved by suitably
sizing the input transistor of the preamplifier. Again, the optimal size is different when considering flicker and
thermal noise. Furthermore, as a consequence of the frequency dependence of the coefficient of V 2 n,a in the
expression of the total equivalent input noise current [see Eq. (29)], the optimal transistor size also depends
on frequency, in contrast with the case of preamplifiers for capacitive sources. For frequencies much lower
than the resonance frequency LC , optimization is achieved by choosing an amplifier input capacitance Ci
=
1/(2 Lp ) for both flicker and thermal noise (3). For > LC , wide-band noise optimization can be obtained by
setting Ci = (CP + C1 )/3 and Ci = (CP + C1 ) in the thermal and flicker noise domain, respectively. Both noise
components must be taken into account when determining the input transistor size for any given application,
which can be done by using numerical simulation.
Also in the case of wide-band preamplifiers for inductive sources, a detailed noise analysis (3) shows that,
in spite of the presence of a large flicker noise component, CMOS technology leads to better noise performance
than the bipolar one. Again, BiCMOS technology has been proposed to exploit the advantages coming from
integrating both CMOS and bipolar devices in the same chip, even though at an increased cost of the fabrication
process.

BIBLIOGRAPHY
1. IRE Subcommittee 7.9 on Noise, Representation of noise in linear two ports, Proc. IRE, 48: 6974, 1960.
2. C. D. Motchenbacher J. A. Connelly Low-Noise Electronic System Design, New York: Wiley, 1993.
3. Z. Y. Chang W. M. C. Sansen Low-Noise Wide-Band Amplifiers in Bipolar and CMOS Technologies, Norwell, MA:
Kluwer, 1991.
4. IRE Subcommittee on Noise, IRE standards on methods of measuring noise in linear two ports, 1959 (IRE Standard
59 IRE 20. S1), Proc. IRE, 48: 6068, 1960.
5. Y. Netzer A new interpretation of noise reduction by matching, Proc. IEEE, 62: 404406, 1974.
6. Y. Netzer The design of low-noise amplifiers, Proc. IEEE, 69: 728741, 1981.
7. M. Steyaert Z. Y. Chang W. Sansen Low-noise monolithic amplifier design: Bipolar versus CMOS, Analog Integr. Circuits
Signal Process., 1: 919, 1991.
8. J. G. Graeme Photodiode Amplifiers: Opamp Solutions, New York: McGraw-Hill, 1996.
9. D. J. T. Heatley Optical Receivers, in J. E. Franca and Y. Tsividis (eds.), Design of Analog-Digital VLSI Circuits for
Telecommunications and Signal Processing, 2nd ed., Englewood Cliffs, NJ: Prentice-Hall, 1994.
A CMOS preamplifier for electret microphones, Proc. 1995 IEEE Int. Symp. Circuits
10. J. Silva-Martnez J. Salcedo-Suner
Syst., 3: 1995, pp. 18681871.
11. J. F. Duque-Carrillo et al. VERDI: An acoustically programmable and adjustable CMOS mixed-mode signal processor
for hearing aid applications, IEEE J. Solid-State Circuits, SC-31: 634645, 1996.
12. B. Stefanelli et al. A very low-noise CMOS preamplifier for capacitive sensors, IEEE J. Solid-State Circuits, SC-28:
971978, 1993.
13. A. C. Pluygers A novel microphone preamplifier for use in hearing aids, Analog Integr. Circuits Signal Process., 3:
113118, 1993.
14. L. Fasoli M. Sampietro Criteria for setting the width of CCD front end transistor to reach minimum pixel noise, IEEE
Trans. Elec. Dev., ED-43: 10731076, 1996.
15. J.-C. Bertails Low-frequency noise considerations for MOS amplifier design, IEEE J. Solid-State Circuits, SC-14:
773776, 1979.
16. E. A. Vittoz The design of high-performance analog circuits on digital CMOS chips, IEEE J. Solid-State Circuits, SC-20:
657665, 1985.

22

PREAMPLIFIERS

17. K. R. Laker W. Sansen Design of Analog Integrated Circuits and Systems, New York: McGraw-Hill, 1994.
18. E. Gatti P. F. Manfredi Processing the signals from solid-state detectors in elementary particle physics, La Rivista del
Nuovo Cimento, 1, serie 3, 1986.
19. V. Radeka Low-noise techniques in detectors, Ann. Rev. Nucl. Part. Sci., 38: 217277, 1988.
20. A. Sartori et al. A 2-D photosensor array with integrated charge amplifier, Sensors and Actuators A. Physical, 4647:
247250, 1995.
21. G. Bertuccio A. Pullia A low noise silicon detector preamplifier system for room temperature X-ray spectroscopy, Proc.
Symp. Semicon. Room-Temperature Radiation Detector Appl. Mater. Res. Soc. Symp. Proc., 302: 1993, pp. 597603.
22. G. Bertuccio A. Pullia G. De Geronimo Criteria of choice of the front-end transistor for low-noise preamplification of
detector signals at sub-microsecond shaping times for X- and -ray spectroscopy, Nucl. Instr. Meth. Phys. Res., A 380:
301307, 1996.
23. E. Gatti A. Hrisoho P. F. Manfredi Choice between FETs or bipolar transistors and optimization of their working points
in low-noise preamplifiers for fast pulse processing: Theory and experimental results, IEEE Trans. Nucl. Sci., 30:
319323, 1983.
24. G. Bertuccio L. Fasoli M. Sampietro Design criteria of low-power low-noise charge amplifiers in VLSI bipolar technology,
IEEE Trans. Nucl. Sci., 44: 17081718, 1997.
25. I. Kipnis et al. A time-over-threshold machine: The readout integrated circuit for the BABAR silicon vertex tracker,
IEEE Trans. Nucl. Sci., 44: 289297, 1997.
26. J. Wulleman A low-power high-gain transresistance BiCMOS pulse amplifier for capacitive detector readout, IEEE J.
Solid-State Circuits, SC-32: 11811191, 1997.
27. Z. Y. Chang W. Sansen Stability and noise performance of constant transimpedance amplifier with inductive source,
IEEE Trans. Circuits Syst., CAS-35: 264271, 1989.

J. F. DUQUE-CARRILLO
University of Extremadura
GUIDO TORELLI
University of Pavia

POWER SYSTEM ON-LINE TRANSIENT STABILITY

ASSESSMENT

INTRODUCTION
Recent major blackouts in North America and Europe
vividly demonstrated that power interruptions or blackouts can signicantly impact the economy and are not acceptable to society. And yet, the ever increasing loading
of transmission networks coupled with a steady increase
in load demands have pushed the operating conditions of
many power systems worldwide ever closer to their stability limits. The combination of limited investment in new
transmission and generation facilities, new regulatory requirements for transmission open access, and environmental concerns are forcing transmission networks to carry
more power than they were designed to withstand. This
problem of reduced operating security margins is being further compounded by factors such as (1) the increasing number of bulk power interchange transactions and non-utility
generators, and (2) the trend toward installing higher output generators with lower inertia constants and higher
short-circuit ratios. Under these conditions, it is now well
recognized that any violation of power system dynamic security limits leads to far-reaching consequences for the entire power system.
By nature, a power system continually experiences two
types of disturbances: event disturbances and load variations. Event disturbances (contingencies) include loss of
generating units or transmission components (lines, transformers, substations) from short-circuits caused by lightning, high winds, failures such as incorrect relay operations or insulation breakdown, sudden large load changes,
or a combination of such events. Event disturbances usually lead to a change in the network conguration of the
power system caused by actions from protective relays and
circuit breakers. They can occur in the form of a single
equipment (or component) outage or in the form of multiple simultaneous outages when taking relay actions into
account. Load variations, on the other hand, are variations
in load demands at buses and/or power transfers among
buses. The network conguration may remain unchanged
after load variations.
Power systems are planned and operated to withstand the occurrence of certain disturbances. The North
American Electric Reliability Council denes security as
the ability to prevent cascading outages when the bulk
power supply is subjected to severe disturbances. The
specic criteria that must be met are set by individual
reliability councils. Each council establishes the types
of disturbances that its system must withstand without
cascading outages.
A major activity in power system planning and operations is to examine the impact of a set of credible disturbances on power system dynamic behaviors such as stability. Power system stability analysis is concerned with a
power systems ability to reach an acceptable steady state
(operating condition) after a disturbance. Stability analysis is one of the most important tasks in power system op-

erations and planning. Today, stability analysis programs

are being used by power system planning and operating
engineers to simulate the response of the system to various credible disturbances. In these simulations, the dynamic behavior of a current or proposed power system is
examined to determine whether stability has been maintained or lost after the contingency. For operational purposes, power system stability analysis plays an important
role in determining the system operating limits and operating guidelines. During the planning stage, power system
stability analysis is performed to check relay settings, to
set the parameters of control devices, or to assess the need
for additional facilities and the locations at which to place
additional control devices in order to enhance the systems
static and dynamic security. Important conclusions and decisions about power system operations and planning are
made based on the results of stability studies.
Transient stability problems, a class of power system
stability problems, have been a major operating constraint
in regions that rely on long-distance transfers of bulk
power (e.g., in most parts of the Western Interconnection
of the United States., Hydro Quebec, the interfaces between Ontario and the New York area and the Manitoba/
Minnesota area, and in certain parts of China and Brazil).
The trend now, with increased instances and total volume
of bulk power transfer, is that many parts of the various interconnected systems are becoming constrained by
transient stability limitations. The wave of recent changes
has greatly increased the adverse effect of both event disturbances and load variations on power system stability.
Hence, it is imperative to develop powerful tools to examine power system stability in a timely and accurate manner
and to derive necessary control actions for both preventive
control and enhancement control.
On-line transient stability assessment (TSA) is an
essential tool needed to avoid any violation of dynamic security limits. Indeed, with current power system operating
environments, it is increasingly difcult for power system
operators to generate all operating limits for all possible
operating conditions under a list of credible contingencies.
Hence, it is imperative to develop a reliable and effective
on-line TSA to obtain the operating security limits at or
near real time. In addition to this important function,
power system transmission open access and restructuring
further reinforce the need for an on-line TSA as it is
the base upon which determination of available transfer
capability and dynamic congestion management problems
and coordination of special protection systems can be
effectively resolved.
Signicant engineering and nancial benets are expected from an on-line TSA. First, one may be able to operate a power system with operating margins reduced by
a factor of 10 or more if the transient stability assessment
is based on the actual system conguration and operating
conditions, instead of assumed worst-case conditions, as is
done in off-line studies. A second benet of on-line analysis
is that the analysis can be reduced to those cases relevant
to actual operating conditions, thereby obtaining more accurate operating margins, allowing more power transfer,
and freeing engineering resources for other critical activities.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Power System On-Line Transient Stability Assessment

Modern energy management systems periodically perform the tasks of on-line power system static security assessment and control for ensuring the ability of the power
system to withstand a set of credible contingencies (disturbances). The assessment involves the selection of the
set of credible contingencies and then the evaluation of the
systems response to contingencies. Various software packages for security assessment and control have been implemented in modern energy control centers. These packages provide comprehensive on-line security analysis and
control based almost exclusively on steady-state analysis,
making them applicable only to static security assessment
and control [1].
From a computational viewpoint, on-line TSA requires
the handling of a large set of mathematical models, which is
described by a large set of nonlinear differential equations
in addition to the nonlinear algebraic equations involved
in the static security assessment. The computational effort required by on-line TSA is roughly three magnitudes
higher than that for the static security assessment (SSA).
This result explains why TSA has long remained an off-line
activity instead of on-line activity in the energy management system. Extending the functions of energy management systems to take account of on-line TSA and control
is a rather challenging task and requires several breakthroughs in measurement systems, analysis tools, computation methods, and control schemes.
Currently, stability analysis programs routinely used in
utilities around the world are based mostly on step-by-step
numerical integrations of power system stability models
to simulate system dynamical behaviors. This practice of
power system stability analysis based on the time-domain
approach has a long history [112]. However, because of the
nature of the time-domain approach, it has several disadvantages: (1) It requires intensive, time-consuming computation efforts; therefore, it has not been suitable for on-line
application; (2) it does not provide information as to how
to derive preventive control when the system is deemed
unstable and how to derive enhancement control when the
system is deemed critically stable; and (3) it does not provide information regarding the degree of stability (when
the system is stable) and the degree of instability (when
the system is unstable). This piece of information is valuable for both planning and operations.
An alternative approach to transient stability analysis employing energy functions, called direct methods, was
originally proposed by Magnusson [13] in the late 1940s
and was pursued in the 1950s by Aylett [14]. Direct methods have a long development history spanning six decades.
Signicant progress, however, has been made recently in
the practical application of direct methods to transient stability analysis. Direct methods can determine transient
stability without the time-consuming numerical integration of the (post-fault) power system [1518]. In addition to
its speed, direct methods also provide a quantitative measure of the degree of system stability. This additional information makes direct methods very attractive when the
relative stability of different network conguration plans
must be compared or when system operating limits constrained by transient stability must be calculated quickly.
Another advantage of direct methods is the ability to pro-

vide useful information regarding how to derive preventive control actions when the underlying power system is
deemed unstable and how to derive enhancement control
actions when the underlying power system is deemed critically stable.
After decades of research and developments in the
energy-function-based direct methods and the timedomain simulation approach, it has become clear that the
capabilities of direct methods and that of the time-domain
approach complement each other. The current direction of
development is to include appropriate direct methods and
time-domain simulation programs within the body of overall power system stability simulation programs [1922].
For example, the direct method provides the advantages of
fast computational speed and energy margins, which make
it a good complement to the traditional time-domain approach. The energy margin and its functional relations to
certain power system parameters are an effective complement to develop tools such as preventive control schemes
for credible contingencies that are unstable and to develop
fast calculators for available transfer capability limited by
transient stability. The direct method can also play an important role in the dynamic contingency screening for online transient stability assessment.
PROBLEM FORMULATION AND SYSTEM MODEL
Electric power systems are nonlinear in nature. Their nonlinear behaviors are difcult to predict because of (1) the
extraordinary size of the systems, (2) the nonlinearity in
the systems, (3) the dynamical interactions within the systems, and (4) the complexity of its component modeling.
These complicating factors have forced power system engineers to analyze the complicated behaviors of power systems through the process of modeling, simulation and validation.
The complete power system model for calculating system dynamic response relative to a disturbance comprises
a set of rst-order differential equations
x = f (x, y, u)

(1)

describing the internal dynamics of devices such as

generators, their associated control systems, certain loads
and other dynamically modeled components, and a set of
algebraic equations
0 = g(x, y, u)

(2)

describing the electrical transmission system (the interconnections between the dynamic devices) and internal
static behaviors of passive devices (such as static loads,
shunt capacitors, xed transformers, and phase shifters).
The differential equations (1) typically describe the dynamics of the speed and angle of generator rotors; the ux
behaviors in generators; the response of generator control
systems such as excitation systems, voltage regulators,
turbines, governors, and boilers; the dynamics of equipment such as synchronous VAR compensators (SVCs),
DC lines, and their control systems; and the dynamics
of dynamically modeled loads such as induction motors.
The stated variables x typically include generator rotor

Power System On-Line Transient Stability Assessment

angles, generator velocity deviations (speeds), mechanical

powers, eld voltages, power system stabilizer signals,
various control system internal variables, and voltages
and angles at load buses (if dynamic load models are
employed at these buses). The algebraic equations (2)
comprise the stator equations of each generator, the
network equations of transmission networks and loads,
and the equations dening the feed-back stator quantities.
An aggregated representation of each local distribution
network is usually used in simulating power system
dynamical behaviors. The forcing functions u acting on the
differential equations are terminal voltage magnitudes,
generator electrical powers, and signals from boilers and
automatic generation control systems.
Some control system internal variables have upper
bounds on their values because of their physical saturation effects. Let z be the vector of these constrained state
variables; then the saturation effects can be expressed as
0 < z(t) z

(3)

A detailed description of equations (1)(3) for each component can be found, for example, in Refs. 3 and 4. For
a 900-generator, 14,000-bus power system, the number of
differential equations can easily reach as many as 20,000,
whereas the number of nonlinear algebraic equations can
easily reach as many as 32,000. The sets of differential
equations (1) are usually loosely coupled.
To protect power systems from damage caused by disturbances, protective relays are placed strategically throughout a power system to detect faults (disturbances) and to
trigger the opening of circuit breakers necessary to isolate faults. These relays are designed to detect defective
lines and apparatus or other power system conditions of
an abnormal or dangerous nature and to initiate appropriate control circuit actions. Because of the action of these
protective relays, a power system subject to an event disturbance can be viewed as going through changes in its
network conguration in three stages: from the pre-fault,
to the fault-on, and nally to the post-fault system. The
pre-fault system is in a stable steady state; when an event
disturbance occurs, the system then moves into the faulton system before it is cleared by protective system operations. Stated more formally, in the pre-fault regime, the
system is at a known stable equilibrium point (SEP), say
(xspre , yspre ). At some time t0 the system undergoes a fault (an
event disturbance), which results in a structural change in
the system caused by actions from relay and circuit breakers. Suppose the fault duration is conned to the time interval [t0 , tcl ]. During this interval, the fault-on system is
described by (for ease of exposition, the saturation effects
expressed as 0 < z(t) z are neglected in the following):
x = f F (x, y) t0 t < tcl
0 = gF (x, y)

(4)

where x(t) is the vector of state variables of the system at

time t. Sometimes, the fault-on system may involve more
than one action from system relays and circuit breakers. In
these cases, the fault-on systems are described by several

Figure 1. The simulated dynamical behavior, pre-fault, fault-on,

and post-fault of a generators angle of a large power system model.

sets of nonlinear equations:

x = f 1F (x, y),
0 = gF1 (x, y)
x = f kF (x, y),
0 = gF2 (x, y)

x = f kF (x, y),
0 = gFk (x, y)

t0 t tF,1
tF,1 t tF,2
(5)
tF,k t tcl

The number of sets of equations equals the number of separate actions from system relays and circuit breakers. Each
set depicts the system dynamics caused by one action from
relays and circuit breakers. Suppose the fault is cleared
at time tcl and no additional protective actions occur after
tcl . The system, termed the post-fault system, is henceforth
governed by post-fault dynamics described by
x = f PF (x, y), tcl t <
0 = gPF (x, y)

(6)

The network conguration may or may not be the same as

the pre-fault conguration in the post-fault system. We will
use the notation z(tcl ) = (x(tcl ), y(tcl )) to denote the fault-on
state at switching time tcl The post-fault trajectory after an
event disturbance corresponds to the solution of equation
(5) over the fault-on time period t0 t < tcl and the solution
of equation (6) over the post-fault time period tcl t < t .
The fundamental problem of power system stability
caused by a fault (i.e., a contingency) can be roughly stated
as follows: Given a pre-fault SEP and a fault-on system,
will the post-fault trajectory settle down to an acceptable
steady state [18]? A simulated system trajectory starting
from a pre-fault SEP, fault-on trajectory and post-fault trajectory, is shown in Figs. 1 and 2.
The two sets of equations (1) and (2) describing power
system dynamic response relative to a contingency are
fairly complex, because electric power systems comprise
a large number of components (equipment and control
devices) interacting with each other, exhibiting nonlinear
dynamic behaviors with a wide range of time scales. The
dynamic behavior after a disturbance involves all system
components, to varying degrees. The degree of involvement
from each component determines the appropriate system
model necessary for simulating the dynamic behaviors.
Traditional practice in power system analysis has been to

Power System On-Line Transient Stability Assessment

Figure 2. The simulated dynamical behavior, pre-fault, fault-on,

and post-fault of a voltage magnitude of a large power system
model. During the fault, the voltage magnitude drops to about
0.888 p.u.

use the simplest acceptable system model that captures

the essence of the phenomenon under study. A logic commonly used in power system dynamic simulations is that
the effect of a system component or control device can be
neglected when the time scale of its response is very small
or very large compared with the time period of interest
and, hence, can be considered in quasi-steady state. This
philosophy has been deemed acceptable because of the
severe complexity involved with a full large-scale power
system model.
Based on the different time-scale involvement of each
component and control device on the overall system dynamic behaviors, power system models have been divided
into three models with different time scales: (1) shortterm stability model (predominately describing electromechanical transients) on which transient stability is
based, (2) extended transient and mid-term stability
model, and (3) long-term stability model on which longterm stability is based. These three models are described
by a set of differential-algebraic equations of the same nature as equations (1) and (2) but with different sets of state
variables with different time constants. However, a fuzzy
boundary distinguishes between the mid-term and longterm model. Compared with transient stability analysis,
mid-term and long-term dynamic behaviors have only come
under study relatively recently [3,4,23]. For transient stability analysis, the assumption of one unique frequency is
kept for the transmission network model, but generators
have different speeds. Generators are modeled in greater
detail, with shorter time constants compared with the models used in long-term stability analysis. Roughly speaking,
transient stability models reect the fast-varying system
electrical components and machine angles and frequencies,
whereas the long-term models are concerned with the representation of the slow oscillatory power balance, assuming
that the rapid electrical transients have damped out.
ON-LINE TSA
On-line TSA is designed to provide system operators with
critical information, including, (1) the transient stability
of the system subject to a list of contingencies and (2)

Figure 3. An architecture for on-line transient stability assessment and control.

available (power) transfer limits at key interfaces subject

to transient stability constraints. An integrated architecture for on-line TSA and control is presented in Fig. 3. In
this architecture, there are two major components in the
on-line TSA module: dynamic contingency screening and a
fast time-domain stability program for performing detailed
stability analysis. Several systems have been developed intended for on-line TSA [2429].
When a new cycle of TSA is warranted, a list of credible
contingencies, along with information from the state estimator and topological analysis, are applied to the dynamic
contingency screening program whose basic function is to
screen out contingencies that are denitely stable or potentially unstable. Contingencies that are classied to be
denitely stable are eliminated from additional analysis.
Contingencies that are classied to be potentially unstable are sent to fast time-domain simulation for detailed
analysis. It is the ability to perform dynamic contingency
screening on a large number of contingencies and to lter
out a much smaller number of contingencies requiring additional analysis that makes on-line TSA feasible. Contingencies that are either undecided or identied as unstable
are then sent to the time-domain transient stability simulation program for detailed stability analysis.
The block function of control actions decisions determines whether timely post-fault contingency corrective

Power System On-Line Transient Stability Assessment

actions such as automated remedial actions are feasible

to steer the system from unacceptable conditions to an
acceptable state. If appropriate corrective actions are not
available, the block function of preventive actions determines the required pre-contingency preventive controls
such as real power redispatches or line switching to maintain the system stability should the contingency occur. If
the system will be marginally stable; i.e., critically stable,
the block function of enhancement actions determines the
required pre-contingency enhancement controls such as
real power redispatches or line switching to increase the
degree of system stability should the contingency occur.
In this architecture, a fast and yet reliable method for
performing dynamic contingency screening plays a vital
role in the overall process of on-line TSA.
Two types of basic information are needed to perform
power system on-line TSA: static data (which is the power
ow data) and dynamic data. The power ow data describe the network and its steady-state operating conditions, which corresponds to a real-time system condition
captured by the EMS and solved by state estimators. The
dynamic data supply the information needed to compute
the response of the modeled devices to a given disturbance, which refers to dynamic models and data matching
the real-time power ow. The dynamic data include models of detailed synchronous machines, dynamic load models, induction motor, static VAR compensator, high-voltage
DC link, FACTS, and user-dened models. Another set of
data, sequence network data, is required only if unbalanced
faults are to be simulated. This set of data contains the
negative and zero sequence network data compatible with
power ow data.
In addition to the above basic information, the following
additional information is needed:

Stability margin in terms of energy margin, or op-

erating margin in MW and/or MVar for each unstable contingency and may include preventive control
actions.
Detailed time-domain responses (swing curves) of
user-specied quantities for potentially unstable contingencies.
Critical contingencies (contingency details such as
fault type, fault location, and circuits lost).
Stability margin in terms of energy margin, or operating margin in MW and/or MVar for each critical contingency and may include enhancement control actions.
Detailed time-domain responses (swing curves) of
user-specied quantities for critical contingencies.
If transfer limits are computed, limits (or security
boundary) at key interfaces, and the limiting contingencies.

In addition to the above main functions, the on-line TSA

system should have the following functions:

A study mode with which the users, such as reliability engineers, can analyze various scenarios using
cases archived from real-time system models or created from operational planning studies.

Software and hardware failover protection.

Interfaces with EMS functions.

Denition of contingency list and creation of necessary data for stability analysis, data validation and
correction (option), and output visualization.
DYNAMIC CONTINGENCY SCREENING

Description of disturbances: this information describes the disturbance to be simulated, e.g., fault
location and duration, circuit switching, or generation/load rejection.

Relay data: These data describe the characteristics of
the protection devices.
A complete on-line TSA assessment cycle will be completed within, say, 15 minutes. This cycle starts when all
necessary data are available to the system and ends when
the system is ready for the next cycle. Depending on the
size of the underlying power system, it is estimated that,
for a large-size power system such as 15,000-bus power
system, the number of contingencies in a contingency list
is between 1000 and 3000. The contingency types will include both three-phase faults with primary clearance and
single-line-to-ground faults with backup clearance.
The outputs of on-line TSA in a given cycle include the
following:

Overall status of the system (secure or insecure and

the operating margin).

Unstable contingencies (contingency details such as

fault type, fault location, and circuits lost).

The strategy of using an effective scheme to screen out a

large number of stable contingencies and capture critical
contingencies and to apply detailed simulation programs
only to potentially unstable contingencies is well recognized. This strategy has been successfully implemented in
on-line SSA. The ability to screen several hundred contingencies to capture tens of the critical contingencies has
made the on-line SSA feasible. This strategy can be applied to on-line TSA. Given a set of credible contingencies,
the strategy would break the task of on-line TSA into two
assessment stages [21, 31]:
Stage 1. Perform the task of dynamic contingency
screening to quickly screen out contingencies that
are denitely stable from a set of credible contingencies.
Stage 2. Perform a detailed assessment of dynamic performance for each contingency remaining in Stage 1.
Dynamic contingency screening is a fundamental function of an on-line TSA system. The overall computational
speed of an on-line TSA system depends greatly on the effectiveness of the dynamic contingency screening, the objective of which is to identify contingencies that are denitely stable and thereby avoid further stability analysis

Power System On-Line Transient Stability Assessment

for these contingencies. It is from the denite classication

of stable contingencies that considerable speed-up can be
achieved for transient stability assessment. Contingencies
that are either undecided, identied as critical, or unstable
are then sent to the time-domain transient stability simulation program for additional stability analysis.
It is, hence, imperative that a dynamic contingency
screening program satises the following ve requirements [31]:
1. Reliability measure: Absolute capture of unstable contingencies as fast as possible; i.e., no unstable (singleswing or multi-swing) contingencies are missed. In
other words, the ratio of the number of captured unstable contingencies to the number of actual unstable
contingencies is 1.
2. Efciency measure: High yield of screening out stable
contingencies as fast as possible; i.e., the ratio of the
number of stable contingencies detected to the number
of actual stable contingencies is as close to 1 as possible.
3. On-line computation: Little need of off-line computations and/or adjustments in order to meet with the constantly changing and uncertain operating conditions.
4. Speed measure: High speed, i.e., fast classication for
each contingency case.
5. Performance measure: Robust performance with respect
to changes in power system operating conditions.
The requirement of absolute capture of unstable contingencies is a reliability measure for dynamic contingency
screening. This requirement is extremely important for online TSA. However, it is from the nonlinear nature of the
dynamic contingency screening problem that this requirement can best be met by a reliable method such as one
with a strong analytical basis. The third requirement asserts that a desired dynamic contingency classier is one
that relies or little or no off-line information, computations,
and/or adjustments. This requirement arises because, under current and near future power system operating environments, the correlation between on-line operational data
and presumed off-line analysis data can be minimal, or in
extreme cases, the two can be irrelevant to one another. In
other words, in a not-too-extreme case, off-line presumed
analysis data may become unrelated to on-line operational
data. This uncorrelated relationship is partly attributed
to the imminent bulk power transactions resulting from
deregulation. The rst four requirements should not be degraded by different operating conditions as dictated by the
requirement for robust performance.
Several methods developed for on-line dynamic contingency screening have been reported in the literature; see,
for example, [21, 3133]. These methods can be categorized
as follows: the energy function approach, the time-domain
approach, and the articial intelligence (AI) approach. The
time-domain approach involves the step-by-step simulation of each contingency for a few seconds, say 2 or 3 seconds, to lter out the very stable or very unstable contingencies. This approach may suffer from an accuracy problem in identifying multi-swing stable or unstable contingencies. The AI approaches, such as the pattern recognition

technique, the expert system technique, the decision tree

technique, and the articial neural network approach, all
rst perform extensive off-line numerical simulations aiming to capture the essential stability features of the systems dynamic behavior. They then construct a classier
attempting to correctly classify new, unseen on-line contingencies. As such, the AI approach is likely to become
ineffective for on-line application to current or near-future
power systems if little correlation exists between on-line
operational data and presumed off-line analysis data. In
addition, the existing AI-based methods unfortunately fail
to meet the on-line computation requirement and cannot
guarantee the reliability requirement. In this regard, the
BCU classiers can meet the requirements [21, 31].
DIRECT METHODS FOR TRANSIENT STABILITY
The direct method evolved in the last several decades.
The current direct method, the controlling unstable equilibrium point (UEP) method, uses an algorithmic procedure to determine, based on the energy function theory
and controlling UEP, whether the system will remain stable, without integrating the post-fault system [16, 17, 18].
The direct method assesses the stability property of the
post-fault trajectory, whose initial state is the system state
when the fault is cleared, by comparing the system energy
at the initial state of post-fault trajectory with a critical
energy value. The direct method not only avoids the timeconsuming numerical integration of the post-fault system
but also provides a quantitative measure of the degree of
system stability. The direct method has a solid theoretical
foundation [16, 17].
Given a power system transient stability model with
specied fault-on systems and a specied post-fault system, direct methods for transient stability analysis consist
of four key steps:
Step 1. Construct an energy function for the post-fault
power system.
Step 2. Compute the energy immediately after the fault
clearing point is reached.
Step 3. Compute the critical energy for the fault-on trajectory.
Step 4. Perform transient stability assessments by comparing the energy computed at Step 2 with the critical energy computed at Step 3. If the former is
smaller than the latter, then the post-fault trajectory
will be stable. Otherwise, it may be unstable.
In Step 4, direct methods determine whether a postfault power system will remain stable when the fault
is cleared solely by comparing the system energy (constructed in Step 1) immediately after the fault clearing
point is reached (computed in Step 2) with to a critical energy (computed in Step 3). It is hence very important to
correctly calculate critical energy values.
The theoretical basis of direct methods for the direct
stability assessment of a post-fault power system is the
knowledge of a stability region; if the initial condition of
the post-fault system lies inside the stability region of a

Power System On-Line Transient Stability Assessment

desired post-fault stable equilibrium point, then one can

ensure without performing numerical integrations that the
ensuing post-fault trajectory will converge to the desired
point. Therefore, the knowledge of the stability region plays
an important role in the theoretical foundation for direct
methods. A comprehensive theory of stability region can
be found in [30]. An overview of the energy function theory
for general nonlinear autonomous dynamical systems will
be presented. The energy function theory has been applied
to power system transient stability models to develop a
theoretical foundation for direct methods. We will also give
an overview of this development.
Several methods are proposed in the literature for determining the critical energy values. The classic method, the
closest UEP method proposed in the early 1970s, has been
found to yield unduly conservative results when applied
to power system transient stability analysis. The potential
energy boundary surface (PEBS) method [34] gives fairly
fast but inaccurate results (mostly overestimates). A desirable method for determining the critical energy value
would be the one that can provide the most accurate approximation of the part of the stability boundary toward
which the fault-on trajectory is heading, even though it
might provide a very poor estimate of the other part of
the stability boundary. To this end, the controlling UEP
method, which uses the (connected) constant energy surface passing through the controlling UEP to approximate
the relevant part of stability boundary, is the most promising method. The concept of controlling UEP and its theoretical basis will be presented in next section.
Energy Function Theory
We consider a general nonlinear autonomous dynamical
system described by the following equation:
x (t) = f (x(t))

(7)

to be the power system model under study, where the state

vector x(t) belongs to the Euclidean space Rn , and the function f : Rn Rn satises the sufcient condition for the
existence and uniqueness of solutions. A state vector x is
called an equilibrium point of system (7) if ( f (x) = 0). We
say that an equilibrium point of (7) is hyperbolic if the
Jacobian of f () at x , denoted J f (x), has no eigenvalues
with a zero real part. For a hyperbolic equilibrium point, it
is an (asymptotically) stable equilibrium point if all eigenvalues of its corresponding Jacobian have negative real
parts; otherwise it is an unstable equilibrium point. If the
Jacobian of the equilibrium point x has exactly one eigenvalue with a positive real part, we call it a type-one equilibrium point. Likewise, x is called a type-k equilibrium
point if its corresponding Jacobian has exactly k eigenvalues with positive real parts.
Let x be a hyperbolic equilibrium point. Its stable and
unstable manifolds, W s (x) and W u (x), are dened as follows:
W s (x) := {x Rn :
t (x) x as t }
W u (x) := {x Rn :
t (x) x as t }

(8)

Every trajectory in the stable manifold W S (x) converges to

x as time goes to positive innity, whereas every trajectory
in the stable manifold W u (x) converges to x as time goes to

negative innity. For a stable equilibrium point, it can be

shown that a number > 0 exists such that x0 x  < implies
t (x0 ) x as. If (t ) is arbitrarily large, then x is
called a global stable equilibrium point. Many physical systems contain multiple stable equilibrium points. A useful
concept for these kinds of systems is that of the stability
region (also called the region of attraction). The stability
region of a stable equilibrium point xs is dened as
A(xs ) := {x Rn : limt
t (x) = xs }

(9)

From a topological point of view, the stability region A(xs )

is an open, invariant, and connected set. The boundary of
stability region A(xs ) is called the stability boundary of xs
and will be denoted by A(xs ).
We say a function V : Rn R is an energy function for
the system (7) if the following three conditions are satised:
1. The derivative of the energy function V (x) along any system trajectory x(t) is nonpositive, i.e.,
V (x(t)) 0

(10)

2. If x(t) is a nontrivial trajectory, i.e., x(t), is not an equilibrium point, then, along the nontrivial trajectory x(t),
the set
{t R : V (x(t)) = 0}

(11)

has measure zero in R.

3. That a trajectory x(t) has a bounded value of V (x(t)) for
t R+ implies that the trajectory x(t) is also bounded.
Stating this in brief:
That V (x(t)) is bounded implies x(t) is also
bounded.
Property (1) states that the energy function is nonincreasing along its trajectory, but it does not imply that
the energy function is strictly decreasing along its trajectory. A time interval [t1 , t2 ] may exist such that V (x(t)) = 0
for t [t1 , t2 ]. Properties (1) and (2) imply that the energy
function is strictly decreasing along any system trajectory.
Property (3) states that the energy function is a proper map
along any system trajectory but need not be a proper map
for the entire state space. Recall that a proper map is a
function f : X Y such that for each compact set (D Y ),
the set f 1 (D) is compact in X. Property (3), which can be
viewed as a dynamic proper map, is useful in the characterization of stability boundary. From the above denition
of energy function, it is obvious that an energy function
may not be a Lyapunov function.
In general, the dynamic behaviors of trajectories of
general nonlinear systems could be very complicated; the
asymptotic behaviors of trajectories can be quasi-periodic
trajectories or even chaotic trajectories [35, 41]. If the underlying dynamical system has some special properties,
then the system may admit only simple trajectories. For
instance, every trajectory of system (7) having an energy
function has only two modes of behaviors: Its trajectory either converges to an equilibrium point or goes to innity
(becomes unbounded) as time increases or decreases and

Power System On-Line Transient Stability Assessment

the stability region of the system can be completely characterized. These results are shown in the following theorems:
Theorem 1: [16, 17] (Global behavior of trajectories). If a
function exists satisfying condition (1) and condition (2) of
the energy function for general nonlinear system (7), then
every bounded trajectory of system (7) converges to one of
the equilibrium points.
Theorem 2: [16, 17] (Energy function and stability
boundary). If an energy function exists for the system (7),
which has an asymptotically stable equilibrium point xs
(but not globally asymptotically stable), then the stability
boundary A(xs ) is contained in the set, which is the union
of the stable manifolds of the UEPs on the stability boundary A(xs ); i.e.,
A(xs )

xi {E A(xs )}

W s (xi )

Theorem 2 offers a means for completely characterizing

the stability boundary of the class of nonlinear dynamical systems having energy functions: The stability boundary A(xs ) is contained in the union of the stable manifolds of the UEPs on the stability boundary. These stable
manifolds govern the dynamical behaviors on the stability boundary. This theorem leads to the development of a
theoretical foundation for direct methods.
The energy function theory presented above is applicable to transient stability models described by ordinary
differential equations (ODEs). Extensions of these results
to network-preserving transient stability models that are
mathematically described by a set of differential and algebraic equations (DAE) can be found in Ref. 36.
CONSTRUCTING ENERGY FUNCTIONS
It can be shown that an analytical expression of energy functions does not exist for general lossy networkpreserving transient stability models [35]. Consequently,
numerical energy functions must be used. We present
procedures to derive numerical energy functions for
structure-preserving transient stability models. Most existing network-preserving models can be rewritten as a set
of general differential-algebraic equations of the following
compact form [15]:
U
0=
(u, w, x, y) + g1 (u, w, x, y)
u
U
0=
(u, w, x, y) + g2 (u, w, x, y)
w
U
(12)
(u, w, x, y) + g3 (u, w, x, y)
T x =
x
y = z
U
M z = Dz
(u, w, x, y) + g4 (u, w, x, y)
y
where u IRl and w IRl are instantaneous variables while
x IRn , y IRn , and z IRn are state variables. T is a positive denite matrix, and M and D are diagonal positive denite matrices. Here differential equations describe generator and/or load dynamics, whereas algebraic
equations express the power ow equations at each bus.
g1 (u, w, x, y), g2 (u, w, x, y), g3 (u, w, x, y), and g4 (u, w, x, y) are

vectors representing the effects of the transfer conductance

in the network Y-bus matrix. With the aid of the singularly perturbed systems, the compact representation of the
network-preserving model becomes
U
1 u =
(u, w, x, y) + g1 (u, w, x, y)
u
U
2 u =
(u, w, x, y) + g2 (u, w, x, y)
w
(13)
U
(u, w, x, y) + g3 (u, w, x, y)
T x =
x
U
(u, w, x, y) + g4 (u, w, x, y)
M z = Dz
y
where 1 and 2 are sufciently small positive numbers.
For the compact representation of the singularly perturbed
network-preserving power system model (14) without the
transfer conductance, we consider the following function
W : Rk+l+2n+m R:
W(u, w, x, y, z) = K(z) + U(u, w, x, y)
=

1 T
z Mz + U(u, w, x, y)
2

(14)

Suppose that along every nontrivial trajectory of system (13) with a bounded value of W(u, w, x, y, z), the
vector (u(t), w(t), x(t)) is also bounded for t R+ . Then
W(u, w, x, y, z) is an energy function for system (13).
A numerical network-preserving energy function
Wnum (u, w, x, y) can be constructed by combining an analytic energy function Wana (u, w, x, y, z) = K(z) + U(u, w, x, y)
and a path dependent potential energy Upath (u, w, x, y);
i.e.,
Wnum (u, w, x, y, z) = Wana (u, w, x, y, z) + Upath (u, w, x, y)
= K(z) + U(u, w, x, y) + Upath (u, w, x, y)
= K(z) + Unum (u, w, x, y)
A general methodology for the derivation of an energy function for general power system stability models can be found
in Refs. 3739 and references therein.
ENERGY FUNCTIONS AND STABILITY REGION
We next present how to estimate the stability region of
a high-dimension nonlinear system, such as a power system, via an energy function. These analytical results will be
used to provide a theoretical foundation for direct methods
in general and for the controlling UEP method.
We consider the following set:
Sv (k) = {x Rn : V (x) < k}

(15)

where V () : R R is an energy function. We shall call the

boundary of set (15), S(k) := {x Rn : V (x) = k}, the level set
(or constant energy surface) and k the level value. If k is a
regular value (i.e., V (x) = 0, for all x V 1 (k)), then by the
Inverse Function Theorem, S(k) is a Cr (n-1)-dimensional
submanifold of Rn . Generally speaking, this set S(k) can
be very complicated with several disjoint connected components even for the two-dimensional case. Let
S(k) = S 1 (k) S 2 (k) . . . S m (k)
i

(16)

where S (k) S (k) = when i = j. That is, each of these

components is connected and disjoint from each other.

Power System On-Line Transient Stability Assessment

Since V () is continuous, S(k) is an open set. Because S(k)

is an open set, the level set S(k) is of (n-1) dimensions.
Furthermore, each component of S(k) is an invariant set.
Despite the possibility that a constant energy surface
may contain several disjoint connected components, there
is an interesting relationship between the constant energy
surface and the stability boundary. This relationship is that
at most one connected component of the constant energy
surface S(r) has a nonempty intersection with the stability
region A(xs ). This relationship is established in Theorem 5
below.

Theorem 5: [16, 17] (Constant energy surface and stability region). Let xs be a stable equilibrium point of system
(7) and A(xs ) be its stability region. Then, the set S(r) contains only one connected component, which has a nonempty
intersection with the stability region A(xs ) if and only if
r > V (xs )
Motivated by Theorem 5, we shall use the notation Sxs (r)
to denote the connected set of S(r) (whose level value is r)
containing the stable equilibrium point xs . We drop the subscript xs of Sxs (r) when it is clear from the context. There
is a close relation between the constant energy surfaces at
different level values and the stability region A(xs ). It can
be shown that the connected set Sxs (r) with a level value r
smaller than the critical value is very conservative in the
approximation of the stability boundary A(xs ). As the set
Sxs (r) is expanded by increasing the level value r, the approximation gets improved until this constant energy surface hits the stability boundary A(xs ) at some point. This
point will be shown to be an unstable equilibrium point. We
call this point the closest UEP of the SEP xs with respect to
the energy function V (). Furthermore, as we increase the
level value r, the connected set Sxs (r) would contain points
that lie outside the stability region A(xs ).
It is inappropriate to approximate the stability region
A(xs ) by the connected set Sxs (r) with a level value higher
than that of the lowest point on the stability boundary
A(xs ). Among the several disjoint connected sets of the constant energy surface, the connected set Sxs (r) is the best candidate to approximate the stability region A(xs ) as shown
in the following theorem.
Theorem 6: [16, 17] (Topological characterization). Consider the nonlinear system (7) that has an energy function.
Let xs be an asymptotically stable equilibrium point whose
stability region A(xs ) is not dense in Rn . Then, the point
with the minimum value of the energy function over the
stability boundary A(xs ) exists, and it must be an unstable equilibrium point.
We recall that the fundamental problem of power system transient stability analysis is concerned with whether,
given a pre-fault SEP and a fault-on trajectory, the postfault initial state is located inside the stability region of an
asymptotically stable equilibrium point at which all the
engineering and operational constraints are satised. In
the context of power system transient stability analysis,
we remark that, given a point in the state space (say, the
initial point of the post-fault system), it is generally dif-

cult to determine which connected component of a level set

contains the point by simply comparing the energy at the
given point and the energy of the level set, because a level
set usually contains several disjoint connected components
and these components are not easy to differentiate based
on an energy function value.
Fortunately, in the context of direct methods, this difculty can be circumvented because direct methods compute
the relevant pieces of information regarding (1) a pre-fault
stable equilibrium point, (2) a fault-on trajectory, and (3)
a post-fault stable equilibrium point. These pieces of information are sufcient to identify the connected component
of a level set that contains the initial point of a post-fault
system. We next discuss the most viable direct method: the
controlling UEP method.
CONTROLLING UEP METHOD
Several methods are proposed in the literature attempting to determine accurate critical energy values; see for
example, Refs. 34, 4044. The classic method, the closest
UEP method proposed in the early 1970s, when applied to
power system transient stability analysis has been found
to yield unduly conservative results. The origin of this conservativeness can be explained from a nonlinear system
viewpoint. The closest UEP method attempts to provide
an approximation for the entire stability boundary of the
post-fault system, rather than for the relevant part of the
stability boundary toward which the fault-on trajectory is
heading. This approximation by the closest UEP method
is independent of the fault-on trajectory. Thus, the closest
UEP method usually gives very conservative results for
transient stability analysis. The potential energy boundary surface (PEBS) method proposed by Kakimoto et al.
gives fairly fast and accurate stability assessments but
may give inaccurate results (both overestimates and underestimates).
A desirable method (for determining the critical energy
value) would be the one that can provide the most accurate
approximation of the part of a the stability boundary toward which the fault-on trajectory is heading, even though
it might provide a very poor estimate of the other part of
stability boundary. This is the spirit of the controlling UEP
method, which uses the (connected) constant energy surface passing through the controlling UEP to approximate
the part of stability boundary toward which the fault-on
trajectory is heading. If, when the fault is cleared, the system state lies inside the (connected) energy surface passing through the controlling UEP, then the post-fault system must be stable (i.e., the post-fault trajectory will settle
down to a stable operating point); otherwise, the post-fault
system may be unstable. This is the essence of the controlling UEP method. A consensus seems to have emerged
that, among several methods (for determining the critical
energy value), the controlling UEP method is the most viable for direct stability analysis of practical power systems
[20,45,16]. The success of the controlling UEP method,
however, hinges on its ability to nd the correct controlling UEP.
Given a power system model with a prefault SEP Xspre ,
a fault-on trajectory Xf (t), and a post-fault (transient) sta-

10

Power System On-Line Transient Stability Assessment

bility system S post with a post-fault SEP Xspost , suppose an

energy function exists for the post-fault system S post and
Xspre lies inside the stability region of Xspost . We next discuss
a rigorous denition of the controlling UEP
Denition [16]. The controlling UEP with respect to the
fault-on trajectory Xf (t) is the UEP of the post-fault system S post whose stable manifold contains the exit point of
Xf (t); i.e., the controlling UEP is the rst UEP whose stable manifold is hit by the fault-on trajectory X f (t) at the
exit point.
This denition is motivated by the fact that a sustained
fault-on trajectory must exit the stability boundary of a
post-fault system and that the exit point, i.e., the point
from which a given fault-on trajectory exits the stability
boundary of a post-fault system, of the fault-on trajectory
must lie on the stable manifold of a UEP on the stability
boundary of the post-fault system. This UEP is the controlling UEP of the fault-on trajectory. Note that the existence
and uniqueness of the controlling UEP with respect to a
fault-on trajectory are assured by Theorem 2 and that the
controlling UEP is independent of the energy function used
in the direct stability assessment. With the formal denition of the controlling UEP, we are in a position to formalize
the controlling UEP method.
The Controlling UEP Method
The controlling UEP method for direct stability analysis of
large-scale power systems proceeds as follows:
1. Determination of the critical energy
Step 1.1: Find the controlling UEP, Xco , for a given
fault-on trajectory Xf (t).
Step 1.2: The critical energy, vcr , is the value of energy
function V () at the controlling UEP; i.e., v cr =
V (Xco ).

Analysis of the Controlling UEP Method

The controlling UEP method asserts that the energy value
at the controlling UEP be used as the critical energy for
the fault-on trajectory Xf (t) to assess stability. Using the
energy value at another UEP as the critical energy can give
erroneous stability assessment. Theorem 7 gives a rigorous
theoretical justication of the controlling UEP method for
direct stability analysis of post-fault systems by just comparing the energy value of the state vector at which the
fault is cleared with the energy value at the controlling
UEP.

Theorem 7: (Fundamental theorem for the controlling UEP

method). Consider a general nonlinear autonomous system that has an energy function V () : Rn R. Let Xco be an
equilibrium point on the stability boundary A(Xs ) of this
system. Let r > V (Xs ) and S(r)  the connected component
of the set {X Rn : V (X) < r} containing Xs , and S(r):  the
(topological) boundary of S(r).
Then,
1. The connected constant energy surface S(V (Xco )) intersects with the stable manifold W s (Xco ) only at point
Xco ; moreover, the set S(V (Xco )) has an empty intersection with the stable manifold W s (Xco ). In other words,
S(V (Xco )) W s (Xco ) = Xco and S(V (Xco )) W s (Xco ) = .
2. S(V (Xu )) W s (Xco ) = if Xu is a u.e.p. and
V (Xu ) > V (Xco ).
3. S(V (Xu )) W s (Xco ) = if Xu is a u.e.p. and
V (Xu ) > V (Xco ).
s ))c =
X
is not the closest UEP, then S(V (X))
(A(X
4. If X
.
5. Any connected path starting from a point
P {S(V (Xco )) A(Xs )} and passing through W s (Xco )
must hit S(V (Xco )) before the path hits W s (Xco ).

2. Approximation of the relevant part of stability boundary

Step 2.1: Use the connected constant energy surface of
V () passing through the controlling UEP Xco
and containing the SEP Xs to approximate
the relevant part of stability boundary for the
fault-on trajectory Xf (t).
3. Determination of stability: Check whether the fault-on
trajectory at the fault clearing time (tcl ) is located inside
the stability boundary characterized in Step 2.1. This is
done as follows:
Step 3.1: Calculate the value of the energy function V ()
at the time of fault clearance (tcl ) using the
fault-on trajectory; i.e., vf = V (Xf (tcl )).
Step 3.2: If vf < vcr , then the point Xf (cl) is located inside the stability boundary and the post-fault
system is stable. Otherwise, it is unstable.
The controlling UEP method yields an approximation of
the relevant part of the stability boundary of the post-fault
system to which the fault-on trajectory is heading. It uses
the (connected) constant energy surface passing through
the controlling UEP to approximate the relevant part of
stability boundary.

We next elaborate on the above fundamental theorem.

Results [1] and [5] of Theorem 7 assert that, for any faulton trajectory Xf (t) starting from a point Xspre A(Xs ) and
if the exit point of this fault-on trajectory
V (Xspre ) < V (X),
Xf (t) lies on the stable manifold of Xco , then this fault-on
trajectory Xf (t) must pass through the connected constant
energy surface S(V (Xco )) before it passes through the stable manifold of Xco [thus exiting the stability boundary
A(Xs )]. Therefore, the connected constant energy surface
co )) can be used to approximate the relevant part of
S(V (X
the stability boundary.
Theorem 7 also shows the slightly conservative nature
of the controlling UEP method in direct stability assessment. More importantly, this method can directly detect
both rst-swing and multiswing stability or instability, although historically direct methods have been said to be
only applicable to rst-swing stability analysis. Note that
once the initial point of the post-fault system lies inside
the stability region A(xs ), the post-fault trajectory will converge to Xs after one or multiple swings.
On the other hand, results [2] and [4] of Theorem 7 assert that the following two situations may occur:

Power System On-Line Transient Stability Assessment

11

Case (1): The set S(V (Xu )) contains only part of the
stable manifold. W s (Xco )
Case (2): The set S(V (Xu )) contains the whole stable
manifold. W s (Xco )
In case (1), the fault-on trajectory Xf (t) may pass
through the connected constant energy surface S(V (Xu ))
before it passes through the stable manifold W s (Xco ). In this
situation, incorrect use of Xu as the controlling UEP still
gives an accurate stability assessment. Alternatively, the
fault-on trajectory Xf (t) may pass through the connected
constant energy surface S(V (Xu )) after it passes through
the stable manifold W s (Xco ). In this situation, the controlling UEP method using Xu as the controlling UEP, which
in fact not the controlling UEP gives an inaccurate stability assessment. This classication is incorrect. In case
(2), the fault-on trajectory Xf (t) always passes through the
connected constant energy surface S(V (Xu )) after it passes
through the stable manifold W s (Xco ). Under this situation,
incorrect use of Xu as the controlling UEP can give inaccurate stability assessments. In particular, it can classify the
post-fault trajectory to be stable when in fact it is unstable.
Results [3] and [4] of Theorem 7 assert that the set
S(V (Xu )) has an empty intersection with the stable manifold W s (Xco ). Under this situation, the fault-on trajectory
Xf (t) always passes through the connected constant energy surface S(V (Xu )) rst before it passes through the
connected constant energy surface S(V (Xco )). Thus, using
V (Xu ) as the critical energy value always gives more conservative stability assessments than using that of the (exact)
controlling UEP, Xco . From these cases, it is clear that for a
given fault-on trajectory Xf (t), if the exit point of this faulton trajectory Xf (t) lies on the stable manifold of Xco , then
using the energy value at a UEP other than Xco can give
stability assessments in both directions: too conservative
stability assessments (classify many stable trajectories to
be unstable) or too optimistic stability assessments (classify unstable trajectories to be stable).
Challenges in Computing Controlling UEP. The task of
nding the (exact) controlling UEP of a given fault for general power system models is very difcult. This difculty
comes in part from the following complexities:
1. The controlling UEP is a particular UEP embedded in
a large-degree state-space.
2. The controlling UEP is the rst UEP whose stable
manifold is hit by the fault-on trajectory (at the exit
point).
3. The task of computing the exit point is very involved;
it usually requires a time-domain approach. I
4. The task of computing the controlling UEP is complicated further by the size and the shape of its convergence region.
It is known that, with respect to a selected numerical
method, each equilibrium point has its own convergence
region, i.e., the region from which the sequence generated
by the numerical method starting from a point in the region
will converge to the equilibrium point. It has been observed

Figure 4. Because of small size and the irregular shape

(fractal-like) of the convergence region of UEP with respect to
Newton method, the task of computing the controlling UEP is
very challenging (see the shaded area). If an initial guess is
not sufciently close to the controlling UEP, then the resulting
sequence generated by, the Newton method, will diverge or
converge to another exit point. This gure depicts that the
sequence generated by the Newton method from the exit Xe point
will not converge to the controlling UEP

and theoretically investigated by several researchers that,

under the Newton method, the size of the convergence region of UEP can be much smaller than that of the SEP. In
addition, the convergence region of either a SEP or a UEP
is a fractal, which refers to structures that cannot be described by the typical geometrical objects such as lines, surfaces, and solids. Irregular shape (no smooth boundaries)
and self-similarity (each tiny piece we observe is similar to
the form of the entire shape) are characteristics of fractals
(Fig. 4.) Unfortunately, nding an initial guess sufciently
close to the controlling UEP is a difcult task.
The complexity (3) also calls into doubt the correctness
of any attempt to directly compute the controlling UEP of
a power system stability model. The only one method that
can directly compute the controlling UEP of a power system
stability model is the time-domain approach. This complexity can serve to explain why many methods proposed in the
literature fail to compute the controlling UEP. It is because
these methods attempt to directly compute the controlling
UEP of the power system stability model that is, as pointed
out in complexity (3), difcult if not impossible to compute
without using the time-domain approach.
The ability to compute the controlling UEP is vital in
direct stability analysis. It may prove fruitful to develop
a tailored solution algorithm for nding controlling UEPs
by exploiting special properties as well as some physical
and mathematical insights of the underlying power system
model. We will discuss in great detail such a systematic
method, called the BCU method, along this line for nding
controlling UEPs for power system models.
BCU METHOD
We next discuss a method that does not attempt to directly
compute the controlling UEP of a power system stability
model (original model); instead it computes the controlling
UEP of a reduced-state model, and then it relates the controlling UEP of the reduced-state model to the controlling
UEP of the original model.

12

Power System On-Line Transient Stability Assessment

A systematic method, called the boundary of stability region based controlling unstable equilibrium point method
(BCU method), to nd the controlling UEP was developed
[46, 47]. The method was also given other names such as
the exit point method [6,48,49] and the hybrid method [50].
The BCU method has been evaluated in a large-scale power
system, and it has been compared favorably with other
methods in terms of its reliability and the required computational efforts [48, 49]. The BCU method has been studied by several researchers; see for example [5156]. Descriptions of the BCU method can be found in books such
as Refs. 3,4,6 and 50. The theoretical foundation of BCU
method has been established in. The Refs. 15, 46, and 57
BCU method and BCU classiers have several practical applications. For example, a demonstration of the capability
of the BCU method for on-line transient stability assessments using real-time data was held at two utilities, the
Ontario Hydro Company and the Northern States Power
Company [58, 59]. The BCU method was implemented as
an EPRI TSA software package that was integrated into
an EMS installed at the control center for the Northern
States Power Company [19]. A TSA system, composed of
the BCU classiers, the BCU method, and a time-domain
simulation engine, was developed and integrated into the
Ranger EMS system [60]. The TSA system has been installed and commissioned, as part of an EMS system at
several energy control centers. The BCU method has been
applied to fast derivation of power transfer limits [61] and
applied to real power rescheduling to increase dynamic security [62]. The BCU method has been improved, expanded,
and extended into the integrated package of TEPCO-BCU
[33,46,47,6365].
We next present an overview of the BCU method from
two viewpoints: numerical aspects and theoretical aspects.
In developing a BCU method for a given power system stability model, the associated articial, reduced-state model
must be dened. To explain the reduced-state model, we
consider the following generic network-preserving transient stability model:

U
(u, w, x, y) + g1 (u, w, x, y)
u
U
(u, w, x, y) + g2 (u, w, x, y)
0=
w
U
(u, w, x, y) + g3 (u, w, x, y)
T x =
x
y = z
U
M z = Dz
(u, w, x, y) + g4 (u, w, x, y)
y
0=

(17)

where U(u, w, x, y) is a scalar function. It has been shown

that the above canonical representations can represent existing transient stability models. In the context of the BCU
method, the above model is termed as the original model.
Regarding the original model (17), we choose the following
differential-algebraic system as the reduced-state model

associated with the original model (17).

U
(u, w, x, y) + g1 (u, w, x, y)
u
U
(u, w, x, y) + g2 (u, w, x, y)
0=
w
U
T x =
(u, w, x, y) + g3 (u, w, x, y)
x
U
(u, w, x, y) + g4 (u, w, x, y)
y =
y
0=

(18)

There are several close relationships between the

reduced-state model (18) and the original model (17). The
fundamental ideas behind the BCU method can be explained as follows. Given a power system stability model
(which admits an energy function), say the original model
(17), the BCU method rst explores the special properties
of the underlying model with the aim of dening a reducedstate model, say the model described in (18), such that the
following static as well as dynamic relationships are met
Static Properties
(S1) The locations of equilibrium points of the reducedstate model (18) correspond to the locations of equilibrium points of the original model (17). For example, (u,
w,
x , y ) is an equilibrium point of the
reduced-state model if and only if (u,
w,
x , y , 0) is an
equilibrium point of the original model (17), where
0 Rm and m is an appropriate positive integer.
(S2) The types of equilibrium points of the reducedstate model are the same as that of the original
model. For example, (us , ws , xs , ys ) is a stable equilibrium point of the reduced-state model if and only
if (us , ws , xs , ys , 0) is a stable equilibrium point of
the original model. (u,
w,
x , y ) is a type-k equilibrium point of the reduced-state model if and only
if (u, w,
x , y , 0) is a type-k equilibrium point of the
original model.
Dynamical Properties
(D1) An energy function for the articial, reduced-state
model (18) exists.
(D2) An equilibrium point, say, (u,
w,
x , y ) is on the stability boundary of the reduced-state model (18) if and
only if the equilibrium point (u,
w,
x , y , 0) is on the
stability boundary of the original model (17).
(D3) It is computationally feasible to efciently detect the point at which the projected fault-on trajectory (u(t), w(t), x(t), y(t)) hit the stability boundary
A(us , ws , xs , ys ) of the post-fault reduced-state model
(18) without resorting to an iterative time-domain
procedure to compute the exit point of the post-fault
reduced-state model (18).
The dynamic relationship (D3) plays an important role
in the development of the BCU method to circumvent the
difculty of applying an iterative time-domain procedure
to compute the exit point on the original model. The BCU
method then nds the controlling UEP of the articial,
reduced-state model (18) by exploring the special structure of the stability boundary and the energy function of

Power System On-Line Transient Stability Assessment

13

the reduced-state model (18). Next, it relates the controlling UEP of the reduced-state model (18) to the controlling
UEP of the original model (17).
The fundamental ideas behind the BCU method can be
explained in the following. Given a power system stability
model (which admits an energy function), the BCU method
rst explores special properties of the underlying model
with the aim to dene an articial, state-reduced model
such that certain static as well as dynamic relationships
are met. The BCU method then nds the controlling UEP
of the state-reduced model by exploring the special structure of the stability boundary and the energy function of
the state-reduced model. Third, it relates the controlling
UEP of the state-reduced model to the controlling UEP of
the original model. In summary, given a power system stability model, a corresponding version of the BCU method
exists. The BCU method does not compute the controlling
UEP directly on the original model because, as pointed out,
the task of computing the exit point of the original model,
a key step to compute the controlling UEP, is very difcult
and usually requires the time-domain approach. Instead,
the BCU method (1) explores the special structure of the
underlying model so as to dene an articial, state-reduced
model that captures all the equilibrium points on the stability boundary of the original model; and then (2) computes the controlling UEP of the original model via computing the controlling UEP of the articial model, which
can be computed without resorting to the time-domain approach.
Figure 5. Steps 1 and 2 of the conceptual BCU method.

A Conceptual BCU Method

Step 1. From the fault-on trajectory [u(t), (t), x(t), y(t),
z(t)] of the network-preserving model (17), detect the exit point (u , w , x , y ) at which the
projected trajectory [u(t), (t), x(t), y(t)] exits the
stability boundary of the post-fault reducedstate model (18).
Step 2. Use the exit point (u , w , x , y ), detected in
Step 1, as the initial condition and integrate
the post-fault reduced-state model to an equilibrium point. Let the solution be (uco , wco , xco , yco ).
Step 3. The controlling UEP with respect to the
fault-on trajectory of the original networkpreserving model (17) is (uco , wco , xco , yco , 0).
The energy function at (uco , wco , xco , yco , 0) is
the critical energy for the fault-on trajectory
[u(t), (t), x(t), y(t), z(t)].
Steps 1 and 2 of the conceptual BCU method compute
the controlling UEP of the reduced-state system. Note that
starting from the exit point (u , w , x , y ), Step 2 of the conceptual BCU method, will converge to an equilibrium point.
The controlling UEP always exists and is unique, and the
stable manifold of controlling UEP of the reduced-state system (uco , wco , xco , yco ) contains the exit point (u , w , x , y )
(Fig. 5.) Step 3 relates the controlling UEP of the reducedstate system (with respect to the projected fault-on trajectory) to the controlling UEP of the original system with
respect to the original fault-on trajectory.

Theoretical Basis
Some analytical results showing that, under certain conditions, the original model (17) and the articial, reducedstate model (18) satisfy static relationships (S1) and (S2) as
well as dynamic relationships (D1) and (D2) can be found
in [46, 57]. A computational scheme has been developed
and incorporated into the BCU method to satisfy dynamic
relationship (D3). We next verify the static relationship.
Theorem 8: (Static relationship). Let (us , ws , xs , ys ) be a
stable equilibrium point of the reduced-state model (18).
If the following conditions are satised:
4 U(ui , wi , xi , yi )
for all the
uwxy
UEP (ui , wi , xi , yi ), i = 1, 2, . . . , k on the stability boundary A(us , ws , xs , ys ).
2. The transfer conductance of reduced-state model (18)
is sufciently small. Then, (u,
w,
x , y ) is a type-k equilibrium point of reduced-state model (18) if and only if
(u, w,
x , y , 0) is a type-k equilibrium point of the original
model (17).

1. Zero is a regular value of

Theorem 8 asserts that, under the stated conditions, the

static properties (S1) and (S2) between original model (17)
and the reduced-state model (18) hold. It can be shown
that a numerical energy function exists for the reducedstate model (18). More specically, it can be shown that for

14

Power System On-Line Transient Stability Assessment

any compact set S of the state-space of model (18), there is

a positive number such that, if the transfer conductance
of the model satises |G| <, then there is an energy function dened on this compact set S. The examination of the
dynamic property (D2) can be found in Refs. 46 and 57.
NUMERICAL BCU METHOD
There are several possible ways to numerically implement the conceptual BCU method for network-preserving
power system models. A numerical implementation of this
method along with several numerical procedures necessary
are presented in this section.
A Numerical BCU Method
Step 1. Integrate the fault-on system of the original
model (19) to obtain the (sustained) fault-on trajectory [u(t), w(t), x(t), y(t), z(t)] until the point
(u , w , x , y ) at which the projected trajectory
[u(t), w(t), x(t), y(t)] reaches its rst local maximum of the numerical potential energy function
Unum (., ., ., .) along the projected trajectory.
Step 2. Apply the stability-boundary-following procedure starting from the point (u , w , x , y ) until the point at which the (one-dimensional) local minimum of the following norm of the postfault, reduced-state system is reached; i.e.,

U






(u, w, x, y) + g1 (u, w, x, y)



u

U






+

(u, w, x, y) + g2 (u, w, x, y)

w

U






+

(u, w, x, y) + g3 (u, w, x, y)

x

U






(u, w, x, y) + g4 (u, w, x, y)

+

y

Let the local minimum of the above norm be

occurred at the point (u0 , w0 , x0 , y0 ).
Step 3. Use the point (u0 , w0 , x0 , y0 ) as the initial guess
and solve the following set of nonlinear algebraic equations:

U






(u, w, x, y) + g1 (u, w, x, y)



u

U






+

(u, w, x, y) + g2 (u, w, x, y)

w

U






+

(u, w, x, y) + g3 (u, w, x, y)

x

U






(u, w, x, y) + g4 (u, w, x, y)
= 0
+

y

Let the solution be (uco , wco , xco , yco ).

Step 4. The controlling UEP with respect to the faulton trajectory [u(t), w(t), x(t), y(t)] of the original
system is (uco , wco , xco , yco , 0).
Remarks

1. In Step 1, the projected trajectory [u(t), w(t), x(t), y(t)] can

be viewed as the projection of the original fault-on trajectory on the state-space of the reduced-state system
(18). The rst local maximum of the numerical potential
energy function Unum (., ., ., .) along the projected trajectory is an approximated exit point at which the projected
trajectory intersects with the stability boundary of the
reduced-state system (18).
2. In Step 2, a stability-boundary-following procedure, presented below, is developed to guide the search process
for CUEP of the reduced-state system starting from the
point (u , w , x , y ) by moving along the stability boundary of the reduced-state system (18) toward the CUEP.
During the search process, the point (u0 , w0 , x0 , y0 ) has
the local minimum of the norm among all computed
points in the search process. The norm is a measure
of distance between the current point and an equilibrium point. This point is also termed as the minimum
gradient point (MGP).
3. The reduced-state system can be numerically stiff, and a
stiff differential equation solver should be used to implement Step 2 of the numerical network-preserving BCU
method.
4. Without the stability-boundary-following procedure implemented in Step 2, the search process can move away
from CUEP, making the corresponding MGP distant
from the CUEP and causing the divergence of the Newton method.
5. n Step 3, the MGP is used as an initial guess for the
Newton method to compute the controlling UEP. It is
well known that if the MGP is sufciently close to the
controlling UEP, then the sequence generated by the
Newton method starting from the MGP will converge to
the controlling UEP; otherwise, the sequence may converge to another equilibrium point or diverge (Fig. 6.).
A robust nonlinear algebraic solver (with a large convergence region) is desirable in Step 3 of the numerical
BCU method.
6. Note that Steps 1 to 3 of the above numerical networkpreserving BCU method compute the controlling UEP
of the reduced-state system (18) and Step 4 relates the
controlling UEP of the reduced-state system to the controlling UEP of the original system (17).
7. From a computational viewpoint, the exit point is characterized by the rst local maximum of the potential energy along the (sustained) fault-on trajectory. To nd the
exit point, one can compute the dot-product of the faulton speed vector and post-fault power mismatch vector at
the each integration step. When the sign of dot-product
changes from positive to negative, the exit point is detected.
Numerical Detection of Exit Point. A numerical procedure for accurate detection of exit point in Step 1 of numerical BCU method by employing the linear interpolation
method is described in the following:
Step 1. Integrate the fault-on trajectory until the dot
product changes sign, say between the interval
[t1 , t2 ].

Power System On-Line Transient Stability Assessment

15

Figure 6. If the MGP does not lie inside the convergent region of the Newton method, then the sequence generated by the Newton method
starting from the MGP will not converge to the controlling UEP. The sequence may diverge as illustrated in (a), or it may converge to the
stable equilibrium point as illustrated in (b).

Step 2. Apply the linear interpolation to the interval

[t1 , t2 ], which results in an intermediate time t0
where the interpolated dot product is expected
to be zero. Compute the exact dot product at
t0 for the post-fault reduced-state system. If the
value is smaller than a threshold value, the exit
point is obtained. Exit loop.
Step 3. If the dot product is positive, then replace t1 with
t0 ; otherwise replace t2 with t0 and go to Step 2.
To nd an adequate MGP for reliably computing the
controlling UEP, a stability-boundary-following procedure
to guide the search process for the MGP starting from the
exit point and move along the stability boundary of the
state-reduced system is described below:
Stability-Boundary-Following Procedure.
Step 1. Integrate the post-fault reduced-state system
starting from the exit point for a few time-steps,
say, 4 to 5 steps of integration; let the new point
be termed the current point on the trajectory.
Step 2. Construct a ray connecting the current point
on the trajectory and the SEP of the post-fault
reduced-state system.

Step 3. Move along the ray starting from the current

point and detect the point with the rst local
maximal potential energy, which is an energy
function for the reduced-state system, along the
ray. In practical implementation, this task is
to check the zero crossing of the dot product
between the power mismatch and the speed.
The sign of the dot product at the current point
determines the direction of the local maximal
search. Replace the current point with the point
with the rst local maximal potential energy.
Step 4. Repeat Steps 13 until a point where the norm
of the post-fault reduced-state is lower than a
threshold value is reached. This point is a desired MGP.

The analytical basis for the above procedure is the structure of the stability boundary of the reduced-state system.
It can be shown that the stability boundary of the original system (respectively, the reduced-state system) is composed of the stable manifold of the u.e.p on the stability
boundary. The controlling UEP is the u.e.p whose stable
manifold contains the exit point of the fault-on trajectory
on the stability boundary of the original system. Moreover,
controlling UEP is usually of type-1 (the UEP whose corresponding Jacobian matrix contains only one eigenvalue

16

Power System On-Line Transient Stability Assessment

with a positive real part). The type-1 u.e.p has the nice
feature of being a SEP inside the stability boundary. Furthermore, the stability boundary is an attracting set in
the state space. Hence, if one can conne the entire search
process to a neighborhood close to the stability boundary of
the post-fault reduced-state system, then the search process will likely obtain an MGP close to the controlling
u.e.p, facilitating the convergence of Newton method. The
stability-boundary-following procedure described above offers such a capability. We note that in Step 3 of the stabilityboundary-following procedure, the task of updating the
point along the post-fault reduced-state trajectory with the
point having a local maximal energy function along the ray
amounts to conne the MGP search process close to the stability boundary.

GROUP-BASED BCU METHOD

The one-parameter transversality conditions play an important role in the theoretical foundation of the conceptual
BCU method [46, 57]. Under this condition, the reducedstate system shares the same UEPs as the original system
on the stability boundaries of both systems. Note that as
this condition is a sufcient condition, the reduced-state
system and the original system may still share the same
UEPs on their stability boundaries, even though the oneparameter transversality condition is not satised. However, because of the complexity of practical power system
models, the one-parameter transversality conditions may
not be always satised [5154].
We can take a different approach for verifying the
one-parameter transversality condition. Instead of checking the one-parameter transversality condition and the
small-transfer-conductance condition, we propose to di

rectly check whether the UEP (uco , wco , xco

, yco
, 0) lies on the
stability boundary of the original model, i.e., check the dynamic property (D2) directly. We will also term the dynamic
property (D2) the boundary property. It can be shown that
the boundary property holds for sufcient damping systems, whereas it may not hold for low damping systems.
The issue of how to determine the critical damping value
above which the boundary property holds remains open.
The critical damping value seems to depend on a variety of
factors, including network topology, loading condition, and
system models used. To overcome this issue, we propose
the development of a group-based BCU method.
We have observed, through our intensive numerical simulations, that the controlling UEPs computed by the BCU
method with respect to a set of contingencies tend to be
close to each other. These controlling UEPs are close to each
other in the state space, whereas the locations where the
faults of the set of contingencies occur are close in the geographical sense. These controlling UEPs are said to form
a group. These contingencies are referred to as a group of
coherent contingencies.
The idea behind the development of the group-based
BCU method is based on observations that the contingency list for transient stability assessment is composed
of groups of coherent contingencies. Some groups may contain a large number of contingencies, whereas others may

contain a small number. This idea is similar, but not related, to the ideas behind the development of dynamic network reduction methods, which are based on the observation of the formation of coherent generators after a contingency. Coherency is an observed phenomenon in power
systems where certain generators tend to swing together
after a disturbance.
The concept of a group of coherent contingencies will
prove to be useful in several applications such as corrective control and preventive control. The coordinates of the
controlling UEP in each group of coherent contingencies
provide useful information on how to design controls to stabilize a power system or to enhance stability with respect
to a set of contingencies.
Extensive computation experience reveals that if the
controlling UEP (CUEP) of the reduced-state system lies
on the stability boundary of the original system, then it is
indeed the CUEP of the original system. This observation,
which is very important, brings up an important numerical question, i.e., how to check whether or the CUEP of the
reduced-state system lies on the stability boundary of the
original system. This property is referred to as the boundary property of the UEP. By checking the boundary property, one can ascertain whether the UEP of the reducedstate system computed by the BCU method is the controlling UEP of the original system, without the need of checking the one-parameter transversality condition. It seems
that the only numerical method capable of checking the
boundary property is the one based on an iterative timedomain process.
An effective time-domain process to check the boundary property for the entire group of coherent contingencies, rather than just for on contingency, has been developed. By checking the boundary property, one can ascertain
whether the UEP of the reduced-state system computed
by the BCU method is the controlling UEP of the original system, without needing to check the one-parameter
transversality condition. To assure the correct grouping of
coherent contingencies, we have introduced the concept of
SEP separation. This concept seens effective for identifying whether contingencies in the same group are correctly
grouped. In addition, by virtue of SEP separation, contingencies within each group can be quickly regrouped. Once
a group of coherent contingencies has been formed, one
only needs to concentrate on the contingencies with the
largest and smallest SEP separation in the same group. In
this manner, a complete check of the boundary property for
each contingency in each group can be avoided and a great
deal of computational work can be saved.
The group-based BCU method has several advantages
over any existing direct stability methods. For instance,
the group-based BCU method ensures the reliability of the
BCU method. In addition, the group-based BCU method
can reduce the conservativeness of the BCU method. The
method captures the inherent characteristics of coherent
contingencies. It reduces the large number of contingencies, whose corresponding CUEP boundary property needs
to be checked, to a small number. The group-based BCU
method is a strict, systematic, yet reliable method to perform stability assessment for a complete list of contingencies. Compared with the conventional TSA procedure, the

Power System On-Line Transient Stability Assessment

increase of computational time of the group-based BCU

method is mild because of the development of contingency
reranking by the SEP separation in each coherent group.
BCU CLASSIFIERS
We present a sequence of seven (improved) BCU classiers
for on-line dynamic contingency screening, developed in
Refs. 31, 33, and 46. Improved BCU classiers are designed
to meet the ve requirements for dynamic contingency
screening. In particular, the BCU classiers can achieve
absolute capture of unstable contingencies, i.e., no unstable (single-swing or multiswing) contingencies are missed.
In other words, the ratio of the captured unstable contingencies to the actual critical contingencies is 1 for both test
systems. Furthermore, the yield of dropout, i.e., the ratio
of dropped-out stable contingencies to actual stable contingencies), of BCU classiers is very high. These simulation
results reveal that the proposed improved BCU classiers
can be highly reliable and effective for on-line dynamic security assessments.
The analytical basis of BCU classiers is based mainly
on the three steps of the BCU method and the dynamic
information derived during the computational procedure
of the BCU method. A large majority of the computational
efforts required in the improved BCU method are involved
in computing the three important state points: the exit
point (step 1), the minimum gradient point (step 2), and
the controlling UEP (step 3). Useful stability information
can be derived from these three points for developing effective schemes for dynamic contingency screening. We next
present the design of each BCU classier along with its
analytical basis.
Classier I: (Classier for SEP Problem)
This classier is designed to screen out potentially unstable contingencies. The basis for this classier is insufciency in the size of the post-fault stability region or in the
extreme case, the nonexistence of a post-fault stable equilibrium point. This is explained as follows. This classier
also checks whether a network island is formed after the
contingency.
For direct methods to be applicable, the following three
conditions need to be satised: (1) The post-fault equilibrium point is asymptotically stable, (2) the pre-fault stable
equilibrium point so and the post-fault equilibrium point s
are close to each other (so that using a nonlinear algebraic
solver, such as the Newton method, with so as the initial
guess, will lead to s ), and (3) the pre-fault stable equilibrium point so lies inside the stability region of the postfault equilibrium point s . If the pre-fault SEP lies outside
the stability region of the post-fault SEP, s , it is very likely
that the post-fault trajectory will not approach s , and is,
hence, potentially unstable. In this classier, two indices
are designed to identify the contingencies that have the
convergence problem of computing post-fault stable equilibrium points.

Ismax : the maximum number of iterations in computing the (post-fault) stable equilibrium point.

17

smax : the maximum angle difference between the prefault stable equilibrium point and the computed (postfault) stable equilibrium point.
Classier II (Highly Stable Classier)
This classier is intended to screen out highly stable contingency cases. Additional stability analysis is unnecessary
for highly stable contingencies. Screening out highly stable
contingencies can greatly improve the goal of high yield for
dynamic contingency screening. If the PEBS crossing cannot be found in the time interval [0, Texit ], and if the potential energy difference Vp ((Texit )) is greater than zero but
less than the threshold value Vpel , and if the maximum angle difference smax is less than a threshold value, then the
contingency case is highly stable and no further analysis
is needed.
Classier III (Classier for Exit Point Problem)
A key step in the BCU method is to integrate the (postfault) state-reduced system starting from the exit point to
nd the minimum gradient point that will be used as an
initial guess for computing the controlling UEP. A problem,
called the minimum gradient point problem, may arise during the integration of the state-reduced system. The problem is described by the following: (1) there is no minimum
gradient point in the simulated trajectory of the (post-fault)
state-reduced system, or (2) the minimum gradient point
lies in such a region that another UEP, instead of the controlling UEP, is obtained when a nonlinear algebraic solver
is used to solve

n


fi () = 0. The causes of the minimum

i=1

gradient point problem can be explained from a computational viewpoint. However, the minimum gradient point
problem usually damages the effectiveness and accuracy
of the BCU method.
Classier IV (Classier for Stability-Boundary-Following
Problem)
This classier is intended to screen out potentially unstable contingencies based on some dynamic information during the minimum gradient point search. If the
stability-boundary-following fails during the minimal gradient point search, then it indicates the CUEP cannot be
found by the BCU method for the study contingency and
the contingency is sent to the time-domain simulation program for additional analysis.
Classier V (Classier for Convergence Problem)
This classier is designed to detect the convergence problem of computing the controlling UEP. In this classier, the
maximum number of iterations, say Iumax , in computing the
controlling UEP starting from the minimum gradient point
is used to detect such a problem. If the required number
of iterations is more than a prespecied number, then the
corresponding contingency is viewed as having a numerical
divergence problem and is classied as unstable.
The convergence region of the Newton method is known
to have a fractal boundary. Using the Newton method, it

18

Power System On-Line Transient Stability Assessment

has been observed that the region of the starting point that
converges to a stable equilibrium point is more signicant
than that of a unstable equilibrium point such as the controlling UEP. Thus, in regular power ow calculation, the
initial guess can be chosen near the stable equilibrium
point to safely lie within the convergence region so that,
after a few iterations, it converges to the desired stable
equilibrium point. This explains why the fractal nature of
the convergence region of Newton method has been unnoticed in power ow study for so long. As power ow study
has been expanded to compute unstable equilibrium points
for applications such as direct transient stability analysis
and low-voltage power ow solutions for voltage collapse
analysis, the fractal nature and the different size of the
convergence region have become more pronounced. Unfortunately, this nature must be taken into account when a
unstable equilibrium point is to be sought.
Classier VI (Classier for Incorrect CUEP Problem)
The problem is described as follows: It converges to a wrong
controlling UEP; i.e., the minimum gradient point lies in
such a region that another UEP, instead of the controlling
UEP, is obtained when a nonlinear algebraic solver is used
to solve

n


 f i () = 0. In this classier, both the coordi-

i=1

nate of the obtained UEP and the angle difference between

the MGP and the obtained UEP are used as indices to detect the problem.
Classier VII (Controlling UEP Classier)
The remaining unclassied contingencies are then sent to
BCU classier VII for nal classication. This classier
uses the energy value at the controlling UEP as the critical energy to classify each remaining contingency as (denitely) stable or (potentially) unstable. If the energy value
at the fault clearing time is less than the energy value at
the controlling UEP, then the corresponding contingency
is (denitely) stable; otherwise it is (potentially) unstable.
The theoretical basis of this classier is the CUEP method.
The index used in this classier is the energy value at the
fault clearing time, whereas the threshold value for this
index is the energy value at the controlling UEP.
In summary, given a list of credible contingencies to
the seven BCU classiers, the rst classier is designed
to screen out those contingencies with convergence problems in computing post-fault stable equilibrium points. The
second and third classiers, based on Step 1 of the BCU
method, are the fastest ones. They use the energy value at
the exit point on the stability boundary of the reduced-state
model as an approximation for the critical energy. The second classier is designed to drop those contingencies that
are highly stable, whereas the third is designed to screen
out those contingencies that may cause computational difculties for the BCU method and, hence, may damage the
reliability of the following BCU classiers. The fourth classier screens out those contingencies that cause failure in
nding the MGP. The fth classier screens out the contingencies with the problem of converging to the controlling
UEP. The sixth classier drops those contingencies with

the problem of incorrect CUEP. The seventh classier uses

the energy at the controlling u.e.p as the critical energy to
classify every contingency left over from the previous classiers into two classes: stable contingencies and unstable
contingencies. This classier is based on Step 3 of the BCU
method.
Contingencies that are classied as denitely stable at
each classier are eliminated from additional analysis. It
is because of the denite classication of stable contingencies that considerably increased speed for dynamic security assessment can be achieved. Contingencies that are
either undecided or identied as unstable are then sent
to the time-domain transient stability simulation program
for further stability analysis. Note that the conservative
nature of the BCU method guarantees that the results
obtained from the seven dynamic contingency classiers
are also conservative; i.e., no unstable cases are misclassied as stable. Classifying a stable contingency, either rstswing or multiswing, as unstable is the only scenario in
which the BCU classiers give conservative classications.
From a practical viewpoint, it is worth noting that a
time-domain simulation program is needed to further analyze those contingencies that are only dropped out from
Classiers I, III, IV, V, and VI. Therefore, the efciency of
the proposed BCU classiers depends on the ratio of those
contingencies screened out from Classiers II and VII with
respect to the total stable contingencies, i.e., the yield of
drop-out of stable contingencies. Note that the number of
stable contingencies is not a criterion for evaluating performance because it depends on several factors, among which
the loading condition, network topology, and contingency
selection all play an important role. The seven BCU classiers perform the process of dynamic contingency screening
in a sequential order.
Numerical Studies
The improved BCU classiers has been extensively evaluated on a practical power system transient stability model.
A total of 507 contingencies on the test system with heavy
loading conditions and ZIP load model and a total of 466
contingencies on the test system with medium loading conditions and non-smooth load model were applied. The type
of faults considered in the evaluation were three-phase
faults with fault locations at both generator and load buses.
Some contingencies are faults that were cleared by opening double circuits, whereas others are faults that were
cleared by opening the single circuit. Two load models were
employed in the simulation: the non-smooth load model
and the ZIP load model with the composition of the 20%
constant current, 20% constant power, and 60% constant
impedance. Both severe and mild faults were considered.
All faults were assumed to have been cleared after 0.07 s.
A time-domain stability program was used to numerically
verify all classication results. Simulation results on both
systems are presented next.
A summary of dynamic contingency screening by the improved BCU classiers and the time-domain stability program on the test system with heavy-loading condition and
ZIP load model for the undamped factor and damped factor
is displayed in Table 1 and Table 2, respectively. A summary

Power System On-Line Transient Stability Assessment

19

Table 1. BCU classiers on a test system (undamped, heavy-loading): ZIP model

Tools
BCU Classiers
Time-Domain

Results
Drop-Out cases
Stable
Unstable

I (U)
83
6
77

II (S)
6
6
1

III (U)
0
0
0

IV (U)
2
2
0

V (U)
12
12
0

VI (U)
1
1
0

VII (S)
378
378
0

VII (U)
25
17
8

Total
507
422
85

VII (U)
26
18
8

Total
507
425
82

Table 2. BCU classiers on a test system (damped, heavy-loading): ZIP model

Tools
BCU Classiers
Time-Domain

Results
Drop-Out cases
Stable
Unstable

I (U)
83
9
74

II (S)
16
16
0

III (U)
0
0
0

IV (U)
1
1
0

V (U)
11
11
0

VI (U)
1
1
0

VII (S)
369
369
0

Table 3. BCU classiers on a test system (undamped, medium-loading): non-smooth model

Tools
BCU Classiers
Time-Domain

Results
Drop-Out cases
Stable
Unstable

Tools
BCU Classiers
Time-Domain

Results
Drop-Out cases
Stable
Unstable

I (U)
26
4
22

II (S)
8
8
0

III (U)
0
0
0

IV (U)
4
4
0

V (U)
4
4
0

VI (U)
0
0
0

VII (S)
419
419
0

VII (U)
5
5
0

Total
466
444
22

Table 4. BCU classiers on a test system (damped, medium-loading): non-smooth model

I (U)
26
4
22

II (S)
11
11
0

III (U)
0
0
0

of dynamic contingency screening on the test system with

medium-loading and non-smooth load model for undamped
factor and damped factor is displayed in Table 3 and Table
4, respectively. A detailed explanation is presented below.
1. Test system with heavy-loading. For the test system
with heavy-loading conditions, ZIP load model, and undamped effect, we summarized the evaluation of BCU
classiers on a total of 507 contingencies in Table 1.
Given a total of 507 contingencies sent to the BCU classiers, the rst BCU classier dropped out 83 cases
and classied them to be unstable. These 83 cases were
numerically veried by the time-domain stability program. Among these cases 77 were indeed unstable according to the time-domain stability program and 6
were stable. The remaining 424 contingencies were sent
to the second BCU classier for another classication.
This classier dropped 6 cases that were classied to
be stable, and they were indeed stable according to the
time-domain stability program. The remaining 418 contingencies were sent to the BCU classier III, which
screened out 0 unstable cases. The remaining 418 contingencies were sent to the BCU classier IV, which
screened out 2 unstable cases. Among these contingencies, according to the time-domain stability program,
2 cases were stable. The fth BCU classier screened
out 12 contingencies as unstable. The BCU VI classier
screened out 1 contingency, which was classied as unstable. This contingency, however, is stable, according to
the time-domain stability program. The remaining contingencies entered the last BCU classier for nal classication. Among them, 378 cases were classied to be
stable and all of these were veried by the time-domain
stability program to be indeed stable; 25 cases were classied to be unstable. Among these cases 8 were indeed
unstable and 17 were stable, as veried by the timedomain stability program. Similar explanations apply

IV (U)
4
4
0

V (U)
3
3
0

VI (U)
0
0
0

VII (S)
418
418
0

VII (U)
4
4
0

Total
466
444
22

to Table 2, which summarizes the evaluation of BCU

classiers on a total of 507 contingencies on the same
test system with damping effect.
2. Test system with medium loading. For the test system with medium-loading conditions, non-smooth load
model, and undamped effect, we summarized the evaluation of BCU classiers on a total of 466 contingencies
in Table 3. Given a total of 466 contingencies sent to the
BCU classiers, the rst BCU classier dropped out 26
cases and classied them to be unstable. These 26 cases
were numerically veried by the time-domain stability
program. Among these cases 22 were indeed unstable
according to the time-domain stability program and 4
were stable. The remaining 440 contingencies were sent
to the second BCU classier for another classication.
This classier dropped 8 cases, which were classied
to be stable, and they were indeed stable according to
the time-domain stability program. The remaining 432
contingencies were sent to the BCU classier III, which
screened out 0 unstable cases. The remaining 432 contingencies were sent to the BCU classier IV, which
screened out 4 unstable case. These 4 cases according
to the time-domain stability program were stable. The
fth BCU classier screened out 4 contingencies. Those
contingencies were classied unstable. Of which, 4 contingencies were, however, all stable. The BCU VI classier screened out 4 contingencies, which were classied
as unstable. The remaining 424 contingencies were sent
to the BCU classier VI, which screened out 0 unstable
cases. The remaining 424 contingencies were sent to the
last BCU classier for nal classication. Among them,
419 cases were classied to be stable and all of these
were veried by the time-domain stability program to
be indeed stable; 5 cases were classied to be unstable.
Of which, they were however all stable. Similar explanations apply to Table 4, which summarizes the evaluation

20

Power System On-Line Transient Stability Assessment

of BCU classiers on a total of 466 contingencies on the

test system with damping effect.
Performance Evaluation
Absolute Capture and Drop-Out. The BCU classiers
met the requirements of absolute capture of unstable contingencies on a total of 1946 contingencies. The capture ratio (the ratio of the captured unstable contingencies to the
actual contingencies) is 1.0. In other words, the BCU classiers capture all unstable contingencies as summarized
in Table 5.
High Drop-out Stable Contingencies. The yield of dropout (the ratio of the dropped-out stable contingencies to
the actual stable contingencies by the BCU classiers) is
90.99% (heavy, ZIP-model, undamped), 90.58% (heavy, ZIP
model, and damped), 96.17% (medium, non-smooth load
model, and undamped), and 96.62% (medium, non-smooth
load model, and damped), respectively, as summarized in
Table 5.
Off-Line Calculations and Robust Performance. It should
be pointed out that the same threshold values for the six
BCU classiers were applied to these 1946 cases. The computational effort required in each BCU classier is different from each other. In addition, as the proposed BCU classiers are connected in a sequential order, the total computational effort required to screen out a contingency (stable
or unstable) by a BCU classier is the summation of the
computational effort required in each BCU classier preceding and including the BCU classier. For instance, the
total computational effort required to screen out a contingency by the BCU classier III is the summation of the
computational effort required in BCU classier I, II and
III.
TEPCO-BCU FOR ON-LINE TSA
TEPCO-BCU is an integrated package developed for fast
and yet exact transient stability assessment (including ac-

curate energy margin calculation and controlling UEP calculations) of large-scale power systems for on-line mode,
on-line study mode, or off-line planning mode [33,63,66].
The architecture of TEPCO-BCU for on-line TSA is presented in Figure 8. Two major components exist in this
architecture: a set of BCU classiers for dynamic contingency screening and a fast and reliable time-domain transient stability simulation program and a BCU-guided timedomain method. When a new cycle of on-line TSA is warranted, a list of credible contingencies, along with information from the state estimator and topological analysis,
are applied to the dynamic contingency screening program
whose basic function is to screen out contingencies that are
denitely stable and to screen out contingencies that are
potentially unstable.
BCU classiers screen out stable contingencies, which
are then eliminated from additional analysis. BCU classiers also screen out potentially unstable contingencies,
which are sent to the fast time-domain stability analysis
program, stage II of TEPCO-BCU, for nal verication and,
if necessary, further analysis. Thus, the slightly conservative nature of BCU method and BCU classiers are remedied. The remaining contingencies that are undecided by
BCU classiers are then sent to the fast time-domain stability program for detailed stability analysis.
It is the ability to perform dynamic contingency screening on a large number of contingencies and to lter out
a much smaller number of contingencies requiring further analysis that make on-line TSA feasible. The block
function of control actions decisions determines whether
timely post-fault contingency corrective actions such as automated remedial actions are feasible to steer the system
away from unacceptable conditions to an acceptable operating state. If appropriate corrective actions are not available, the block function of preventive actions determines
the required pre-contingency preventive controls such as
real power redispatches or line switching to maintain the
system stability should the contingency occur.
The algorithmic methods behind TEPCO-BCU include
the BCU method [46, 47], BCU classiers [31, 67], improved
energy function construction [35], and the BCU-guide

Table 5. Performance evaluation of BCU classiers on a test system with four different operating and modeling conditions: heavy, medium, ZIP load, and
non-smooth load

#
1
2
3
4
5

Conditions/requirements
Absolute capture of unstable contingencies
High yield of stable contingencies
Litile off-line computations
High speed
Robust performance

Heavy/undamped/ Heavy/damped/
Medium/undamped/
Medium/damped/
ZIP load model
ZIP load model non-smooth load model non-smooth load model
100%
100%
100%
100%
90.99%
90.58%
96.17%
96.62%
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

Table 6. The average time per contingency per processor and the average time per contingency per node calculated from the total CPU time
Number of nodes
1 node
2 node

Clock time duration

118 seconds
61 second

Average time per node

0.59 seconds
0.31 seconds

Number of CPUs
2 CPUs
4 CPUs

Average time per processor

1.18 seconds
1.22 seconds

Table 7. The average time per contingency per processor/per node

Number of CPUs
2 CPUs
4 CPUs

Total processing time

211.7 seconds
209.3 seconds

Average time per processor

1.059 seconds
1.046 seconds

Number of compute nodes

1 node
2 node

Average time per node

0.529 seconds
0.523 seconds

Power System On-Line Transient Stability Assessment

21

Table 8. The wall clock time calculated to process 3000 contingencies, (the timings for the 1-node and the 2-node congurations are calculated for the 3000
contingencies directly from the test results)

Number of computer nodes

1 node
2 node
10 nodes

Reference
Test results
Test results
Conservative estimate

Wall clock time

29.5 minutes
15.5 minutes
3.1 minutes

Detailed time-domain simulation of selected contingencies

It is true that most contingencies in a contingency list
associated with a well-planned power system should be
stable. Furthermore, some of these stable contingencies
are highly stable in the sense of large CCTs (critical clear
times). For each highly stable contingencies, one may not
be very interested in its degree of stability or in its accurate energy margin other than interested in the assurance
of its being indeed highly stable. On the other hand, all unstable contingencies must be all correctly identied. From
an analysis viewpoint, the exact energy margin of each unstable contingency may not be important. From a control
viewpoint, the exact energy margin of each unstable contingency and its sensitivity with respect to control variables can be useful for developing an effective control for
preventing the system from instability should the contingency occur. As to a marginally stable or critically stable
contingency, its exact energy margin provides the information regarding how far the system is away from transient
instability once the contingency occurs and the sensitivity
of energy margin with respect to control actions provide
useful information for deriving (enhancement) control to
increase the system distance to transient instability.
Figure 7. The architecture of BCU classiers.

time domain method [33]. Several advanced numerical

implementations for BCU method have been developed
in TEPCO-BCU. The improved energy function construction has been developed to overcome the long-standing
problem associated with the traditional numerical energy
function, which has suffered from severe inaccuracy.
Another distinguishing feature of TEPCO-BCU is that
it provides useful information regarding derivation of
preventive control against insecure contingencies and of
enhancement control for critical contingencies.
The main functions of TEPCO-BCU include the following:

Fast screening of highly stable contingencies

Fast identication of insecure contingencies
Fast identication of critical contingencies
Computation of energy margin for transient stability
assessment of each contingency

BCU-based fast computation of critical clearing time
of each contingency

Contingency screening and ranking for transient stability in terms of energy margin or critical clearing
time

BCU Guided Time-Domain-based Methods

The existing direct methods may not be able to compute an
accurate energy function value for every contingency. The
alternative is the time-domain based method for computing the energy margin. The task of how to derive an energy
function value from a time-domain simulated trajectory is
a practical one. Theoretically speaking, the exact energy
margin is the difference between the energy value at the
exit point of the original (post-fault) system and the energy value at the fault clearance point. The exit point of the
original system is the intersection point between the (sustained) fault-on trajectory and the stability boundary of the
(post-fault) power system. It is well known that the task of
computing the exit point of the original system is very time
consuming and requires several time-domain simulations.
Hence, the task of computing the exact energy margin is
challenging.
Given a contingency on a power system, the energy margin, an indicator for transient stability and a measure for
the degree of stability/instability, for the given contingency
is dened by the following formula:
V = Vcr Vcl

(19)

where V is the energy margin, Vcr is the (exact) critical

energy with respect to the given fault, and Vcl is the energy
at the fault clearing time. Physically speaking, the critical
energy of a contingency corresponds to the total energy in-

22

Power System On-Line Transient Stability Assessment

Figure 8. The architecture of TEPCO-BCU for on-line TSA.

jected into the fault-on system at the critical clearing time.

Any attempt to develop a method for computing energy
margin (19) will encounter the following difculties

The (exact) critical energy with respect to the given

fault is very difcult to compute.

The (functional) relationship between energy margin

and fault clearing time is nonlinear and difcult to
derive.
Another approach, trajectory sensitivity-based timedomain methods, has been suggested in the literature
[68, 69]. It may appear from the surface that the trajectory sensitivity-based time-domain method might be faster
than regular time-domain based methods. However, for a
practical power system, the task of calculating trajectory
sensitivity with respect to initial conditions always encounters the difculty of formidable dimensionality explosion.
This difculty arises especially for large power system,
and the trajectory sensitivity-based method is not practically applicable to energy margin computations of practical

power systems. We envision that the trajectory sensitivitybased method would be useful in some applications where
only moderate dimensionality explosion is involved.
A BCU-guided time-domain method for accurate energy
margin calculation has been developed and tested on several practical power system models [63]. The method is
reliable and yet fast for calculating energy margins whose
value is compatible with that computed by the controlling
UEP method. The BCU-guided time-domain method uses
a BCU-guided scheme to specify, within a given time interval, a reduced-duration time interval and employs an
one-dimensional search method, such as the golden bisection interpolation algorithm to the specied time interval,
to reduce the total number of time-domain simulations required for nding the CCT, which is then used to compute
critical energy.
The BCU-guided method is highly effective compared
with existing time-domain-based methods: it is reliable
and yet fast for exact stability assessment and energy
margin computations. Another important property is that
the energy margins computed by the BCU-guided timedomain method is comparable with, and yet less than,

Power System On-Line Transient Stability Assessment

exact energy margins, which are computed by an exact

time-domain stability method. The effectiveness can be
attributed to the fact that some information provided by
the BCU method such as the exit point and the minimum
gradient point are fully integrated into the BCU-guided
method to signicantly reduce the duration of time interval within which time-domain stability simulations are
performed.
A comparison study among the BCU-guided method, the
second-kick method, and the exact time-domain method
in terms of accuracy and computational speed was conducted on a practical 200-bus power system model [63].
The following observations were derived from this comparison. For every contingency, the BCU-guided time-domain
method always computes an energy margin that is less
than, and yet close to, that computed by the exact timedomain method. This property indicates the conservativeness of the BCU-guided method in computing the energy
margin. This property, which lies in the spirit of direct
methods, is desirable in practical applications. A comparison between the computational speed of the BCUguided time-domain method and that of the exact timedomain method is roughly the ratio of 1 to 2. The energy margins computed by the BCU-guided time-domain
method are compatible with those computed by the exact time-domain method. Overall, the BCU-guided method
has the fastest computational speed among the three
methods.
Applications to Large-Scale Test System
TEPCO-BCU program has been evaluated on a large-scale
power system consisting of more than 12,000 buses and
1300 generators. In this test data, the system was modeled by a network-preserving network representation. Of
the 1300 generators, 25% are classic modeled generators,
whereas 75% are detail-modeled generators with an excitation system. A contingency list composed of 200 contingencies are considered. Of the 200 contingencies, 2 are
unstable, about 20 are critically stable, and the remaining
are stable.
The performance of TEPCO-BCU on this test system is
summarized as follows. The capture of unstable contingencies by TEPCO-BCU is 100%; i.e., no unstable (single-swing
or multiswing) contingencies are missed. Thus, the ratio of
the number of captured unstable contingencies to the number of actual unstable contingencies is 1. The ratio of the
number of stable contingencies screened out by TEPCOBCU to the number of actual stable contingencies is about
95%. The average computation time per contingency running TEPCO-BCU on a single processor is 1.18 second for
a 3.6-GHz PC.
Parallel TEPCO-BCU
To meet the on-line dynamic contingency screening requirements for large power systems with a large number of
contingencies, TEPCO-BCU needs to be implemented on a
parallel processing architecture. Parallel processing is the
simultaneous execution of the same task (split up and specially adapted) on multiple processors in order to obtain
faster speed. The parallel nature can come from a single

23

machine with multiple processors or multiple machines

connected together to form a cluster. It is well recognized
that every application function benets from a parallel processing across a wide-range of efciency. Some application
functions are just unsuitable for parallel processing.
The test bed system is made up of two IBM 236 IBM
eServer xSeries Servers interconnected by a Gigabit Ethernet Switch. The conguration for each IBM 236 eServer
is as follows: CPU: Xeon 3.6 GHz (Dual processors) with
2-MB L2 cache per Processor, Hyper-Threading Technology and Intel Extended Memory 64 Technology, 1 GB DDR
II SDRAM - ECC - 400 MHz - PC2-3200, Storage Control:
SCSI (Ultra320 SCSI) - PCI-X / 100 MHz (Adaptec AIC7902), and RAM: 1 GB (installed) / 16 GB (max) - DDR II
SDRAM - ECC - 400 MHz - PC2-3200.
The parallel TEPCO-BCU program has been evaluated
on a large-scale power system consisting of more than
12,000 buses and 1300 generators. Of the 1300 generators, 25% are classical modeled generators whereas 75%
are detail-modeled generators with an excitation system.
A contingency list composed of 3000 contingencies are considered. The parallel TEPCO-BCU was run on the test
data to determine the average time needed to process a
contingency for each conguration tested. Two tests were
ran, rst using a single compute-node and then using two
compute-nodes. Time was marked at the beginning of the
test and again when TEPCO-BCU completed the screening
to give the duration of the test, or the wall clock time. The
computation performance regarding the average time per
contingency per node and the average time per contingency
per processor was recorded. The test showed that the parallel implementation of TEPCO-BCU cut the average processing time per node by 50% when a second compute-node
was added.
Test data that were collected during the tests to record
the total CPU time spent during the TEPCO-BCU run on
processing of the contingencies is summarized in Tables
68. The average time per contingency per processor and
the average time per contingency per node calculated from
the total CPU time are also presented in the tables. It is observed that the average time per contingency per processor
remains essentially unchanged irrespective of the number
of processors given uniform testing conditions. The 2-node
and 4-node test comparison is provided to observe the small
degree of variation.
The timings for the 1-node and the 2-node congurations were calculated for the 3000 contingencies directly
from the test results. A 5% overhead was used in the estimation of the 10-node timing, despite the fact that the
testing showed overhead to be in the vicinity of 3%, in order to be on the conservative side. In addition, as the test
dataset resulted in a high number of unstable and critical
stable cases, it is likely that datasets that produce a more
typical percentage of stable cases will result in even faster
performance results for the TEPCO-BCU fast screening.

CONCLUDING REMARKS
On-line transient stability assessment (TSA) is an essential tool needed to obtain the operating security limits at

24

Power System On-Line Transient Stability Assessment

or near real time. In addition to this important function,

power system transmission open access and restructuring
further reinforce the need for on-line TSA, as it is the base
upon which available transfer capability, dynamic congestion management problems, and special protection systems
issues can be effectively resolved. There are signicant engineering and nancial benets to be expected from on-line
TSA.
After decades of research and development in the
energy-function-based direct methods and the timedomain simulation approach, it has become clear that the
capabilities of direct methods and that of the time-domain
approach complement each other. The current direction of
development is to include appropriate direct methods and
time-domain simulation programs within the body of overall power system stability simulation programs. For example, the direct method provides the advantages of fast computational speed and energy margins, which make it a good
complement to the traditional time-domain approach. The
energy margin and its functional relation to certain power
system parameters form an effective complement to develop tools, such as preventive control schemes for credible
contingencies that are unstable and to develop fast calculators for available transfer capability limited by transient
stability. The direct method can also play an important role
in the dynamic contingency screening for on-line transient
stability assessment.
This chapter has presented an overview of stateof-the-art methodology and effective computational
methods useful for on-line TSA. The current direction of
development for on-line TSA is to combine a reliable and
fast direct method and a fast time-domain method into an
integrated methodology to take advantage of the merit of
both methods. TEPCO-BCU has been developed under this
direction by integrating the BCU method, BCU classiers,
and the BCU-guide time domain method. Several advanced numerical implementations for BCU method have
been developed in TEPCO-BCU. The current version of
TEPCO-BCU can perform exact stability assessment and
accurate energy margin computation of each contingency
of large-scale power systems. Exact stability assessment
is meant to classify stable contingencies as stable and
unstable contingencies as unstable, whereas accurate
energy margin computation is meant to give accurate
critical clearing time of each contingency of large-scale
power systems. The evaluation results indicate that a
parallel version of TEPCO-BCU works well with reliable
transient stability assessment results and accurate energy
margin calculations on a 12,000-bus test system with a
contingency list of 3000 contingencies.
The group-based BCU method raises and addresses the
issue of how to rigorously verify the correctness of the TSA
results. In the past, this issue has been neglected because
of the great computational efforts and difculty involved.
Given a credible list of contingencies, the TEPCO-BCU system can fast screen out critical contingencies. This capability in conjunction with some relevant functions can lead to
several practical applications. These relevant functions include the energy function method and the controlling UEP
coordinates and their sensitivities with respect to parameters or control actions. One such application is the devel-

opment of a dynamic security constrained optimal power

ow method. A preliminary dynamic security constrained
OPF algorithm is realized based on the TEPCO-BCU engine [66]. Several applications based on TEPCO-BCU engine will be developed in the future.
As the size of power system analysis data increases
due to, say, deregulation, it becomes clear that effective
data-handling schemes, data verication and correction,
and graphical user interface (GUI) are important for
power system analysis tools. It is also clear that the
approach of detailed representation for the study system
and adequate and yet simplied representation for the
external system is well accepted and several methods
for reducing external systems have been proposed. In
this regard, the data handling of the separated power
system data, i.e., the data for the study system and the
data for the external system, can be very complicated and
error-prone with the conventional text-based format. In
Ref. 70, effective data-handling schemes and GUI have
been developed for an integrated power system analysis
package. Two reduction techniques are also presented: one
is a static reduction technique for power ow analysis, and
the other is a dynamic reduction technique for transient
stability analysis and small-signal analysis.
Although current power system networks cannot completely prevent disastrous cascading, their ability to manage power system disturbances can be considerably enhanced. Power systems have been relying mostly on protection systems and discrete supplementary control schemes
to manage disturbance and prevent disastrous cascading.
This practice needs further enhancement in both scope and
depth. On-line TSA should join this practice. The design
of protection systems and discrete supplementary control
schemes have been often based on passive and static
considerations. The parameter settings of protection systems and discrete supplementary control schemes are not
adaptive to system operating conditions and network congurations. Moreover, the design and parameter settings
of protection systems and discrete supplementary control
schemes do not take into account system dynamic behaviors. Consequently, several adverse behaviors of protection
systems and discrete supplementary control systems occur
that cause service interruption of electricity and system
blackouts. These behaviors include (1) unnecessary relay
trippings (relays overact to stable swings) and (2) unnecessary distance relay trippings caused by system low voltage
and heavy loading conditions. Increased coordination between on-line TSA and the parameter settings of protection
systems and between that and discrete supplementary
control schemes should help eliminate these adverse
behaviors and make protection systems really adaptive.
Traditionally, an energy management system (EMS)
performs generation scheduling and control of the electrical power output of generators so as to supply the continuously changing customer power demand in an economical
manner. All system analysis and decision making in EMS
are all based on static considerations. A linkage between
EMS and protection systems, discrete supplementary control systems, and special protection systems has been missing. This linkage can be established using on-line measurements, static analysis results available at the EMS, and

Power System On-Line Transient Stability Assessment

additional required measurements, such as wide-area measurements, to design and develop new needed functions,
both static and dynamic security, for EMS. These new functions can be utilized to develop hierachical and adaptive relays and adaptive discrete supplementary controllers and
adaptive special protection systems by periodically broadcasting updated information of both static and dynamic
security assessment results derived at the EMS to selected
protection systems and generator sites for adaptive protection systems. This updated static and dynamic security
assessment information can be used to improve the rules
residing in the relays and control schemes of discrete supplementary controller and/or special protection systems so
that the overall system will greatly improve the ability to
manage disturbance and to prevent disastrous cascading.

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Further Reading
T. Takazawa, Y. Tada, H.-D. Chiang, and H. Li, Development of
parallel TEPCO-BCU and BCU screening classiers for on-line
dynamic security assessment, The 16th Conference of the Electric Power Supply Industry, Mumbai India, Nov. 2006, 610.
Y. Tada, A. Kurita, M. Masuko, Y. Takahara, and K. Koyanagi,
Development of an integrated power system analysis package, Power System Technology, 2000. Proceedings, PowerCon2000. International Conference, Perth Australia, Dec. 2000,
47.
Y. Tada, T. Yamada, T. Takazawa, Y. Takahara, and T. Shishido,
Enhancement of data handling in integrated power system
analysis package, named IMPACT, using information technologies, International Power Engineering Conference, IPEC 2003,
Singapore, Nov. 2003, 2630.
Y. Tada, A. Kurita, T. Ryuya, and H. Okamoto, Development of
voltage stability constrained OPF as one of the functions of the
integrated power system analysis package, Named IMPACT,
IFAC Symposium on Power Plants & Power Systems Control,
Seoul, Korea, Sep. 2003, 1519.

27

J. L. Jardim, C. S. Neto, and W. T. Kwasnicki, Design features of

a dynamic security assessment system. IEEE Power System
Conference and Exhibition, New York, Oct. 1316, 2004.
F. A. Rahimi, M. G. Lauby, J. N. Wrubel, and K. L. Lee, Evaluation
of the transient energy function method for on-line dynamic
security assessment, IEEE Trans. Power Systems, Vol. 8, No.
2, May 1993, pp. 497507.
Electric Power Research Institute, Users Manual for DIRECT 4.0,
EPRI TR-105886s, Palo Alto, CA, Dec. 1995.
F. A. Rahimi, Evaluation of Transient Energy Function Method
Software for Dynamic Security Analysis, Final Report RP
4000-18, EPRI, Palo Alto, CA, Dec. 1990.
IEEE Committee Report, Transient stability test systems for direct methods, IEEE Trans. Power Systems, Vol. 7, Feb., 1992,
pp. 3743.
M. A. El-kady, C. K. Tang, V. F. Carvalho, A. A. Fouad, and V. Vittal,
Dynamic security assessment utilizing the transient energy
function method, IEEE Trans. Power Systems, Vol. PWRS-1,
1986, pp. 284291.

Dr. HSIAO-DONG CHIANG

Dr. YASUYUKI TADA
Dr. HUA LI
Cornell University, Ithaca, NY
Tokyo Electric Power Company,
Tokyo, Japan
Bigwood Systems, Inc., Ithaca,
NY

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

PROGRAMMABLE FILTERS
This article is about programmable electric filter circuits. It is a practical review and involves no difficult
mathematics, although it does assume some familiarity with filter terminology. It does not cover digital filters,
which tend to be programmable by definition, since they are usually the direct result of running a computer
program or at least some kind of number-crunching algorithm.
Programmable filters have characteristics which can be intentionally adjusted to provide useful and
desired results, by means of external control inputs which can be of many different forms, both analog and
digital.
The circuits described in detail here are programmable in the sense that the resulting response of the
filter is a known function of the adjustment process employed. A wider class of filters, which might be termed
variable rather than programmable, have response parameters which can be changed by altering something,
but perhaps in a way which is an imprecise function of variables under the users control, or which varies in
an unknown way between different units from a production batch; these techniques are not covered in depth
here.

The Need for Programmability in a Filter Circuit

In many applications, the response shape, passbands, and stopbands of filter circuits needed in the design can
be specified in advance; these frequencies are fixed numbers, the same for every unit which is manufactured
and unchanging no matter what the circumstances of use. For such applications, fixed frequency filters are
utilized, and design procedures for such circuits are well established.
Applications involving some form of filtering are familiar to everybody; for instance, a radio receiver can
be viewed as a form of filter because its job is to pick out a carrier signal on which some wanted information
has been impressed by the sender, in the presence of huge amounts of competing unwanted information. A
radio receiver which could only receive one station out of the thousands transmitted would be of little use, and
so any usable radio can in this sense be thought of as a programmable filter.
There are many other applications where filtering is required, in order to discriminate between some
wanted signals and some unwanted ones on the basis of their frequencies, but where the characteristics of this
filtering need to be changed in response to some changing mode of application or in response to an external
circumstance.
The primary form of parameter adjustment covered here will be that of the cutoff frequency of the
filter; in other words, it is assumed that when the filter is adjusted, its intrinsic response shape is not to be
altered. For example, if the desired response shape is described by a Chebychev lowpass function, then the
flatness and ripple in the passband should not be affected simply by changing the actual value of the passband
cutoff frequency. In some cases, programmability of the response shape itself is also required, such as in the
programmable audio equalizer described subsequently.
1

PROGRAMMABLE FILTERS

The choice between a fully programmable filter , or simply a circuit in which some parameter can be
varied somewhat, generally depends on whether it is possible to determine, by examining the result of filtering
the signal, whether the filtering was effective. Another way of saying this is that if a form of closed-loop control
is possible, then it may be possible to get away with an unpredictable adjustment method. If only open-loop
operation is possible, then the adjusting technique needs to be correct because an iterative approach to getting
the response correct is not possible.
Another frequent feature of the need for programmability, as distinct in this case from selectability, is
that the actual operational parameter requiredfor instance the cutoff frequencymay not be known until
the actual point in time at which it has to be set.
To return again to the radio analogy, a closed-loop techniquelistening to the radio and judging whether
the desired station is correctly tunedenables a rough-and-ready adjustment method to be used, one for
which the manufacturer may not have made any promises about what the position of the tuning dial actually
means. In contrast, a more modern radio might enable you to punch in the frequency of the station with
such precision, and to set it with such accuracy, that the tuning is achieved with no correction necessary. This
is open-loop operation and requires different (and more accurate) techniques whether the system is a radio or,
say, an industrial data acquisition process.

Programmable Elements Available for Filter Parameter Adjustment

We now assume that we are to attempt to control the behavior of a single filter circuit in some way. Naturally,
the brute force method of achieving a range of filter responses is to design a fixed filter circuit for each of the
desired outcome responses and build them all into the equipment, with a big selector switch. This is generally
likely to work (assuming no unexpected interactions between the circuits) but is rarely likely to be efficient for
component cost, power consumption, or board area consumed and thus it is not usually a serious approach.
The adjustability might be offered to the user in the form of a big front-panel dial, or some form of interface
port to attach to a processor or network. Whatever way the interface is achieved, at some point in the circuit
programmable components of some sort will be required in order to turn the needs of the user into intentionally
adjusted parameters of a filter circuit.
Adjustable or Variable Components. These components generally have no role to play in programmable rather than adjustable filters, but they are useful in certain noncritical circuits. This is because the
control relationship may be known only empirically and may offer poor consistency over batches and perhaps
unknown stability over time and temperature.
Examples are (1) light-sensitive resistors using cadmium sulfide or a semiconductor junction, programmed
using a controllable light source, and (2) rotary resistive potentiometers adjusted with a motor (some form of
positional feedback might be used to improve the accuracy and consistency of this approach).
Note that discrete junction field-effect transistors (FETs) make excellent switches for the techniques of the
next sections, but their analog characteristicsthe region between fully on and fully offare not well-defined
and so it is difficult to make repeatable circuits when used as variable resistances with a programmable gatesource voltage. However, careful matching of individual FETs may produce usable results over a range of up
to a decade (1,2).
Switched Two-terminal Component Arrays. These comprise arrays of fixed two-terminal components (i.e., resistors, capacitors, or inductors) connected together by controllable switches to provide composite
components whose value can be selected from a range of values (but which is constant any time that the
selection is not being changed).
This approach is perhaps the most obvious one; it is similar to the build several complete filters and
select between them method except that it changes less than the entire network of filter components each
time you select a new cutoff frequency. How many components you actually need to change when you change

PROGRAMMABLE FILTERS

Fig. 1. A 4-bit binary-weighted resistor array.

Fig. 2. An 8-bit binary-weighted capacitor array.

the cutoff frequency depends on the filter circuit used; clearly, the fewer the better; this is covered in more
detail in the section entitled Fundamental Restrictions on Programmability.
Binary-Weighted Arrays. A particularly useful technique for constructing programmable components
and it can be capacitors (3) or resistorsis to use a switched array of components with a binary weighting
between the values. A couple of examples will illustrate the point.
Firstly, consider four resistors in series, of value 100
, 200
, 400
, and 800
. Place a controllable
switch in parallel with each resistor, and construct a truth table showing the realized resistance from node 1 to
node 5 for each of the 16 possible 4-bit input control words which are used to control the switches. This shows
that the circuit generates a resistance whose value is 100
multiplied by the value of this digital wordfrom
0
to 1500
in increments of 100
, assuming the switches resistance is negligible (Fig. 1).
Another example is eight capacitors, of value 1 pF, 2 pF, 4 pF, and so on up to 128 pF, each in series with
a switch, such that all capacitors share one common terminal (node 1) and all switches share another (node
10) as shown in Fig. 2. A 256-entry truth table could be constructed, though this is unnecessary because it
should be fairly clear that this circuit will realize a programmable capacitance which can be varied from 0
pF (all switches open) to 255 pF (all switches closed) in steps of 1 pF. Here we are ignoring any capacitance
contribution from the switch elements, which at this level of capacitance can be quite significant.
Programmable two-terminal components can be substituted quite freely in most active (and passive)
filter circuits for conventional components, as long as the limitations of the switch technology do not affect the
circuit performance.

PROGRAMMABLE FILTERS

Fig. 3. An inverting integrator.

The Integrator. Before moving on to the other techniques in this section, let us introduce a versatile
circuit block with great relevance to active filter design, the integrator. The simplest form, the operational
amplifier-based integrator (Fig. 3), uses the virtual earth at the inverting input of an op-amp operating with
feedback, to produce an output voltage which is the time integral of the current flowing through the capacitor:
The input current Ii is determined by the input voltage V i as Ii = V i /R; this same current flows in the capacitor,
resulting in an output voltage of

or

Other mechanisms are possible which turn the applied input voltage into a proportional current which is
applied to the virtual earth, and they can be thought of as having a transresistance equivalent to R in
the equation above. The time constant of the integrator, t, which can also be thought of as determining its
gain, directly determines the frequency behavior of any filter circuit in which the integrator is embedded, and
this time constant can be programmed in various ways other than using a resistor; the following subsections
describe some approaches.
Continuously Variable Transconductances. These consist of circuits integrated on a single substrate are based on the highly predictable and repeatable physics of the bipolar junction transistor [and also
the metal-oxide semiconductor (MOS) transistor operating in its weak inversion region] and produce a controllable attenuation, gain, or conductance.
The bipolar junction transistor has a highly predictable relationship between its output current and its
input voltage. By relying additionally on the very close matching of devices available on a single substrate, it
is possible to produce a range of circuits whose performance can be adjusted accurately enough with externally
applied control voltages or currents that they are useful in the construction of programmable filters. The control
of such circuits is easily arranged because the production of programmable voltages or currents is quite simple.
These circuits tend to be used in the construction of integrators within active filter designs (4).
The OTA. The operational transconductance amplifier (OTA) is a voltage input, current output device
with a programming terminal into which a current is injected which controls the transconductance of the
device (5). Filters based on such programmable transconductances are termed gm C filters and have become
an important technology for the integration of continuous-time filters onto monolithic processes (6,7). OTA
integrated circuits are also available, with the classical example being the CA3080 (8). A programmable

PROGRAMMABLE FILTERS

Fig. 4. Two integrators with gain-tuned time constants. Dynamic range considerations determine the choice between
them. Any form of gain control element can be used.

integrator is particularly easy to implement with an OTA, requiring simply a grounded capacitor attached to
the output.
The VCA or Analog Multiplier. Another device which has found use in programmable filter circuits is
the voltage-controlled amplifier (VCA). The amplifier can actually be either a voltage amplifier or a current
amplifier. A voltage-controlled voltage amplifier with a linear relationship between gain and control voltage is
also known as a four-quadrant voltage multiplier; cascading one of these with a fixed time constant integrator
is one method of producing an integrator with a voltage-controlled time constant; a careful analysis of dynamic
range is required to determine whether the VCA should be located before or after the integrator (Fig. 4). In
either case, the effective time constant te = RC/Gv .
Particularly effective filters can be constructed with the voltage-controlled current amplifier (VCCA) (9)
which once again finds its place in the integrator, this time shown in Fig. 5. The VCCA is interposed between the
resistor R and the virtual earth of the operational amplifier around which the capacitor C provides feedback.
Impressing an input voltage V i on the resistor causes a current V i /R to flow into the VCCA, and the output
current Ia (shown in Fig. 5 as directed toward the VCCA) will therefore be Gc V i /R, where Gc is the current
gain of the VCCA. The current flowing in the integrating capacitor is therefore changed by the same amount,
and hence the time constant of the integrator is changed:

so

PROGRAMMABLE FILTERS

Fig. 5. Noninverting integrator using a voltage-controlled current amplifier.

Fig. 6. A digital potentiometer; the resistance of the selector switches does not affect the accuracy of potential division
between A and B.

This technique can provide very high linearity performance since there is no signal voltage on either the input
or output terminals of the VCCA due to the virtual earth at the input of the operational amplifieronly the
current changes with differing input signals.
Switched Voltage or Current Dividers. These are voltage or current dividers and variable transconductances constructed from switched arrays of resistors, whose division ratio can be altered by applying some
form of control. This might be thought to be simply an extension of the switched two-terminal component array,
but elements which offer attenuation (or gain) are used in quite separate roles in filter circuits from simple
two-terminal impedances and are worth considering separately.
Digital Potentiometers. An electronically switched version of the conventional resistive potentiometer
has become popular; this version consists of a string of resistors connected in series such that each of the
points at which adjacent resistors join can be selected for connection to the wiper terminal (Fig. 6). This type
of circuit is easier to implement in low-cost silicon processes because it is much easier to make a large number
of resistors whose absolute value is not too important but whose matching and tracking is quite critical than
it is to make even a small number of resistors whose value is accurate and stable. As a result, these digital
pots find favor in circuits where their rather unpredictable impedance does not affect the circuit response at
all, this being done by the very stable division ratio afforded by the chain of well-matched resistors; in other
words, these pots are being used purely for their division properties and not as variable resistances.
Digital potentiometers are also available with built-in nonvolatile memory, enabling them to store their
setting when power is removed. This makes them useful for programming filters where the setting needs to be
changed only occasionally (e.g., for calibration purposes).
The R-2R Ladder and the MDAC. Another circuit arrangement of resistors and switching, which can
be used to form a programmable divider for either voltage or current, is the R2R ladder, which is a key
element of a component called a multiplying digital-to-analog converter (MDAC) (10).

PROGRAMMABLE FILTERS

Fig. 7. A 3-bit R2R network controlling an integrator.

The R2R ladder has the useful property that, when fed by an input voltage, the voltage on each successive
node on the ladder is reduced by a factor of exactly 2 from that on the previous node. To see why this is, we first
prove by induction that the input resistance of an R2R ladder which is terminated at its last node by a resistor
of value 2R has itself an input resistance of 2R. Figure 7 shows a single section of the ladder terminated into
2R; by inspection, the resistance from node 2 to ground is the parallel combination of two 2R resistorsin
other words, R. The input resistance measured at node 1 is therefore R + R = 2R, and the voltage at node two
is just V i R/(R + R) or V i /2.
We can cascade as many of these ladder sections as we require; and note that since the voltage at each
successive node is reduced by a factor of 2, then so is the current in each of the 2R resistors. In other words, the
currents in the grounded arms of the ladder form a binary weighted set. A selection of these binary weighted
currents can be routed to the virtual earth of an op-amp instead of to ground, and it can be deployed to program
an integrator with a programmable time constant (Fig. 8 shows a circuit with three branches but MDACs are
available with up to 16 branches, offering very high resolution):

with

where any Dx can equal 0 or 1 depending on whether the branch current is switched to ground or to the op-amp
input.
Since Ii = V i /2R and I2 = Ii /2, I3 = I2 /2, I4 = I3 /2, we have

where here a ranges between 0 and 78 .

The fundamental value of the MDAC resistors is sometimes not known to within a certain tolerance error,
due to the limitations of integrated circuit (IC) processing. The time constant of an integrator made with the
MDAC will similarly suffer from this same error because it is proportional to the reference resistance R (11).

PROGRAMMABLE FILTERS

Fig. 8. A mark:space ratio controlled integrator; any suitable electronic switch can be used for SW1.

One solution to this is to use the MDAC instead in a programmable attenuator which can be used to provide
an adjustable integrator in the manner of Fig. 4(a) or Fig. 4(b).
Time-Domain Switching. This refers to circuits using some form of signal division in the time domain
to manipulate an existing fixed component in order to synthesize a component which appears to have a value
which is dependent on the nature of the controlling signal or clock.
Mark:Space Ratio Control. A technique for varying the apparent value of a resistor is to place it in
series with a switch which is periodically opened and closed at a rate which is much higher than the frequency
of any interesting signals in the circuit (12). In Fig. 8, if the mark:space ratio of the switching waveform is
1:1, it should be clear that the average value of the current which can flow when a voltage is impressed on the
resistorswitch combination is only half that which could flow if the switch were always on. In fact the effective
conductance is simply proportional to the fraction m of time that the switch is on, so Ii = V i m/R. Since this
adjustable mark:space ratio can be generated by a very precise digital divider, it is clear that this can be used
to turn an accurate resistor into an accurate digitally programmed resistor over quite a wide range:

Switched Capacitor Filters. The other, highly significant technique is that of the switched capacitor;
this is an important configuration in modern electronics and is covered elsewhere (see Switched capacitor
networks). However, a brief review of the basic principle should illustrate how this technique relates to the
other methods described here.
Consider Fig. 9, in which the capacitor C1 is switched between positions 1 and 2 by an input clock, which
we shall assume has a 1:1 mark:space ratio. In position 1, the voltage on capacitor C1 rapidly assumes the
value of the input voltage V i (we assume that the switch resistance is low enough for this to happen). When
the switch moves over to position 2, the charge in capacitor C1 is transferred to C2 ; in other words,

Therefore

PROGRAMMABLE FILTERS

Fig. 9. A switched-capacitor integrator.

Since this transfer happens once every period t where t = 1/F s , we can integrate the successive small changes
in V 0 to get

Once again, this circuit is a controllable integrator, and thus it can be used in any active filter circuit which
consists of combinations of integratorsseveral of which are ideal candidates for programmable filters as we
shall now see.

Active Filter Architectures and Programming

This section provides a quick and practically biassed summary. Coverage of particular active filter circuits can
be found in Van Valkenburg (13) and particularly in Moschytz and Horn (14). The two most common forms of
active filter synthesis are the cascade method and the ladder-derived method; this article will focus on cascade
synthesis since it is the most common and practical method for programmable filters.
Filter circuit blocks which have a frequency response which can be described by a pair of poles (and possibly
one or two zeroes) are used as basic building blocks to construct a filter circuit of high order; these blocks are
called second-order filter sections, or sometimes just biquads. Higher-order filter circuits are needed when
greater discrimination is needed between different frequencies in the input signalin common parlance, when
a sharper filter is required. If the filter circuit blocks can be made programmable by using the techniques of
the last section, then several of these blocks can be combined to make a programmable filter with the required
response to do the job.
Some Representative Filter Sections and their Applications. A second-order active filter section
will consist of at least one amplifier [which is usually an op-amp (voltage in, voltage out)], at least two capacitors,
and several resistors. The analysis of the popular sections has been carried out many times, and the results are
widely published. Figures 10, 12, and 13 show three second-order all-pole low-pass filter sections in a format
representative of published filter textbooks (14), and they show equations which relate their component values
and the parameters which the sections are intended to produce. These are expressed here as the pole frequency
wp and the pole quality factor qp , which is the most common way of describing such a section. Sections which
also create a transmission zero are not covered here, but the same principles will apply.
Examples of practical applications are also shown for these filter circuits, but practical considerations
such as component choice and the effect of device imperfections are covered in detail in the section entitled
Design for Manufacturability. Note that there are many more active filter topologies than can be covered by
this article, and the reader is encouraged to seek them out and apply these principles to determine how they
can be programmed.

10

PROGRAMMABLE FILTERS

Fundamental Restrictions on Programmability. Before examining the individual circuit topologies,

it is worth asking the question, How may components need to be altered in a programmable filter? These allpole filters can be completely described by two parameters wp and qp , which are functions of the components
in the filter. It will usually (but not always) be possible to rearrange the expressions so that two selected
component values are a function of all the other component values plus wp and qp , which means that in general
any filter circuit can be set to the required wp and qp by programming just two components. However, the
functional relationship between filter parameter and control code may be highly nonlinear, and there may also
be forbidden regions where parameter values cannot be set.
Circuits which are useful bases for programmable filters therefore need to conform to more stringent
criteria so that the programming approaches described in the previous section can be used effectively. The
majority of applications considered require that the pole frequency of the filter section be adjusted while the
pole quality factor remains constant. This is needed to ensure that the shape factor of the filter does not change
when the frequency is programmed.
This leads to an important rule: If two components are such that pole frequency is a function of only the
product of their values and the pole quality factor is a function of only the ratio of their values, then the cutoff
frequency of the filter section can be adjusted without change of filter shape by making an equal fractional
change to each component. As long as the component ratio stays constant, the pole quality factor does not
change. Equally, but of slightly less importance, the quality factor can be altered by changing the ratio of the
components, and the pole frequency will not change as long as the product of the component values is invariant.
If, for a given filter section, a pair of components can be found for which the rule above is valid, then the
section can be called canonically programmable. A particular circuit might offer several pairs of components
for which it is canonically programmable, in which case the choice depends on the suitability or attractiveness
of the programming techniques available for the project.
The VCVS or Sallen & Key Circuit. The first filter section is commonly called the Sallen & Key circuit;
requiring only one operational amplifier, set in this case to have unity gain, it has a low component count. Note
by examining the equations in Fig. 10 that the pole frequency is a simple function of the four basic passive
components, and that changing any one of these will change the frequency. If we look at the expression for the
pole quality factor qp , we can see that this constrains the changes we can make to the components if we also
dont want the qp to change. We can see that qp is actually a function only of the ratios R3 /R1 and C2 /C4 , so
if we can keep these ratios constant we will keep the qp constant and thus preserve the shape of the filter; in
other words, this section is canonically programmable for (R1 , R3 ) and for (C2 , C4 ). In this simple Sallen & Key
circuit, value-programmable components are ideal control elements, whereas programmable dividers cannot
be so easily employed.
In the unity gain lowpass version of the Sallen & Key circuit shown, the resistors can be set to be of equal
value whereas the capacitors will be unequal, unless the pole quality factor is equal to 0.5, which is unlikely.
Therefore for this lowpass version, it is common to see the tuning carried out by two identical banks of switched
resistorswith the capacitors being fixed, or possibly switched in decade steps to give a really large overall
range of cutoffs.
The Sallen & Key circuit is also frequently used in a highpass role (Fig. 11), and in this application it is
usual to have the capacitors of equal value and use the ratio between the resistors to set the pole quality factor.

The GIC-Derived or Fliege Circuit. The second filter type is usually known as the Generalised
Impedance Converter (GIC)-derived filter section (Fig. 12 shows the lowpass circuit). Requiring two operational amplifiers and a few more passive components than the Sallen & Key circuit, it has been shown to be
much more suited to high values of pole quality factor (15).
Comparing the expressions for wp and qp , it can be seen that the circuit is only canonically programmable
for (C1 , C4 ). This means that the GIC-derived section can be programmed for cutoff frequency with adjustable
capacitors. Interestingly, the component R1 is absent from the expression for the cutoff frequency, and therefore

PROGRAMMABLE FILTERS

11

Fig. 10. The voltage controlled voltage source (VCVS) or Sallen & Key unity-gain low-pass filter. (Adapted from Ref. 14,
with permission.)

Fig. 11. The Sallen & Key unity gain high-pass filter. (Adapted from Ref. 14, with permission.)

it is possible to adjust the pole quality factor freely by adjusting this resistor, which could be implemented as
a single programmable resistor array.
Variations of this circuit cover high-pass, bandpass, and notch responses and share the same characteristic
as the lowpass circuit, namely that the pole frequency can only be canonically tuned by adjusting the capacitor
values.
State-Variable Circuits. The third filter type, shown in Fig. 13, is variously known as the state-variable
or KerwinHuelsmanNewcombe (KHN) biquad. It employs three operational amplifiers, which might be
considered to be wasteful in comparison to other circuits, but the cost and area penalties using modern amplifier
technologies are small. The only significant disadvantage is the increased power consumption entailed.
Inspection once more of the expressions for wp and qp shows that both the resistor pair (R5 , R6 ) and
the capacitor pair (C6 , C8 ) meet the criterion for canonical programmability. The ratio of resistors R3 and R4

12

PROGRAMMABLE FILTERS

Fig. 12. The generalized impedance converter (GIC)-derived or Fliege low-pass filter. (Adapted from Ref. 14, with permission.)

appears in both expressions, meaning that this ratio should best be left alone. The ratio of resistors R1 and R2
appears only in the expression for qp , providing an independent method for adjusting the pole quality factor,
which will be found useful.
Examining the topology more closely, it can be seen that the component pairs (R5 , C6 ) and (R7 , C8 ) are
each employed with an amplifier to form an integrator; in fact, only the products R5 C6 and R7 C8 appear in
the expressions for wp and qp . In other words, the structure is canonically programmable for integrator time
constants (t1 , t2 ). This is extremely useful because it means that the integrators can be replaced with any of
the programmable integrator structures discussed in the previous section. This versatility has resulted in the
KHN biquad being the filter topology of choice for the majority of programmable filter applications requiring
high performance and closely predictable responses.
Most of the programmable integrator techniques discussed earlier can be employed in a KHN biquad
circuit. Figure 14 shows such a biquad programmed by binary-weighted switched resistors and decade-selected
capacitors; all the switching is done by an integrated switch array. Note that the switches are referred to
the inverting inputs of the integrator amplifiers, which means that there is no signal swing on a conducting
switch (see section entitled Component Nonlinearities and Imperfections). It is important to ensure that
enough control voltage is available to turn the switches on and off fully over the entire signal voltage swing;
commercially available integrated complementary metal-oxide semiconductor (CMOS) switch packages will
achieve this, but more care must be taken with individual JFET or DMOS switches.

PROGRAMMABLE FILTERS

13

Fig. 13. The KHN state-variable low-pass filter, shown in its noninverting configuration. (Adapted from Ref. 14, with
permission.)

Figure 15 shows the classical circuit for using an OTA in a KHN biquad circuit (8). This circuit is limited in
its dynamic range not by fundamental constraints but because the integrated circuit OTAs currently available
have a very limited input voltage range, only a few tens of millivolts for linear operation, which is the reason
that input attenuation must be used at the front of each OTA.
An alternative topology (Fig. 16) using OTAs relies on their very high output impedance to allow a
grounded capacitor connected at the output to directly integrate the output current. The capacitor is then
buffered to prevent the next stage from loading it. Integrated circuits combining OTAs and buffers are readily
available. In this circuit the integrators are noninverting, which allows a passive summation network to be
used to combine the state feedback, eliminating one op-amp.
A common audio frequency application of the programmable state-variable circuit is in the design of
equalizers for audio systems. Reference 9 describes a representative circuit employing VCCA tuning for the
integrators in a KHN biquad; the current actually injected into the virtual earth of the amplifier is equal to
the current flowing through the VCCAs input resistor multiplied by a scaling factor which is the logarithm of
the input control voltage divided by a reference voltage. This results in a linear decibels per millivolt function
which is appropriate for audio applications. Note also that the VCCA used here produces an output current
which is in the same direction with respect to the VCCA as the input current is. From the point of view of the
filter circuit, this turns the integrator in which the VCCA is embedded into a noninverting one, and so the
polarity of the feedback from the output of the first integrator must be reversed to allow for this. The reference

14

PROGRAMMABLE FILTERS

Fig. 14. The KHN low-pass filter programmed with arrays of resistors and capacitors.

Fig. 15. A KHN low-pass filter with op-amp integrators tuned by operational transconductance amplifiers (OTAs).

also illustrates the ease in which a VCCA-based circuit can be configured to provide independent control over
wp and qp in this topology.
MDAC-Programmed State-Variable Filters. The MDAC has found wide application in programmable
KHN biquads; many manufacturers produce highly accurate MDAC devices and provide application notes on
their use in filter design. Figure 17 shows a circuit in which not only the integrator time-constants but also the
feedback paths which were represented by (R3 , R4 ) and (R1 , R2 ) (see Fig. 13) are replaced with MDACs (11),

PROGRAMMABLE FILTERS

15

Fig. 16. An alternative OTA-tuned low-pass filter with two integrators, not requiring a summing amplifier.

Fig. 17. An MDAC-programmed KHN state-variable low-pass filter, with additional MDACs to give finer control of pole
frequency and quality factor.

with an extra inverter employed to ensure that all feedback can be returned to the virtual earth of the input
op-amp. The extra MDACs a and b provide higher resolution for setting the wp and qp values of the section; the
MDACs controlling the integrators (in multiple biquads which may be cascaded to make a higher order filter)
can be controlled with a common code. The tolerances of the programming MDACs fundamental resistance
can be compensated for with the extra MDACs.
The MDAC-programmed integrator has several subtleties which can affect the performance of filters into
which it is embedded. Firstly the output capacitance is a nonlinear function of the code applied, which can
cause the behavior of filters using this technique to depart from ideal at high frequencies (16).
A further difficulty is not immediately obvious but restricts the performance of MDAC-based filters
primarily at the lower extremes of their programming range and also affects any other tuning method in
which some form of resistive voltage or current division is used to alter the integrator time constant. The
operational amplifiers used to construct the integrators contribute to the overall noise and direct-current (dc)

16

PROGRAMMABLE FILTERS

Fig. 18. A test circuit to explore the effect of the dc offset of a standard integrator in a feedback configuration.

Fig. 19. A test circuit to explore the effect of the dc offset of an attenuator-tuned integrator in a feedback configuration.

offset performance of the filters; and the greater the voltage division set by the programming circuits for the
integrators, the greater is the consequent magnification of these effects, due to the overall dc feedback which
exists around the KHN circuit (17).
Consider the two integrators of identical time constant as shown embedded in the circuits of Figs. 18 and
19. In Fig. 18 the time constant is set to be RC by means of components of those values; in Fig. 19 the same
time constant is achieved by feeding a resistor of value R/100 through an attenuator with a gain of 0.01; this
produces the same current into the integrator and hence the same time constant. These integrators are each
embedded in the feedback loop of an ideal test op-amp with grounded input to force the integrator output V 0 to
zero (note that feedback is returned to the noninverting input of this test amplifier since the integrators invert;
also note that the op-amps in the integrators are assumed ideal for the moment). The noninverting input of
the integrator op-amps would normally be grounded, but let us inject a small voltage V e into each inverting
input and work out what the change in the output voltage of the test op-amp will be. In the case of Fig. 18 we
can see that to balance the voltage V e the output of the test opamp V a will equal V e ; at dc the capacitor has no
effect and can be ignored. This is because there is no voltage dropped across the resistor R.
In Fig. 19 we can see by the same argument that the output of the attenuator has to be equal to V e to
balance the dc conditions, but this means that the output of the test amplifier is now 100V e to achieve this.

PROGRAMMABLE FILTERS

17

These test circuits are not real filter circuits, but the split feedback loops in a state-variable filter mean
that the effective attenuation caused by either an MDAC or for instance a digital pot causes a buildup of
dc offset, and also low frequency noise, related to the input behavior of the integrator op-amps; it worsens as
the effective attenuation factor increasesthat is, toward low cutoff frequencies. This effect is not seen when
programmable resistances are used, and it allows the latter type of filter to offer superior stability and dynamic
range compared to MDAC-tuned filters using the same filter op-amps.

Design for Manufacturability

Programmable filters of the types referred to here tend to be manufactured from separate general-purpose
electronic components, although some manufacturers have produced integrated circuits combining several of
the required functions (18). The integration of entire circuits of this type onto a monolithic substrate presents
many problems, which is why alternative techniques such as switched capacitor filtering have become popular.
This section highlights issues relating to the use of real components in programmable filters.
Device Tolerances. Clearly, since the frequency response of a filter circuit is a function of the values
of the components in it, changes in these values will change the filter response. For some special applications,
it is possible to have resistors and capacitors manufactured to the exact values determined by theory; but
this is impractical for most filter designs, whether fixed shape or programmable. Normally, the designer
must recognize the availability of preferred value ranges in the design process. The finite tolerances and
the availability of only discrete values of components impacts the design of programmable filters employing
directly switched components; the small deviations of the values of these components from ideal will cause the
frequency response of the realized filter, after it has been normalized to the intended cutoff frequency, to vary.
Controlling this variation usually leads to the requirement for closely matched and toleranced components.
In this respect, control techniques using MDACs, which are trimmed very accurately during the production
phase, can be very helpful.
Op-Amp Bandwidth and Predistortion. Predistortion is the term applied to the alteration of the
values used in a filter circuit so that the finite bandwidth effects of the amplifiers used are exactly compensated
for. If a programmable filter needs to cover a wide frequency range, it is quite possible that it will have to work in
regions where predistortion would not otherwise be an issue, as well as in regions where the undistorted values
would produce an incorrect response due to amplifier limitations. The presence of this problem presupposes that
it has not been possible within the design to find an amplifier whose performance is in all respects adequate,
and that some form of compensation will be required.
There are two approaches to a resolution of this problem. Firstly, it may be possible to set the adjustable
components or circuit elements (e.g., integrators) to values which are different from what would be expected
if the amplifiers were perfect, but in such a way that both the pole frequency and the pole quality factor are
achieved. This will require higher resolution from the controlled circuit elements than would be needed simply
to achieve the individual frequency steps required. For instance, a pair of simple 4-bit binary-switched resistor
arrays would normally be sufficient to provide a 15:1 frequency adjustment for say a Sallen & Key circuit or a
KHN Biquad at lower frequencies, but at high frequencies the 15 different values needed by each resistor (and
they will probably not be equal) might require at least 8-bit resolution, immediately doubling the complexity
of the control elements (19).
In fact, as mentioned in the section entitled Parasitic Capacitance, this increase in the complexity of
the control elements may itself inject another form of variability into the parameter setting process due to the
variation of parasitic capacitances which cannot be disregarded at higher frequencies, and which can combine
to make the pole frequency and pole quality factor an almost unpredictable function of the digital control
word, making automated functional calibration on a computer-controlled test fixture the only realistic way of
manufacturing these circuits (16).

18

PROGRAMMABLE FILTERS

However, the use of voltage-controlled circuit elements blends in well with this approach, since it is
usually quite easy to provide large numbers of static or slowly varying dc control signals from the central
control processor, often using a Pulse Width Modulation (PWM) technique which requires little in the way of
expensive, high-accuracy DAC components.
The other way of resolving the problem is to find a compensation technique for the circuit topology which
is orthogonal to the process for generating the theoretical component values. This involves additional (usually
passive) circuit elements which are added to the circuit so that, to at least a good approximation, the circuit
produces the intended response parameters when a particular set of component values, intended for use with
ideal amplifiers, are selected by the control circuitry.
By far the most important example of this technique is the use of phase-lead compensation in the two
popular biquads based on a pair of integrators: (a) the KHN biquad already discussed in detail, and (b) its close
cousin the TowThomas biquad (20). In this technique a fixed capacitor is placed across one of the resistors
in the filter which is not adjusted when the filter is used in a programmable context (nearly always R3 in Fig.
13); the RC time constant is set to provide phase lead which cancels out the phase lag introduced by the three
amplifiers. This compensation is effective whatever the components used in the two integrators, and it is a
sound practical way to compensate programmable KHN filters. To a first approximation, the value of the time
constant for such a compensation capacitor used in a loop with three amplifiers, two of which are realizing a
standard integrator, is

where wa , the unity gain frequency of the amplifiers, is measured in rads/second. If we know the value of the
resistor, the capacitor value follows directly.
Parasitic Capacitance. Layout parasitics are generally constant and unrelated to the activities of the
control circuits in a programmable filter circuit. Such parasitics often affect the performance of an active filter
and should be taken into account in the design. Layout parasitics can be expanded to include the effects of
input capacitance of the amplifiers used; this is a significant source of error in many circuits and must also be
considered. Naturally, filter circuits containing only grounded capacitors are the easiest to make allowances
for (since the parasitic input capacitance of the amplifier is effectively connected to ground because ground and
the power supplies are, or should be, common at high frequencies).
However, a separate class of parasitics plague programmable filters and can be the limiting factor in their
successful operation at higher frequencies. All programming techniques which deploy an array of switches to
link components into the circuitand this includes the MDAC structures discussed earlierare affected by
the variation of the parasitic capacitance of the switch elements between the off and on states. In addition,
since various circuit branches are switched in and out by this process, static parasitics associated with these
branches are switched too, making the total amount of parasitic capacitance a complex function of the digital
code used to control the filter parameter.
The reason why this causes an unwelcome effect rather than just a smoothly varying degradation which
can be coped with in a similar way to the problem caused by op-amp bandwidth limiting relates to the way in
which a wide range of component value is implemented efficiently using some form of binary coding. As seen
earlier, this applies to both binary-weighted component networks and to MDACs.
Consider the integrator circuit of Fig. 20, in which a 4-bit binary controlled resistor network is being used
to control the time constant. The relevant parasitic capacitances are also included; C1 through C4 are the stray
capacitances across the resistor elements (note that these will in general not be related to the resistance value
in any simple way) while the switch terminal capacitances are shown as Ci and C0 (again, note that these
capacitances depend on the state of the switch). As shown previously, this circuit is capable of adjusting the
cutoff frequency of a filter in which this integrator, and others like it, are embedded, between F and 15F, where

PROGRAMMABLE FILTERS

19

Fig. 20. A resistively programmed inverting integrator showing the parasitic capacitances associated with typical 4-bit
control.

F will be set by all the other components in the filter but will be proportional to 1/RC. With switches in the solid
position, the cutoff is being set to 7F; the most significant bit is off and all the rest are on. With switches in
the dotted position, the cutoff is being set to 8F and the most significant bit is now on, with the rest off. In one
case, we have three on switches, together with their own parasitics and those of the connected sub-branches
(the resistors themselves), while in the other case, only one switch is on. In particular the effect of the stray
capacitance on the resistors causes a variable degradation of the performance of the integrator.
Since there is a very nonlinear relationship between a number and the number of on binary bits needed
for its representation, then if the parasitic elements in a circuit are significant, their effect will vary in a very
complex way as the filter cutoff frequency is programmed using a switched resistor technique. Solutions to this
problem generally involve ensuring that the ratio between the fixed capacitor used in the integrator and the
parasitic capacitances introduced by the switched components is as high as possible.
Component Nonlinearities and Imperfections. The effect of amplifier nonlinearity on filter performance is common to both programmable and fixed response filters; however, the particular techniques used
to achieve programmability have their own influence on nonlinearity and also to a certain extent on the noise
developed by the circuit.
Circuits using electronic switches will be sensitive to the nonlinear behavior of the on resistance of the
switch used, as a function of signal voltage swing. Improving process technologies bring steady reductions in
this source of distortion, but clearly the best solution is to eliminate the signal voltage swing by some means.
The KHN biquad employing switched resistors (Fig. 14) achieves this by operating the on switches at a
virtual earth point, so that whatever the signal swings at the outputs of the amplifiers in the filter, there is no
modulation of the on resistance.

20

PROGRAMMABLE FILTERS

When analog switches are used to switch banks of capacitors into a filter circuit, the on resistance of the
switch will cause an error in the filter response which is difficult to compensate for. This resistance should be
kept as low as possible; if space and power consumption are not critical, small relays can be used instead of
silicon-based switches.
Even when used in series with an intentional resistor, the on resistance behavior of a silicon switch can
cause problems due to the high positive temperature coefficient of resistance which it displays. The effect of
this resistance temperature coefficient should be taken into account; it makes little sense to spend money on
ultrastable resistors only to throw it away with this source of error (17).
Testing. Filters of this complexity present a greater alignment and testing challenge than those with
a fixed shape and cutoff frequency, because the programmability must be confirmed for the whole range over
which it is offered. It may be that a single specification for the realized performance of the filter is applied
whatever the programmed parameter, or the deterioration of performance occurring toward the extremes of
the range of programmability may be recognized by a loosening of tolerances at these extremes.
Automated testing in which both the programmable filter under test and the test equipment employed
are sent through a sequence of settings is essential for testing to be both efficient and effective. The nature of
the tests employed can be thought of as providing a test vector which is quite analogous to that employed in
the testing of digital circuits. The test vector, or set of tests to be performed, must be constructed to ensure that
(1) the end user of the circuit can see clearly that specification-related tests have been performed and have
been passed and (2) any potential areas known to the designer where failure may occur have been carefully
explored.

BIBLIOGRAPHY
1. U. Kumar A decade range linearly tuneable versatile filter, IEEE Trans. Instrum. Meas., IM-30: 165167, 1981.
2. E. Damm Spannungsgesteuerte Analogfilter, Elektronik, 10: 9092, 1976.
3. A. M. Durham W. Redman-White J. B. Hughes Digitally-tuneable continuous time filters with high signal linearity,
IEE Colloquium Digital Analogue Filter Filtering Syst., 1991, pp. 9/19/4.
4. R. Schaumann Design of continuous-time fully integrated filters: A review, IEE Proc., 136 (4, Pt. G): 184190, 1989.
5. S. Franco Use transconductance amplifiers, Electron. Des., 24 (19): 98101, 1976.
6. Y. P. Tsividis J. O. Voorman (eds.) Integrated Continuous-Time Filters: Principles, Designs & Applications, New York:
IEEE Press, 1993.
7. K. Fukahori A bipolar voltage-controlled tuneable filter, IEEE J. Solid-State Circuits, SC-16: 729737, 1981.
8. H. A. Wittlinger Applications of the CA3080 high performance operational transconductance amplifier, application note
ICAN6668, NJ: RCA, 1973.
9. G. K. Hebert F. Floru Digitally-controllable audio filters and equalizers, 13th Int. Conf. AES, Dallas, TX, 1994.
10. D. J. Sheingold Application Guide to CMOS Multiplying D/A Converters, Norwood, MA: Analog Devices, 1978, pp.
1214.
11. J. M. Zurada Digitally tuneable active filter biquads, Proc. Southeastcon 81, 1981, Huntsville, AL, pp. 364368.
12. R. W. Harris H. T. Lee Digitally controlled, conductance tuneable active filters, IEEE J. Solid-State Circuits, SC-10:
182185, 1975.
13. M. E. Van Valkenburg Analog Filter Design, Philadephia: Holt-Saunders, 1982.
14. G. S. Moschytz P. Horn Active Filter Design Handbook, New York: Wiley, 1981.
15. N. Fliege A new class of second-order RC-active filters with two operational amplifiers, Nachrichtentech. Z., 26 (6):
279282,1973.
16. K. Goodman J. M. Zurada Frequency limitations of programmable active biquadratic filters, Proc. Southeastcon 81,
1981, Huntsville, AL, pp. 369373.
17. K. Castor-Perry Using resistor-set filters, application note 7, Kemo, Ltd.
18. UAF42 Universal active filter data sheet, Tucson, AZ: Burr-Brown.

PROGRAMMABLE FILTERS

21

19. K. Goodman J. M. Zurada A predistortion technique for RC-active biquadratic filters, Int. J. Circuit Theory Appl., 11:
289302, 1983.
20. L. C. Thomas The biquad: part Isome practical design considerations, IEEE Trans. Circuit Theory, CT-18: 350357,
1971.

READING LIST
D. Lancaster Active Filter Cookbook, Indianapolis, IN: Sams.
P. Horowitz W. Hill The Art of Electronics, 2nd ed., Cambridge, UK: Cambridge Univ. Press, 1989.
R. Schaumann M. A. Soderstrand K. R. Laker Modern Active Filter Design, New York: IEEE Press, 1981.
W. Heinlein H. Holmes Active Filters for Integrated Circuits, New York: Springer-Verlag, 1974.

KENDALL CASTOR-PERRY
Burr-Brown Corp.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering

c 1999 John Wiley & Sons, Inc.
Copyright

PULSE-SHAPING CIRCUITS
Digital communications systems such as wireless, optical, and wireline telecommunication networks have
numerous well-known advantages over analog systems. These systems format binary data into discrete time
symbols, modulate the carrier using some form of digital modulation scheme (modulation in this simplified
context includes symbol modulation and up-conversion to a carrier frequency) to convert them to transmittable
continuous-time signals, and transmit them over a channel. At the receiver the received signal is demodulated
(demodulation includes both down-conversion and symbol demodulation), symbol timing is recovered, and the
received symbols are reformatted into a usable form. This process is shown in simplified form in Fig. 1.
The discrete time symbols of a digital communication system are of duration T and are sequential, that
is, they are orthogonal in time. To preserve the fixed time duration of symbols generated in the transmitter
would require infinite bandwidth in the signal processing of the communication system and the communication
channel. Finite bandwidth processing causes the symbols to spread in time. This causes the symbols to overlap
in time and induces intersymbol interference (ISI).
As will be described in the next section, even when finite bandwidth signal processing is used in the
communication system, the effects of ISI could be eliminated if ideal signal processing components (brick
wall filters as an example) could be implemented. This is of course not possible. Pulse shaping is used in the
implementation of digital communication systems to minimize ISI caused by nonideal channel characteristics
and nonideal component implementations.
Pulse shaping is performed in the transmit and receive filters of a communication system. The most
common class of filters used for pulse shaping are Nyquist filters (1,2,3). This article gives an overview of the
theoretical foundations of pulse-shaping and describes some practical implementations of pulse shaping filters.
The material in this article assumes that the communication channel can be modeled as a linear time-invariant
filter with additive white Gaussian noise (AWGN). For more detailed and in-depth coverage of pulse shaping
the reader is referred to Refs. 1 to 3.

Theoretical Background
Ideal data symbols are of fixed duration T. The spectrum for such a symbol is of the form

PULSE-SHAPING CIRCUITS

Fig. 1. Simplified block diagram of a digital communication system.

Fig. 2. General form of a pulse shape for an ideally band-limited symbol.

Thus such a symbol would require infinite bandwidth, which is of course impractical. Real communication
channels are of fixed bandwidth W. The ideal band-limited channel response (1) is

The transmit filter, which is designed to shape the transmit symbols to meet the power spectrum constraints of the channel, has an ideal frequency-domain response (1) of

The time-domain transmit filter response is therefore

This response is referred to as the pulse shape. hT (t) is the familiar sinc function, which has zero crossings
at integer multiples of Wt except at Wt = 0 where it has a value of 1. If we assume a symbol sequence Sn and
set T = /W, then the pulse for each symbol is of the form shown in Fig. 2 for a single pulse and in Fig. 3 for
multiple pulses.
From Fig. 3 it is obvious that if symbols are sampled at times t = nT, where n is an integer, the effects of
ISI are mitigated. This is because the contribution to the composite waveform is zero for all pulses except for
the pulse corresponding to S 0 because they are all at a zero crossing point.
The problem is that to produce hT (t) = sin(Wt)/Wt requires an ideal brick wall filter, which is impossible
to implement. One could attempt to approximate the ideal filter but this would not be cost effective and would

PULSE-SHAPING CIRCUITS

Fig. 3. Multiple pulse shapes for an ideally band-limited symbol.

have other undesirable effects on the system such as making timing recovery difficult (1). To address these
problems, more practical pulse shapes have been developed.
The pulse shape at the input to the demodulator, hp (t), is the convolution of the transmit filter, the channel
response, and the receive filter, that is,

From our preceding discussions it is clear that to eliminate ISI, hp (t) should be forced to cross zero at
nonzero integer multiples of T. This can be written as

The composite input to the demodulator is

where N R (t) is the noise input at the demodulator, that is,

From Eq. (1) it can be seen that forcing the composite pulse to cross zero does not necessarily produce an
optimal solution because it ignores the noise contribution. Joint optimizations are possible but they are beyond
the scope of this discussion. The reader is referred to 1 for in-depth coverage of this subject matter.
Taking the Fourier transform of Eq. (6) and applying the Nyquist sampling theorem, we get

Equation (9) is referred to as the Nyquist criterion, and filter responses (pulses) that meet this criterion
are referred to as Nyquist filters (pulses).
These filters require more than the ideal bandwidth defined in Eq. (3). While simplifying the system
implementation, this additional bandwidth requirement costs additional spectrum and noise bandwidth at the

PULSE-SHAPING CIRCUITS

receiver. The additional bandwidth is referred to as excess bandwidth and is usually expressed as a percentage
of the ideal bandwidth, that is,

The actual pulse shape used in a particular application is highly dependent on the targeted channel
characteristics. The most commonly used filters satisfying the Nyquist criterion for pulse shaping are raised
cosine filters. For this reason raised cosine pulse shaping will be used in this article to describe implementations.
Raised cosine filters are of the form

where controls the rate at which the energy rolls off. The smaller is, the faster the roll off. Note that for
= 0,

which is the ideal pulse shape for a band-limited channel.

In most actual implementations the raised cosine filter is partitioned with part of the response implemented in the transmit filter and part implemented in the receive filter. The most common partitioning is to
implement each as the square root of the raised-cosine filter. This is commonly referred to as a root-raised-cosine
filter (1) and is given as

PULSE-SHAPING CIRCUITS

Fig. 4. Pulse-shaping process in a digital transmitter.

and

Implementation
In contemporary digital communication systems it is often not possible to achieve economically the required
performance from analog pulse-shaping filters. Shaping filters are therefore implemented using a hybrid
approach. The bulk of the shaping is done at baseband using finite impulse response (FIR) digital filters, which
implement a truncated version of the pulse shape.
On the transmit side of a communication system data symbols are passed to an interpolating digital filter
(4). The impulse response of the digital filter typically spans multiple symbol times and is the convolution of
the desired pulse-shaping response and precompensation for the roll-off frequency response of the subsequent
digital-to-analog converter (DAC) if the roll-off is great enough to affect system performance. The output of the
digital filter is passed to a DAC and a subsequent image reject filter for conversion to continuous-time analog
format. The output of the DAC in the spectral domain is the baseband spectrum and images of the baseband
spectrum occurring within bands, which are bounded by integer multiples of one-half of the sampling rate f s ,
all multiplied by a sinc function with nulls occurring at integer multiples of the sampling rate. In the case of
low-pass signals the images are present near integer multiples of the sampling rate. In the time-domain the
output waveform is stair stepped. The image reject filter removes all of the spectral images and passes the
baseband spectrum, thus smoothing or interpolating the time-domain waveform.
At the output of the image reject filter, the shaped symbol pulses are in continuous-time analog format.
They can then be up-converted to the desired radio frequency (RF) for transmission. This process is shown in
Fig. 4.
The operation at the receiver is the transpose of the transmit operation. The analog front end (AFE) of
the receiver translates the RF signal into a convertible pulse train. The pulse train is then converted to a
digital form via an analog-to-digital converter (ADC). The pulse train is filtered by a decimating FIR filter (4)
with a root-raised-cosine response to complete the raised-cosine pulse-shaping operation. The receive process
is shown in Fig. 5.

PULSE-SHAPING CIRCUITS

Fig. 5. Pulse-shaping process in a digital receiver.

Digital Pulse-Shaping Network. The actual design procedure for a pulse-shaping network is now
presented. A transmit-side root-raised-cosine pulse-shaping network is described. The receive-side network
will not be addressed since it is the network transpose of the transmit network.
Assume a digital data transmission system has a symbol period of T seconds, that is, every T seconds a
new b Q bit symbol is transmitted. In this description we assume bQ = 1 for simplicity of illustration, although
this is not necessary. Before transmission, it is necessary to shape each transmitted pulse. In this case a positive
pulse shape is transmitted for a bit value of one, and a negative pulse is transmitted for a bit value of zero. In
addition to considering the desired pulse type, it is necessary to determine the length of the pulse relative to
the symbol length and the resolution of the pulse or the number of bits used to compute the pulse values.
The interpolating FIR filter shown in Fig. 4 must be economically implementable and can therefore only
approximate a desired pulse shape, the root-raised cosine given by Eq. (14) in this case. The response is
approximated by first determining the desired filter length. The filter length N is the product of the symbol
interpolation factor L and the desired span M. The span is the number of symbol periods over which the shaping
filter will operate.
The interpolation factor is selected to minimize the sinc(x) distortion at the upper edge of the band
of interest caused by the DAC and to simplify the implementation of the image reject filter: the greatest
consideration is the latter. As was mentioned previously, sinc(x) distortion in the band of interest can be
compensated for by putting a precompensation function [1/sinc(x)] in the interpolating filters response. The
higher the interpolation rate, the more distance there is between the band of interest and the first image in
the spectral domain. The more distance there is, the simpler the image reject filter. Thus the interpolation
factor becomes a trade-off between the complexity of the digital interpolating filter and DAC speed, and the
complexity of the image reject filter. Typically, an interpolation factor of between 8 and 16 is a reasonable trade.
The span over which the impulse response is approximated depends on the amount of out-of-band energy
that can be tolerated. An ideal impulse response begins to approach zero after a number of time-domain side
lobes. However, the synthesized impulse is of finite duration. How closely the tails of the response approach
zero is dependent on the length of time the impulse is approximated. Out-of-band energy is reduced as the
span increases so the trade-off becomes filter order versus out-of-band energy due to time-domain side-lobe
truncation. Typical values of the span factor are 4 to 16. A typical root-raised-cosine pulse shaper would have
an interpolation factor of 8 coupled with a span of 8 to yield a total filter length of 64.
Filter Coefcient Calculation. There are a number of possible methods for calculating the coefficients
of the pulse-shaping filter. Two will be discussed here: the direct and optimal methods.
The Direct Method.. An FIR digital filter is of the form

PULSE-SHAPING CIRCUITS

The direct method samples the continuous-time impulse response at appropriate points in time to generate
the filter coefficients a. Under the assumption of proper sampling

where H D (z) is the desired frequency-domain pulse shape and N 1 is the filter order.
As stated previously, the total number of coefficients, N, is related to the span and interpolation factors
by N = LM. Thus, continuing with the root-raised-cosine example one would simply calculate N evenly spaced
values using Eq. (14) to calculate the coefficients a n . Since hT (t) is an even function about t = 0, it is necessary
to shift hr (t) in time such that the sampled version of hT (t) [ denoted by h(n) ] is evenly symmetric around
samples (N 2)/2 and N/2 to ensure a fully linear phase response (5). Since there are L samples per symbol
period T, h r (t) should be evaluated at integer multiples of T/L. This, along with the time-shift requirement,
dictates that the discrete-time values necessary to define h T (t) are given by

Substituting this into Eq. (14) gives the sampled version of h T (t),

This process is illustrated in Fig. 6 for a filter of length N equal to 64 and including 4 12 side lobes on either
side of the main lobe of the root-raised-cosine function. Figure 7 shows the corresponding frequency-domain
response of the pulse-shaping filter.
As is the case with any digital filter coefficient design method, once the floating-point coefficients are
calculated, they must be converted to fixed-point format if the target digital filter is to be implemented in fixedpoint arithmetic. Conversion of coefficients to fixed-point format can be as simple as truncation or rounding or
can require sophisticated optimization processes. Let

be the quantized coefficients. The next step in the coefficient design process is to calculate the frequency
response of the quantized filter coefficients and compare it with the desired frequency response to see if the
filter is within acceptable error bounds. The frequency response of an FIR filter is found by evaluating the
filtersz transform on the unit circle. That is, the magnitude frequency response of the quantized coefficients is

PULSE-SHAPING CIRCUITS

Fig. 6. A discrete time sampled root raised cosine.

Fig. 7. Frequency-domain response of the sampled root-raised cosine shown in Fig. 6.

given as

H
(z) can be evaluated directly or by using a form of the DFT. If the filters frequency response does not meet
the required error bounds, then either the filter order N or the number of bits in the coefficient quantization
must be increased and the appropriate steps in the coefficient design process must be repeated.
Coefficient quantization is not as straightforward as data quantization. The quantization of data words
yields 6.02 dB of signal-to-noise ratio per bit. The number of bits required for coefficient quantization is a
function of filter order and the frequency-response shape. A good rule of thumb for a worst-case metric (6) for

PULSE-SHAPING CIRCUITS

the number of coefficient bits required is

so that

assuming no limiting roundoff error in the actual filter implementation. In most practical pulse-shaping filter
implementations, the coefficient word length should be closer to the lower bound.
The floating-point coefficients (a) for the case M = L = 8 are shown in matrix form. Each column represents
samples in adjacent symbol periods. Since the impulse response spans eight symbol periods, there are eight
corresponding columns.

In converting the floating-point coefficients to fixed-point coefficients, maximum arithmetic efficiency can
be obtained by scaling the fixed-point coefficients so that the maximum possible filter output is at the overflow
threshold. Worst-case peak signals would occur for data patterns in which the maxima and minima of the
impulse response overlap, or add (in the case of a negative pulse, the absolute value of the minima adds to the
composite pulse). It turns out for the example here that an efficient peak value for the impulse response to
take is 194 for a 9-bit integer twos complement representation (maximum possible positive value of 255).

10

PULSE-SHAPING CIRCUITS

Fig. 8. Illustration of the conceptual interpolation process.

Scaling the matrix of the floating-point values to a peak value of 194 and rounding each coefficient to the
nearest integer results in the coefficient set shown here, which completes the synthesis of the pulse coefficients.

The Optimal Method.. The optimal method requires an optimizing filter design program such as the
ParksMcClellan program (5,7) but guarantees an optimum solution. To design the pulse-shaping filter coefficients using the optimal method the EFF subroutine (EFF is the actual name of the subroutine in the published
program) in the ParksMcClellan computer design program must be modified by inserting a floating-point,
discrete-frequency version of the desired frequency- domain pulse shape. The program is then executed with
a desired filter order and the same iterative process of evaluating the frequency response of the quantized
coefficient set as described previously for the direct method is followed until a set of coefficients is generated
that is within the desired error bound. This method yields much more reliable results than the direct method.
Even more sophisticated filter programs exist that optimize quantized coefficients. These programs allow
designers to optimize the efficiency of a filter implementation.
Filter Hardware Implementation. The actual hardware realization of a pulse-shaping filter is highly
dependent on symbol rates, filter order, process, etc. Assuming symbol rates that allow implementations in
state-of-the-art semiconductor processes, the filter would be implemented as some variation of a polyphase
architecture (4).
Interpolation is the process of increasing the sampling rate while preserving the signals spectral content.
The conceptual first step in interpolation is to insert L 1 zero-valued samples between each valid input
sample, expanding the sampling rate by L. This causes the original signal spectrum to be repeated L 1 times.
This process is referred to as sample rate expansion. To complete the interpolation, the zero-valued input
samples are converted to spectrally accurate approximations of the signal. This is equivalent to preserving the
original signal spectrum. Thus, and again conceptually, the zero-stuffed input stream is filtered by a low-pass
filter with a passband at the original spectral location and a passband gain of L. This filters out all of the
repeated spectra. This conceptual process is shown in Fig. 8.
In real implementations it would be a waste of storage and computational resources to store and multiply
zero-valued data samples. For this reason, polyphase structures are used. A polyphase interpolator configures

PULSE-SHAPING CIRCUITS

11

Fig. 9. Polyphase implementation of an FIR interpolation filter.

the standard N-tap filter structure into k phases of an (N 1)-element delay line. For example, an eighth-order
(N = 9) FIR filter with k = 3 phases has three sets of three coefficients. The coefficients for the eighth-order
filter are a0 , a1 , . . ., a8 . The first polyphase taps the eight element delay line at the input to the filter (a0 ), after
the third delay (a3 ), and after the sixth delay (a6 ). The second phase taps a1 , a4 , and a7 . The third phase taps
a2 , a 5 , and a8 . However, since all but every third element in the delay line would contain a zero-valued data
sample, the delay line can be collapsed to a two-element delay line (N/k 1 elements) with all phases using the
same samples. The output of the interpolator is the commutated output of the three phases. Figure 9 illustrates
the polyphase implementation of the nine-tap interpolator. Reference 4 details the efficient implementation of
interpolation and decimation filters.
An interpolation filter can be implemented using standard multiply and accumulate elements, or in some
cases it is most efficient to use table look up based bit-slice filter methods (8). The trade-off is dependent on

12

PULSE-SHAPING CIRCUITS

the number of bits required for the representation of a symbol. For low-bit count, the bit-slice implementation
is usually more efficient. As bit count increases, table sizes become unmanageable.

DAC
The DAC has the task of generating an analog output based on the digital input supplied by the FIR filter.
The DAC must be linear to ensure no unwanted spurious energy is generated. Several implementations are
possible depending on the DAC resolution required. For relatively modest resolutions of 4 to 8 bits, simple
binary weighted current or charge-based approaches are possible. For higher resolutions, it may be desirable
to use segmented approaches where each least significant bit (LSB) step has a separate current- or chargebased generator. For example, a 5-bit segmented current-steered DAC would have 32 separate current sources
feeding a common resistor to generate the desired output voltage. Sources are turned on or off depending on
the value of the control word. This is opposed to a binary approach in which only five current sources are used
scaled in binary fashion. For higher-bit resolutions, the binary approach can suffer from linearity errors due to
mismatches at major carries. The advantage of a binary approach is smaller implementation area. For DACs
of 9-bit resolution or higher, a combination of binary [for the most significant bits (MSBs)] and segmented (for
the LSBs) is frequently used.
Standard DACs offer no image suppression, even if the DAC runs at a rate greater than the digital
word update rate. Image suppression could be improved if the DAC could interpolate between successive word
updates. Such a converter can be demonstrated, following up on the example begun for the pulse-shaping
network. Suppose specifications require that all spurious energy be at least 40 dB down with respect to the
baseband level. This requires that all spectral images of the FIR filter be attenuated sufficiently to achieve this.
Further suppose that the symbol rate is 128 kbaud. The update rate f s of the digital filter is 1.024 MHz (due
to the 1:8 interpolation factor from the preceding example), and hence the first image replica will appear there.
If the DAC were updated at the 1.024 MHz rate, then the amount of attenuation of the image due to roll off
is only 17 dB. Consider an interpolating DAC operating at five times the digital update rate (f s1 = 5.12 MHz).
The block diagram of an architecture suitable for monolithic integration accompanied by illustrative spectral
plots is shown in Fig. 10. In this architecture, it is shown that interpolation can provide 20 dB of additional
attenuation.
A simplified single-ended schematic of an interpolating DAC is shown in Fig. 11 (9). and 2 are nonoverlapping clocks operating at the interpolation frequency (5.12 MHz in the preceding example). The operational
amplifiers are conventional fully differential folded cascade topologies. The input voltage reference is selected
based on specific channel requirements and typically ranges from 250 mV to 1 V. It is usually supplied by an
on-chip band-gap generator. The configuration is a cascaded charge redistribution DAC with the first stage
an offset insensitive programmable amplifier to realize the four least significant bits (10). Gain is determined
by the sum of the binary weighted capacitors at the input, dependent on the LSB word. The second stage
is a modified second-order switched-capacitor biquad (11). This stage has programmable gain to realize the
four most significant bits of the DAC and acts as the summing point for the LSB portion. A straightforward
charge-transfer analysis yields the low- frequency output level as a function of the reference voltage V ref and
critical circuit capacitor values

PULSE-SHAPING CIRCUITS

13

Fig. 10. Digital-to-analog converter top-level block diagram.

Here, b0 , b 1 , . . ., b 7 represent the digital data (possible values of 0 or 1) with b 7 as the least significant
bit. Since the DAC is fully differential, the sign bit is easily incorporated by cross-coupling the input connection
to V ref . Interpolation is accomplished by the fact that the final stage is really a switched-capacitor filter. dc
and ac analysis is simplified by replacing the DAC capacitor array structure with an equivalent single-ended
switched-capacitor network as shown in Fig. 12. Including the input offset voltages Voff2 , Voff3 for the operational
amplifiers, the defining charge equations for this network are given by

where V

o2

and V

o3

are outputs of amplifiers 2 and 3, respectively.

14

PULSE-SHAPING CIRCUITS

Fig. 11. Simplified single-ended DAC schematic.

Fig. 12. Interpolating filter.

Under steady-state conditions n . With V

in (n) = V in (n1) = 0,

then

where V o2 and V o3 are the dc offset voltage at the outputs of amplifiers 2 and 3, respectively. Under these
conditions, solving Eqs. (27) and (28) yield the output offset voltages for the DAC,

PULSE-SHAPING CIRCUITS

15

where Eq. (31) is valid during high 1 . It is interesting to note that although the DAC output is a fully held
signal over the 5.12 MHz clock period, it has no operational-amplifier-induced dc offset. This is simply due to
the fact that output offset at this point is due solely to amplifier 2, which has been nulled out.
Ignoring offset, Eqs. (27) and (28) may be transformed to the z domain, where the following transfer
function may be derived:

This is the form of a second-order low-pass filter. Interpolation is accomplished by designing the filter such that
little passband loss occurs at the digital filters 3 dB point of 64 kHz. Setting specifications for the interpolating
filter at no more than 0.3 dB loss at 100 kHz; then with a sampling frequency of 5.12 MHz, this leads to a
desired transfer function of

Coefficient matching with Eq. (32) yields the necessary capacitor values. With 17 dB of loss due to the S/H effect
and the loss at 1.024 MHz due to Eq. (33), the image at the DAC output is 37 dB lower. Hence, an additional
20 dB of image rejection is achieved with the use of interpolation techniques.
Image Filter. There are several techniques that are used to realize continuous-time monolithic filters.
Standard active filter techniques utilizing resistors and capacitors are the simplest approach but pole frequencies cannot be accurately placed due to typical process variations. If the image response is located very far away
from the baseband spectrum, then accurate pole placement may not be necessary. In that case, the filter is
simply designed such that the worst-case RC product leading to a high cutoff frequency is still sufficient to meet
stopband energy requirements. Frequently, only first-order filters are required, but if the passive variation is
significant enough, higher-order filters may be necessary to provide sufficient attenuation. If a process has
very linear components, such as thin-film resistors and double polysilicon or metal capacitors, it is possible to
realize wide dynamic range filters with excellent linearity. Dynamic ranges over 93 dB are possible if linearity
is a concern. If only diffused resistors or depletion capacitors are available, then the corresponding voltage
dependence of the passive devices reduces linearity considerably. In that case, interpolating DAC techniques
may be desirable such that only a simple external RC filter is necessary for image filtering. Of course linearity
requirements must be considered to make a final decision.
Another technique that may be used includes MOSFET-C (metal oxide semiconductor field-effect transistor capacitance) filters (12), where MOSFET transistors operated in the linear region are used to replace
resistors in active filters. Using special linearization techniques, MOSFET-C filters can achieve reasonable
linearity (50 dB to 60 dB) and no special resistor material is required. However, MOSFET-C filters are limited
in the frequency range that they can operate due to operational amplifier limitations and distributed parasitics
(13). They also require the use of tuning networks to ensure that the MOSFET devices stay in the linear region
and close to the resistor values necessary to achieve the necessary time constants.
Finally, transconductance-C (g m C) networks can be used as image filters (14). g m C filters have the
advantage of being able to achieve very high cutoff frequencies, typically in the 10 MHz to 100 MHz area.
These may be useful in cases where data rate is very high and image frequencies may be close to baseband.

16

PULSE-SHAPING CIRCUITS

Linearization techniques can achieve dynamic ranges in the area of 50 dB to 65 dB. g m C filters have pole
frequencies proportional to g m /C, so stable transconductance networks are required to achieve stable pole
locations. Usually, this implies some sort of tuning network to accurately set gm for the desired cutoff.

Summary
In this article an overview of the motivation, theory, and implementation of pulse shaping in digital communication systems has been presented. Digital communication systems transmit digital data as discrete-time
symbols modulating a continuous-time waveform. Because actual communication channels are band limited,
symbol times can overlap, inducing intersymbol interference. Pulse shaping can reduce or eliminate intersymbol interference if it is closely matched to the characteristics of the channel.
A theoretical background for pulse shaping was established based on a channel that can be modeled as
a linear time-invariant filter with additive white Gaussian noise. It was shown that for this type of channel a
class of filters known as Nyquist filters are the most commonly used for pulse shaping and the most popular
filter in this class is the raised cosine filter. Since the implementation of pulse shapers are commonly distributed
between the transmit and receive sides of a communication system, an example of the implementation of a
transmit-side square-root-raised-cosine filter was presented.
The square-root-raised-cosine filter implementation presented was a hybrid analog and digital implementation, taking advantage of the strengths of both technologies.

BIBLIOGRAPHY
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.

E. A. Lee D. G. Messerschmitt, Digital Communication, 2nd ed., Norwell, MA: Kluwer Academic, 1994.
B. Sklar, Digital Communications, Fundamentals and Applications, Englewood Cliffs, NJ: Prentice-Hall, 1988.
R. E. Ziemer R. L. Peterson Digital Communications and Spread Spectrum Systems, New York: Macmillan, 1985.
R. E. Crochiere L. R. Rabiner, Multirate Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1983.
L. R. Rabiner B. Gold, Theory and Application of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1975.
G. A. Mian A. P. Nainer, On the performance of optimum linear phase low-pass FIR digital filters under impulse
response coefficient quantization, IEEE Trans. Acoust. Speech Signal Process. ASSP-29: 925932, 1981.
T. W. Parks McClellan, A program for the design of linear phase finite impulse response digital filters, IEEE Trans.
Audio Electroacoust., AU-20: 195199, 1972.
F. J. Taylor, Digital Filter Design Handbook, New York: Dekker, 1983.
B. A. Myers et al., A frequency agile monolithic QPSK modulator with spectral filtering and 75  differential line
driver, IEEE J. Solid State Circuits, 33: 13941405, 1998.
R. Gregorian G. Temes, Analog MOS Integrated Circuits for Signal Processing, New York: Wiley, 1986, pp. 414416.
R. Gregorian, Switched capacitor filter design using cascaded sections, IEEE Trans. Circuits Syst., CAS-27: 515521,
1980.
Y. Tsividis, M. Banu, J. Khoury, Continuous-time MOSFET-C filters in VLSI, IEEE J. Solid State Circuits, SC21:
1530, 1986.
J. Khoury Y. Tsividis, Analysis and compensation of high frequency effects in integrated MOSFET-C continuous-time
filters, IEEE Trans. Circuits Syst., CAS-34: 862875, 1987.
K. Laker W. Sansen, Design of Analog Integrated Circuits and Systems, New York: McGraw-Hill, 1994, pp. 652657.

BRENT A. MYERS
DAVID B. CHESTER
Intersil Corporation

220

RAMP GENERATOR

RAMP GENERATOR

Ramp generators are found in many circuit applications

where a linear change of some voltage is required. For example, ramp voltages are used to generate the x and y scan voltages in a CRT or in electronic motor controllers. A voltage
that rises or falls linearly in time can be generated very simply, by charging a capacitor at a constant rate over a period
of time. When a capacitor is charged from a simple voltage
source Vo, via a series resistor R, the voltage on the capacitor
rises according to the well-known exponential relationship
VC Vo(1 et/RC). This voltage is not a linear ramp, because
the charging current is not constant. To render the ramp voltage linear, a constant current source must be substituted for
the resistor-voltage source combination, to provide the desired linearity. Now all that is required is a system of controlling the pattern and rate of capacitor charge and discharge,
to determine whether the circuit is a triangle-wave or sawtooth-wave generator.

The next sections contain some examples of how practical circuits might be constructed using comparators, discrete components and a 555 timer. The ramp period in all of these circuits is effectively calculated from the magnitude of the
voltage swing, the magnitude of charging current, and the
value of timing the capacitor, although, in those circuits, employing integrators it is convenient to use the expression for
the integrator output in the derivation of output period.
Non-linear Ramp
Consider the square wave generator circuit based on a regenerative comparator (Schmitt Trigger) shown in Fig. 1. This
R
Vc

Vo
+VA

+
VA

+
+

R1
VS

Vo

R2

Vo

VM
t
T1

T2

Figure 2. Triangle-wave generator using an integrator and showing

the relationship between T1 and T2.

GENERATING A RAMP VOLTAGE

Vref

R1

C
R2

circuit works by feeding back the output voltage Vo via the

resistor R to provide a current that charges and discharges
the capacitor C in an oscillatory manner. Whenever the output changes state, the positive input to the comparator snaps
to a new value, above or below earth potential, providing the
regenerative action. The changing VC causes the differential
input to become less and eventually to change sign, at which
point the output changes state again. If one looks at the capacitor voltage, VC, also shown in Fig. 1, one can see that this
is an approximation to a triangle wave, but is not linear as
explained above.
An operational amplifier integrator circuit can be used to
ensure that the capacitor charging current is constant and
the linear ramp output of the circuit then only need be fed
back to the comparator input to produce a circuit that is simultaneously a square wave and triangle-wave generator.
This approach requires just one further change to the circuit.
Since an integrator is an inverting circuit, such feedback will
produce a ramp voltage on the comparator that is in antiphase with that required to make the two inputs converge,
and can be corrected by connecting an inverting buffer between the integrator and the capacitor.
Triangle-Wave Generator

Vc
VA
t
VA
Vo
VA
t

VA
Figure 1. Square-wave generator showing the presence of a nonlinear ramp voltage on the timing capacitor.

A slightly different approach has been taken in the circuit

shown in Fig. 2. The square-wave output of the comparator is
applied to an integrator as described, but the integrator output is then fed back to the noninverting input of the comparator rather than the inverting input, thus eliminating the need
for an additional inverting buffer (1,2). The frequency of the
output, f o, for this circuit is (2):




VS2
R1
1 2
fo =
4R2 RC
VA

(1)

The median point of the output waveform is set according to

Eq. (2) and the ratio of ramp-up and ramp-down periods,

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

RAMP GENERATOR

VCC

T1 : T2, is set by Eq. (3), where the comparator output switches

between VA (2).
VM = Vref

R

+ R2
R1

RC1

Current Source-Controlled Circuit

The direct approach, shown in the circuit of Fig. 3, uses one
current source to charge the timing capacitor and a second to
discharge it, so that the rising and falling slopes are set by
the ratio of the current sources. The charge and discharge of
the capacitor is once again controlled by a regenerative comparator, this time connected to a complementary pair of
switches. When the comparator output is high, S1 is closed,
allowing C to be charged by I1, while S2 is open. When the
differential input to the comparator changes sign, its output
changes state and S2 is closed, while S1 is open, and C can be
discharged via I2, until the comparator differential input
changes sign again. This circuit can be easily used for sawtooth generation, since one or the other of the current sources

S1
+VS

I1

I2

RC3

Q1

(3)

Even though the T1 : T2 ratio can be varied widely, this circuit

is not such a good choice if a sawtooth waveform is required,
since either T1 or T2 is then required to be zero. If a single
ramp is required rather than the repetitive output provided
by this circuit, it can be easily converted to monostable operation (1).
This circuit has a useful operating frequency range up to
about 40 kHz, with the limit set by the comparator output
slew rate. A general purpose operational amplifier can easily
be used here, but for higher frequency operation a high slew
rate device, such as an LM6365, can be used to extend the
maximum frequency (depending on the voltage swing required). However, it should be noted that bipolar operational
amplifiers do not generally provide full rail to rail output voltage swing, which can lead to drift in the Schmitt Trigger
thresholds, so for general use, an FET output operational
amplifier which does give full rail to rail voltage swing is a
better choice.

Vo

RC2

R1

(2)

V + VS
T1
= A
T2
VA VS

S2

221

R1
C
R2
VS

Figure 3. Ramp voltage generator using current source switching for

triangle or sawtooth output, showing the action of S1 and S2 to charge
and discharge C.

R2

Q2

REE

Q5
Vo
RE5

Q3

VEE

RBB

VBB

Q4

Figure 4. Sawtooth generator constructed from discrete components

which also makes use of a (single transistor) current source.

can be omitted and replaced by a short circuit, so that C can

be charged or discharged using a very short time constant
circuit. The current sources themselves could be either simple
current regulator connected BJTs or FETs, or a more complex
current regulator device, depending on the accuracy and stability required. Once again, the maximum useful operating
frequency is set by the comparator output slew rate, but may
be pushed beyond the normal operating range of the comparator if great accuracy is not required (and also no use is being
made of the square-wave output). Note that if the output is
driving a low impedance load, a buffer circuit will be required
to prevent load current from affecting the charge and discharge rates of C.
Sawtooth Circuit Using Discrete Devices
It is usually simpler to use operational amplifier-based circuits, where the specifications allow, but their slew rate limit
can be overcome by using discrete components, and one implementation of a sawtooth generator is shown in Fig. 4. The
p-n-p Q1 is configured as a current source, but a more accurate current regulator circuit could be substituted, if required.
The collector current from Q1 charges the timing capacitor,
C, with the capacitor voltage used as the input to the differential pair Q2 and Q3 connected as a Schmitt Trigger. Initially,
let Q2 be off and Q3 be on. When the voltage on the base of
Q2 rises above that on the base of Q3, the circuit switches
regeneratively, so that its output at the collector of Q3 goes
high. This output, in turn, switches on Q4 and discharges C
turning Q2 off and Q3 on again.
This configuration has one disadvantage, in that Q4 must
conduct both the discharge current from C and the charging
current from Q1. Q4 must accommodate both of these currents,
and the discharge of C is thus slowed. A useful modification
is to use the Schmitt Trigger output from the collector of Q3,
to set the base voltage on Q1, so that it switches on and off in
antiphase with Q4, but output levels of the Schmitt Trigger
must be compatible with the bias requirements of Q1.
The input switching levels for the Schmitt Trigger can be
varied by changing VBB, allowing the circuit to be used as a
voltage to frequency converter if desired, since the time taken

222

RAMP GENERATOR

Q1

R1

Q2
V3

+Vi

Vi
R2

R3
Vi

for the capacitor voltage to ramp to the switching point will

vary. Q5 is simply an emitter follower to buffer the load.
VOLTAGE-CONTROLLED ARCHITECTURES
Some of the circuits can be modified to operate in voltagecontrolled mode, an example of which is shown in Fig. 5, and
is based on the triangle-wave generator from Fig. 2. Here the
comparator output controls two MOS transistors, Q1 and Q2,
acting as a CMOS inverter, effectively selecting either the
voltage on the n-channel source or the voltage on the p-channel source. The input control voltage, Vi, is applied to the pchannel source and its inverse is applied to the n-channel
source, via the unity gain inverting amplifier. Thus the integrator is integrating Vi rather than the comparator output,
so that the slope rate of the integrator output now depends
upon Vi. Since the voltage required at the input of the comparator to cause it to switch is constant, the effect is that
output frequency, f o, depends on Vi and, where the comparator output switches between VA, is given by (2):
V 1 + R1 /R2
fo = i
VA
4RC

Vo

R3

Figure 5. Voltage-controlled circuit for triangle-wave

generation illustrating the use of a CMOS inverter to
integrate the correct polarity of the input voltage Vi.

tooth circuit, which makes use of the THRESHOLD (TH) and

TRIGGER (TR) inputs and the DISCHARGE (DIS) terminal
(3). The capacitor C is charged via the p-n-p transistor working as a current source. When the voltage on the capacitor is
high enough to activate the TH input, C is discharged quickly
through the DIS pin (achieved by turning on an internal discharge transistor). When the voltage on C has fallen to the
value that activates the TR input, the discharge transistor is
turned off and the cycle begins again. The voltage on the
capacitor is therefore a sawtooth wave, which varies between
1/3 VCC and 2/3 VCC (in a 555 the TH input is activated for a
voltage greater than 2/3 VCC and the TR input is activated for
a voltage less than 1/3 VCC). A buffer is required as before to
avoid loading the capacitor. The frequency of operation can
be calculated from the values of VCC, C, and the current
source.

Vref
=

(4)

Note that the presence of the CMOS inverter circuit, in effect,

provides the additional inverter missing from the original triangle-wave generator (as discussed above) and the feedback
connection is brought to the inverting input of the comparator
this time. The operation is once again limited by amplifier
slew rate and the frequency varies linearly over a reasonably
large range. Care must be taken, however, to ensure that Vi
does not become too large; otherwise, the amplifier inverting
Vi will saturate and the circuit will not function correctly.
Figure 6 shows a further approach, where the circuit is
an extension of the current source-controlled circuit. Voltagecontrolled switches are switched between their open and
closed states by the operational amplifier output. The capacitor charge and discharge current is set by the voltage-controlled current sources whose control voltage is determined
by the input voltage Vi.
USING THE 555
555 integrated circuit components are used in many timing
circuits, as well as in ramp generators. Figure 7 shows a saw-

Rt

Voltage controlled
current source (LM)

LM1

A
B

S1
C

D
E

+
S2

Ct
R1

F
R2

LM2

Input Vi

Vref

Output Vo

Figure 6. Voltage-controlled circuit providing variable frequency triangle or sawtooth output using voltage-controlled current sources
switched to charge and discharge C.

RANGE IMAGES

+15 V (VCC)

R3

R1

6
2
7

R2

Vc

555

TH
TR
DIS

2. P. M. Chirlian, Analysis and Design of Integrated Electronic Circuits, 2nd ed., New York: Wiley, 1987.
3. P. Horowitz and W. Hill, The Art of Electronics, 2nd ed., Cambridge: Cambridge University Press, 1989.

+5

BIBLIOGRAPHY
1. J. Millman and C. C. Halkias, Integrated Electronics: Analog and
Digital Circuits and Systems, New York: McGraw-Hill, 1972.

= 50 A
+10

drops below VCC. This would then leave insufficient voltage

across the current sources, to allow for conduction (about 1 V
for the current regulator and a further 0.7 V for the gatedrain diode). The CMOS 555, however, produces a full-range
output swing.

8
VCC

Sawtooth

L. I. HAWORTH
A. F. MURRAY
Figure 7. 555 timer circuit for sawtooth-wave generation using a
transistor current source to charge C and the DIS terminal to discharge C.

If a triangle wave is required, the circuit of Fig. 8 can be

used (3), which operates in a similar way to the sawtooth circuit. It does not make use of the DIS pin, but does require a
bidirectional current source, which can be implemented as
two current-regulator-connected JFETs in series (e.g.,
1N5287, providing about 33 mA). Current flow is bidirectional, because one JFET will regulate the current, while the
other behaves like a forward-biased diode, due to gate-drain
conduction, and the square wave output of the 555 is used to
drive the current sources. When the 555 output is at VCC the
capacitor charges up to 2/3 VCC, whereupon the output
switches to 0 V and the capacitor discharges to 1/3 VCC, causing the output to switch back to VCC again. Once again, the
output varies between 1/3 VCC and 2/3 VCC, and an output
buffer is required. Finally, if this circuit is used with a 5 V
power supply it is essential to use a CMOS 555 variant, because bipolar 555s typically have a high output, two-diode

+15 V (VCC)

8
VCC

R
6
2

555

TH
TR

1
+10

Vc

+5

223

Triangle out

Figure 8. 555 timer circuit for triangle-wave generation which uses

two current-regulator-connected JFETs to provide charge and discharge current for C.

University of Edinburgh

RANDOM ACCESS MEMORIES. See SRAM CHIPS.

RANDOMNESS. See PROBABILITY.

302

RECTIFYING CIRCUITS

RECTIFYING CIRCUITS
Almost all electronic circuits need to utilize direct current (dc)
sources of power for operation. Hand-held and portable electronic equipment use replenishable or rechargeable batteries
as their main source of power. Normally, a power supply provides energy for all other electronic equipment. A power supply is composed of electronic circuitry that essentially converts alternating current to direct current. Electronic circuits
designed to accomplish this conversion are known as rectifying circuits (see Table 1). They are classified into three major categories:
Half-wave rectifier (HWR)
Full-wave rectifier (FWR)
Bridge rectifier
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

RECTIFYING CIRCUITS
Table 1. Comparison of the Three Rectifier Circuits

Number of diodes
Peak line voltage
rms line voltage
Peak inverse voltage
dc output voltage
Ratio of rectification
Transformer utilization factor
Ripple frequency
Ripple factor

Half-Wave

Full-Wave

One
Vm
V m / 2
Vm
0.318Vm
0.406
0.287
f
1.21

Two
Vma
Vm / 2
2Vm
0.636Vm
0.812
0.693b
2f
0.482

Bridge

303

the valleys of the pulsating dc signal output of the rectifier

and strives to accomplish a smooth dc output. The voltage
regulator tries to maintain a constant output voltage regardless of the fluctuations in the input ac signal and the output
dc load current consumption. Main equations pertaining to
the three rectifier circuits can be found in the Appendix 1, 2,
and 3.

Four
Vm
Vm / 2
Vm
0.636Vm
0.812
0.812
HALF-WAVE RECTIFIER CIRCUIT
2f
0.482

One-half the secondary coil voltage.

b
Average of primary and secondary coils.

At the present time, the silicon diode is the most commonly

used electronic device for rectification purposes. Semiconductor diodes have replaced previously used devices such as vacuum tube diodes and dry-disk or metallic rectifiers. Figures
1(a) and 1(b) show the constructional features of four types of
rectifiers that can be used to accomplish the task of converting alternating current (ac) to dc. The principle of rectification is to permit current flow in one direction only. The diode is capable of accomplishing this task because it conducts
only when it is forward biased. This means that the anode or
the positive electrode of the diode receives positive voltage.
When the cathode or the negative electrode is connected to the
positive supply terminal, the diode is reverse biased. Thereby
the diode can be used in an appropriate circuit, called a rectifier circuit, to convert an alternating waveform to a unidirectional waveform. While discussing rectifier circuits throughout this article a sinusoidal waveform is considered as input,
for convenience of mathematical treatment.
A rectifying circuit is normally used in conjunction with a
transformer, filter, and a voltage regulator. Figure 2 shows a
block diagram representation of a power supply. The transformer reduces or increases the amplitude of the ac voltage so
that appropriate dc magnitude is obtained after rectification
filteration and regulation. In addition, the transformer provides electrical isolation that may be necessary. The rectifier
circuit converts the sinusoidal output of the transformer to a
unidirectional pulsating dc signal. The filter circuit fills in

The basic action of a simple half-wave rectifier circuit with a

resistive load can be examined using a circuit shown in Fig.
3(a). A semiconductor diode, a load resistor, and the secondary coil of a transformer are connected in series. The primary
coil of the transformer receives the ac input supply. Let the
output voltage of the transformer secondary coil be represented as vi Vm sin t where vi is the instantaneous value
of the voltage and Vm is the peak value. Furthermore, let us
assume that the forward voltage drop of the diode is very
small (0.7 V for silicon and 0.3 V for germanium) compared
to the input signal. We find the relation i id iR, where i is
the current in the transformer secondary coil closed circuit,
id is the diode current, and iR is the current in the resistance
R. The diode offers a resistance Rf while conducting in the
on state and offers infinite resistance while not conducting
in the off state. Therefore, mathematically speaking, the
half-wave rectifier obeys the following equations:

id = iR = Im sin t if 0 t
i=
0 if t 2

where Im Vm /(Rf R).

Figures 3(b) and 3(c) represent the input and output waveforms. It is observed that the output load resistance experiences only one half cycle for every one full cycle of input waveform. The average value of one full cycle of the input
waveform can easily be computed to be equal to zero. Similarly, the average value of the output dc current can be calculated by considering one full cycle of the output waveform. It
needs to be recognized that the output waveform is only one
half cycle of the sine wave input. This is because the negative
half of the input waveform is not admitted to pass through

Cathode end
Metal

Cathode end

Cathode end

Cathode end

Copper

Bismuth-cadmium alloy

Magnesium

Barrier layer

Barrier layer

Barrier layer

Cuprous oxide

Selenium

Cupric sulfide

Lead

Aluminum

Copper

Anode end

Anode end

Anode end

Barrier layer

pn junction

(a)
Figure 1. Salient features of (a) metallic rectifiers and (b) a semiconductor diode (both not to
scale).

Metal
Anode end
(b)

304

RECTIFYING CIRCUITS

Figure 2. Block diagram showing components of power supply.

Ac input
supply

Transformer

the diode. When not conducting, the diode has to withstand

this peak inverse voltage (PIV) offered by the negative half
cycle. In this case, the magnitude of PIV [also called peak
reverse voltage (PRV)] equals Vm. The output waveform extends to 2 radians; however, only one half of the sine wave
from 0 to is available across the load resistor. Expressed
mathematically, this means


Idc = (1/2 )

Im sin t dt = Im /

The integration is carried out from 0 to because the current

between and 2 is zero. Across the output load resistance
the dc voltage Vdc IdcR ImR/.

Rectifier
diode
+

Ac
supply

Load
resistor

Transformer
(a)

Rectifier

Filter

Regulator

Dc output
to load

Similarly the dc voltage across the diode can be calculated

mathematically. However, a simpler way is to apply Kirchhoffs voltage law. Since the sum of dc voltages should total
zero, it is easily observed that the dc voltage across the diode
Vdiode ImR/ and the rms value of the current Irms Im /2.
FULL-WAVE RECTIFIER CIRCUIT
The full-wave rectifier circuit can be visualized as comprising
two half-wave rectifier circuits, strategically connected to the
center top of a transformer secondary coil. Such a circuit is
shown in Fig. 4(a). Two semiconductor diodes are connected
to the two ends of the transformer secondary coil. The load
resistor is connected between the center tap of the transformer secondary coil and the junction of the negative electrodes of the two diodes. The primary coil of the transformer
receives the ac input supply. The output voltage of the transformer secondary coil is again represented as vi Vm sin t.
Here Vm represents the peak transformer secondary coil voltage from one end to the center tap. Furthermore, let us again
assume that the forward voltage drop of the diode is very
small (this is normally represented as V) compared to the
input signal from the center-tapped transformer secondary
coil. We have the relations i1 id1 and i2 id2, where i1 is the
current in one half of the transformer secondary coil circuit,
i2 is and the current in the other half of the transformer secondary coil circuit, and id1 and id2 are diode currents. Also,
iR i1 i2, where iR is the current in the resistance. The dc
current can be calculated as in the previous case:
Idc = 2Im /
Vdc = 2ImR /

Vm

(b)

Average value of
output voltage
Vm
0

(c)
Figure 3. (a) Half-wave rectifier circuit; (b) input waveform shows
both halves of sine wave; (c) output waveform across the load resistor
shows only positive half cycle and negative half cycle appears across
diode.

where Im Vm /Rf R).

It must, however, be remembered that in this case, Vm represents the peak transformer secondary coil voltage from the
center tap to one end of the transformer. (The half-wave rectifier did not utilize a center-tapped secondary coil.) Figure 4(b)
represents the input waveform. Figure 4(c) through 4(h) represent the output waveforms. It is observed that the load resistance procures both halves of the sine wave. The output
waveforms are always positive, regardless of the fact that the
input waveform alternates between positive and negative
states every half-cycle. This is because when the top end of
the transformer secondary coil is positive with respect to the
center tap, diode D1 conducts and permits the flow of current
from right to left in the load resistor R. Diode D2 is open or
off because the bottom end of the transformer secondary coil
must be negative with respect to the center tap. When the
bottom end of the transformer secondary coil is driven positive with respect to the center tap, diode D2 conducts and
again permits the flow of current from right to left in the load
resistor R. Diode D1 is open or off because the top-end of the
transformer secondary coil must be negative with respect to
the center tap. It can be seen that in this full-wave rectifier

RECTIFYING CIRCUITS

i1

D1
+

Vm
B

Ac
supply

iR

R +

A
vo
Vm

FULL-WAVE BRIDGE RECTIFIER CIRCUIT

Center-tapped transformer
(a)

Vm
(b)

Vdc

(d)

Idc

Im

(e)

Vm
0

(f)

Vm
0

When a center-tapped transformer is not available, a bridge

rectifier circuit provides full-wave rectification. The bridge
consists of four diodes connected in a systematic loop as
shown in Fig. 5(a). This creates four junction points, a, b, c,
and d, as shown in the diagram. The transformer secondary
coil is connected between b and c, whereas the load resistor
is connected between a and d, as shown. Figure 5(b) represents the top end of the transformer secondary coil being positive with respect to the bottom end. Only diodes D1 and D4
are capable of conducting. Diodes D2 and D3 are off. The
transformer secondary coil, diode D1, the load resistor R, and
the diode D4 all form a series circuit, permitting the current
to flow in the load resistor from left to right. During the next
half cycle, the top end of the transformer secondary coil is
negative with respect to the bottom end. Therefore, only diodes D2 and D3 are capable of conducting. Diodes D1 and D4
are off. The transformer secondary coil, diode D2, the load
resistor R, and the diode D3 form a series circuit, permitting
the current to flow in the load resistor, again, from left to
right. This is shown in Fig. 5(c). It is important to observe
that the current in the load resistor is always from a to d
regardless of whether b is positive or negative. The bridge
rectifier circuit is the best choice; however, it suffers from a
minor disadvantage. It needs four diodes instead of two. However, the PIV of each diode is only Vm and not 2Vm, as in the
case of full-wave rectifier. Currently, ready-made bridges are
mass manufactured and are available in an encapsulated
form. A schematic is shown Fig. 5(d).
VOLTAGE REGULATION
Voltage regulation provides the engineer a measure to study
the behavior of the circuit under changing load-current conditions. The percentage of voltage regulation is defined as
VR% = [100(Vno load Vfull load )]/Vfull load

2Vm

(g)

(h)

(c)
0

circuit, the PIV across each diode is twice the maximum

transformer voltage measured from the center tap to either
the top or bottom end. Voltages experienced by diodes D1 and
D2 are shown in Figs. 4(g) and 4(h). In each case the voltages
equal 2Vm, where Vm is the peak voltage corresponding to one
half of the secondary coil.

i2

D2
+

305

2Vm

Figure 4. (a) Full-wave rectifier circuit (ideal diodes); (b) input

waveform; (c) load voltage waveform; (d) load current waveform; (e)
current in diode D1; (f ) current in diode D2; (g) voltage across diode
D1; (h) voltage across diode D2.

Ideally, the voltage regulation of a well-designed power supply should be zero. In other words, the voltage delivered by
the power supply should be totally independent of the current
drawn by the load. Suppose the supply is rated 12 V dc. The
instrument should deliver 12 V, whether it is delivering zero
load current (no load) or 600 A load current. Such stringent
specification require highly sophisticated electronic circuits.
It is possible to achieve VR% of less than 1%. An example of
a regulation curve is shown in Fig. 6. This graph indicates
that the power-supply voltage drops from 12 V at zero current
to 8 V at full load of 5 A. The percentage of voltage regulation
can be calculated as follows:
VR% = [(12 8)/8](100) = 50%

306

RECTIFYING CIRCUITS

Secondary
output voltage

Ac input
supply

D1

D2
RLOAD

D4

D3
c

Transformer
(a)

b
D1
Ac input
supply
(positive
half
cycle)

RLOAD

+
a

iR

D4
c

(b)

~ ~ +

Ac input
supply
(negative
half
cycle)

D2

iR

a
+

Figure 5. (a) Bridge rectifier circuit; (b) current path, top

end positive; (c) current path, top end negative (observe that
the current iR in the load resistance is always from a to d,
left to right); (d) encapsulated bridge rectifier.

RLOAD
D3
c
(c)

Ac input
supply
leads

Dc output
delivery
leads

(d)

The minimum load resistance that can be connected to the

power supply is calculated as
Rload (minimum) = Vfull load /Ifull load = 8/5 = 1.6 
14

RIPPLE

12

Vdc (V)

10
8
6
4
2

2
3
Idc (A)

Figure 6. Regulation graph of a 12-V supply.

The output signal of a full-wave rectifier has a frequency

equal to twice the value of the input signal frequency. With a
60 Hz input, a 120 Hz unwanted signal appears at the output,
in addition to the dc output. This undesired ac component of
output is called ripple. In other words, ripple is small
amounts of alternating current waveforms superimposed on
the dc waveform. The ratio of the amount of ripple to the dc
value is called the ripple factor. It can also be expressed in
percent values and identified as percent ripple. The ripple factor provides the engineer with a measure to examine the effectiveness of the rectifier circuit. A ripple factor greater than
1 means that the amount of alternating current in the output
is greater than the amount of direct current in the output. It
is imperative that rectifier circuits need to be appropriately
designed to achieve ripple factors less than 1. The engineer

RECTIFYING CIRCUITS

Vout

Vc

120 Hz Ripple
Vdc

Time
(a)

307

all electronic circuitry demands a smooth dc voltage that is

constant in value and closely resembles the output voltage of
a good battery source. This conversion of half-wave and fullwave signals to constant dc voltage values is accomplished
using a filter. Several types of filters are available, the simplest being a single capacitor. Other types include a choke
filter, filter, and double filter. The capacitor charges when
the diode is conducting and discharges via the load resistor
when the diode is off. The action of the capacitor can be examined by referring to Figs. 8(a) to 8(e). Let us choose a large
capacitor so that the capacitance sustains a voltage as defined
by the point a or c as shown in Fig. 8(b). During the positive

B
+

Vc
+

Vdc
Ac
supply

RLoad

(b)

(a)

VB

(c)

(b)

Figure 7. (a) Output waveform of a power supply unit contains a

120 Hz ripple; (b) dc component of the output waveform; (c) ac component of the output waveform.

can thus ensure that the amount of alternating current in the

output is less than the amount of direct current in the output.
Ripple is directly proportional to the load current Idc and inversely proportional to the capacitance. However, capacitive
filters help provide smooth dc output waveforms. Let Fig.
7(a) represent the output waveform of a power-supply unit.
This waveform is made up of two components, a dc component
shown in Fig. 7(b), and an ac component, shown in Fig. 7(c).
A perfectly designed rectifier circuit should deliver a smooth
dc output.
Mathematically, we can write this statement as

aa

Vm

c
Dc voltage

0
(c)

b
0

d
Dc current c

(d)

Va2 + Vb2 = Vc2

Ripple has been defined as the ratio of Vb to Va, Vb /Va. If the
rms value of the ripple voltage is given as Vr, then the ripple
factor is Vr /Vdc.

(e)

FILTERS
The pulsating dc output signals from the half-wave, full-wave,
and bridge rectifiers have very limited applications. Almost

Figure 8. (a) Half-wave rectifier with a capacitor filter across the

load resistor; (b) capacitor must be large enough to fill in the valleys (shaded); (c) voltage across load resistor; (d) current through
load resistor; (e) diode current.

308

RECTIFYING CIRCUITS

Iron core
inductance

Ac
input
RLoad

Transformer

Ac
input
supply

Dc
output
to
RLOAD

L
Full-wave
rectifier

Figure 11. Full-wave rectifier with filter (LC combination) and

load resistor R.

Bridge
rectifier
(a)

Rsurge

Ac
input

RLoad

Bridge
rectifier

Transformer

(b)
Figure 9. (a) Bridge rectifier with load resistor RLOAD and filter capacitor C; (b) the addition of a surge resistance limits the sudden gush
of current that takes place during the instant the circuit is energized.

half of the supply cycle, when the diode is conducting, the

capacitor gets charged. This charging operation takes place
during the time interval between a and b. At point b the
charging current ceases because the diode is reverse biased
and has stopped conducting. But the load continues to receive
current from the discharging capacitor during the time interval from b to c. Again, at point c the capacitor begins its
charging operation and the cycle repeats. The load resistor
voltage and current waveforms are shown in Figs. 8(c) and
8(d), respectively. A full-wave rectifier with a single capacitance across the load is shown in Fig. 8(e). The corresponding
output waveform, with the action of its filter capacitor, is
shown in Fig. 8(f). An approximate analysis yields
Vdc = Vm Idc /4 fC

Ac input supply

D1

where f is the power line frequency and C represents the

value of filter capacitor used.
Instead of using only a capacitance, sometimes a resistance called the surge resistance is often used in addition to
the load resistance, as shown in Fig. 9(b). The filter capacitor
is initially uncharged and acts as a short circuit when the
circuit shown in Fig. 9(a) is energized. Therefore there is sudden inrush of current, and this is called the surge current. In
some cases this current surge may be large enough to destroy
the diodes. Therefore a current-limiting resistor is added in
series as shown in Fig. 9(b). Other combinations of resistances and capacitances are also used. A two-section RC filter used in conjunction with a full-wave rectifier is shown in
Fig. 10.
When the load current is heavy, an LC filter, which is
also called a choke filter, is preferred to an RC filter. The
ripple can be reduced by choosing the inductive reactance to
be much higher than the capacitive reactance. For example,
if XL is ten times as large as XC, then the ripple is attenuated
by a factor of 10. An example wherein a full-wave rectifier
employs one section in which LC filters are used is shown in
Fig. 11. This is also called a filter. Using two sections results in an improvement in the value of ripple. Still further
reduction in ripple can be accomplished by using a double
filter as shown in Fig. 12. However, the voltage regulation
may be poorer because of voltage drop in the choke filters.
Rectifier circuits combined with appropriate filter circuits provide a convenient method of converting ac to dc. However, the
proper choice depends upon the application desired. Some of
the factors that need to be considered are the permissible ripple, the regulation required, the nature of load current desired, the size and weight of the complete network, and the
cost of components. A choke filter should consist of pure inductance; however, it possesses a small amount of resistance.
A filter that includes the choke resistance of the coil as well

RLoad

Iron core
inductances
D1,D2

Rectifier diodes

D2
Center-tapped
transformer
Figure 10. Two-section RC filter can reduce the ripple by a factor
of 2 where is the ripple factor for one RC section.

Ac
input
supply

L
Full-wave C
rectifier

L
C

Figure 12. Full-wave rectifier with double filter.

Dc
output
to
RLOAD

RECTIFYING CIRCUITS

309

R
3 Vm

Input
from
rectifier

C1

C2

Output
to
load

Vm

2Vm

C1
Vm

D1

+
C3

D2

D3

C2
+

Figure 13. Capacitance input filter.

2Vm

is shown in Fig. 13. This is also called a capacitance input

filter. Another version, called a Tee filter or a choke input
filter is shown in Fig. 14. Under light load conditions, capacitor input filters help rectifiers generate fairly smooth dc signals with small ripple. However, the regulation is relatively
poor. In addition, as the load currents increase ripple also increases.
RATIO OF RECTIFICATION
The ratio of rectification is defined as the ratio of dc output
power delivered by the rectifier circuit to the ac input power
delivered to the rectifier circuit. It needs to be recognized that
the transformer is an ac apparatus and therefore it is possible
to calculate the rms value of the load voltage and the rms
value of the load current. The product of these two values
yields the total power delivered by the transformer. However,
the objective of the rectifier circuit is to provide direct current
to the load. Therefore one can calculate the dc voltage and
the dc current at the load resistor. The product of these two
quantities results in the dc load power. The ratio of rectification can thus be determined. However, this ratio should not
be confused as an efficiency measure because efficiency calculations include the losses in the transformer as well as the
diodes.
Voltage Doublers
By suitably modifying the full-wave and the bridge rectifier
circuits, it is possible to create circuits that can provide twice
the peak supply voltage, or 2Vm. By cascading several voltage
doubler circuits suitably, it is possible to generate very high
dc voltages. The full-wave voltage doubler circuit is shown in
Fig. 13(a). Another interpretation of the circuit is shown in
Fig. 13(b) wherein the load resistor is omitted for sake of clarity. Diode D1 charges the capacitor C1 when the top end of

L1

L2

R1

Figure 15. Voltage tripler.

the supply source is positive with respect to the bottom end.

Similarly, diode D2 charges the capacitor C2 when the bottom
end is positive with respect to the top end of the input source.
In this circuit, each capacitor is charged once per cycle, but at
different times. The capacitors therefore receive two charging
pulses per cycle. Furthermore it is observed that capacitances
C1 and C2 are in series. This results in a doubling effect.
Figure 13(c) shows the waveform across the two capacitors
and indicates how they add up. The load resistor may be connected between the two extreme ends of the two capacitors
as shown in the diagram. The ripple frequency is twice the
frequency of the supply and the ripple is greater and the regulation poorer compared with an equivalent full wave rectifier.
Figure 14(a) shows the half-wave voltage doubler circuit.
It is also called the cascade voltage doubler circuit. Diode D1
operates when the bottom end of the supply is positive and
charges the capacitor C1 to the maximum value of the supply
voltage Vm as shown. During the next half cycle, when the top
end of the supply is positive, the supply voltage is actually
aiding the capacitor C1 because of the series connection of
the supply and capacitor C1. The maximum possible value is
2Vm, and therefore the capacitor C2 charges to the same value
of 2Vm via diode D2. The load need only be connected across
capacitor C2, unlike the previous case wherein the load was
connected across a series combination of capacitors C1 and
C2. Therefore the load receives only one charging pulse per
cycle. The ripple is very high, but its frequency in this case is
the same as the supply line frequency. The voltage regulation
of this circuit is also very poor.
Voltage tripler and voltage quadrupler circuits are shown
in Figs. 15 and 16. It is possible to design circuits that provide
more than 4Vm. However, the such circuits result in extremely
poor voltage regulation.

Vm

R2

2 Vm

+
C1
Input
from
rectifier

Output
to
load

D1

D2

+
C3
D3

C2
+

C4
+

2 Vm
Figure 14. Choke input tee filter.

2 Vm
4 Vm

Figure 16. Voltage quadrupler.

D4

310

RECTIFYING CIRCUITS

0
Rs
Input

Output

RL

Output

Input

Rs

Output

Input

RL

Output

Input

Output

Output

Rs
Input

RL

Output

Input

Rs

V
0

Input

RL

Output

Input

(a)

(b)

Figure 17. Clipper circuits modify the sine wave input. (Input voltage waveform remains the
same for all circuits.) (a) Left: Rectifier diodes used as clippers; Right: Waveform across output
load resistor RL. (b) Left: Rectifier diodes used as clippers; Right: Waveform across, output,
diodebattery series combination where RS series resistor.

Clippers
Many electronic circuits demand the removal of unwanted
signals below or above a predetermined or specified voltage
level. By suitably rearranging a diode rectifier circuit and a
dc battery power supply, it is possible to obtain a variety of
clipper circuits. A sample of selected clipper circuits along
with their output waveforms is shown in Fig. 17. All these
circuits assume a sinusoidal input voltage of 50 V peak-topeak magnitude (Vm 25 V).
Clampers
A clamper adds a dc component to the signal. The principle is
to utilize the charging nature of a capacitor. Selected exam-

ples of clamper circuits are shown in Fig. 18. The clamper is

also called a dc restorer, particularly when associated with
television circuitry. All these circuits assume a sinusoidal input voltage of 50 V peak-to-peak magnitude (Vm 25 V).

APPENDIX 1. HALF-WAVE RECTIFIER CALCULATIONS

The rms value of a complete sine wave is Vm / 2. The output
of the half-wave rectifier is only one half of a sine wave.
Therefore, the rms value of the load voltage is equal to
(1/ 2)(Vm / 2) Vm /2. The average or dc value Vdc of this
rectified sine wave is Vdc Vm / 0.318Vm. The rms value of

RECTIFYING CIRCUITS

311

+2Vmax
Output

Input

C
R

0
Output

Input

C
R

+2Vmax

VB

0
VB

Output

Input

+2Vmax

Input

VB

+2Vmax

VB

+2Vmax

0
VB

Output

Output

Input

Input

Output

VB

R
VB

+2Vmax
0
VB

(b)

(a)

Figure 18. (a) Clamper circuits retain shape of the input sine waveform, but add a dc bias to
the waveform. (b) Left: While designing clamping circuits, it is essential that 5 RC T/2, where
T period of sine wave; Right: Output waveforms of clamping circuits obtained across resistance, R (Input voltage waveform for all six clamping circuits).

the ripple voltage is Vr. Therefore (Vm /2)2 (Vm /)2 (Vr)2
Solving, Vr 0.386Vm.
The ripple factor is Vr /Vdc 0.386Vm /0.318Vm 1.21.
ac
ac
ac
dc
dc
dc

load
load
load
load
load
load

voltage
current
power
voltage
current
power

Vm /2
(Vm /2)/R
(Vm /2)[(Vm /2)/R] Vm2 /4R
Vm /
Vm /R
(Vm /)(Vm /R) Vm2 /2R

The ratio of rectification is the dc load power divided by the

ac load power, or (Vm2 /2R)/(Vm2 /4R). The ratio of rectification
is 4/2 0.406. This is no indication of the efficiency; however,
it can be stated that the overall operating efficiency of a halfwave rectifier with a resistive load cannot be greater than
40.6%. An ideal rectifier has no losses and has therefore a
100% power efficiency.
The rating of the secondary winding of the transformer is
Vm / 2 V.
ac current in the secondary
winding the ac load
current

(Vm /2)/R A

ac power rating of the transformer

Transformer utilization
factor
Transformer utilization
factor

(Vm / 2)[(Vm /2)/R]

Vm2 /22R W
(dc load power)/(ac power
rating)
(Vm2 /2R)/(Vm2 /22R)
22/2 0.287

APPENDIX 2: FULL-WAVE RECTIFIER CALCULATIONS

In this case both halves of the ac input sine wave are rectified
and utilized. Therefore the magnitude of several of the values
that were calculated for the half-wave rectifier gets multiplied
by a factor of 2. The rms value of a complete sine wave is
Vm / 2. The average of dc value of the rectified sine wave
Vdc 2Vm / 0.636Vm. The rms value of the ripple voltage
is Vr. Therefore (Vm / 2)2 (2Vm /)2 (Vr)2. Solving, Vr
0.307Vm.
The ripple factor is Vr /Vdc 0.307Vm /0.636Vm 0.482.
ac
ac
ac
dc

load
load
load
load

voltage
current
power
voltage

Vm / 2
(Vm / 2)/R
(Vm / 2)[(Vm / 2)/R] Vm2 /2R
2Vm /

312

RECTIFYING CIRCUITS
Table 2. Rectifier Circuit Terminology
Term

Input (ac)

Output (dc)

Half-wave rectifier

VRMS (Vm / 2) 0.707Vm

IRMS (Im /2) 0.5Im

Efficiency of HWR (purely

resistive load)

[(IDC)2RLOAD]/[(IAC)2RLOAD] (0.318Im)2 /(0.5Im)2 0.406

Efficiency of FWR (purely

resistive load)

Vdc VAVG (Vm /) 0.318Vm

Idc IAVG (Im /) 0.318Im

VRMS (Vm / 2) 0.707Vm

Vdc VAVG 2(Vm /) 0.636Vm
IRMS (Im / 2) 0.707Im
Idc IAVG 2(Im /) 0.636Im
[(Idc)2RLOAD]/[(IAC)2RLOAD] (0.636Im)2 /(0.707Im)2 0.812

a
It is important to observe that in a half-wave rectifier (HWR), the voltage is present during both half cycles.
Therefore, VRMS 0.707 Vm; however, the current flows for only one half cycle. Therefore IRMS 0.5 Im. For the
above calculations, an ideal rectifier has been assumed and therefore the internal resistance of the rectifier r
has been ignored.

dc load current
dc load power

2Vm /R
(2Vm /)(2Vm /R) 4Vm2 /2R

The ratio of rectification is the dc load power divided by the

ac load power, or (4Vm2 /2R)/(Vm2 /2R). The ratio of rectification
is 8/2 0.812. The overall operating efficiency is therefore
twice that of a half-wave rectifier, that is, 81.2%.
The full-wave rectifier utilizes the center-tapped secondary
winding of a transformer. But the primary coil has a single
winding. Therefore the calculations for the primary and secondary circuits must be done separately. The secondary coil
of the transformer actually contains two circuits. Each circuit
performs the function of a half-wave rectifier. Therefore the
transformer utilization factor for the secondary coil is twice
that of the half-wave rectifier.
The transformer utilization factor for secondary winding is
2(0.287) 0.574. Disregarding the center tap, we can calculate the transformer utilization factor for the primary
winding.
dc load voltage
dc load current

lations that were carried out for the full-wave rectifier are
still valid in this case. The rms value of a complete sine wave
is Vm / 2. The average or dc value of the rectified sine wave
Vdc 2Vm / 0.636Vm. The rms value of the ripple voltage
is Vr. Therefore (Vm / 2)2 (2Vm /)2 (Vr)2. Solving, Vr

Vmax

Vdc 2Vm /
Idc 2Vm /R 2Im /, Im Vm /R.

The rating of the transformer winding can be calculated using

the rms values of voltage and current:

Vrms = Vm / 2 V, Irms = Im / 2 A

(a)
Vmax

VRMS

VRMS =

Vmax

= 0.707 Vmax
2
Vdc = 0.318 Vmax

VDC

Substituting and rearranging, we obtain

Vdc = (2 2/ )Vrms

Idc = (2 2/ )Irms
The dc power can now be determined in terms of the ac power:

(b)

Vmax

Vdc Idc = (8/ 2 )Vrms Irms

The transformer utilization factor is the dc power divided by
the ac power or VdcIdc /VrmsIrms 8/2 0.812. The average
transformer utilization factor is (0.574 0.812)/2 0.693.

VDC = VAVG
0

APPENDIX 3. BRIDGE RECTIFIER RIPPLE CALCULATIONS

Both halves of the ac input sine wave are rectified and utilized in a bridge rectifier as well. Therefore many of the calcu-

(c)
Figure 19. Half-wave rectification waveforms: (a) One full cycle of
input sine wave; (b) Output waveform: half-wave rectifier; (c) Averaging over one full cycle.

RECTIFYING CIRCUITS

313

siderable variation, or ripple in the rectified output. A ripple

factor is therefore defined, that helps in evaluating and comparing different rectifier circuits.

Vmax

Effective value of alternating current

portion of rectified output wave
Ripple factor =
Average value of rectified output wave

(a)

A filter is a circuit that is used to eliminate undesired ripple

from the output voltage of the rectifier. Normally, a welldesigned capacitor is used to obtain a smooth dc output from
a rectifier. The necessary capacitance can be calculated using
the following formula:
C = [(load current)(one full cycle of waveform)]/
[twice ripple voltage]

V
VRMS = max = 0.707 V
max
2
Vdc = 0.636 Vmax

Vmax
VRMS
Vdc

(b)

Vmax
Vdc

Vdc = VAVG

(c)
Figure 20. Full-wave rectification waveforms: (a) One full cycle of
input sine wave; (b) Output waveform: full-wave rectifier; (c) Averaging over one full cycle.

0.307Vm. The ripple factor is Vr /Vdc 0.307Vm /0.636Vm

0.482. The ratio of rectification will not change and remains
0.812, as it was for the full-wave rectifier. There is no secondary center tap; therefore the transformer utilization factor is
0.812, as it was for the full-wave rectifier when we disregarded the center tap.
EPILOGUE
The main objective of a rectifier circuit is to convert alternating current/voltage into pure direct current/voltage. A rectifier diode accomplishes this. As an example, 1N4004 diode
has a rating of 1 ampere and 400 volts PIV. However, instead
of providing a steady output current/voltage, the rectifier circuit might be delivering a current/voltage that may have con-

For example, using the frequency in the U.S., i.e., 60 Hz, period 1/60 s. If the load current is 10 amperes and only 3
volts peak-to-peak ripple voltage is permitted, then capacitance required will be [10(1/60)]/[(2)(3)] 27,777.77 microfarads.
Table 2 and Figs. 19 and 20 help clarify the terminology
associated with rectifier circuits.
BIBLIOGRAPHY
C. L. Alley and K. W. Atwood, Microelectronics, Englewood Cliffs, NJ:
Prentice-Hall, 1986.
G. L. Batten, Jr., Programmable Controllers, New York: McGrawHill, 1994.
D. A. Bell, Electronic Devices and Circuits, 3rd ed., Englewood Cliffs,
NJ: Prentice-Hall, 1980.
R. Boylestad and L. Nashelsky, Electronic Devices and Circuit Theory,
3rd ed., Englewood Cliffs, NJ: Prentice-Hall, 1982.
J. J. Carr, Elements of Electronic Instrumentation and Measurement,
3rd ed., Englewood Cliffs, NJ: Prentice-Hall, 1996.
J. J. Carr, Sensors and Circuits, Englewood Cliffs, NJ: PrenticeHall, 1993.
J. R. Carstens, Electrical Sensors and Transducers, Prentice-Hall,
1993.
G. M. Chute and R. D. Chute, Electronics in Industry, 5th ed., New
York: McGraw-Hill, 1979.
W. D. Cooper and A. D. Helfrick, Electronic Instrumentation and Measurement Techniques, Englewood Cliffs, NJ: Prentice-Hall, 1985.
E. O. Doebelin, Measurement Systems, 4th ed., New York: McGrawHill, 1990.
E. O. Doebelin, Engineering Experimentation, New York: McGrawHill, 1995.
R. C. Dorf and J. A. Svoboda, Introduction to Electric Circuits, 3rd
ed., New York: Wiley, 1996.
R. C. Dorf and R. H. Bishop, Modern Control Systems, 7th ed., Reading, MA: Addison-Wesley, 1995.
J. R. Eaton and E. Cohen, Electric Power Transmission Systems, 2nd
ed., Englewood Cliffs, NJ: Prentice-Hall, 1983.
D. G. Fink and H. W. Beaty, Standard Handbook for Electrical Engineers, New York: McGraw-Hill, 1993.
A. R. Hambley, Electronics, New York: Macmillan, 1994.
M. Kaufman and A. H. Seidman, Handbook of Electronics Calculations, New York: McGraw-Hill, 1979.
E. N. Lurch, Fundamentals of Electronics, 3rd ed., New York: Wiley,
1981.

314

RECURSION

A. P. Malvino, Electronic Principles, 2nd ed., New York: McGrawHill, 1979.

J. Millman and A. Grabel, Microelectronics, 2nd ed., New York:
McGraw-Hill, 1987.
M. H. Rashid, Microelectronic Circuits, Boston, MA: PWS Publishing
Co., 1999.
J. Webb and K. Greshock, Industrial Control Electronics, Columbus,
Ohio: Merrill Publishing Co., 1990.

MYSORE NARAYANAN
Miami University

RELAXATION OSCILLATORS AND NETWORKS

Relaxation oscillations comprise a large class of nonlinear
dynamical systems, and arise naturally from many physical systems such as mechanics, geology, biology, chemistry,
and engineering. Such periodic phenomena are characterized by intervals of time during which little happens, interleaved with intervals of time during which considerable
changes take place. In other words, relaxation oscillations
exhibit two time scales. The dynamics of a relaxation oscillator is illustrated by the mechanical system of a seesaw
in Figure 1. At one side of the seesaw is there a water container which is empty at the beginning; in this situation the
other side of the seesaw touches the ground. As the weight
of water running from a tap into the container exceeds that
of the other side, the seesaw ips and the container side
touches the ground. At this moment, the container empties itself, and the seesaw returns quickly to its original
position and the process repeats.
Relaxation oscillations were rst observed by van der
Pol [1] in 1926 when studying properties of a triode circuit.
Such a circuit exhibits self-sustained oscillations. van der
Pol discovered that for a certain range of system parameters the oscillation is almost sinusoidal, but for a different
range the oscillation exhibits abrupt changes. In the latter case, the period of the oscillation is proportional to the
relaxation time (time constant) of the system, hence the
term relaxation oscillation. van der Pol [2] later gave the
following dening properties of relaxation oscillations:
1. The period of oscillations is determined by some form
of relaxation time.
2. They represent a periodic autonomous repetition of
a typical aperiodic phenomenon.
3. Drastically different from sinusoidal or harmonic oscillations, relaxation oscillators exhibit discontinuous jumps.
4. A nonlinear system with implicit threshold values,
characteristic of the all-or-none law.
A variety of biological phenomena can be characterized
as relaxation oscillations, ranging from heartbeat, neuronal activity, to population cycles; the English physiologist
Hill [3] even went as far as saying that relaxation oscillations are the type of oscillations that governs all periodic
phenomena in physiology.
Given that relaxation oscillations have been studied in
a wide range of domains, it would be unrealistic to provide
an up-to-date review of all aspects in this article. Thus, I
choose to orient my description towards neurobiology and

Figure 1. An example of a relaxation oscillator: a seesaw with a

water container at one end (adapted from [4]).

emphasize networks of relaxation oscillators based on the

following two considerations (the reader is referred to [4]
for an extensive coverage of relaxation oscillations). First,
as described in the next section, neurobiology has motivated a great deal of study on relaxation oscillations. Second, substantial progress has been made in understanding
networks of relaxation oscillators. In the next section, I describe a number of relaxation oscillators, including the van
der Pol oscillator. The following section is devoted to networks of relaxation oscillators, where the emergent phenomena of synchrony and desynchrony are the major topics. Then, I describe applications of relaxation oscillator
networks to visual and auditory scene analysis, which are
followed by some concluding remarks.
RELAXATION OSCILLATORS
In this section I introduce four relaxation oscillators. The
van der Pol oscillator exemplies relaxation oscillations,
and has played an important role in the development of dynamical systems, in particular nonlinear oscillations. The
Fitzhugh-Nagumo oscillator and the Morris-Lecar oscillator are well-known models for the conductance-based membrane potential of a nerve cell. The Terman-Wang oscillator
has underlain a number of studies on oscillator networks
and their applications to scene analysis. As demonstrated
by Nagumo et al. [5] and Keener [6], these oscillator models
can be readily implemented with electrical circuits.
Van der Pol Oscillator
The van der Pol oscillator can be written in the form

x + x = c(1 x2 )x

(1)

where c > 0 is a parameter. This second-order differential

equation can be converted to a two variable rst-order differential equation,

x = c[y f (x)]

(2)

y = x/c

(2)

Here f (x) = x + x3 /3. The x nullcline, i.e. x = 0, is a cubic

curve, while the y nullcline, y = 0, is the y axis. As shown

in Fig. 2(a), the two nullclines intersect along the middle
branch of the cubic, and the resulting xed point is unstable
as indicated by the ow eld in the phase plane of Fig. 2(a).
This equation yields a periodic solution.
As c > 1, Eq. (2) yields two time scales: a slow time scale
for they variable and a fast time scale for the x variable.
As a result, Eq. (2) becomes the van der Pol oscillator that
produces a relaxation oscillation. The limit cycle for the van
der Pol oscillator is given in Fig. 2(b), and it is composed of
four pieces, two slow ones indicated by pq and rs, and two
fast ones indicated by qr and sp. In other words, motion
along the two branches of the cubic is slow compared to
fast alternations, or jumps, between the two branches. Fig.
2(c) shows x activity of the oscillator with respect to time,
where two time scales are clearly indicated by relatively
slow changes in x activity interleaving with fast changes.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Relaxation Oscillators and Networks

Morris-Lecar Oscillator
In modeling voltage oscillations in barnacle muscle bers,
Morris and Lecar [9] proposed the following equation,

x = gCa m (x)(x 1) gK y(x xK ) gL (x xL ) + I

y = [y (x) y]/y (x)

(4)
(4)

where
m (x) = {1 + tanh[(x x1 )/x2 ]}/2
y (x) = {1 + tanh[(x x3 )/x4 ]}/2
y (x)
= 1/cosh[(x x3 )/(2x4 )]

Figure 2. Phase portrait and trajectory of a van der Pol oscillator. (a) Phase portrait. The x nullcline is the cubic curve, and the y
nullcline is the y axis. Arrows indicate phase ows. (b) limit cycle
orbit. The limit cycle is labeled as pqrs, and the arrowheads indicate the direction of motion. Within the limit cycle, qr and sp are
two fast pieces (indicated by double arrowheads), and pq and rs
are slow pieces. (c) Temporal activity of the oscillator. Here the x
activity is shown with respect to time.

By simplifying the classical Hodgkin-Huxley equations [5]

for modeling nerve membranes and action potential generation, FitzHugh [7] and Nagumo et al. [8] gave the following two-variable equation, widely known as the FitzHughNagumo model,

y = (x + by a)/c

Terman-Wang Oscillator
Motivated by mathematical and computational considerations, Terman and Wang [11] proposed the following equation,

FitzHugh-Nagumo Oscillator

x = c[y f (x) + I]

and x1 x2 , x3 , x4 , gCa , gK , gL , xK , and xL are parameters.

Ca stands for calcium, K for potassium, L for leak, and I is
the injected current. The parameter controls relative time
scales of x and y. Like Eq. (3), the Morris-Lecar oscillator is
closely related to the Hodgkin-Huxley equations, and it is
used as a two-variable description of neuronal membrane
properties or the envelope of an oscillating burst [10]. The
x variable corresponds to the membrane potential, and y
corresponds to the state of activation of ionic channels.
The x nullcline of Eq. (4) resembles a cubic and the y
nullcline is a sigmoid. When is chosen to be small, the
Morris-Lecar equation produces typical relaxation oscillations. From the mathematical point of view, the sigmoidal
y nullcline marks the major difference between the MorrisLecar oscillator and the FitzHugh-Nagumo oscillator.

(3)
(3)

where f(x) is as dened in Eq. (2), I is the injected current,

and a, b, and c are system parameters satisfying the conditions: 1 > b > 0, c2 > b, and 1 > a > 1 2b/3. In neurophysiological terms, x corresponds to the neuronal membrane
potential, and y plays the aggregate role of three variables
in the Hodgkin-Huxley equations. Given that the x nullcline is a cubic and the y nullcline is linear, the FitzHughNagumo equation is mathematically similar to the van der
Pol equation. Typical relaxation oscillation with two time
scales occurs when c > 1. Because of the three parameters
and the external input I, the FitzHugh-Nagumo oscillator
has additional exibility. Depending on parameter values,
the oscillator can exhibit a stable steady state or a stable
periodic orbit. With a perturbation by external stimulation,
the steady state can become unstable and be replaced by
an oscillation; the steady state is thus referred to as the
excitable state.

x = f (x) y + I

y = [g(x) y]

(5)
(5)

where f (x) = 3x x3 + 2, g(x) = [1 + tanh(x/)], and I

represents external stimulation to the oscillator. Thus x
nullcline is a cubic and the y nullcline is a sigmoid, where
and are parameters. When  1, Eq. (5) denes a typical
relaxation oscillator. When I > 0 and with a small , the
two nullclines intersect only at a point along the middle
branch of the cubic and the oscillator produces a stable periodic orbit (see Fig. 3(a)). The periodic solution alternates
between silent (low x) and active (high x) phases of near
steady-state behavior. As shown in Fig. 3(a), the silent and
the active phases correspond to the left branch (LB) and
the right branch (RB) of the cubic, respectively. If I < 0, the
two nullclines of Eq. (5) intersect at a stable xed point
along the left branch of the cubic (see Fig. 3(b)), and the
oscillator is in the excitable state. The parameter determines relative times that the periodic solution spends in
these two phases. A larger results in a relatively shorter
active phase.
The Terman-Wang oscillator is similar to the aforementioned oscillator models. It is much simpler than the
Morris-Lecar oscillator, and provides a dimension of exibility absent in the van der Pol and FitzHugh-Nagumo
equations. In neuronal terms, the x variable in Eq. (5) cor-

Relaxation Oscillators and Networks

chrony in a locally coupled network. Specically, Somers

and Kopell using relaxation oscillators and Wang using
Wilson-Cowan oscillators [18] each demonstrated that an
oscillator network can synchronize with just local coupling.
Note that Wilson-Cowan oscillators in their normal parameter regime are neither sinusoidal nor relaxation-type.
Two Oscillators: Fast Threshold Modulation

Figure 3. Nullclines and trajectories of a Terman-Wang oscillator. (a) Behavior of a stimulated oscillator. The x nullcline is a cubic
and the y nullcline is a sigmoid. The limit cycle is shown with a
bold curve, and its direction of motion is indicated by arrowheads.
LB and RB denote the left branch and the right branch of the cubic,
respectively, (b) Behavior of an excitable (unstimulated) oscillator.
The oscillator approaches the stable xed point PI .

responds to the membrane potential, and y the state for

channel activation or inactivation.
NETWORKS OF RELAXATION OSCILLATORS
In late eighties, neural oscillations in the gamma frequency
range (about 40 Hz) were discovered to in the visual cortex
[12] [13]. The experimental ndings can be summarized as
the following: (1) neural oscillations are triggered by sensory stimulation, and thus the oscillations are stimulusdependent; (2) long-range synchrony with zero phase-lag
occurs if the stimuli appear to form a coherent object; (3)
no synchronization occurs if the stimuli appear to be unrelated. These intriguing observations are consistent with
the temporal correlation theory [14], which states that in
perceiving a coherent object the brain links various feature
detecting neurons via temporal correlation among the ring activities of these neurons.
Since the discovery of coherent oscillations in the visual
cortex and other brain areas, neural oscillations and synchronization of oscillator networks have been extensively
studied. Most of the early models are based on sinusoidal
or harmonic oscillators and rely on all-to-all connectivity to
reach synchronization across the network. In fact, according to the Mermin and Wagner theorem [15] in statistical
physics, no synchrony exists in one- or two-dimensional
locally coupled isotropic Heisenberg oscillators, which are
similar to harmonic oscillators. However, all-to-all connectivity leads to indiscriminate synchrony because the network is dimensionless and loses critical information about
topology. Thus, such networks are very limited in addressing perceptual organization and scene analysis the main
motivations behind computational studies of oscillatory
networks that appear to require topological relations.
Somers and Kopell [16] and Wang [17] rst realized
that there are qualitative differences between sinusoidal
and non-sinusoidal oscillators in achieving emergent syn-

When analyzing synchronization properties of a pair of

relaxation oscillators, Somers and Kopell [16] introduced
the notion of fast threshold modulation. Their mechanism
works for general relaxation oscillators, including those described in the previous section. Consider a pair of identical
relaxation oscillators excitatorily coupled in a way mimicking chemical synapses. The coupling is between the fast
variables of the two oscillators, and can be viewed as binary,
resulting in the so-called Heaviside coupling. The two oscillators are uncoupled unless one of them is in the active
phase, and in this case the effect of the excitatory coupling
is to raise the cubic of the other oscillator by a xed amount.
Let us explain the mechanism of fast threshold modulation using the Terman-Wang oscillator as an example. The
two oscillators are denoted by o1 = (x1 , y1 ) and o2 = (x2 , y2 ),
which are initially in the silent phase and close to each
other with o1 leading the way as illustrated in Fig. 4. Figure 4 shows the solution of the oscillator system in the
singular limit 0. The singular solution consists of several pieces. The rst piece is when both oscillators move
along LB of the uncoupled cubic, denoted as C. This piece
lasts until o1 reaches the left knee of C, LK, at t = t1 . The
second piece begins when o1 jumps up to RB, and the excitatory coupling from o1 to o2 raises the cubic for o2 from C
to CE as shown in the gure. Let LKE and RKE denote the
left and right knees of CE . If |y1 y2 | is relatively small,
then o2 lies below LKE and jumps up. Since these interactions take place in fast time, the oscillators are effectively
synchronized in jumping up. As a result the cubic for o1
is raised to CE as well. The third piece is when both oscillators lie on RB and evolve in slow time. Note that the
ordering in which the two oscillators track along RB is reversed and now o2 leads the way. The third piece lasts until
o2 reaches RKE at t = t2 . The fourth piece starts when o2
jumps down to LB. With o2 jumping down, the cubic for o1
is lowered to C. At this time, if o1 lies above RK, as shown
in Fig. 4, o1 jumps down as well and both oscillators are
now in the silent phase. Once both oscillators are on LB,
the above analysis repeats.
Based on the fast threshold modulation mechanism,
Somers and Kopell further proved a theorem that the synchronous solution in the oscillator pair has a domain of attraction in which the approach to synchrony has a geometric (or exponential) rate [16]. The Somers-Kopell theorem
is based on comparing the evolution rates of the slow variable right before and after a jump, which are determined
by the vertical distance of an oscillator to they nullcline
(see Fig. 4).
A Network of Locally Coupled Oscillators
In the same paper Somers and Kopell suspected that their
analysis extends to a network of relaxation oscillators, and

Relaxation Oscillators and Networks

Figure 5. Architecture of a two dimensional LEGION network

with nearest neighbor coupling. The global inhibitor is indicated
by the black circle, and it receives excitation from every oscillator
of the 2-D grid and feeds back inhibition to every oscillator.
Figure 4. Fast threshold modulation. C and CE indicate the uncoupled and the excited cubic, respectively. The two oscillators o1
and o2 start at time 0. When o1 jumps up at t = t1 , the cubic corresponding to o2 is raised from C to CE . This allows o2 to jump up
as well. When o2 jumps down at t = t2 , the cubic corresponding to
o1 is lowered from CE to C. This allows o1 to jump down as well.
In the gure, LK and RK indicate the left knee and the right knee
of C, respectively. LKE and RKE indicate the left knee and right
knee of CE , respectively.

performed numerical simulations with one-dimensional

rings to support their suggestion. In a subsequent study, by
extending Somers and Kopell analysis, Terman and Wang
proved a theorem that for an arbitrary network of locally
coupled relaxation oscillators there is a domain of attraction in which the entire network synchronizes at an exponential rate [11].
In their analysis, Terman and Wang employed the time
metric to describe the distance between oscillators. When
oscillators evolve either in the silent phase or the active
phase, their distances in y in the Euclidean metric change;
however, their distances in the time metric remain constant. On the other hand, when oscillators jump at the
same time (in slow time), their y distances remain unchanged while their time distances change. Terman and
Wang also introduced the condition that the sigmoid for
the y nullcline (again consider the Terman-Wang oscillator) is very close to a step function [11], which is the case
when in Eq. (5) is chosen to be very small. This condition
implies that in the situation with multiple cubics the rate
of evolution of a slow variable does not depend on which
cubic it tracks along.
Recently, Campbell et al. [19] showed that the denition
of a canonical relaxation oscillator can lead to qualitatively
different kinds of oscillation through parameter choices.
In addition, their numerical investigation indicates that a
network of relaxation oscillators in the relaxation regime
(the normal case) approach synchrony with an average
time that is a power relation of the network size with a
small exponent. On the other hand, relaxation oscillators in
the spiking regime, where the active phase is much shorter
than the silent phase, approach synchrony with an average
time that is a logarithmic relation of the network size, although for the same network synchrony in the relaxation
regime is typically faster than that in the spiking relation.

LEGION Networks: Selective Gating

A natural and special form of the temporal correlation theory is oscillatory correlation [20], whereby each object is
represented by synchronization of the oscillator group corresponding to the object and different objects in a scene are
represented by different oscillator groups which are desynchronized from each other. There are two fundamental aspects in the oscillatory correlation theory: synchronization
and desynchronization. Extending their results on synchronizing locally coupled relaxation oscillators, Terman
and Wang used a global inhibitory mechanism to achieve
desynchronization [11]. The resulting network is called LEGION, standing for Locally Excitatory Globally Inhibitory
Oscillator Networks [20].
The original description of LEGION is based on TermanWang oscillators, and basic mechanisms extend to other
relaxation oscillator models. Each oscillator i is dened as

xi = f (xi ) yi + Ii + Si +

yi = [g(xi ) yi ]

(6)
(6)

Here f( ) and g(x) are as given in Eq. (5). The parameter

denotes the amplitude of Gaussian noise; to reduce the
chance of self-generating oscillations the mean of noise is
set to . In addition to test robustness, noise plays the
role of assisting desynchronization. The term Si denotes
the overall input from other oscillators in the network:
Si =

Wik H(xk x ) Wz H(z z )

(7)

k N(i)

where Wik is the dynamic connection weight from k to i, and

N(i) is the set of the adjacent oscillators that connect to i.
In a two-dimensional (2-D) LEGION network, N(i) in the
simplest case contains four immediate neighbors except on
boundaries where no wrap-around is used, thus forming a
2-D grid. This architecture is shown in Fig. 5. H stands for
the Heaviside function, dened as H() = 1 and H() = 0 if
< 0. x is a threshold above which an oscillator can affect
its neighbors. Wz is the weight of inhibition from the global
inhibitor z, whose activity is dened as

z = ( z)

(8)

where is a parameter. The quantity = 1 if xi z for at

least one oscillator i, and = 0 otherwise. Hence z (see
also Eq. (7)) represents a threshold.

Relaxation Oscillators and Networks

Figure 6. Selective gating with two oscillators coupled through a

global inhibitor. C and CZ indicate the uncoupled and the inhibited
cubic, respectively. The two oscillators o1 and o2 start at time 0.
When o1 jumps up at t = t1 the cubic corresponding to both o1 and
o2 is lowered from C to CZ . This prevents o2 from jumping up until
o1 jumps down at t = t2 and releases o2 from the inhibition. LK and
RK indicate the left knee and the right knee of C, respectively. PZ
denotes a stable xed point at an intersection point between CZ
and the sigmoid.

The dynamic weights Wik s are formed on the basis of

permanent weights Tik s according to the mechanism of dynamic normalization [21] [22], which ensures that each oscillator has equal overall weights of dynamic connections,
WT , from its neighborhood. According to Ref. [11], weight
normalization is not a necessary condition for LEGION to
work, but it improves the quality of synchronization. Moreover, based on external input Wik can be determined at the
start of simulation.
To illustrate how desynchronization between blocks of
oscillators is achieved in a LEGION network, let us consider an example with two oscillators that are coupled only
through the global inhibitor. Each oscillator is meant to correspond to an oscillator block that represents a pattern in a
scene. The same notations introduced earlier are used here.
Again, assume that both oscillators are in the silent phase
and close to each other with y1 < y2 , as shown in Fig. 6. The
singular solution of the system consists of several pieces,
where the rst one lasts until o1 reaches LK at t = t1 . When
both oscillators are on LB, z = 0. The second piece starts
when o1 jumps up, and when o1 crosses z , switches from
0 to 1, and z 1 on the fast time scale. When z crosses z ,
the cubic corresponding to both o1 and o2 lowers from C to
CZ , the inhibited cubic. The third piece is when o1 is the
active phase, while o2 is in the silent phase. The parameters are chosen so that CZ intersects with the sigmoid at
a stable xed point PZ along LB as shown in Fig. 6. This
guarantees that o2 PZ , and o2 cannot jump up as long as
o1 is on RB, which lasts until o1 reach the right knee of CZ
at t = t2 . The fourth piece starts when o1 jumps down to
LB. When o1 crosses z , z 0 in fast time. When z crosses
z , the cubic corresponding to both o1 and o2 returns to C.
There are now two cases to consider. If o2 lies below LK, as
shown in Fig. 6, then o2 jumps up immediately. Otherwise
both o1 and o2 lie on LB, with o2 leading the way. This new
silent phase terminates when o2 reaches LK and jumps up.

The above analysis demonstrates the role of inhibition

in desynchronizing the two oscillators: o1 and o2 are never
in the active phase simultaneously. In general, LEGION
exhibits a mechanism of selective gating, whereby an oscillator, say oi jumping to its active phase quickly activates the global inhibitor, which selectively prevents the
oscillators representing different blocks from jumping up,
without affecting oi s ability in recruiting the oscillators
of the same block because of local excitation. With the selective gating mechanism, Terman and Wang proved the
following theorem. For a LEGION network there is a domain of parameters and initial conditions in which the network achieves both synchronization within blocks of oscillators and desynchronization between different blocks in
no greater than N cycles of oscillations, where N is the number of patterns in an input scene. In other words, both synchronization and desynchronization are achieved rapidly.
The following simulation illustrates the process of synchronization and desynchronization in LEGION [20]. Four
patterns two Os, one H, and one I, forming the word
OHIO are simultaneously presented to a 20 20 LEGION network as shown in Figure 7(a). Each pattern is
a connected region, but no two patterns are connected to
each other. The oscillators under stimulation become oscillatory, while those without stimulation remain excitable.
The parameter is set to represent 10% noise compared to
the external input. The phases of all the oscillators on the
grid are randomly initialized. Figs. 7(b)7(f) show the instantaneous activity (snapshot) of the network at various
stages of dynamic evolution. Fig. 7(b) shows a snapshot of
the network at the beginning of the simulation, displaying the random initial conditions. Fig. 7(c) shows a snapshot shortly afterwards. One can clearly see the effect of
synchronization and desynchronization: all the oscillators
corresponding to the left O are entrained and have large
activity; at the same time, the oscillators stimulated by the
other three patterns have very small activity. Thus the left
O is segmented from the rest of the input. Figures 7(d)(f)
show subsequent snapshots of the network, where different patterns reach the active phase and segment from the
rest. This successive popout of the objects continues in an
approximately periodic fashion as long as the input stays
on. To provide a complete picture of dynamic evolution, Fig.
7(g) shows the temporal evolution of every oscillator. Synchronization within each object and desynchronization between them are clearly shown in three oscillation periods,
which is consistent with the theorem proven in [11].

Time Delay Networks

Time delays in signal transmission are inevitable in both
the brain and physical systems. In local cortical circuits,
for instance, the speed of nerve conduction is less than 1
mm/ms such that connected neurons 1 mm apart have a
time delay of more than 4% of the period of oscillation assuming 40 Hz oscillations. Since small delays may completely alter the dynamics of differential equations, it is
important to understand how time delays change the behavior, particularly synchronization, of relaxation oscillator networks.

Relaxation Oscillators and Networks

Figure 7. Synchronization and desynchronization

in LEGION. (a) A scene composed of four patterns
which were presented (mapped) to a 20 20 LEGION network. (b) A snapshot of the activities of the
oscillator grid at the beginning of dynamic evolution.
The diameter of each black circle represents the x
activity of the corresponding oscillator. (c) A snapshot taken shortly after the beginning. (d) Another
snapshot taken shortly after (c). (e) Another snapshot taken shortly after (d). (f) Another snapshot
taken shortly after (e). (g) The upper four traces show
the combined temporal activities of the oscillator
blocks representing the four patterns, respectively,
and the bottom trace shows the temporal activity of
the global inhibitor. The ordinate indicates the normalized x activity of an oscillator. Since the oscillators receiving no external input are excitable during
the entire simulation process, they are excluded from
the display. The activity of the oscillators stimulated
by each object is combined into a single trace in the
gure. The differential equations were solved using
a fourth-order Runge-Kutta method (from [20]).

Campbell and Wang [23] studied locally coupled relaxation oscillators with time delays. They revealed the phenomenon of loose synchrony in such networks. Loose synchrony in networks with nearest neighbor coupling is dened as follows. Coupled oscillators approach each other so
that their time difference is less than or equal to the time
delay between them. They analyzed a pair of oscillators
in the singular limit 0, and gave a precise diagram in
parameter space that indicates regions of distinct dynamical behavior, including loosely synchronous and antiphase
solutions. The diagram points out that loose synchrony exists for a wide range of time delays and initial conditions.
Numerical simulations show that the singular solutions
derived by them extend to the case 0 <  1. Furthermore,
through extensive simulations they conclude that their parameter diagram for a pair of oscillators says much about
networks of locally coupled relaxation oscillators. In particular, the phenomenon of loose synchrony exists in a similar
way. Figure 8 demonstrates loosely synchronous behavior
in a chain of 50 oscillators with a time delay that is 3%
of the oscillation period between adjacent oscillators. The
phase relations between the oscillators in the chain become

stabilized by the third cycle.

Two other results regarding relaxation oscillator networks with time delays are worth mentioning. First, Campbell and Wang [23] identied a range of initial conditions in
which the maximum time delays between any two oscillators in a locally coupled network can be contained. Second,
they found that in LEGION networks with time delay coupling between oscillators, desynchronous solutions for different oscillator blocks are maintained. Thus, the introduction of time delays does not appear to impact the behavior
of LEGION in terms of synchrony and desynchrony.
Subsequently, Fox et al. [24] proposed a method to
achieve zero phase-lag synchrony in locally coupled relaxation oscillators with coupling delays. They observed that
different speeds of motion along different nullclines could
result in rapid synchronization. Their analysis in particular shows how to choose appropriate y nullclines to induce
different speeds of motion, which in turn lead to zero-lag
synchrony. Numerical simulations demonstrate that their
analytical results obtained in the case of two coupled oscillators extend to 1-D and 2-D networks. More recently,
Sen and Rand [25] numerically investigated the dynam-

Relaxation Oscillators and Networks

ics of a pair of van der Pol oscillators coupled with time

delays. Their comprehensive analysis revealed regions in
the 2-D plane of coupling strength and time delay where
stable zero-lag synchrony occurs, as well as regions where
antiphase solutions exist. Interestingly, there is an overlap between synchronous and antiphase solutions; in other
words, the coupling and delay parameters can be chosen
so that the two modes of behavior are both stable, a phenomenon of bi-rhythmicity.
APPLICATIONS TO SCENE ANALYSIS
A natural scene generally contains multiple objects, each of
which can be viewed as a group of similar sensory features.
A major motivation behind studies on oscillatory correlation is scene analysis, or the segmentation of a scene into a
set of coherent objects. Scene segmentation, or perceptual
organization, plays a critical role in the understanding of
natural scenes. Although humans perform it with apparent
ease, the general problem of scene segmentation remains
unsolved in sensory and perceptual information processing.
Oscillatory correlation provides an elegant and unique
way to represent results of segmentation. As illustrated in
Fig. 7, segmentation is performed in time; after segmentation, each segment pops out at a distinct time from the
network and different segments alternate in time. On the
basis of synchronization and desynchronization properties
in relaxation oscillator networks, substantial progress has
been made to address the scene segmentation problem; see
Wang [26] for a comprehensive review.
Image Segmentation
Wang and Terman [22] studied LEGION for segmenting
real images. In order to perform effective segmentation,
LEGION needs to be extended to handle images with noisy
regions. Without such extension, LEGION would treat each
region, no matter how small it is, as a separate segment,
resulting in many fragments. A large number of fragments
degrade segmentation results, and a more serious problem is that it is difcult for LEGION to produce more than
several (5 to 10) segments. In general, with a xed set of
parameters, LEGION can segment only a limited number
of patterns [11]. This number depends on the ratio of the
times that a single oscillator spends in the silent and active phases; see, for example, Figs. 3 and 7. This limit is
called the segmentation capacity of LEGION [22]. Noisy
fragments therefore compete with major image regions for
becoming segments, and the major segments may not be
extracted as a result. To address this problem of fragmentation, they introduced the notion of lateral potential for
each oscillator, which allows the network to distinguish between major blocks and noisy fragments. The basic idea is
that a major block must contain at least one oscillator, denoted as a leader, which lies in the center area of a large homogeneous image region. Such an oscillator receives large
lateral excitation from its neighborhood, and thus its lateral potential is charged high. A noisy fragment does not
contain such an oscillator.

More specically, a new variable pi denoting the lateral

potential for each oscillator i is introduced into the denition of the oscillator (cf. (6)). pi 1 if i frequently receives
a high weighted sum from its neighborhood, signifying that
i is a leader, and the value of pi determines whether or not
the oscillator i is a leader. After an initial time period, only
leaders can jump up without lateral excitation from other
oscillators. When a leader jumps up, it spreads its activity to other oscillators within its own block, so they can
also jump up. Oscillators not in this block are prevented
from jumping up because of the global inhibitor. Without
a leader, the oscillators corresponding to noisy fragments
cannot jump up beyond the initial period. The collection of
all noisy regions is called the background, which is generally discontiguous.
Wang and Terman obtained a number of rigorous results concerning the extended version of LEGION [22]. The
main analytical result states that the oscillators with low
lateral potentials will become excitable after a beginning
period, and the asymptotic behavior of each oscillator belonging to a major region is precisely the same as the network obtained by simply removing all noisy regions. Given
the Terman-Wang theorem on original LEGION, this implies that after a number of cycles a block of oscillators corresponding to a major region synchronizes, while any two
blocks corresponding to different major regions desynchronize. Also, the number of periods required for segmentation
is no greater than the number of major regions plus one.
For gray-level images, each oscillator corresponds to a
pixel. In a simple scheme for setting up lateral connections,
two neighboring oscillators are connected with a weight
proportional to corresponding pixel similarity. To illustrate
typical segmentation results, Fig. 9(a) displays a gray-level
aerial image to be segmented. To speed up simulation with
a large number of oscillators needed for processing real
images, Wang and Terman abstracted an algorithm that
follows LEGION dynamics [22]. Fig. 9(b) shows the result of segmentation by the algorithm. The entire image
is segmented into 23 regions, each of which corresponds to
a different intensity level in the gure, which indicates the
phases of oscillators. In the simulation, different segments
rapidly popped out from the image, as similarly shown in
Fig. 7. As can be seen from Fig. 9(b), most of the major
regions were segmented, including the central lake, major
parkways, and various elds. The black scattered regions
in the gure represent the background that remains inactive. Due to the use of lateral potentials, all these tiny
regions stay in the background.
Auditory Scene Analysis
A listener in an auditory environment is generally exposed
to acoustic energy from different sources. In order to understand the auditory environment, the listener must rst
disentangle the acoustic wave reaching the ears. This process is referred to as auditory scene analysis. According to
Bregman [27], auditory scene analysis takes place in two
stages. In the rst stage, the acoustic mixture reaching the
ears is decomposed into a collection of sensory elements (or
segments). In the second stage, segments that likely arise
from the same source are grouped to form a stream that is

Relaxation Oscillators and Networks

Figure 8. Loose synchrony in a chain of 50 relaxation oscillators (from [23]). This network achieves
loose synchrony and stability by the third period of
oscillation.

Figure 9. Image segmentation (from [22]). (a) A

gray-level image consisting of 160 160 pixels. (b)
Result of segmenting the image in (a). Each segment
is indicated by a distinct gray level. The system produces 23 segments plus a background, which is indicated by the black scattered regions in the gure.

Figure 10. Speech segregation (from [30]). (a) Peripheral responses to a mixture of voiced utterance and telephone ringing. The 2-D response is produced by 128 auditory lters with center
frequencies ranging from 80 Hz to 5 kHz, over 150 time frames. (b) Segregated speech that is indicated by white pixels representing active oscillators at a time. (c) Segregated background that is
indicated by white pixels representing active oscillators at a different time.

Relaxation Oscillators and Networks

a perceptual representation of an auditory event.

Auditory segregation was rst studied from the oscillatory correlation perspective by von der Malsburg and
Schneider [14]. They constructed a fully connected oscillator network, each oscillator representing a specic auditory feature. Additionally, there is a global inhibitory oscillator introduced to segregate oscillator groups. With a
mechanism of rapid modulation of connection strengths,
they simulated segregation based on onset synchrony, i.e.,
oscillators simultaneously triggered synchronize with each
other, and these oscillators desynchronize with those representing another stream presented at a different time.
However, due to global connectivity that is unable to encode topological relations, their model cannot simulate the
basic phenomenon of stream segregation.
By extending LEGION to the auditory domain, Wang
proposed an oscillator network for addressing stream segregation [28]. The basic architecture is a 2-D LEGION network, where one dimension represents time and another
represents frequency. This network, plus systematic delay
lines, can group auditory features into a stream by phase
synchronization and segregate different streams by desynchronization. The network demonstrates a set of psychological phenomena regarding auditory scene analysis, including dependency on frequency proximity and temporal proximity, sequential capturing, and competition among different perceptual organizations [27]. Brown and Wang [29]
used an array of relaxation oscillators for modeling the perceptual segregation of double vowels. It is well documented
that the ability of listeners to identify two simultaneously
presented vowels is improved by introducing a difference
in fundamental frequency (F0) between the vowels. Prior
to the oscillator array, an auditory mixture is processed by
an auditory lterbank, which decompose an acoustic signal into a number of frequency channels. Each oscillator
in the array receives an excitatory input from its corresponding frequency channel. In addition, each oscillator
sends excitation to a global inhibitor which in turn feeds
back inhibition. The global inhibitor ensures that weakly
correlated groups of oscillators desynchronize to form different streams. Simulations on a vowel set used in psychophysical studies conrm that the results produced by
their oscillator array qualitatively match the performance
of human listeners; in particular vowel identication performance increases with increasing difference in F0.
Subsequently, Wang and Brown [30] studied a more difcult problem, speech segregation, on the basis of oscillatory correlation. Their model embodies Bregmans twostage conceptual model by introducing a two-layer network
of relaxation oscillators. The rst layer is a LEGION network with time and frequency axes that segments an auditory input into a collection of contiguous time-frequency
regions. This segmentation is based on cross-channel correlation between adjacent frequency channels and temporal
continuity. The second layer, which is a laterally connected
network, then groups auditory segments produced in the
rst layer on the basis of common periodicity. More specifically, dominant F0 detected within a time frame is used
to divide all frequency channels into those that are consistent with F0 and the rest. As a result, the second layer
segregates the segments into a foreground stream and the

background. Figure 10 shows an example of segregating a

mixture of a voiced utterance and telephone ringing. The
input mixture after peripheral analysis is displayed in Fig.
10(a). The segregated speech stream and the background
are shown in Figs. 10(b) and 10(c), respectively, where a
segment corresponds to a connected region.
CONCLUDING REMARKS
Relaxation oscillations are characterized by two time
scales, and exhibit qualitatively different behaviors than
sinusoidal or harmonic oscillations. This distinction is particularly prominent in synchronization and desynchronization in networks of relaxation oscillators. The unique properties in relaxation oscillators have led to new and promising applications to neural computation, including scene
analysis. It should be noted that networks of relaxation oscillations often lead to very complex behaviors other than
synchronous and antiphase solutions. Even with identical
oscillators and nearest neighbor coupling, traveling waves
and other complex spatiotemporal patterns can occur [31].
Relaxation oscillations with a singular parameter lend
themselves to analysis by singular perturbation theory
[32]. Singular perturbation theory in turn yields a geometric approach to analyzing relaxation oscillation systems,
as illustrated in Figs. 4 and 6. Also based on singular solutions, Linsay and Wang [33] proposed a fast method to
numerically integrate relaxation oscillator networks. Their
technique, called the singular limit method, is derived in
the singular limit 0. A numerical algorithm is given for
the LEGION network, and it produces large speedup compared to commonly used integration methods such as the
Runge-Kutta method. The singular limit method makes it
possible to simulate large-scale networks of relaxation oscillators.
Computation using relaxation oscillator networks is inherently parallel, where each single oscillator operates in
parallel with all the other oscillators. This feature, plus
continuous-time dynamics makes oscillator networks attractive for direct hardware implementation. Using CMOS
technology, for example, Cosp and Madrenas [34] fabricated a VLSI chip for a 16 16 LEGION network and used
the chip for a number of segmentation tasks. With its dynamical and biological foundations, oscillatory correlation
promise to offer a general computational framework.
ACKNOWLEDGMENTS
The preparation for this article was supported in part by
an AFOSR grant (FA9550-04-1-0117) and an NSF grant
(IIS-0534707).
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DELIANG WANG
Department of Computer
Science & Engineering
Center for Cognitive Science,
The Ohio State University,
Columbus, OH, 43210-1277

SAMPLE-AND-HOLD CIRCUITS

651

SAMPLE-AND-HOLD CIRCUITS
Sample-and-hold circuits were first introduced as a front end
for analog-to-digital data converters. Processing electrical information in a discrete or digital fashion appears to be more
reliable, repeatable, and accurate than in the analog domain.
However, converting analog signals to digital ones can be often disrupted if the input signal changes during the conversion cycle. The exact moment in time when the input is
sensed and compared with a reference can be different across
the data converter, resulting in aperture errors. Consequently, it appears useful to memorize the input signal and
hold it constant for the comparators that perform the conversion to the digital domain. Among different data-converter architectures, only the so-called flash ones can perform without requiring a sample-and-hold circuit although its usage is
usually beneficial even in this case.
Another application for sample-and-hold circuits is as a
back end for digital-to-analog data converters. The analog
voltage generated by these converters is subject to glitches
due to the transitions occurring between consecutive digital
input codes. A sample-and-hold circuit can be used to sample
the analog voltage between the glitches, effectively smoothing
the output waveform between two held output-voltage levels.
Then, a low-pass filter following the sample-and-hold circuit
is able to restore the continuous-time analog waveform much
more efficiently than in the presence of glitches.
Switched-capacitor or switched-current signal processing
inherently requires the input signal to be sampled and held
for subsequent operations. There is a widespread usage of
this type of processing; hence a variety of applications employ
some sort of sample-and-hold circuit as a front end. It can be
inferred that any sampled-data system requires a sampleand-hold operation at some point.
When used inside a larger system, the performance of a
sample-and-hold circuit could limit the overall performance.
Speed, accuracy, and power consumption are a few criteria to
be observed during the design process or simply from a users
perspective. This article is intended to describe and present
different implementations of sample-and-hold circuits as well
as associated nonidealities. The following section includes a
list of errors that make a real-life implementation different
from the ideal sample-and-hold circuit model. The third section describes different implementations of these circuits
organized into metal oxide semiconductor (MOS) transistorbased open-loop architectures, MOS-transistor-based closedloop architectures, bipolar-device-based architectures, and
current-mode architectures. The last section of the article outlines some conclusions and provides a brief overview regarding modern applications of sample-and-hold circuits.

SAMPLE-AND-HOLD PERFORMANCE SPECIFICATIONS

A simplified model of a sample-and-hold circuit is a switch
connected between the input and one terminal of a holding
capacitor. The other terminal of the capacitor is tied to a reference voltage (ground), and the output of the sample-andhold is the voltage across the capacitor. The switch is controlled by a digital signal that determines the sampling time
and the hold duration. Ideally, the output voltage tracks the
input exactly when the switch is closed (track or sample
mode) and stores a sample of the input voltage when the
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

652

SAMPLE-AND-HOLD CIRCUITS

Sampling moment

Error band

Input

Output

Error band

Settling time

Pedestal
error
Output

Offset

Settling time

Figure 1. Offset and settling time during sample mode. The output
of a sample-and-hold circuit settles to a step at the input.

Figure 3. Settling time and pedestal voltage during the sample-tohold transition.

switch opens (hold mode). In reality the behavior of the circuit

deviates from this ideal model affecting the performance. The
following subsections describe the specifications used to characterize sample-and-hold circuits.

specification discussed in the preceding subsection. This nonideal behavior is shown in Fig. 3. Another nonideal effect is
also presented in Fig. 3 and is called the pedestal error. This
error appears as an offset in the output signal and is due
to charge injected from the sampling switch, which could be
dependent on the input signal, implying nonlinearity.
Aperture time is another important specification and is defined as the amount of time it takes for the sampling switch
to open. This is attributed to the finite slope of the clock and
a gradual transition of the sampling switch from a low-impedance (closed) to a high-impedance (opened) state. The signal
stored at the output is a function of the aperture delay ta, the
analog delay tda of the signal through the sample-and-hold circuit, and the digital delay tdd of the clock signal that turns off
the switch. It can be ultimately characterized as shown in
Fig. 4 by an effective aperture time teff . The analog delay is
caused by the frequency response of the sample-and-hold circuit, and the digital delay is produced by any logic in the path
of the external clock to the switch. The aperture jitter is the
variation in the hold signal delay. In some applications, such
as analog-to-digital data conversion, a constant delay in the
sampling time is not important. However, aperture jitter
could be extremely damaging, adding significant noise to the
output signal and effectively lowering the resolution of the
system.

Sample-Mode Specifications
The operation during the sample mode is similar to a voltage
or current amplifier. Thus any specifications used to characterize an amplifier can be used to characterize the sampleand-hold circuit in sample mode. Some of the key specifications in this mode of operation are offset, settling time, gain
error, and nonlinearity. The offset is defined as the difference
between the input and the output with no signal applied at
the input. This is shown in Fig. 1. The time it takes for the
output to settle within a certain error band around its final
value with a step applied at the input is called the settling
time. The size of the step is usually full scale as shown in Fig.
1 unless specified otherwise. Gain error and nonlinearity are
both steady-state errors that describe the deviation of the
magnitude transfer characteristic from a straight line with a
slope of 1. As represented in Fig. 2, the gain error appears as
the deviation of the slope of line P1P2 from 45 and can be
expressed as Gerror 1 tan . One definition of nonlinearity
is the maximum deviation of the transfer characteristic from
line P1P2. This is also shown in Fig. 2. Other sample-mode
specifications include bandwidth, slew rate, distortion, and
noise, which also characterize a general amplifier, are defined
in a similar fashion.
Sample- to Hold-Mode Specifications
The switching from sample to hold mode is accompanied by
transients that appear in the output. The time it takes for
these transients to settle within a given error bound is called
the settling time, similar to the corresponding sample-mode

Hold-Mode Specifications
Ideally, the holding capacitor should be completely isolated
from any interference during the hold mode and the output
signal should remain constant. In a real-life implementation
there is always a small current flowing across the holding ca-

Input

Output

End point = P2

Nonlinearity

Start point = P1

Gain error = 1 tan

Input

Figure 2. Gain error and nonlinearity. A sample-and-hold circuit exhibits gain error as deviation of line P1P2 from a 45 slope, and nonlinearity as curvature in the inputoutput characteristic.

tda
Internal hold
clock
External hold
clock

Output

ta
tdd

teff
Figure 4. Time delays that determine the effective aperture time
during the sample-to-hold transition: ta, aperture delay; tdd, digital
delay; tda, analog delay; teff , effective aperture time.

SAMPLE-AND-HOLD CIRCUITS

Open-Loop Sample-and-Hold Circuits

Sampling
moment
Input
Droop

653

Feedthrough
(peak-to-peak)

Output
Figure 5. Droop and feed-through errors during hold mode.

pacitor during the hold mode. This nonideal effect produces

droop in the output signal as shown in Fig. 5. As an example,
in an analog-to-digital data converter the droop should not
exceed one-half of the least-significant bit value during the
conversion cycle. Generally, the droop current could be a bipolar base current or simply junction leakage. Another specification during the hold mode is the feedthrough from the input
signal. This occurs through parasitic capacitance between the
input and the output nodes of a sample-and-hold circuit, although it can occur between other nodes in the system and
the output. Figure 5 also presents this effect. Again, in reference to the data-converter example, the feedthrough peak-topeak amplitude should not exceed one least significant bit of
the converter.
There are a few other factors that influence the performance during the hold mode. Nonidealities in the holding capacitor can cause dielectric absorption. Consequently, the capacitor exhibits a memorylike behavior, corrupting the newly
stored sample in the direction of the previous sample. Electrical noise is also a factor, and the value of the capacitor plays
an important role since the kT/C term (k is the Boltzmann
constant, T the absolute temperature in kelvin, and C the
holding capacitor value) is usually the main contributor.
Hold- to Sample-Mode Specifications
When switching from the hold to sample mode, there is a delay between the sampling edge of the clock and the moment
the output settles to the steady state when it tracks the input.
This time is known as the acquisition time and is also determined by an error band. Since the input can change significantly while the circuit is in hold mode, the acquisition time
is usually specified for a full-scale change in the input unless
mentioned otherwise.
IMPLEMENTATION OF SAMPLE-AND-HOLD CIRCUITS
If one starts with the basic ideal model for a sample-and-hold
circuit, there are various ways to implement a switch and a
capacitor in either discrete or monolithic forms. The interface
between this model and the input signal or adjacent system
blocks implies the usage of additional circuitry. There is also
added complexity from dealing with different circuit nonidealities, an increase in operating speed, or a decrease in power
consumption. The following subsections embrace this gradual
approach from a basic model to a more complex structure,
which provides an implementation that is close to real life. A
variety of topologies and implementations is presented including open- and closed-loop, bipolar, and MOS-based, as well as
current-mode circuits.

The simplest voltage-mode sample-and-hold circuit requires

only two elements: a switch and a capacitor, as shown in Fig.
6 (13). The switch is controlled by a clock signal that is
turned on and off each sample period. When the switch is on,
the input voltage appears on the capacitor, and the circuit is
actually in track mode. When the switch is turned off, the
signal voltage at that instance is sampled on the capacitor,
which holds the voltage constant until the next track phase.
Although this ideally implements the desired sample-andhold function using only two elements, the difficulty in realizing an ideal switch severely limits the performance of such a
design. Real switches are implemented using MOS or bipolar
transistors or diode bridges, each of which has its own idiosyncrasies. This subsection will primarily focus on the use of
MOS switches, while circuits utilizing bipolar transistors or
diodes will be discussed in the following subsection.
A MOS transistor deviates from an ideal switch in several
ways, the most obvious of which is in terms of on-resistance.
When the MOS switch is turned on, it typically will have a
low drain-to-source voltage (VDS) and a high gate-to-source
voltage (VGS) [n-type MOS assuming (NMOS), opposite polarity for p-type MOS (PMOS)], causing it to operate in the triode or nonsaturation region, where the drain-to-source current (IDS) is given by (4)
IDS = K

W
2
[(VGS VT )VDS 12 VDS
]
L

(1)

which, when VDS (VGS VT), can be approximated as

IDS K

W
(V VT )VDS
L GS

(2)

where VT is the threshold voltage. The large-signal on-resistance of the switch is then given by the voltage across the
device, VDS, divided by the current through it, IDS, yielding


1
W
Rswitch K
(VGS VT )
L

(3)

The switch on-resistance is clearly nonzero, meaning that the

circuit will exhibit some transient exponential settling when
the switch first turns on and then a low-pass filtering response during steady-state operation while it remains on (for
input signal frequencies greater than dc). Clearly the switch
resistance must be designed properly to provide sufficient levels of settling and bandwidth for the speed and precision
needed.

In

Out

In
Out

Figure 6. Simple sample-and-hold circuit with example signals

shown. When is high, the output tracks the input and when is
low, the output is held.

654

SAMPLE-AND-HOLD CIRCUITS

Not only is the resistance of the switch nonzero and dependent on the semiconductor process parameter K and device
size (W and L), but it also varies with the voltage on the
source of the transistor, which will be a function of the input
voltage. If, as is done in the simplest cases, the gate of the
transistor is tied to a constant-supply-voltage level while the
switch is on, then the switch resistance varies with the input
signal, causing nonlinear dynamic circuit operation. If an
NMOS switch is used, then its on-resistance will rise toward
infinity as the input voltage approaches VDD VT,n, limiting
the input range to voltages well below this. Similarly, a
PMOS switch will limit the input to voltages well above
VSS VT,p. A wider input range is obtained by using a complementary MOS (CMOS) switch, consisting of an NMOS and
a PMOS switch in parallel, with the PMOS device driven by
the inverted version of the sampling signal . This configuration enables sampling of an input range extending from VSS
to VDD, although on-resistance of the switch will still vary significantly over the entire range, giving rise to nonlinear dynamic performance. This effect can be avoided by driving the
switch gates with a bootstrapped version of the input signal
while the switches are on, such that both gates and sources
will vary similarly with respect to the input (5). This removes
the input signal dependence from the VGS term in Eq. (3),
making the on-resistance independent of the input, at least
to first order. In reality, higher-order effects will eventually
come into play to limit the linearity, but this technique is useful in gaining some performance improvement.
Another limitation of the MOS switch is charge injection
and clock feedthrough, which are sometimes used interchangeably to describe two effects that occur when the switch
is turned off. When the transistor is on, charge collects under
the gate of the transistor to form the channel from drain to
source. When the switch is turned off, this charge exits the
channel primarily to the drain and source, with the proportional split depending on speed of the clock transition and the
impedance seen by the charge in each direction (6). The part
of the charge that exits toward the sampling capacitor will
cause the capacitor voltage to drop slightly (assuming an
NMOS transistor with negative channel charge) from its immediately previous value. This would only create a constant
pedestal error in the sample-and-hold circuit output if the
packet of charge were always the same, but unfortunately
this is not the case. The channel charge is approximately
given by
Qchannel CoxWL(VGS VT )

(4)

which reveals that, if the gate of the switch is tied to a constant supply voltage while turned on, then the channel charge
will be signal dependent. In reality, this signal dependence of
the injected charge is a major source of nonlinearity in the
sample-and-hold circuit.
The second effect, often termed clock feedthrough, is caused
by the MOS overlap capacitance between the gate and source
or drain connected to the sampling capacitor. As the gate voltage is dropping from a high on-voltage to a low off-voltage, the
transistor actually shuts off when the gate is approximately a
threshold voltage above the source or drain voltage. As the
gate voltage continues to fall further, the voltage step is capacitively coupled onto the sampling capacitor through the
MOS overlap capacitance, causing the voltage on the sampling capacitor to change. Both of these charge effects can be

In

2W

Out
W

Figure 7. Simple sample-and-hold circuit with dummy-switch compensation for reducing the charge injection. The dummy device is half
the size (W/L vs. 2W/L) of the series switch device.

reduced by driving the gate with a bootstrapped version of the

input signal, which makes the effects independent of signal to
first order, just as in the case of switch on-resistance. The use
of a full CMOS switch rather than only a single NMOS or a
single PMOS device also gives a very rough cancellation of
these effects. The NMOS device will inject negative channel
charge onto the sampling capacitor, while the PMOS switch
will inject positive channel charge. Similarly, the charge coupled through the overlap capacitances will also be in opposing
directions. Unfortunately, these cancellations do not hold as
the input is varied over its input range and so give little
benefit.
Dummy-switch cancellation is another technique that can
be used, though generally with limited effectiveness, to reduce charge injection and clock feedthrough. As shown in Fig.
7, a dummy-switch device with half the gate area of the main
switch is placed on the capacitor side of the sampling switch
and is clocked with an inverted version of the sampling signal
. Thus, during acquisition, the main switch is on and the
dummy switch is off. At the sampling instant, the dummy
switch is turned on, causing it to pull charge from the sampling capacitor to form the channel under its gate. This
charge approximately cancels that injected by the main
switch, assuming roughly half of the main switch charge was
injected toward the capacitor.
The simple sample-and-hold circuit using a MOS switch
can also experience input signal feedthrough during the hold
mode due to the MOS overlap capacitances, especially when
sampling high-speed inputs. When the circuit is in hold mode,
the MOS gate will be pulled to the low supply voltage (assuming an NMOS switch), typically by a digital gates output. The
digital gate will have a finite, nonzero resistance from its output to the low supply voltage, yielding an effective circuit
such as that shown in Fig. 8. Analysis of this circuit reveals
a nonzero transfer function from the input to the sampled
output node, causing the feedthrough. Care must be taken
during the design process to characterize the level of feedthrough that occurs and keep it sufficiently low through a
low-resistance gate drive or more elaborate design modifications.

Coverlap Coverlap
In

Out
Rdriver

Figure 8. Effective circuit of the simple sample-and-hold circuit using an NMOS switch while in hold mode. The gate is driven low by a
circuit with nonzero output resistance, such as a digital gate or clock
driver. The MOS overlap capacitances couple the input signal to the
output even with the MOS switch turned off.

SAMPLE-AND-HOLD CIRCUITS

In

Buffer

Buffer

Out

In

C
Out

Figure 9. Simple sample-and-hold circuit with input and output

buffering.

A fundamental trade-off occurs in this simple sample-andhold circuit between speed and linearity. In order for the circuit to have high bandwidth and fast settling, a large width
transistor with low on-resistance is needed. However, larger
width also means more channel charge, which then increases
the charge injection and generally reduces the circuits linearity performance. While the sampling switch must be designed
to meet the speed and settling requirements of the given application, it should not be unnecessarily overdesigned to have
excessively low on-resistance.
Yet another limitation of the design shown in Fig. 6 is its
lack of drive capability while in hold mode. If this circuit is
loaded by a resistive or switched capacitive load, then the
sampled signal voltage on the capacitor will leak off while the
sampling switch is off. This problem is easily addressed by
adding a unity-gain buffer at the output. The loading that
this sample-and-hold circuit places on the input signal source
can also be a problem in some applications, particularly for
sources with large output resistance or limited slew rate. This
is also easily remedied with another unity-gain buffer, now
placed at the input. The resulting design is shown in Fig. 9.
While these buffers do solve the loading problems, in reality
each will have some amount of dc offset, gain error (i.e., the
gain of the buffer is not exactly unity), and nonlinearity, all
of which will directly affect the offset, gain error, and nonlinearity of the overall sample-and-hold circuit. The dynamic performance of the buffers is also a concern. When the sampling
switch is turned on, the input buffer may have to supply a
sudden impulse of current to the sampling capacitor, typically
causing a transient settling response at the buffer output.
This may include both slewing and linear settling behavior,
both of which must settle out to the desired level of precision
before the sampling switch is opened. The buffers will also
have limited bandwidth, creating a steady-state amplitude
and phase error that varies with input frequency, independent of whether the buffer transient responses have settled
or not.
While the simple open-loop sample-and-hold circuit shown
in Fig. 6 does have many performance limitations, some of
these can be reduced or avoided by modifying the circuit architecture. An alternative open-loop sampling using three
clocks is shown in Fig. 10. While 1 and 1d are high, the

1d

In

Buffer

Out

Figure 10. Modified sample-and-hold circuit using additional

switches and an output buffer.

655

input voltage is sampled across the capacitor through the

series resistances of the two switches. The actual sampling
instant occurs when 1 falls, open-circuiting the right side of
the capacitor. 1d then falls immediately afterward, disconnecting the capacitor from the input signal. When 2 goes
high, an inverted version of the sampled input voltage appears at the right side of the capacitor and is buffered to the
output. Note that this circuit cannot be termed a track-andhold circuit, since the output never tracks the input directly,
but instead has its input grounded while the input capacitor
is being charged. The advantage of this design is its avoidance
of signal-dependent charge-injection effects. The 1d falling
edge is intentionally delayed from the 1 falling edge in order
to make only the 1 switchs charge injection important (otherwise 1d is the same as 1). After the 1 switch is off, any
further charge injection or transients at the left-hand side of
the capacitor will not affect the charge that has been isolated
on the node at the right-hand side of the capacitor. In addition, because the 1 switch always operates at ground potential, its channel charge (and on-resistance) will always be the
same, without the need for a bootstrapped gate drive. The
only signal dependence left in the charge injected by the 1
switch is due to variations in the impedance looking back toward the input signal source as the input voltage varies.
While this sample-and-hold circuit has an advantage with
respect to charge injection, it also has a disadvantage in that
it is sensitive to parasitic capacitance at the right-hand side
of the sampling capacitor. Parasitic capacitance to ground at
this point will lead to charge redistribution during 2, thereby
attenuating the sampled voltage and causing a gain error in
the system. In addition, if the parasitic capacitor happens to
be nonlinear, such as the reverse-biased diode junction capacitance associated with the 1 switch, then nonlinearity will
also be introduced along with the attenuation. These effects
are reduced by making the sampling capacitor sufficiently
larger than the parasitic capacitors, but then settling is affected, and another trade-off between speed and linearity can
be seen. An alternative solution to these problems is to use a
closed-loop architecture, which exploits the benefits of negative feedback within its design. These architectures are discussed in a following subsection.
From an ideal standpoint, one would prefer a sample-andhold circuit that did not have any reset phases or a track
phase, but would instead only transition from one hold state
to the next hold state, thus giving the circuitry that follows
the maximum time to utilize the held signal. Although the
circuits shown in Figs. 9 and 10 provide a valid output for
approximately half of the sampling period, this can be extended to a full sampling period simply by using two or more
parallel sample-and-hold circuits that operate on different
clock phases and multiplexing among their outputs, as shown
in Fig. 11 (7). This multirate polyphase design approach
trades off power and circuit area in exchange for an increase
in effective sampling rate and a maximized valid output time.
While this works perfectly in theory, practical issues such as
matching from channel to channel will limit its range of application. For example, if four parallel channels are used, each
with a different dc offset and different gain, then the single
output after multiplexing will contain pattern noise even
when a zero input is applied. In addition, a modulation effect
can occur between the pattern noise and the signal, mixing
high-frequency components to low frequency and vice versa.
If the input is band-limited and sufficiently oversampled,

656

SAMPLE-AND-HOLD CIRCUITS

1A
VIn

1B
VOut

2A
1

1B

3B

2B

3B

4A
1

3A
4A

3A
1

1A
2A

2B
1

have double the input and output swing as the single-ended

design, due to the fact that the signals are now Vplus Vminus
rather than Vplus Vground. This helps keep the signal higher
above the noise floor, thus maintaining a higher signal-tonoise ratio. While fully differential circuits provide numerous
advantages, they also require approximately double the area
and power of a single-ended design, and extra circuitry and
complexity are needed to control the common-mode voltages
of nodes throughout the design. However, most designers of
high-performance analog circuitry have accepted the need for
differential circuitry and utilize it extensively.

4B

4B
1

SAMPLE-AND-HOLD CIRCUITS USING

BIPOLAR AND DIODE DEVICES

Figure 11. Polyphase sample-and-hold architecture demonstrated

using four parallel channels, each phased separately, to achieve a
fourfold increase in effective sampling rate.

then the pattern noise and modulation artifacts can be kept

spectrally separate from the signal component and thus filtered out in a later stage.
While all of the designs shown thus far have used a single
input voltage relative to ground and have provided a single
output also relative to ground, each of the circuits can easily
be converted to a fully differential configuration. Figure 12
demonstrates a fully differential version of the circuit originally shown in Fig. 10, in which the input is applied as the
difference between two node voltages, and the output is supplied as the difference between the two output node voltages.
Fully differential configurations are widely used in high-performance analog designs due to a variety of advantages. If
one assumes that corresponding switches and components are
matched, a fully differential circuit will provide cancellation
of dc offsets associated with charge injection and clock feedthrough due to the (ideally) same charge being injected onto
both sampling capacitors. Because the output is used differentially, only the difference between the sampling capacitor
voltages is important, and so the identical charge that was
injected into both capacitors cancels out. Fully differential circuits also have low (ideally zero) even-order harmonic distortion components due to their symmetry if both sides of the
differential circuitry are matched. These designs also exhibit
higher power-supply rejection than single-ended designs due
to power-supply noise, causing a similar response on both
sides of the differential circuit, which then cancels out when
only the difference in the two output nodes is considered. In
addition, even though the voltage swing of the input and output nodes remains the same, the fully differential circuit will
1d

+
In

++
Buffer

+
Out

1d
Figure 12. Fully differential version of the sample-and-hold circuit
shown in Fig. 10.

The basic components of sample-and-hold circuits can be also

implemented using bipolar technology. Semiconductor diodes
and bipolar transistors are potential candidates for performing the switch function as well as input and output buffering. The holding capacitor could be a metal-metal or a MOS
structure in the case of monolithic implementations or just a
discrete component otherwise. The first part of this subsection
will discuss sample-and-hold circuits in which the required
switching operation is implemented using bipolar transistors.
Following this, diode-bridge sample-and-hold circuits are introduced and the subsection is concluded with a discussion
regarding performance comparison between MOS and bipolar
implementations.
Although the bipolar transistor exhibits similar behavior
to a MOS transistor, when used in amplifier configurations,
there are fundamental differences that prohibit its usage directly as a switch in the same fashion as a MOS-based one.
As an example, for an npn bipolar transistor, when the
base voltage is lower or equal to its collector and emitter voltages, the resistance seen between the emitter and collector is
high. When its base voltage is higher (both basecollector and
baseemitter junctions are forward biased), the resistance
seen between the emitter and collector becomes low; however, it is very nonlinear. Consequently, an arrangement such
as that in Fig. 6 from the previous subsection, where the
switch was replaced with an npn transistor, is not possible.
Consequently, bipolar transistors can be used as switches although not in series with the holding capacitor. An alternative is to use bipolar transistors configured as source followers
in the signal path and employ bipolar-based switches to control their bias current.
Figure 13 presents a simple sample-and-hold circuit in
which the switch is constituted by the combination of bipolar
transistors T1T3 and a current source I. When the clock signal is high, the circuit is in track mode. Transistors T2 and
T3 can be regarded, respectively, as a closed and an open
switch. The current source sinks a bias current I through T1,
which behaves like an emitter follower, and the output voltage Vout tracks the input Vin. The buffer is assumed to have
unity gain. When the clock signal is low, transistor T2 becomes an opened switch and transistor T3 appears as a closed
one, and the current I flows entirely through transistor T3.
The value of the voltage VB (voltage at the buffer output) during this state is determined by the buffer circuitry and the
value of current I, and is designed to be low enough such that
transistor T1 is turned off. This is the hold state, when Vout is
preserved on Chold until transistor T1 is reconfigured again as

SAMPLE-AND-HOLD CIRCUITS
Vsupply

Vin

Buffer

Hold
track

VB
T1

Clock

Hold
track

Clock
Vout

T2

the value of the current source I, since VT is the thermal voltage (VT kT/q 26 mV at 300 K, where k is Boltzmanns
constant, q is the electron charge, and T is the absolute temperature). In the ideal case of an on switch in series with
the holding capacitor (as in Fig. 6), the relation between the
input and the output voltages is
1
Vout (s)
=
Vin (s)
1 + sCholdRswitch

Clock

Clock
T3

Hold
track

(7)

Chold

From Eqs. (6) and (7) it can be inferred that the equivalent
value of the on switch resistor for the circuit from Fig. 13 is

Vin

Rswitch =
Vout

Figure 13. Sample-and-hold circuit using bipolar transistors as

switches. Transistors T2 and T3 act like switches while transistor T1
and the buffer condition the signal from input to output.

an emitter follower. An example for the buffer circuit is

shown in Fig. 14. In track mode, the gain of the buffer is
GB =

657

gm,TB RC
1
1 + gm,TB RE

(5)

if RC RE and gm,TB 1, where TB, RE, and RC are the transistor (gm,TB is its transconductance) and respectively the resistors from Fig. 14. The latter assumption is justified if the
transconductance value is large enough, or equivalently,
there is enough bias current flowing through transistor TB.
Unlike the MOS transistor case, the transconductance of a
bipolar device biased in the linear region is not dependent on
the process parameters and is determined solely by the bias
current, in a first-order approximation. This is advantageous
since the equivalent Rswitch value in the track mode depends
on the source-follower transconductance value. The relation
between input and output voltages of the sample-and-hold circuit from Fig. 13 can be expressed in the s-transform domain
as
gm,T1
Vout (s)
= GB
Vin (s)
gm,T1 + sChold

(6)

where gm,T1 I/VT is the transconductance value of transistor

T1. As mentioned earlier, this value is dependent solely on

Vsupply
RC
Vb

Vin
TB

RE

Figure 14. An input buffer for the sample-and-hold circuit in Fig. 13.

1
gm,T1

VT
I

(8)

As discussed in the open-loop sample-and-hold circuit subsection, the nonlinearity of this equivalent Rswitch resistor is a major contributor to the degradation in performance of the sample-and-hold circuit. Another contributor is the gain error
associated with the equivalent switch (source follower T1 on
Fig. 13) or the input and output buffering operations. Equations (6) and (8) suggest that in a first-order approximation,
there is no nonlinearity associated with transistor T1 and the
only dc gain error is generated by GB. However, the current
source that generates the current I does have finite output
impedance, and this introduces gain and linearity error. For
example, if RI is defined as the current-source output impedance, the dc gain of the circuit in track mode acquires a new
term gm,T1RI /(1 gm,T1RI), where gm,T1 is the transconductance
of transistor T1. Also, the equivalent on switch resistance
becomes
Rswitch =

RI
1 + gm,T1RI

(9)

A given linearity requirement will constrain the input signal

range such that there are small enough variations in the bias
current I due to changes in the input.
There is no buffering at the output shown in Fig. 13, although the circuit would require it for driving a low impedance. Besides gain error, the output buffering introduces
droop errors when implemented with bipolar transistors. The
base current has significantly larger values than the gate current associated with MOS-transistor-based buffers. This effect can be alleviated by using differential topologies in which
the base current produces a shift in the common mode but
leaves the differential voltage across holding capacitors unaffected. Charge injection in bipolar implementations of
switches is less destructive than that in the MOS transistor
case. The reason is a smaller dependency between the amount
of charge dumped into the holding capacitor at the transition
moment from track to hold and the input voltage. Differential
topologies also attenuate this effect as in the droop error case.
Ultimately, the hold-mode feed through, from the Vb voltage
(in Fig. 13) to Vout through the base-emitter capacitance of
transistor T1 can seriously affect performance. Ways to cope
with this are reducing the size (area) of transistor T1 and,
again, employing differential structures that allow placing
cross-coupled capacitors from the input to the output as described in Ref. 8.
Another sample-and-hold circuit based on bipolar transistors is shown in Fig. 15 (9). Transistors TN1, TN2, and TN3

658

SAMPLE-AND-HOLD CIRCUITS

Vsupply

I1

I2
Clock
TN3

Vin

Chold
Input
buffer

Output
buffer

Clock

Vout

Clock
TN2

TN1
TP1

TP2

Rb1

Clock

Rb2

Clock
(a) Basic schematic

Vin
Figure 15. Sample-and-hold circuit where the holding capacitor is connected in series between input and
output; (a) detailed schematic with TN1, TN2, TP1,
TP2 as switches, and inputoutput buffering; (b) simplified schematic during track mode; (c) simplified
schematic during hold mode.

Chold
Input
buffer

b2

= VT ln

I2
IS,TP2

I2
R
TP2 b2

Vout

Vin

Chold
Input
buffer

Vr2

(10)

where Vbe,TP2 is the base-emitter voltage of transistor TP2, VT

is the thermal voltage, IS,TP2 is a constant current related to
transistor TP2, and TP2 is the forward gain factor for transistor TP2. In other words, voltage Vr2 is independent of the input signal and is equal to the sum of the base-emitter voltage
of transistor TP2 and the voltage drop across resistor Rb2. The
voltage on the capacitor is VChold Vin Vr2, which is basically
a shifted version of the input. The output voltage Vout is reset
to Vr2 during this track or sample phase. When the clock signal goes high transistors TN1 and TN3 turn off and TN2
turns on. Current I1 is steered to flow entirely through resis-

Output
buffer

Vout

Vr1
(c) Hold mode, clock high

(b) Track (sample) mode, clock low

are npn devices that function as series switches for steering bias currents. Transistors TP1 and TP2 are pnp devices
and work in either linear region or are turned off. For simplicity, it is assumed that the input and output buffers have unity
gain. When the clock signal is low, transistor TN2 is turned
off, and transistors TN1 and TN3 are turned on. Current I1
[generated by the current source as shown in Fig. 15(a)] flows
entirely through resistor Rb1, which is designed such that the
voltage drop on it, IRb1, turns off transistor TP1 (pnp type).
Also, current I2 [generated by a current source as shown in
Fig. 15(a)] flows through transistor TP2 ( pnp type), which
is biased in the linear region. Removing all transistors that
are turned off, the schematic can be simplified as in Fig.
15(b). The voltage Vr2 shown on this figure can be expressed
as
Vr2 = Vbe,TP2 + VR

Output
buffer

tor Rb2, which is designed in a similar fashion as Rb1 such that

the voltage drop on it, IRb2, turns off transistor TP2. The schematic, again, can be simplified as in Fig. 15(c). The input
buffer provides some current IB, which flows through transistor TP1 biasing it in the linear region. Vr1 can be also expressed as in Eq. (10)
Vr1 = Vbe,TP1 + VR

b1

= VT ln

IB
I
+ B Rb1
IS,TP1
TP1

(11)

with similar meanings applied to transistor TP1. The output

voltage becomes
Vout = Vr1 VC

hold sampled

= Vr1 + Vr2 Vin |sampled

(12)

It is worth mentioning that the output voltage holds a value

of the input sampled when the clock goes high, and it is reset
to Vr2 when the clock goes back to the low state. This puts an
additional bandwidth requirement on the output buffer,
which needs to settle more than the full range of the input
signal. Also, assuming unity gain buffers, as stated initially,
the output is a shifted version of the input taken with opposite sign. To achieve a perfect copy of the sampled input, a
differential topology should be employed (to eliminate the
shift) and either the input or output buffer should have a negative gain. Since there is no true track mode at the output,
one could consider the voltage on the capacitor as a function
of the input when clock is low, and derive the equivalent on
switch resistance. However, this requires taking into account

SAMPLE-AND-HOLD CIRCUITS

the design of the buffers and the parasitic effects of bipolar

devices, which becomes rather involved.
The most common high-speed sample-and-hold circuits employ semiconductor diode bridges. The switching times for
semiconductor diodes are inversely proportional to the cutoff
frequency characteristic to a given bipolar or bipolar CMOS
process. Also the on resistance for these devices is very low
compared to MOS-based switches. For a given current and
reasonable sizes, the transconductance of bipolar transistors
is significantly higher than that for their MOS counterparts.
Since semiconductor diodes can be considered as bipolar devices with the base shorted to the collector, their on resistance is Rswitch 1/gm VT /I, where VT is the thermal voltage
and I is the bias current flowing through the diode. The small
on resistance and short switching times make the diodebridge-based sample-and-hold circuits attractive for veryhigh-speed applications. Figure 16 presents such a basic sample-and-hold circuit without input and output buffering. The
switch is implemented using a diode bridge and two switched
current sources. When the clock is low, the switched current
sources do not generate any current and present a very high
impedance at their output such that the diodes turn off. This
is the hold mode, when in the absence of parasitic effects such
as diode leakage, feedthrough due to diode junction capacitance, or droop due to the output buffer, the output voltage
preserves the sampled input voltage. When the clock goes
high, current I starts flowing through the diodes and the output voltage is following the input after a short settling period.
Since the resistance through the diode is fairly low, the series
terminal contact resistance rb of the diode becomes significant
and should be taken into account. The equivalent on switch
resistance can be expressed as





1
1
1
1
rb1 +
rb4 +
+ rb2 +
+ rb3 +
gm1
gm2
gm4
gm3
Rswitch =
1
1
1
1
rb1 +
+ rb2 +
+ rb4 +
+ rb3 +
gm1
gm2
gm4
gm3
1
VT
(13)
= rb +
= rb +
gm
I
if rb1 rb2 rb3 rb4 rb and gm1 gm2 gm3 gm4 gm,
which is equivalent to state that there are no mismatches
among diodes D1D4. Mismatches among diodes as well as

Vsupply
Clock

I
A

D1

Hold
track

D2

Vin
Vout
D4

Hold
track

Clock

D3
Chold

B
Clock

Hold
track

Vin

Vout
Figure 16. Basic sample-and-hold circuit using a diode bridge.

659

Vsupply

I3

D5

I2
A
D1

Vin

D2

Input
buffer

Output
buffer
D4

D3

D6

Clock

Clock
T2

Vout

Chold

T1
Clock
I1 = I2 + I3
Clock

Figure 17. Diode-bridge-based sample-and-hold circuit with buffering and clamping to the output voltage.

parasitic effects mentioned earlier impact the performance of

the sample-and-hold circuit from Fig. 16 by introducing nonlinearity and gain error. Fortunately, there are circuit techniques that alleviate these effects and one of them is presented later. The voltage at nodes A and B during the track
mode is input dependent. However, during hold mode these
voltages change to some value independent of the input, and
this change couples to the output node through the diode D2
and D3 junction capacitance, creating nonlinearity. This effect can be virtually eliminated during the hold mode by
clamping nodes A and B to a value dependent on the input
sample. This creates a constant voltage change at these nodes
from track to hold, and consequently, a constant perturbation
of the held voltage, which results in offset but no nonlinearity.
Figure 17 presents a circuit that performs the described
clamping operation and includes input and output buffers
that are assumed to have unity gain. When the clock signal
is high, transistor T2 is turned off and current I2 flows through
the diode bridge, generating a low-resistance path between
the input and the holding capacitor Chold. This is the track
mode when the voltage on Chold and the output voltage are
following the input voltage. When the clock goes low, during
the hold mode, transistor T1 turns off and transistor T2 turns
on, bypassing the diode bridge. Current I3 is necessary to
clamp the voltage at node B to Vinsampled Von,D6. Meanwhile,
node A is clamped to Vinsampled Von,D5. So the voltage at nodes
A and B changes from track to hold by Von,D1 Von/D5 and
Von,D3 Von,D6, respectively. These Von voltages are dependent
on the diode sizes and bias current [Von VT ln(Ib /IS)] so the
coupling from nodes A and B to the voltage on Chold through
the junction capacitance of diodes D2 and D3 is signal independent. Also, during the track mode diodes D5 and D6 are
turned off since the output voltage follows the input and the
voltages at node A and B are Vin Von,D1 and Vin Von,D4, respectively. It is important to note that the range of the input
signal is limited to keep the diodes and current sources in
their desired regions of operation.

660

SAMPLE-AND-HOLD CIRCUITS

There are various architectures (1012) based on Fig. 17

that deal with alleviating undesired effects including those
mentioned earlier as well as input and output buffer linearity
and speed. Ultimately, the trade-offs made to improve the
performance of the sample-and-hold circuit need to be tailored
according to the overall application requirements. Bipolartransistor- or diode-based switches appear as a viable option;
however, there are a few key issues that can tip the balance
between a MOS and a bipolar implementation (2). The equivalent on resistance is more linear and potentially smaller in
the bipolar case. Also, bipolar transistors require a smaller
clock voltage swing to be controlled as switches, which results
in a more accurate sampling instant. On the negative side,
they limit significantly the input range and generally create
an offset (eventually due to mismatches) between the input
and output voltages.
Closed-Loop Sample-and-Hold Circuits
Several of the problems that plague open-loop sample-andhold circuits can be avoided through the use of closed-loop
negative feedback in the design. Some of the circuits included
here still perform an open-loop sampling operation, but they
utilize negative feedback in the buffer stage that follows. One
of the simplest configurations that is often used in switchedcapacitor circuitry is the reset integrator, shown in Fig. 18
(13). During 1, the input is sampled onto C1 and the
switched-capacitor integrator is reset to zero by discharging
CF. On 2, the charge on C1 is integrated onto CF, yielding
Vout (C1 /CF)Vin. Note that, as discussed in the subsection
concerning open-loop topologies, the switches at the virtual
ground side of the sampling capacitor open slightly before
those on the opposite side. The use of the switched-capacitor
integrator also avoids problems associated with the parasitic
capacitance at the right-hand side of the sampling capacitor
to ground, since this node always returns to the same virtual
ground potential during both sample and hold modes. Clearly,
the design of an operational amplifier with sufficient gain and
bandwidth is critical to the circuits performance. Droop during the hold mode is typically low in this design and is signal
independent, caused by the leakage current through reversebiased source- or drain-to-bulk diodes associated with the
turned-off switches at the operational amplifier input. A disadvantage of this approach is that the output is not valid until near the end of 2, so an extra clock phase is often needed
after 2 (shown by 3 in Fig. 18) for the circuitry that follows
this stage to utilize the output.

2
1

Vin

C1

Vin

CF

1d
2
2d
3

OA

2d

Vout

Figure 18. A reset integrator sample-and-hold circuit, which uses

open-loop sampling and an operational amplifier in closed-loop feedback as an integrator.

Vout

OA
+

A similar circuit that avoids the extra clock phase is shown

in Fig. 19. The input is sampled onto C1 relative to the virtual
ground of the operational amplifier on 1, and then is placed
in feedback around the amplifier during 2, yielding Vout
Vin. Thus, C1 serves as both sampling and feedback capacitor.
An advantage of this technique is that the dc offset and lowfrequency noise of the amplifier (such as 1/f noise) is removed
by this sampling scheme. The disadvantage is that the operational amplifier is required to sink the input current needed
to charge C1 initially, potentially increasing the operational
amplifier power dissipation, but it still does not offer any input buffering to the driving source.
Another approach to a switched-capacitor sample-and-hold
circuit is shown in Fig. 20 in fully differential form and consists of a simple first-order all-pass filter, with a z-domain
transfer function given by
z1C1 /C2
Vout
=
Vin
1 z1 (1 C1 /C2 )

(14)

which, when C3 C2, reduces to Vout /Vin z1C1 /C2. Therefore,

the input can be simply sampled and scaled by C1 /C2, or a
single-pole discrete-time filter can also be included if so desired. This circuit can easily be utilized with conventional
switched-capacitor design and has even been successfully
used for subsampling a 910 MHz input at a 78 106 samples/
s rate (14).
2

C3

1d
2d

C2

1d

C1

2d

2d

VIn

Figure 19. A sample-and-hold circuit based on switched-capacitor

techniques and using a single capacitor both for sampling and in feedback around the operational amplifier.

1d

C1

1d

+
OA
+

+
VOut

C2

1d

C1

2
2
1

C3

1d
2d

Figure 20. A first-order all-pass switched-capacitor filter used as a

sample-and-hold circuit.

SAMPLE-AND-HOLD CIRCUITS

The sample-and-hold circuit shown in Fig. 20 differs from

those shown in Figs. 18 and 19 in that the circuits output is
not reset during a clock phase. The output transitions from
its previous value to its new value during 2 and then remains constant on 1, thus giving circuitry that follows longer
time to process the signal. Another switched-capacitor sample-and-hold circuit with this same property is shown in fully
differential form in Fig. 21 and utilizes both positive and negative feedback during 2. On 1, the input is sampled onto
C3, and the present output is sampled onto C1. At 2, the C3
capacitors are switched in parallel with the C2 feedback capacitors, and the C1 capacitors are switched in positive feedback around the amplifier. Using C1 C3 results in Vout /Vin
z1, again without any reset phase necessary (15,16).
While the architectures discussed above all require at least
two or three clock phases to function properly, in high-speed
applications it is desirable to use as few clocks as possible,
preferably just one. Figure 22 shows such a circuit that has
achieved 150 106 samples/s operation in a 0.7 m bipolar
CMOS process (17). While 1 is high, the circuit operates as
a continuous-time amplifier with transfer given by
Vout
R 1 + jR1C1
= 2
Vin
R1 1 + jR2C2

(15)

which reduces to Vout /Vin R2 /R1 when R1C1 R2C2. When

1 falls, the input voltage is sampled and buffered to the output. As in the switched-capacitor designs, the sampling
switch operates at the operational amplifier virtual ground
voltage at all times and thus (to first order) does not introduce
signal-dependent charge injection at sampling. A danger with
this design is that the input may still feed through to the
output even during hold mode via the capacitors and resis-

C3

1
2

C1

1d
+
VIn

2d

C2

1
+
OA
+
C
2 2

+
VOut

R1

R2
C2

C1

+
+
OA
+

VIn
C1

C2

R1

R2

Figure 22. A sample-and-hold circuit design using closed-loop feedback during both sampling and hold modes and needing only a single
clock phase (2 is not necessary).

tors. This is only a concern if the operational amplifiers output resistance is too low, but the effect can still be reduced by
adding an extra switch to short out the differential input voltage during the hold mode, as shown by the dashed line in Fig.
22. While this makes a two-phase clocking scheme necessary,
it may be required depending on the operational amplifier design and the hold-mode feed-through requirements.
A similar design that also provides input buffering is
shown in Fig. 23 and replaces the resistors in the previous
design with a differential input transconductance amplifier
with gain G (18,19). During acquisition mode, the system has
a transfer function of
1
Vout
=
Vin
1 + jC/G

(16)

that results in Vout Vin for frequencies well below 0

G/C. The sampling switch isolates the integrator from the
transconductance amplifier during the hold mode, so the integrator holds its state until the switch is turned on again. As
in the circuit of Fig. 22, the sampling switch always operates
at an approximately constant virtual ground voltage (assuming the operational amplifier has sufficient gain and bandwidth for the application), so its charge injection and clock
feed-through will be signal independent to first order. The
closed-loop negative feedback reduces system nonlinearity
caused by that of the open-loop transconductance amplifier
and operational amplifier. An extra switch at the transcon-

C1
Vin

C3

+
VOut

661

+
G

I0

2d

OA
+

Vout

VIn

1d

Figure 21. Another switched-capacitor circuit used as a sample-andhold circuit, now using both positive and negative feedback around
the operational amplifier.

Figure 23. A closed-loop sample-and-hold circuit with both input

and output buffering, using a differential input transconductance amplifier and a switched-capacitor integrator. The switch shown with
the dashed line is recommended to prevent the transconductance amplifier output from saturating while 1 is off.

662

SAMPLE-AND-HOLD CIRCUITS

ductance amplifier output to ground is also recommended, in

order to prevent that node from saturating high or low while
the sample-and-hold circuit is in hold mode. Without this
switch, the transconductance amplifier may experience a
longer recovery time when the circuit returns to acquisition
mode, thus lowering the circuits maximum sampling rate.
In general, sample-and-hold circuit designs that utilize
closed-loop feedback during sampling, such as that shown in
Fig. 23, are not widely used. Input buffering can be achieved
at very high linearity albeit moderate speed using a high-gain
operational amplifier in unity-gain configuration, and openloop sampling at the input of a switched-capacitor integrator
can achieve linearity in excess of 100 dB when designed carefully. The use of an operational amplifier in closed-loop feedback in an integrator configuration is very common, with a
variety of switching configurations possible, and is widely
used to also provide output buffering. Closed-loop designs like
that shown in Fig. 22 are often used not for the increased
linearity of a feedback configuration but instead for the need
of a phase with only a single clock, an advantage in highspeed design. Interestingly, a closed loop sample-and-hold topology as described in Ref. 20 can be even used to perform a
single-ended to differential voltage conversion.

Vsupply

Sample Sample Sample

I
Iout

Iin
SW1

SW3
SW2

2
M1

Chold
Iin

Iout

Figure 24. Current-mode sample-and-hold circuit (current copier).

Capacitor Chold is charged during 1 and holds its charge during 2
generating the output current Iout through transistor M1.

the voltage on the holding capacitor Chold is

Current-Mode Sample-and-Hold Circuits

Current-mode sample-and-hold circuits provide an alternative to voltage-mode implementations described so far. Conversions between current and voltage usually influence the
performance of the overall circuit, and selecting between the
two types of sampling provides an additional degree of freedom during design. Currents could be stored using inductors
similar to voltages being stored on capacitors. However, monolithic implementation of inductors is not practical in todays
technologies and even discrete components do not offer a viable solution due to their nonzero series resistance, which
leads to loss. Also, switching inductors without generating
significant transients appears as extremely challenging.
The easiest and most common method for storing currents
is to convert the current to a voltage or charge and store that
on a holding capacitor. During the hold mode, the current can
be restored through an inverse voltage-to-current conversion.
Since the same transconductance element can be used for the
current-to-voltage and the voltage-to-current conversions, the
overall performance is not affected in a first-order approximation. This subsection will discuss some basic topologies for
current-mode sample-and-hold circuits as well as their nonidealities.
Most current-mode circuits including sample-and-hold circuits are implemented using MOS technology. Very small
gate currents (compared to significant base current in the bipolar case) combined with the existence of gate capacitance
that could be used as a holding capacitor, easy switch, and
logic function implementation are a few reasons behind this
selection. For monolithic implementations, MOS technology is
also less expensive. Figure 24 presents a basic current-mode
sample-and-hold circuit called the alternatively current
copier. Two phases of a clock control the circuit functionality.
When 1 is high, switches SW1 and SW2 are closed and the
input current Iin flows into transistor M1 together with the
bias current I. During this period switch SW3 is opened and
there is no current generated at the output Iout 0. Since
transistor M1 is configured as a MOS diode during this phase,

VC

hold

= VGS,M1 = VT +

2(I + Iin )
nCoxW/L

(17)

where VTh and W/L are the threshold voltage and the size
ratio of transistor M1, respectively, n is the electrical mobility corresponding to n-channel devices, and Cox is the oxide
capacitance. When 1 goes low, the input current value at
that instant is sampled as a voltage on Chold, according to Eq.
(17). When 2 goes high, switches SW1 and SW2 are opened
and switch SW3 is closed. This is the hold phase, when the
output current can be expressed as
Iout = 12 nCox (VGS,M1 VT )2 I = Iin |sampled

(18)

since VGS,M1 VChold as it was stored when 1 went low. It can

be seen that the output current is a perfect copy of the sampled input current in the absence of nonidealities. However,
charge injection from switches and finite output impedance of
transistor M1 can seriously affect the performance. Also, it is
important that 1 and 2 do not overlap since the sample
stored on Chold is corrupted if switches SW2 and SW3 are
closed at the same time. Figure 25 shows a simple circuit that
generates a two-phase nonoverlapping clock. The nonoverlap
duration is given approximately by three logic gate delays.

2
Clock

Clock

1
2
1
Figure 25. Circuit for generating nonoverlapping phases of a clock.

SAMPLE-AND-HOLD CIRCUITS

There are circuit techniques and topology variations that

can be employed to attenuate the effect of nonidealities or to
improve the speed. When the switch SW1 in Fig. 24 is turned
off, a part of the charge stored in its channel is dumped into
the holding capacitor. This charge is signal dependent and
results in nonlinearity at the output. One method to alleviate
this effect was described in the subsection concerning openloop sample-and-hold circuits and relies on dummy-switch
cancellation (21). If the clock edges are steep enough and
switches are implemented using MOS transistors, half of the
charge from switch SW1 appears on Chold when this switch is
turned off. Consequently, a dummy switch with half the
width of switch SW1 can be turned on at the same time,
which would attract the parasitic charge from Chold generated
by switch SW1. Figure 26 shows the dummy-switch cancellation technique. The size ratio of transistor Mdummy is half that
of M1 since the parasitic channel charge of a MOS device is
proportional to this ratio, as described in Eq. (4). Also,
switches SW1 and SW3 were replaced with NMOS transistors
M3 and M4 such that for the shown level of clock phases 1
and 2 they preserve the switch functionality from Fig. 24.
For low and medium resolution (less than 8 bits) the dummyswitch cancellation provides a reliable solution and allows
fast operation due to the small number of components, hence
parasitics, involved. However, mismatches between the
dummy and main switches, nonideal clock edges, and ultimately process-dependent channel charge present a serious
challenge for higher-resolution designs. Employing differential topologies can alleviate the effect of the mismatches. Also,
since the current error due to charge injection is inversely
proportional to the holding capacitor, making Chold larger improves accuracy at the expense of speed. This could be circumvented using Miller-type closed-loop structures that increase
the effective capacitance value with a negligible penalty in
speed performance (2).
Another way of reducing the effect of signal dependent parasitic charge injection is to perform a multiple-step cancellation. Figure 27 shows a two-step cancellation technique that
uses multiple phases of a clock and was first described in Ref.
22. Phase 1 is split into 11 and 12, which contribute to the

Vsupply

2
Sample Sample Sample

I
Iout

Iin
M3

M4

M2

Mdummy

M1
Chold

Iin

Iout

Figure 26. Charge-injection error cancellation using a dummy

switch. The circuit is similar to the one described in Fig. 24, except
switches were replaced by transistors M2, M3, M4, and a dummy
(Mdummy) was added.

663

Sample Sample Sample

Vsupply

11
Cp

Vref

M2
SW5

12

11

SW4

Iin

12
Iout

SW1

SW3

SW2
M1

Chold

Iin

Iout

Figure 27. Two-step charge-injection error cancellation using multiple clock phases.

cancellation process. When 11 is high, 1 is also high and the

circuit behaves similarly to that in Fig. 24. Also, during this
phase Vref is connected to the gate of the PMOS transistor M2,
which acts as a current source with the value Iref . When 11
goes low, the voltage on the holding capacitor Chold corresponds to a current of Iref Iin Ierr through transistor M1,
where Ierr is due to the charge injection from SW2. Ierr exhibits
a strong input signal dependency and if left uncanceled it
would introduce nonlinearity in the output current. Phase
12 goes high immediately following 11. During this, transistor M2 becomes diode connected and generates a current of
Iref Ierr. The corresponding voltage is stored on capacitor Cp
(see Fig. 27). When 12 goes low, 1 also goes low and transistors M1 and M2 remain with their gates connected only to
Chold and Cp, respectively. This is the hold phase: 2 is high
and the output current is generated as a difference between
the current through M1 and the current through M2. The current through M2 is Iref Ierr Ioff , where Ioff is due to the
charge injection on Cp from switch SW4 being turned off and
the end of 12. Since the current through transistor M1 remained as Iref Iin Ierr, the output current during the hold
phase becomes Iin Ioff . The channel charge from switch SW4,
which produces Ioff , contains very little input signal dependency because the voltage across switch SW4 during 12 is
almost constant with respect to the input signal. This is valid
only if the frequency of the clock that generates 1, 11, 12,
and 2 is low enough compared to the signal bandwidth and
the input current Iin varies very little during 12. As a result
the output current is an accurate copy of the input plus an
offset component.
A major performance degradation in current-mode sampleand-hold circuits is due to the finite input resistance of MOS
transistors. This introduces nonlinearity since the current
stored and generated by a MOS device acquires a component
that is a function of the drain-to-source voltage. This voltage
is more often signal dependent unless some precautions are
employed. Cascode structures and differential topologies can
be used to reduce this nonideality. Also, Ref. 23 shows the

664

SAMPLE-AND-HOLD CIRCUITS

1, 2

2, 3
5

Iin
+

Iout

Current
copier

able during 2 and the input is sampled at the end of 1. Any

error in the current copier can be mapped as E(z) and added
into the signal path as shown in Fig. 28. The transfer functions from the input Iin(z) and E(z) to the output Iout(z) can be
expressed as

1
2

H(z) =
4
5

(a)

Intregrator Current
copier
Iin(z)
+

E(z)
+

z1/2
1
1z

z1/2

Iout(z)

(b)

Vsupply

Vsupply

Vsupply
I

3 5

Iin
Ifeed

Iout

2
M1 M2
C1

M3
C2

M4

C3

(c)

Figure 28. Current-mode sample-and-hold circuit using negative

feedback and oversampling. (a) Conceptual diagram; (b) z-domain
block diagram; (c) transistor level implementation.

usage of negative feedback to increase the output resistance

of a MOS device.
Negative feedback and oversampling of the input signal
can be used to reduce the effect of all types of errors described
so far and implement a highly accurate current-mode sampleand-hold circuit at the expense of more hardware. Figure
28(a) presents a conceptual diagram for such a circuit (24).
The difference between the input and output currents is fed
into a current-mode integrator clocked by 1 and 2. Its output is copied to the overall circuit output if 5 is high or fed
back to create the aforementioned difference during 4.
Clearly, the output is an accurate copy of the sampled input
since the integrator and the closed loop would force their difference to zero. Before describing the functionality in more
detail, it is useful to observe the circuit from a z-domain perspective as in Fig. 28(b). The integrator and the current copier
are assumed to be ideal and their z-domain transfer functions
are z1/2 /(1 z1) and z1/2, respectively. The term z1/2 in the
integrator transfer function signifies that its output is avail-

Iout (z)
= z1 ,
Iin (z)

H =

Iout (z)
= 1 z1
E(z)

(19)

It can be seen that the input transfer function H(z) is just a

delay as in the case of any sample-and-hold circuit. On the
other side, the error transfer function H has a zero at dc
(when z 1) similar to the noise-shaping performed by a
first-order data converter. As a result, H is a high-pass
characteristic and the amount of error at the output is proportional to the ratio of the input frequency f input to the frequency
of the clock f clock. The errors associated with the integrator are
also attenuated by the aforementioned oversampling ratio
(OSR f clock /2f input) as discussed in Ref. 24. By increasing the
number of integrators and feedback loops, the analogy to
modulation can be continued and the accuracy of the output
current increases accordingly. The speed can be also improved
using parallel architectures based on the same circuit from
Fig. 28(a) clocked on alternate phases.
Figure 28(c) shows a MOS transistor implementation of
the diagram from Fig. 28(a). The difference between the input
current Iin and the feedback current Ifeed is applied to the integrator during 1. The functionality of the current-mode integrator can be easily explained assuming a constant input current Ict. Assuming that initially the same current I/2 flows
through both transistors M1 and M2, when 1 goes high transistor M1 will conduct I/2 Ict. When 1 goes low and 2 goes
high transistor M2 will conduct I/2 Ict. When 1 goes high
again, M1 will conduct I/2 2Ict and correspondingly when
2 goes high transistor M2 will conduct I/2 2Ict. Clearly, the
left-hand branch containing transistor M1 will conduct more
and more current, while the right-hand branch including
transistor M2 will conduct less and less. Transistor M3 mirrors out the current resulting from the integration process.
Then, transistor M4 is used to create a current copier as in
Fig. 24, which generates alternatively the output and the
feedback currents.
Another circuit that uses feedback to provide an accurate
sample of the input current is shown in Fig. 29 (25). This is
similar to Fig. 23 except that instead of a voltage at the input
of the transconductance, a current at its output is sampled.

Chold
+
gm1
T3

Clock

SW1

OA

+
gm2

+
Iin

Iout
Iin

Iout
Figure 29. Closed-loop current-mode sample-and-hold circuit. This
circuit resembles the one in Fig. 23, except that a current is stored
as opposed to a voltage.

SAMPLE-AND-HOLD CIRCUITS

When the clock is high the input current is stored as a voltage

on Chold. Since the negative input to the operational amplifier
OA is preserved as a virtual ground, the feedback loop containing gm1, switch SW1, and the operational amplifier OA
forces the voltage on the holding capacitor to VChold Iin /gm1
where gm1 is the transconductance value. During the hold period when the clock signal is low, the output is maintained at
Iout =

gm2
I |
gm1 in sampled

(20)

It is worth mentioning that gm2 and gm1 are physically different elements and their mismatches as well as nonlinearity
impact the performance of this sample-and-hold circuit. Also,
the speed of the circuit depends largely on the operational
amplifier settling time.
Real-life implementations of the current-mode sample-andhold circuits described so far include usually more elaborate
structures that are targeted at cancelling parasitic effects.
Some of them employ differential topologies or improvements
related to the finite output impedance of MOS transistors.
Other structures employ more sophisticated clocking schemes
or feedback to cancel charge-injection errors. Furthermore,
closed-loop architectures must deal with stability issues that
come into play as a trade-off regarding the accuracy (in the
case of discrete-time feedback as in Fig. 28) or the speed (for
the continuous-time feedback as in Fig. 29) of the circuit. Although there are advantages in using current-mode sampleand-hold circuits particularly regarding operating speed,
their widespread usage was hampered by the need of voltageto-current and current-to-voltage conversions as well as implementation difficulties when higher accuracy is required.
CONCLUSIONS
Sample-and-hold circuits are widely used in a broad variety
of circuits and systems, from sensor-conditioning applications
to communications designs to data-conversion systems. In
many cases the whole system design starts with specifying
the sample-and-hold operation, and its implementation can
even dictate a specific overall architecture. While the concept
of a sample-and-hold circuit seems quite simple in its idealized form, the previous sections have shown how complex and
detailed the designs and requirements can become. The various performance metrics that have been established for evaluating sample-and-hold operation are useful in setting specifications for a design to be used in particular applications.
These specifications then allow the designer to survey the
many techniques and architectures that exist for sample-andhold circuits and focus on the one that best meets these requirements and is most efficient for implementation. The
broad variety of design topologies available is evidence itself
of their differing advantages and disadvantages, all of which
must be considered when determining the suitability of a design for the given application.
The designs discussed here were chosen as a representative subset of the many sample-and-hold architectures that
exist, and myriad variations and modifications on these can
be found. The techniques used in the designs depend heavily
on the integrated-circuit technology, with series switches and
switched-capacitor-based designs most prevalent in MOS
technologies, while current steering and diode bridges are

665

common in bipolar designs. Current-based designs, as discussed earlier, are attractive for applications involving current-output sensors and current-mode signal processing, and
have given rise to several innovative design concepts. Higherspeed and finer-line integrated-circuit processes will continue
to push existing design techniques to higher and higher performance levels, and innovative conceptual and architectural
breakthroughs will provide an extra boost to exceed the performance barriers that rise as time goes on.
BIBLIOGRAPHY
1. W. Kester and J. Bryant, Sample and Hold Circuits in W. Kester
(ed.), Analog Devices Linear Design Seminar, Norwood, MA: Analog Devices, 1995, pp. 8.448.67.
2. B. Razavi, Principles of Data Conversion System Design, Piscataway, NJ: IEEE Press, 1995.
3. A. Sanchez, Understanding sample-hold modules, in Analog Devices Analog Dialogue, Norwood, MA: Analog Devices, 1971, pp.
5154.
4. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Orlando, FL: Saunders HBJ, 1987.
5. T. L. Brooks et al., A 16b pipeline ADC with 2.5 MHz output
data-rate, ISSCC Dig. Tech. Papers, San Francisco, 1997, pp.
208209.
6. G. Wegmann, E. A. Vittoz, and F. Rahali, Charge injection in
analog MOS switches, IEEE J. Solid-State Circuits, SC-22 (6):
10911097, 1987.
7. T. V. Burmas et al., A second-order double-sampled delta-sigma
modulator using additive-error switching, IEEE J. Solid-State
Circuits, 31 (3): 284293, 1996.
8. P. Vorenkamp and J. P. M. Verdaasdonk, Fully bipolar, 120Msample/s 10-b track-and-hold circuit, IEEE J . Solid-State Circuits, 27 (7): 988992, 1992.
9. B. Razavi, Design of a 100-MHz 10-mW 3-V sample-and-hold amplifier in digital bipolar technology, IEEE J. Solid-State Circuits,
30 (7): 724730, 1995.
10. B. Razavi, A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply, IEEE J. Solid-State Circuits, 30 (12): 1326
1332, 1995.
11. M. H. Wakyama et al., A 1.2-m BiCMOS sample-and-hold circuit with a constant-impedance, slew-enhanced sampling gate,
IEEE J. Solid-State Circuits, 27 (12): 16971708, 1992.
12. T. Wakimoto and Y. Akazawa, Circuits to reduce distortion in the
diode-bridge track-and-hold, IEEE J. Solid-State Circuits, 28 (3):
384387, 1993.
13. P. E. Allen and E. Sanchez-Sinencio, Switched-Capacitor Circuits,
New York: Van Nostrand Reinhold, 1984.
14. D. H. Shen et al., A 900 MHz RF front-end with integrated discrete-time filtering, IEEE J. Solid-State Circuits, 31 (12): 1945
1954, 1996.
15. K. Y. Kim, N. Kusayanagi, and A. A. Abidi, A 10-b, 100MS/s
CMOS A/D converter, IEEE J. Solid-State Circuits, 32 (3): 302
311, 1997.
16. G. Nicollini, P. Confalonieri, and D. Senderowicz, A fully differential sample-and-hold circuit for high-speed Applications, IEEE J.
Solid-State Circuits, 24 (5): 14611464, 1989.
17. L. Schillaci, A. Baschirotto, and R. Castello, A 3-V 5.4-mW
BiCMOS track & hold circuit with sampling frequency up to 150
MHz, IEEE J. Solid-State Circuits, 32 (7): 926932, 1997.
18. U. Gatti, F. Maloberti, and G. Palmisano, An accurate CMOS
sample-and-hold circuit, IEEE J. Solid-State Circuits, 27 (1): 120
122, 1992.

666

SATELLITE ANTENNAS

19. K. R. Stafford, A complete monolithic sample/hold amplifier,

IEEE J. Solid-State Circuits, SC-9 (6): 381387, 1974.
20. W.-C. Song et al., A 10-b 20-Msample/s low-power CMOS ADC,
IEEE J. Solid-State Circuits, 30 (5): 514521, 1995.
21. T. S. Fiez and D. J. Allstot, Switched-current circuit design issues, IEEE J. Solid-State Circuits, 26 (3): 192202, 1991.
22. J. B. Hughes and K. W. Moulding, S2I: A switched-current technique for high performance, Electron. Lett., 29 (16): 14001401,
1993.
23. X. Hu and K. W. Martin, A switched-current sample-and-hold circuit, IEEE J. Solid-State Circuits, 32 (6): 898904, 1997.
24. I. Mehr and T. L. Sculley, A 16-bit current sample/hold circuit
using a digital CMOS process, Proc. IEEE Int. Symp. Circuits
Syst., 1994, pp. 5.4175.420.
25. D. H. Robertson, P. Real, and C. Mangelsdorf, A wideband 10bit, 20 Msps pipelined ADC using current-mode signals, ISSCC
Dig. Tech. Papers, San Francisco, 1990, pp. 160161.

IURI MEHR
Analog Devices, Inc.

TERRY SCULLEY
ESS Technology, Inc.

NADI ITANI
Cirrus Logic, Inc.

SAMPLED-DATA CONTROL. See DIGITAL CONTROL.

SAMPLED-DATA SYSTEMS. See SWITCHED CAPACITOR
NETWORKS.

SAMPLING WATTMETERS. See WATTMETERS.

192

SEQUENTIAL CIRCUITS

VDD

CK

Q D
R

Q
CK

(a)

(b)

Figure 2. (a) Set-reset latch, (b) half (master) of D latch.

has elementary intelligence. The experience of a sequential

circuit is the processed data of the past inputs. This is the
most fundamental significance of a sequential circuit. A combinatorial circuit driven by uniformly delayed input signals is
not a sequential circuit, even if it has memories. Since the
combinatorial circuit is known (1,2), we consider the memories first. The sequential circuit memories have subtle details
that characterize the circuit. In recent years, most of the logic
circuits have been built as integrated circuits, and for a largescale integration, CMOS is the preferred technology. The circuit examples are mostly CMOS circuits.
MEMORIES

SEQUENTIAL CIRCUITS
DEFINITION AND STRUCTURE
Logic circuits are classified into combinational and sequential
circuits. The classification has no ambiguity, because there
are two qualitatively different digital circuit elements in their
idealized model: logic gates, which respond instantaneously to
the inputs, and memories, which retain the past input data. A
combinational circuit is made of logic gates only. A sequential
circuit is made of combinational circuits and memories, and
some inputs to the combinational circuits are driven by the
outside signal and the rest by the memory outputs. The combinational circuits drive the memories and store the logic operation results in them. The signal paths of a sequential circuit make a closed loop, as schematically shown in Fig. 1. As
the digital signals circulate the loops, the processing is carried out in sequence. That is why the circuit is called sequential. Since some of the input signal to the combinational circuit comes from the memories that hold the data previously
processed by the circuit, it is able to produce a logic answer
not only from the present input data, but also using the past
input data. If intelligence is defined as the capability of using
experience for present decision making, a sequential circuit

Inputs

Outputs
Combinational
circuit
Memory

Figure 1. Structure of a sequential logic circuit.

Memory devices used in a sequential logic circuit are of two

different types. One type has positive feedback controlled by
signals from the outside, and its memory retention time can
be controlled by the control signals or by a clock. The clock is
a systemwide memory control signal by which the processing
proceeds in regular steps, and the memory is able to retain
the data for any length of time. This type of memory is called
a latch or a flip-flop. The other type of memory is either a
cascaded chain of gates or some other continuous physical
structure that is able to delay the input signal to the output.
The output signal of the delay circuit at time t is the input
signal at time t , where is the delay time.
The memory devices of the first type have popular names.
The conventionally used devices are as follows: (1) set-reset
latch, (2) D latch, (3) T flip-flop, and (4) J-K flip-flop. The T
flip-flop changes the state every time the input makes a transition. The J-K flip-flop has several combinations of these features. All of the memory devices come in clocked and unclocked versions. The D- and the set-reset latches are
preferentially used in integrated circuits, and the other types
are referred to in McCluskey (3), Nagle (1), and Mano (2). In
CMOS VLSI circuits, two types of latchesthe set-reset latch
and the D-latchare most frequently used. Although there
are several variations of latch circuits, a typical circuit used
for ultra-high-speed CMOS circuits is shown in Figs. 2(a) and
2(b). In Fig. 2(a), if S is HIGH and R is LOW, the set-reset
latch stays in the state it was previously forced into. Subject
to this condition, if S is temporarily pulled down to LOW
while R is kept LOW, the latch is set, or Q output becomes
LOW if it has not been in the set state. Subject to the same
condition, if R is temporarily pulled up to HIGH while S is
kept HIGH, the latch is reset, or Q output becomes HIGH. If
S is LOW and R is HIGH simultaneously, the latchs subsequent state is unpredictable. In a VLSI circuit such a conflict
can be prevented by adding an extra logic circuit. J-K flipflop, originally intended to avoid the control input conflict, is
used infrequently. The circuit of Fig. 2(b) is the half of the D

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

SEQUENTIAL CIRCUITS

latch. In a sequential logic circuit the second stage, in which

the control clock CK and CK are exchanged, is directly cascaded to it, and the pair is called a master-slave D-latch pair.
The circuit of Fig. 2(a) or 2(b) has a strong output driver
(shown by the large inverter sign) that drives the output, and
a weak driver (shown by the small inverter sign) that holds
the input of the strong driver. The set/reset FET of Fig. 2(a)
and the transmission gate of Fig. 2(b) must be able to overpower the output node held by the small inverter. This type
circuit is faster than the conventional latch circuit using the
tristable inverters.
The delay device used instead of the controllable memory
device is generally called a delay line. In spite of the name,
the traditional LC or the acoustic-delay lines are not used
anymore. Rather, the natural delays of the cascaded logic
gates, especially of simple inverters, are used. In this type of
delay-memory circuit, certain requirements exist for the circuits operational integrity. Figure 3, curve A, shows the input
waveform to a delay line. If the delay line outputs a slowly
rising (or falling) waveform like curve B, the delay line as a
memory device is not acceptable. This is because the delay
time of signal B referenced to signal A depends on where the
logic threshold voltage, the boundary between the Boolean
HIGH and LOW levels, is set. Depending on the logic gate
driven by the delay line output, as well as the gates operating
condition (e.g., the timing of the other input signal), the delay
time varies over a wide range. Since the delay line does not
have a definite delay time, the circuits operational integrity
is compromised. A signal like curve C has a clearly defined
delay time, and the delay line is acceptable as a memory. To
create a waveform like C, the delay line circuit must have a
crisply switching buffer at least at the output stage, or LC
delay line structure. A passive RC low-pass filter is not acceptable, because the output waveform looks like curve B. A
confusing issue in sequential circuit classification is that if a
chain of logic gates makes a closed loop, the loop works as a
memory device as well as a combinational logic circuit. It is
impossible to separate the loop circuit into combinational and
memory parts. From this viewpoint, any logic circuit that has
a closed loop of gates is a sequential circuit, and this is its
widest definition based on the circuit structure. The schematic of Fig. 1 cannot be used to characterize this type of
circuit directly without further interpretation, which will be
provided later.
CLASSIFICATION OF SEQUENTIAL CIRCUITS
In a sequential circuit, the combinational logic part has no
feature to distinguish one circuit from the other. To classify a
sequential circuit, we observe the structure of the loops. The
key features by which to classify sequential circuits are (1) if
a loop is a single loop or a multiple loop, and (2) how the loops
are controlled. The most convenient means of classification
is to single out the most convenient and most widely used

Voltage
A

Time

Delay time
Figure 3. Delay line memory waveform requirement.

193

synchronous sequential circuit by focusing attention on the

function of the clock, and then to discuss the other, asynchronous sequential circuits, in regard to their special features.
The memory device used for a conventional synchronous
sequential circuit is a pair of D latches (Fig. 2) connected in
the master-slave configuration. The rectangular box represents the latch. The symbols in the box, D is the input, C is
the clock, and Q and Q are the normal and the inverted outputs [see Fig. 2(b)]. The latch pair replaces the memory block
of Fig. 1. The combinational logic circuit is driven by outputs
from the slave latches and by external signals. The external
signals must be synchronized to the clock, to fit into the appropriate timing window. The master latch receives the signal
processed by the combinational circuit. In the simplest implementation, all the master and all the slave latches are driven
by a clock and its complementary, respectively. When the
master latches are transparent (input open), the slave latches
are their inputs closed, and vice versa. The clock transition
must be fast to ensure that either the master latch is transparent and the slave latch is closed, or the master latch is
closed and the slave latch is transparent. This is called an
edge-triggered timing scheme.
At the beginning of a process cycle, the clock transition
effects disconnection between the logic circuit and the master
latches. The source data to the combinational logic circuit are
secured first by the positive feedback retention mechanism of
the master latches, to the designated Boolean levels. The
Boolean levels are transferred to the slave latches that are
transparent and to the combinational circuit; while that is
going on, the combinational logic circuit has already started
processing the data. Then the second clock transition effects
disconnection between the master and the slave latches, and
the slave latches apply positive feedback to retain the acquired data. The master latches are now open and are ready
to accept the processed data as they arrive at the master
latchs input terminals. During the data acquisition process
by the master latch, the latch circuits delay exercises intelligence to filter out the noise and the spurious pulses. At the
end of the logic operation period set by the clock, the master
latch is disconnected from the combinational logic circuit, and
its output is connected to the slave latch. The master latches
exercise intelligence to decide the Boolean level of the output
of the combinational circuit by eliminating the spurious noise,
and then by quantizing to generate the Boolean level. The
processed data, or the answer of the cycles logic operation, is
now available to the slave latch. The synchronous sequential
circuit is now ready to start a new clock cycle with new input data.
Synchronous sequential logic circuits have a number of advantages. Their step-by-step operation timed by the systemwide clock is easy to understand, design, and simulate, since
the electrical phenomena in different cycles can be studied
independently. This is perhaps the most important reason for
their preferred use. Asynchronous sequential circuits are difficult to understand, design, and verify. Some of the problems
of asynchronous sequential circuits, such as the race condition, do not exist in synchronous circuits, and in a synchronous system metastability failure does not occur if simple and
uniform design discipline is followed. Furthermore, the data
processing load can be optimally distributed over the clock
cycles to attain the maximum throughput. Based on these advantages, synchronous sequential circuits are the predomi-

194

SEQUENTIAL CIRCUITS

nant choice in implementing high-performance systems. The

clock required to drive the system is simple. This scheme has
a variation: The combinational logic circuits are inserted between the master and the slave latches, as well as between
the slave and the master latches. This variation has more
flexibility than the simplest scheme and is more tolerant to
the rise/fall time requirement of the clock, but it requires a
four-phase clock.
A sequential circuit that does not have the features of the
previously defined synchronous sequential circuit belongs to
a loosely defined group of asynchronous sequential circuits.
Existence of the system-wide clock is crucial, but the choice
of memory is also an issue: Specifically, a circuit using setreset latches instead of D latches, or a circuit using the delay
element as a memory device belong to asynchronous circuits.
Practically, a large-scale synchronous sequential circuit may
have an asynchronous sequential circuit as part of it, and
clear distinction between them is impossible. Asynchronous
sequential circuits are convenient for implementing simple
function directly interfacing to the human hand.
REPRESENTATION OF SEQUENTIAL CIRCUIT OPERATION
Sequential circuits carry out the most complex signal processing operations in electronics. It is necessary to have a
simple and intuitive way to represent their operation in
graphical or tabular form. The circuit shown in Fig. 4 has two
inputs, one output, and two D latches. The D latches are in
the master-slave configuration, or the two cascaded stages of
the simple latch circuit shown in Fig. 2(b) and driven by the
complementary pair of clocks. The two latch outputs (y1, y2)
can be any of the four combinations, (0,0) through (1,1). The
input variables x and w, and the two outputs of the latches
y1 and y2, determine the present state of the circuit at the
clock phase in which the master and the slave latches are
disconnected. The set of variables x, w, y1, and y2 (not the
complemented form y2) define the total state of the sequential circuit.
The next states Y1 and Y2, and the output z of the circuit
of Fig. 4, are written by Boolean algebra as follows:
Y1 = y2 + x

Y2 = y1 + w

z = wy1 + xy2

The output of latches 1 and 2 determines the present internal

state of the circuit. The Boolean levels are written in a vector
format (y1, y2), as (0,0) or (0,1), to designate the internal state.
As the HIGH to LOW clock transition occurs, the connection
to the master latches is closed, and the state of the master
latches is transferred to the slave latches to become the next
state of the circuit. The sequence of transitions caused by the
clock transition and by the input signal describes the opera-

Latch 1

Latch 2

D Q

D Q

w
y1

00
10/1
11/1

00/0 00/0 10/0 11/0

01/1
00/0
11
11/1
10/1
01/0
00/0
00/0

10
10/1

Figure 5. State transition diagram.

tion of the circuit. One convenient way to describe the circuit

operation is to use the state transition diagram shown in Fig.
5. In this figure the four internal states of the circuit are
shown within the circles. The arrowed curves connecting the
circles are the state transitions caused by the clock and the
input signals. The indications associated with the curves, **/
*, show the input signal Boolean levels in the order of (w-x)
in front of the slash, followed by the Boolean level of the output z.
The state diagram of Fig. 5 is the Mealy-type state diagram (2), by which the input signals and the present internal
state determine the output signals and the next internal
state. In the Mealy diagram the clock of the memories affects
the state transition and the output change, but, in addition,
an asynchronous input change may affect the output. To
make a completely synchronous representation of the system,
the input signals must be assumed to have been delivered
from the outside memories, which are driven by the same
clock. There is a second, Moore-type, state diagram, in which
only the present state and the inputs creating a transition to
the next state are shown. The present outputs are determined
by combinational circuits from the present internal state. In
the Moore diagram the outputs are synchronized to the memory clock.
A second way of describing the circuit operation is to use
the state transition table shown in Table 1. In this table, the
columns are the four possible combinations of the input signals w and x, and the rows are the four possible present internal states of the circuit [as defined before, the vectorical combination of the latch outputs (y1, y2)]. The entries of the table
are the next state of the circuit upon the clock transition followed by the output(s). Both the state diagram and the state
table describe the circuit operation independent of the input
signal sequence, and this compactness is the convenient feature of the two representations.

Present State

Y1

C Q

Y2

01

Table 1. State Transition Table

y2
x

01/1
11/1

C Q
CK

Figure 4. An example of a synchronous sequential circuit.

y1 y2
00
01
11
10
*

Input w and x
00
11/0
11/0
11/0
11/0

01
11
01/1
01/1
11/0
11/0
11/0
10/1
01/1
00/1
Next state Y1 , Y2 /output

10
11/0
11/0
10/1
10/1

SEQUENTIAL CIRCUITS

The state transition diagram and the state transition table

give the peculiarities of the circuits. The circuit has two internal states, (00) and (01), which are transitory; if the clock
edge arrives, the state changes to other state. The states (10)
and (11) are not transitory; if in the state (10) and if the input
is (10), the circuit returns to the same state after a clocktick.
The state (11) has two possible inputs, (01) and (00), that
bring the circuit back to the same state after a clocktick. If
(01) and (00) input alternate and if the circuit is originally in
the internal state (11), the circuit is stuck at state (11) forever. The circuit has no stable state. The circuit has instability: If the input is (11), the circuit goes through a sequence
(00) (01) (11) (10) and back to (00). The circuit works
as a ringoscillator. As observed from this example, the input
sequence independent representation provides many insights
into sequential circuit operation.
MODEL OF ASYNCHRONOUS SEQUENTIAL CIRCUITS
Definition of asynchronous sequential circuits is not a simple
matter, because the memory device, a latch, is not an atomlike building block of a logic circuit: Either it is a uniform
delay line, or it consists of atomlike gates, and a memory can
be built by connecting any number of logic gates in a closed
loop. Such a generalized data storage device has a built-in
data processing capability as well, and the inputs to the loop
cannot be named by descriptive names, such as set, reset, and
clock. This complication makes design, analysis, and representation of the operation of an asynchronous sequential circuit complex and its subclassification arbitrary. A simple
memory device like a set-reset latch is used in asynchronous
sequential circuits. Asynchronous sequential circuits that use
unclocked set-reset latches, shown in Fig. 2(a), are often used
to implement a simple state machine that accepts inputs directly from a human operator. The debounce circuit, which
reshapes the pulse from toggling a mechanical switch, is perhaps the most popular use of a set-reset latch.
To design a sequential logic circuit that has specified functionality is the problem of synthesis. Circuit synthesis requires analysis methods, a few general methods to convert
the functionality specifications to the best form for implementation, and a lot of insight and experience in system-level operation. We discuss the first two, the analysis methods and
design specifications that are common to synchronous and
asynchronous circuits, while using an asynchronous circuit as
an example.
The circuit shown in Fig. 6 is an asynchronous sequential
circuit having two loops made by conventional logic gates. The
objective of the following analysis methods is to find out the
peculiarities of operation of the circuit: If the peculiarities are
found, we may say that we understand the circuit. The first

x1

Y1
y1
y2

x2

M1
M2

Y2

Figure 6. An example of an asynchronous sequential circuit.

195

Table 2. State Transition Table

*
y1 y2
00
01
11
10
*

Inputs x1 and x2
00
01
11
11
01

01
00
11
11
00

11
00
11
00
00

10
01
11
01
01

Y1 and Y2

analysis step is to separate the logic operation and the delay

of the gates. The logic gates in the figure are idealized logic
gates that execute the logic operation instantly. The delay
times of all the gates of the two loops are lumped into the
fictitious delay elements M1 and M2 shown in the figure,
which work as delay line memories. A digital signal propagates from the right to the left through the fictitious delay
elements, and the input and the output have different node
variable names. The outputs of the delay elements have node
Boolean variables y1 and y2, and inputs Y1 and Y2, respectively. The input signals x1 and x2 and y1 and y2 define the
total states of the asynchronous sequential circuit.
In a synchronous sequential circuit the one clock for all the
memories has the function of pushing the state of the circuit
forward. In an asynchronous sequential circuit any input signal may control the state of the memories, which are most
often complex loops of gates. Then for the following analysis,
as well as in the real operation of the circuit, only one input
variable is allowed to change at a time. When the input variable changes, the circuit must have arrived at the steady
state already, determined by the previous input signal
change. An asynchronous sequential circuit operates subject
to this stronger condition than a synchronous sequential circuit, and therefore the processing power and the operational
flexibility are less than for a synchronous circuit.
Using the total state (x1, x2, y1, y2), the next state variables
Y1 and Y2 are determined by the Boolean logic equations
Y1 = x1 y2 + y1 y2

Y2 = x1 y2 + y1 y2 + x2

and the state transition table is made, as shown in Table 2.

In this example, Y1 is the output.
The transition table shows various peculiarities of the circuit. If the input signal (x1, x2) is either (0,0) or (0,1) and if
the initial internal state (y1, y2) is (1,1), the next internal
state (Y1, Y2) is (1,1), or the internal state never changes. The
circuit is in a steady state if x1 0. Similarly, if the input
signal is either (0,1) or (1,1) (or if x2 1) and if the initial
internal state is (0,0), the state never changes. In the two
conditions the circuit is in a steady state that does not change
with time. If the input signal is held at (0,0) and if the initial
internal state is (0,0), the next internal state is (0,1), followed
by (1,1), and the circuit arrives at the steady states for x1 0
and x2 0. If the internal state immediately after the input
signal change is not one of the steady state, the circuit takes
several steps to one of the steady states. This is not the only
mode of operation of the circuit. If the input signal is held at
(1,0) and if the initial internal state is (0,1), the next internal
state is (1,1), and the next to the next internal state is (0,1),
the same internal state as the initial internal state. The circuit oscillates between the two internal states. In this case

196

SEQUENTIAL CIRCUITS

the circuit is equivalent to a three-stage cascaded enabled inverting gate, which works as a ringoscillator.
The state transition diagram or state transition table provides many details of asynchronous sequential circuit operation, other than those discussed before. For the purpose of
circuit synthesis, it is convenient to represent the internal
state not by a preassigned Boolean vector form like (0,0), but
by a symbolic character A, B, . . .. Here we use identification
like A: (0,0), B: (0,1), C: (1,1), and D: (1,0) in the state transition table, as in Fig. 7. This figure is to show various structures of a state transition table, and it is not related to the
last example. Figure 7(a) shows that the next state of B for
any value of input x is B. This means that state B is a state
if, once entered, the circuit stays in forever. The state can be
entered from another state, or it can be initially set. If the
other entries *s of Fig. 7(a) have no B state, the B state is an
isolated internal state, and if the state transition table has
an isolated internal state, the state diagram is separated to
two independent parts. Figure 7(b) shows that as long as x is
1 the next state of B is C, and the next state of C is B. The
states B and C alternate, and the circuit oscillates. This is an
unstable circuit that is not practically usable as a logic circuit.
In Fig. 7(c) the oscillation goes over the entire state as x
makes a transition from 0 to 1 and stays at the value: The
state sequence is A, D, B, C, and back to A.
The entries of the state transition table can be any of the
four internal states, A, B, C, or D, in any order and in any
number of duplications, although many of such randomly generated tables do not carry out useful functions. This great
variability creates many other strange, often practically undesirable behaviors. In Fig. 7(d) we note the internal state A
(0,0), B (0,1), C (1,1), and D (1,0). If the initial state is
A, the two memory outputs that determine the internal state
of the circuit both flip if x changes from 0 to 1. If the timing
sequence is included in consideration, the change may take
place in three different ways: (1) a simultaneous change, A
C, (2) A B C, and (3) A D C. In the state transition
table of Fig. 7(d), all the three changes end up with the same
final state C. The circuit executes the logic operation correctly. If the state transition diagram is as shown in Fig. 7(e),
however, the final state depends on the timing sequence: (1)
A simultaneous change, A C, ends up with state C; (2) if

y1 y2
A

A B occurs first, the circuit settles at state B; (3) if A D

occurs first, the circuit settles at state D. Since the order of
occurrence of the state change is not indicated in the logic
diagram, the final state cannot be determined from the logic
diagram alone. The problems discussed in relation to Figs.
7(d) and 7(e) are called the race condition, since the final destination depends on the order of the state change (5). Figure
7(d) is called a noncritical race, since the final state does not
depend on the order. Noncritical race is usually harmless for
logic circuit operation. Figure 7(e) is called a critical race,
since the final state is determined by the order. A critical race
condition can be avoided if there is a state sequence that
leads to the correct final state, if the state change sequence
occurs in an arbitrary order. In Fig. 7(f), if the state sequence
occurs simultaneously, the circuit ends up with state C. The
critical race condition is avoided by the intermediate state B,
which has the right destination state C. If A B occurs first,
the sequence B C follows, and the circuit ends up with a
correct state. If A D occurs first, however, the circuit ends
up with state D, which is not the state the designer intends.
From these observations, the critical race condition can be
avoided in several ways: by providing an intermediate internal state like B, through which the circuit ends up with the
correct final state, or by assigning proper binary state vectors
to the symbolic internal states A, B, C, and D such that only
one latch changes the state upon input transition. A number
of possibilities of circuit operation exist, and the state table is
a simple method by which to analyze complex cases.

OPERATION ON THE SET OF INTERNAL STATES

State is the central concept of sequential circuits. Operations
on a set of states, such as simplification, choice of a better set
of states for hardware minimization or for high reliability, or
assigning binary vectors to a symbolic state, as we saw before
are an important issue, both for circuit analysis and synthesis. If a sequential circuit is considered as a black box accessible only from the input and output terminals, the set of internal states within the black box creating the functionality may
have many alternatives. If a circuit design already exists, the
choice of internal states may not be the simplest or most de-

*
B

*
B

y1 y2
A

Figure 7. State transition diagram and asynchronous sequential circuit operation.

(b)

y1 y2
A

1
D

*
C

*
B

*
B

y1 y2
A
B

(a)

y1 y2
A

(c)

1
C

y1 y2
A

1
C

(d)

(e)

(f)

SEQUENTIAL CIRCUITS
Table 3. Original State Transition Table
Initial State

Table 4. Simplified State Transition Table

Initial State

Input x
x0
F/0
D/0
F/1
E/1
E/0
E/0
A/1

*
A
B
C
D
E
F
G
*

197

x1
C/0
F/1
B/1
A/0
C/0
C/0
B/1

*
A
B
C
D
*

Input x
x0
A/0
D/0
A/1
A/1

x1
C/0
A/1
B/1
A/0
Final state/the output

Final state/the output

sirable. The first of such issues is simplification of the circuit

by reduction of the number of internal states of a sequential
circuit while maintaining the same input-output functionality. This is the first step to sequential circuit synthesis.
Suppose that the state transition table, Table 3, is given.
State reduction can be carried out by several methods: (1) by
inspection, (2) by partition, and (3) by using an implication
table (1,2). By inspection, for input x 0 and x 1, states E
and F go to the same state, E and C, respectively, and the
outputs for the two cases are also the same at 0. Then the
two states E and F are equivalent. Further reduction of the
number of states, however, is not obvious by an inspection. As
for the systematic methods useful in such cases, the partition
method is referred to in the references, and a versatile and
simple implication table method is briefly summarized here.
To display the equivalent/nonequivalent relationship of a
pair of internal states, we make a diagram by stacking the
boxes, as shown in Fig. 8. If two internal states are equivalent, the sequential circuit must generate the same output(s)
for all the combinations of the input variable values. Any pair
of internal states having at least one different output for a
combination of inputs are not equivalent. The box at the column index B and the row index D, for instance, contains an
indicator since the two internal states are not equivalent
by this criterion. Most of the boxes get marks, and the internal state pairs are removed from further consideration.
This table is called an implication table because of the internal states A through G, there can be internal states that are
equivalent but are named by different symbolic indicators.

B
C
D
E

(E,F)

(E,F)

E=F

A NEW LOOK AT SEQUENTIAL LOGIC CIRCUITS

(A,F)
A

Some of them are equivalent if the following situation occurs:

If internal states A and E are to be equivalent, the internal
states E and F must be equivalent for x 0. As for x 1, the
equivalence condition is already satisfied by the same internal state C. The equivalency requirement of internal states A
and F (namely, E F) is written in the box at column A and
row E, by a sign (E,F). Since internal E and F being equivalent implies internal states A and E being equivalent, the table is called an implication table. If the same procedure is
repeated for the other empty boxes, that internal states A and
E and internal states C and G are equivalent is implied by E
and F and A and F being equivalent, respectively. The equivalence of states E and F is already established by inspection
and is indicated by E F.
Since states E and F are equivalent, the completed implication table shows that states A and E are equivalent, and
states A and F are also equivalent. Then internal states C
and G are also equivalent. The original seven states are
grouped into equivalent states (A,E,F), B, (C,G), and D. The
seven-state table is simplified to the four-state table shown in
Table 4. Obviously, the circuit having four states is easier to
implement than the circuit having seven states, yet the two
implementations are functionally equivalent. Since m memories create a maximum of 2m internal states, the number of
the memories is reduced from 3 to 2 by the reduction process.
Synthesis of a sequential circuit having the specified functionality begins with conversion of the requirement in the
common language into a state transition table or diagram. In
this phase of the work the states carry symbolic names, such
as A, B, C. The state transition table is then examined by the
procedure described in this section if the equivalent states
can be found, and if the total number of states can be reduced,
to make the circuit simpler. In the next step the binary numbers are assigned to each state A, B, C, . . ., such that the
circuit is race free. Then, using the simplified and the stateassigned transition table, the logic function tables for the
combinational logic circuit, which creates the required output
(z1, z2, . . .), and the next internal states (Y1, Y2, . . .) from
the inputs (x1, x2, . . .) and the present state (y1, y2, . . .) are
set up. The required combinational circuits are then synthesized using the standard technique (1,2) and they are integrated with the memory circuit. This process completes the
synthesis procedure.

Figure 8. Implication table to find equivalent states.

Synchronous sequential circuits have the merits of easily understood operation, simple and systematic design procedure,
efficient use of combinational hardware, ability to carry out
varieties of operation by adding small amounts of logic gates

198

SERVOMECHANISMS

and control signals (as in the processor datapath), and easy

interfacing to the external circuits that have the same systemwide clock signal. These merits of synchronous sequential
circuits are especially advantageous to the large-scale integrated circuit environment, and they have been the driving
force of the rapid growth of microprocessor technology. Although these advantages will be exploited actively in the future, there are other advantages of synchronous sequential
circuits that are clearly visible (e.g., ultra-high-speed electronics from the electronic circuit theorists viewpoint).
The basic structure of the synchronous sequential circuit
shown in Fig. 1 using the edge-triggered master-slave D-latch
pair allows us, conceptually, to cut the circuit loop open between the master and slave latches. Then the slave latch provides the digital information to the combinational circuit, and
the master latch receives the information processed by it. A
digital signal is an object, very similar to an elementary particle in quantum mechanics, and the slave latch-combinational
logic-master latch combination is equivalent to a measurement setup to determine the velocity of the pseudoparticle
that carries the digital information. We note here that the
quantum mechanical nature of the digital circuit originates
from the impossibility of setting a clear threshold voltage that
distinguishes the Boolean HIGH and LOW levels. Since the
threshold voltage is uncertain, or hidden from the digital circuit theory, the digital circuit becomes a quantum mechanical
object, very similar to what has been envisioned by Einstein,
Podorsky, Rosen (4), and Shoji (6).
From this viewpoint a new idea of increasing the speed
of digital signal processing to the limit emerges. By properly
choosing the circuit between the latches, the quantum mechanical information-carrying particle can be transferred by
the equivalent to the quantum mechanical tunnel effect,
which takes, in its purely physical model, a short time. This
new viewpoint suggests that the combinational circuit between the two latches need not be constructed from logic
gates, but can and should be constructed from varieties of circuits including analog circuits. It is my belief that the advantage of a synchronous sequential circuit originates from its
basic structure, the pair of information source and observation setup. The structure, once considered as the basic quantum mechanical arrangement, should be able to provide the
fastest circuit we can build, yet it satisfies the basic requirement of digital circuitsthe step function signal format
generated by clocked latches. From this viewpoint a sequential circuit will be a rich source of research in future electronic
circuit theory.
The quantum mechanical nature of a digital signal shows
up most clearly when, against the circuit designers intention,
a narrow isolated pulse is generated, or a simple step function
waveform is converted into a multiple transition, a wavy step
function wavefront during the combinational logic operation.
The narrow isolated pulse is called a static hazard, and the
multiple transition step function a dynamic hazard (3). A hazard is an essential mode of operation of a combinational logic
circuit built from gates having nonzero delay, and this is clear
from the following example. Suppose that a synchronous sequential circuit includes a NAND gate, whose two inputs A
and B were the HIGH and the LOW logic levels, respectively.
The output is at the default HIGH level. After the slave
clocktick, the step function signal fronts arrive sometime
later at A and B to make a HIGH to LOW transition at input

A and a LOW to HIGH transition at input B. After the transitions are over, the output of the NAND gate is at the same
HIGH logic level as before. The problem is that the timing
relation of the wavefront is not always subjected to the control of the designer. If the LOW to HIGH transition of the B
input occurs earlier than the opposite polarity A input transition, both inputs of the NAND gate become temporarily
HIGH, and the output of the gate is a temporarily LOW logic
level. A downgoing isolated pulse whose width is the time between the input B transition to the input A transition is generated. Hazard is an unexpected and unwelcome guest to a
circuit designer, and it is significant in state-of-art high-speed
CMOS logic circuits. One way to describe a high-frequenty
logic circuit operation is as a continuous sequence of generation and erasure of hazard pulses. The hazard pulse is usually
narrow, and it may or may not be wiped out as the signal
further propagates the gate chain. Some hazard features survive and arrive at the destination latch. The latch is the final
measure to screen all the extra features of the step function
front, by cleaning up the deformed pulse from the combinational circuit at the clocktick. This function is an elementary
intelligent function of a digital circuit, and thus the synchronous logic circuit does have the minimum required and fundamentally necessary features of intelligent signal processing.
That is why the circuit is so widely used. In an asynchronous
sequential circuit, this function is distributed over the circuit,
and this confuses the issue.
BIBLIOGRAPHY
1. H. T. Nagle, Jr., B. D. Carroll, and J. D. Irwin, An Introduction to
Computer Logic, Englewood Cliffs, NJ: Prentice-Hall, 1975.
2. M. M. Mano, Digital Design, 2nd ed., Englewood Cliffs, NJ: Prentice-Hall, 1991.
3. E. J. McCluskey, Logic Design Principles, Englewood Cliffs, NJ:
Prentice-Hall, 1986.
4. D. Bohm, Quantum Theory, Englewood Cliffs, NJ: Prentice-Hall,
1951.
5. M. Shoji, Theory of CMOS Digital Circuits and Circuit Failures,
Princeton: Princeton Univ. Press, 1992.
6. M. Shoji, Dynamics of Digital Excitation, Norwell, MA: Kluwer,
1998.

MASAKAZU SHOJI
Bell Laboratories

SEQUENTIAL CIRCUITS AND FINITE STATE AUTOMATA, TESTING. See LOGIC TESTING.
SERVICES, HOME COMPUTING. See HOME COMPUTING SERVICES.

400

SMOOTHING CIRCUITS

of constancy do not exist, although expensive laboratory

power supplies strive to approximate them.
When any electronic circuit is incorporated into end-use
equipment, the available dc supply has imperfections that can
interfere with the proper operation of the circuit. A realistic
model of a practical dc voltage supply is shown in Fig. 1. It
comprises an ideal dc voltage source Vdc, an alternating current (ac) voltage source vr(t) that represents superimposed
ripple, and a generalized series impedance Zs, which represents the supplys internal impedance and that of wires, PCB
traces, and connections. In the ideal case, vr(t) and Zs are both
zero, but they take on nonzero values for a real supply. In a
typical power supply, the dc source Vdc ultimately derives
from a wall plug or similar electric utility line source with its
own variations.

What is Smoothing?
It is possible to design an electronic circuit to withstand some
variation at the dc supply. However, high-performance circuits such as audio amplifiers or precision sensors require a
supply of the highest possible quality, and almost any design
can benefit from a clean supply. The concept of a smoothing
circuit is to add extra elements to Fig. 1 to provide an equivalent dc output that approaches the ideal. A smoothing circuit
provides an interface between the nonideal supply and the
intended electronic load. In power supply practice, it is usual
to distinguish between a smoothing circuit, which has the
primary function of eliminating effects of the ripple voltage
vr(t) and the source impedance Zs, and a regulation circuit,
which has the primary function of enforcing a constant Vdc.
However, many smoothing methods incorporate regulation
functions.
Smoothing can take the form of a passive circuit, constructed mainly from energy storage elements, or an active
circuit that corrects or cancels supply variation. Both of these
major topics are discussed in this article. We begin with definitions, then consider fundamental issues of smoothing. Following this, we present passive smoothing methods in depth.
Active smoothing methods are described after passive
methods.
It is important to point out that an ideal dc voltage supply
is not the only possibility for circuit power. In a few cases, an
ideal dc current supply or a specific ideal ac supply is needed
instead. The reference materials provide additional information about smoothing of current sources and ac supplies.

Ls

SMOOTHING CIRCUITS
Most electronic circuits are designed to operate from a perfect
constant-voltage direct-current (dc) supply. This is often
shown on a schematic diagram as VCC, VDD, or 12 V, for instance. Ideally, the supply voltage would remain constant
despite all disturbances: It would never show any spikes,
ripples, or variations of any sort. It would not change in the
face of variations at its input, and it would not be altered no
matter how high the load current. In practice, such paragons

vr(t)

Rs

Zs

Smoothing
circuit

Load

Vdc

Imperfect dc supply

Figure 1. Model of an imperfect dc supply, smoothing circuit and

load.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

SMOOTHING CIRCUITS

Definitions

Peak-to-peak supply voltage excursion

r=
Average voltage

(1)

If vr is sinusoidal, with vr(t) Vpk cos(r t), then the ripple

factor is r 2Vpk /Vdc. An oscilloscope can be used in ac-coupled mode to measure the numerator of Eq. (1), and a dc voltmeter can measure the denominator. The ripple factor should
be as small as possible.
A smoothing circuit should provide a lower value of r at its
output than at its input. This is the basis for an important
figure of merit.
Ripple attenuation is the ratio of the smoothing circuits
input ripple voltage to its output ripple voltage. It is often
expressed in decibels:

Ripple attenuation
= 20 log10

Rs

Ls

The following definitions are in common use.

The ripple factor r provides a measure of the ripple voltage
vr relative to Vdc. It is usually defined in terms of peak-to-peak
variation:

Peak-to-peak voltage excursion at input

Peak-to-peak voltage excursion at output


(2)

The ripple attenuation should be as large as possible.

When a smoothing circuit is not present, the output impedance of a power supply is the source impedance Zs. Therefore,
output impedance provides a second helpful figure of merit.
The objective is to provide as low an impedance as possible
over a wide frequency range.
The end-use application has certain important measures
as well. The sensitivity of the load to supply variation is measured in terms of power supply rejection.
The power supply rejection ratio (PSRR) is a measure of the
ultimate effect of supply variation at the point of end use.
Given a final output voltage magnitude VO and power supply
ripple voltage magnitude Vr, the rejection ratio is given by
Power supply rejection ratio = 20 log10 (VO /Vr )

(3)

Here VO is that portion of the output voltage that is related

to supply ripple (excluding signals, random noise, and other
disturbances). The PSRR value should be as high as possible.
The frequency of the ripple waveform is important for
smoothing circuit design.
The ripple frequency is defined as the fundamental frequency of the ripple waveform, whether or not the waveform
is sinusoidal. In many cases, the ripple frequency is a multiple of the ac line frequency that provides the energy. In
switching power supplies, the ripple frequency is usually
much higher.
Example: Amplifier Load
Figure 2 shows an inverting amplifier supplied from a nonideal source, and will serve to illustrate the need for smoothing. In the case of a perfect voltage source with vr(t) Zs
0, the amplifiers intended output voltage is VO gmRVi,
where gm is the transistors transconductance. However, the
supply ripple voltage feeds directly through R to the output,
and it modifies the output voltage to VO gmRVi Vr. The

401

A
Vr

Zs

R
V0
g mV i

Vi

Vdc

Imperfect dc supply

Amplifier

To other
circuitry

Figure 2. Imperfect dc supply feeding a simple amplifier and other

circuitry.

circuit in Fig. 2 is poor in this respect. Its PSRR is unity, or

0 dB, and therefore it relies entirely on smoothing within the
power supply for its function. Well-designed amplifiers, such
as IC operational amplifiers, can have PSRR levels of 60 dB
or greater.
Furthermore, the imperfect dc supply has impedance Zs,
which appears in series with R, so the output voltage becomes VO gm (R Zs)Vi Vr. Since Zs most likely depends
on frequency, the amplifiers frequency response (the variation of VO /Vi with frequency) is no longer flat. In addition, an
alternating-current (ac) voltage develops across Zs, equal to
gmZsVi. If another circuit is powered from points A and B in
Fig. 2, considered as dc supply rails, this extra ac voltage appears as superimposed ripple. Thus the supply impedance Zs
provides a mechanism by which signals in one circuit can couple into another. Under certain conditions, the cross-coupling
can be strong enough to produce large-amplitude, self-sustaining oscillations.
A remedy for the impedance and cross-coupling effects is
to connect a large capacitor between A and B. This is known
as decoupling the circuits from each other. A large capacitor
means one with impedance ZC 1/(C) that is much smaller
than the impedances R and Zs at all frequencies of interest.
The idea is that the signal current in R should flow mostly
through C rather than Ls. It will then develop a small voltage
of approximately gmVi /(C) between points A and B. When
Rs is small, a ripple current of approximately Vr /(Ls) will
flow through Ls and C; this current will produce a ripple voltage Vr /(2LsC) between A and B. The larger the value of C,
the smaller the unwanted voltage gmVi /(C), and the better A
and B approach ideal voltage rails. Higher values of Ls will
also help reduce the ripple voltage between A and B once a
capacitor is present. Rather than being an unwanted element,
the source inductance becomes useful. In fact, extra inductance might be added in series to increase the smoothing
effect.
This example shows the basis of a general passive smoothing circuit: Ls and C form a second-order low-pass filter between the ripple voltage source and the amplifier circuit. The
filter passes dc unaffected. Well above the cutoff frequency of
the filter at approximately the resonant frequency, 0
1/ LC, ripple is attenuated by about 40 dB/decade.
SMOOTHING FROM AN ENERGY PERSPECTIVE
Before discussing practical smoothing techniques, we look at
power and energy relations, which define fundamental physical limitations associated with smoothing.

402

SMOOTHING CIRCUITS

Power and Energy

Let work or energy be denoted as a function w(t). Instantaneous power is the rate of change of energy, p(t) dw/dt.
The first law of thermodynamics states that energy is conserved: w constant, and after differentiating we obtain
(dw/dt) 0. Therefore, the energy supplied to a system
must match the energy output, plus any energy that is stored
internally. In terms of power, we can identify a power balance
equation:

d

pout (t)
pin (t) =
wstored +
dt

dw
+ pH (t)
dt

(5)

d(W + w)

+ (PH + p H )
dt

1
T

(7)

By definition, the ripple components have zero average, so the

long-term result is
PI = PO + PH

(8)

pH
i0
+
vI pI

Internal stored
energy w

+
p0 v0

Figure 3. Power flows and energy in a smoothing circuit.

Internal energy storage is used in smoothing circuits such as

LC filters, which in theory can be 100% efficient. There are
only two basic ways of storing energy in a circuit: electrically
and magnetically. A capacitor provides electric storage based
on its stored charge, q CV. The derivative of this for constant capacitance provides the familiar property i
C(dv/dt). At any point in time, the power into the device is
v(t)i(t), and the capacitive stored energy is

wC (t) =

v(t)i(t) dt =
0

v(t)C
0

dv(t)
dt =
dt

Cv dv =
0

1 2
Cv (t)
2
(10)

The other way of storing energy is in a magnetic field. An

inductor provides magnetic flux linkage in its core proportional to the current i flowing in a coil around the core, with
Li. The time derivative of this for constant inductance,
combined with Faradays law by which d /dt is equivalent to
voltage, gives the conventional property v L(di/dt). The
same procedure as for the capacitor yields the inductive
stored energy:
wL (t) =

p(t) dt

Nondissipative Smoothing

(6)

Since W is constant, an immediate simplification is that the

dW/dt term is zero. Furthermore, we are interested in the
long-term average power flows:
P = lim

(9)

The aim of smoothing is to make pO close to zero. We can try

to accommodate the input ripple power either by a change in
stored energy, by dissipation, or by a combination of these.

So, in general, the power entering a smoothing circuit at any

instant undergoes a three-way split: Some power leaves via
the electrical output, some increases the internal stored energy, and the remainder is dissipated as heat. This power balance equation identifies two techniques available for realizing
smoothing circuits: energy storage and dissipation. Both will
be considered shortly.
Let pI(t) PI pI(t), where PI is a constant (dc) term and
pI(t) is the ripple component (ac term), and similarly for the
other variables. The power balance equation becomes
(PI + p 1 ) = (PO + p O ) +

dw
+ p H
dt

p I = p O +

(4)

That is, the total power flowing into any system equals the
total power flowing out, plus the rate of change of internally
stored energy.
In a typical electronic system, there are unwanted losses
that constitute an output heat flow, and it is convenient to
consider this heat output separately. Figure 3 shows a
smoothing circuit that has instantaneous input power pI(t),
electrical output power pO(t), internal energy storage w(t), and
heat output power (losses) pH(t). The power balance equation
for this circuit is
pI (t) = pO (t) +

This average power balance equation leads to the definition

of efficiency, PO /PI that is, the ratio of average output
power to average input power, usually expressed as a percentage. An important design aim of a smoothing circuit should
be to attain a high efficiencythat is, approaching 100%.
If we take the full-power balance equation and subtract
the average-power balance equation, we arrive at the ripplepower balance equation:

1 2
Li (t)
2

(11)

Capacitance and inductance are electric duals: An expression concerning capacitance can be transformed into an expression about inductance by swapping the roles of v and i
and then replacing C by L and q by . For a capacitor we can
write dv/dt i/C, so the larger the value of C, the smaller
the rate of change of voltagethat is, the more constant the
voltage remains. For an inductor we can write the dual expression di/dt v/L. From an energy storage perspective, we
deduce that capacitors act to maintain constant voltage; inductors act to maintain constant current.
With finite capacitance and inductance, true constancy
cannot be achieved. The basis of nondissipative smoothing circuits is to alternate capacitors and inductors, progressively
smoothing voltage and current in turn.
Figure 4(a) shows an input power with sinusoidal variation. Nondissipative smoothing circuits attempt to store ripple energy during the high parts of the cycle, and then they
dispense this energy during low parts of the cycle to smooth
the overall flow. The available power becomes PI, the dashed
line in Fig. 4(a).

SMOOTHING CIRCUITS

403

The highest possible efficiency PO /PI gives

Power

pI(t)

PH

PI

;;;;;
(a)

Waveform Considerations and Frequency-Domain Analysis

The implications of ripple factor, regulation, and many measures of smoothing performance depend on the nature of the
ripple waveform. Ripple waveforms in conventional power
supplies can be sinusoidal or triangular, or they can take the
form of narrow spikes. We can consider ripple as a periodic
signal with a particular spectrum and then apply frequencydomain analysis. Formally, we represent a ripple signal vr(t)
by its Fourier series,

Power

Power here must

be dissipated

Minimum possible
value of PH
t

vr (t) = a0 +

Figure 4. Hypothetical ripple power waveform. In (a), average

power PI is available with nondissipative smoothing. In (b), dissipative smoothing delivers a lower value.

Dissipative Smoothing
Dissipation is used in circuits such as linear voltage regulators and linear active smoothing filters. These devices are inherently less than 100% efficient. Their basic operation is to
enforce constant output power by treating ripple as excess
energy.
Recall the ripple-power balance equation,
(12)

If there is no stored energy, the term dw

/dt is zero. The objective of pO 0 can be achieved only if we make pH pI that
is, if we convert all the input ripple power into heat power
(loss). The lost energy is actually higher than this, and we
should consider the implications for efficiency. Consider again
an input power with ripple as in Fig. 4(a). Suppose pI(t) has
a maximum downward excursion PH; this means that the
total heat power pH(t) has a minimum value of PI PH. By
the second law of thermodynamics, this value must be positive: Heat power always flows out of the circuit (excluding
heat engines). This forces us to set a positive value of PH to
account for correct heat flow. The implications can be seen in
Fig. 4(b). Here the value of PO is set as high as possibleto
the minimum of the input power excursionand all power in
the shaded region must be thrown away as heat to meet the
zero pO objective. Since PH is positive in a dissipative smoothing circuit, the efficiency is less than 100%.
In a case with sinusoidal ripple power, such that pI(t)
PI pi cos(t), the highest output power with pO 0 will be
PO = PI pi

an cos(nt) + bn sin(nt)

(15)

n=1

(b)

dw
+ p H
p I = p O +
dt

(14)

Recall that nondissipative smoothing circuits cannot achieve

zero ripple with finite component values. Although dissipative
smoothing circuits can never achieve 100% efficiency, they
can achieve zero ripple, in principle.

Maximum possible
value of P0

pi
PI

(13)

where the radian frequency is related to the frequency f

and the time period T of the signal as 2f 2/T. The
time function a1 cos(t) b1 sin(t) is defined as the fundamental of ripple, while terms at higher values of n are harmonics. Because most smoothing filters have a low-pass nature, they attenuate the harmonics more than the
fundamental. For design purposes, it is often sufficient to consider the gain at the fundamental ripple frequency, r.
Consider input and output voltage phasors taken at this frequency. We will express the gain in decibels:


 V ( jr ) 

Gain (dB) = 20 log10  O
VI ( jr ) 

(16)

For arbitrary complex frequency s, the transfer function can

be written as
A(s) =

VO (s)
VI (s)

(17)

PASSIVE SMOOTHING FILTERS

Let us now approach the design of passive filters for smoothing. In principle, smoothing filters might be designed like the
low-pass filters employed for signal processing (1,2). But unlike signal filters, where existing source and load impedances
can be augmented with resistance to the desired value,
smoothing filters must avoid resistance wherever possible in
the interest of efficiency. Therefore they generally have illdefined source and load impedances, and standard low-pass
filter tabulations are inapplicable except in special circumstances.

404

SMOOTHING CIRCUITS

consider the situation with an input voltage source and a current-source load. When fed from a voltage source vI and delivering an output current IO, the filter output voltage is vI
IOR, and its efficiency is

VI(t)
Smoothing
circuit

Load

Figure 5. Diode bridge with output smoothing filter and load.

To illustrate the point, consider a smoothing filter fed from

a diode-bridge rectifier, as shown in Fig. 5. The rectifiers effective output impedance is not clear, and in fact it can vary
considerably, even within a cycle. Even the basic circuit action is unclear, since the timing of diode turn-on and turn-off
will depend on the smoothing circuit and the load. Conventional circuit theory is difficult to apply in such circumstances.
In almost any practical smoothing application, the dynamic characteristics of the load are unknown or poorly defined. Given a dc load specified as drawing current I at voltage V, one might assume a resistive load, with R V/I. In
reality, this may not be the case: At one extreme, the load
could approximate a constant current of I (a linear voltage
regulator tends to behave this way); at the other it might approach a constant voltage of V (a battery to be charged is one
common case). In between, the load could be resistive, capacitive, or inductive, with the possibility of nonlinear behavior
or time variation. If information about the source and load
impedances is available to the filter designer, it should be utilized. Otherwise, assumptions must be made, with an attempt
toward worst-case analysis.

1
1 + sCR

The simplest type of passive smoothing filter is the singlesection RC low-pass filter of Fig. 6(a). This is widely used for
decoupling purposes at low power levels, where its limited efficiency is not a concern. For this filter, worst-case design can

I0

VI

(19)

The gain at the ripple radian frequency r is

Gain (dB) = 20 log10

1 + (rCR)2

20 log10 (rCR)

if rCR  1

(20)

The one-section filter has a corner frequency at 0 1/(RC),

and the gain falls asymptotically (i.e., for 0) at 20 dB/
decade, or 6 dB/octave. Thus, with R selected on efficiency
grounds, the value of C is chosen to give the desired attenuation of the fundamental ripple frequency.
Two or more RC networks can be cascaded to form a multisection filter, as in Fig. 6(b). A two-section filter, with each
section comprising R/2 and C/2, provides
A(s) =

1
1+

The gain is

Gain (dB) = 20 log10

RC Smoothing

(18)

The value of R should be chosen to give an acceptable efficiency. The voltage gain transfer function is
A(s) =

IO R
VI

=1

3
4 sRC

1+

(21)

1
2
16 (sRC)

7
2
16 (r RC)

24 40 log10 (r RC)

1
4
256 (r RC)

if r RC  1

(22)

The corner radian frequency is 0 4/(RC), and the gain falls

asymptotically at 40 dB/decade or 12 dB/octave. A three-section filter, with R/3 and C/3 in each section, has
A(s) =

1
1 + 23 sRC +

5
2
81 (sRC)

1
3
729 (sRC)

(23)

V0

and gain of

Gain (dB)

(a)

= 20 log10
R/2

VI

R/2

C/2

1+

26
(r RC)2
81

57 60 log10 (r RC)

I0

C/2

V0

(b)
Figure 6. RC smoothing filters, single section and multisection.

13
(r RC)4
6561

if r RC  1

1
(r RC)6
531,441

(24)

The corner frequency is now 0 9/(RC), and the gain falls

at 60 dB/decade or 18 dB/octave. It is rare to encounter more
than three sections in practice. The efficiency of these multisection filters depends only on the total resistance R, so it is
the same as for a single section.
We can represent the gain conveniently with a Bode plot,
which shows gain in decibels as a function of frequency (on a

SMOOTHING CIRCUITS

log scale in hertz) over the range of interest. The Bode plots
in Fig. 7 represent RC filters with one to three sections.
Given a total resistance R and a total capacitance C, what
is the best number of sections to use? For n sections, the corner frequency is proportional to n2, while the slope of the high
frequency asymptote is 20n dB/decade. A two-section filter
gives greater attenuation than one section if rRC 12.0;
otherwise it is more effective to use one section. Similarly,
three sections are better than two if rRC 32.9 (with analysis based on the fundamental). When deciding on the number
of sections, practical factors should also be taken into account,
such as availability of suitable components, their size, cost,
PCB area occupied, and the effect upon reliability.
As an example, let us consider the design of a filter with
the following specifications: VI 12 V, IO 10 mA, 98%,
f r r /(2) 120 Hz, gain 30 dB. From the efficiency
formula, Eq. (18), we find R 36 . Using the approximate
gain formulae, we obtain the following values:
n

rRC

Practical Component Values

1
2
3

31.62
22.39
28.18

1165 F
825 F
1038 F

36 , 1200 F
2 18 , 2 470 F
3 12 , 3 330 F

The two-section filter might be considered the best because it

has the lowest value of rRC and therefore the lowest total
capacitance. But a single-section filter is simpler, and it might
be the preferred design solution in practice.
There are more sophisticated RC smoothing circuits (3,4),
including the parallel T notch network (4,5). These were used
in the past when low ripple was essential. Today, active
smoothing methods are a better alternative to these rather
sensitive circuits.
LC Smoothing
Single-stage and two-stage LC smoothing filters are shown in
Fig. 8. For these filters, the efficiency is 100% in principle,
although in practice it will be limited by parasitic resistances
within the components. For the single-stage circuit, the voltage gain transfer function is
A(s) =

1
1 + s2 LC

(25)

I0

VI

V0

(a)

L/2

VI

L/2

I0

C/2

C/2 V0

(b)
Figure 8. LC smoothing filters, single section and multisection.

The gain is
Gain (dB) = 20 log10 |1 r2 LC|

Gain (dB) = 20 log10 |1 (r /0 )2 |

40 log10 (r /0 )

if r /0  1

(27)

It is essential that the resonant frequency be significantly

lower than the ripple frequency; otherwise, the filter could
actually increase the ripple.
When two LC networks are cascaded to form a multisection filter, additional resonances are created, and it becomes
even more important to ensure that 1/ LC is well below the
ripple frequency. The two-section filter with component values L/2 and C/2 has the transfer function
A(s) =

1
1 + 34 s2 LC +

1
2
2
16 (s LC)

(28)

The gain is
1
(r2 LC)2 |
16

(29)

With 0 1/ LC once again, the gain becomes

Gain (dB) = 20 log10 |1 34 (r /0 )2 +

Gain (dB)

(26)

The LC product is associated with a resonant frequency 0

1/ LC. With this in mind,

Gain (dB) = 20 log10 |1 34 r2 LC +

20

24 80 log10 (r /0 )

1 section
2 sections
3 sections
40

60
0.01

405

0.1
1
10
Frequency 2 RC

100

Figure 7. Frequency response for multisection RC filters.

1
(r /0 )4 |
16

if r /0  1

(30)

The filtering effect as frequency increases is much larger than

for a two-section RC smoother. However, the frequency behavior is more complicated, having two resonant peaks. A
Bode diagram for one-, two-, and three-section LC filters with
no load is shown in Fig. 9. For the single-section filter, the
ripple frequency must be at least 2 times the resonant frequency to ensure some reduction. Frequencies more than
about five times the resonant value are strongly attenuated.

406

SMOOTHING CIRCUITS

Gain (dB)

I0
VI

50

C0

1 section
2 sections
3 sections

V0

Figure 10. LC filter with blocking pair.

100

10. This combination blocks all flow at 0 1/ LC. The

transfer function is

150
0.01

0.1

10

100

Frequency 2 LC

A(s) =

Figure 9. Frequency response for multisection LC filters.

For the two-section filter, the ripple will increase without

bound if the ripple frequency is 1.23 or 3.24 times the resonant frequency 0 1/ LC, but again the filter is effective if
the ripple value is at least five times the resonant value. The
two-section filter gives better results than the single-section
filter provided that rLC 5.2. The three-section filter has
peaks near 1.340, 3.740, and 5.410, and it is better than
the two-section filter only if rLC 8.8. The resonance
problems make even the three-section filter rarely used for
smoothing except at extreme power levels (several kilowatts
or more).
The gain parameters for Fig. 9 depend only on the LC
product, but do not give guidance on the selection of L and
C. One general rule is to choose rLC 5. A second requirement can be generated based on the impedance needs of an
ideal dc supply: The output impedance should be much lower
than the load impedance. This implies that the impedance of
the capacitor across the output terminals should be much
lower than the effective load impedance, ZL. The single-section LC filter thus requires
1
1
 |ZL | or C 
rC
r |ZL |

(31)

In the preceding RC example, the load draws 10 mA from a

12 V source. The effective load impedance is 12 V/10 mA
1200 . For a single-stage LC filter with ripple frequency of
120 Hz, this requires C 1.1 F. A value of 100 F will be
suitable. With the resonance requirement rLC 5, we find
L 0.44 H.
The actual performance of LC smoothing circuits is closely
linked to the quality of their components. Any real inductor
or capacitor has its own internal equivalent series resistance
(ESR). In smoothing circuits, ESR values are often not much
different from the intended filter component impedance levels. For example, ESR in the output capacitor of an LC network can limit the ability to provide low output impedance.
Discussion of the nature of ESR and its effect on filters can
be found in Ref. 2.
LC Blocking and Traps: Resonant Smoothing
Since the ripple frequency is well-defined in many systems,
there are certain circumstances in which resonance can be
used to advantage. Consider the series blocking circuit of Fig.

1 + s2 LC
1 + s2 L(C + CO )

(32)

At high frequency, A(s) C/(C CO), so the design requires

CO C to give useful high-frequency attenuation. The unwanted high-gain resonance then occurs at a relatively low
frequency 1/ L(C CO). If LC 1/r2 and CO 10C, this
combination will give excellent ripple attenuation at r, and
more than 20 dB of attenuation at higher frequencies. As in
the basic LC filters, the value of CO is chosen to provide a low
output impedance.
Consider again the previous power supply example with
1200 load impedance. With a blocking filter, it is likely that
the largest remaining ripple component will appear at 3f r, or
360 Hz. An output capacitor value of 5 F will make the impedance sufficiently low at this frequency. This suggests a capacitor value of 0.5 F for the blocking pair. The inductor is
selected based on 1/ LC 240 rad/s, giving L 3.5 H.
Blocking filters are most useful when specific high frequencies
are involved, rather than power line frequencies. A similar
design procedure to block 20 kHz ripple in a switching power
supply will lead to a smaller inductor.
Figure 11 shows a shunt trap filter. In this case, the load
will not see any ripple at the single frequency 0 1/ LC
except owing to component ESR values. The transfer function
is
A(s) =

1 + s2 LC
1 + s2 (L + LI )C

(33)

At very high frequency, A(s) L/(L LI), so the circuit

should have LI L to provide good high-frequency attenuation. This circuit acts as the dual of the blocking circuit. The
impedance of the inductor LI should be much higher than that
of the load to prevent flow of unwanted frequencies. Like
blockers, traps are used to eliminate specific high frequencies.
In high-power supplies, traps are often used to eliminate particular strong harmonics rather than for broad ripple smoothing. Additional discussion of tuned traps can be found in
Ref. 6.

LI
VI

I0
L

V0

C
Figure 11. LC filter with a trap.

SMOOTHING CIRCUITS

1,1

This decay will continue as long as the diodes are reversebiased, that is, vO vI. When the full-wave voltage increases
again during the next half-cycle, two diodes will turn on at
time ton as the full-wave value crosses the decaying output.
The output voltage maximum is the peak input Vpk, while the
minimum output occurs at the moment of diode turn-on, ton.
Thus the peak-to-peak output ripple is Vpk vI(ton). To guarantee small ripple, the output voltage should decay very little
while the diodes are off. This means ton toff to keep the
ripple low. For small ratios of (ton toff )/ , the exponential can
be represented accurately by the linear term from its Taylor
series expansion,

1,2
C

vI(t)

2,1

2,2

V0

To load
Figure 12. Full-bridge rectifier with capacitive filter.

ex 1 + x,

Capacitive Smoothing for Rectifiers

A rectifier can be used with a purely capacitive smoothing
filter. With a resistive load, the structure becomes an RC combination of the filter element and the load. This arrangement,
shown in Fig. 12, is sometimes called the classical rectifier
circuit. It is very common for filtering rectifiers below 50 W,
and it is used widely at higher power ratings as well.
In the classical rectifier, the shape of the ripple combines
a sinusoidal portion during times when the diodes conduct,
and an exponential decay during times when the diodes do
not conduct. The nature of the waveform supports useful approximations to the shape without resorting only to the fundamental frequency (6). The circuit output waveforms are
given in Fig. 13. The waveform vI(t) is shown as a dotted line
for reference. When a given diode pair is on, the output is
connected directly, and vO vI. When the diodes are off, the
output is unconnected, and vO decays exponentially according
to the RC time constant: assuming a resistive load, R. Consider the time of the input voltage peak, and assume that the
diodes labelled 1,1 and 2,2 are on. In this arrangement, the
output voltage matches the input apart from the diode forward drops (which are assumed to be small for the moment)
and the input current is iI iC iR. The arrangement will
continue until the diode current drops to zero and the devices
turn off. This time toff occurs shortly after the voltage peak,
and the time of the peak is a good approximation to the turnoff point.
Once the diodes are off, the output decays exponentially
from its initial value. The initial voltage will be vI(toff ), and
the time constant will be the RC product, so
Diodes off:

vO (t) = Vpk sin Itoff e(tt off )/

Voltage

Vpk

(34)

TI/2

TI

3TI/2

Time
Figure 13. Output voltage of classical rectifier.

x1

(35)

The time difference ton toff cannot be more than half the
period of vI(t), so the low ripple requirement can be expressed
as RC TI /2 if TI is the input period.
The details of the output voltage waveform and the target
of having low ripple lead to several reasonable assumptions
that can be made for the smoothing filter, leading in turn to
a simplified design framework:
1. The turn-off time occurs close to the voltage peak. It can
be assumed to coincide with the peak input voltage, and
the output voltage at that moment will be Vpk.
2. The voltage decay while the diodes are off is nearly linear, as in Eq. (35). Thus after toff , the voltage falls linearly as Vpk(1 t/RC), with t being measured from the
voltage peak.
3. Since the total time of voltage decay never exceeds half
the period (for the full-wave rectifier case), the voltage
will not be less than Vpk[1 TI /(2RC)]. The peak-topeak ripple VO will be no more than VpkTI /(2RC).
4. The diodes are on just briefly during each half-cycle.
The input current flows as a high spike during this interval. Given a turn-on time ton, the peak input current
is approximately C(dv/dt) CVpk cos(Iton).
All these simplifications require RC TI /2, the usual case
to produce low ripple.
These simplifications are equivalent to assuming that the
output waveform is a sawtooth, with a peak value of Vpk and
a trough value of Vpk[1 TI /(2RC)]. Therefore, the ripple is
also a sawtooth, with a peak-to-peak value of VO
VpkTI /(2RC). This shape yields a simple design equation.
Given an output load current IO (approximately equal to
Vpk /R if the load is resistive), a desired ripple voltage VO,
and input frequency f I 1/TI, we have
VO =

Vpk/2

407

IO
,
2 f IC

or C =

IO
2 f I VO

(36)

The capacitance is selected based on the highest allowed load

current. Notice that if a half-wave rectifier substitutes for the
bridge, the basic operation of the circuit does not change, except that the maximum decay time is TI instead of TI /2. The
factors of 2 in Eq. (36) will not be present.
The sawtooth waveform can be filtered further by connecting an LC or RC passive circuit after the smoothing capacitor.
Sawtooth ripple with a peak-to-peak value of VO corresponds

SMOOTHING CIRCUITS

iI

120:10
+

V0

Output voltage (V)

120 V
60 Hz

18

36

12

24

12

0
v0(t)

12

vI (t)
iI(t)

12

Input current (A)

408

24

Figure 14. Circuit to provide 12 V output from a smoothed rectifier.

18

0.005

to a ripple waveform fundamental of

VO
sin r t

(37)

and this VO / amplitude provides a good basis for design of

further filtering.
The capacitor handles a substantial ripple current, and
this should be considered when choosing the component. Once
the peak input current Ipk CVpk cos(Iton) is determined,
the rms current in the capacitor can be estimated. The capacitor current will be a series of approximately sawtooth spikes
of height Ipk and a narrow width TI ton, and this waveform
has an rms value IC given by

IC

3
Ipk

3ICVpk

(38)

0.01

0.015
Time (s)

0.01

0.025

36
0.03

Figure 15. Output voltage and input current for rectifier example.

standard 22 mF capacitor will meet the requirements. The

waveforms that result from these choices are shown in Fig.
15. Notice that the current into the rectifier bridge does indeed flow as a series of spikeswith a peak value of about 36
A. The rms capacitor current is about 7 A.
The assumptions used for simplified rectifier design yield
excellent end results, compared with more precise calculations. For example, precise calculation shows that a 22 mF
capacitor yields 0.66 V ripple instead of 0.72 V. The linear
ripple assumption is a conservative approximation: It always
overestimates the actual ripple when exponentials are involved.
Current Ripple Issues

This expression can be used to determine the ripple current

rating requirement of the capacitor.
Capacitive Smoothing Example
Let us illustrate capacitive smoothing by choosing a suitable
capacitor for a classical rectifier. The rectifier is to supply 12
V 3% to a 24 W load, based on a 120 V, 60 Hz input source.
The arrangement needed to solve this problem is shown in
Fig. 14.
A transformer will be needed to provide the proper stepdown ratio for this design. For completeness, let us include a
typical 1 V diode on-state forward drop. The load should draw
24 W/12 V 2 A, and therefore it is modeled with a 6
resistor. When a given diode pair is on, the output will be two
forward drops less than the input waveform, or vI 2 V. We
need a peak output voltage close to 12 V. Therefore, the peak
value of voltage out of the transformer should be about 14 V.
The root mean square (rms) value of vI is almost exactly 10 V
for this peak level. Let us choose a standard 120 V to 10 V
transformer for the circuit on this basis.
To meet the 3% ripple requirement, the output peak-topeak ripple should be less than 0.72 V. The capacitance
should be
C=

IO
2A
= 23 mF
=
2 f I VO
2(60 Hz)(0.72 V)

(39)

The approximate methods overestimate the ripple slightly,

since the time of the exponential decay is less than TI /2, so a

The narrow input current spikes in Fig. 15 beg the question

of whether smoothing will be needed for the input current.
The high current will produce significant voltage drops in any
circuit or device impedances, and it raises issues of coupling
through an imperfect ac source. To improve the input current
waveform, inductance can be placed in series with the rectifier input. With added inductance, the moment of diode turnoff will be delayed by the inductors energy storage action.
When the diodes are on, the new circuit is a rectified sine
wave driving an inductor in series with the parallel RC load.
To analyze the situation, it is convenient to use the fundamental of the ripple voltage expected to be imposed on the
inductor-capacitor-load combination. For large inductor values, this ripple will not exceed that of the rectified sinusoid.
For small inductor values, this ripple is approximately the
sawtooth waveform with the capacitor alone. The function
Vpk sin(It) has a fundamental component of amplitude
4Vpk /3, while the sawtooth has the fundamental amplitude
given in Eq. (37). Figure 16 shows an equivalent circuit based
on the fundamental of the imposed ripple voltage.

i(t)
VI
sin ( t)
2

j L
1
j C

+
R

V0

Figure 16. Fundamental equivalent circuit for ripple evaluation in

a rectifier.

SMOOTHING CIRCUITS

From the circuit in Fig. 16, we can compute the current

drawn from the fundamental source, and then we can use a
current divider computation to find the ripple imposed on the
load resistance. The result for the peak-to-peak output ripple
voltage as a function of the input peak-to-peak ripple voltage
VI (estimated based on the fundamental) is
VO =

VI
(1 + jL/R 2 LC)

24

Current (A)

12

0
i I, L = 0
iI, L = 0.2 mH
iI, L = 2 mH

0.005

0.01

0.015

VL

+
R

C2

V0

Example: Smoothing for dcdc Converters

A dcdc converter application will help illustrate LC smoothing design and a simplified approach. A typical switching
dcdc converter, with a two-stage LC output filter, is shown
in Fig. 18. The semiconductor devices act to impose a voltage
square wave at the filter input terminals.
The key to a simplified approach is this: At each node
within the filter, it is desired that the ripple be very low. This
simple concept means, for instance, that the voltage V1 in Fig.
18 should be nearly constant. If that is true, the inductor L is
exposed to a square voltage waveform. The various waveforms are given in Fig. 19. Since the inductor voltage vL
L(di/dt), the inductor current in Fig. 19(b) can be determined
from

iL (t) =

0.02

0.025

Time (s)

Figure 17. Rectifier input current when inductance is added.

vL (t)
dt
L

(41)

The integral of a square wave is a triangle wave. This supports a linear ripple assumption for further analysis.
With linear ripple, the inductance L becomes relatively
easy to select. Consider a case in which an inductor is exposed
to a square wave of amplitude Vpk, a frequency of f, and a
pulse width of DT, as illustrated in Fig. 19(a). In the stepdown circuit of Fig. 18, this would lead to an average output
voltage of DVpk. While the voltage is high, the inductor is exposed to (1 D)Vpk L(diL /dt). Since the ripple is linear, this
can be written vL L(iL /t), with t DT. Now, the inductance can be chosen to meet a specific current ripple requirement,
L=

24

L2

Figure 18. A dcdc buck converter with two-stage LC output filter.

36

36

+
VI

V1 iL2

(40)

To make sure the inductor gives a useful effect, it is important that 0 1/ LC be significantly less than the ripple
frequency r.
Consider again the example 12 V supply described previously. The ripple frequency is 240 rad/s. Inductor values
up to about 100 H have little effect, or could even increase
the ripple, owing to resonance. An inductance of 200 H
yields a value of VO /VI 0.67. What value of imposed input ripple should we use? The value r2LC in the denominator
of Eq. (40) is 2.5, which is only a little larger than 1. The
input ripple will be nearly that of the capacitor alone, and the
inductor would be expected to reduce ripple by about 30%.
Simulation results were computed for the complete rectifier,
and they showed a reduction by 28% to 0.042 V. At the same
time, the peak value of iI dropped from almost 36 A to only
8.2 A.
Figure 17 shows the current iI for no inductance, for 200
H, and for a 2 mH inductor. The current waveforms show
how the turn-off delay brings down the peak value and makes
the current smoother. One important aspect is that the turnoff delay decreases the peak voltage at the output. For example, the 2 mH case provides a 9 V output instead of the required 12 V. For a larger inductor, the actual output voltage
would be the average of the rectified sine wave, equal to
2Vpk /. In the limit of L the current iI becomes a square
wave with a peak value equal to the load current. More complete discussion of designs of LC filters for rectifier smoothing
can be found in Refs. 3, 4, and 6.

12

iL

409

vL DT
iL

and iL =

vL DT
L

(42)

This simple but powerful expression leads to a quick selection

of values once the circuit requirements are established.
A special value of inductance from Eq. (42) is the one that
sets current ripple to 100%. This is the minimum inductance that will maintain current flow iL 0 and is termed the
critical inductance, Lcrit. Setting a specific ripple level is equivalent to setting the ratio L/Lcrit. For example, if the current
ripple is to be 10%, the inductance should be ten times the
critical value, and so on.
Now consider the capacitor C that follows the inductor.
The desire for low ripple means that the current in inductor
L2 should be almost constant. The current in the capacitor C
will be very nearly the triangular ripple current flowing in
L. Since iC C(dvC /dt), we have

vC =

iC (t)
dt
C

(43)

SMOOTHING CIRCUITS

Voltage at diode

410

To provide low relative ripple v1 /vL, the resonant radian frequency 1/ LC must be well below the square-wave radian
frequency 2/T. This is easy to see by requiring v1 /vL 1
in Eq. (45). Then

Vpk

DT

DT 2
 1,
8LC
T = 1/f

2T

;;
Voltage or current

r8

(46)

The next inductor L2 should provide almost constant output vO, so it is exposed to the piecewise quadratic ripple voltage from capacitor C. Analysis of this waveform is more complicated, but it can be approximated well as by a sine wave
with peak value v1 /2. The fundamental should provide a
good basis for further stages. Then the approximate sinusoidal waveform appears entirely across L2. The ripple current
in L2 is

v1
1
v1
sin(rt) dt =
iL2 =
cos(rt)
(47)
L2
2
2L2 r

3T

(a)

Area

1
 f

LC

VL(t)

Since r 2/T, the peak-to-peak current ripple in L2 is

5iL(t)L/T

iL2 =

v1 T
vL DT 3
=
2L2
16L2 LC

(48)

By a similar process, the final output voltage ripple is

25v1(t)LC/T 2

vO =

iL2T
vL DT 4
=
2C2
32 2 L2C2 LC

(49)

Since these relationships are based on ideal results for each

part, the assumption here is that the ripple is reduced significantly at each stage. This requires 1/ L2C2 2/T, and
so on.
Actually, it is unusual in the context of dcdc conversion
to reduce the ripple substantially in each LC filter stage.
More typically, the first stage performs the primary ripple reduction, while the second stage uses much smaller components to filter out the effects of ESR in C.

100iL2(t)L2LC/T 3

500v0(t)L2C2LC/T 4

ACTIVE SMOOTHING
0

2T

3T

Time
(b)
Figure 19. Current and voltage waveforms at points within the LC
filter of Fig. 18. (a) Diode voltage. (b) Voltages and currents in the
smoothing filter.

The integral of a triangle is a piecewise-quadratic waveform.

Of more immediate concern is the effect on voltage ripple, as
shown in Fig. 19(b). When the capacitor current is positive,
the voltage will be increasing. The total amount of the voltage
increase, v1, will be proportional to the shaded area under
the triangle, and
v1 =

iL T
1 1 T iL
=
C2 2 2
8C

Series-Pass Smoothing
Figure 20 shows a simple series-pass circuit for smoothing
and regulation. In the arrangement shown, a constant low-

(44)

With the ripple current value from Eq. (42), this means that
the ripple on voltage V1 is
v DT 2
v1 = L
8LC

In active smoothing, circuits that resemble amplifiers are

used in addition to storage elements for the smoothing process. Both dissipative and nondissipative approaches exist,
but dissipative methods are the most common. The energy
arguments require dissipative active smoothers to deliver output power below the minimum instantaneous input power.
For this reason, most dissipative active methods combine
smoothing and regulation. Voltage regulators are covered in a
separate article, so just a short introduction is provided here.

(45)

Imperfect
dc
VI
supply

iI = ic
iB

VBE

VR

+
To
V0 load

Figure 20. Series-pass active smoothing and regulating circuit.

SMOOTHING CIRCUITS

411

Shunt Smoothing
B

RB

RC

C
r

r0
gmvbe

RE
E
Figure 21. Hybrid- transistor model.

power reference voltage VR is produced and is then used to

drive the base of a pass transistor. In its active region, the
transistor exhibits a nearly constant baseemitter voltage
drop, and the current iC equals iB. The emitter voltage will
be VR VBE, which is nearly constant. If is high, the base
current will be low, and the voltage VBE will change little as
a function of load.
From a smoothing perspective, the interesting aspect of
the series-pass circuit is that the output voltage is independent of the input voltage, provided that the input voltage is
high enough for proper biasing of the transistor. This is exactly representative of the dissipative smoothing concept. For
example, if the output is intended to be 5 V and if the transistor voltage VCE should be at least 2 V for proper bias in the
active region, then any input voltage higher than 7 V will
support constant 5 V output. The input voltage can vary arbitrarily, but the output will stay constant as long as it never
dips below 7 V.
The efficiency of a series-pass circuit is easy to compute. If
is very large, the emitter current IE IO will equal the collector input current IC II. The efficiency is
=

PO
V I
V
= O O = O
PI
VI II
VI

(50)

High efficiency demands that the input and output voltages

be as close as possible.
A real series-pass circuit will still exhibit a certain level of
ripple. The basis for this can be seen in the small-signal hybrid- model of a bipolar transistor (7), shown in Fig. 21. In
the case of fixed voltage at the base terminal and voltage with
ripple at the collector terminal, the stray elements r0 and C
both provide a path by which ripple current can reach the
output. In a good-quality transistor, r0 can be made very high,
so internal capacitive coupling to the base terminal is the
most important leakage path. In practical applications, it is
common to provide a passive smoothing filter stage at the series-pass element input to help remove high-frequency harmonics. The output of the regulator is provided with capacitive decoupling to prevent loop problems such as those
described in the Introduction. With these additions, a seriespass smoother can reduce ripple to just a few millivolts even
with several volts of input ripple. That is, ripple reductions
on the order of 60 dB or more can be achieved. Discussions of
integrated circuits that implement series-pass circuits can be
found in Refs. 8 and 9.

Series smoothing makes use of the ability of a bipolar transistor to establish an emitter current that depends on the base
input rather than on the input source. Shunt smoothing is a
dual of this in certain respects: It makes use of the ability of
certain elements to establish a voltage that is independent of
the source. In Fig. 22, a basic form and a typical implementation of a shunt regulator are shown. The imperfect dc supply
provides energy flow and current iI through the resistance
RI. The fixed voltage delivers the desired output current IO.
The fixed element makes IO independent of iI, and smoothing
is accomplished.
The simple circuit of Fig. 22(a) is actually very common in
battery-powered devices. When a charger is connected, it is
only necessary to make sure that the average value of iI is
greater than IO to provide both regulation and charging. With
the charger is disconnected, the battery continues to maintain
operation of the load. In this case, the storage action of the
battery means that the instantaneous value of iI is unimportant; an unfiltered rectifier can be used as the imperfect dc
supply, for example. The actual level of output ripple depends
on the quality of the battery as a dc source.
The Zener diode circuit of Fig. 22(b) is common for use in
generation of reference voltages, and it is also widely used for
low-power sensor supply requirements and similar applications. Since the diode does not have any energy storage capability, this smoother requires that the instantaneous value of
iI must always be greater than the desired IO. If the output
current is not well-defined, a worst-case design must estimate
the highest possible output current as the basis for the minimum iI.
In a shunt regulator, there is power loss in the resistor:
the square of the rms value of iI times the input resistance
RI. There is also additional power in the fixed voltage element: the difference iI IO times VO. The power in the voltage
element is lost in the Zener circuit, or it serves as charging
power in the battery circuit. The output power PO is VOIO. If
we could select a value of input current to exactly match the
output current (the best-case situation with minimum input

Imperfect
VI
dc
supply

iI

RI

l0
To
load

V0

(a)

Imperfect
VI
dc
supply

iI

l0
V0

To
load

(b)
Figure 22. Shunt smoothing alternatives.

412

SMOOTHING CIRCUITS

Imperfect
dc supply

Power
conversion

High
ripple
port

Active
Low
smoothing ripple
circuit
port

ac current sensors

~
iI

High
ripple
port

Feedforward
path

ic

~
i0

Low
ripple
port

Cancellation Smoothers

Feedback path
Cancellation current driver

Figure 23. A general active smoothing system and its generic implementation.

current and minimum loss), the loss power PL would be IO2 RI.
Since the input current is (VI VO)/RI, the efficiency would
be

PO
=
PO + IO2 RI

function of the selected reference value, and it is independent

of the input. Large voltage ratios are troublesome for the linear smoothers. For example, if either type is used for 48 V to
5 V conversion, the best possible efficiency is only about 10%
even if ripple is not an issue.
Both series and shunt smoothers benefit if the input source
ripple is relatively low, provided that this is used to advantage to keep the voltage ratio low as well. For example, a
series smoother with an input voltage of 7 V 0.1 V and an
output voltage of 5 V can produce an output with less than 1
mV of ripple with efficiency of about 70% if the series-pass
element can work with bias levels down to 1.9 V. A shunt
smoother can function with even lower bias. With a fixed load
level of 100 mA, an input voltage of 5.5 V 0.1 V, and an
output voltage of 5.00 V, a shunt regulator with efficiency up
to about 85% can be designed.

VO IO

V V  = VO
VI
I
O
VO IO + IO
RI
RI

(51)

Any realistic design must have higher input current. For this
reason, a shunt smoother is always less efficient than a series
smoother for given input and output voltages. It is a very simple circuit, however, which explains its wide use, especially at
low power levels.
Summary of Linear Smoothing
Series and shunt smoothers are termed linear active circuits
because they function as amplifiers. The output is a linear

In cancellation smoothing (10,11), methods similar to series

and shunt circuits are used, but handle only the ripple itself.
This avoids the dc dissipation inherent in both of the linear
methods, since the dc input to output voltage ratio becomes
irrelevant. The general principle of cancellation smoothing
can be observed in Fig. 23, which shows a shunt-type current
injection cancellation smoother. In such a system, the input
ripple current iI is sensed, and the controller creates a cancelling current iC as close as possible to iI. The practical version
in Fig. 24 shows an input filter inductor and a transformerbased amplifier coupler. With these additions, the current
amplifier handles none of the dc current or power, and there
is very little dissipation.
Cancellation smoothing can work either on feedforward or
feedback principles (or with a combination of these). In feedforward cancellation, the input ripple current is sensed, and
an amplifier with good bandwidth and a gain of exactly 1 is
needed. The ability of such a system to produce smooth output depends on the accuracy of the gain. For example, if the
actual gain is 0.99 instead of 1.00, then the output ripple
will be 0.01 times that at the inputa reduction of 40 dB. It
is not trivial to produce precise gain over a wide frequency
Low ripple here
I0

iI

VI

V0

L
Dc dc
converter
with
imperfect
input

Current
transformer

iC
Dc blocking

CC

CF
Feedforward
path
RF

Figure 24. Implementing a feedforward

ripple current canceler.

Load
C0

~
vL
~
iI
Integration
~
to provide iI
~
from vL

Current
driver

Feedback
path
Gain
correction
to minimize
ripple

SOCIAL AND ETHICAL ASPECTS OF INFORMATION TECHNOLOGY

range, but even 10% gain error can provide a useful 20 dB of

current ripple reduction.
In feedback cancellation, the operating principle is to measure and amplify the output ripple signal iO and use this to
develop a correction current equal to the gain k times the output ripple. Feedback cancellation has the advantage of correcting ripple caused by noise at the output as well as ripple
derived from the imperfect dc supply. High gain is required.
For example, if k 100, the output ripple ideally is a factor
of 100 lower than the input ripple, and the ripple is reduced
by 40 dB. Gain of k 1000 reduces current ripple by up to
60 dB, and so on. This is too simplistic, however. The sensing
device for iO has an associated time lag. If the gain is too high,
this time lag will lead to instability. Feedback cancellation is
extremely effective in systems with low ripple frequencies (below about 10 kHz), since a brief time lag in the sensor will
not have much effect at low speeds.
Cancellation methods, often combining feedforward and
feedback techniques, have been used in power supplies at 50
Hz and 60 Hz (12,13), spacecraft systems switching at up to
100 kHz (11), and a variety of dcdc conversion systems
(10,14).

ACKNOWLEDGMENT
P. Krein participated as a Fulbright Scholar, supported
through the joint United StatesUnited Kingdom Fulbright
Commission during a visiting appointment at the University
of Surrey.

BIBLIOGRAPHY
1. A. I. Zverev, Handbook of Filter Synthesis, New York: Wiley, 1967.
2. A. B. Williams, Electronic Filter Design Handbook, New York:
McGraw-Hill, 1981.
3. P. M. Chirlian, Analysis and Design of Integrated Electronic Circuits, London: Harper and Row, 1982, p. 1011.
4. R. J. Rawlings, Parallel T filter networks, in F. Langford-Smith
(ed.), Radio Designers Handbook, 4th ed., London: Iliffe Books,
1967, pp. 11941196.
5. Anonymous, High Q notch filter, linear brief 5, in Linear Applications Databook, Santa Clara: National Semiconductor, 1986, p.
1096.
6. P. T. Krein, Elements of Power Electronics, New York: Oxford
Univ. Press, 1998.
7. A. Vladimirescu, The SPICE Book, New York: Wiley, 1994.
8. R. J. Widlar, A versatile monolithic voltage regulator, National
Semiconductor Application Note AN-1, 1967.
9. R. J. Widlar, IC provides on-card regulation for logic circuits, National Semiconductor Application Note AN-42, in Linear Applications Databook, Santa Clara: National Semiconductor, 1986.
10. P. Midya and P. T. Krein, Feedforward active filter for output
ripple cancellation, Int. J. Electronics, 77: 805818, 1994.
11. D. C. Hamill, An efficient active ripple filter for use in dcdc conversion, IEEE Trans. Aerosp. Electron. Syst., 32: 10771084, 1996.
12. L. Gyugyi and E. C. Strycula, Active ac power filters, Proc. IEEE
Industry Applications Soc. Annu. Meeting, 1976, p. 529.
13. F. Kamran and T. G. Habetler, Combined deadbeat control of a
series-parallel converter combination used as a universal power
filter, IEEE Trans. Power Electron., 13: 160168, 1998.

413

14. L. E. LaWhite and M. F. Schlecht, Active filters for 1 MHz power

circuits with strict input/output ripple requirements, IEEE
Trans. Power Electronics, 2: 282290, 1987.

PHILIP T. KREIN
University of Illinois

DAVID C. HAMILL
University of Surrey

SUMMING CIRCUITS

SUMMING CIRCUITS
Electronic systems perform operations on information signals
represented by electrical variables. Among these operations,
one of the most simple, and therefore most common and
widely used, is the summation or addition of signals, with a
large range of variations.
Signal addition is a fundamental operation upon which
many other simple and complex operators are based. For example, digital processing circuits perform most of their operations from some combination of addition and shifting.
Signal-processing circuits can be classified into two large
groups, according to the way in which they perform their processing function: analog and digital processing systems. Analog processing systems operate on signals defined over a continuous range or interval. These signals are generally
associated with the continuous value of some electrical magnitude of the circuit, like a voltage, current, charge, or magnetic flux defined in connection with some element or electrical nodes in the network. Analog summing operations emerge
from the basic laws of electromagnetism, Maxwell equations,
and in particular their derived result in circuit theory (Kirchhoff s Laws). On the other hand, digital processing systems
operate over abstract number representations, generally codified as a sequence of digits, without a direct connection to a
physical magnitude in the network. Possible values of each
digit are discrete (two in the typical binary case), and each
value is associated to some range of an electrical variable. In
these cases, summation follows algorithmic rules not related
to circuit theory.
ANALOG ADDERS
Introduction
An electronic analog adder operates over two or more electrical input signals (x1, x2, . . ., xN), providing an electrical output signal xs, which is the sum of the former
xS = x1 + x2 + + xN

(1)

The electrical signals involved may be of the same or different

nature (voltage, current, charge, flux). Often, input signals
are all of the same type. If signals of different nature are combined, appropriate constants must be introduced to maintain
a proper dimensionality (1). Such signal multiplication by a
constant or scaling, is often found as a constitutive operator
of analog summing circuits, as shall be seen, even when all
input signals are of the same nature. The involved constants

633

are always related to physical properties of one or more circuit elements and, in some cases, to other electrical signals.
The number of analog summing circuits reported in the
literature is extremely large. Therefore, a classification is
mandatory for their discussion. This classification can be
made according to the nature of the signals to be added (current or voltage) and also by the nature of the output signal.
Another distinctive property is the way in which the time
evolution of the input signals is taken into account: continuous-time or sampled-data systems. Although in either case
the expected input and output signals are continuous in amplitude (i.e., analog), continuous-time signals are defined at
any instant within some time interval, and the corresponding
systems operate continuously in time. On the other hand, the
information carried by discrete-time signals is defined only for
discrete-time instants, and the corresponding sampled-data
systems operate under the control of one or more periodic
clock signals.
An alternative form of classification refers to the circuit
technique employed to find the summing circuit, in particular
to the type of elements required for its implementation: resistors, capacitors, analog switches, operational amplifiers, current conveyors, transistors, operational transconductance amplifiers, and the like.
Analog Summation Fundamentals
Analog summing circuits are essentially based on Kirchhoff
Laws. To be precise, most analog summing circuits rely on
Kirchhoff Current Law (KCL), which can be formulated as
follows: The algebraic sum of currents flowing into any network node is zero. According to this law, the summation of
any number of current signals is straightforward. It can be
obtained by simply connecting the circuit branches carrying
the currents to be added to a common node and allowing an
additional branch for the sum of the currents to flow out of
the node. Obviously, the current branches must have one of
the nodes available to be connected to the summing node.
The Kirchhoff Voltage Law introduces a similar tool for
voltage signals. It can be formulated as follows: The algebraic
sum of the potential drops around any loop is zero. According
to this law, the summation of voltage signals is also straightforward and can be obtained from a series connection of the
pair of terminals between which the incoming voltage signals
are defined. Because the incoming voltage sources are connected in series, they must be floating, that is, the voltage
drops must be insensitive to a shift of their terminal voltages
with respect to an arbitrary reference level.
Although summing circuits based on either of the two approaches are possible, voltage signals found in most electronic
circuits are defined as the potential at a particular node measured from a common ground reference: therefore, floating
voltage signals are not usual. For this reason, most analog
summing circuits rely on KCL, as stated previously.
Still, KCL-based summing circuits can operate on voltage
signals, as long as the incoming voltages are transformed into
currents, added at a common node, and the resulting current
transformed again into a voltage. This is the most common
operation principle of summing circuits, found in traditional
and well-known structures.
Because summation is linear by definition, voltage-to-current and current-to-voltage transformations should be linear.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

634

SUMMING CIRCUITS

In its simplest form, these transformations can be obtained

from linear two-terminal elements, whose constitutive equations are defined as
V =ZI

I =Y V

or

(2)

where Z and Y are the impedance and admittance of the twoterminals element, respectively. It is obvious that Z 1/Y.
Figure 1 shows a conceptual example of voltage-signals
summation based on KCL. Simple analysis results in the following expression for the output voltage:

Vo =

N


Z
i=1

Zi

Vi =

N


Yi
Vi
Y
i=1 F

(3)

Elements Z1 to ZN perform a linear transformation of the input voltages into currents. These currents are added at node
Ns according to KCL. The resulting current Is is reproduced
by the current-controlled current-source (CCCS) and linearly
transformed into the output voltage Vo with the help of element ZF. Note that the output voltage represents a weighted
summation of the input voltage signals, all of them defined
with respect to a common voltage reference.
The intermediate transformation into currents results in
different scaling factors or weights Wi for each input signal
Wi =

Yi
Z
= F
YF
Zi

(4)

allowing the output voltage to be expressed as

Vo =

N

WiVi

(5)

i=1

The impedance ZF of the output element provides a gain

control for the output signal. Scaling weights and global gain
control introduce a large flexibility in these summing operators. Some of these capabilities rely on an active element (in
this example a CCCS) to implement a virtual ground at node
Ns, which in turn allows the transformation of current Is into
the output voltage without altering the individual currents

I1
V1

Z1
I2

V2

VN

IS

Z2

.
.
.
.
.
.
.
.

IN

. Ns
.
.
.
.

Vo
IS

ZF

ZN

Figure 1. Conceptual example of voltage-signals summation based

on KCL. This is the underlying fundamental of most analog summing circuits.

I1
V1

Z1
IS

I2
V2

VN

Z2

.
.
.
.
.
.
.
.

Vo

. Ns
.
.
.
.

IN

ZF

ZN

Figure 2. Voltage-signals summation without active element. Scaling factors become interdependent.

Ii. This will be illustrated in connection with Fig. 2, a simplified version of Fig. 1 in which the active element has been
eliminated. Simple analysis results in the following expression for the new output voltage:
N

Vo =

YiVi

i=1
N

(6)

Yi + YF

i=1

which is still a weighted summation of the input voltages.

Now, however, the scaling factors associated with the different input signals cannot be controlled independently. Furthermore, in the simplest case in which all elements are resistors, the weighting factors will all be smaller than one. In
addition, the effect of the external load on the output voltage
must be carefully considered. Because of these and other related reasons, most analog summing circuits employ some
type of active element.
Analog Summing Circuits with Operational Amplifiers
A simple and well-known alternative for a practical implementation of Fig. 1 uses operational amplifiers as active devices and linear resistors as two-terminal elements. Other
simple two-terminal elements can also be employed (e.g., capacitors), although special considerations are required. In
what follows, we assume the use of linear resistors R 1/G
for simplicity.
The resulting circuit is shown in Fig. 3. In this circuit, current Is flows from the virtual ground node toward the output
terminal, resulting in a sign inversion in the summing operation. This summing circuit, in which all weights are negative,
is commonly referred to as an inverting configuration.
Positive weights can be achieved by several means, the
simplest of them being the use of an additional inverting configuration with a single input (i.e., an inverting amplifier), as
shown in Fig. 4.
Another alternative results from the combination of the
circuit in Fig. 2 with a noninverting amplifier. This solves the
restriction on the weights to values smaller than unity and
provides the necessary driving capability for the output voltage. The resulting circuit, commonly known as a noninverting
configuration, is shown in Fig. 5. Note that the grounded input element is used as an additional input.
The circuits in Figs. 3Fig. 5 are restricted to same-sign
weights. When a summing circuit with both positive and neg-

SUMMING CIRCUITS

635

I1
V1

Z1

V2

VN

ZF

IS

I2

Z2

.
.
.
.
.
.
.
.

IN

. Ns
.
.
.
.

Vo
+

N
N
N
RF
Gi
Vo =
Vi =
Vi = Wi Vi
i = 1 Ri
i = 1 GF
i= 1

ZN

Figure 3. Voltage-summing circuit using operational amplifiers (inverting configuration).

I1
V1

Z1

V2

Z2

.
.
.
.
.
.
.
.

VN

ZF

IS

I2

Vo =

IN

Wi Vi

i= 1

. Ns
.
.
.
.

Vo
Wi =

ZN

Z
Gi
= F
GF
Zi

Figure 4. Positive-weight summing circuit using two inverting configurations.

Gi Vi
G i = 1
Vo = 1 +
GF N
Gi
i=1

ZF

I1
V1

Z1

V2

Z2

I2

VN

.
.
.
.
.
.
.
.

Vo
+

IN

.
.
.
.
.

Wi = 1 +

ZN

V1

Z1

V2

Z2

.
.
.
.
.
.
.
.

G
GF

Gi
N

Gi
i =1

Figure 5. Positive-weight summing circuit using a noninverting amplifier.

Z 0
M
GF + Gj
N G+
M G
j= 0
j
i

Vo =
Vi+
V

GF
GF j
N
j= 1
+ i =1
Gi
i= 0

.
.
.
.
.

VM

ZM

V1+

Z1+

V2+

Z2+

ZF

Vo

VN+

.
.
.
.
.
.
.
.

+
ZN

.
.
.
.
.
Z 0+
Figure 6. Generalized summing circuit based on an operational amplifier.

636

SUMMING CIRCUITS

ative weights is required, some of the input signals can be

inverted at the expense of an additional active element per
inverted input. Another alternative is the use of the so-called
generalized adder, obtained from a combination of the inverting and noninverting configurations in Figs. 3 and 5. The
resulting circuit and its transfer function are shown in Fig. 6.
As with Fig. 3, negative weights are given by the ratio of
the input Gj to the feedback GF conductances and are independent of each other. On the other hand, positive weights
depend on all input conductances. In order to eliminate this
drawback, two additional elements Z0 and Z0 are introduced
to allow for the possibility of making
M

GF +

Gj

j=0
N

=1

(7)

G+
i

i=0

which allows the transfer function of the generalized adder to

be expressed as

Vo =

N

Wi+Vi

i=1

M

W j V j

(8)

j=1

circuits are in fact direct implementations of Fig. 1. As in the

previous case, different configurations with positive and negative weights can be obtained.
Figure 7 shows a noninverting [Fig. 7(a)] and an inverting
[Fig. 7(b)] configuration. Both of them are possible with either
type I or type II CCs. The two configurations differ only in
the sign of the CCs: CC for the noninverting configuration
and CC for the inverting counterpart.
If either CC or CC are not available, the necessary sign
inversion can be achieved at the expense of an additional CC
of either sign, as shown in Fig. 8. Note that the sign-inverter
in Fig. 8(a) operates on a voltage signal. Its input impedance
is high; therefore, it may be connected to any circuit node
without affecting its behavior. On the other hand, inverting
stages in Fig. 8(b, c) operate on currents and thus should be
inserted in series at the output of the CC in Fig. 7, whose
loading element ZF must be eliminated.
The combination of the circuits in Figs. 7 and 8 results in
either inverting or noninverting summing circuits realizable
with any type of CC. If positive and negative weights are required on the same summing device, we can use inverters at
specific inputs, or a generalized adder architecture based on
CCs. Figure 9(a) shows an implementation based on CCI of
either sign. Indeed, the output of the CCI is not used. Note
that its transfer function would be identical to Eq. (8) if

with positive and negative weights having similar expressions

G+
Wi+ = i
GF

W j =

and

Gj
GF

N

(9)

Note that Eq. (7) can also be written as

1+

M

N


G
G+
0
=
Wi+ + 0
GF
GF
i=1

W j +

j=1

(10)

Therefore, if

1+

M

W j <

j=1

N

Wi+

(11)

i=1

we can select G0 0 and


G
0 = GF

N

Wi+

i=1

M


W j 1

(12)

i=0

j=1

= GF 1 +

M


j=1

W j


Wi+

(13)

Gj = GF

(14)

j=0

N

N

M

where GF is an arbitrary normalization conductance, not associated to any element, that plays the role of GF in Eq. (9).
Elements Z0 and Z0 in Fig. 9(a) serve the purpose of achieving
Eq. (14). As with opamp-based adders, only one of these elements is required.
The design equations required to obtain the different Gi
values are identical to those obtained for the generalized
adder in Fig. 6.
Figure 9(b) shows a generalized adder based on a CCII and
its transfer function. The positive signed expression is obtained if a CCII is employed, whereas the negative sign corresponds to the use of a CCII. In either case, the transfer
function can again be expressed in the form of Eq. (8) if Z0
and Z0 are chosen to verify

On the other hand, if Eq. (11) is not true, we can select G0

0 and

G+
0

G+
i

G+
i =

i=0

M

Gj

(15)

j=0

As in the previous case, only one of both impedances are

needed. If

i=1

M

Therefore, only one element among Z0 and Z0 is actually required.

Summing Circuits Using Current Conveyors
The use of current conveyors (see CURRENT CONVEYORS) as the
required active element in Fig. 1 results in a new family of
summing circuits. Indeed, because current conveyors (CC)
perform as current-controlled current-sources, the resulting

W j <

j=1

N

Wi+

(16)

i=1

we can select G0 0 and


G
0

= GF

N


i=1

Wi+

M


j=1


W j

(17)

SUMMING CIRCUITS

I1
V1

I1

Z1

V1
x CCI
or
y
CCII+

Z2

VN

. Ns
.
.
.
.

IN

V2

Vo

.
.
.
.
.
.
.
.

VN

N
N G
i
Vi = Wi Vi
GF
i=1
i=1

x CCI
or
y
CCII

Z2

IS ZF

ZN

Vo =

IS

I2
+

.
.
.
.
.
.
.
.

Z1

IS

I2
V2

637

IN

. Ns
.
.
.
.

Vo
IS ZF

ZN

N
N G
i
Vo =
Vi = Wi Vi
GF
i=1
i=1

(a)

(b)

Figure 7. Summing circuits using a single current conveyor: (a) noninverting configuration and
(b) inverting configuration.

Otherwise, we can select G0 0 and

G+
0 = GF


M

W j

j=1

N

ential input of the OTAs allow the realization of either-sign

weights by simply swapping the input nodes.
Figure 11 shows a generalized adder structure, whose
transfer function is given by


Wi+

(18)

i=1

Vo =

An important remark concerning the presented summing circuits with CCs is that, because the output impedance of the
current conveyor is high, any current drain from the output
node Vo would result in deviations from the expected behavior. If a low impedance load is to be driven by Vo, a buffer will
be required.

Wi+ =

CCII+

CCII

g+
mi
gmF

and

W j =

g
mj
gmF

(20)

Discrete-Time Summing Circuits

Using Switched-Capacitors Techniques
Switched-capacitor (SC) techniques substitute continuoustime current flow by periodic charge-package transferences.
In their simplest and most common form, SC circuits are controlled by a pair of nonoverlapped clock signals defining two
alternating configurations of the circuit. These two phases
are often referred to as even and odd.
The operation of an SC summing circuit can be described
in general as follows: given a set of voltage signals to be

y CCI+
or
x CCI

Vo = Is ZF

z
IS

(19)

j=1

IS
x

(a)

W j V j

which can be made highly insensitive to variations in the IC

fabrication process. As with CC-based realizations, an output
buffer will be required if low impedances are to be driven.

IS
V0 = V01

M

where the weights are given by transconductances ratio

The use of operational transconductance amplifiers (OTA) as

active elements constitutes by itself a general technique for
the realization of analog circuits, with special relevance in
integrated circuit (IC) realizations. Summing devices are easily realized with this circuit technique.
Figure 10(a) shows the symbol and transfer function of an
OTA. Its differential input provides a large flexibility in the
realization of most operators, including positive and negative
resistors, as shown in Figs. 10(b, c). OTAs by themselves provide a direct transformation of voltages into currents,
whereas the resistor configurations in Fig. 10 allow the inverse transformation. Therefore, we have all elements required to realize a summing structure. In addition, the differ-

Wi+Vi

i=1

Summing Circuits Using Operational

Transconductance Amplifiers

V01

N

ZF

z
Vo = Is ZF

ZF

(c)

(b)

Figure 8. Sign inverters using current conveyors: (a) inverter using a CCII , (b) inverter using
a CCII, and (c) inverter using either a positive or a negative CCI.

638

SUMMING CIRCUITS

V1

Z1

Z2

V2

VM

Z 0

.
.
.
.
.
.
.
.

+
V1

+
Z1

Z2

Z2

.
.
.
.
.

ZM

V0

ZN

Z 0

.
.
.
.
.
.
.
.

x
V1+

Z1+

V2+

Z2+

VN+

Z0

i=1

Vo

.
.
.
.
.

ZN+

Z +0

M
Gi+ Vi+

CCII

ZF

.
.
.
.
.
.
.
.

.
.
.
.
.

Vo =

CCI

.
.
.
.
.
.
.
.

V2

VM

y
x

VN

Z1

.
.
.
.
.

ZM

V2

V1

Gj Vj

+
Vo =

j=1

M
Gi+ Gj
i=0
j= 0

Gi+

N G+
i
V+
GF i
i= 1

i= 0
M

Gj
j= 0

(a)

M G
j
GF Vj
j= 1

(b)

Figure 9. Generalized adders using current conveyors: (a) using CCI and (b) using CCII.

added, each of them is periodically sampled, during one of

the clock phases, in a linear capacitor. The resulting charge
packages are added in a common node and transformed into a
voltage during the same or the next clock phase using another
capacitor. Note that the underlying operation principle is
identical to that of the previous continuous-time circuits, except that current flows are replaced by periodic discrete-time
charge transferences, which indeed may be considered as a
current flow from a time-averaged perspective.
Figure 12(a) shows a set of SC input branches. In the oddto-even phase transition, a charge package Qoe, equal to the
sum of the charge variations in each capacitor, flows to a virtual ground node. The value of Qoe is easily obtained
applying the charge-conservation principle, yielding

Qoe = Qe Qo =

(21)
Note that signal information is conveyed in the difference of
capacitor charges at the end of two consecutive odd and even

V1

gm

I = gm V
(a)

+
+
gm1

gm

V=

1
gm I

(b)

V=

gm

1
gm I

V1

V2

+
VN

Vo

+
+
gm2

.
.
.
.
.
.
.
.

+
+
gmN

gm2

..
..
.

gmF

..
..
.

.
.
.
.
.
.
.
.

gmM

(c)

Figure 10. (a) Symbol and transfer function of an operational transconductance amplifier. (b) Implementation of a grounded resistor using an OTA with negative feedback. (c) Implementation of a grounded
negative resistor using an OTA with positive feedback.

gm1



Ci Vi2e (n) + Vi3o (n 12 ) Vi1o (n 12 )

i=1

V2
I

N

N g+
M g

Vo = mi Vi+ mj Vj
gmF
gmF
i= 1
j= 1
Figure 11. Generalized adder circuit based on OTAs.

VM

SUMMING CIRCUITS
o
V11

e
V12

o
V21

e
V22

o
VN1

C1

C2

.. e
..
..
..

e
VN2

o
V13

e
V23

V1o

V1e

V2o

V2e

..
..
.

CN

C1

o
VN3

Qoe

C2

Qoe

639

..
..
..
..

..
..
.

VNo

VNe

CN

(a)

(b)

Figure 12. (a) Generic input branch of a SC summing circuit. (b) Input branch for SC structures
insensitive to opamp offset-voltage.

phases, represented by time-instants (n 
)T and nT, respectively, where T is the clock-signal period. The discrete-time
nature of the processing is therefore evident.
Each term in Eq. (21) is given by voltage differences at the
two plates of the corresponding capacitor. Although the virtual ground node is nominally equivalent to ground, the input-referred offset voltage of the required active element introduces a small error. This error will be relevant if the
required accuracy is in the range of 78 equivalent bits or
above. Offset-voltage effects can be avoided if one of the plates
of the capacitor is permanently connected to the virtual
ground node, as shown in Fig. 12(b), which results in the following expression for Qoe,

Qoe = Qe Qo =

N

Ci [Vie (n) Vio (n 12 )]

discharge the feedback capacitor and to provide a current

path to the virtual ground node. Therefore, only one of the
charge packages originated by the input branches, Qoe in the
example, is actually transformed into a voltage, and the output signal is valid only during one of the clock phases. Indeed,
during the other clock phase, the output voltage is equal to
the opamp offset voltage, resulting in large slewing requirements from the opamp. Figures 13(b, c) present alternative
charge-sensing stages with lower slewing requirements at the
expense of an increased complexity. Other relevant differences are related to their particular sensitivity to the finite
gain and bandwidth of the opamps (1).
Combinations of the input branches in Fig. 12 and the
sensing stages in Fig. 13 result in summing structures insensitive to parasitic capacitances. If Fig. 12(b) is employed, the
result is also insensitive to the opamp offset, but only during
one of the clock phases.
In every case, the output voltage can be obtained from

(22)

i=1

Results similar to Eqs. (21) and (22) can be obtained for the
charge package Qoe originated just after the even-to-odd
transition.
The transformation of these charge signals into a voltage
requires a linear capacitor and an active element to implement the required virtual ground. An operational amplifier
with capacitive feedback is the most common choice, as shown
in Fig. 13(a). Note that one of the clock phases is used to

Qoe

Co

Vie =
Qoe /Co

Note that a sign inversion takes place in the charge-sensing

stage. The underlying voltage-charge-voltage transformations
using capacitors result in the following expression for the ab-

Qoe

Co

oo

Qoe

Co

Co

Vo

o
+

(23)

Vo

o
e

(a)

Co
(b)

Co
(c)

Figure 13. Charge-sensing stages insensitive to opamp offset-voltage and stray capacitances:
(a) Gregorian stage (2), (b) Maloberti stage (3), and (c) Nagaraj stage (4).

Vo

640

SUMMING CIRCUITS

solute value of the weighting coefficients:

Wi =

Ci
Co

(24)

which can be made highly independent of IC fabrication technology variations. As seen from Eqs. (21) and (22), contributions of either sign are possible, depending on the particular
switching configuration of the input branch. Note also that a
delay of T/2 exists for some of the input signals. The delay is
related to the sign of the weighting factor, in particular if the
offset-insensitive branch is used.
The operational amplifiers in Figs. 12 and 13 can be replaced by operational transconductance amplifiers whenever
the SC circuit drives a capacitive load. This is in fact a common practice in IC realizations, in which OTAs are usually
advantageous in terms of area and power as compared to traditional, low output-impedance opamps.
Advanced Considerations in the Design
of Analog Summing Circuits
The discussion of the preceding circuits has been made, as
usual, on the basis of idealized descriptions of circuit elements: models. Practice, however, shows that real circuits operation is affected by several second-order effects. These include qualitative deviations of components behavior from
their ideal model, systematic and random variations of electrical parameters from their nominal values, additional parasitic elements, and external interferences. Some of these error
sources and their effects on analog summing circuits are described next.
Element Tolerances. Electrical parameters of real circuit
components differ from their nominal values as a result of
unavoidable manufacturing process inaccuracies. Such deviations are generally unpredictable and, therefore, commonly
treated as statistical variables. In general, manufacturers
provide a tolerance range for representative parameters of
electronic components. Typical discrete-component tolerances
are in the range of 1 to 20%.
Inaccuracies in component values result in deviations in
circuit performances, which may be critical or not depending
on specific sensitivities and acceptability margins.
Concerning analog summing circuits, element tolerances
result in deviations from the desired weighting factors. In
particular, we have seen that weighting factors are generally
given by parameter ratios of same-type elements. Using the
case of a resistor ratio Ro /Ri as an example, the actual weight
value can be expressed as

Ro


1+
Ro +
Ro
Ro

Ro

Ri
Ro
Ro

Wi =
=
1
+

=

Ri
Ri +
Ri
Ri
Ri
Ro
Ri
1+
Ri
(25)
Note that relative weight deviations are given by the difference of the relative error of the two resistors. Therefore, extreme deviations may be as large as twice the tolerance of the
components (assumed equal for simplicity), but they can also
be extremely low. Assuming uncorrelated errors in the two
resistors, it is easy to show that the standard deviation of the

weight will be equal to 2 times the tolerance of the resistors. This is a reasonable assumption when discrete components are being employed. However, when integrated circuits
are being formed, same-type components are fabricated simultaneously under extremely similar conditions; therefore,
appreciable correlation exists. In this case, the two error
terms tend to cancel each other, and it is not rare to obtain
accuracies in the order of 0.1% with absolute value tolerances
of about 20%.
Active Element Offset Voltage. Mismatch among ideally
identical devices within active devices (opamps, current conveyors, OTAs) produce deviations in their performance as
well. One of the most representative is the so-called inputreferred offset voltage. Its effect can be analyzed using a random-value dc (direct current) voltage source at one of the input terminals. In analog summing structures, it produces at
the output an additional term that is independent of the input
signals (output offset). As an example, the analysis of the general adder in Fig. 6 results in the following expression for its
output voltage:

Vo =

N

Wi+Vi

i=1

M


W jV j

1+

j=1

M


W j

Eos

(26)

j=1

where Eos is the opamp offset voltage.

Active Elements Dynamic Response. The dynamic response
of active elements is reflected in the dynamic behavior of analog summing circuits. The corresponding analysis requires a
dynamic model of the specific active device. We will consider
again the opamp-based generalized adder in Fig. 6 as an example. Using a dominant-pole linear model for the opamp, we
obtain the following expression:



N
M




1
+



Vo (s) =
Wi Vi (s)
W j V j (s)
s
i=1
j=1
1+
sp

(27)

where sp is the dominant pole of the summing circuit given by

sp = 

GB

M

1+
Wj

(28)

j=0

and GB is the gain-bandwidth product of the opamp (see OPERATIONAL AMPLIFIERS).

The application of a step voltage at one of the input signals

will thus result in an exponential response characterized by
a time constant



M
N


1

1
1

1+
=
=
Wj =
Wi+
sp
GB
GB
j=0
i=0

(29)

where we have used the design Eq. (7). Note that system response-time increases with the sum of either positive or negative weights. This is a general statement valid for analog
summing circuits based on other active devices.
An important nonlinear limitation of operational amplifiers, known as slew rate, establishes an upper bound for the

SUMMING CIRCUITS

slope of the output voltage waveform. In cases where the linear model predicts faster variations, the opamp will respond
with a constant slope independent of the input signal.
Finite Opamp Open-Loop Gain. Opamps finite low-frequency gain A0 produces a uniform attenuation of summingcircuit weight values. As an example, analysis of the generalized adder in Fig. 6 yields the following result:
N

Vo =

Wi+Vi

i=1

1+

1
A0

M

W j V j

j=1

1+

M

(30)

W j

Introduction

j=0

Wi+Vi

M

i=1

W j V j

j=1

Vo =

1+ 1+

N

Wi+

i=1

M

(31)

W j

j=1

where is the ratio of OTAs output-conductance to transconductance, which is assumed equal for every OTA for simplicity. This is indeed a correct assumption on most practical
cases. Similarly, the analysis of the generalized CC-based
adder in Fig. 9(b) yields
N

Vo =

i=1

Wi+Vi+

M

vices. Input (and output) impedance of active devices results

in uniform weight deviations. Opamp input bias-currents produce output offset, and finite power-supply rejection-ratio
(PSRR) and common-mode rejection-ratio (CMRR) result in
spurious components at the output signal due to power-supply and common-mode signals coupling. High-order parasitic
dynamic effects of active devices could produce stability problems. Finally, electronic noise from active devices and resistors may be relevant in certain applications cases.
DIGITAL ADDERS

Finite Output Impedance of CCs and OTAs. When current

conveyors or operational transconductance amplifiers are
used, their finite output impedance produces a result similar
to that of the finite open loop gain of operational amplifiers.
An analysis of the generalized OTA-based adder in Fig. 11
results in
N

641

W jV j

j=1

1 + Gp /GF

(32)

where Gp is the output conductance of the CCs.

Parasitic Devices. Any real circuit includes, in addition to
the devices employed to implement the desired function,
many other unwanted "devices" such as wiring and contact
resistances, self and mutual inductances among wires, capacitive couplings, and transmission-lines. These parasitic elements may become relevant in certain circumstances, like
high-frequency operation; in integrated circuit design; and, in
general, whenever their electrical parameters are in the
range of nominal devices. In these cases, special circuit techniques and careful routing should be considered.
Feedthrough. In switched-capacitor circuits, the MOS transistors employed as analog switches produce charge-injection
effects on the capacitors employed for charge storage. These
effects can be attenuated using small switches and large capacitors.
Other Error Sources. Nonlinearity of passive and active elements produce distortion on the output signal. A clear example is the output voltage- and current-saturation of active de-

Previous sections focused on analog summing circuits. Digital

adders operate with an essentially different codification of signals and are, therefore, different from their analog counterparts in practically every aspect.
Digital addition follows strict algorithmic rules on abstract
numbers represented by a sequence of digits. In many senses,
the process is identical to human summation of magnitudes
represented by decimal (base 10) numbers. One major difference is the numerical base, which in the vast majority of digital systems is base 2. Numbers are therefore represented by
strings of bits (i.e., digits), whose possible values are either 0
or 1. The most common form of representation of unsigned
numbers is binary magnitudes, which follows the same conceptual rules as decimal representation. An additional difference is related to the representation of signed numbers. For
the purpose of arithmetic operations, the so-called twos complement notation is the most widely used. Finally, an important constraint on digital summing circuits is their fixed
word-length, imposed by hardware realizations, which may
result in truncation or round-off errors depending on the representation employed: fixed-point or floating-point (see DIGITAL ARITHMETIC). In what follows, fixed-point arithmetic is assumed.
Binary-Magnitudes Arithmetic
The addition of two (positive) binary magnitudes A and B can
be performed following the same conceptual rules employed
in hand addition of decimal numbers. Fig. 14(a) illustrates
the procedure, beginning from the right-hand side column,
which represents the least significative bit (LSB) and proceeding toward the most significative bit (MSB) on the left-hand
side.
The sum of any pair of bits ai and bi, each with values 0 or
1, ranges from 0 to 2 and must be represented by a two bits
number commonly denoted as (Ci1 Si), as shown in Fig. 14(b).
The sum-bit Si is already part of the result S A B,
whereas the carry-bit Ci1 must be added to the next column.
Therefore, three bits must be added at each column i: ai, bi
and the carry-bit from the previous column Ci. The sum of
three bits ranges from 0 to 3 and can still be represented with
a two-bits number (Ci1 Si), as shown in Fig. 14(c). Thus, the
process can start from the LSB column, for which C0 0 is
assumed, and proceed toward the MSB in a repetitive manner. This procedure is the underlying fundamental of binary
digital adders.
Basic Circuit Blocks. A digital circuit block realizing the
truth table in Fig. 14(b) is commonly known as a half-adder

642

SUMMING CIRCUITS

0
1
0
Figure 14. Examples of (a) binary addition process, (b) arithmetic addition of two
bits, and (c) arithmetic addition of three
bits.

1
0
0
1

1
0
1
0

Carry
1
A
1
B
0 Sum

(a)

(HA), whereas that defined by Fig. 14(c) is referred to as a

full-adder (FA). Fig. 15(a, b) contain representations for these
two basic building blocks of digital adders. Their implementation can be carried out following any general procedure for
Boolean functions realization.
The functionality of a HA can be expressed as two Boolean
functions:
SHA
= ai b i + ai b i = ai b i
i

HA
Ci+1
= ai b i

(33)

from which an implementation using two digital gates, an

XOR and an AND, is straightforward, as shown in Fig. 16.
Because the input-to-output signal path goes through just one
gate, the propagation delay of this realization corresponds to
one gate level.
An FA can be implemented using two HAs and one OR
gate, as shown in Fig. 17(a). This realization requires a reduced number of gates but, on the other hand, exhibits a delay of three gate levels. Other implementations can be built
on the basis of the Boolean expressions for the two outputs of
a FA,

SFA
i = ai bi Ci + ai bi Ci + ai bi Ci + ai bi Ci
= ai bi Ci
FA
Ci+1

= ai bi + bi Ci + ai Ci

Si

(35)

bi

HA
bi

Ci + 1
(a)

ai

00

01

01

10

01

11

10

00

01

10

01

01

10

11

10

(b)

(c)

Serial and Parallel Adders. The addition of two n-bit binary

numbers can be carried out serially or in parallel. A serial
adder, shown in Fig. 18, contains one single FA and a flipflop and is controlled by a clock signal. The two words A and
B are sequentially added on a bit-to-bit basis, beginning with
the LSB, for which the flip-flop must be initially set to zero.
Consecutive clock cycles produce consecutive bits of the resulting sum S, as well as a carry-bit, which is stored in the
flip-flop and employed as input to the FA in the next clock
cycle. The summation of the two words requires n clock cycles.
Therefore, serial adders constitute a slow solution in general.
On the other hand, they are highly efficient in terms of
hardware.
Parallel adders can be regarded as the opposite alternative, realizing fast additions at the expense of an increased
hardware cost. Figure 19 shows an intuitive realization of a
parallel adder, commonly known as serial-carry and also as
ripple adder. Its hardware cost is of n full adders. The carrybits are transmitted in a chain from the FA corresponding to
the LSB toward the MSB. This signal path determines the
response time of the parallel adder, which can be described
as
tsp = ntFA

(36)

where tFA is the response time of one FA. The response times
of both the serial and the parallel adders are proportional to
the number of bits. However, because the period of the clock
signal employed in the serial adder must be at least several
times larger than tFA, it is clear that parallel adders are
faster. Still, parallel adders may be too slow for certain applications, especially for long digital words (large n). Certain advanced architectures overcome these problems at the expense
of additional hardware (see High-Performance Digital
Adders).
Addition and Substraction of Signed Numbers
Addition-Substraction Equivalence. The addition and the
substraction of two signed numbers can both be formulated
on the basis of a summing operation, by simply changing the
sign of one of the operands when needed. Fig. 20 shows a
conceptual flow diagram of an adder/substracter circuit based

Si

Ci

bi 0 0

(Ci + 1 Si)2 = ai + bi + Ci

Ci + 1

FA
Ci + 1

Ci

(Ci + 1 Si)2 = ai + bi

(34)

Figure 17(b) shows an implementation using double-rail input

signals and two levels of NAND gates, and Fig. 17(c) shows
an implementation using single-rail signals using just twoinput NAND gates, with a propagation delay of six gate levels. Many other alternatives exist.
A careful evaluation of these alternatives in terms of cost
and speed should take into account the diverse complexity
(transistor count) and propagation delay of different gates. In
general, NAND, NOR, and INV gates are faster and simpler,
whereas AND, OR, and especially XOR and NXOR gates are
more complex and slower. The requirement of double-rail inputs signals may result in additional cost and delay, depending on the specific case.

ai

ai

ai
bi

ai
bi

(b)

Figure 15. Basic digital-adder modules representation: (a) half

adder and (b) full adder.

Si
Figure 16. Half adder implementation.

SUMMING CIRCUITS

Si
HA
Ci+1

Si
HA
Ci+1

ai
bi
Ci

Si

ai

ai
bi
Ci

Ci +1

bi
ai
Si

ai
bi
Ci

(a)

643

Ci +1

Ci
bi
Ci

ai
bi
Ci

(b)
Ci

ai

Si

bi

Ci +1
(c)
Figure 17. Alternative implementations of a full adder: (a) with two HAs and one OR gate, (b)
with double-rail inputs and two levels of NAND gates, (c) with two-input NAND gates and six
levels of delay.

on this approach. Signal a/s controls whether the sign of operand B is changed or not before the summation is performed.
The specific meaning of a sign-inversion operation depends
on the representation being used for the signed numbers, as
described in Fig. 20.
In a sign-magnitude (SM) representation, a sign inversion
is achieved by complementing just the sign bit, whereas the
rest of the bits remain unchanged. In ones complement (C1)
arithmetic, a sign inversion is obtained complementing every
bit in the word. Finally, in twos complement (C2) arithmetic,
a sign inversion requires adding one unit to the word obtained
by complementing every bit.
Signed-Numbers Addition in Twos Complement Arithmetic. It
can be shown that the addition of signed numbers in twos

. . . 0 1 1(0) C

complement representation coincides with the (positive) binary magnitude summation of their digital codes. Fig. 21
shows examples covering the four possible cases of operand
signs. The final (MSB) carry-bit Cn is neglected for the purpose of evaluating the result. It may be used, however, together with Cn1 to detect overflow. The possibility of using
simple binary adders, like those described previously, for the
summation of signed number has turned twos complement
arithmetic the most widely used in digital operators, and the
only one considered in what follows.
Twos Complement Adder-Subtracter Circuit. Figure 22(a)
describes a digital adder-subtracter, controlled by signal a/s,
following the diagram illustrated in Fig. 20. It is based on
a parallel binary-magnitude adder, and a parallel transfer/
complement (B/B) block. The realization and functionality of

. . . 0, 1, 1, (0)

. . .1 0 0 1 A

Ci

. . .0 0 1 1 B

. . . 0, 0, 1, 1

bi

. . .1 1 0 0 S

. . . 1, 0, 0, 1

ai

Si

. . . 1, 1, 0, 0

FA
Ci +1

D
. . . 0, 1, 1
Ck

Figure 18. Serial adder and summation

example. t indicates increasing time sequence.

644

SUMMING CIRCUITS

an 1 bn 1 Cn 1

FA

Figure 19. Parallel adder with serial carry (ripple

adder).

a2 b2 C2

a1 b1 C1

FA

FA

FA

C3 S2

C2 S1

C1 S0

Cout = Cn Sn 1

a0 b0 C0 = Cin

A, B
a(0)

s(1)

(a/s)

SM: yn 1 = bn 1; yi = bi, i = 0, 1, ..., n 2

Y= B

C1: Y = C1(B); yi = bi, i = 0, 1, ..., n 1

Y=B

C2: Y = C2(B) = C1(B) + 1 = B + 1

Figure 20. Flow diagram of a signed-number adder/subtracter circuit.

F = A +Y

A = 0100
Cn

Cn 1
an 1 an 2 ... a1 a0
bn 1 bn 2 ... b1 b0

A = 0010

(+ 4)

0010

(+ 2)

0010

(+ 2)

1100

( 4)

0110

(+ 6)

1110

( 2)

B = 1110

A = 1100

11

F=A+B

B = 1100

0100

A = 0100

Fn 1 Fn 2 ... F1 F0

B = 0010

B = 1110

11

0100

(+ 4)

1100

( 4)

1110

( 2)

1110

( 2)

0010

(+ 2)

1010

( 6)

Figure 21. Four possible cases of arithmetic addition of signed numbers addition in twos complement representation. The result is correct in every case after neglecting the carry bit.

B
n

a/s

Bn 1

a/s

B/B circuit

Y
Yn 1

Co

Parallel adder [n]

B0

Bn 2

Ci

a/s

Yn 2

Y0

a/s = 0

Y=B

a/s = 1

Y=B
(b)

F
(a)
Figure 22. (a) Adder/subtracter circuit for signed numbers in twos complement notation and
(b) transfer/complement (B/B) circuit.

SUMMING CIRCUITS

this last circuit block is described in Fig. 22(b). If a/s 0, the

B/B circuit simply transfers its input B to its output, and the
parallel adder, with the initial (LSB) carry-bit Ci set to 0, performs the addition of the two operands A B. The result is
correct for signed twos complement numbers and also for binary magnitudes. On the other hand, if a/s 1, the B/B circuit complements every bit bi of operand B and transmits the
result to the full adder, which now sees a 1 at Ci. The result
is that A is added with B 1, that is, B in twos complement
representation; therefore, the full adder produces the difference A B as expected.
Overflow Problems
An n-bits binary magnitude may take values ranging from 0
to 2n 1, and the sum of two such magnitudes from 0 to
2n1 2. Similarly, the possible values of an n-bits signednumber in twos complement representation range from
2n1 to 2n1 1, and the sum or difference of two such numbers from 2n to 2n 2. This means that the n-bits output of
the adder-subtracter circuit in Fig. 22 will be unable to show
the correct result in certain cases. This phenomenon is commonly known as overflow and is obviously something that
should be detected. Furthermore, it would be convenient to
determine the correct result also in these cases.
When unsigned binary magnitudes are being added, the
MSB carry-bit Cn provides a flag-signal for overflow occurrences. It can also be shown that function
V = Cn Cn1

(37)

which can be obtained at the expense of an additional XOR

gate, constitutes a valid overflow flag for the addition and the
subtraction of signed numbers in twos complement representation. Both signals are active when high.
In the event of overflow, and regardless the operation being performed, the correct result can be obtained, in its proper
representation (binary magnitude or twos complement), from
the n 1 bits number compound by Cn (the new MSB or the
new sign bit) and the n-bits output-word of the circuit in
Fig. 22.
High-Performance Digital Adders
As in most digital processing circuits, the main concern in the
optimization of digital adders is to increase their operation
speed. Response time reductions can be achieved through improvements in the basic digital adder circuit block (the FA),
through algorithmic or architectural modifications, or a combination of both. Parallel ripple adders are often used as a
reference for the evaluation of advanced solutions, which in
general focus on the elimination or at least the attenuation of
the constraint imposed by the long signal path of carry signals from the least to the most significative bit.
Most modifications to the conventional implementations of
the FA circuit block involve a reduction of the capacitive load
of the carry signal [e.g., the so-called mirror, dynamic, and
Manchester-adders (5)]. FA blocks with modified I/O signals
are employed in the carry-completion adder architecture (6),
yielding a reduced average response time.
Most architectural modifications rely on a segmentation of
the bit-chain in smaller groups. One alternative, known as
the carry-bypass adder (5), is based on evaluating within each

645

group whether an eventual carry input Ci would propagate

through the group. If it does, Ci is directly transferred to the
carry output Co. Otherwise, Ci can be ignored, and Co is computed from the group input bits. A similar strategy results in
the so-called carry-skip adder (6). An alternative architecture,
the linear carry-select adder (5), computes within each group
two results corresponding to the two possible values of Ci, and
selects one of them after receiving its actual Ci value. A modification of this last architecture, the square root carry-select
adder (5), employs increasing-length groups and results in a
propagation type proportional to the square root of the number of bits.
Carry look-ahead adders (6,7) employ a significative different approach. Their architecture allows all carry-bits to be
obtained simultaneously at the expense of a rapidly increasing complexity with the number of bits. In practice, this limits
the number of bits to about four, forcing the use of combined
approaches for larger word lengths.
Finally, a pipeline adder architecture (5) results in a high
summing throughput, although the propagation time of individual summations may be larger than with the standard ripple adder.
Other alternatives relying on innovative circuit techniques
(e.g., threshold gates, multivaluated-logic) or technologies
(e.g., optical processors) do exist, but they will not be treated
here.

BIBLIOGRAPHY
1. R. Unbehauen and A. Cichocki, MOS Switched-Capacitor and Continuous-Time Integrated Circuits and Systems, New York: SpringerVerlag, 1989.
2. R. Gregorian and G. C. Teme, Analog MOS Integrated Circuits for
Signal Processing, New York: Wiley-Interscience, 1986.
3. F. Maloberti, Switched-capacitor building blocks for analogue signal processing, Electronics Lett., 19: 263265. 1983.
4. K. Nagaraj et al., Reduction of finite-gain effect in switched-capacitor circuits, Electron. Lett., 21: 644645, 1985.
5. Jan M. Rabaey, Digital Integrated Circuit: A Design Perspective,
Upper Saddle River, NJ: Prentice-Hall, 1996.
6. Amos R. Omondi, Computer Arithmetic Systems. Algorithms, Architectures and Implementations, Upper Saddle River, NJ: PrenticeHall, 1994.
7. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design. A
Systems Perspective, Reading, MA: Addison-Wesley, 1985.

RAFAEL DOMINGUEZ-CASTRO
SERVANDO ESPEJO
ANGEL RODRIGUEZ-VAZQUEZ
CARMEN BAENA
MANUEL VALENCIA
University of Seville, IMSE-CNMCSIC

SUNPHOTOMETERS. See PHOTOMETERS.

SUPERCAPACITORS. See CAPACITOR STORAGE.
SUPERCONDUCTING ANALOG AND DIGITAL MICROWAVE COMPONENTS. See SUPERCONDUCTING
MICROWAVE TECHNOLOGY.

SWITCHED CAPACITOR NETWORKS

165

SWITCHED CAPACITOR NETWORKS

The requirement for fully integrated analog circuits prompted
circuit designers two decades ago to explore alternatives to
conventional discrete component circuits. A sound alternative
was developed, a switched-capacitor (SC). The basic idea was
replacing a resistor by a switched-capacitor CR simulating a
resistor. Thus, this equivalent resistor could be implemented
with a capacitor and two switches operating with a two-phase
clock. This equivalent resistor is equal to 1/f CCR, where f C is
the sampling (clock) frequency. SC circuits consist of
switches, capacitors, and operational amplifiers (op amps).
They are described by difference equations in contrast to differential equations for continuous-time circuits. Concurrently
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

166

SWITCHED CAPACITOR NETWORKS

the mathematical operator to handle sample-data systems,

such as switched-capacitor circuits is the z-transform, and the
Laplace transform for continuous-time circuits. A host of
practical properties of SC circuits have made them very popular in industry:

approach. Furthermore, many practical analog/digital

(A/D) converters use SC implementations.
FUNDAMENTAL BUILDING BLOCKS
The fundamental building blocks in SC circuits are voltagegain amplifiers, sample/holds integrators, and multipliers. A
combination of these blocks is interconnected to yield a number of useful circuits.

1. The time constants (RC products) from active-RC circuits become capacitor ratios multiplied by the clock period TC, that is,



1 C
C
=
= TC
(1a)
fC CR
CR

Gain Amplifiers
The gain amplifier is a fundamental building block in
switched-capacitor circuits. A voltage amplifier is implemented as shown in Fig. 1(a). The switched-capacitor resistor
gives a dc path for leakage current but reduces further the
low-frequency gain. A detailed analysis of this topology shows
that the dc output voltage is equal to Ileak T/CP, with CP the
parasitic capacitor associated with the feedback path. The
leakage current Ileak in switched-capacitor circuits is a result
of the diodes associated with the bottom plate of the capacitors and the switches (drain and source junctions). This leakage current is about 1 nA/cm2. Using typical analytical methods for switched-capacitor networks, it can be shown that the
z-domain transfer function of this topology becomes

where T Tc 1/f C is the sampling frequency. The

accuracy of is expressed as
dTC
d
dC dCR
=

TC
C
CR

(1b)

Assuming that TC is perfectly accurate gives

dC dCR
d
=

C
CR

2.

3.

4.

5.

(1c)

Because the two capacitors C and CR are built close together, d / compatible with conventional CMOS technologies is in the neighborhood of 0.1%.
Ordinarily the load of an SC circuit is mainly capacitive. Therefore the required low-impedance outputstage op amp is no longer required. This allows the use
of a single-stage operational transconductance amplifier
(OTA) which is especially useful in high-speed applications. Op amp and OTA are not differentiated in the
rest of this article.
Reduced silicon area, because the equivalent of large resistors is simulated by small capacitors. Moreover, positive and/or negative equivalent resistors are easily implemented with SC techniques.
Switched-capacitor circuits are implemented in a digital
circuit process technology. Thus, useful mixed-mode signal circuits are economically realized in standard MOS
technology with available double-poly.
The SC design technique has matured. In the audio
range, SC design techniques are the dominant design
1

H(z) =

V0 (z) CS
1 z1


=
Vi (z)
CI 1 1 C P z1
C

with z ej2fT. For low frequencies, z 1, the transfer function

is very small, and only for higher frequencies does the circuit
behave as a voltage amplifier.
A practical version is shown in Fig. 1(b). During 2, the op
amp output voltage is equal to the previous voltage plus the
op amp offset voltage plus V0 /AV, where AV is the open-loop dc
gain of the op amp. In this clock phase, both capacitors, CI
and CS, are charged to the voltage at the inverting terminal
of the op amp. This voltage is approximately equal to the op
amp offset voltage plus V0 /AV. During the next clock phase,
the sampling capacitor is charged to CS(VI V), but because
it was precharged to CSV, the injected charge to CI is equal
2

Cl

Cp

2
CH

2
Vi

Cl

Cs

Vo
+

Vi

Cs

Vo
+

Cspike
Figure 1. Voltage gain amplifiers: (a)
with dc feedback; (b) available during both
clock phases.

(a)

(2)

C
z1
= S
CI z (1 CP /CI )

(b)

SWITCHED CAPACITOR NETWORKS

Vin

+
CH

(a)

2
(n1)

1
Time (T)

(n1/2)
(b)

Figure 2. Open-loop S/H: (a) simple S/H buffer; (b) timing diagram.

to CSVI. As a result of this, the op amp output voltage is equal

to (CI /CS)VI. Therefore, this topology has low sensitivity to
the op amp offset voltage and to the op amp finite DC gain. A
minor drawback of this topology is that the op amp stays in
the open loop during the nonoverlapping phase transitions,
producing spikes during these time intervals. A solution for
this is to connect a small capacitor between the op amp output and the left-hand plate of CS.
Sample-and-Hold
The function of a sample/hold (S/H) is to transform a continuous-time signal into a discrete-time version. A simple S/H circuit is shown in Fig. 2(a). Its clock phases are shown in Fig.
2(b). This open-loop architecture is attractive because of its

167

simplicity and potential speed. It is often convenient to add

an input buffer stage to the S/H circuit. The acquisition time
depends on the tracking speed and input impedance of the
input buffer, the on-resistance of the switch, and the value of
the holding capacitor. The hold settling time is governed by
the settling behavior of the buffer. A drawback of this architecture is the linearity requirements imposed on the buffers
as a consequence. This limits the speed. Moreover, the inputdependent charge injected by the sampling switch onto the
hold capacitor yields an undesirable source of nonlinearity.
This type of S/H architecture achieves a linearity to nearly 8
bits. A full-period S/H signal is obtained by either a cascade
of two S/H circuits of Fig. 2, driven by opposite clock phases,
or by a parallel connection of two simple S/H circuits, output
sampling switches, and a third (output) buffer as illustrated
in Fig. 3. Structures with closed-loop connections are also
used. Figure 4(a) illustrates a popular architecture often encountered in pipelined A/D converters. In the acquisition
mode, switches associated with 1 and 1 are on whereas 2
is off, and the transconductance amplifier acts as a unity-gain
amplifier. Thus the voltage across CH is the input voltage and
the virtual ground. In the transition to the hold mode, the
switches associated with 1 and 1 turn off one after the
other. Then 2 turns on. One advantage of this architecture
is that because 1 turns off first, the input-dependent charge
injected by 1 onto CH does not appear in the held output voltage. Besides, because of the virtual ground, the channel
charge associated with 1 does not depend on the input signal.
Yet another advantage is that the offset voltage is not added
to the output. A disadvantage is that a high-slew-rate transconductance amplifier is required. Figure 4(b) shows a doublesampling S/H circuit. The S/H operation is valid for both
clock phases.
Multipliers
One difficulty in an SC multiplication technique is that continuous programmability or multiplication of two signals is
not available. A digitally programmable coefficient is realized
with a capacitor bank, as shown in Fig. 5. The resolution of
this technique is limited because the capacitor size increases
by 2k where k is the number of programming bits.

C1

+
Vin

V0

CH

+
C2
Figure 3. Double-sampling S/H architecture.

168

SWITCHED CAPACITOR NETWORKS

2
CH

1'
Vin

V0

Gm

CH

Vin

V0

1
2

(a)

(b)

Figure 4. (a) SC S/H single-ended. (b) Double-sampling S/H.

When continuous programmability is required, a continuous multiplier is used. Despite many reported multiplier circuits, only two cancellation methods for four-quadrant multiplication are known. Because a single-ended configuration
does not completely cancel nonlinearity and has poor PSRR,
a fully differential configuration is often necessary in a sound
multiplier topology. The multiplier has two inputs. Therefore
there are four combinations of two differential signals, that
is (x, y), (x, y), (x, y), and (x, y). The multiplication and
cancellation of an unwanted component are achieved by either of the following two equalities:
4xy = [(X + x)(Y + y) + (X x)(Y y)]
[(X x)(Y + y) + (X + x)(Y y)]

(3a)

or

8xy ={[(X + x) + (Y + y)] + [(X x) + (Y y)] }

2

{[(X x) + (Y + y)]2 + [(X + x) + (Y y)]2 }

2 1C

2 2C

2 kC

Figure 5. Digitally programmable capacitor bank.

(3b)

These two approaches are depicted in Fig. 6. The topology of

Fig. 6(a) is based on two-quadrant multipliers. Fig. 6(b) is
based on square law devices. X and Y are arbitrary constant
terms and are not shown in Fig. 6.
MOS transistors are used to implement these cancellation
schemes. Let us consider a simple MOS transistor model
characterized in its linear and saturation regions, respectively by the following equations:




V
Id = K Vgs VT ds Vds
2
for |Vgs | > |VT |, |Vds | < |Vgs VT |
Id =

K
(Vgs VT )2
2

for |Vgs | > |VT |, |Vds | > |Vgs VT |

(4a)
(4b)

where K oCox W/L and VT are the conventional notations

for the transconductance parameter and the threshold voltage
of the MOS transistor, respectively. The terms VgsVds in Eq.
2
in Eq. (4b) are used to implement Eqs. (3a) and
(4a) or Vgs
(3b), respectively. Next we discuss a sound combination of a
continuous-time multiplier and an SC integrator. In an SC
circuit, the multiplier precedes the integrator, thus forming a
weighted integrator. The output of the multiplier is a voltage
signal or a current signal. In the case of a voltage-mode multiplier, the configuration of the SC integrator is identical with
a conventional integrator, as shown in Fig. 7. The transconductance multiplier is connected directly to the op amp, as
shown in Fig. 8. A common drawback in a weighted integrator
is the multiplier offset because it is accumulated in the integrator. This problem is more serious for the transconductance mode.
The topology in Fig. 8 with the multiplier implemented by
a FET transistor operating in the linear region is known as
MOSFET-C implementation. Instead of using a single transistor, a linearizing scheme uses four transistors as shown in
Fig. 9.
The four FETs in Fig. 9(a) are operating in the linear region, and depletion FETs are often used in many cases to

SWITCHED CAPACITOR NETWORKS

169

y
xy
x

xy

( )2

x + y

( )2

x y

( )2

xy

( )2

4xy

xy

x+y

xy

x2 + 2xy + y2

x2 2xy + y2
8xy

x2 + 2xy + y2
x2 2xy + y2

Figure 6. Four-quadrant multiplier topologies: (a) using single-quadrant multipliers; (b) Using square devices.

y
(a)

(b)

overcome the transistor threshold limit. The drain current of

each FET is given by




v+
v+
x
d
+
+
(v+
id1 = K v+
y vx VT
d vx )
2



v+
v
x
d
+
+
(v
id2 = K v

y
x
T
d vx )
2



v
v+
x
d

id3 = K v
(v+

y
x
T
d vx )
2
and

(5)


v
v
x
d

(v
id4 = K v+
T
y
x
d vx )
2

id = (id1 id2 ) = Kvx (v+

y vy )

Because of the closed loop, the voltages v and v are virtually

equal and fixed by the common-mode feedback circuit in the
op amp. The differential current applied to the integrator is
expressed by

K
C

vx ( )vy ( ) d

(7)

where vx vx vx, vx vx vx, and vy vy vy. If vx and

vy are sampled signals, then the circuit operates as a discretetime MOSFET-C circuit. The integrator output yields
n
KT 
vo (nT ) =
vx (k)vy (k)
C k=0

(8)

where T is the time period of the sampled system.

(10)

id = (id1 id2 ) = Kvx vy

(11)

A switched, single-ended implementation using three op

amps is achieved, as shown in Fig. 11. C1 is reset at 1, and
then the difference of the two integrators is sampled at 2.
The charge on C2 is transferred at the next 1. The output
voltages of the two integrators are given by





1
vx
(vx ) dt
K vy vx VT
C1 T
2

TK 
vx  
vx
vx vy vx + VT
=
C1
2




1
vx
v2 =
(vx ) dt
K vx VT
C1 T
2
TK  
vx  
vx
vx + VT
=
C1
2
v1 =

Vy
Vx

(9)

If depletion-mode FETs are used, then the vy is referred to

the ground, as shown in Fig. 10. The differential current is
given by

(6)

The common-mode current injected into the integrator is canceled out by the common-mode feedback. The integrator output is given by

vo (t) = v+
o (t) vo (t) =




vx
(vx )
id1 = K v
y vx VT
2



vx
(vx )
id2 = K v+
y vx VT
2
and the differential current is given by

id = (id1 + id3 ) (id2 + id4 ) = K(v+

x vx )(vy vy )

Several modifications are possible from this prototype. In

the balanced differential op amp, the drain voltage vd is virtually grounded because the common-mode voltage is fixed to
ground. In this case, only two FETs are required, as shown in
Fig. 9(b). The drain current of each FET is given by

(12)

Vy
Vm

Vx

im

Vout

Figure 7. Weighted integrator with voltage-mode multiplier.

Vout

Figure 8. Weighted integrators with transconductance multiplier.

170

SWITCHED CAPACITOR NETWORKS

v y+
vy

vx

vy

C1

v o+

v x

vo

v1
C2

vx

C3

vo

v2

C1

v y+

(a)

Figure 11. An SC weighted integrator.

v y+

v o+

v o

reset at 1. Its output is sampled at 2. Then, the voltage sampled in C2 yields the expression

vx
+





1
vx
(vx ) dt
K vy vx VT
C1 T
2

vx  
TK 
vx
vx vy vx + VT
=
C1
2

vC (A ) =
2

v y
(b)
Figure 9. (a) Multiplier implemented by MOSFET-C techniques.
(b) A MOSFET-C multiplier with balanced differential op amp.

During the second phase B, T the gate input is connected to

vy. Integrator A is reset at 1. At 2, v1 becomes
vC (B ) =
2

where T is the period defined as the time difference between

the end of 1 and the end of 2. The voltage across C2 is given
by
vC =
2

TK
vx vy
C1

TK  
vx  
vx + Vt
vx
C1
2

Q2 = C2 [v1 (B ) v1 (B )] =

TKC2 z1/2
vo =
vx ( z)vy ( z)
C1C3 1 z1

(14)

A weighted integrator is also implemented with two op

amps and one FET. It requires several additional clocks. Basically, it multiplexes the FET and the op amp by substituting
two FETs and two integrators, as shown in Fig. 12.
The operation involves two additional clock phases. During
phase A, the gate input is connected to vy. Integrator A is

(16)

One node of C2 is connected to integrator A and the other

node is connected to integrator B. The total charge into integrator B is given by

(13)

At 1, the charge in C2 is transferred to C3. The output of the

integrator becomes

(15)

TKC2
vx vy
C1

(17)

A single FET SC weighted integrator does not have an offset due to an FET mismatch. However, all transconductanceweighted integrators depend on the clock period T. Unfortunately, a jitter-free clock is impossible to implement. This
jitter causes offset and incomplete cancellation, even in the
circuit shown in Fig. 12. Next an SC weighted integrator with
voltage-mode offset cancellation is described.
The multiplier offset caused by device mismatch in the
multiplier is the most critical limitation in continuous-time
weighted SC integrators. A simple and effective offset cancel-

Integrator A

vy

Integrator B

v o+

vx

vy
vx

v o

C1

C3

2 C2
v1

2 B
2 A

Figure 12. Single FET SC weighted integrator.

Figure 10. Ground-referenced MOSFET-C multiplier.

vo

SWITCHED CAPACITOR NETWORKS

of (x, y), (x, y), (x, y), (x, y) at each clock phase 1, 2, 3,
4, respectively.
At the end of phase 4, CI contains

Reset

x+
x

v m+ 1

CH

CI

CH

v m

1
A

2
1

+
A

+
CI

171

2 B

vout ( phase 4) = 4K

Vout+

CH
xy
C1

(21)

2 B
Vout

x and y should be kept constant during the four phases. If the

four phases are considered unit time period than the
weighted integrator is characterized as follows:
vout ( z) = 4K

Reset

1
CH
x( z)y( z)
C1 1 z1

(22)

Note that multiplier offset cancellation is obtained in the integrator.

Figure 13. A switched-capacitor weighted integrator with offset cancellation.

lation scheme using SC techniques is discussed next. The

multiplier offset is modeled by
z = K( x + xo )( y + yo ) + zo

(18)

where K is a multiplication constant, xo and yo are offsetrelated device mismatches at the input stage of the x and y
signals, respectively, and zo is the offset caused by device mismatch at the output stage. This offset is canceled by four combinations of input signal polarity as follows:

zx,y

Integrators
Standard stray-insensitive integrators are shown in Fig. 15.
In sampled data systems, input and output signals are sampled at different times. This yields different transfer functions. We assume two-phase nonoverlapping clocks, an odd
clock phase 1 and an even clock phase 2. Thus, for a noninverting integrator, the following transfer functions are often
used:

= K( x + xo )( y + yo ) + zo

zx,y = K(x + xo )( y + yo ) + zo
zx,y = K(x + xo )(y + yo ) + zo

H oe ( z) =

(19)

zx,y = K( x + xo )(y + yo ) + zo

(23a)

a p z1/2
Voe ( z)
ap
=
= 1/2
Vino ( z)
1 z1
z z1/2

(24a)

For an inverting integrator,

Then the offset is canceled out similarly to a nonlinearity cancellation in a multiplier, that is,
( zx,y zx,y ) + (zx,y zx,y ) = 4Kxy

a p z1
Voo ( z)
ap
=
=
o
1
Vin ( z)
1z
z1

H oo ( z) =

H oo ( z) =

an
Voo ( z)
an z
=
=
o
1
Vin ( z)
1z
z1

(23b)

(20)

This scheme is implemented with a switched-capacitor circuit, as shown in Fig. 13. 1 and 2 are nonoverlapping clock
phases. At 1, the multiplier output is sampled and is held in
CH. At 2, one node of CH is connected to the multiplier output
whereas the other node is connected to the integrator input.
Then, the charge is injected into the integrating capacitor CI.
The voltage across CI, after the clock 2, becomes [vm(2)
vm(1)] where vm is the multiplier output voltage at the given
clock phase. The switches (1 2 and A B), at the multiplier input nodes, change input signal polarities. Using clocks
shown in Fig. 14, the multiplier input is given as a sequence

1
Vin

ap

Vo

V oe

(a)
C

Phase 1 2

3 4

1
2

Vin

V oo

an C

A
B
Figure 14. Clock phase diagram.

V oe

(b)
Figure 15. Conventional stray-insensitive SC integrators: (a) noninverting; (b) inverting.

172

SWITCHED CAPACITOR NETWORKS

C4

1
CM

C3

C2

C1

V in

V ino

Vo

CB

C1

2( 1)

1( 2)

Ch

V oo

Figure 17. Offset and gain-compensated integrator.

Figure 16. An inverting SC integrator with reduced capacitance
spread.

and
H oe ( z) =

an z1/2
Voe ( z)
an
=

= 1/2
Vino ( z)
1 z1
z z1/2

(24b)

where z1 represents a unit delay. A crude demonstration,

showing the integrative nature of these SC integrators in the
s-domain, is to consider a high sampling rate, that is, a clock
frequency ( fc 1/T) much higher than the operating signal
frequencies. Thus, let us consider Eq. (23a) and, assuming a
high sampling rate, we can write a mapping from the z- to
the s-domain:
z 1 + sT

age. The voltage across Ch compensates for the offset voltage

and the dc gain error of the op amp. Note that the SC integrator of Fig. 17 can operate as a noninverting integrator if
the clocking in parenthesis is employed. CM provides a timecontinuous feedback around the op amp. The transfer function, for infinite op amp gain, is given by
H oo ( z) =

(25)

(26)

This last expression corresponds to a continuous-time, noninverting integrator with a time constant of T/ap 1/f cap, that
is, a capacitance ratio times the clock period.
In many applications the capacitor ratios associated with
integrators are very large, thus the total capacitance becomes
excessive. This is particularly critical for biquadratic filters
with high Q, where the ratio between the largest and smallest
capacitance is proportional to the quality factor Q. A suitable
inverting SC integrator for high Q applications is shown in
Fig. 16. The corresponding transfer function is given by
C1C3
1
V e ( z)
=
H ( z) = oo
Z1/2
Vin ( z)
C2C4 1 z1
oe

V0e =

C1 e
C
C
1
z1
Vi 2
Vie + 3
Ve
1
1
2
CF
CF 1 z
CF 1 z1 i 3

(29)

Observe that the capacitor C3, and switches are the implementation of a negative resistor. Also note that if Vei2 is equal
to Ve0, this connection makes the integrator a lossy one. In
that case Eq. (29) is written


C
1+ 2 z1
C
1
C
CF
= 1 Vie + 3
Ve
V0e
z1
CF 1 CF z 1 i 3
for Vie = V0e
2

Vi

Vi

C2

2
Vi

(30)

C1

(27)

where C4 C4 C3. This integrator is comparable in performance to the conventional circuit of Fig. 15, in terms of stray
sensitivity and finite-gain error. Note from Eq. (27) that the
transfer function is defined only during 2. During 1, the circuit behaves as a voltage amplifier. Thus high slew-rate op
amps could be required. A serious drawback in the integrator
of Fig. 16 is the increased offset compared with standard SC
integrators. In typical two-integrator loop filters, however, the
other integrator is chosen to be offset and low dc gain-compensated, as shown in Fig. 17. The SC integrator integrates
by C1 and CB, and the hold capacitor Ch stores the offset volt-

(28)

Furthermore, if the dc offset is tolerated in certain applications, an autozeroing method is used to compensate for the dc
offset. Next we discuss a general form of a first-order building
block (see Fig. 18). The output voltage is expressed as

Then
1
a p

H(s) =

=
z 1 z
(T/a p )s
= 1+sT

C1
Voo ( z)
=
Vino ( z)
CB (1 z1 )

C3

CF

Figure 18. General form of a first-order building block.

Vo

SWITCHED CAPACITOR NETWORKS

C3

C4
CA

Vi

C1

CB

C2

173

V oe

C5
C6
Figure 19. An SC biquadratic section.

The building block of Fig. 18 is the basis of higher order filters. An illustrative example follows.
SC Biquadratic Sections
The circuit shown in Fig. 19 implements any pair of poles and
zeros in the z-domain. For CA CB 1,

H ee ( z) =

V0e ( z)
(C + C6 )z2 + (C1C2 C5 2C6 )z + C6
= 25
e
Vin ( z)
z + (C2C3 + C2C4 2)z + (1 C2C4 )
(31)

In particular cases, this capacitance spread is prohibited. For

such cases the SC integrators shown in Figs. 16 and 17 replace the conventional building blocks. This combination
yields the practical SC biquadratic section shown in Fig. 20.
This structure offers reduced total capacitance and also reduces the effect of the offset voltage of the op amps. Note that
the capacitor Ch does not play an important role in the design,
and can be chosen with a small value. For the poles, comparing z2 (2 r cos )z r2 and the analysis of Fig. 20,

C2C3
= 1 + r2 2 r cos
CA + CB
CA C2C4
= 1 r2
CA CACB

Simple design equations follow:

Low-pass
High-pass
Band-pass

C5 = C6 = 0
C1 = C5 = 0
C1 = C6 = 0

C2C4 = 1 r2

(32a)

C2C3 = 1 2 r cos + r2

(32b)

For equal voltages at the two integrator outputs and assuming that Q is greater than 3 and a high sampling rate (
odT 1),

C4 =

(34b)

Comparing the coefficients of the denominator of Eq. (31) with

the general expression z2 2 r cos r2, we obtain the following expressions:

C2 = C3 =

(34a)

1 + r2 2 r cos
= 0 T
d

1 r2 1
=
C2
Q

(32c)
(32d)

The capacitance spread for a high sampling rate, CA 1, and

a high Q is expressed as





Cmax
C1 C1
1
,Q
= max
,
= max
Cmin
C2 C4
0 T
d

(33)

where CA1 CA CA. Simple design equations are obtained

by assuming a high sampling rate, a large Q, and C2 C3
C4 CA Ch 1. Then
CA + CB
=

1
od T

(35a)

and
CA
= Qod T 1

(35b)

Another common use of SC filters is high-frequency applications. In such cases a structure with a minimum gain-bandwidth product (GB u) is desirable. This structure is shown
in Fig. 21 and is often called a decoupled structure. It is worth
mentioning that two SC architectures can have ideally the
same transfer function, but with real op amps, their frequency (and time) response can differ significantly. A rule of
thumb for reducing GB effects in SC filters is to avoid a direct
connection between the output of one op amp to the input of
another op amp. It is desirable to transfer the output of an op
amp to a grounded capacitor and, in the next clock phase,
transfer the capacitor charge into the op amp input. More dis-

174

SWITCHED CAPACITOR NETWORKS

C3
C A"

2
1

CA'

2
2

2
C4
CA

CB

2
Vi

C1

1
C2

CH

Vo

C5
C6

Figure 20. An improved capacitance

area SC biquadratic section.

a 7 C0

2
1

a 9C '0

1
2

2 a 8C 0'

2
1

1
C0

a 1C 0

a'5C0'

1
2
Figure 21. A decoupled SC biquadratic
section.

C '0

2
V in

2 a 2C '0

a 5C '0

2
1

+ V0

SWITCHED CAPACITOR NETWORKS

cussion on u effects is in the next section. Analysis of Fig. 21

yields the following expressions:

(36a)
(36b)

If the input is sampled during 2 and held during 1, the ideal

transfer function is given by

H e (z) =

V0e (z)
Vie (z)

a5
=
1 + a8

The actual center frequency suffers small deviations:

o A =

1 + a9
r2 =
1 + a8
2 + a8 + a9 a2 a7
2 r cos =
1 + a8

z2 z(a5 + a5 a1 a2 )/a5 + a5 /a5

2 + a8 + a9 a2 a7
1 + a9
2
z z
+
1 + a8
1 + a8

(37)

The capacitor a9C0 can be used as a design parameter to optimize the biquad performance. A simple set of design equations follows:

(1 + a9 ) r2
r2

1 + r2 2 r cos
(1 + a9 )
a2 = a7 =
r2

a8 =

(38a)
(38b)

Under a high sampling rate and high Q, the following expressions are obtained:
0
= fc

a2 a7
1 + a8

(39a)

and


Q
=

a2 a7 (1 + a8 )
a8 a9

(41)

Finite OP AMP Gain-Bandwidth Product. The op amp bandwidth is very critical for high-frequency applications. The
analysis is carried out when the op amp voltage gain is modeled with one dominant pole that is,
AV (s) =

A0
A
u u
= 0 3 =
=
1 + s/3
s + 3
s + 3
s

(42)

where A0 is the dc gain, u is approximately the unity-gain

bandwidth, and 3 is the op amp bandwidth. Also, it is assumed that the op amp output impedance is equal to zero.
The analysis taking into account AV(s) is rather cumbersome
because the op amp input-output characterization is a continuous-time system modeled by a first-order differential
equation and the rest of the SC circuit is characterized by
discrete-time systems modeled by difference equations. The
step response of a single op amp SC circuit to a step input
applied at t t1 is given by
Vo (t) = Vo (t1 )e(tt 1 ) u + Vod {1 e(tt 1 ) u }

(43)

where Vod is the desired output which is a function of the initial conditions, inputs, and filter architecture and is a topology-dependent voltage divider, 0 1.

Cf
= 
(44)
Ci
i

(39b)

A tradeoff between Q-sensitivity and total capacitance is

given by a8 and a9.
EFFECTS OF THE OP AMP FINITE PARAMETERS
Finite Op Amp dc Gain Effects
The effect of finite op amp dc voltage gain A0 in a lossless SC
integrator is to transform a lossless integrator into a lossy
one. This degrades the transfer function in amplitude and
phase. Typically the magnitude of deviation due to the integrator amplitude variation is not critical. By contrast, the
phase deviation from the ideal integrator has a very important influence on overall performance. When real SC integrators are used to build a two-integrator biquadratic filter,
the actual quality factor becomes




1
2Q

Q
QA =
= 1
1
2
A0
+
Q A0

A0
o
1 + A0

We can conclude that the o deviations are negligible. However, the Q deviations are significant depending on the Q and
A0 values.

175

(40)

where the Cf sum consists of all feedback capacitors connected

directly between the op amp output and the negative input
terminal and the Ci sum is over all capacitors connected to
the negative op amp terminal. Note that the u product determines the rise time of the response, therefore both and
u should be maximized. For the multiple op amp case, the
basic concept prevails. For the common case where t t1
T/2 at the end of any clock phase, the figure of merit to be
maximized becomes Tu /2. This means that a rule of thumb
for reduced gain-bandwidth effects requires that
Tu /2 5

(45)

This rule is based on the fact that five times constants are
required to obtain a steady-state response with a magnitude
of error of less than 1%.
Noise and Clock Feedthrough
The lower range of signals processed by electronic devices is
limited by several unwanted signals at the circuit output. The
rms values of these electrical signals determine the noise
level of the system, and it represents the lowest limit for the
incoming signals to be processed. Input signals smaller than

176

SWITCHED CAPACITOR NETWORKS

the noise level, in most of the cases, cannot be driven by the

circuit. The most critical noise sources are those due to (1) the
elements used (transistors, diodes, resistors, etc.); (2) the
noise induced by the clocks; (3) the harmonic distortion components generated by the intrinsic nonlinear characteristics
of the devices; and (4) the noise induced by the surrounding
circuitry. In this section, types (1), (2) and (3) are considered.
The noise generated by the surrounding circuitry and coupled
to the output of the switched-capacitor circuit is further reduced by using fully differential structures.
Noise Due to the MOSFET. In an MOS transistor, noise is
generated by different mechanisms but there are two dominant noise sources, channel thermal noise and 1/f or flicker
noise. A discussion of the nature of these noise sources
follows.
Thermal Noise. The flow of the carriers caused by drainsource voltage takes place on the source-drain channel, most
like in a typical resistor. Therefore, thermal noise is generated because of the random flow of the carriers. For an MOS
transistor biased in the linear region, the spectral density of
the input referred thermal noise is approximated by
2
Veqth
= 4kTRon

(46)

where Ron, k, and T are the drain-source resistance of the

transistor, the Boltzmann constant, and the temperature (in
degrees Kelvin), respectively. In saturation, the spectral noise
density is calculated by the same expression but with Ron
equal to 2/3gm, where gm is the small signal transconductance
of the transistor.
1/f Noise
This type of noise is mainly caused by the imperfections in
the silicon-silicon oxide interface. The surface states and the
traps in this interface randomly interfere with the charges
flowing through the channel. Hence the noise generated is
strongly dependent on the technology. The 1/f noise (flicker
noise) is also inversely proportional to the gate area because
with larger areas, more traps and surface states are present
and some averaging occurs. The spectral density of the input
referred 1/f noise is commonly characterized by
2
Veq1/f
=

kF
WLf

(47)

where the product of WL, f, and kF are the gate area of the
transistor, the frequency in hertz, and the flicker constant,
respectively. The spectral noise density of an MOS transistor
is composed of both components. Therefore the input referred
spectral noise density of a transistor operating in its saturation region becomes
2
Veq
=

8 kT
k
+ F
3 gm
WLf

(48)

Op Amp Noise Contributions. In an op amp, the output referred noise density is composed of the noise contribution of
all transistors. Hence the noise level is a function of the op
amp architecture. A typical unbuffered folded-cascade op amp

VDD
VC2
M2
M3

M2
VR2

VR2
Vi2

Vi1
M4

M3

M1

VR1

M1

VC1

V0
VR1

M4

M6

M5

M5
VSS

Figure 22. A folded-cascade operational transconductance amplifier.

(folded cascade OTA) is shown in Fig. 22. To compute the

noise level, the contribution of each transistor must be evaluated. This can be done by obtaining the OTA output current
generated by the gate referred noise of all the transistors. For
instance, the spectral density of the output referred noise current due to M1 is straightforwardly determined because the
gate referred noise is at the input of the OTA, leading to
2
i2o1 = G2mVeq1

(49)

where Gm (equal to gm1 at low frequencies) is the OTA transconductance and veq1 is the input referred noise density of
M1. Similarly, the contributions of M2 and M5 to the spectral
density of the output referred noise current are given by

i2o2 = g2m2 v2eq2

(50)

i2o5 = g2m5 v2eq5

The noise contributions of transistors M3 and M4 are very

small compared with the other components because their
noise drain current, due to the source degeneration implicit
in these transistors, is determined by the equivalent conductance associated with their sources instead of by their transconductance. Because the equivalent conductance in a saturated MOS transistor is much smaller than the transistor
transconductance, this noise drain current contribution can
be neglected. The noise contribution of M6 is mainly commonmode noise. Therefore it is almost canceled at the OTA input
because of current substraction. The spectral density of the
total output referred noise current is approximated by
i20 = 2[G2m v2eq1 + g2m2 v2eq2 + g2m5 v2eq5]

(51)

The factor 2 is the result of the pairs of transistors M1, M2,

and M5. From this equation, the OTA input referred noise
density becomes


2
VOTAin

2v2eq1

1+

g2m 2v2eq2 + g2m5 v2eq5

G2m v2eq1


(52)

SWITCHED CAPACITOR NETWORKS

According to this result, if Gm is larger than gm2 and gm5, the

OTA input referred noise density is mainly determined by the
OTA input stage. In that case and using Eq. (48), Eq. (52)
yields
2
VOTAin

2
2

= Vequ1/
= 2Veq1
f + 4kTReqth

177

CI

Vi

(53)

1 V
x

Cs

Vy 2'

1'

where the factor 2 has been included in Veq1/f and Reqth. In Eq.
(47), veq1/f is the equivalent 1/f noise density and Reqth is the
equivalent resistance for noise, equal to 4/3gm.

Vo

Figure 23. Typical switched-capacitor, lossless integrator.

Noise in a Switched-Capacitor Integrator

In a switched-capacitor lossless integrator, the output referred noise density component due to the OTA is frequency
limited by the gain-bandwidth product of the OTA. To avoid
misunderstandings, in this section f u (the unity gain frequency of the OTA in Hertz) is used instead of u (in radians
per second). Because f u must be higher than the clock frequency f c and because of the sampled nature of the SC integrator, the OTA high-frequency noise is folded back into the
integrator baseband. In the case of the SC integrator and assuming that the flicker noise is not folded back, the output
referred spectral noise density becomes




2 fu
v2oeq1 = v2eq1/ f + 4kTReqth 1 +
|1 + H(z)|2
(54)
fc
where the folding factor is equal to f u /f c) and H(z) is the zdomain transfer function of the integrator. The factor 2f u /f c is
the result of both positive and negative foldings. Typically,
the frequency range of the signal to be processed is around
and below the unity-gain frequency of the integrator. Therefore H(z) 1 and Eq. (54) are approximated by




2 fu
v2oeq1 = v2eq1/ f + 4kTReqth 1 +
|H(z)|2
(54b)
fc
Noise from Switches. In switched-capacitor networks,
switches are implemented by single or complementary MOS
transistors. These transistors are biased in the cutoff and
ohmic region for open and closed operations, respectively. In
the cutoff region, the drain-source resistance of the MOS
transistor is very high. Then the noise contribution of the
switch is confined to very low frequencies and it can be considered a dc offset. This noise contribution is one of the most
fundamental limits for the signal-to-noise ratio of switchedcapacitor networks.

1 goes down before 1. This is shown in Fig. 24. Although

CP1 is connected between two low-impedance nodes, CP2 is connected between 1, a low impedance node, and the capacitor
CS. For 1 vi VT, the transistor M1 is on, and the current
injected by CP2 is absorbed by the drain-source resistance.
Then vx remains at a voltage equal to vi.When M1 is turned
off, 1 vi VT, and charge conservation at node vx leads to
vx = vi +

CP2
(V vi VT )
CS + CP2 SS

(55)

where VSS is the low level of 1 and 2. During the next clock
phase, and both capacitors CP2 and CS are charged to vx, and
this charge is injected to CI. Thus, an integrator time constant
error proportional to CP2/(CS CP2) is induced by CP2. In addition, an offset voltage proportional to VSS VT is also generated. Because the threshold voltage VT is a nonlinear function
of vi, an additional error in the transfer function and harmonic distortion components appears at the output of the integrator. The same effect occurs when clock phases 2 and 2
have a similar sequence.
Let us consider the case when 1 is opened before 1, as
shown in Fig. 24(b). Before M1 turns off, Vx vi, and vY
0. When M1 is off, VSS 1 vi VT, the charge is recombined
among CS, CP1, CP2, and CP3. After the charge redistribution,
the charge conservation at node vY leads to
CS [vx (t) vY (t)] CP3 vY (t) = CS vi (t0 )

(56)

where vi(t0) is the input voltage just at the end of the previous
clock phase. Observe from Eq. (56) that the addition of the
charges stored on CS and CP3 is conserved. During the next
clock phase, vx(t) 0, and both capacitors CS and CP3 transfer
the ideal charge CSvi(t0) to C1, making the clock-feedthroughinduced error negligible. The conclusion is that if the clock

Clock Feedthrough
Another factor that limits the accuracy of switched-capacitor
networks is the charge induced by the switch clocking. These
charges are induced by the gate-source capacitance, the gatedrain capacitance, and the charge stored in the channel when
the switch is in the on state. Furthermore, some of these
charges depend on the input signal and introduce distortion
in the circuit. Although these errors cannot be canceled, there
are some techniques to reduce these effects.
Analysis of clock feedthrough is very difficult because it
depends on the order of the clock phases, the relative delay of
the clock phases, and also on the speed of the clock transistions. For instance, in Fig. 23 let us consider the case when

1
1

1'

C1
Vi

C2

C1
Cs

Vx

Vi

C2
Cs
Vx

Cp

Figure 24. MOS Switches: Charge induced due to the clocks: (a) if
1 goes down before 1 and (b) if 1 goes down before 1.

178

SWITCHED CAPACITOR NETWORKS

phase 1 is a bit delayed, then 1 the clock-induced error is

negligible. This is also true for clock phases 2 and 2.
In Fig. 23, the right hand switches also introduce clock
feedthrough but unlike the clock feedthrough previously analyzed, which is input-signal-independent. When clock phase
2 decreases, the gate-source overlap capacitor extracts the
following charge from the summing node:
Q = CGS0 (VSS VT )

(57)

In this case, VT does not introduce distortion because vy is

almost at zero voltage for both clock phases. The main effect
of CGS0 is to introduce an offset voltage. The same analysis
reveals that the bottom right-hand switch introduces a similar offset voltage.
From the previous analysis it can be seen that the clock
feedthrough is reduced by using transistors of minimum dimension. This implies minimum parasitic capacitors and minimum induced charge from the channel. If possible, the clock
phases should be arranged for minimum clock feedthrough.
The effect of the charge stored in the channel has not been
considered.
Dynamic Range
Dynamic range is defined as the ratio of the maximum signal
that the circuit drives without significantly distorting the
noise level. The maximum distortion tolerated by the circuit
depends on the application, but 60 dB is commonly used.
Because the linearity of the capacitors is good enough and if
the harmonic distortion components introduced by the OTA
input stage are small, the major limitation for distortion is
determined by the output stage of the OTA. For the folded
cascade OTA of Fig. 22 this limit is given by

According to this result, the dynamic range of the switchedcapacitor integrator is reduced when power supplies are
scaled down and a minimum number of capacitors are employed. Clearly, there is a compromise between power consumption, silicon area, and dynamic range. As an example,
for the case of CI 1.0 pF, supply voltages of 1.5 V, and
neglecting VDSATP, the dynamic range of a single integrator is
around 78 dB. For low-frequency applications, however, the
dynamic range is lower because of the low-frequency flicker
noise component.
DESIGN CONSIDERATIONS FOR LOW-VOLTAGE,
SWITCHED-CAPACITOR CIRCUITS
For the typical digital supply voltages of 05V, switchedcapacitor networks achieve dynamic ranges of the order of 80
to 100 dB. As long as power supplies are reduced, the swing
of the signal decreases and the resistance of the switches increases further. Both effects reduce the dynamic range of
switched-capacitor networks. For very low supply voltages,
however, the main limitation on the dynamic range of the
switched-capacitor circuit is from analog switches. A discussion of these topics follows.
Low-Voltage Operational Amplifiers

where VDSATP is the source-drain saturation voltage for the P

transistors M2 (M3) and M3. A similar expression is obtained
for the lowest limit. Assuming a symmetrical output stage,
from Eq. (59), the maximum rms value of the OTA output
voltage is given by

The implementation of op amps for low voltage applications

is not a fundamental limitation as long as the transistor
threshold voltage is smaller than (VDD VSS)/2. This limitation becomes clear in the design example presented in this
section. The design of the operational amplifier is strongly dependent on the application. For high-frequency circuits, the
folded-cascade is suitable but the swing of the signals at the
output stage is limited by the cascade transistors. If a large
output voltage swing is needed, a complementary output
stage is desirable. To illustrate the design tradeoffs involved
in a design of a low-voltage OTA, let us consider the folded
cascade OTA of Fig. 22. For low-voltage applications and
small signals, the transistors must be biased with very low
VGS VT. For 0.75 V applications and VT 0.5 V, VGS1
VT1 VDSAT6 must be lower than 0.25 V, otherwise the transistor M6 goes to the triode region. For large signals, however,
the variations of the input signal produce variations at the
source voltage of M1. These variations are of the order of
1.44(VGS1 VT1). Hence, for a proper operation of the OTA
input stage it is desirable to satisfy the following equation:

vORMS
= (VDD 2VDSATP )/ 2

0.25 > 2.44(VGS1 VT 1 ) + VDSAT6

vo max
= VR2 + VTP3

(58)

If the reference voltage VR2 is maximized, Eq. (45) yields

vo max
= VDD 2VDSATP

(59)

(60)

If the in-band noise, integrated up to 1/RintCI is considered and if the most important term of Eq. (60) is retained,
the dynamic range of the single-ended, switched-capacitor integrator becomes
(VDD 2VDSATP )
DR =
2 2kT/CI

The increases in threshold voltage of M1 because of body

effects have to be taken into account. In critical applications,

Table 1. Dimension and Bias Current for the Transistors

(61)

At room temperature operation, this equation reduces to the

following expression

DR
= 5.5 109 CI (VDD 2VDSATP)

(63)

(62)

Transistor

W, m/L, m

IBIAS , mA

M1
M2
M3
M4
M5
M6

48/2.4
120/2.4
60/2.4
60/4.2
60/4.2
60/4.2

2.5
5.0
2.5
2.5
2.5
5.0

Switch resistance ( 103)

SWITCHED CAPACITOR NETWORKS

179

For a single NMOS transistor, the switch resistance is approximated by

400
300

RDS =

200

1
W
mnCOX (VGS VT )
L

(64)

100
0
0.00

0.05

0.10
Vin (V)

0.15

where mn and COX are technological parameters. According to

Eq. (44), the switch resistance increases further when VGS approaches VT. This effect is shown in Fig. 25 for the case
VDD VSS 0.75 V and VT 0.5 V. From this figure, the
switch resistance is higher than 300 k for input signals of
0.2 V. However, for a drain-source voltage higher than VGS
VT, the transistor saturates and no longer behaves as a
switch. This limitation clearly further reduces the dynamic
range of switched-capacitor circuits.
A possible solution to this drawback is to generate the
clocks from higher voltage supplies. A simplified diagram of
a voltage doubler is depicted in Fig. 26a. During the clock
phase 1, the capacitor C1 is charged to VDD, and, during the
next clock phase, its negative plate is connected to VDD.
Hence, at the beginning of 2, the voltage at the top plate of
C1 is equal to 2(VDD) (VSS). Hence, C1 is connected to CLOAD
and, after several clock cycles, if CLOAD is not further discharged, the charge is recombined leading to an output voltage equal to 2(VDD VSS). An implementation for an N-well
process is shown in Fig. 26(b). In this circuit, the transistors
M1, M2, M3, and M4 behave as the switches S1, S2, S3, and S4
of Fig. 26(a). Whereas normal clocks are used for M1 and M2,
special clock phases are generated for M3 and M4 because they
drive higher voltages. The circuit operates as follows.
During 1, M8 is opened because 2 is high. The voltage at
node vy is higher than VDD because the capacitors C3 and CP
were charged to VDD during the previous clock phase 2. At
the beginning of 1, when the voltage goes up, charge is injected to the node through the capacitor C3. Because the bottom plate of C2 is connected to ground by M6, C2 is charged to
VDD VSS through M7. Also, C1 is charged to VDD VSS. Dur-

0.20

Figure 25. Typical switch resistance for an NMOS transistor.

PMOS transistors fabricated in a different well with their

source tied to their own well are used. The dimensioning of
the transistors and the bias conditions are directly related to
the application. For instance, if the switched-capacitor integrator must slew 1 volt in 4 ns and the sampling capacitor is
of the order of 20 pF, the OTA output current must be equal
to or higher than 2.5 mA. Typically, for the folded cascade
OTA, the DC current of the output and the input stages are
the same. Therefore, the bias current for M1, M3, M4, and M5
equals 2.5 mA. The bias current for M2 and M6 is 5 mA. If
VGS1 VT1 equals 0.06 V the dimensions of M1 can be computed. Similarly, the dimensions of the transistors can be calculated, most of them designed to maximize the output range
of the OTA. The dimensions and the bias condition for the
OTA are given in Table 1.
A very important issue in the design of low-voltage amplifiers is the reference voltage. In the folded-cascade of Fig. 22,
the values of the reference voltages VR1 and VR2 must be optimized for maximum swing of the output signal.
Analog Switches
For low-voltage applications, the highest voltage processed is
limited by the analog switches rather than by the op amps.

2'

VDD

Vy

M8

1
Cp

VDD

S4

M7
V0

C1

S2

S1

CLoad

Vx
C2

2'

M6

M5

VSS

M4

2'

M3
C1

M1

M2
(a)

(b)

V0
CLoad

VSS

Figure 26. Voltage doubler: (a) simplified

diagram and (b) transistor level diagram.

SWITCHED CAPACITOR NETWORKS

ing 2, the refresh clock phase, the bottom plate of C1 is connected to VDD by the PMOS transistor M2. Note that if an
NMOS transistor is employed, the voltage at the bottom plate
of C1 is equal to VDD VT resulting in lower output voltage.
If C1 is not discharged, the voltage at its top plate is 2VDD
VSS The voltage at node vx approaches 3VDD 2VSS volts turning M3 on and enabling the charge recombination of C1 and
CLOAD. As a result, after several clock periods, the output voltage v0 is equal to 2VDD VSS. It has to be noted that vY is
precharged to VDD during this clock phase and that M7 is off,
keeping the voltage vx high. To avoid discharges, the gate of
M4 is also connected to the bottom plate of C2. Thus, M4 is
turned off during the refresh phase.
Some results are shown in Fig. 27. For this figure, the voltage at the nodes vX, vY, and v0 are depicted. The supply voltages used are VDD 0.75 V and VSS 0.75 V. The voltage
at node vx is nearly equal to 3VDD 2VSS, for this example,
equal to 3.75 V. The output voltage nearly equals 2.25 V.

10
5
Band-pass gain (dB)

180

0
20
5
10
15
20
500

2500

3000

Figure 28. Frequency response of the second-order, band-pass filter.

1
1
0.9229
0.1953
a5 =
0.9229
0.5455
a2 a7 = 2 + a8
0.9229

Biquadratic filter. In this section, a second-order band-pass

filter is designed. Following are the specifications for this
biquad:
Center frequency:
Quality factor:
Peak gain:
Clock frequency:

1.63 kHz
16
10 dB
8 kHz

a8 =

H(z) =

(66)

Solving these equations, the following values are obtained:

a8 = 0.0835
a5 = 0.2116

A transfer function that realizes this filter is given by the

following expression:
0.1953(z 1)z
z2 0.5455z + 0.9229

(65)

This transfer function is implemented by using the biquad

presented before. For the biquad of Fig. 21 and employing
a1 a5 a9 0, the circuit behaves as a band-pass filter.

a2 a7 = 1.4924
A typical design procedure employs a2 1. For this case, the
total capacitance is of the order of 32 unity capacitances. The
frequency response of the filter is shown in Fig. 28.
Reading List
P. E. Allen and E. SanchezSinencio, Switched-Capacitor Circuits,
New York: Van Nostrand, 1984.
R. W. Brodersen, P. R. Gray, and D. A. Hodges, MOS switched-capacitor filters, Proc. IEEE, 67: 6175.
R. Castello and P. R. Gray, A high-performance micropower switchedcapacitor filter, IEEE J. Solid-State Circuits, SC-20: 11221132,
1985.
R. Castello and P. R. Gray, Performance limitations in switched-capacitor filters, IEEE Trans. Circuits Syst., CAS-32: 865876, 1985.

3
Magnitude (V)

1500 2000
Frequency (Hz)

Equating the terms of Eq. (65) with the terms of Eq. (37), the
following equations are obtained:

Design Example

J. Crols and M. Steyaert, Switched-op amp: An approach to realize

full CMOS switched-capacitor circuits at very low power supply
voltages, IEEE J. Solid-State Circuits, 29: 936942, 1994.

A. I. A. Cunha, O. C. Gouvevia Filho, M. C. Schneider, and C. GalupMontoro, A current-based model of the MOS transistor, IEEE ISCAS, 1997, pp. 16081611.

1000

R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Techniques

for Analog and Digital Circuits, New York: McGrawHill, 1990.

20

40

60

80

100

120

Time (s 10 )
Figure 27. Time response of the voltage doubler at start-up.

140

R. Gregorian and G. Temes, Analog MOS Integrated Circuits, New

York: Wiley, 1986.
A. Mekkaou and P. Jespers, Four quadrant multiplier for neural networks, Electron. Lett., 27: 320322, 1991.

SWITCHED RELUCTANCE MOTOR DRIVES

H. Qiuting, A novel technique for the reduction of capacitance spread
in high-Q SC circuits, IEEE Trans. Circuits Syst., 36: 121126,
1989.
B. Razavi, Principles of Data Conversion System Design, New York:
IEEE Press, 1995.
J. J. F. Rijns and H. Wallinga, Stray-insensitive sample-delay-hold
buffers for high-frequency switched-capacitor filters, Proc. IEEE/
ISCAS, June 1991, 3, 16651668.
E. SanchezSinencio, J. SilvaMartnez, and R. L. Geiger, Biquadratic SC filters with small GB effects, IEEE Trans. Circuits Syst.,
876884, 1984.
R. Unbehauen and A. Cichocki, MOS Switched-Capacitor and Continuous-Time Integrated Circuits and Systems, Berlin, Heidelberg:
Springer-Verlag, 1989.
E. Vittoz, Very low power circuit design: Fundamentals and limits,
IEEE/ISCAS 93 Proc., Chicago, Illinois, May 1993, 14511453.
G. Wegmann, E. A. Vittoz, and F. Rahali, Charge injection in analog
MOS switches, IEEE J. Solid-State Circuits, 22: 10911097, 1987.

EDGAR SANCHEZ SINENCIO

Texas A&M University

SWITCHED-CURRENT TECHNIQUE. See ANALOG INTEGRATED CIRCUITS.

SWITCHED FILTERS. See DISCRETE TIME FILTERS.

SWITCHED NETWORKS. See DISCRETE TIME FILTERS;
TELEPHONE NETWORKS.

181

178

THRESHOLD LOGIC

THRESHOLD LOGIC
Threshold gates are based on the so-called majority or threshold decision principle, which means that the output value depends on whether the arithmetic sum of values of its inputs
exceeds a threshold. The threshold principle is general itself
and conventional simple logic gates, such as AND and OR
gates, are special cases of threshold gates. Thus, threshold
logic can treat conventional gates as well as threshold gates
in general, in a unified manner.
For many years logic circuit design based on threshold
gates has been considered an alternative to the traditional
logic gate design procedure. The power of the threshold-gate
design style lies in the intrinsic complex functions implemented by such gates, which allow system realizations that
require fewer threshold gates or gate levels than a design
with standard logic gates. More recently, there has been increasing interest in threshold logic because a number of theoretical results show that polynomial-size bounded level networks of threshold gates can implement functions that
require unbounded level networks of standard logic gates. In
particular, important functions such as multiple addition,
multiplication, division, or sorting can be implemented by
polynomial-size threshold circuits of small constant depth.
Threshold-gate networks have been found to be also useful in
modeling nerve networks and brain organization, and with
variable threshold (or weights) values they have been used
to model learning systems, adaptive systems, self-repairing
systems, pattern-recognition systems, etc. Also, the study of
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

THRESHOLD LOGIC

algorithms for the synthesis of threshold-gate networks is important in areas such as artificial neural networks and machine learning.
The article has three well differentiated sections. First,
a basic section deals with definitions, basic properties,
identification, and complementary metal-oxide-semiconductor
(CMOS) implementation of threshold gates. The second section is dedicated to the synthesis of threshold gate networks,
from those for specific (and very well-studied) functions such
as symmetric or arithmetic functions to general procedures
for generic functions. Finally, the third section describes the
specific application of threshold logic for the analysis and implementation of median and stack filters.
THRESHOLD AND MAJORITY GATES
A threshold gate (TG) is defined as a logic gate with n input
variables, xi (i 1, . . ., n), which can take values 0,1 and for
which there is a set of n 1 real numbers w1, w2, . . ., wn
and T, called weights and threshold, respectively, such that
the output of the gate is

n


for
wi xi T

1
i=1
f =
(1)
n


wi xi < T
for
0
i=1

A function represented by the output of a threshold gate, denoted by f(x1, x2, . . ., xn), is called a threshold function. The
set of weights and threshold can be denoted in a more compact vector notation by [w1, w2, . . ., wn; T].
A majority gate is defined as a logic gate with n input variables, i (i 1, . . ., n), and a constant input 0, which can
take values 1, 1 and for which there is a set of real numbers w0, w1, w2, . . ., wn, called weights, such that the output
of the gate is:

n


+1
for
wi i 0

i=0
f =
(2)
n


<
0
1
for

i i
i=0


n

Hyperplane
2x1 + x2 + x3 = 3

f(x1, x2, x3)

0
0
0
0
0
1
1
1

x3
x2

x1
: True point of f;

: False point of f

Figure 1. Separation of points of f by a hyperplane.

between a majority function and a threshold function as far

as logical operations are concerned.
For example, the TG defined as [2, 1, 1; 3] represents the
logical function f(x1, x2, x3) x1x2 x1x3. This switching function can be equally represented as the majority gate [2, 1, 1;
2] provided that binary values 1 and 1 are correlated to
1 and 0, respectively.
However, it is important to note that nowadays the term
majority gate is specifically employed for a subset of the gates
defined by (1) or (2). They are 2n 1 input gates that generate a binary 1 when more than n inputs are at binary 1. Because the definition of a threshold function is in terms of linear inequalities, threshold functions are often called linearly
separable functions. From a geometrical point of view, a TG
with n inputs can be seen as a hyperplane cutting the Boolean
n-cube. It evaluates a function f in the sense that f 1(1) lies
on one side of the plane and f 1(0) on the other. An example
is shown in Figure 1.
Figure 2(a) shows the IEEE standard symbol for a TG with
all input weights equal to 1 and threshold in T. This standard
does not have any symbol for a TG with weights other than
1. It is clear that a symbol for that gate can be built by tying
together several inputs (a weight of wi for the input xi can be
obtained by connecting xi to wi gate inputs) but it can result
in a cumbersome symbol, so we will use the nonstandard symbol of Fig. 2(b) for TGs with generic weights.
Basic Useful Properties of Threshold Functions

A function represented by the output of a majority gate, denoted by f(1, 2, . . ., n), is called a majority function. Analogously to the threshold function, a majority function can be
denoted in a vector notation as [w1, w2, . . ., wn; w00].
Definitions for threshold and majority gates can be seen as
different. However, if 1 and 1 in a majority gate are correlated to 1 and 0 in a threshold gate, respectively, then a majority gate with a structure [w1, w2, . . ., wn; w00] and a
threshold gate [w1, w2, . . ., wn; T] have identical logical operations provided that the relation i 2xi 1 is employed and
that T is given by

1
T=
2

x1 x2 x3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

179

wi w0 0

There are a number of properties of threshold functions that

are useful from the point of view of the viability and efficiency
of implementing system using TGs as building blocks. These
properties are not proven here but interested readers can find
a complete treatment in Refs. 13. The emphasis here is put
on their usefulness described previously. Some previous definitions are required.

x1
x2 .
xn

x1
w1
x2 . w2
f

.
.

xn

.
. w
n

f
T

i=1

As a corollary to this statement, it can be easily shown that

the class of all threshold functions is equivalent to the class
of all majority functions. Henceforth, we will not differentiate

(a)

(b)

Figure 2. Threshold gate symbols: (a) all weights equal to 1; (b)

weights not equal to 1.

180

THRESHOLD LOGIC

A function f(x1, x2, . . ., xn) is positive in xi if and only if

there is a sum-of-product expression for f in which xi does not
appear. It can be shown that if f is positive in xi, then whatever the xi residue of f, f xi(x1, x2, . . ., xn) f(x1, x2, . . ., xi
0, . . ., xn), is 1, the xi residue of f, f xi(x1, x2, . . ., xn) f(x1,
x2, . . ., xi 1, . . ., xn), is also 1. This is, f xi(x1, x2, . . ., xn)
implies f xi(x1, x2, . . ., xn), or f xi f xi, where is the symbol
for logical implication.
A function f(x1, x2, . . ., xn) is negative in xi if and only if
there is a sum-of-product expression for f in which xi does not
appear. It can also be shown that f is negative in xi if and
only if f xi f xi.
A function is unate if and only if it is negative or positive
in each of its variables. Now let us enunciate some properties
of threshold functions:
Property 1. All threshold functions are unate. There are
many unate functions that are not threshold functions.
Property 2. The weights associated with variables in which
the function is positive (negative) are positive (negative).
Property 3. Any threshold function can be realized with
integer weight and threshold values.
Property 4. Any threshold function can be realized with
positive weight and threshold values if inversion is
available.
The first two properties are important for the implementation
of a procedure for identifying threshold functions, an essential
task when a threshold-gate design style is adopted. Determining whether a function is unate or not is simpler than determining whether it can be realized by a TG. So first the
function is checked for unateness. If it is not a unate function
then it is not a threshold function either. Moreover, during
the checking for unateness, variables are classified into positive or negative variables, which also contributes to the simplification of the identification procedure applying the second
property.
The third and fourth properties are interesting from the
point of view of the physical implementation of the TGs. For
example, some of the currently available realizations that will
be described later realize positive weights and thresholds.
Property 4 guarantees that this does not limit the class of
threshold functions they can implement.
Figure 3 shows the elementary relations of threshold functions. The meaning of the arrow labeled with 1 is that if f(x1,
x2, . . ., xn) is a threshold function defined by [w1, w2, . . .,
wn; T], then its complement f(x1, x2, . . ., xn) is also a threshold function defined by [w1, w2, . . ., wn; 1 T]. If a
function can be realized as a threshold element, then by selec-

f(x)

f(x)

[w;T]

(1)

[w;1 T]
f(x)

x
[w;T wi]
f(x)

[w; 1 T + wi]
f d(x)

Figure 3. Elementary properties of threshold functions.

x1

x2

x3

h(x 1 , x 2 , x 3 )

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0T
1
0
w3 T
0
0
w2 T
1
1
w2 w3
0
0
w1 T
1
1
w1 w3
0
1
w1 w2
1
0
w1 w2
No solution
h is not a threshold function

x1

x2

x3

f (x 1, x 2, x 3 )

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
0
1
0
1
1
1
1

0T
w3 T
w2 T
w2 w3
w1 T
w1 w3
w1 w2
w1 w2

T
T
T
w3 T

T
T
T
w3 T

w 1 2, w 2 1, w 3 2, T 0
f is a threshold function represented by the vector [2, 1, 2; 0]
Figure 4. Examples of a straightforward procedure for threshold
function identification.

tively complementing the inputs it is possible to obtain a realization by an element with only positive weights.
Threshold-Function Identification
A straightforward approach for solving the threshold-function
identification problem consists in writing a set of inequalities
from the truth table and solving it. If any solution exists, the
function is a threshold function with weights and threshold
given by the solution. If there is no solution, the function is
not a threshold function. In Fig. 4 a pair of examples of this
procedure is shown. This procedure is not very efficient because 2n inequalities are required for a function with n variables. The problem can be solved in a more practical manner
using some of the properties listed before. In order to describe
this alternative procedure some definitions are needed.
There are 2n assignments of values to n Boolean variables.
An assignment A (a1, a2, . . ., an) is smaller than or equal
to an assignment B (b1, b2, . . ., bn), denoted as A B, if
and only if ai bi (i 1, 2, . . ., n). Given a set of assignments A1, A2, . . ., Ak, those Ai for which there is no Aj such
that Aj Ai, 1 j k, j i, are the maximal assignments.
The minimal assignments are those Ai for which there is no
Aj such that Aj Ai, 1 j k, j i. Given a function depending on n variables, each assignment for which the function evaluated to 1 is called a true assignment and each one
for which the function is 0 is called a false assignment.
The procedure has the following steps:
1. Determine whether the function f is unate. If not, the
function is not a threshold function and the procedure
finishes.
2. Convert the function f into another one g, positive in all
its variables by complementing every variable for
which f is negative.

THRESHOLD LOGIC

x1

x2

x3

h(x 1 , x 2 , x 3 )

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
0
0
1
0
1
1
0

181

(1) Unateness checking not passed

x2

x3

h x1 (x 2 , x 3 )

0
0
1
1

0
1
0
1

1
0
0
1

x2

x3

h x1 (x 2 , x 3 )

0
0
1
1

0
1
0
1

0
1
1
0

As neither h xi h xi nor h xi h xi are verified, then h is not a threshold function

x1

x2

x3

f (x 1 , x 2 , x 3 )

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
0
1
0
1
1
1
1

(1) Unateness checking: f positive in x 1 and x 2 ; f negative in x 3

(2) Function g is positive in all variables

A0
A1
A2
A3
A4
A5
A6
A7

x1

x2

x3

g (x 1 , x 2 , x 3 ) f(x 1 , x 2 , x 3 )

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
1
1
1
1
1

(3) Minimal true assignments A 1 , A 4 ; maximal false assignments A 2

(4) Reduced set of inequalities: w 3 T, w 2 T, and w 1 T, solution for
g(x 1 , x 2 , x 3 ): [2, 1, 2; 2]
(5) Solution for f (x 1 , x 2 , x 3 ): [2, 1, 2; 0]
Figure 5. Examples of the second procedure for threshold function identification.

3. Find minimal true assignments and maximal false assignments for g.

4. Generate inequalities for the assignments obtained in
step 3. If there is no solution to such a set of inequalities, the function g is not a threshold function and the
procedure finishes.
5. Derive weights and threshold vector for original function f applying the properties just stated. For every
variable xi that is complemented in the original function, its associated weight is changed to wi, and T to
T wi.

Static Threshold-Logic Gates. There are two notable contributions to static threshold-gate CMOS implementations: one
is based on the ganged technique (47), and the other uses
the neuron MOS (MOS) transistor principle (811). In Refs.
5 to 7 the ganged technique proposed in Ref. 4 was employed
to build TGs with positive and integer weight and threshold
values. Figure 6(a) shows the circuit structure for these
ganged-based TGs. Each input xi drives a ratioed CMOS inverter; all inverter outputs are hard-wired, producing a nonlinear voltage divider that drives a restoring inverter or chain
of inverters whose purpose is to quantize the nonbinary sig-

Figure 5 illustrates the procedure for functions h and f from

Fig. 4.
CMOS Threshold-Gate Implementations
The effectiveness of threshold logic as an alternative for modern very-large-scale integrated circuit (VLSI) design is determined by the availability, cost, and capabilities of the basic
building blocks. In this sense, several interesting circuit concepts have been explored recently for developing standard
CMOS-compatible threshold gates. The most promising are
presented in this section. In order to denote their context of
application, we distinguish between static and dynamic realizations.

[Wp/Lp, Wn/Ln]b

[Wp/Lp, Wn/Ln]i

V
x1
x2
x3

PMOS

.
.
.

xn
VC

NMOS

CMOS inverters
(a)

(b)

Figure 6. Static threshold logic gates: (a) ganged threshold gate; (b)
MOS threshold gate.

182

THRESHOLD LOGIC

nal at the ganged node (f). The design process for these gates
involves sizing only two different inverters. Assuming the
same length for all transistors, the transistor widths [Wp,
Wn]i,b of each inverter are chosen taking into account the wi
and T values to be implemented. Weight values other than 1
can be realized by simply connecting in parallel the number
of basic inverters (inverter with wi 1) indicated by the
weight value; on the other hand, the value of T is determined
by the value of the output inverter threshold voltage. Due to
the sensitivity of this voltage and f to process variations, the
ganged-based TG has a limited number of inputs (fan-in). A
good study of this limitation can be found in Ref. 12. However,
the main drawback of this TG is the relative high power consumption.
Other interesting static TGs are based on the MOS transistor. This transistor has a buried floating polysilicon gate
and a number of input polysilicon gates that couple capacitively to the floating gate. The voltage of the floating gate
becomes a weighted sum of the voltages in the input gates,
and hence it is this sum that controls the current in the transistor channel. The simplest MOS-based threshold gate is
the complementary inverter using both p- and n-type MOS
devices. A schematic of this TG is shown in Fig. 6(b). There
is a floating gate, which is common to both the p- and n-type
(PMOS and NMOS) transistors, and a number of input gates
corresponding to the threshold gate inputs, x1, x2, . . ., xn,
plus some extra inputs (indicated by VC in the figure) for
threshold adjustment. Weights for every input are proportional to the ratio between the corresponding input capacitance Ci between the floating gate and each of the input gates,
and the total capacitance, including the transistor channel capacitance between the floating gate and the substrate, Cchan.
Without using the extra control inputs, the voltage in the
floating gate is given by

VF =


n

!
Ctot

CiVx i

VDD
R

M1 M2

VOUT

V x2
W/L

M 4n + 1

M3

Ire

V x1

W/2L

W/L

W/L
W/L
M 42
M 41

M 4n

VOUT

M8
Iin

V xn

OUT

OUT
R
W/2L

M7 M6

V y1
M 91

M5

V y2

V yn

W/L

M 92

M 9n

M 9n + 1

M10

(a)
VDD

M1

M2

OUT

OUT
1

M x0

M3

M4

D
1

V x1

Vx2

V xn

M x1

M x2

M xn

V yn

V yn 1

V y1

M yn

M yn 1

M y1

M y0

(b)

VR
C1

Vo
Cj

Cn

Vref

V1

Vj

Vn

R
E

(c)

i=1

Figure 7. Dynamic threshold gates: (a) latch-type threshold gate; (b)

alternative latch-type threshold gate; (c) capacitive-type threshold
gate.

where

Ctot = Cchan +

n


Ci

i=1

As VF becomes higher than the inverter threshold voltage, the

output switches to logic 0. It is obvious that this MOS
threshold gate is simpler than the ganged threshold gate,
however, its sensitivity to parasitic charges in the floating
gate and to process variations could limit its effective fan-in
unless adequate control is provided (15). In particular, ultraviolet light (UV) erasure is recommended for initialization.
Dynamic Threshold-Logic Gates. Two different principles
have been exploited in dynamic TG implementations: the bistable operation of simple CMOS latches, and the capacitive
synapse used in artificial neuron architectures. In both cases,
compact gates with low power consumption, high speed, and
high fan-in have been developed (1315).

The first latch-type threshold gate was proposed in Ref. 13

and its schematic is shown in Fig. 7(a). Its main part consists
in a CMOS current-controlled latch (transistor pairs M2 /M5
and M7 /M10) providing the gates output and its complement,
and two input arrays (M41 to M4n and M91 to M9n) constituted
by an equal number of parallel transistors whose gates are
inputs of the TG and their sizes are determined by the corresponding weight and threshold values. Transistor pairs
M1 /M3 and M6 /M8 specify the precharge or evaluation situation, and the two extra transistors M4n1 and M9n1 ensure correct operation when the weighted sum of inputs is equal to
the threshold value. Precharging occurs when the reset signal R is at logic 0. Transistors M1 and M6 are on, transistors
M3 and M8 are off, and both OUT and OUT are at logic 1.
Evaluation begins when R is at a logic 1, transistors M1 and
M6 are turned off, M3 and M8 are turned on, and nodes OUT
and OUT begin to be discharged. In this situation, depending
on the logic values at the inputs of the two transistor arrays,

THRESHOLD LOGIC

one of the paths will sink more current than the other, making the decrease of its corresponding output node voltage
faster (OUT or OUT). When the output node of the path with
the highest current value is below the threshold voltage of
transistors M5 or M10, one of them is turned off, fixing the
latch situation completely. Supply current only flows during
transitions and, consequently this TG does not consume
static power.
Input terminal connections and input transistor sizes in
this TG must be established according to the threshold value
T to be implemented, and to the fact that when all transistors M4i and M9i (i 1, 2, . . ., n) have the same dimension
and the same voltage at their gate terminal, then Iin Iref due
to M4n1. If a programmable TG is required, the best design
choice is to use one of the input arrays for the TG inputs and
the other array for control inputs, which must be put to logic
1 or 0 depending on the value of T. For illustration, the operation of a 20-input threshold gate [1, 1, . . ., 1; T] with programmable threshold T is shown in Fig. 8. The outputs depicted correspond to different values of T: (a) T 1, this is a
20-input OR-gate; (b) T 10; and (c) T 20, a 20-input ANDgate. The results shown correspond to the following sequence
of logic input patterns: (x1, x2, . . ., x19, x20) (0, 0, . . ., 0,
0), (0, 0, . . ., 0, 1), (0, 0, . . ., 1, 1), . . ., (1, 1, . . ., 1, 1).
The i-th input combination is evaluated in the i-th reset
pulse. So, we have the weighted sum of the inputs in the x
scales.
The circuit in Fig. 7(b) is an alternative realization proposed in Ref. 14 for dynamic latch-type threshold gates. In
this gate, the input transistor arrays (Mxi and Myi, i 0, 1,
. . ., n) are connected directly to the latchs output nodes, and
precharging occurs when 1 and 2 are at logic 0, putting
nodes D, OUT, and OUT at logic 1. For the evaluation phase
both 1 and 2 are at logic 1 but 2 must return to the low
level before 1 in order to allow latch switching. The performance of this TG is similar to that in Ref. 13 but it needs
more transistors and two different control signals that have
to be obtained from a general clock.

183

The principle of capacitive synapse has been exploited in

the capacitive threshold-logic gate proposed in Ref. 15. Its
conceptual circuit schematic is shown in Fig. 7(c) for an ninput gate. It consists of a row of capacitors Ci, i 1, 2, . . .,
n, with capacitances proportional to the corresponding input
weight, Ci wiCu, and a chain of inverters that functions as
a comparator to generate the output. This TG operates with
two nonoverlapping clock phases R and E. During the reset
phase, R is high and the row voltage VR is reset to the first
inverter threshold voltage while the capacitor bottom plates
are precharged to a reference voltage Vref . Evaluation begins
when E is at a logic 1, setting gate inputs to the capacitor
bottom plates. As a result, the change of voltage in the capacitor top plates is given by

VR =


n

!

Ci (Vi Vref )

Ctot

i=1

where Ctot is the row total capacitance including parasitics.

Choosing adequate definitions for Vref and Ci as functions of
the input weight and threshold values, this above relationship can be expressed as

VR =


n

!

(wi xi T )CuVDD

Ctot

i=1

which together with the comparison function of the chain of

inverters give the TG operation:
Vo = VDD

if

n


w i xi T

i=1

and
Vo = 0

if

n


wi xi < T

i=1

3.0
2.0

1.0
0.
3.0

VOUT
OR gate
(T = 1)

2.0
1.0
0.
3.0

VOUT
MAJ gate
(T = 10)

2.0
1.0
0.
3.0

VOUT
AND gate
(T = 20)

2.0
1.0
0.0
0.0

25.0n

50.0n

75.0n

100.0n 125.0n 150.0n

Time (linear scale)

175.0n

200.0n
220.0n

Figure 8. Simulation results for a progammable threshold gate implemented by

the circuit of Fig. 7(a). The letter n stands
for nanoseconds.

184

THRESHOLD LOGIC

Experimental results from different capacitive threshold-logic

gates fabricated in a standard CMOS technology (15) have
shown the proper functionality of this type of threshold gates
and its large fan-in capability.
THRESHOLD-GATE NETWORKS
There are functions that cannot be implemented by a single
threshold element. However, as TGs realize more complex
functions than the conventional gates, this section studies the
capabilities of interconnecting TGs so that the potential advantages of realizing digital systems using TGs as building
blocks are pointed out. First, the question of whether any
Boolean function can be realized interconnecting TGs is addressed. Then the computation power of such a network is analyzed.
Figure 9 shows the model for a feed-forward network of
functional elements. It is the most general type of network
without feedback because inputs can be connected to any of
the functional blocks in the network, and the only restriction
affecting the functional blocks to which the output of one of
them can be connected is that loops are not allowed. The
depth of a network is the maximum number of functional elements in a path from any input to any output. The size of a
network is defined as the total number of functional elements
it contains. In the following a feed-forward network in which
the functional elements are conventional digital gates (AND,
OR, NOT) will be referenced as a logic circuit or logic network. It is well known that any Boolean function can be implemented by a logic circuit, and so, any Boolean function can
also be implemented by a feedforward network of TGs as
AND, OR and NOT gates are TGs. However, from a practical
point of view, these results are not enough. The existence of
a determinate network implementing a given function can be
irrelevant. This is illustrated by a network that computes the
function too slowly to fulfill speed specifications or a network
with too large a hardware cost. That is, the depth and the
size of the network are critical because these parameters are

x1
x2 .
..
xn

c
c

related to the speed and to the required amount of hardware,

respectively. For example, it is well known that any function
can be implemented with a depth-2 logic network of AND and
OR gates (depth-3 network of NOTANDOR gates if input
variables are in single rail). However, it is also well known
that there are common functions for which the number of required gates in such implementations increases exponentially
with the number of variables, and so they are not realized in
two levels. From a different point of view, there are functions
that cannot be implemented by a polynomial-sized network
with constant depth (independent of the number of variables),
resulting in too large a computation time for large n.
It follows from the previous arguments that a more realistic problem is determining the existence of a constant-depth
network with size bounded by a polynomial in n, O(n), for a
Boolean function of n variables. There are a number of functions for which the answer to this question is negative for
logic networks and positive for threshold networks.
Consider, for example, the parity function, f parity(x1, x2,
. . ., xn), which is 1 if and only if an even number of its inputs
are logical 1. No logic circuit with a polynomial (in n) number
of unbounded fan-in ANDORNOT gates can compute it
with constant depth (16). In Fig. 10(a) a depth-2 logic network
implementing parity for n 4 is depicted. For arbitrary n, its
size is 2n1 1. A depth-2 threshold network for f parity of four
variables is shown in Fig. 10(b). For an arbitrary n only n
1 gates are required.
The parity function belongs to the more general class of
symmetric functions that can be efficiently implemented by
threshold networks and that have received much attention.
Symmetric functions are the subject of the next subsection.
Threshold Networks for Symmetric Functions
Symmetric functions are not particularly easy to realize using
traditional logic gates. However, an important feature of
threshold logic gates is their capability for obtaining implementations of symmetric functions by simple networks.

FU1

c
x1
x2 ..
xn .

c
c
c
c

FU2

x1
x2 ..
xn .

c
c
c
c
c

FU3

c
c
.. c
x1 . c
x2 .. c
. c
xn
Figure 9. Feed-forward network of functional elements (FU). The letter c denotes
where connections can exist.

FUM 1

c
c
.. c
. c
x1
c
x2 .. c
xn . c

FUM

THRESHOLD LOGIC
x 1
x 2
x 3
x 4
x 1
x 2
x3
x4
x 1
x2
x3
x4
x 1
x2
x3
x 4
x1
x 2
x 3
x4
x1
x 2
x3
x 4
x1
x2
x 3
x 4
x1
x2
x3
x4

x1
1
x2 . 1

&

xn
&

&

&
+

fparity

&

&

x1
x2
x3
x4
x1
x2
x3
x4
x1
x2
x3
x4
x1
x2
x3
x4

xn

1 k'1 + 1

..

1
+1
1
+1

fparity

w1

.. w2
. w

1 k'2 + 1

..
.

x1
1
x2 . 1

x1
1
x2 . 1
.
xn

xn

..

f(x1,...,xn)

k1

1 k's + 1

wj = kj + 1 kj
ws =

n + 1 ks
0

( j = 1, 2,..., s 1)
if k's < n
if k's = n

Figure 12. Minnick solution to the threshold-gate network implementation of a symmetric function.

&
(a)

(b)

Figure 10. Networks realizing f parity for n 4: (a) logic network; (b)
threshold network. Symbol & denotes AND gates and symbol denotes OR gates.

Classically, two main solutions have been considered depending on the availability of the input variables of the network. Muroga (1) proposed a solution suitable when the input
variables are available only at the first-level gates and the
network has feed-next interconnections. Then any symmetric
function of n variables can be implemented by a network that
has at most n 1 threshold gates in two levels. To show that,
let us suppose that the symmetric function is 1 if and only if
the number of 1s in the n variables, given by k, is in one of
the ranges k1 k k1, k2 k k2, . . ., ks k ks. Figure
11 shows the threshold-gate network used to implement this
function. If the number of 1s in the input variables, k, is ki
k ki, 1 i s, then all the TGs whose thresholds are equal
to or smaller than k have outputs of 1, and the other TGs
have outputs of 0. Then, there are 2i 1 gates with output
1. Among them, i gates are connected to the output gate with
weight 1, and i 1 gates with weight 1. Thus the

x1
1
x2 . 1
.

k1

..
.
x1
1
x2 . 1
.
xn

..

x1
1
x2 . 1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

&

xn

185

x1
x2

1
1

xn

1 k'1 + 1

+1

..
.

.. 1
.

+1
1

f(x1,...,xn)
1

ks x1
1
x2 . 1
.
xn

1 k's + 1

Figure 11. Muroga solution to the threshold-gate network implementation of a symmetric function.

weighted sum of these inputs is 1, and the output gate will

give an output of 1. When ki 1 k ki1 1, there are
2i gates with output 1, but the weighted sum of these inputs
to the second TG is 0 and, consequently the output of that
output gate is 0.
Minnick (in Ref. 1) authored a solution for which the input
variables are available at gates of any level. A symmetric
function of n variables can be implemented by a network that
has at most 1 n/2 TGs in at most two levels. Here x
denotes the integral part of x. To show that, let us suppose
that the symmetric function is 1 if and only if the number of
1s in the n variables, given by k, is in one of the ranges k1
k k1, k2 k k2, . . . ks k ks. Figure 12 shows the
threshold-gate network used to implement the symmetric
function. If the number of 1s in the input variables k is ki
k ki, 1 i s, then all the TGs with threshold equal to or
smaller than k have an output of 1. As ki1 1 ki k
ki, then there are i 1 TGs giving an output of 1, which add

i1


w j = (ki k1 )

j=1

to the weighted sum of the output threshold gate. The

weighted sum of that gate will be (ki k1) k, which, when
compared to k1, results in a number that is equal to or greater
than zero, and in consequence, the output of the output
threshold gate is 1. The case for an output of 0 can be shown
in a similar manner. Also an equivalent realization can be
found by expressing the outputs of the first-level threshold
gates as inverted instead of weighted negatively.
An interesting solution for the modulo-2 sum (parity) of n
variables was proposed by Kautz in (1). It is realizable with
at most s 1 log2n threshold gates. The feed-forward
network proposed is shown in Fig. 13(a), and the synthesis
problem can be easily extended to solve a general symmetric
function. Let us consider the general feed-forward solution
shown in Fig. 13(a) specific to s 4. Figure 13(b) shows the
output values of the gates of this network in terms of the
number of 1s in the input variables. It can be easily seen that
the number of 1s in the input variables at which transitions

THRESHOLD LOGIC

xn

1
1

gs 1

1 Ts 1 x1
x2

..
.

xn

..
.

..
.

ws 1 s 2
1
gs 2
1
1 Ts 2

x1
x2

ws 1 s 3
ws 2 s 3
1
gs 3
1

..
.

1Ts 3

..
.

xn

..
.

x1
x2

..
.

186

x1
x2

ws 1 0
ws 2 0
.. ws 3 0
. w
g0
10
1
1

..
.

xn

T0 w30 w10

T2 w32

T0

(a)
g3
g2
g1
g0
T0 w30 w20 w10

T1 w31 w21

T0 w30 w20

T1 w31

(b)

T0 w30

T3

T0 w20 w10

Usually when implementing arithmeticlike functions by

threshold networks, the required weights can grow exponentially fast with the number of variables. This is undesirable
because of the requirements of high accuracy it places on the
actual implementations. An example is the comparison function f comp(x1, x2, . . ., xn, y1, y2, . . ., yn), which takes as input

T1 w21

Threshold Networks for Arithmetic Functions

T0 w20

from the value 0 to 1 occur in gk defines the oppositely direct

transitions from 1 to 0 in gk1, gk2, . . ., g0. Also, it is important to consider that although T3, T2, T2 w32, T1, T1 w21,
T1 w31, T0, T0 w10, T0 w20, T0 w30 for g3, g2, g1, and g0
are independent and arbitrarily determined, some of the relations for g1 and g0 (T1 w31 w21, T0 w20 w10, T0
w30 w10, T0 w30 w20, and T0 w30 w20 w10) are
consequently determinated. Thus, the synthesis of a general
symmetric function can become very complex because of this
mutual dependence of parameters.
Solutions proposed by Muroga and Minnick (1) implement
symmetric functions in an O(n) depth-2 threshold network.
Reducing the size of the network significantly from O(n) requires an increasing of the network depth beyond 2. Recently
it has been shown (17) that any symmetric function of n variables can be implemented with a depth-3 threshold network
with at most 2n O(1) threshold gates, that is, an increase
of 1 in the depth allows an implementation with a gate count
reduced by a factor of O(n).

T2

T0 w10

T1

T0

Figure 13. Kautz solution to the thresholdgate network implementation of a symmectric function: (a) general structure, (b) transitions of output values for s 4.

two n-bit binary numbers x xnxn1 x1 and y ynyn1

y1 and produces output equal to 1 if and only if x y.
Figure 14(a) shows a TG implementing the function. The
depth-2 network in Fig. 14(b) would be preferable for moderately large values of n because of the smaller weights it requires. A subclass of the threshold gates, those for which the
weights are polynomially bounded by the number of input
variables, is more practical. Restricting the allowed weights
does not limit too much the computational power of the network. It has been shown (18,19) that any depth-d polynomialsize threshold circuit can be implemented by a depth-(d 1)
polynomial-size network of the restricted threshold elements.
Interesting results have been derived for functions such as
multiple addition, multiplication, division, or sorting, which
have been shown to be computable by small constant-depth
polynomial-size threshold networks. Different proposed implementations exhibit different depth-size trade-offs. Some
results concerning optimal depth threshold networks are
given in Ref. 20. It is demonstrated that multiplication, division, and powering can be computed by depth-3 polynomialsize threshold circuits with polynomially bounded weights.
The efficient threshold networks derived for these functions rely in many cases on the underlying new computation
algorithms. One example is the block save addition (BSA)
principle for multiple addition. Siu and Bruck (21) showed
that the sum of n numbers can be reduced to the sum of two
numbers by using the BSA principle. The key point of this

THRESHOLD LOGIC

technique is the separation of the n numbers in columns of

log n bits that are separately added. Each sum is at most
2log n bits long, and hence it overlaps only with the sum of
the next column. Here x denotes the smallest integer equal
to or greater than x. So a number is obtained by concatenating the partial sums from the columns placed in even positions and another number with the concatenation of the sum
from the odd columns.
In general, the realizations introduced so far cannot be directly applied if the fan-in of the TGs is constrained to be not
more than m, m n, where n stands for the number of input
variables. Thus another area receiving attention is that of deriving depth-size trade-off for threshold networks implementing arithmeticlike functions with a simultaneous bound on
the maximum allowable fan-in. Let us resort again to the parity function in order to illustrate this statement. In Ref. 22 it
is shown that the parity function of n inputs can be computed
d
using a threshold circuit of size O(nm1/(2 1)), depth O(d log
n/log m), and fan-in bounded by m for every integer d 0.

187

logic gates, many basic functions can be computed much

faster and/or much cheaper using TGs than using logic gates.
This is one of the motivations for investigating devices able
to implement TGs. However, the usefulness of threshold logic
as a design alternative, in general, is determined not only by
the availability, cost, and capabilities of the basic building
blocks but also by the existence of synthesis procedures. The
problem to be solved at this level can be stated as given a
combinational logic function, described in the functional domain (by means of truth tables, logic expressions, etc.), derive
a network of the available building blocks realizing f that is
optimal according to some design criteria.
Many logic synthesis algorithms exist for targeting conventional logic gates but few have been developed for TGs, although the problem was addressed as early as the beginning
of the 1970s by Muroga. The procedure described by this author (1) transforms the problem of deriving the smallest (lowest gate count) feed-forward network realizing a given function in a sequence of mixed integer linear programming
(MILP) problems. The problem of determining whether a
given function f can be realized by a feed-forward threshold
network with M gates, and if it can, determining the weights
and the threshold for each of the M elements can be formu-

Threshold Network Synthesis

The significance of the preceding results is that assuming
TGs can be built with a cost and delay comparable to that of
x1
1
x2 . 2
..
xr
2r 1
1
y1
y2 . 2
..
yr
2r 1 1
x1
1
x2 . 2
..
xr
2r 1
1
y1
y2 . 2
..
yr
2r0 1
xr +
xr +

1
2

x2r

xn
y1
y2

2n 1
1
2

yn

2n 01

(a)

fcomparison

yr + 1
yr + 2 .
.
y2r .

1
2

2r 1 1

xr + 1
xr + 2
x2r
yr + 1
yr + 2

y2r
xn r + 1
xn r + 2
xn
yn r + 1
yn r + 2
yn
xn r + 1
xn r + 2
xn
yn r + 1
yn r + 2
yn

fcomparison

.. 2
. 2r 1
1

.. 2
. 2r0 1
..
.

2t 1
2t 1

2t 1

.. 2
. 2r 1

r = log2n

t = n/r

1
2

..
. 2r 1
1

1
2

.. 2
. 2r 1

x1
x2

.. 2
. 2r 1
1

.. 2
. 2r 1
0

(b)

Figure 14. Networks realizing f comparison:

(a) depth-1 network; (b) depth-2 network.

188

THRESHOLD LOGIC

lated as a MILP problem (the cost function is usually the total

weight sum of the network). Starting with M 1 and incrementing M until a feasible MILP problem is encountered, one
derives the implementation with less gates. Clearly, exact approaches are practical only for small instances of the synthesis problem. The main limitation seems to be the number of
variables that the function being synthesized depends on, because the number of inequalities and variables in the MILP
problem to be solved increase exponentially with n. Thus,
heuristic approaches are more relevant.
Concerning two-level (depth-2) threshold networks, an algorithm called LSAT (23), inspired in techniques used in classical two-level minimization of logic circuits, has been developed. The core of the algorithm performs as follows. Suppose
we have a two-level threshold network satisfying the following conditions: (1) weights of first-level TGs are restricted to
the range [z, z] and (2) weights of the second-level gate
are all equal to 1 and the threshold of this gate is S. Another
threshold network that also satisfies previous conditions (1)
and (2) with a minimal number of gates is obtained. This operation is repeated increasing S by 1 until a value of S is
reached for which no solution is found. As a two-level
ANDOR network is a threshold network of the type handled
by the procedure with z 1, S 1, the algorithm is started
with this network. Such a two-level circuit is easy to obtain
and in fact is a standard input for other synthesis tools. LSAT
has a run-time polynomial in the input size given by n z,
where n stands for the number of variables and z defines the
allowed range for the weights. This means central processing
unit (CPU) time increases if large weights are required.
The practical use of synthesis procedures for TGs is not
restricted to the design of integrated circuits but to areas
such as artificial neural networks or matching learning. Different problems encountered in these fields are naturally formulated as threshold network synthesis problems

APPLICATION TO MEDIAN AND STACK FILTERS

For some time, linear filters have been widely used for signal
processing mainly due to their easy design and good performance. However, linear filters are optimal among the class of
all filtering operations only for additive Gaussian noise.
Therefore problems such as reduction of high frequency and
impulsive noise in digital images, smoothing of noisy pitch
contours in speech signal, edge detection, image preprocessing in machine recognition, and other related problems
with the suppression of noise that is non-Gaussian, nonadditive, or even not correlated with the signal can be difficult to
solve (24).
These unsatisfactory results provided by linear filters in
signal and image processing have been overcome by resorting
to nonlinear filters. The more well known is perhaps the median filter, which has found widespread acceptance as the
preferred technique to solve the signal restoration problem
when the noise has an impulsive nature or when the signals
have sharp edges that must be preserved. But the median
filter has inherent problems because its output depends only
on the values of the elements within its window. So, a median
filter with a window width of n 2L 1 can only preserve
details lasting more than L 1 points. To preserve smaller
details in the signal, a smaller window width must be used.

But the smaller this window width, the poorer the filter noisereduction capability (25).
This contradiction can be solved by incorporating in the
filter output the index order of the sequence of elements. It is
typically done by weighting filter input values according to
their relative sequence index order. This idea leads in a natural way to the concept of the weighted-median (WM) filter
(26), which has the same advantages as the median filter but
is much more flexible in preserving desired signal structures
due to the defining set of weights. Median and weighted-median filters are well-known examples of a larger class of nonlinear filters: the stack filters, which also include the maximum-median filters, the midrange estimators, and several
more filters.
Stack filters are a class of sliding finite-width-window,
nonlinear digital filters defined by two properties called the
threshold decomposition (a superposition property) and the
stacking property (an ordering property) (24). The threshold
decomposition of an M-valued signal X (X1, X2, . . ., XN),
where Xi 0, 1, 2, . . ., M 1, i 1, . . ., N is the set of
(M 1) binary signals x1, x2, . . ., xM1, called threshold signals, defined as:


xij

if Xi j

else

j = 1, . . ., M 1

(3)

From this definition, it is clear that

M1


xij = Xi

i {1, . . ., N}

j=1

and also that the xij are ordered, that is, xi1 xi2
xiM1 i 1, . . ., N. This ordering property is called the
stacking property of sequences.
Two binary signals u and v stack if ui vi, i 1, . . .,
N. Let us suppose that both signals are filtered with a binary
window filter of width L [i.e., we use a Boolean function B:
0, 1L 0, 1 for the filtering operation, which results in
B(u) and B(v)]. The binary filter B exhibits the stacking property if and only if B(u) B(v) whenever u v.
The stack filter SB(X) is defined by a binary filter B(x) as
follows:

X) =
SB (X

M1


B(xx j )

(4)

j=1

The threshold decomposition architecture of stack filters

means that filtering an M-valued input signal by the stack
filter SB is equivalent to threshold decomposing the input signal to M 1 binary threshold signals, filtering each binary
signal separately with the binary filter B, and finally adding
the binary output signal together to reconstruct the M-valued
signal. As stack filters possess the stacking property, this reconstruction section needs only to detect the level just before
the transition from 1 to 0 takes place.
Figure 15 illustrates the threshold decomposition architecture of a stack filter with a window width of 3 for the fourvalued input signal shown at the upper left corner. The binary signals are obtained by thresholding the input signal at
levels 1, 2, and 3. Binary filtering is independently performed

THRESHOLD LOGIC

Output signal

Input signal
Interger signals:

Xi

230121322

189

SB

23 1022322

Add binary outputs

(stacking property)

Threshold at 1, 2, and 3
(threshold decomposition)
Filtering

Binary signals:

x3i

010000100

010000100

x2i

110010111

110011111

x1i

110111111

1 1 10 1 1 1 1 1

by the digital function B(a, b, c) ac b, in which a, b, and

c are the bits, in time order, appearing in the filters window.
In the original integer domain of the M-valued input signal, the stack filter corresponding to a positive Boolean function (PBF) can be expressed by replacing logical operators
AND and OR with MIN and MAX operations, respectively. In
consequence, the output of a stack filter is a composition of
maximum and minimum operations on the samples in the
window. For the example in Fig. 15, this means that the operation performed by SB is SB(A, B, C) MAXMINA, C, B.
Both filtering operations are represented in Fig. 15: by
threshold decomposition if the lightface arrows are followed
and directly, by the stack filter SB, following the boldface
arrows.
The next question is to know which binary functions possess the stacking property. It has been shown that the necessary and sufficient condition for this is that the binary function is a PBF, that is, positive in all its variables. These
functions are a subset of unate functions that have the property that each one possesses a unique minimum sum-of-products (SOP) expression, and hence each stack filter can be described in terms of a unique minimum SOP Boolean
expression. Finally, as shown previously, threshold functions
are a subset of unate functions. Stack filters that are based
on TGs with nonnegative weights and nonnegative threshold
values are called weighted-order statistics filters.
It can be very instructive to show the relations of the more
usual members of the class of stack filters, namely, weightedorder statistic (WOS), weighted-median (WM), order-statistic
(OS), and standard-median (SM) filters. In Fig. 16 these relations are shown by means of boxes and arrows. Each box corresponds to a filter subclass specified by the integer domain
filter and the binary domain filter. The arrows indicate the
containing conditions among classes of filters.
From a practical point of view, there are several options
for the very-large-scale integrated circuit (VLSI) implementation of the PBFs of a stack filter: binary logic gates, sort-andselect circuits, or count-and-compare circuits. If logic gates or
a programmable logic array (PLA) is used, a number of terms

bounded by

Figure 15. Illustration of threshold decomposition and the stacking property.

n
n/2

or

n/2

for a window width of n can be obtained. The hardware complexity for sort-and-select circuits is O(n log n) and O(n) for
count-and-compare circuits. The PBF can also be realized as
a look-up table by a 2n-sized random-access memory (RAM) or
read-only memory (ROM), and if a RAM is used, programmable PBF-based filters can be made.
In the case of a WOS filter, its PBF can be realized by a
TG. It constitutes a great advantage because the number of
product terms or sum terms of the PBF can be as large as


n
T

while the representation of a TG needs only n 1 components, the n weights and the threshold T. Therefore, while
the implementation of a generic stack filter can be very diffi-

Positive Boolean functions

Stack filters, MAX-MIN network

Threshold gates, linearly separable PBFs

WOS filters

Linearly separable self-dual PBFs

WM filters

Linearly separable isobaric PBFs

OS filters

Self-dual linearly separable isobaric PBFs

SM filters

Figure 16. Relations of linearly separable subclasses of stack filters.

190

THYRISTOR PHASE CONTROL

cult, the implementation of the subclass of WOS filters can be

affordable if an efficient realization of TGs is used.

21. K. Siu and J. Bruck, Neural computation of arithmetic functions,

Proc. IEEE, 78 (10): 16691675, 1990.

BIBLIOGRAPHY

22. K. Siu, V. P. Roychowdhury, and T. Kailath, Toward massively

parallel design of multipliers, J. Parallel Distr. Comput., 24: 86
93, 1995.

1. S. Muroga, Threshold Logic and its Applications, New York: Wiley, 1971.
2. Z. Kohavi, Switching and Finite Automata Theory, New Delhi:
Tata McGraw-Hill, 1978.
3. E. J. McCluskey, Logic Design Principles: With Emphasis on Testable Semicustom Circuits, Englewood Cliffs, NJ: Prentice Hall,
1986.
4. K. J. Schultz, R. J. Francis, and K. C. Smith, Ganged CMOS:
Trading standby power for speed, IEEE J. Solid-State Circuits,
25 (3): 870873, 1990.
5. C. L. Lee and C-W. Jen, CMOS threshold gate and networks for
order statistic filtering, IEEE Trans. Circuits Syst. I, Fundam.
Theory Appl., 41 (6): 453456, 1994.
6. J. M. Quintana, M. J. Avedillo, and A. Rueda, Hazard-free edgetriggered D flipflop based on threshold gates, Electron Lett., 30
(17): 13901391, 1994.
7. J. M. Quintana et al., Practical low-cost CMOS realization of
complex logic functions, Proc. Eur. Conf. Circ. Theor. Design, pp.
5154, 1995.
8. T. Shibata and T. Ohmi, A functional MOS transistor featuring
gate level weighted sum and threshold operations, IEEE Trans.
Electron Devices, 39 (6): 14441445, 1990.
9. T. Shibata and T. Ohmi, Neuron MOS binary-logic integrated circuitsPart I: Design fundamentals and soft-hardware-logic circuit implementations, IEEE Trans. Electron Devices, 40 (3): 570
576, 1993.
10. T. Shibata and T. Ohmi, Neuron MOS binary-logic integrated circuitsPart II: Simplifying techniques of circuit configuration
and their practical applications, IEEE Trans. Electron Devices, 40
(5): 974979, 1993.
11. W. Weber et al., On the application of the neuron MOS transistor
principle for modern VLSI design, IEEE Trans. Electron Devices,
43 (10): 17001708, 1996.
12. N. Balabbes et al., Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays, IEEE Trans. Circuits Syst. I,
Fundam. Theory Appl., 43 (2): 143152, 1996.
13. M. J. Avedillo et al., Low-power CMOS threshold-logic gates,
Electron. Lett., 31 (25): 21572159, 1995.
14. J. Fernandez Ramos et al., A threshold logic gate based on
clocked coupled inverters, Int. J. Electron., 84 (4): 371382, 1998.
zdemir et al., A capacitive threshold-logic gate, IEEE J.
15. H. O
Solid-State Circuits, 31 (8): 11411150, 1996.
16. M. Furst, J. B. Saxe, and M. Sipser, Parity, circuits and the polynomial-time hierarchy, Proc. IEEE Symp. Found. Comp. Sci.,
1981, pp. 260270.
17. K-Y. Siu, V. P. Roychowdhury, and T. Kailath, Depth-size tradeoffs for neural computation, IEEE Trans. Comput., 40 (12): 1402
1412, 1991.
18. M. Goldmann, J. Hastad, and A. Razborov, Majority gates vs.
general weighted threshold gates, Proc. 7th Annu. Conf. Struct.
Complexity Theory, 1992, pp. 213.
19. M. Goldmann and M. Karpinski, Simulating threshold circuits by
majority circuits, Proc. 25th Annu. ACM Symp. Theory Comput.,
1993, pp. 551560.
20. K. Siu and V. P. Roychowdhury, An optimal-depth threshold circuit for multiplication and related problems, Soc. Ind. Appl. Math.
J. Discrete Math., 7 (2): 284292, 1994.

23. A. L. Oliveira and A. Sangiovanni-Vincentelli, LSATAn algorithm for the synthesis of two level threshold gate networks,
Proc. Int. Conf. Comput. Aided Design, 1991, pp. 130133.
24. P. D. Wendt, E. J. Coyle, and N. C. Gallagher Jr., Stack filters,
IEEE Trans. Acoust. Speech Signal Process., 34 (4), 898911,
1986.
25. B. I. Justusson, Median filtering: Statistical properties, in T. S.
Huang (eds.), Two-Dimensional Digital Signal Processing II, New
York: Springer, 1981.
26. L. Yin et al., Weighted median filters: A tutorial, IEEE Trans.
Circuits Syst. II Analog Digit. Signal Process., 43 (3), 157192,
1996.

MARIA J. AVEDILLO
JOSE M. QUINTANA
ADORACION RUEDA
University of Seville

THYRISTOR. See THYRISTOR PHASE CONTROL.

TIME-VARYING FILTERS

249

TIME-VARYING FILTERS
In many applications of digital signal processing it is necessary that different sampling rates coexist within a system.
One common example is two systems working at different
sampling rates; they have to communicate and the sampling
rates have to be made compatible. Another common example
is a wideband digital signal that is decomposed into several
nonoverlapping narrowband channels in order to be transmitted. In this case, each narrowband channel can have its sampling rate decreased until its Nyquist limit is reached,
thereby saving transmission bandwidth.
In this article we will describe such systems. They are generally referred to as multirate systems. Most of them have
one property in common: They are not shift invariant or they
are, at most, periodically shift invariant.
First, we will describe the basic operations of decimation
and interpolation and show how arbitrary rational samplingrate changes can be implemented using them. Then, we will
deal with filter banks, showing several ways by which a signal
can be decomposed into critically decimated frequency bands,
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

250

TIME-VARYING FILTERS

and then be recovered from them with minimum error. Finally, wavelet transforms will be considered. They are a relatively recent development of functional analysis that is arousing great interest in the signal processing community, and
their digital implementation can be regarded as a special case
of critically decimated filter banks.
DECIMATION, INTERPOLATION, SAMPLING-RATE CHANGES
Intuitively, any sampling-rate change can be effected by recovering the band-limited analog signal y(t) from its samples
x(m), and then resampling it with a different sampling rate,
thus generating a different digital signal x(n). Of course the
intermediate analog signal x(t) must be filtered so that it can
be resampled without aliasing. As an example, suppose we
have a digital signal x(m) that was generated from an analog
signal y(t) with sampling period T1, that is x(m) y(mT1),
m . . ., 0, 1, 2 . . .. It is assumed that y(t) is band limited
to [/T1, /T1]. Therefore, by replacing each sample of the
signal by an impulse proportional to it, we have the equivalent analog signal:

y (t) =

x(m)(t mT1 )

(1)

m=

Its spectrum is periodic with period 2/T1. In order to recover

the original analog signal y(t) from y(t), the repetitions of the
spectrum must be discarded. Therefore, y(t) must be filtered
with a filter h(t) whose ideal frequency response H( j) is as
follows (1):



1 ,
T1 T1
H( j) =
(2)

0, otherwise
It is then easy to show that (1)
y(t) = y (t) h(t) =

1 

x(m)sinc
(t mT1 )
T1 m=
T1

(3)

Then, resampling y(t) with period T2, generating the digital

signal x(n) y(nT2), n . . ., 0, 1, 2 . . ., we have
x(n) =

1 

x(m)sinc (nT2 mT1 )

T1 m=
T1

Figure 2. (a) Spectrum of the original

signal. (b) Spectrum of the signal decimated by a factor of 2.

(4)

x(m)

xd(n)

Figure 1. Decimation by a factor of M.

This is the general equation governing sampling-rate

changes. Observe that there is no restriction on the values of
T1 and T2. Of course, if T2 T1, and aliasing is to be avoided,
the filter in Eq. (2) must have a frequency response equal to
zero for [/T2, /T2].
Since this equation consists of infinite summations involving the sinc( ) function, it is impractical to use it (1). In general, for rational sampling-rate changes, which cover most
cases of interest, one can derive expressions working solely
on the digital domain. This will be covered in the next three
subsections, where three special cases will be considered: decimation by an integer factor M, interpolation by an integer
factor L, and sampling-rate change by a rational factor L/M.
Decimation
To decimate (or subsample) a digital signal x(m) by a factor of
M is to reduce its sampling rate M times. It is equivalent to
keeping only every Mth sample of the signal. It is represented
as in Fig. 1.
The decimated signal is then xd(n) x(nM). In the frequency domain, if the spectrum of x(m) is X(ej), the spectrum
of the subsampled signal, Xd(ej), becomes (see Appendix A)

Xd (e j ) =


1 M1
2 k
X (e j M )
M k=0

(5)

As illustrated in Figs. 2(a) and 2(b) for M 2, Eq. (5)

means that the spectrum of xd(n) is composed of copies of the
spectrum of x(m) expanded by M and repeated with period
2. This implies that, in order to avoid aliasing after subsampling, the bandwidth of the signal x(m) must be limited to the
interval [/M, /M]. Therefore, the subsampling operation
is generally preceded by a low-pass filter [see Fig. 5(a)], which
approximates the following frequency response:
 

1, ,
j
M M
Hd (e ) =
(6)
0, otherwise

TIME-VARYING FILTERS

x(m)

xi(n)

x(m)

Hd(z)

251

xd(n)

(a)

Figure 3. Interpolation by a factor of L.

x(m)

Some important facts must be noted about the decimation

operation:

Hi(z)

xi(n)

(b)

It is shift varying, that is, if the input signal x(m) is

shifted, the output signal will not generally be a shifted
version of the previous output. More precisely, be D M the
decimation by M operator. If xd(n) D Mx(m), then in
general D Mx(m k) xd(n k). However, D Mx(m
Mk) xd(n k). Because of this property, the decimation is referred to as a periodically shift-invariant operation (2).
Referring to Fig. 5(a), one can notice that, if the filter
Hd(z) is FIR, its outputs need only be computed every M
samples, which implies that its implementation complexity is M times smaller than the one of a usual filtering
operation. This is not generally valid for IIR filters. One
case when this sort of reduction in complexity can be obtained is for IIR filters with transfer function of the type
H(z) N(z)/D(zM) (2).
If the frequency range of interest for the signal x(m) is
[p, p], with p /M, one can afford aliasing outside
this range. Therefore, the constraints upon the filter can
be relaxed, yielding the following specifications for Hd(z)
(2):

Hd (e j )

1, || [0, p ]


=
2k
2k

,
0,
||

p
p , k = 1, 2, . . ., M 1
M
M

(7)

Interpolation
To interpolate (or upsample) a digital signal x(m) by a factor
of L is to include L 1 zeros between its samples. It is represented as in Fig. (3).

Figure 5. (a) General decimation operation. (b) General interpolation operation.

The interpolated signal is then


x(n/L), n = kL, k Z
xi (n) =
0,
otherwise

(8)

In the frequency domain, if the spectrum of x(m) is X(ej),

it is straightforward to see that the spectrum of the interpolated signal, Xi(ej), becomes (2)
Xi (e j ) = X (e jL )

(9)

Figures 4(a) and 4(b) exemplify the spectra of the signals

x(m) and xi(n) for an interpolation factor of L.
Since the digital signal is periodic with period 2, the interpolated signal will have period 2/L. Therefore, in order to
obtain a smooth interpolated version of x(m), the spectrum of
the interpolated signal must have the same shape of the spectrum of x(m). This can be obtained by filtering out the repetitions of the spectra beyond [/L, /L]. Thus, the up-sampling operation is generally followed by a low-pass filter [see
Fig. 5(b)] which approximates the following frequency response:
 

L, ,
j
L L
Hi (e ) =
(10)
0, otherwise
Some important facts must be noted about the interpolation operation:

X( )

2 2 + p p

2 p

( )

8
L

( )

(a)
Xi()

8
L

6
L

4
L

2
L
L

0
(b)

2
L

4
L

6
L

Figure 4. (a) Spectrum of the original

signal. (b) Spectrum of the signal after interpolation by L.

252

TIME-VARYING FILTERS

As with the decimation operation, the interpolation is

only periodically shift invariant. More precisely, if I L is
the interpolation by L operator, xi(n) I Lx(m) implies
that I Lx(m k) xi(n kL) (2).
Referring to Fig. 5(b), one can notice that the computation of the output of the filter Hi(z) uses only one out of
L samples of the input signal because the remaining
samples are zero. This means that its implementation
complexity is L times smaller than the one of a usual
filtering operation.
If the signal x(m) is band limited to [p, p], the repetitions of the spectrum will only appear in a neighborhood
of radius p /L around the frequencies 2k/L, k 1, 2,
. . ., L 1. Therefore, the constraints upon the filter can
be relaxed as in the decimation case, yielding (2)

 
p

L,
||

0,

L
j


Hi (e ) =
2k p 2k + p

,
k = 1, 2, . . ., L 1
0, ||
L
L
(11)
The gain factor L in Eqs. (10) and (11) can be understood by
noting that since we are maintaining one out of L samples of
the signal, the average energy of the signal decreases by a
factor L2, and therefore the gain of the interpolating filter
must be L.
Supposing L 2, two common examples of interpolators
are
Hi(z) 1 z1 zero-order hold
Hi(z) 
(z 2 z1)linear interpolation
Rational Sampling-Rate Changes
A rational sampling rate change by a factor L/M can be implemented by cascading an interpolator by a factor of L with a
decimator by a factor of M. This is exemplified in Fig. 6.
Since H(z) is an interpolation filter, its cutoff frequency
must be less than /L. However, since it is also a decimation
filter, its cutoff frequency must be less than /M. Therefore,
it must approximate the following frequency response:


H(e j ) =

L, || min
0,

 
,
L M

(12)

x(m)
H(z)

xd(n)

x(m)
M

H(z)

Figure 7. Decimation followed by interpolation.

M can be assumed to be relatively prime, this yields:

 
p

L, || < min L , M


H(e j ) =
p 2
p
2

||
0, min
L
L M
L

(13)

Inverse Operations
At this point, a natural question to ask is: are the decimation
by M (D M) and interpolation by M (I M) operators inverses of
each other? In other words, is D MI M I MD M identity?
It is easy to see that D MI M identity, because the M 1
zeros between samples inserted by the interpolation operation
are removed by the decimation, thereby restoring the original
signal. On the other hand, I MD M is not an identity, since the
decimation operation removes M 1 out of M samples of the
signal and the interpolation operation inserts M 1 zeros
between samples. Their cascade is equivalent to replacing
M 1 out of M samples of the signal with zeros, which is
obviously not an identity.
However, if the decimation by M operation is preceded by
a band-limiting filter from /M to /M [Eq. (6)], and the
interpolation operation is followed by the same filter, then
I MD M becomes an identity (see Fig. 7). This can be easily
seen in the frequency domain. The band-limiting filter prevents aliasing after decimation, and the spectrum of the decimated signal will be in [, ]. After interpolation by M,
there will be images of the spectrum of the signal in the intervals [k/M, (k 1)/M], k M, M 1, . . . M 1. The
band-limiting filter will keep only the image in [/M, /M],
which corresponds to the original signal.
Filter Design Using Interpolation
A very interesting application of interpolation is in filter design. Since the transition bandwidths of the interpolated
signal are L times smaller than the ones of the original signal, this fact can be used to generate sharp cutoff filters with
low computational complexity. A very good example is given
by the frequency masking approach (3). The process is
sketched in Fig. (8), for an interpolation ratio of L 4.

otherwise

Likewise the case of decimation and interpolation, the

specifications of H(z) can be relaxed if the bandwidth of
the signal is smaller than p. The relaxed specifications are
the result of cascading the specifications in Eq. (11), with the
specifications in Eq. (7) for p replaced by p /L. Since L and

H1(z)

F1(z)
+

X(z)

Y(z)

x(m)

H(z)

xc(n)

Figure 6. Sampling rate change by a factor of L/M.

zD

F2(z)

Figure 8. Filter design and implementation using interpolation (frequency masking approach).

TIME-VARYING FILTERS

The idea is to generate a filter with a transition bandwidth

one-fourth that of the prototype filter H1(z). Initially, a prototype half-band filter H1(z) is designed with a given transition
bandwidth, four times larger than the one needed, and therefore, with implementation complexity much smaller than the
one of a direct design (1). From this prototype, its complementary filter H2(z) is generated by a simple delay and subtraction, that is, H2(z) zD H1(z). Their frequency responses
are illustrated in Fig. 9(a). After interpolation, their responses are as shown in Fig. 9(b). The filters F1(z) and F2(z)
serve to select the parts of the interpolated spectrum of H1(z)
and H2(z) that will be used in composing the desired filter
response F(z) Y(z)/X(z) [see Fig. 9(b)]. It is interesting to
note that F1(z) and F2(z), besides being interpolation filters,
are allowed to have large transition bandwidths, and therefore have low implementation complexity (1). As can be seen
from Fig. 9(c), one can generate large bandwidth sharp cutoff
filters with low implementation complexity.

x(n)

H0(z)

x0(n)

H1(z)

x1(n)

253

HM 1(z)

xM 1(n)

Figure 10. Decomposition of a digital signal into M frequency bands.

FILTER BANKS

H1( )

( )

( )

H2( )

2
(a)
H1(4)

F1(w)

H2(4)

( )

In a number of applications, it is necessary to split a digital

signal x(n) into several frequency bands, as in Fig. 10.
In this case, each of the bands xk(n), k 0, . . ., M 1,
has at least the same number of samples as the original signal x(n). This implies that after the M-band decomposition,
the signal is represented with at least M times more samples
than the original one. However, there are many cases in
which this expansion on the number of samples is highly undesirable. One such case is signal transmission (4), where
more samples mean more bandwidth and consequently increased transmission costs.
In the common case where the signal is uniformly split in
the frequency domain, that is, each of the frequency bands
xk(n) has the same bandwidth, a natural question to ask is:
Since the bandwidth of each band is M times smaller than
the one of the original signal, could the bands xk(n) be decimated by a factor of M without destroying the original information? If this were possible, then one could have a digital
signal split into several frequency bands without increasing
the overall number of samples. In other words, the question
is whether it is possible to recover exactly the original signal
from the decimated bands. This section examines several
ways to achieve this.

F2(w)

Decimation of a Band-Pass Signal and Its Inverse Operation

( )

(b)
F()

( )
(c)

Figure 9. (a) Prototype half-band filter H1(z) and its complementary

H2(z). (b) Frequency responses of H1(z) and H2(z) after interpolation
by a factor of 4. Notice the responses of F1(z) and F2(z). (c) Frequency
response of the equivalent filter F(z).

Decimation of a Band-Pass Signal. As was seen in the section

entitled Decimation, if the input signal x(m) was low pass
and band limited to [/M, /M], the aliasing after decimation by a factor of M could be avoided [see Eq. (5)]. However,
if a signal is split into M uniform frequency bands, at most
one band will have its spectrum confined to [/M, /M]. In
fact, if a signal is split into M uniform real bands, one can
say that band xk(n) will be confined to [(k 1)/M, k/M]
[k/M, (k 1)/M] [1] (see Fig. 11).
This implies that band k, k 0 is not confined to [/M,
/M]. However, by examining Eq. (5) one can notice that
aliasing is still avoided in this case. The only difference is
that, after decimation, the spectrum contained in [(k 1)/
M, k/M] is mapped to [0, ] if k is odd, and to [, 0] if k
is even. Similarly, the spectrum contained in the interval
[k/M, (k 1)/M] is mapped to [, 0] if k is odd and to [0,

254

TIME-VARYING FILTERS

] if k is even (2). Then, the decimated band k will look as in

Figs. 12(a) and 12(b) for k odd and even, respectively.

Xk( )
X0( )

(k + 1) k
M
M

k
M

(k + 1) ()
M

Figure 11. Uniform split of a signal into M bands.

( )

(a)

( )

(b)
Figure 12. Spectrum of band k decimated by a factor of M: (a) k odd;
(b) k even.

(k + 1)
M

k
M

k
M

(k + 1)
M

()

Figure 13. Spectrum of band k after decimation and interpolation

by a factor of M for k odd.

x(n)

Inverse Operation for Bandpass Signals. We have seen above

that a band-pass signal can be decimated by M without
aliasing, provided that its spectrum is confined to [(k 1)/
M, k/M] [k/M, (k 1)/M]. The next natural question
is: Can the original band-pass signal be recovered from its
decimated version by an interpolation operation? The case of
low-pass signals was examined in the subsection entitled Inverse Operations.
The spectrum of a decimated band-pass signal is as in
Figs. 12(a) and 12(b) for k odd and even, respectively. After
interpolation by M, the spectrum for k odd will be as in Fig.
13.
We want to recover band k as in Fig. 11. From Fig. 13 it is
clearly seen that it suffices to keep the region of the spectrum
in [(k 1)/M, k/M] [k/M, (k 1)/M]. The case for
k even is entirely analogous. The process of decimating and
interpolating a band-pass signal is then very similar to the
case of a low-pass signal (see Fig. 7), with the difference that
H(z) is a band-pass filter with bandwidth [(k 1)/M,
k/M] [k/M, (k 1)/M].
Critically Decimated M-Band Filter Banks. It is clear that if
a signal x(m) is decomposed into M non-overlapping bandM1
pass channels Bk, k 0, . . ., and M 1 such that k0
Bk [, ], then it can be recovered from these M channels
by just summing them up. However, as conjectured above, exact recovery of the original signal might not be possible if
each channel is decimated by M. However, in the section entitled Decimation of a Band-Pass Signal and Its Inverse Operation, we examined a way to recover the band-pass channel
from its subsampled version. All that is needed are interpolation operations followed by filters with passband
[(k 1)/M, k/M] [k/M, (k 1)/M] (see Fig. 13).
This process of decomposing a signal and restoring it from the
frequency bands is depicted in Fig. 14. We often refer to it as
an M-band filter bank. The frequency bands uk(n) are called
sub-bands. If the input signal can be recovered exactly from
its sub-bands, it is called an M-band perfect reconstruction
filter bank. Figure 15 details a perfect reconstruction filter
bank for the 2-band case.
However, the filters required for the M-band perfect reconstruction filter bank described above are not realizable [see
Eqs. (6) and (10)], that is, at best they can be only approximated (1). Therefore, in a first analysis, the original signal

H0(z)

H1(z)

u0(m)

u1(m)

G0(z)

G1(z)

HM 1(z)

Figure 14. M-band filter bank.

y(n)

uM 1(m)

GM 1(z)

TIME-VARYING FILTERS

xl

H0(z)

0
0
0

/2

/2

Sl

/2

rl

/2

yl

G0(z)

0
0

/2

/2

/2

/2

/2

/2

0
0

H1(z)

/2

xh

/2

Sh

/2

rh

0
0

/2

/2

Sl

/2

rl

/2

+


+


h(2l)z2l + z1

l=

h(Ml)zMl + z1

+


h(2l + 1)z2l

l=
+


h(Ml + 1)zMl

l=
+


+ + zM+1

(14)

h(Ml + M 1)zMl

l=

M1


z j E j (zM )

j=0

where Ej(z) l h(Ml j)zl are called polyphase components of the filter H(z).
Equation 14 is a polyphase decomposition (5) of the filter
H(z). In the polyphase decomposition we decompose the filter
H(z) into M filters, the first one with every sample of h(m)
whose indexes are multiples of M, the second one with every
sample of h(m) whose indexes are one plus a multiple of M,
and so on. Using a polyphase decomposition, filtering followed
by decimation can be represented as in Fig. 18(b). Applying
the noble identities to this figure, we arrive at Fig. 18(c) (5).
Figure 18(c) provides an interesting and useful interpretation to the operation of filtering followed by decimation. Figure 18(c) means that this operation is equivalent to filtering
the samples of x(m), whose indexes are equal to an integer k
plus a multiple of M with a filter composed by only the samples of h(m) whose indexes are equal to the same integer k
plus a multiple of M, for k 0, . . . M 1.
The polyphase decompositions also provide useful insights
into the interpolation operation, but in these cases an alterna-

yl

0
0

h(k)zk =

l=

G0(z)

+


Polyphase Decompositions. The Z transform H(z) of a filter

h(n) can be written as

Figure 15. Two-band perfect reconstruction filter bank using ideal filters.

k=

Noble Identities. The noble identities are depicted in Figs.

17(a) and 17(b). They have to do with the commutation of the
filtering and decimation or interpolation operations. They are
very useful in analyzing multirate systems and filter banks.
Their proof can be found in Appendix B.

xl

yh

H(z) =

Perfect Reconstruction

H0(z)

0 /2

G1(z)

would be only approximately recoverable from its decimated

frequency bands. This is well illustrated in Fig. 16, which details a 2-band filter bank using nonideal (or nonrealizable)
filters.
In Fig. 16, one can notice that since the filters H0(z) and
H1(z) are not ideal, the subbands sl(m) and sh(m) will have
aliasing. In other words, the signals xl(n) and xh(n) cannot be
respectively recovered from sl(m) and sh(m). Nevertheless, by
closely examining Fig. 16, one can see that since yl(n) and
yh(n) are added in order to obtain y(n), the aliased components
of yl(n) will be combined with the ones of yh(n). Therefore, at
least in principle, there exists the possibility that these aliased components cancel out and y(n) is equal to x(n), that is,
the original signal can be recovered from its subbands. This
is indeed the case, not only for the 2-band but also for the
general M-band case (5). In the remainder of this section we
will examine methods of designing the analysis filters Hk(z)
and the synthesis filters Gk(z) so that perfect reconstruction
can be achieved, or at least arbitrarily approximated.

255

/2

/2

/2

/2

/2

H1(z)

0
0

/2

xh

/2

Sh

/2

rh

/2

G1(z)

0 /2

yh

Figure 16. Two-band filter bank using

realizable filters.

256

TIME-VARYING FILTERS

x(m)

y(n)

H(z)

x(m)

y(n)

G(z)
(a)

R0(z)

x(m)

x(m)

H(zM)

y(n)

z1
R1(z)

(a)
x(m)

M
z1

H(z)

.
.
.

y(n)

.
.
.

.
.
.

RM-1(z)

.
.
.
z1

y(n)

(b)

x(m)

H(zM)

y(n)

Figure 19. (a) Interpolation by a factor of M. (b) Interpolation using

polyphase decompositions and the noble identities.

(b)

In Fig. 20(a), the model with decimators and delays is noncausal, having advances instead of delays. In causal systems, the causal model of Fig. 21 is preferred.

Figure 17. Noble identities. (a) Decimation. (b) Interpolation.

tive to Eq. (14) is usually employed. In it, we define Rj(z)

EM1j(z), and the polyphase decomposition becomes:

H(z) =

M1


z(M1 j) R j (zM )

(15)

j=0

Based in Eq. (15), interpolation followed by filtering can be

represented in a manner analogous to the one in Fig. 18(c),
as depicted in Fig. 19(b) (5).
Commutator Models. The operations described in Figs.
18(c) and 19(b) can also be interpreted in terms of rotary
switches. These interpretations are referred to as commutator
models. In them, the decimators and delays are replaced by
rotary switches as depicted in Figs. 20(a) and 20(b) (5).

x(m)

M-Band Filter Banks in Terms of the Filters Polyphase Components. By substituting each of the filters Hk(z) and Gk(z) by its
polyphase components, the M-band filter bank of Fig. 14 becomes as in Fig. 22(a). The matrices E(z) and R(z) are formed
from the polyphase components of Hk(z) and Gk(z). Eij(z) is the
jth polyphase component of Hi(z) [see Eq. (14)] and Ruv(z) is
the uth polyphase component of Gv(z) [see Eq. (15)] (5). In Fig.
22(b), the noble identities were applied.
Perfect Reconstruction M-Band Filter Banks. In Fig. 22(b), if
R(z)E(z) I, where I is the identity matrix, the M-band filter
bank becomes as in Fig. 23.
By substituting the decimators and interpolators in Fig. 23
by the commutator models of Figs. 21 and 20(b), respectively,
we arrive at the scheme depicted in Fig. 24, which is clearly
equivalent to a pure delay. Therefore, the condition

H(z)

y(n)

(a)

E0(zM)

x(m)

x(m)

z1
E1(zM)

z1

z1

E0(z)

E1(z)

z1

.
.
.
Figure 18. (a) Decimation by a factor of
M. (b) Decimation using polyphase decompositions. (c) Decimation using polyphase
decompositions and the noble identities.

z1

.
.
.

.
.
.

EM-1(zM)

(b)

.
.
.

.
.
.
y(n)

.
.
.

.
.
.

z1
EM-1(z)

M
(c)

.
.
.
y(n)

TIME-VARYING FILTERS

x0(m)

x0(m)

x1(m)

257

z
x1(m)

x(n)

.
.
.

.
.
.
xM1(m)

n=0

x(n)

xM1(m)

(a)

x0(m)

x0(m)

M
z1

x1(m)
x1(m)

x(n)

.
.
.
xM1(m)

.
.
.
z1

xM1(m)

n=0

x(n)
M
Figure 20. Commutator models for (a)
Decimation. (b) Interpolation.

(b)

R(z)E(z) I guarantees perfect reconstruction for the M-band

filter bank (5). It should be noted that if R(z)E(z) is equal to
the identity times a pure delay, perfect reconstruction still
holds. Therefore, the weaker condition R(z)E(z) ZI is sufficient for perfect reconstruction.

Clearly R(z)E(z) I. The polyphase components Eij(z) of the

analysis filters Hi(z), and Ruv(z) of the synthesis filters Gv(z)
are then:
E00 (z) =

Example. Two-Band Perfect Reconstruction Filter Bank

Be M 2, and

1

E(z) =

R(z) =

1
2

R00 (z) = 1

1
1

1
2

H0 (z) =
(17)

12

x(n)

n=0

E11 (z) = 1 (18)

R10 (z) = 1

R11 (z) =

1
(19)
2

1
(1 + z1 )
2

(20)
(21)

x0(m)

z1
M

.
.
.

E10 (z) = 1

H1 (z) = 1 z1

x1(m)

zM+1

1
2
1
R01 (z) =
2
E01 (z) =

Then, from Eqs. (19) and (14) we can find the Hk(z), and
from Eqs. (18) and (15) we can find the Gk(z). They are

(16)

x0(m)

x(n)

1
2

x1(m)

.
.
.
xM1(m)

z1

xM1(m)
M

Figure 21. Causal commutator model

for decimation.

258

TIME-VARYING FILTERS

x(n)

x0(m)

z1

z1
M

x(n)

z1

R(zM)

.
.
.

.
.
.

.
.
.

y(n)
zM + 1

.
.
.

z1

xM 1(m)

z1
M

z1

What is very interesting in this case is that the filters need

not be selective at all in order for this kind of transmultiplexer to work (see Fig. 26).

z1
M

z1

M
E(z)

.
.
.

n=0

Figure 24. The commutator model of an M-band filter bank when

R(z)E(z) I is equivalent to a pure delay.

(a)

x(n)

n=0

y(n)

...

E(zM)

...

z1

x1(m)

.
.
.

z1

R(z)

.
.
.

.
.
.

.
.
.

z1

z1
M

y(n)

Two-Band Perfect-Reconstruction Filter Banks. The two-band

case is as seen in Fig. 27.
Representing the filters H0(z), H1(z), G0(z), and G1(z) in
terms of their polyphase components [Eqs. (14) and (15)], we
have

(b)

H0 (z) = H00 (z2 ) + z1 H01 (z2 )

Figure 22. (a) M-band filter bank in terms of the polyphase components of the filters. (b) Same as in (a) but after application of the
noble identities.

G0 (z) = 1 + z1

(22)

1
G1 (z) = (1 z1 )
2

(23)

This is known as the Haar filter bank. The normalized frequency responses of H0(z) and H1(z) are depicted in Fig. 25.
One can see that perfect reconstruction could be achieved
with filters that are far from being ideal. In other words, even
though each subband is highly aliased, one can still recover
the original signal exactly at the output.
Transmultiplexers. If two identical M-channel perfect reconstruction filter banks as in Fig. 14 are cascaded, we have that
the signal corresponding to uk(m) in one filter bank is a delayed version of the corresponding signal in the other filter
bank, for each k 0, . . ., M 1. Therefore, with the same
filters as in Fig. 14, one can construct a perfect reconstruction
transmultiplexer as in Fig. 26, which can combine the M signals uk(m) into one single signal y(n) and then recover the
signals vk(m), which are just delayed versions of the uk(m) (5).

H1 (z) = H10 (z ) + z

M
z1
M

x0(m)
x1(m)

G0 (z) = z1 G00 (z2 ) + G01 (z2 )

(26)

G1 (z) = z

xM 1(m)

G10 (z ) + G11 (z )
2

(27)

The matrices E(z) and R(z) in Fig. 22(b) are then

E(z) =

H00 (z)
H10 (z)

H01 (z)
H11 (z)

R(z) =

G00 (z)
G01 (z)

G10 (z)
G11 (z)

(28)

If R(z)E(z) I we have perfect reconstruction (Figs. 23 and

24). In fact, from Fig. 24, we see that the output signal will
be delayed by M 1 1 sample. In the general case, one can
have R(z)E(z) Iz, which makes the output signal to be
delayed by 1. Therefore, the 2-band filter bank will be
equivalent to a delay of 1 samples if
R(z) = z E 1 (z)

(29)

1
H0

H1

0.6

z1
M

0.4
0.2

...

...
z1

(24)
(25)

0.8

x(n)

H11 (z )

z1
y(n)

Figure 23. M-band filter bank when R(z)E(z) I.

0.5

1.5
2
Freq.

2.5

Figure 25. Normalized frequency responses of the filters described

by Eqs. (20) and (21).

TIME-VARYING FILTERS

G0(z)

G1(z)

GM1(z)

H0(z)

H1(z)

HM1(z)

y(n)

(m)

...

u0

(m)

uM 1 (m)

v0

(m)

v1

(m)

...

u0

259

vM 1 (m)

Figure 26. M-band transmultiplexer.

From Eq. (28), this implies that

G00 (z)
G01 (z)

Equations (3436) suggest a possible way to design 2-band

perfect reconstruction filter banks. The design procedure is as
follows (4):

G10 (z)
G11 (z)

z
=
H00 (z)H11 (z) H01 (z)H10 (z)

H11 (z)
H10 (z)

H01 (z)
H00 (z)

(30)

Equation (30) is enough for IIR filter design, as long as

stability constraints are taken into consideration. However, if
we want the filters to be FIR, as is often the case, the term in
the denominator must be a pure delay. Therefore,
H00 (z)H11 (z) H01 (z)H10 (z) = czl

(31)

From Eqs. (2427) we can express the polyphase components in terms of the filters Hk(z) and Gk(z) as

H0 (z) + H0 (z)
2
H1 (z) + H1 (z)
2
H10 (z ) =
2
H00 (z2 ) =

H0 (z) H0 (z)
2z1
(z)
H1 (z)
H
H11 (z2 ) = 1
2z1

(32)

G0 (z) + G0 (z)
2
G1 (z) + G1 (z)
2
G11 (z ) =
2

(33)

H01 (z2 ) =

G0 (z) G0 (z)
2z1
G (z) G1 (z)
G10 (z2 ) = 1
2z1
G00 (z2 ) =

G01 (z2 ) =

(34)

Now, substituting Eq. (31) into Eq. (30), and computing

the Gk(z) from Eqs. (26) and (27), we arrive at
G0 (z) =
G1 (z) =

z2(l)
H1 (z)
c

(35)

z2(l)
H0 (z)
c

Some important points should be noted in this case:

If one wants the filter bank to be composed of linear
phase filters, it suffices to find a linear phase product
filter P(z), and make linear phase factorizations of it.
If the delay is zero, some of the filters will certainly be
noncausal: for l negative, either H0(z) or H1(z) must be
noncausal [see Eq. (34)]; for l positive, either G0(z) or
G1(z) must be noncausal. Therefore, a causal perfect reconstruction filter bank will always have nonzero delay.
The magnitudes of the frequency responses, G0(ej) and
H1(ej), are mirror images of each other around /2
[Eq. (35)], the same happening to H0(ej) and G1(ej)
[Eq. (36)].
Design Examples. One product filter P(z) satisfying P(z)
P(z) 2z2l1 is

Substituting Eq. (32) into Eq. (31), we have that

H0 (z)H1 (z) H0 (z)H1 (z) = 2cz2l1

1. Find a polynomial P(z) such that P(z) P(z)

2z2l1.
2. Factorize P(z) into two factors, H0(z) and H1(z). Care
must be taken in order that H0(z) and H1(z) be lowpass.
3. Find G0(z) and G1(z) using Eqs. (35) and (36).

(36)

1
(1 + 9z2 + 16z3 + 9z4 z5 )
16
1
(1 + z1 )4 (1 + 4z1 z2 )
=
16

P(z) =

We can see from its frequency response in Fig. 28(a) that

P(z) is a low-pass filter.
One possible factorization of P(z) results in the following
filter bank [Eqs. (35) and (36)], a popular symmetric short
length filter (4):
1
(1 + 2z1 + 6z2 + 2z3 z4 )
8
1
G0 (z) = (1 + 2z1 + z2 )
2
1
H1 (z) = (1 2z1 + z2 )
2
1
G1 (z) = (1 + 2z1 6z2 + 2z3 + z4 )
8

H0 (z) =
u0(m)
H0(z)

G0(z)

x(n)

y(n)

H1(z)

u1(m)

Figure 27. Two-band filter bank.

G1(z)

(37)

Their frequency responses are depicted in Fig. 28(b).

(38)
(39)
(40)
(41)

260

TIME-VARYING FILTERS

Particular Cases of Filter Bank Design

In the section entitled Perfect Reconstruction, we examine

general conditions to design perfect reconstruction filter
banks. In the remainder of this section we will analyze some
specific filter bank types which have been used a great deal
in practice.

1.5
1
0.5
0

0.5

1.5
2
Freq
(a)

2.5

Quadrature Mirror Filter Banks. An early, proposed approach

to the design of 2-band filter banks is the so-called quadrature
mirror filter bank (QMF) (6), where the analysis high-pass
filter is designed by alternating the signs of the low-pass filter
impulse response samples, that is

H1 (z) = H0 (z)

2
H0
H1

1.5

where we are assuming the filters have real coefficients. For

this choice of the analysis filter bank, the magnitude response
of the high-pass filter (H1(ej)) is the mirror image of the lowpass filter magnitude response (H0(ej)) with respect to the
quadrature frequency /2. This is the origin of the QMF nomenclature.
The analysis of the 2-band filter bank illustrated in Fig. 27
can be alternatively made as follows. The signals after the
analysis filter are described by

1
0.5
0

0.5

1.5
2
Freq

2.5

Xk (z) = Hk (z)X (z)

(b)

(47)

for k 0, 1. The decimated signals are

2
H0
H1

1.5

Uk (z) =

1
[X (z1/2 ) + Xk (z1/2 )]
2 k

(48)

for k 0, 1, whereas the signal after the interpolator are

1
[X (z) + Xk (z)]
2 k
1
= [Hk (z)X (z) + Hk (z)X (z)]
2

Uk (z2 ) =

0.5
0

(46)

0.5

1.5
2
Freq

2.5

(49)

Then, the reconstructed signal is represented as

(c)
Figure 28. Frequency responses of (a) P(z) from Eq. (37); (b) H0 and
H1(z) from the factorizations in Eqs. (38) and (40); (c) H0 and H1(z)
from the factorizations in Eqs. (42) and (44).

Another possible factorization is as follows:

H0 (z) =

1
(1 + 3z1 + 3z2 z3 )
4

(42)

G0 (z) =

1
(1 + 3z1 + 3z2 + z3 )
4

(43)

H1 (z) =

1
(1 3z1 + 3z2 z3 )
4

(44)

G1 (z) =

1
(1 + 3z1 3z2 z3 )
4

(45)

Their frequency responses are depicted in Fig. 28(c).

In what follows we will examine some particular cases of
filter bank design that have been widely used in many classes
of applications.

Y (z) = G0 (z)U0 (z2 ) + G1 (z)U1 (z2 )

1
[H (z)G0 (z) + H1 (z)G1 (z)] X (z)
2 0
1
(50)
+ [H0 (z)G0 (z) + H1 (z)G1 (z)] X (z)
2



 H0 (z)
H1 (z)
G0 (z)
1;
=
X (z) X (z)
H0 (z) H1 (z)
G1 (z)
2
=

The last equality represents the so called modulation matrices representation of a two-band filter bank. The aliasing effect is represented by the terms containing X(z). A possible
solution to avoid aliasing is to choose the synthesis filters as
follows
G0 (z) = H1 (z)

(51)

G1 (z) = H0 (z)

(52)

Note that this choice keeps the desired features of G0(z) and
G1(z) being low-pass and high-pass filters, respectively. Also,
the alias is now canceled by the synthesis filters instead of

TIME-VARYING FILTERS

1
[H (z)G0 (z) + H1 (z)G1 (z)]
2 0
1
= [H0 (z)H1 (z) H1 (z)H0 (z)]
2

0
20
dB

being totally avoided by analysis filters, relieving the specifications of the latter filters (see the subsection entitled Maximally Decimated M-Band Filter Banks).
The overall transfer function of the filter bank after the
alias component is eliminated is given by

100

(54)

H(e j ) =

(55)

for N odd. For N even the sum becomes a subtraction, generating an undesirable zero at /2.
The design procedure consists of minimizing the following
objective function using an optimization algorithm

= 1 + 2 =

+ (1 )
0

|H0 (e j )|2 d



jN  2

 d
H(e j ) e

2 

80

(53)

Note that the QMF design approach of two-band filter banks

consists of designing the low-pass filter H0(z). The above equation also shows that perfect reconstruction is achievable only
if the polyphase components of the low-pass filter (E0(z) and
E1(z)) are simple delays. This limits the selectivity of the generated filters. As an alternative, we can choose H0(z) to be an
FIR linear-phase, low-pass filter, and eliminate any phase
distortion of the overall transfer function H(z), which in this
case also has linear phase.
In this case, the filter bank transfer function can be written as

e jN
[|H0 (e j )|2 + |H0 (e j( ) )|2 ]
2
e jN
=
[|H0 (e j )|2 + |H1 (e j )|2 ]
2

H0(z)
H1(z)

(56)

where s is the stopband edge, usually chosen a bit above

0.5. The parameter provides weighting between the stopband attenuation of the low-pass filter and the amplitude distortion of the filter bank, with 0 1. Although this objective function has local minima, a good starting point for the
coefficients of the low-pass filter and an adequate nonlinear
optimization algorithm lead to good results, that is, filter
banks with low amplitude distortions and good selectivity of
the filters. Usually, a simple window-based design provides a
good starting point for the low-pass filter. In any case, the
simplicity of the QMF design makes it widely used in prac-

0.5

1.5 2
Freq

2.5

2.5

(a)
0.006
0.005
0.004
0.003
0.002
0.001
0
0.001
0.002
0.003
0.004
0.005

dB

1
[H 2 (z) H02 (z)]
2 0
= 2z1 [E0 (z2 )E1 (z2 )]

H(z) =

40
60

H(z) =

where in the last equality we employed the alias elimination

constraint in Eq. (52).
In the original QMF design, the alias elimination condition
is combined with the alternating-sign choice for the high-pass
filter of Eq. (46). In this case the overall transfer function is
given by

261

0.5

1.5 2
Freq
(b)

Figure 29. Johnstons QMF design of order 15. (a) Magnitude responses. (b) Overall amplitude response.

tice. Figures 29(a) and 29(b) depict the magnitude responses

of the analysis filters of order 15 of a QMF design, along with
the amplitude response of the whole filter bank.
The nomenclature QMF filter banks is also used to denote
M-channel maximally decimated filter banks. For M-channel
QMF filter banks there are two design approaches that are
widely used, namely the perfect reconstruction QMF filter
banks and the pseudo-QMF filter banks. The perfect reconstruction QMF designs require the use of sophisticated nonlinear optimization programs because the objective function
is a nonlinear function of the filter parameters. In particular
for a large number of subbands, the number of parameters is
usually large. On the other hand, the pseudo-QMF designs
consist of designing a prototype filter, with the subfilters of
the analysis bank being obtained by the modulation of the
prototype. As a consequence, the pseudo-QMF filter has a
very efficient design procedure. However, only recently it was
discovered that the modulated filter banks could achieve perfect reconstruction. The pseudo-QMF filter banks are also
known as cosine-modulated filter banks, since they are designed by applying cosine modulation to a low-pass prototype
filter (see the section entitled Cosine-Modulated Filter
Banks).
Conjugate Quadrature Filter Banks. In the QMF design, it
was noted that designing the high-pass filter from the lowpass prototype by alternating the signs of its impulse response is rather simple, but the possibility of getting perfect
reconstruction is lost except for trivial designs. In a later
stage of development (see Ref. 7), it was discovered that by
time-reversing the impulse response and alternating the

262

TIME-VARYING FILTERS

signs of the low-pass filter, we can design perfect reconstruction filter banks with selective subfilters. The resulting filters
are called conjugate quadrature (CQF) filter banks.
Therefore, in the CQF design, we have that the analysis
high-pass filter is given by:
H1 (z) = zN H0 (z1 )

(57)

By verifying again that N must be odd, the filter bank transfer function is given by

H(e

e jN
[H0 (e j )H0 (e j ) + H0 (e j )H0 (e j )]
2
e jN
(58)
[P(e j ) + P(e j )]
=
2

)=

From Eqs. (3536) we have that, in order to guarantee perfect

reconstruction, the synthesis filters should be given by
G0 (z) = zN H0 (z1 )

(59)

G1 (z) = H0 (z)

(60)

Perfect reconstruction is equivalent to having the timedomain response of the filter bank equal to a delayed impulse,
that is,
h(n) = (n )

(61)

Now by examining H(e j) in Eq. (58), one can easily infer that
the time-domain representation of P(z) satisfies
p(n)[1 + (1)n ] = 2[n ( N)]

(62)

Therefore, the design procedure consists of the following

steps:
By noting that p(n) 0 for odd n except for n N, we
can start by designing a half-band filter of order 2N, specifically a filter whose average value of the passband and
stopband edges is equal to /2 (that is p s /2 /2)
and has the same ripple (hb) in the passband and stopband. In this case, the resulting half-band filter will have
zero samples on its impulse response for n odd. This halfband filter can be designed by using a standard minimax
approach for FIR filters. However, since the product filter P(ej) has to be positive, we should add (hb /2) to the
frequency response of the half-band filter in order to generate P(ej). The stopband attenuation of the half-band
filter should be at least twice the desired stopband attenuation of the low-pass filter plus 6 decibels (5).
If one wants the filter bank to be composed of linear
phase filters, it suffices to find a linear phase product
filter P(z), and make linear phase factorizations of it (see
the subsection entitled Two-Band Perfect-Reconstruction Filter Banks). For this case, we will obtain the trivial linear phase filters described in Eqs. (2023), that
show very little selectivity, as shown in Fig. 25.
The usual approach is to decompose P(z) such that H0(z)
has either near linear phase or has minimum phase. In
order to obtain near linear phase, one can select the zeros
of H0(z) to be alternatively from inside and outside the
unit circle as frequency is increased. Minimum phase is

obtained when all zeros are either inside or on the unit

circle of the Z plane.
Cosine-Modulated Filter Banks. The cosine-modulated filter
banks are an attractive choice for the design and implementation of filter banks with a large number of sub-bands. Their
main features are:
1. ease of design. It consists essentially of generating a
low-pass prototype whose impulse response satisfies
some constraints required to achieve perfect reconstruction;
2. low cost of implementation, measured in terms of multiplication count, since the resulting analysis and synthesis filter banks rely on the discrete cosine transform
(DCT), which is amenable to fast implementation and
can share the prototype implementation cost with each
subfilter.
In the cosine-modulated filter bank design, we begin by
finding a linear phase prototype low-pass filter H(z) whose
passband edge is 2/M and the stop-band edge is 2/M
, 2 being the transition band. For convenience, we assume
that the length of the prototype filter is an even multiple of
the number M of subbands, that is, N 2LM. Although the
actual length of the prototype can be arbitrary, this assumption greatly simplifies our analysis.
Given the prototype filter, we generate cosine-modulated
versions of it in order to obtain the analysis and synthesis
filter banks as follows:



N 1

(63)
hl (n) = 2h(n) cos (2l + 1)
n
+ (1)l
2M
2
4



N 1

(64)
gl (n) = 2h(n) cos (2l + 1)
n
(1)l
2M
2
4
for 0 n N 1 and 0 l M 1. We should notice that
in Eq. (63), the term that multiplies 2h(n) represents the (l,
n) element of the DCT matrix, cl,n.
The prototype filter can be represented on its polyphase
decomposition as follows

H(z) =

L1
 2M1

l=0

h(2lM + j)z(2lM+ j) =

j=0

2M1


z j E j (z2M ) (65)

j=0

where Ej(z) = l0 h(Ml j)zl are the polyphase components

of the filter H(z). With this formulation, the analysis filter
bank can be described as
L1

Hl (z) =

N1


hl (n)zn =

n=0

L1
 2M1

l=0

2LM1


cl,n h(n)zn

(66)

n=0

cl,n h(2lM + j)z (2lM + j)

(67)

j=0

The expression above can be further simplified if we explore

the following property:



N

(n + 2kM)
cos (2l + 1)
2M
2



N

n
(68)
= (1)k cos (2l + 1)
2M
2

TIME-VARYING FILTERS
x(m)

E0(z)

E1(z)

z1

z1

263

I+J

.
.
.

.
.
.

z1
EM1(z)

z1

H0(z)

H1(z)
DCT

EM (z)

EM+1(z)

.
.
.

.
.
.

z1

HM1(z)

IJ

.
.
.

.
.
.

z1
M

E2M+1(z)

Figure 30. Cosine-modulated filter bank.

which leads to

der to achieve perfect reconstruction, that is

(1)k cl,n = cl,n+2kM

(69)

With this relation and after a few manipulations, we can rewrite Eq. (67) as follows

Hl (z) =

2M1


cl,n z( j) E j (z2M )

e(z) =

H0 (z)
H1 (z)
..
.
HM1 (z)

 

j=0

E0 (z2M )

e(z) =

H0 (z)
H1 (z)
..
.
HM1 (z)

= (C1 C2 )

E0 (z2M )
z1 E1 (z2M )
..
.
(2M1)
z
E2M1 (z2M )




where C1 and C2 are matrices whose elements are cl,n and

cl,nM, respectively, for 0 l, n M 1. The above equation
and Eqs. (132134) suggest the structure of Fig. 30 for the
implementation of the cosine modulated filter bank. This
structure consists of the implementation of the polyphase
components of the prototype filter in cascade with a DCTbased matrix.
Equation (71) can be expressed in a convenient form to deduce the constraint on the prototype impulse-response in or-

..

.
E2M1 (z2M )

d(z)
zM d(z)

=
C1

(71)

0
E1 (z2M )

The above expression can be rewritten in a compact form as

follows

= C1 C2

(70)

E0 (z2M )

0
E1 (z2M )
..

.
EM1 (z2M )

+ zMC2

EM (z2M )

d(z)

EM+1 (z2M )
..
0

.
E2M1 (z2M )

(72)
= E(z )d(z)
M

(73)

where E(z) is the polyphase matrix as defined in Eq. (28).

264

TIME-VARYING FILTERS

In order to achieve perfect reconstruction in a filter bank

with M channels, we should have E(z)R(z) R(z)E(z) Iz.
However, it is well known (see Ref. 5), that the polyphase
matrix of the analysis filter bank can be designed to be paraunitary, that is ET(z1)E(z) I, where I is an identity matrix
of dimension M. In this case the synthesis filters can be easily
obtained from the analysis filter bank using either Eq. (64),
or
R(z) = z E 1 (z) = z E T (z1 )

(74)

The task remains of showing how the prototype filter can

be constrained such that the polyphase matrix of the analysis
filter bank becomes paraunitary. The desired result is the following: The polyphase matrix of the analysis filter bank becomes
paraunitary, for a real coefficient prototype filter, if and only if
E j (z1 )E j (z) + E j+M (z1 )E j+M (z) =

1
2M

(75)

for 0 j M 1. An outline of the proof of this result is

given in Appendix C. These M constraints can be reduced because the prototype filter has linear phase, that is, for M odd
0 j (M 1)/2 and for M even 0 j M/2 1.
The necessary and sufficient conditions for perfect reconstruction on cosine-modulated filter banks are equivalent to
having pairwise power complementary polyphase components
on the prototype filter. This property can be explored to further reduce the computational complexity of these type of filter banks by implementing the power complementary pairs
with lattice realizations, which are structures specially suited
for this task (see Ref. 5).
Figure 31 depicts the frequency response of the analysis
filters each with length 35, for a bank with five subbands.
The filters banks discussed in this section have as main
disadvantage the nonlinear phase of the analysis filters, an
undesirable feature in applications such as image coding. The
lapped orthogonal transforms (LOTs) were originally proposed to reduce the blocking effects caused by discontinuities
across block boundaries, specially for images (see Ref. 8). It
turns out that LOT-based filter banks are very attractive be-

10
0
10

Lapped Transforms. Although there are a number of possible designs for linear-phase filter banks with perfect reconstruction, the LOT-based design is simple to derive and to
implement. The term LOT applies to the cases where the
analysis filters have length 2M. Generalizations of the LOT
to longer analysis and synthesis filters (length LM) are available. They are known as the extended lapped transforms
(ELTs) proposed by Malvar (8) and the generalized LOT (GenLot) proposed in Ref. 9. The ELT is closely related to the cosine-modulated filter banks and does not produce linearphase analysis filters. The GenLot is a good choice when long
analysis filters (with high selectivity) are required together
with linear phase.
In this subsection we will briefly discuss the LOT filter
bank, where the analysis and synthesis filter banks have
lengths 2M. The analysis filters are given by

e(z) =

H0 (z)
H1 (z)
..
.
HM1 (z)



= C
1 C
2

(76)

z1
..
.

(77)

z(2M1)
where C1 and C2 are matrices whose elements are cl,n and
cl,nM, respectively, for 0 l, n M 1. The above equation
can also be rewritten in a more convenient form as

H0 (z)
H1 (z)
..
.
HM1 (z)

(78)

= {C
1 + zMC
2 } d(z)

(79)

= E(zM )d(z)

(80)

e(z) =

30

where E(z) is the polyphase matrix of the analysis filter bank.

The perfect reconstruction condition with paraunitary
polyphase matrices is generated if

40

R(z) = z E 1 (z) = z E T (z1 )

20

dB

cause they lead to linear-phase analysis filters and have fast

implementation. The LOT-based filter banks are members of
the family of lossless FIR perfect-reconstruction filter banks
with linear phase.

50

(81)

The polyphase matrix of the analysis filter bank becomes

lossless for a real coefficient prototype filter if the following
conditions are satisfied:

60
70
80

T

C
T
1 C1 + C2 C2 = I

(82)

90

C
T
1 C2

(83)

0.5

1.5
Freq

2.5

Figure 31. Frequency response of the analysis filters of a cosinemodulated filter bank.

C
T
2 C1

=0

where the last relation guarantees that the overlapping tails

of the basis functions are orthogonal. The proof of this result
is given elsewhere (8).

TIME-VARYING FILTERS

1/2

265

H0(z)

1/2

H1(z)

z1
1

.
.
.

1/2
H2(z)

.
.
.

.
.
.

.
.
.

.
.
.

z1

1/2

z1
M
2

1
DCT

M+1
2

M+2
2

z1

z1

H
1

.
.
.

1/2

1/2

z1

.
.
.
z1

1
M

H
(z)
M1

C2

1
=
2

Ce Co
Ce Co

J(Ce Co )
J(Ce Co )

L0 =
(85)

1
2
1
2

Ce Co
Ce Co

I
I

z J
z1 J

z1 J(Ce Co )
z1 J(Ce Co )



I
I

I
I



Ce
Co

(86)

The last equality above suggests the structure of Fig. 32 for

the implementation of the LOT filter bank. This structure
consists of the implementation of the polyphase components
of the prototype filter using a DCT-based matrix. It is also
included in the figure an orthogonal matrix L1 whose choice
is discussed next. The inclusion of this matrix generalizes the
choice of the filter bank and keeps the perfect reconstruction
conditions. The polyphase matrix is then given by
1
E(z) = L1
2

I
I

z1 J
z1 J



I
I

I
I



Ce
Co

(87)

The basic construction of the LOT presented above is

equivalent to the one proposed by Malvar (see Ref. 8), who
utilizes a block transform formulation to generate lapped

Figure 32. Lapped orthogonal transform.

transforms. This formulation differs somewhat from the one

in Eqs. (7687). He starts with an orthogonal matrix based
on the DCT having the following form:

(84)

where the matrices Ce and Co are M/2 by M matrices consisting of the even and odd DCT basis of length M, respectively. The reader can easily verify that the above choice satisfies the relations (82) and (83). With this we can build an
initial LOT whose polyphase matrix is given by

E(z) =

HM + 2 (z)
2

1/2

A simple construction for the matrices above based on the

DCT is choosing
1
2

(z)

.
.
.

M1 M1

C1
=

L1

M
2

HM + 2 (z)
2

.
.
.

z1

.
.
.

1
2

Ce Co
Ce Co

J(Ce Co )
J(Ce Co )


(88)

This choice is not at random. First, it satisfies the conditions

of Eqs. (82) and (83). Also, the first half of the basis functions
are symmetric whereas the second half is antisymmetric, thus
keeping the phase linear. The choice of DCT basis is the key
to generate a fast implementation algorithm. Starting with
L0 we can generate a family of more selective analysis filters
in the following form
Llot = L1 L0

(89)

where the matrix L1 should be orthogonal and also be amenable to fast implementation. The most widely used form for
this matrix is

L1 =

I
0

0
L2


(90)

where L2 is a square matrix of dimension M/2 consisting of a

set of plane rotations whose angles are submitted to optimization aiming at maximizing the coding gain when using the
filter bank in subband coders, or improving the selectivity of
the analysis and synthesis filters (8).
Figure 33 depicts the frequency response of the analysis
filters of an LOT with eight subbands.
Fast Algorithms. We now present a general construction of
a fast algorithm for the LOT. Start by defining two matrices

266

TIME-VARYING FILTERS

expansions, compressions, and translations of a single mother

function (t), called wavelet.
Its applications range from quantum physics to signal coding. It can be shown that for digital signals, the wavelet
transform is a special case of critically decimated filter banks
(11). In fact, its numerical implementation relies heavily on
that. In what follows, we will give a brief introduction to
wavelet transforms, emphasizing its relation to filter banks.
Indeed it is quite easy to find in the literature good material
analyzing wavelet transforms from different points of view.
For example, Ref. 10 is a very good book on the subject, written by a mathematician. For people with a signal processing
background, Ref. 4 is very useful. The text in Ref. 12 is excellent and very clear, at a more introductory level.

0
10

dB

20
30
40
50
60

0.5

1.5
Freq

2.5

Figure 33. Frequency response of the analysis filters of an LOTbased filter bank with eight sub-bands.

as follows
C
3 = C
1C
T
1

(91)

C
4

(92)

C
1

+ C
2

By premultiplying both terms in Eq. (82) separately by C1 and

by C2, and using the results in Eq. (83), one can show that
C
1 = C
3C
4

(93)

C
2 = {I C
3 }C
4

(94)

With the above relations it is straightforward to show that

the polyphase components of the analysis filter can be written
as
E(z) = {C
3 + z1 [I C
3 ]}C
4

(95)

The previously discussed initial solution for the LOT matrix can be analyzed in the light of this general formulation.
After a few manipulations the matrices of the polyphase description above corresponding to the LOT matrix of Eq. (88)
are given by
C
3

1
=
2

C
4

1
=
2

CeCeT + CoCoT
CeCeT + CoCoT

Ce Co
Ce Co

CeCeT + CoCoT
CeCeT + CoCoT

(96)

J(Ce Co )
J(Ce Co )

(97)

Hierarchical Filter Banks

The cascade of 2-band filter banks can produce many different
kinds of critically decimated decompositions. For example,
one can make a 2k-band uniform decomposition as depicted in
Fig. 34(a) for k 3. Another common type of hierarchical decomposition is the octave-band decomposition, in which only
the low-pass band is further decomposed. In Fig. 34(b), one
can see a 3-stage octave-band decomposition. The synthesis
filter banks are not drawn because they are entirely analogous.
Octave-Band Filter Banks and Wavelet Transforms
Wavelets. Consider the octave-band analysis and synthesis
filter bank in Fig. 35, where the low-pass bands are recursively decomposed into low- and high-pass channels. The outputs of the low-pass channels after an S 1 stages decomposition are xS,n and the outputs of the high-pass channels are
cS,n, S 1.
Applying the noble identities to Fig. 35 we arrive at Fig.
36. After S 1 stages and before decimation by a factor of
2S1, the Z transforms of the analysis low- and high-pass
(S)
(S)
channels, Hlow
(z) and Hhigh
(z), respectively, are
S

XS (z)
k
=
H0 (z2 )
X (z)
k=0

(98)

CS (x)
s
(S1)
= H1 (z2 )H low
(z)
X (z)

(99)

(S)
H low
(z) =

(S)
H high
(z) =

The synthesis channels are analogous to the analysis ones,

i.e.,
(S)
G low
(z) =

S


G0 (z2 )

(100)

k=0

The substitution of these equations back in Eq. (95) clarifies

the relation between the algebraic formulations and the actual structure that implements the algorithm.
WAVELET TRANSFORMS
Wavelet transforms are a relatively recent development from
functional analysis and have attracted great attention in the
signal processing community (10). The wavelet transform of a
function belonging to L 2, the space of the square integrable functions, is its decomposition in a base composed by

(S)
(S1)
G high
(z) = G1 (z2 )H low
(z)

(101)

If H0(z) has enough zeros at z 1, it can be shown (4,12)

that the envelope of the impulse response of the filters from
Eq. (99) has the same shape for S 0, 1, 2, . . . In other
words, this envelope can be represented by expansions and
contractions of a single function (t) (see Fig. 37 for the analysis filter bank).
In Fig. 37, the envelopes before and after the decimators
are the same. However, it must be noted that after decimation
we cannot anymore refer to impulse responses in the usual

TIME-VARYING FILTERS

x0

(n)

H1 (z)

x1

(n)

H0 (z)

x2

(n)

H1 (z)

x3

(n)

H0 (z)

x4

(n)

H1 (z)

x5

(n)

H0 (z)

x6

(n)

H1 (z)

x7

(n)

H0 (z)

x0

(n)

H1 (z)

x1

(n)

x2

(n)

x3

(n)

H1 (z)

x(n)

H0 (z)

H1 (z)

H0 (z)

H0 (z)

H0 (z)

267

H1 (z)

(a)

H0 (z)
H0 (z)

x(n)

H1 (z)

H1 (z)

Figure 34. Hierarchical decompositions: (a)

8-band uniform; (b) 3-stage octave-band.

(b)

way, because the decimation operation is not shift invariant

(see the subsection entitled Decimation).
If s is the sampling rate at the input of the system in Fig.
37, we have that this system has the same output as the one
from Fig. 38, where the boxes mean continuous-time filters
with impulse responses equal to the envelopes of Fig. 37. Note
that in this case, sampling with frequency s /k is equivalent
to subsampling by k.
As stated above, the impulse responses of the continuoustime filters of Fig. 38 are expansions and contractions of a
single mother function (t). In Fig. 38, the highest sampling
frequency was s /2. Each channel added to the right had an
impulse response with double the width and sampling rate
half of the previous one. There is no impediment in also adding channels to the left of the channel with sampling frequency s /2. Each new channel added to the left would have

an impulse response with half the width and double the sampling rate of the previous one. If we keep adding channels to
both the right and the left indefinitely, we arrive at Fig. 39.
If a continuous-time signal is input to the system of Fig. 39
its output is referred to as the wavelet transform of x(t), and
the mother function (t) is called the wavelet, or, more specifically, the analysis wavelet (13).
Assuming, without loss of generality, that s 2 (Ts 1),
it is straightforward to derive from Fig. 39 that the wavelet
transform of a signal x(t) is (actually, in this formula, the impulse response of the filters are expansions and contractions
of (t))


cm,n =

2 2 (2mt n)x(t) dt

(102)

268

TIME-VARYING FILTERS

x(n)

H0(z)

x0,n
2

H1(z)

2
C0,n
2

G1(z)

H0(z)

x1,n

H1(z)

H1(z)

...

...

C1,n

C2,n

...

...

x(n)
G0(z)

22

x0,n

G0(z)

x1,n

G0(z)

x2,n

Figure 35. Octave-band analysis and synthesis filter bank.

The constant 2m/2 is included because, if (t) has unity energy, 2m/2(2mt n) has also unity energy, which can be assumed without loss of generality.
From Figs. 36 and 39 and Eq. (99), one can see that the
wavelet (t) is band-pass, because each channel is a cascade
of several low-pass filters and a high-pass filter. When the
wavelet is expanded by 2, its bandwidth is decreased by 2, as
seen in Fig. 40. Therefore, the decomposition in Fig. 39 and
Eq. (102) is, in the frequency domain, as in Fig. 41.
In a similar manner, the envelopes of the impulse responses of the equivalent synthesis filters after interpolation
[see Fig. 36 and Eq. (101)] are expansions and contractions of

x(n)

H0(z)

H0(z2)

x1,n

H0(z4)

H1(z)

H1(z2)

H1(z4)

...

...

C1,n

C2,n

G1 (z)

G1 (z2)

C0,n

x(n)

x0,n

G0 (z)

x0,n

G1 (z4)

G0 (z2)

x1,n

H0(z2)

H0(z)

H0(z4)

H1(z)

H1(z2)

H1(z4)

...

...

...

G1(z)

G1(z)

x2,n

H0(z)

x2,n

Figure 37. The impulse response of the filters from Eq. (102) has
the same shape for every S.

a single parent function (t). Using a similar reasoning to the

one leading to Figs. 3739, one can obtain the continuoustime signal x(t) from the wavelet coefficients cm,n [Eq. (102)]
(4):
x(t) =

cm,n 2 2 (2mt n)

(103)

m= n=

Equations (102) and (103) are the direct and inverse wavelet transforms of a continuous-time signal x(t). The wavelet
transform of the corresponding discrete-time signal x(n) is
merely the octave-band decomposition in Figs. 35 and 36. A
natural question to ask at this point is: How are the continuous-time signal x(t) and the discrete-time signal x(n) related
if they generate the same wavelet coefficients? In addition,
how can the analysis and synthesis wavelets be derived from
the filter bank coefficients and vice and versa? In order to
answer these questions we need the concept of a scaling
function.

(t)

...

...

s
2

...

s
4

s
8

...

...

G0 (z4)

x2,n

Figure 36. Octave-band analysis and synthesis filter bank after the
application of the noble identities.

Figure 38. This system has the same outputs as the system from
Fig. 37.

TIME-VARYING FILTERS

...

...

...

...

...

s
2

s
4

s
8

...

...

C0,n

C1,n

C2,n

...

Scaling Functions. By looking at Eqs. (102) and (103) we see

that the values of m which are associated with the width of
the filters (Fig. 39) range from to . Since all signals
encountered in practice are somehow band limited, one can
assume generally that the output of the filters with impulse
responses (2mt) are zero for m 0. Therefore, m now varies
from 0 to . Looking at Figs. 3537, we see that m
means the low-pass channels will be indefinitely decomposed.
However, in practice, the number of stages of decomposition
is fixed, and after S stages we have S band-pass channels and
one low-pass channel. Therefore, if we restrict the number of
stages of decomposition in Figs. 3539 and add a low-pass
channel, we can modify Eq. (103) such that m assumes only
a finite number of values.
In order to do this, we notice that if H0(z) has enough zeros
at z 1, the envelopes of the analysis low-pass channels
[Eq. (98)] are also expansions and contractions of a single
function (t), which is called analysis scaling function. Likewise, the envelopes of the synthesis low-pass channels are
expansions and contractions of the synthesis scaling function
(t) (4). Therefore, if we make an S 1 stage decomposition,
Eq. (103) becomes:

x(t) =

S1


xS,n 2

(2

t n)

(104)
m

cm,n 2 2 (2mt n)

m=0 n=

(t)

( )

0
(t/2)

Figure 39. Wavelet transform of a continuous signal x(t).

where


xS,n =

2 2 (2St n)x(t) dt

(105)

Therefore, the wavelet transform is in practice given by

Eq. (105). The summations in n will in general depend on the
supports (those regions where the functions are nonzero) of
the signal, wavelets, and scaling functions (13).
Relation Between x(t) and x(n)<. Equation (105) shows how
to compute the coefficients of the low-pass channel after an
S 1 stages wavelet transform. In Fig. 35, xS,n are the outputs of a low-pass filter H0(z) after S 1 stages. Since in Fig.
36 the discrete-time signal x(n) can be regarded as the output
of a low-pass filter after zero stages, we can say that x(n)
would be equal to x1,n. In other words, the equivalence of the
outputs of the octave-band filter bank of Fig. 35 and the wavelet transform given by Eqs. (102) and (103) occurs only if the
digital signal input to the filter bank of Fig. 35 is equal to
x1,n. From Eq. (105) this means:


x(n) =
2(2t n)x(t) dt
(106)

2s

n=

( )

(2 )

Equation (106) can be interpreted as x(n) being the signal

x(t) digitized with the band-limiting filter having as impulse
response 2(2t).
Therefore, a possible way to compute the wavelet transform of a continuous-time signal x(t) is as depicted in Fig. 42.
x(t) is passed through a filter having as impulse response the
scaling function contracted by 2 in time and sampled with
Ts 1 (s 2), the resulting digital signal being input to
the octave-band filter bank in Fig. 35 with the filter coefficients given by Eqs. (107) and (109). At this point, it is important to note that, strictly speaking, the wavelet transform is

( )

0/2
( /2)
(2t)

269

20

( )

Figure 40. Expansions and contractions of the wavelet in the time

and frequency domains.

0/4

0/2

( )

Figure 41. Wavelet transform in the frequency domain.

270

TIME-VARYING FILTERS

c0,n
c1,n
x(t)

2 (2t)

s = 2

x(n)

Octave
band
filter
bank

c2,n
.
.
.
cs,n
as,n

a wavelet transform is not necessarily defined for every twoband perfect reconstruction filter bank. There are cases in
which the envelope of the impulse responses of the equivalent
filters of Eqs. (98)(101) is not the same for every S (4).
The regularity of a wavelet or scaling function is roughly
the number of continuous derivatives that a wavelet has. It
is somehow a measure of the extent of convergence of the
products in Eqs. (111)(114). In order to define regularity
more formally, we first need the following concept (15):
A function f(t) is Lipschitz of order , 0 1 if, x, h
,

Figure 42. Practical way to compute the wavelet transform of a continuous-time signal.

| f (x + h) f (x)| ch

only defined for continuous-time signals. However, it is common practice to refer to the wavelet transform of a discretetime signal x(n) as the output of the filter bank in Fig. 35 (4).

where c is a constant.
Using this definition, we have that the Holder regularity of
a scaling function (t) is r N , where N is integer and 0
1, if (15):

Relation between the Wavelets and the Filter Coefficients. If

h0(n), h1(n), g0(n) and g1(n) are the impulse responses of the
analysis low- and high-pass filters and synthesis low- and
high-pass filters, respectively, and (t), (t), (t) and (t) are
the analysis and synthesis scaling functions and analysis and
synthesis wavelets, respectively, we have (11):


h0n =


g0n =


h1n =


g1n =

(t) 2(2t + n) dt

d N (t)
is Lipschitz of order
dt N

(108)

(t) 2(2t + n) dt

(109)

(t) 2(2t n) dt

(110)

H
0 (z) =

() =

1 + z1 
2

H0 (z)

then (t) generated by H0(z) will have regularity r 1 (15).

The regularity of a wavelet is the same as the regularity
of the corresponding scaling function (15).
It can be shown that the regularity of a wavelet imposes
the following a priori constraints on the filter banks (4):

H0 (1) = G0 (1) = 2
(117)
H0 (1) = G0 (1) = 0

And, considering their Fourier transforms (4),

() =


1
w
H0 (e j 2 n )
2
n=1

(111)


1
w
G0 (e j 2 n )
2
n=1

(112)

1
w  1
w

() = H1 (e j 2 )
H0 (e j 2 n )
2
2
n=2

(113)

1
w  1
w

() = G1 (e j 2 )
G0 (e j 2 n )
2
2
n=2

(114)

When (t) (t) and (t) (t), the wavelet transform is

orthogonal (13). Otherwise, it is only biorthogonal (14). It is
important to notice that, for the wavelet transform to be defined, the corresponding filter bank must provide perfect reconstruction.
Regularity
From Eqs. (111)(114) one can see that the wavelets and scaling functions are derived from the filter bank coefficients by
infinite products. Therefore, in order for a wavelet to be defined, these infinite products must converge. In other words,

(116)

It can be shown that, in order that a scaling function (t)

be regular, H0(z) must have enough zeros at z 1. In addition, supposing that (t) generated by H0(z) [Eq. (111)] has
regularity r, if we take

(107)

(t) 2(2t n) dt

(115)

(118)

Equation (117) implies that the filters H0(z), H1(z), G0(z)

and G1(z) have to be normalized in order to generate a wavelet transform.
It is interesting to note that when deriving the wavelet
transform from the octave-band filter bank in the subsection
Wavelets, it was supposed that the low-pass filters had
enough zeros at z 1. In fact, what was meant there was
that the wavelets should be regular.
In Fig. 43 we can see examples of wavelets with different
regularities.
Examples
Every two-band perfect reconstruction filter bank with H0(z)
having enough zeros at z 1 has corresponding analysis
and synthesis wavelets and scaling functions. For example,
the filter bank described by Eqs. (20)(23), normalized such
that Eq. (117) is satisfied, generates the so-called Haar wavelet. It is the only orthogonal wavelet that has linear phase (4).
The scaling function and wavelets are shown in Fig. 44.
The wavelets and scaling functions corresponding to the
filter bank described by Eqs. (38)(41) are depicted in Fig. 45.
A good example of orthogonal wavelet is the Daubechies
wavelet, whose filters have length 4. They are also an exam-

TIME-VARYING FILTERS

2 1.5

1 0.5

0.5

1.5

1.5

0.5

(a)

3 2

0.5

271

1.5

(b)

5 4 3 2 1

(c)

(d)

Figure 43. Examples of wavelets with different regularities. (a) Regularity 1. (b) Regularity 0. (c) Regularity 1. (d) Regularity 2.

ple of CQF filter banks (see the section entitled CQF filter
banks). The filters are (13)
H0 (z) = + 0.4829629 + 0.8365163z1
+ 0.2241439z2 0.1294095z3
H1 (z) = 0.1294095 0.2241439z

APPENDIX A

+ 0.8365163z2 0.4829629z3
G0 (z) = 0.1294095 + 0.2241439z1
+ 0.8365163z2 + 0.4829629z3
G1 (z) = 0.4829629 + 0.8365163z

(119)

It is important to notice that, unlike the biorthogonal

wavelets in Fig. 45, these orthogonal wavelets are nonsymmetrical, and, therefore, do not have linear phase.

(120)

Here we prove Eq. (5), which gives the spectrum of the decimated signal xd(n) as a function of the spectrum of the original signal x(m). We have that

(121)

xd (n) = x(nM)

(123)

0.2241439z2 0.1294095z3

(122)

Since the wavelet transform is orthogonal, the analysis

and synthesis scaling functions and wavelets are the same.
The scaling function and wavelet are depicted in Fig. 46.

Defining x(m) as



x (m) =

x(m), m = nM, n Z
0,

(124)

otherwise

x(m) can also be expressed as:

x
(m) = x(m)

(m lM)

(125)

l=

The Fourier transform of xd(n), Xd(ej) is then:

0.5

+ 0.5

Scaling function

0.5

+ 0.5

Wavelet

Figure 44. Haar wavelet and scaling function.

Xd (e j ) =
=


n=


n=

xd (n)e jn =

x(nM)e jn

n=

x
(nM)e jn =

x
(M)e j M = X
(e j M )

(126)

272

TIME-VARYING FILTERS

2 1.5 1 0.5

0.5

1.5

1.5

0.5

(a)

Figure 45. Wavelet transform generated by

the filter bank from Eqs. (38)(40). (a) Analysis scaling function. (b) Analysis wavelet. (c)
Synthesis scaling function. (d) Synthesis
wavelet.

0.5

0.5

2 1.5 1 0.5

(c)

0
(b)

0.5

0.5

1.5

1.5

(d)

But from Eq. (125),

X (e

1
X (e j ) F
)=
2


(m lM)

l=




2 M1
2k
1
X (e j )

2
M k=0
M



1 M1
2 k
X [e M ]
M k=0

(127)

Then, from Eq. (126),

2 1.5 1 0.5

0.5

1.5

(a)

Xd (e j ) = X
(e j M ) =



1 M1
2 k
X [e M ]
M k=0

(128)

which is the same as Eq. (5).

APPENDIX B
In order to prove the identity in Fig. 17(a), one has to first
rewrite Eq. (5), which gives the Fourier transform of the decimated signal xd(n) as a function of the input signal x(m), in
terms of Z transforms:

Xd (z) =
2 1.5 1 0.5

0.5


1 M1
1
2 k
X (z M e M )
M k=0

(129)

1.5

(b)
Figure 46. Wavelet and scaling function corresponding to the filter
bank from Eqs. (122)(125). (a) Scaling function. (b) Wavelet.

For the decimator followed by filter H(z), we have that:

Y (z) = H(z)Xd (z) =

M1

1
1
2 k
H(z)
X (z M e M )
M
k=0

(130)

For the filter H(zM) followed by the decimator, if U(z)

X(z)H(zM) we have, from Eq. (129):

E0 (z2 )

C2T C2 = 2M[I (1)L1J]

(133)

C1T C2 = C2T C1 = 0

(134)

E T (z1 )E(z)
E0 (z2 )

0
E1 (z

)
..

EM (z

EM+1 (z2 )
..

E0 (z2 )

0
E1 (z

.C1

.
EM1 (z2 )

0
EM (z2 )

0
EM+1 (z2 )

EM (z

..

E2M1 (z2 )

0
2

0
EM+1 (z2 )
..
0

E T (z1 )E(z)

E0 (z2 )

= 2M

E0 (z

0
E1 (z

)
..

EM1 (z2 )
0

E1 (z2 )
..

EM (z2 )

0
EM+1 (z2 )
..

E2M1 (z2 )

0
EM (z2 )

EM1 (z2 )

.
E2M1 (z2 )

EM+1 (z2 )

This result allows some simplification in Eq. (135) after we

replace Eqs. (132) and (133). The final result is

0
EM+1 (z2 )
..
0

C2T

0
..

E2M1 (z2 )

)
..

(136)

.J

EM1 (z2 )

EM1 (z2 )

C T1

0
2

EM (z2 )

(132)

..

where I is the identity matrix, J is the reverse identity matrix, and 0 is a matrix with all elements equal to zero. All
these matrices are square with order M. With this result it
straightforward to show that

.C2

273

EM1 (z2 )
E1 (z

Before we prove the desired result, we need properties related

to the modulation matrix that are required in the proof. These
results are widely discussed in the literature, see for example
Ref. 5. The results are

.J

C1T C1 = 2M[I + (1)L1J]

E0 (z

APPENDIX C

..

(131)

This is the same as Eq. (130), and the identity is proved.

The identity in Fig. 17(b) is straightforward. H(z) followed
by an interpolator gives Y(z) H(zM)X(zM), which is the expression for an interpolator followed by H(zM).

0
E1 (z2 )



1 M1
1 M1
1
2 k
1
2 k
2 M k
Y (z) =
U (z M e M ) =
X (z M e M )H(ze M )
M k=0
M k=0

1 M1
1
2 k
=
X (z M e M )H(z)
M k=0

TIME-VARYING FILTERS

E2M1 (z2 )
(137)

If the matrix above is equal to the identity matrix, we achieve

perfect reconstruction. The result above is equivalent to require that polyphase components of the prototype filter are
pairwise power complementary which is exactly the result of
Eq. (75).

E2M1 (z2 )
(135)

Since the prototype is a linear phase filter, after a few manipulations it can be shown that

BIBLIOGRAPHY
1. A. V. Oppenheim and R. W. Schaffer, Discrete-Time Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1989.

274

TOKEN RING NETWORKS

2. R. E. Crochiere and L. R. Rabiner, Multirate Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1983.
3. Y.-C. Lim, Frequency-response masking approach for the synthesis of sharp linear phase digital filters, IEEE Trans. Circuits Syst.,
33: 357364, 1986.
4. M. Vetterli and J. Kovacevic, Wavelets and Subband Coding, Englewood Cliffs, NJ: Prentice-Hall, 1995.
5. P. P. Vaidyanathan, Multirate Systems and Filter Banks, Englewood Cliffs, NJ: Prentice-Hall, 1993.
6. A. Croisier, D. Esteban, and C. Galand, Perfect channel splitting
by use of interpolation/decimation/tree decomposition techniques, Int. Symp. on Info., Circuits and Syst., Patras, Greece,
1976.
7. M. J. T. Smith and T. P. Barnwell, Exact reconstruction techniques for tree-structured subband coders, IEEE Trans. Acoust.,
Speech Signal Process., 34: 434441, 1986.
8. H. S. Malvar, Signal Processing with Lapped Transforms, Norwood, MA: Artech House, 1992.
9. R. L. de Queiroz, T. Nguyen, and K. R. Rao, The GenLOT: generalized linear-phase lapped orthogonal transform, IEEE Trans.
Signal Process., 44: 497507, 1996.
10. I. Daubechies, Ten Lectures on Wavelets, Philadelphia, PA: Soc.
Ind. Appl. Math., 1991.
11. M. Vetterli and C. Herley, Wavelets and filters banks: theory and
design, IEEE Trans. Signal Process., 40: 22072232, 1992.
12. G. Strang and T. Nguyen, Wavelets and Filter Banks, Wellesley,
MA: Wellesley Cambridge Press, 1996.
13. I. Daubechies, Orthonormal bases of compactly supported wavelets, Commun. on Pure and Appl. Mathematics, XLI: 909996,
1988.
14. A. Cohen, I. Daubechies, and J.-C. Feauveau, Biorthogonal bases
of compactly supported wavelets, Commun. on Pure and Appl.
Math., XLV: 485560, 1992.
15. O. Rioul, Simple regularity criteria for subdivision schemes,
SIAM J. Math. Anal., 23: 15441576, November 1992.
16. R. David Koilpillai and P. P. Vaidyanathan, Cosine-modulated
FIR filter banks satisfying perfect reconstruction, IEEE Trans.
Signal Process., 40: 770783, 1992.
17. N. J. Fliege, Multirate Dig. Signal Process., Chichester, UK: Wiley, 1994.
18. T. Nguyen and R. David Koilpillai, The theory and design of arbitrary-length cosine-modulated FIR filter banks and wavelets, satisfying perfect reconstruction, IEEE Trans. Signal Process., 44:
473483, 1996.

EDUARDO A. B. dA SILVA
PAULO S. R. DINIZ
Program of Electrical Eng. and
Electronics Dept.
COPPE/EE/Federal University of
Rio de Janeiro

TIMING ANALYSIS. See CRITICAL PATH ANALYSIS.

TOKEN RING. See LOCAL AREA NETWORKS (LANS).

TUNNEL DIODE CIRCUITS

TUNNEL DIODE OSCILLATORS. SEE TUNNEL DIODE CIRCUITS. TUNNEL DIODE AMPLIFIERS. SEE TUNNEL DIODE
CIRCUITS.

Tunnel diodes are important two-terminal pn junction devices, since they give a negative incremental resistance.
This characteristic is obtained by tunneling due to a very
high doping level and allows them to be used for such
things as amplication, creation of oscillations, modulation
and demodulation, logic, and memory. They were rst introduced in the 1958 paper of Leo Esaki (1) and consequently
are often called Esaki diodes. The circuit symbol is shown
in Fig. 1(a), and a typical dc current-versus-voltage curve
in Fig. 1(b), where the local peak and valley values are indicated. In Fig. 1(b) the initial (positive) slope near the origin
is due to the tunneling, and the positive slope further out
is due to the normal diode action of a pn junction diode.
The transition between these two regions is seen to give a
negative slope and is the reason for the utility of the tunnel
diode.
MODELS AND EQUIVALENT CIRCUITS
Theoretical models for the tunnel-diode i(v) characteristics
give the general shape, but the values are somewhat off (2,
p. 44; 3, p. 47). Consequently, it is more useful in circuit
designs to use curve-tted models. A meaningful one is the
piecewise linear model (4, p. 1049)

where Vp is the peak voltage, Vv is the valley voltage, and

the vector of coefcient constants P = [P0 ,P1 ,P2 ,P3 ]T , (using
T
for transpose) can be found by choosing i,v pairs at four
independent points and solving the four resulting linear
equtions; good choices are at v = 0, Vp , Vv , 2Vv . Different
currents can be obtained by design of the junction area;
typical values are Vp = 50 mV (with Ip = 2 mA) and Vv = 200
mV (with Iv = 0.3 mA) (3, p. 49). If we set

then by assembling the currents at these points into the

vector I of currents

we have

Figure 1. Tunnel diode: (a) symbol; (b) typical dc characteristic;

(c) piecewise approximation to characteristic.

Figure 1c shows the curve obtained from Eq. (1) for (Vp ,
Ip ) = (0.05 V, 2 mA), (Vv , Iv ) = (0.2 V, 0.3 mA), and (2Vv ,
I2v ) = (0.4 V, 2 mA), giving P = [0.0007, 0.024, 0.026,
0.009917]T . In actual fact a better curve t is found by replacing Ip with 1.1Ip and Iv with 0.9Iv .
When used in small-signal ampliers, the diode is normally biased to operate in the middle of the negative-

resistance region (at the inection point). There the smallsignal equivalent circuit is as shown in Fig. 2 (5, p. 310),
where the main element of interest is the negative conductance, g, the other elements being parasitics, which
generally limit the frequency response. Cj is the junction

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Tunnel Diode oscillators. See TUNNEL DIODE CIRCUITS. Tunnel Diode ampliers. See TUNNEL DIODE CIRCUITS.

Figure 2. Equivalent circuit.

capacitance at the bias point, this being given by (3, p. 67)

where Cjv is the capacitance at the valley and Vj is the

internal junction voltage at Vbias . Typical values of Cjv are
in the range of 0.1 pF to 10 pF. Rs and Ls are the lead
resistance and inductance, normally on the order of 1

and 100 pH.
As can be seen from Fig. 1(b), when the peak current is made larger (by a using bigger junction area), the
diode negative resistance decreases (diode conductance g
increases), since the peak and valley voltages Vp and Vv
are xed. Thus, increasing the power-handling capability
of a tunnel diode, by designing for larger peak currents,
normally decreases the efciency of conversion of bias into
signal power.
OSCILLATOR
The negative resistance region of the tunnel diode can be
used in the design of several circuits such as oscillators
and pulse generators. In this section, applications to pulse
and sinusoidal oscillators are introduced. First we give the
basic circuit and set up the differential equation that illustrates the concepts. Consider Fig. 3, where the voltage source E biases the tunnel diode into the negativeresistance region. The inductor and capacitor are set to
give the fundamental frequency of oscillation, 0 , and the
signal is generated across the load resistor RL . In order
for the circuit to oscillate, the negative conductance should
be larger than the load conductance GL = 1/RL . Since the
tunnel-diode curve has positive slope for signals outside
the negative-resistance region, the oscillations become limited by the range of voltage from Vv to Vp , in which case the
circuit is really a relaxation oscillator. Assuming the inductor and capacitor are without loss, the describing state
equations for Fig. 3 are

Differentiating the second equation and substituting into it

the rst, setting x = v E and F(x) = df(v)d/v with v replaced
by x + E, and noting that dx/dt = dv/dt, we get the Van der
Pol equation

Figure 3. Tunnel-diode oscillator.

Here the undamped natural frequency, that obtained when

F(x) = GL , is 0 2 = 1/LC. But because F(x) is nonlinear and
both positive and negative, the actual frequency is only
approximately 0 and is difcult to obtain analytically, so
it is best found from simulations.
When F(x) + GL is negative (in the negative-resistance
region of the tunnel diode), this system is a relaxation oscillator and exhibits a unique limit cycle. When F(x) + GL
is only slightly negative, the response is very close to a
sinusoidal one, since the limit cycle is bounded to almost
within the negative-resistance portion of F(x) + GL . But
if GL is small (that is, the load resistance is large), then
the limit cycle covers a much larger portion of the positiveresistance portion of F(x) + GL , in which case the output becomes more pulselike. Thus, by adjusting the parallel resistance one can produce different classes of oscillations with
this tunnel-diode oscillator. The situation is illustrated by
the time-domain curves of Fig. 4 for the tunnel diode using the approximation of Fig. 2 with C = 1 nF, L = 10 H,
and E = (Vp + Vv )/2 = 1.25 V. In Fig. 4 are shown inductor
currents and capacitor voltages for two values of the load
resistor. In the case where the positive load resistor (here
85
) almost cancels the negative resistance (84
) of
the tunnel diode, designated by subscripts 1, we obtain a
sinusoidal output voltage, while when the load resistor is
very large (100 M
), designated by subscripts 2, the output voltage is more pulselike. The limit cycles and effective
conductances (tunnel diode in parallel with RL ) seen by the
LC circuit are shown in Fig. 5(a), for the 85
, and (b), for
the 100 M
, cases. As seen from Fig. 5(a), the sinusoidal
case results when the load resistance is effectively canceled
by the tunnel-diode negative resistance.
Other circuits and results can be found in Ref. 6, pp.
810811.
AMPLIFIERS
Because the negative incremental resistance can be used
to cancel losses in a circuit, the tunnel diode can be used to
achieve gain. In practice such tunnel-diode ampliers are
used at microwave frequencies, where there are two main
classes of ampliers designed with tunnel diodes: transmission and reection ampliers. Figure 6 shows the basic
congurations for both types, where a Norton equivalent
input source is shown for convenience in treating previous
transistorized stages. Since these are small-signal ampliers, the equivalent circuit of Fig. 2 replaces the tunnel
diode, for most designs the series resistance and inductance are assumed negligible. Various alternative cong-

Tunnel Diode oscillators. See TUNNEL DIODE CIRCUITS. Tunnel Diode ampliers. See TUNNEL DIODE CIRCUITS.

and, using 12 for the 22 identity matrix,

The lossless condition is important for the design and physically means that the total input power is zero in the sinusoidal steady state; this is expressed (7, p. 122) in terms of
S as

where the lower asterisk denotes matrix transposition

along with complex conjugation (s replaced by its negative
and complex conjugated; for circuits with real elements this
means transpose and replace s by s). Loading a 2-port
with a 1-port scattering variable (reection coefcient) SL
gives the input reection coefcient in terms of the 2-port
S as

In the case of a tunnel diode load of resistance Rtd , as in

Fig. 6, then

where is the reection coefcient of a positive resistor of

value Rtd . Substituting Eq. (13) into (10a,b), and using Eq.
(11), for which the determinants satisfy det(S) = 1/det(S ),
yields the input reection coefcient
Figure 4. Oscillations of the oscillator.

urations are shown in Fig. 7, which includes two other

types of transmission ampliers and one other reection
one. In both Figs. 6 and 7 the designated 2-ports are taken
to be lossless, in which case the tunnel-diode parasitic capacitance, which is a lossless component, is absorbed in
them during design. And since microwave frequencies are
most often involved, the circuit descriptions are most conveniently expressed through scattering matrices. Consequently, before discussing the ampliers further, we review
a bit of the necessary scattering theory.
Consider the 2-port of Fig. 8, where we dene 2-vectors
of port currents i and voltages v. Using s for the complex
frequency variable, these are used to dene the 2 2 scattering matrix S(s) through the incident (vi ), and reected,
(vr ), scattering variables, with respect to the positive reference port resistances R1 and R2 , which form the diagonal
matrix R = diag[R1 , R2 ], by

Since the designs are actually based on the input

impedance, we note that, for v = Zi,

Equation (15) says that to synthesize the 2-port with a negative resistance (tunnel diode) for the load we synthesize
1/Si (s) with a positive load resistor equal in magnitude
to that of the negative resistance and then turn the 2-port
around and load it with the tunnel diode to get the desired
Si (s).
Tunnel-diode ampliers are primarily designed through
specication of the transducer power gain G() in the sinusoidal steady state, s = j, this being dened as

since |Is |2 /(4Gs ) is the power available from the source, and
the power into the load is GL |V0 |2 for the circuit of Fig. 6,
while v1 i = Is /Gs as in Eq. (4) if R1 = Rs is chosen.
Considering rst the transmission amplier, the results
depend upon the size of the load resistor versus the tunnel diode resistance. Usually GL > Gtd for load stability,
so assume that R2 = 1/(GL Gtd ) > 0. Since R2 I2 = V2 we
have Vo = v2 r and v2 i = 0, as seen from Eq. (8a,b), giving
Vo /v1 i = v2 r /v1 i = s21 . For the reection amplier, the 3-port
circulator is described by the following 3 3 scattering matrix, where we choose as its reference matrix R = diag[Rs ,

Tunnel Diode oscillators. See TUNNEL DIODE CIRCUITS. Tunnel Diode ampliers. See TUNNEL DIODE CIRCUITS.

Figure 5. Limit cycles and effective conductances:

(a) RL = 85
; (b) RL = 100 M
.

R1 , RL ]:

the last by Eq. (14). Summarizing,

in which case Vo = v3circ r = v2circ i = v1,2port r = Si,2port v1,2port i =

Si,2port v2circ r = Si,2port v1circ i ; we also have v1circ i = Rs Is /2.
For the 2-port, though, if we choose its reference
R2 = Rtd , then v2 r = 0 and hence s21 v1 i = s22 v2 i ,
from Eq. (1), from which v1 r = (s11 s12 s21 /s22 )v1 i = (det
S/s22 )v1 i = (1/s11 )v1i ; that is, Si,2port = 1/s11 , where s11 is
the (1,1) entry of the lossless 2-port scattering matrix
and Si,2port is the input reection coefcient seen at
port 1 when the tunnel diode is at port 2. We obtain
Vo /Is = (Rs /2)Si,2port (s) = (Rs /2)[1/s11 (s)] = (Rs /2)[1/Si,port (s)],

Since synthesis is based on s11 , in the case of the transmission amplier we convert to s11 via the (1,1) entry of
the lossless constraint: |s11 (j)|2 = 1 |s21 (j)|2 ; while for
the reectance amplier we use (s) = 1/s11 (s) as derived
above. Because the lossless 2-ports will be synthesized with
passive components, we require s11 (s), for the transmission amplier, and
(s) for the reection amplier, to
be bounded real. Since we desire the tunnel-diode capacitance to be extracted from the lossless 2-port, we place a
minus sign on the ratio of the highest powers of s in these
reection coefcients. Then the synthesis follows stan-

Tunnel Diode oscillators. See TUNNEL DIODE CIRCUITS. Tunnel Diode ampliers. See TUNNEL DIODE CIRCUITS.

Figure 8. 2-port for discussion of scattering theory.

MEMORY

Figure 6. Basic tunnel-diode ampliers: (a) transmission; (b) reection.

Figure 7. Alternative amplier types: (a,b) transmission; (c) reection.

dard circuit synthesis techniques for resistive terminated

lossless 2-ports; a number of references for this are in Ref.

2, pp. 204205.

A computer system or any digital processing system requires memory. Usually, within each system, there are
many different types of memory components. In the digitalcircuit and computer jargons the two acronyms RAM and
ROM is used to distinguish between two main classes of
memory. ROM is read-only memory, whereas RAM usually
refers to the kind of read and/or write memory that is called
random-access memory. Basically, there are two types of
MOS RAMs: static RAMs (SRAMs) and dynamic RAMs
(DRAMs). SRAMs use bistable circuits such as latches to
store binary data. On the other hand, DRAMs use capacitors to store binary data in the form of capacitor charges. Of
course, storing binary data on a capacitor requires much
less area than storing the same information on latches.
However, due to capacitor discharges over time (leakage
current), DRAMs require periodic refreshing to maintain
and/or regenerate their data. It should also be noted that
both dynamic and static RAMs are dependent on their dc
power supply voltages, and therefore, in the absence of
power supply, all stored data will be lost; hence RAM is
called volatile memory (8, p. 1113; 9, p. 573).
Tunneling-based SRAM (TSRAM), in its simplest form,
consists of a pass transistor and a pair of tunnel diodes.
The rst tunnel-diode SRAM was introduced by Goto et al.
(.10, pp. 2529], as shown in Fig. 9 (9, p. 578]. In Fig. 10, a
load-line graph illustrates the two stable points for VN (low)
and VN (high). As can be seen on the gure, these stable
points (voltages VN ) are close to the supply voltages 0 and
Vdd . A large restoring current will stabilize any perturbation about these two stationary points. Assume the stored
datum is zero, and therefore the TSRAM is at its left stable point. This point corresponds to the low (almost zero)
voltage VN . At this point the restoring current I1 is much
larger than its opposing current I2 . Therefore any deviation
from this stable point, I1 = I2 , will cause more restoring current (discharging current) than opposing current (charging
current) to ow through node N Therefore, the net current
through node N will be discharging and will reduce the
voltage at node N, VN , to its stable zero value. On the other
hand, assume a high bit is stored, which means VN is almost equal to Vdd . In this case too, any reduction in VN will
be opposed by the restoring current (charging current) I2 .
As can be seen in the Fig. 10, the restoring current I2 is
larger than its opposing current I1 . Therefore the net current, I2 I1 , will be a charging current, which will tend to
restore the voltage VN to it original value Vdd .

Tunnel Diode oscillators. See TUNNEL DIODE CIRCUITS. Tunnel Diode ampliers. See TUNNEL DIODE CIRCUITS.

Figure 9. Tunneling-based SRAM.

Figure 10. Operating principle of tunneling-based SRAM.

LOGIC-CIRCUIT APPLICATIONS
Introduction
The growth of technology demands larger, faster, and more
efcient integrated circuits (ICs) on a single chip. Engineers and scientists have answered this demand by continually scaling down the size of transistors in fabrication. As a result, the newer IC chips have more transistors, faster switching speed, and less power consumption
due to the size and supply voltage reduction. As this reduction in size continues, engineers are looking for alternative
approaches. New and preliminary applications of resonant
tunneling diodes in (RTDs) IC technology suggests that
this device can help electrical engineers to design faster
logic gates with fewer active devices (11,12). In addition
to high speed, logic circuits using RTDs have fewer active
elements and therefore are less complex in design and consume less power. Since the RTD is a latching structure, it
can replace traditional latching structures; this would further reduce the total number of gates in the design.
Logic Circuits
Recent developments in semiconductor technology, such as
molecular-beam epitaxy, have made it possible to integrate
RTDs with conventional semiconductor devices. Here, the
principle of operation of a logic circuit with RTDs and heterojunction bipolar transistors (HBTs) is discussed (11).
Figure 11 shows such a RTD + HBT bistable logic circuit
(11). There are m inputs IN1 ,. . . , INm , and one clock tran-

Figure 11. Schematic of the bistable RTD + HBT logic gate (11).

sistor CLK. All transistors, connected in parallel, are driving a single RTD load. Input transistors Q1 to Qm which
are either on or off depending on the gate voltage, yield
collector currents of Ih or zero respectively. The clock transistor will have two current states, Iclkh and Iclkq respectively for the high and quiescent conditions respectively.
A global reset state is when all collector inputs are zero.
Figure 12 shows the operation of this circuit. It shows the
RTD load curve and all possible collector currents. It shows
two groups of possible input currents, one for the quiescent clock transistor current (CLK Q), and the other for
the high clock transistor current (CLK H). In each of the
two groups, all possible total input-transistor collector currents are shown. Considering there are m input transistors, this means there are m levels of total transistor collector current one for each. When the clock transistor cur-

Figure 12. Operating principle of the bistable RTD + HBT

logic gate (11).

Tunnel Diode oscillators. See TUNNEL DIODE CIRCUITS. Tunnel Diode ampliers. See TUNNEL DIODE CIRCUITS.

rent is Iclkq , Fig. 12 shows that there are two stable states, a
low and a high, for any possible input combination. When
clock transistor current is Iclkh , Fig. 12 shows that there
is exactly one, low stable state for any n or more high inputs. In other words, there is exactly one stable operating
point when the RTD current is nIh + Iclkh or more. The operating sequence is as follows: First, reset the logic gate
by resetting all collector currents to zero; this will cause
the output to go high. Second, remove the reset signal and
set the clock to high. Then, if n or more inputs are high,
then the logic will go to low; otherwise it will be high.
Third, change the clock to its quiescent level. This will reduce the clock current while the output logic remains the
same.
Consider a three-input logic circuit. Now suppose n is 1.
The output f(x1 , x2 , x3 ) is low (logic zero) if and only if one or
more of the inputs x1 , x2 , x3 are high. This by denition is a
three-input NOR gate. Now assume n is 3. Then the output
f(x1 , x2 , x3 ) is low (logic zero) if and only if all three inputs
x1 , x2 , x3 are high. This by denition is a three-input NAND
gate. For n = 2, we obtain an inverted majority or inverted
carry function.
This design scheme can be easily extended to consider
weighted inputs. In such a case the output will be low if
w1 x1 + w2 x2 + . . . + wm xm > n. The circuit of Fig. 11 can be
used to implement the above weighted function when the
collector current of each transistor is weighted by a factor.
This can be accomplished by using different transistors.

BIBLIOGRAPHY
1. L. Esaki New phenomenon in narrow Ge pn junction, Phys.
Rev., 109: 603, 1958.
2. J. O. Scanlan Analysis and Synthesis of Tunnel Diode Circuits,
London: Wiley, 1966.
3. M. A. Lee B. Easter H. A. Bell Tunnel Diodes, London: Chapman and Hall, 1967.
4. J. Vandewalle L. Vandenberghe Piecewise-linear circuits and
piecewise-linear analysis, in Wai-Kai Chen, (ed.), The Circuits and Filters Handbook, Boca Raton, FL, CRC Press, 1995,
Chap. 35, pp. 10341057.
5. R. Ludwig P. Bretchkko RF Circuit Design, Theory and Applications, Upper Saddle River, NJ: Prentice Hall, 2000, pp.
307310.
6. R. Boylestad L. Nashelsky Electronic Devices and Circuit Theory, 6th ed., Englewood Cliffs, NJ: Prentice Hall, 1996.
7. R. W. Newcomb Linear Multiport Synthesis, New York:
McGraw-Hill, 1966.
8. A. S. Sedra K. C. Smith Microelectronic Circuits, 4th ed. Oxford: Oxford University Press, 1998.
9. J. P. A. Van der Wagt Tunneling-based SRAM, Proc. IEEE, 87:
571595, 1999.

10. E. Goto et al. Esaki

diode high-speed logical circuits, IRE
Trans. Electron. Comput., 9: 2529, 1960.
11. P. Muzumder et al. Digital circuit application of resonant tunneling devices, Proc. IEEE, 86: 664686, 1998.
12. J. P. Sun et al. Resonant tunneling diodes: Models and properties, Proc. IEEE, 86: 641661, 1998.

ROBERT W. NEWCOMB

SHAHROKH AHMADI
University of Maryland, College
Park, MD
George Washington University,
Washington, DC

 Stability is the receivers ability to remain tuned to the

desired frequency over time with variations in supply
voltage, temperature, and vibration, among others.

UHF RECEIVERS
An ultra-high frequency (UHF) receiver receives radio signals
with input frequencies between 300 MHz and 3000 MHz. Radio waves in this part of the spectrum usually follow line-ofsight paths and penetrate buildings well. The natural radio
environment is significantly quieter at UHF than at lower frequencies, making receiver noise performance more important.
UHF antennas are small enough to be attractive for vehicular
and hand-held applications, but are not as directional or expensive as microwave antennas. Many radio services use
UHF, including land mobile, TV broadcasting, and point-topoint. The point-to-point users are rapidly disappearing, and
the greatest current interest in receiver design centers on cellular and personal communications system (PCS) applications
in bands from 800 MHz to 950 MHz and 1850 MHz to 1990
MHz.
UHF receiver design was once a specialized field incorporating parts of the lumped-circuit techniques of radio frequency (RF) engineering and the guided-wave approach of microwave engineering. Recent trends in circuit integration and
packaging have extended RF techniques to the UHF region,
and there are few qualitative distinctions between UHF receivers and those for lower frequencies. UHF receivers differ
from their lower-frequency counterparts primarily by having
better noise performance and by being built from components
that perform well at UHF.

UHF RECEIVER OPERATION

The Role of a UHF Receiver in a Radio Communications System
Radio frequency communications systems exist to transfer information from one source to a remote location. Figure 1 is a
system block diagram of a simple radio communications system. A transmitter takes information from an external
source, modulates it onto an RF carrier, and radiates it into
a radio channel. The radiated signal grows weaker with distance from the transmitter. The receiver must recover the
transmitted signal, separate it from the noise and interference that are present in the radio channel, and recover the
transmitted information at some level of fidelity. This fidelity
is measured by a signal to noise ratio for analog information
or by a bit error rate for digital information.
Receiver Characteristics
The following characteristics describe receiver performance:
Sensitivity is a measure of the weakest signal that the
receiver can detect. The ideal receiver should be capable
of detecting very small signals. Internally generated
noise and antenna performance are the primary factors
limiting the sensitivity of UHF receivers.
Selectivity describes the receivers ability to recover the
desired signal while rejecting others from transmitters
operating on nearby frequencies.

Dynamic range is a measure of the difference in power

between the strongest signal and the weakest signal that
the receiver can receive.
Image rejection measures the receivers ability to reject
images, incoming signals at unwanted frequencies that
can interfere with a wanted signal.
Spurious response protection measures the receivers freedom from internally generated unwanted signals that interfere with the desired signal.
The Superheterodyne Architecture
The most widely used receiver topology is the superheterodyne or superhet. A block diagram of this topology is shown
in Fig. 2. It provides amplification both at the incoming radio
frequency and at one or more intermediate frequencies. The
incoming signal from the channel passes through the preselector filter, RF amplifier, and image filter, where it is applied
to the mixer. The mixer combines the incoming signal with
the local oscillator (LO) waveform to generate output at the
sum and difference of the signal and LO frequencies. The LO
frequency can be above or below the signal frequency. If the
LO frequency is above the signal frequency, the receiver uses
high-side injection. If the LO frequency is below the signal
frequency, the receiver uses low-side injection. The intermediate frequency (IF) filter selects either the sum or the difference and rejects the other. The selected frequency is termed
the intermediate frequency (IF), and the IF amplifier provides
additional gain at this frequency. The detector/demodulator
extracts the transmitted information from the IF waveform.
Some superhet architectures use two or more intermediate
frequencies in succession to simplify the requirements placed
on the filters. The mixing process is sometimes called conversion. A receiver with one intermediate frequency is a singleconversion receiver, and a receiver with two intermediate frequencies is a dual-conversion receiver. Unless explicitly
stated otherwise, examples in this article refer to single-conversion receivers.
While other receiver architectures exist, the superheterodyne has many advantages. Distributing the amplifier gain
between the RF and IF frequencies makes it less difficult to
prevent unwanted oscillation. The receiver is tuned to a
wanted input frequency by selecting the frequency of the LO.
The IF filter can have a fixed center frequency, so its characteristics like bandwidth and delay can be optimized. It does
not have to be retuned when the receiver is tuned to a new
channel.
Weak Signal Performance. At UHF, internally generated
noise limits the weakest signal that can be detected. The
noise generated by the RF amplifier is amplified by all the
stages in the receiver so that it determines the receiver sensitivity. Low-noise, high-gain RF amplifiers produce the greatest sensitivity. There is often a trade-off between sensitivity

613

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

614

UHF RECEIVERS

Information
source

Image
471.25 MHz

Transmitter

LO
516.25 MHz

Desired
561.25 MHz

IF
45 MHz

IF
45 MHz

Channel
22.5
MHz
Receiver

Information
destination

1/2 IF spur
538.75 MHz

Figure 1. Block diagram of a UHF communications system showing

the role of the receiver.

Figure 3. The frequency relationship between the desired signal, the

local oscillator signal, and the image signal for a TV receiver with a
45 MHz intermediate frequency. Note that the image and the desired
signal frequencies are symmetric about the local oscillator frequency.

and strong signal performance, since a high-gain RF amplifier

can overload the mixer with a strong signal.

tion is easier with high IF frequencies. The higher the IF frequency, the more difficult it is to make narrowband filters.
Filters are the major impediment to fully integrated UHF receivers. They are usually separate discrete components.

Images
The mixing or frequency conversion process introduces unwanted and spurious responses. The most important unwanted response is called an image. The image frequency and
the wanted frequency are symmetrical about the LO frequency. Any unwanted signal at the image frequency that
gets into the mixer will be amplified and demodulated essentially as if it came in at the wanted frequency. Consider a
simple example. A TV broadcast receiver is tuned to 561.25
MHz, the video carrier frequency for television channel 29.
The receiver has an IF of 45 MHz, so the LO runs at 516.25
MHz. A difference frequency of 45 MHz is generated by mixing 561.25 MHz and 516.25 MHz. Suppose there is a nearby
transmitter on channel 14. When the 471.25 MHz channel 14
video mixes with the 516.25 MHz LO output, the difference is
also 45 MHz. The receiver is tuned to channel 29, but it will
also pick up channel 14 if the channel 14 signal reaches the
mixer. The preselector and image filters must pass the desired signal but reject the image. Figure 3 shows the frequency relationship among the desired signal, the image, and
the LO for a single-conversion receiver. Note that the image
and the wanted response are separated by twice the IF frequency. A dual-conversion superhet would have three images.
Images are the key drawback to the superheterodyne architecture. Their elimination requires filters, and image rejec-

Spurious Responses
The image is only one of many possible unwanted mixer outputs. The mixer is an inherently nonlinear device that generates and combines harmonics of the LO and signal frequencies. Continuing with the numbers from the previous
example, the second harmonic of the 516.25 MHz LO appears
at 1032.5 MHz. If a 538.75 MHz signal reaches the mixer, the
mixer generates a second harmonic at 1077.5 MHz. The mixer
also generates the sum and the difference of the harmonics.
One of these products is at the 45 MHz IF frequency, and the
receiver has a spurious response at 538.75 MHz. This response is sometimes called the half IF spur because it appears
22.5 MHz or one-half the IF frequency from the desired response. Two times the IF, in this case 90 MHz, separates the
image from the wanted signal. It is much easier to design the
image and the preselector filters to remove the image than
the half IF spur.
Other spurious products are a serious problem in superhet
receivers. Mixers generate not only the second harmonic but
higher-order harmonics as well. Balanced mixers, which suppress the even-order harmonics, are widely used to eliminate
some of the spurious mixing products. UHF receivers may
have multiple mixers and intermediate frequencies, and pre-

Local oscillator
Preselector
filter

RF
amplifier

Image
filter
Mixer

Input

Output
Figure 2. The architecture of a superheterodyne receiver.

IF filter

IF amplifier

Detector
demodulator

UHF RECEIVERS

f1
870.060
MHz

Spectrum
analyzer

Combiner

f2
870.090
MHz

Device under
test

Figure 4. A test set up for measuring third-order products. The frequencies shown are for the example presented in the text.

dicting all the spurious mixing products can be difficult. Software for this purpose is commercially available to help the
designer select mixers.
Strong Signal Behavior. At UHF frequencies it is difficult to
build a preselector filter narrow enough to pass a single channel of information. It may not be desirable to build very narrowband filters if the receiver is to be tuned over a range of
frequencies. If the range of desired signal frequencies cannot
pass through the preselector filters, then these filters must be
retuned when the LO is tuned to the new frequency. This
process, called tracking, increases the complexity of the receiver. For these reasons the receivers ultimate bandwidth is
usually set at IF, and a number of unwanted signals can
reach the mixer.
All of the unwanted signals that reach the mixer will produce sum and difference frequency products with the LO. The
RF amplifier may generate some of the unwanted signals. RF
amplifiers are not perfectly linear; strong signals can cause
them to saturate. This nonlinearity generates harmonics,
which combine either in the amplifier itself or in the mixer.
The nonlinear behavior of amplifiers and mixers is specified in terms of third-order mixing products. Figure 4 shows
a test set up for measuring these products. The output for an
ideal amplifier would be only at the input frequencies f 1 and
f 2. Amplifier nonlinearities generate harmonics of f 1 and f 2
plus the mixing products of these harmonics. These mixing
products are specified in terms of the harmonic number of the
signals that generate them. Particularly important are the
third-order products 2f 1 f 2 and 2f 2 f 1. Figure 5 shows the
output of a nonideal amplifier. The third-order products are
the most problematic since their frequencies fall close to the
desired signal and are difficult to filter.
As an example, consider a handheld analog cellular telephone receiver. Channel 1 is 870.030 MHz, channel 2 is
870.060 MHz, channel 3 is 870.090 MHz, and channel 4 is

Input signals
870.06

870.09

Power
870.03

870.12

Third-order
products

Frequency (MHz)
Figure 5. Sketch of a spectrum analyzer display showing the output
of a nonideal amplifier with strong input signals at 870.06 and 870.09
MHz. The amplifier generates unwanted third-order products at
870.03 and 870.12 MHz.

615

870.120 MHz. The second harmonic of channel 2 is 1740.12

MHz. If this mixes with channel 3, the difference is 870.030
MHz, which is channel 1. Similarly, the second harmonic of
channel 3 mixes with channel 2 to produce a signal at 870.12
MHz, which is channel 4. Figure 5 shows that third-order
mixing of channels 2 and 3 creates signals on channels 1 and
4. If the receiver is tuned to channel 1 or 4 and strong channel
2 and 3 signals are present, then nonlinear RF amplifier or
mixer products will interfere with channel 1 or 4, limiting the
receivers ability to detect a weak signal on these channels.
The nonlinear products increase with increasing signal levels. The power in the third-order products increases three
times faster than the power of the desired signals. The point
where the power in the third-order products would be equal
to the power in the desired signal is called the third-order
intercept point.
Spurious Free Dynamic Range. The weakest signal the receiver can detect is limited by the internally generated noise.
The equivalent power of this noise is the noise floor. The
strongest signals the receiver can tolerate without internally
generated interference are those that create a third-order
mixing product that equals the noise floor. The ratio of the
strongest signal power to the noise floor power is the spurious
free dynamic range (SFDR).
High-gain, low-noise RF amplifiers maximize sensitivity.
Maximizing SFDR requires a careful tradeoff among the gain,
noise performance, and third-order intercept of all the stages
prior to the narrowest filter in the system. Building a sensitive receiver is relatively easy; building a sensitive receiver
that can handle strong signals can be a challenge.
Other Receiver Topologies
Direct Conversion Receivers. The superhet receiver converts
the incoming signal to an intermediate frequency, but it is
possible to convert the radio signal directly to the original
baseband of the transmitted information. This requires the
LO to be tuned to the frequency of the incoming signal. If the
signal and LO frequencies are equal, their difference is zero.
The mixer output is the original information, which was contained in modulation sidebands, about the carrier frequency.
A receiver that works this way is called a direct conversion
(DC), homodyne, or zero IF receiver (see Fig. 6).
Direct conversion receivers offer a simpler design and
fewer components than superhets. High-gain amplifiers are
easier to build at baseband than at the signal or IF frequency,
so a DC receiver can be as sensitive as a superhet. This topology minimizes the number of components at the RF and IF
frequencies. On the other hand, mixer imbalance and LO
leakage (LO feedthrough) into the antenna can cause large
DC offsets. Local oscillator phase noise is highest close to the
LO frequency, and the mixer translates this noise directly to
baseband. Low frequency noise in mixers and high-gain baseband amplifiers can limit sensitivity. Depending on the choice
of mixer, DC receivers have spurious responses at integer
multiples of the input frequency, so a preselector filter is still
required. Since all the signal processing occurs at baseband,
it is possible to integrate the entire receiver, including the
mixer. This is attractive for small low-power receivers like
those found in pagers. DC receivers cannot be used for narrowband FM without extra signal processing.

616

UHF RECEIVERS

Local oscillator
Preselector
filter

RF
amplifier

Input

Output
Mixer

Low-pass
filter

Baseband
amplifier

Figure 6. The homodyne or direct conversion receiver. The incoming signal is converted directly
to baseband without intermediate processing at an intermediate frequency.

Tuned Radio Frequency Receivers. The tuned radio frequency (TRF) receiver of Fig. 7 is an old design that offers
great simplicity. The signal passes through a preselector filter
and is amplified by an RF amplifier at the signal frequency.
The classic TRF receiver consists of a cascade of tuned amplifiers. The filtering and amplifying functions are combined.
The amplified signal goes directly to the detector, which is
typically a simple diode amplitude demodulator. TRF receivers work well with amplitude modulation or on-off keyed digital signals. They are not used for narrowband phase or frequency modulation, since these waveforms are difficult to
demodulate at UHF. The simplicity of the TRF is attractive
for low-current, low-cost applications. Because the TRF receiver has no oscillators, there is no oscillator radiation. TRF
receivers escape the government regulations that limit RF
emissions. They have none of the spurious mixing responses
that are a problem in superhet receivers. Because TRF receivers contain no mixers, they have no images and can reproduce
exactly the frequency or phase information in the original
signal.
TRF receivers have several disadvantages. They are not
frequency agile and thus are useful only for single-frequency
systems. TRF receivers cannot use standard low cost filters
like those available at common IFs for superhets. Narrowband filters, which match modulation bandwidths, are difficult to build at UHF, and tuning a TRF receiver to a new
frequency requires retuning or replacing the filters. TRF receiver sensitivity is limited because of the difficulty of building stable high-gain amplifiers at UHF. For these reasons,
the UHF applications for TRF receivers tend to be limited to
very low cost short-range devices.
Regenerative and Superregenerative Receivers. Regenerative
receivers come from the earliest days of radio and are capable
of very high sensitivity with only a single active device. A
regenerative receiver is an amplifier to which frequency selective positive feedback has been applied. If the feedback is adjusted below the point of oscillation, the receiver acts as a
square law detector. It is suitable for amplitude modulated
signals. The feedback can be advanced to the point where oscillation occurs. The regenerative receiver then acts as a self-

Preselector
filter

Figure 7. The tuned radio frequency receiver. The incoming signal is amplified
and detected without frequency conversion.

oscillating direct conversion receiver. In this mode, it will demodulate single sideband (SSB) or continuous wave signals.
The superregenerative receiver is a variation on the regenerative theme. The positive feedback is advanced beyond the
point where oscillations begin. This increases the gain. It
takes a finite amount of time for the oscillation amplitude to
build up due to energy storage in the oscillator-tuned circuit.
Before the oscillation amplitude reaches a significant level,
the oscillating amplifier is shut off or quenched. The process
of oscillation buildup and quenching is repeated. Injecting a
signal close to the oscillation frequency speeds the buildup of
oscillations. The envelope of any amplitude modulation on the
injected signal can be extracted from the amplitude of the oscillations in the superregenerative detector.
Superregenerative receivers find application in shortrange, low-cost devices such as radio-controlled toys and garage door openers. They work well at UHF, and their high
sensitivity and extreme simplicity make them attractive for
such applications.
The major drawbacks of a superregenerative receiver are
poor selectivity and the potential to create interference. They
can be easily overloaded by strong adjacent channel signals,
and, if not properly designed, they can radiate a potent signal
of their own. The use of positive feedback results in very high
gain, but it accentuates any variations in amplifier gain due
to temperature, voltage, aging, or other effects. Stable performance is difficult to obtain, and receiver bandwidth will vary
inversely with gain. It is very difficult to meet emission specifications with regenerative and superregenerative receivers.

DESIGNING SUPERHETERODYNE RECEIVERS FOR UHF

Weak Signal Behavior
Noise Temperature and Receiver Sensitivity. Sensitivity is a
measure of a receivers weak signal performance. Depending
on the particular application, sensitivity may be expressed in
terms of (1) the receivers noise floor, (2) the minimum detectable signal, or (3) the minimum input signal level necessary
to achieve a useful output. However defined, sensitivity is

RF
amplifier

Input

Output
Detector

Baseband
amplifier

UHF RECEIVERS

617

TA, the resulting system noise temperature TS is given by

TA

TS = TA + Te
Real receiver
Gain g
Bandwidth B
Noisy

Figure 8. Representation of a real receiver. It amplifies thermal

noise from the antenna and adds its own internally generated noise.

closely related to the irreducible noise level at the receivers

output.
Noise is generated within all electronic components, active
or passive. The noise power that a resistor at physical temperature T would deliver to an ideal power meter whose response
is frequency independent over a measurement bandwidth B
is given by
PN = kTB

(1)

where k is Boltzmanns constant (1.38 1023 J/K).

Any other one-port noise source can be described by an
equivalent noise temperature TN such that the noise delivered
to an ideal power meter with measurement bandwidth B is
PN = kTN B

(2)

Now imagine a two-port device with gain g connected between

an antenna or other noise source with noise temperature TA
and a load. The noise power delivered to the load will consist
of amplified input noise plus additional noise that is generated inside the two-port device:
pN = gkTA B +
p

(3)

where p is the internally generated noise (see Fig. 8).

For analysis, it is convenient to represent the internally
generated noise as if it came from a fictitious noise source at
the input of a noiseless equivalent circuit of the two-port device. This noise temperature Te of this fictitious noise source
is the effective input noise temperature of the device (see Fig.
9):
pN = gkTA B +
p = gkTA B + gkTe B = gk(TA + Te )B

(4)

If a receiver with effective input noise temperature Te is

connected to an antenna with equivalent noise temperature

TA

Te

Equiv receiver
Gain g
Bandwidth B
Noiseless

PN

Figure 9. The noiseless equivalent receiver. Internally generated

noise is represented as if it came from a fictitious input at temperature Te.

(5)

The receiver noise floor is kTSB, where B is the overall receiver bandwidth (usually set by the IF filter). The minimum
detectable signal (MDS) is usually specified as the noise floor.
Depending on the application, the receiver sensitivity may be
defined as the noise floor or as the minimum signal necessary
to produce a specified output signal-to-noise ratio (SNR). The
noise floor is sometimes specified with a bandwidth B of 1 Hz.
At room temperature, this corresponds to 174 dBm.
Noise Figure. While noise temperature is perhaps a more
immediately useful quantity, the noise figure of a UHF receiver is more commonly specified. The noise figure of a twoport device was originally defined as the ratio of the input
SNR to the output SNR. This definition is quite useful for
back of the envelope calculations for point-to-point microwave systems, but it suffers from a lack of uniqueness (since
it depends on the antenna noise temperature) and universal
applicability. Officially, noise figure is the ratio of (A) the
total noise power per unit bandwidth (at a corresponding output frequency) delivered by the system into an output termination to (B) the portion thereof engendered at the input frequency by the input termination, whose noise temperature is
standard (290 K at all frequencies) (1).
Mathematically, the noise figure is given as a ratio by nf
and in decibels by NF:
nf = 1 +

Te
290

NF = 10 log10 (nf )

(6)
(7)

While some authors argue rather vehemently that noise figure is not a meaningful concept, it is well established as a
specification for UHF receivers and their components. Overall
values of 2 dB are achievable. Most calculations ultimately
require the noise temperature, conveniently obtained from
the noise figure by
Te = 290(nf 1)

(8)

The noise figure as defined in Eq. (6) is the standard noise

figure, based on an assumed standard source noise temperature of 290 K. This is the one that manufacturers measure
and quote. An actual noise figure, based on the true source
temperature, is often used to calculate the minimum detectable signal or SNR degradation. See Ref. 2 for an excellent
discussion of noise figure issues.
Determining Receiver Noise Temperature and Noise Figure. Most analyses of receiver performance assume that
bandwidth narrows as one moves from the RF input to the IF
output. The last stage has the narrowest bandwidth, and it
effectively determines the overall bandwidth. Thus, if the preselector, RF amplifier, mixer, and so on, have bandwidths
B1, B2, B3 . . . BN, and if BN is much less than any of the
others, then the overall bandwidth B is given by
B min{B1 , B2 , B3 . . . BN } = BN

(9)

UHF RECEIVERS

Under these conditions, the overall noise temperature and

noise figure are given by

Te = T1 +
nfo = nf1 +

N1

1
T2
T
+ 3 + TN
g1
g1 g2
g
m=1 m

N1

1
nf2 1 nf3 1
+
+ (nfN 1)
g1
g1 g2
g
m=1 m

(10)

(11)

where Ti, gi, and Bi are the noise temperature, gain, and
bandwidth of the ith stage. It is important to note that the
gains and noise figures in the preceding equations are ratios,
not decibel values.
If one bandwidth dominates but is not the bandwidth of
the last block in the chain, it is still possible to calculate Te
and NFo. This situation occurs in some modern receiver designs that put most of their gain in a wideband amplifier at
the end of the IF chain. A narrowband low-gain amplifier precedes the mixer. This architecture leads to better dynamic
range performance. Under these conditions, let B1 and g1 be
the bandwidth and gain of the low gain and narrowband part
of the receiver, and let B2 and g2 be the bandwidth and gain
of the subsequent high gain and wideband part of the receiver. The corresponding noise temperatures and noise figures are T1 and nf1 and T2 and nf2. Under these conditions,
the output noise power is given by Eq. (12) and the overall
noise temperature and noise figure by Eqs. (13) and (14).
po = g1 g2 kTA B1 + g1 g2 kT1 B1 + g2 kT2 B2
= g1 g2 kTA B1 + g1 g2 kTe B1
Te = T1 + T2
nfo = 1 +

B2
g1 B1

Te
B
= nf1 + (nf2 1) 2
To
g1 B1

(12)
(13)
(14)

It is possible for the wideband IF stage to dominate the receivers noise performance in this topology. Additional filters
are sometimes added just prior to the detector, or as part of
the detector, effectively narrowing B2.
Mixer Noise Performance. Like all two-port devices, mixers
both process incoming noise and add to it their own internally
generated noise. The situation is more complicated in mixers
because the input noise is translated in frequency from two
places in the spectrum. Noise coming in at the wanted signal
frequency and at the unwanted image frequency appears at
the IF frequency. Depending on how the total output noise
power is interpreted, a mixer can be described by both a double sideband (DSB) noise figure and a single sideband (SSB)
noise figure. A single sideband noise temperature corresponds
to the single sideband noise figure, and a double sideband
noise temperature corresponds to the double sideband noise
figure. The SSB quantities are twice as large (or 3 dB larger
if expressed in decibels) as the DSB quantities, which seems
backward.
This confusion arises largely because SSB and DSB apply
to the NF measurement technique rather than to the way in
which the mixer is used. In an NF measurement, the input to
the mixer is connected to a broadband noise source, and the
noise power at the mixer output is compared to the noise

power at the mixer input. The noise figure so measured is

called the DSB NF because noise got into the mixer through
both the wanted signal frequency and the unwanted image
frequency. Noise at the two frequencies is analogous to the
two sidebands that surround a carrier in some modulation
schemes. For the given output power, there is twice as much
input noise power as there would be in an SSB noise measurement. Thus, the signal-to-noise ratio is 3 dB better than
it would be in an SSB noise measurement, and the DSB noise
figure is 3 dB better than the SSB noise figure. See Refs. 3
and 4 for a detailed discussion of the measurement issues.
A double set of parameters with the SSB quantities larger
than the DSB quantities leads to a great deal of confusion
about which noise figure should be used for a particular application. See Ref. 2 for a detailed discussion of this point. The
rule of thumb is if, for a particular application, the mixer input sees equal incoming noise powers at the signal and image
frequencies, the mixer is described by the SSB noise temperature and noise figure. If the input noise level at the signal
frequency is much greater than the input noise level at the
image frequency, then the frequency-translated image noise
has little effect on the output noise power, and the mixer is
described by the DSB noise temperature and noise figure.
The last situation is attractive because it allows the lower
noise figure to be used. The reader should note that its application does require that the mixer see insignificant input
noise in the image band. If the stage immediately ahead of
the mixer is an image rejection filter, its noise output in the
image band should be checked. The filter could look like a
noise source at the ambient temperature.
LO Phase Noise. Local oscillator noise can be a significant
contributor to the overall receiver noise level. Oscillator noise
takes two forms: amplitude and phase noise. In well-designed
oscillators, the effect of amplitude noise can be neglected (5),
but phase noise effectively phase modulates the oscillator frequency. Oscillator performance is measured in terms of the
power spectral density of the resulting modulation sidebands.
The spectral density can be predicted from the Q of the oscillator resonator and from the noise power generated by the
active device in the oscillator (6). Figure 10 shows the phase
noise in a typical oscillator output spectrum.

Power spectral density (dBc/Hz)

618

30
50
70
90
110
130
150
170
10

100

1000
10K
100K
Offset from carrier (Hz)

1M

Figure 10. The phase noise spectrum of a typical local oscillator.

UHF RECEIVERS

IF
IF bandwidth

Mixed
oscillator
noise
Frequency
IF

Compression
pt.

Strong adjacent
channel signal

Weak desirable
signal

Saturation

Output power, dBm

Noisy LO

619

Linear
region

1 dB
Overdrive
Compression

Figure 11. An illustration of reciprocal mixing, the process by which

local oscillator phase noise combines with an adjacent channel signal
to raise the receiver noise floor.

Input power, dBm

Strong Signal Behavior

Nonlinear Operation and Intermodulation Products. In ideal
linear components superposition holds, and the output waveform is linearly proportional to the input waveform. No frequencies appear in the output waveform that were not present in the input waveform. Any real two-port device will,
when driven hard enough, become nonlinear. Nonlinear operation in receivers creates unwanted signals called intermodulation products that interfere with the wanted signals. It also
can cause a loss of sensitivity when an unwanted strong signal is close in frequency to a wanted weak signal.
To illustrate nonlinearity, consider an RF amplifier with a
sinusoidal input at frequency f 1. A typical plot of input power
versus the output power delivered at frequency f 1 would appear as shown in Fig. 12.
At low power levels, the relationship between output and
input powers is linear. At high levels of input power, the slope
decreases and the input-output relationship becomes nonlinear. This onset of nonlinearity is called gain compression (or
just compression). A common measure of large-signal handling ability is the input 1 dB compression point, the input
power level at which the output power falls 1 dB below the
extrapolation of the linear relationship. Gain compression in
a receiver results in an effect called desensitizing. If a receiver is tuned to a weak signal and a strong signal appears

Figure 12. Nonlinear behavior of an amplifier. As the input power

level increases, the gain decreases below its linear value.

in the RF amplifiers passband, the strong signal can reduce

the RF amplifier gain. The gain reduction can make the weak
signal disappear even though the strong signal is not translated into the IF passband and never reaches the demodulator. Desensitizing is a problem in large signal handling that
is distinct from intermodulation products.
Increasing the input power beyond the 1 dB compression
point causes the plot to fall farther below a linear relationship. This part of the curve is called the compression region.
The output power reaches a peak and then decreases. The
peak is called saturation, and the region beyond the peak is
the overdrive region.
Output power falls below the linear value after compression begins because output is developed at frequencies other
than the input frequency. As long as the input is a sinusoid
at frequency f 1, these frequencies are harmonics of f 1 (i.e.,
2f 1, 3f 1 . . .) and easy to filter. If the input contains two or
more frequencies, then the resulting intermodulation products can interfere with and distort the wanted output signal.
Intermodulation products are usually described in terms of
a two-tone test, where the input signal is two equal-amplitude
sinusoids at closely spaced frequencies f 1 and f 2. These represent a wanted signal and an equal-amplitude adjacent-channel interferer. Nonlinearities cause outputs to appear at all
the sums and positive differences of integer combinations of
f 1 and f 2. The most important are the third-order products at
frequencies 2f 1 f 2 and 2f 2 f 1, described earlier (see Fig.
13).

Output power, dBm

Phase noise degrades receiver dynamic range through

what is called reciprocal mixing. Figure 11 shows the effect
of reciprocal mixing in a receiver containing a noisy LO and
a strong adjacent channel signal that is outside the IF bandwidth. Without the LO noise, this signal would be rejected by
the IF filter. With LO noise the strong adjacent channel signal acts as a local oscillator for the oscillator noise. The oscillator noise appears as signals adjacent to the LO, and those
noise frequencies separated by the IF from the interfering signal will be mixed into the IF. The noise floor is increased by
the oscillator phase noise, and it obscures the desired weak
signal.
Phase noise produces an additional receiver impairment in
systems where information is carried in signal frequency (frequency modulation, FM) or phase (phase modulation, PM).
In digital phase shift keyed (PSK) systems, it is necessary to
regenerate the phase of the carrier signal as a demodulation
reference. Mixing transfers the phase noise of the receivers
LO to the incoming signal. This increases the phase uncertainty of the demodulation reference and leads to bit errors.

Po1 Po1
R, dB
Po3

Po3

2f1f2 f1

f2 2f2 f1

Frequency
Figure 13. The spectrum of the output of a nonlinear amplifier with
inputs at frequencies f 1 and f 2. The amplifier creates unwanted thirdorder products at frequencies 2f 1 f 2 and 2f 2 f 1. The wanted output
signals are at power level Po1 and the unwanted products are at
power level Po3.

620

UHF RECEIVERS

To quantify the process, one should plot the output power

Po3 at one of the third-order frequencies (2f 1 f 2 or 2f 2 f 1)
versus the input power Po1 at f 1 or f 2. On a dBm or dBW scale,
the curve will be a straight line with a slope of 3, at least for
reasonable values of input power (7). On the same graph we
can also plot output power at one of the input frequencies.
Below the compression region, this will be the straight line.
If we extrapolate the straight line far enough, it will cross
the third-order curve at the third-order intercept point. The
corresponding input power is called the third-order input intercept point IIP3, and the corresponding output power is
called the third-order output intercept point OIP3 (see Fig.
14). IIP3 and OIP3 measure the strong-signal handling capabilities of an amplifier, mixer, or other two-port device. Note
that the third-order intercept point is a graphical construction. No real device operates at that point.
To measure the intercept points, one can drive the device
at a level where the third-order products are measurable and
view the output on a spectrum analyzer. Figure 13 sketches
the resulting display. If Po1 and Po3 are the output powers in
dBm at one of the wanted frequencies and one of the thirdorder frequencies, then the rejection R is given by
R = Po1 Po3 dB

(15)

Po1 is related to the input power Pi at one of the wanted frequencies ( f1 or f 2) by the gain, G, of the device.
Po1 = Pi + G dBm

(16)

The input and output intercept points can be calculated from

R
+ Pi dBm
2

(17)

R
+ Po1 dBm
2

(18)

OIP3 = IIP3 + G dBm

(19)

IIP3 =
OIP3 =

Determining Receiver Third-Order Intercept Point. Consider

a receiver that consists of a cascaded system of M stages with

dB gains Gi and dBm input intercept points IIPi. The corresponding linear values are gi and iipi.
Following Ref. 8, we assume that (1) the interfaces between stages are all at 50 , and (2) the third-order products
add in-phase. Assumption (1) is realistic, and assumption (2)
leads to a worst-case analysis. Under these conditions, we can
project the output intercept points of the individual stages
through to the output of the last stage and add the projected
values reciprocally. For 1, 2, 3, and M stages, the overall output intercept point in milliwatts is given by

oipo =

oipo =

oipo =

oipo =

1
for 1 stage
1
oip1

1
for 2 stages
1
1
+
oip2
g2 oip1

1
for 3 stages
1
1
1
+
+
oip3
g3 oip2
g3 g2 oip1
1
for M stages
M1
1
1
+ i=1
M
oipM
oipi k=i+1 gk

(20)

(21)

(22)

(23)

This formula can be written in a simpler form to yield OIPo

directly in dBm:


M

1
(24)
OIPo = 10 log10
oipi gi+1 gi+2 . . . gM
i=1
The overall input intercept point is the overall output intercept point divided by the total gain.
oip
iipo = M o
i=1 gi

(25)

Expressed in dBm,

IIPo = OIPo

M


Gi

(26)

i=1

Output power, dBm

Dynamic Range
Third-order intercept
point, IP3

OIP3

Po1
1

R
3

Po3
IIP3
Input power, dBm
Figure 14. An illustration of how first-order (Po1) and third-order
(Po3) output power increase with increasing input power in a nonlinear device. The straight-line extrapolations of the two curves cross at
the third-order intercept point.

The dynamic range of a receiver is the decibel difference between the strongest signal and the weakest signal that the
receiver can handle. There are multiple definitions of dynamic
range, depending on how the strongest signal and the weakest signal are defined.
Spurious Free Dynamic Range. Spurious free dynamic range
makes the weakest signal the MDS (receiver noise floor
kTSB), where TS is the system noise temperature and B is the
bandwidth. TS is the sum of the antenna noise temperature
TA and the effective input noise temperature of the receiver
Te:
TS = TA + Te

(27)

so this definition describes the receiver when it is used with

an antenna having a specified noise temperature.

UHF RECEIVERS

621

Output power, dBm

where m and n are positive integers. If any of these spurious

responses (spurs) fall within the IF passbandthat is, if
Third-order intercept
point, IP3

OIP3

f o (m, n) = f I

B
2

(32)

Po1

Po3
Noise floor at output

SFDR

MDS + G

x1
MDS

x3

IIP3

Input power, dBm

where B is the IF bandwidththey can interfere with wanted

signals. The frequencies f I, f R, and f L must be chosen so that
this either does not occur or any spurs within the IF passband
are at negligible power levels. The process, described later, is
outlined in Ref. 9. The amplitudes of the spurs depend on the
nature of the mixers nonlinearity. Typical values are found
in Ref. 10 and in most mixer manufacturers catalogs.
We began by treating the frequencies as parameters and
m and n as positive real variables. The relationship between
m and n is

Figure 15. The spurious free dynamic range of a receiver is the decibel difference between the noise floor and the input signal level that
would bring third-order products to the noise floor.

The strongest signal used in the SFDR definition is the

input power that, in a two-tone intermodulation test, makes
the power in either of the third-order products at the receiver
output equal to the noise power (see Fig. 15). Mathematically,
2
SFDR = (IIP3 MDS) dB
3

LO and IF Frequency Selection. There are several standard

IF frequencies (10.7 MHz and 45 MHz are two examples commonly used in UHF radios), and the selected IF frequency
should be one for which appropriately priced components are
available. The higher the IF frequency, the farther images
will lie from the wanted frequency and the easier it will be to
filter them out. Beyond these general guidelines, the IF and
LO frequencies should be selected so that no high-level intermodulation products fall within the IF passband.
To illustrate the process, consider a mixer with input signal f S, local oscillator signal f L, and wanted IF output signal
f I. Depending on whether the LO frequency is above (highside injection) or below (low-side injection) the signal frequency, the mixer will produce a wanted output at either

fI
f
+ m L (curve I)
fR
fR
fI
fL
n=
m (curve II)
fR
fR
fI
f
n=
+ m L (curve III)
fR
fR

(29)

or
(30)

The mixer will also produce unwanted outputs at all positive

values of
(31)

(34)

We plot these for f R and f L corresponding to the upper and

lower limits of the receivers tuning range. The needed lines
are easy to draw from the known intercepts ( fI /f R) and ( fI /f L)
and the slope ( fL /f R). Ideally only the line representing the
wanted response should pass through a point corresponding
to integer values of m and n. That should be the (1, 1) point.
If one of the plotted curves comes close to an integer-valued point, we can determine if the corresponding spur lies
within the passband by plotting the appropriate line with f I
replaced by f I B/2.
n
5

(fL/fR)

(I)

4
3
(fI/fR)

(II)

Wanted (1,1)
(fL/fR)

(III)

f o (m, n) = (m f L nf R )

(33)

All solutions to Eq. (33) that yield integer values of m and n

correspond to spurious responses that may fall within the IF
passband of the receiver.
Plotting these equations on a set of n versus m axes (Fig.
16) yields three straight lines whose equations are

(28)

UHF Receiver Design

fI = fR fL

fI
f
m L
fR
fR

n=

Other Definitions of Dynamic Range. In practice, third-order

products may be tolerated at levels somewhat higher than the
noise floor. The maximum permissible signal may be the input power for which the rejection R in Eq. (17) reaches a specified level.

fI = fL fR

n=

1
2
(fL/fR)

Figure 16. A graphical technique to check for mixer spurious responses in a receiver. The three straight lines are plotted from Eq.
(34). In an ideal receiver design, the lines would not cross any points
corresponding to integer values of both m and n except (1, 1).

622

UHF RECEIVERS

With properly chosen IF and LO frequencies, no high-level

spurs will fall within the IF passband. Usually, a high LO
frequency gives better performance.
Mixer Selection (11). Almost any nonlinear device can serve
as a mixer. Mixers can be active or passive, and they can rely
on filters or cancellation or on some combination of both to
provide needed isolation between their RF, IF, and LO ports.
Figures of merit for mixers include conversion gain, noise
figure, third-order intercept point, required LO drive, and relative levels of intermodulation products. Some mixer types
are more sensitive to impedance mismatches than others.
Active mixers require dc power, less amplifier gain, and
less LO drive than passive mixers. Passive mixers do not need
dc, but they require more LO drive and more amplifier gain
than active mixers. Which type of mixer requires less total dc
power for the whole receiver depends on the overall design.
Manufacturing factors (cost, ease of automated assembly,
etc.) may be more important in mixer selection than small
differences in RF characteristics or power consumption.
Mixers may be unbalanced, single balanced, or double balanced. An unbalanced mixer usually has a single active component (a diode or a transistor) and relies on filters to provide
LO-RF and LO-IF isolation. Single-balanced mixers use cancellation to achieve LO-RF isolation and filters for LO-IF isolation. Double-balanced mixers use cancellation to achieve
both LO-RF and LO-IF isolation. Usually (but not always)
whether a mixer is unbalanced, single balanced, or double
balanced can be determined by counting the balun transformers. An unbalanced mixer has none, a single-balanced mixer
usually has one, and a double-balanced mixer usually has
two.
Diode mixers operate as switches and chop the RF waveform at the LO frequency. Since proper operation depends on
the LO rather than the RF signal turning the diodes on and
off, the maximum RF power that a diode mixer can handle
without unacceptable distortion is somewhere between 10 and
6 dB below the LO level. Switching-diode mixers usually offer
a larger dynamic range but higher conversion loss and noise
figure than mixers whose operation is based on device nonlinearity.
Low-cost double-balanced diode mixers are widely available. They are inherently broadband and offer conversion
gains typically between 6 and 8 dB. Required RF drive
levels are fairly high5 dBm is typical.
Passive field-effect transistor (FET) mixers apply the LO
directly to the gate of an unbiased FET. The LO drive modulates the channel resistance at the LO frequency, and the RF
signal applied to the drain sees this modulation. Because
their operation is based on this resistance modulation, passive FET mixers are often called FET resistive mixers. Their
primary advantage over diode mixers is that they offer very
good intermodulation distortion performance; third-order input intercept points of 30 dBm or better are possible. FET
resistive mixers can be made with single devices or in singlebalanced and double-balanced configurations.
Active FET mixers can consist of single devices. In the
past, dual-gate active FET mixers were common, but these
have largely disappeared. Gilbert cell multipliers offer uniformly good performance.
An image-canceling mixer contains two internal mixers
whose LO drives are 90 out of phase. The RF amplifier out-

put is divided and fed to both mixers in phase. The output of

one internal mixer is phase shifted by an additional 90. The
resulting waveforms may be added or subtracted to cancel the
unwanted (image) response. (See Ref. 2.) Successful operation
of an image-canceling mixer depends on maintaining the required power levels and phase shifts over the IF bandwidth
for the expected signal amplitudes and operating temperature
ranges. Typical image suppression is in the 28 to 45 dB range.
RF and IF Amplifiers. RF amplifiers for UHF receivers are
selected to give the desired overall noise figure and dynamic
range. IF amplifiers are selected to present a particular desired signal level at the demodulator. To keep the demodulator from being overdriven at high input signal levels, IF amplifiers may incorporate limiting or automatic gain control
(AGC), depending on whether or not signal amplitude information is important. Both RF and IF amplifiers are available
as separate components for all standard frequency bands,
chips combining IF and mixing or RF and mixing functions
are widely available. These typically incorporate Gilbert cell
multipliers. One current example is the Motorola MC13156
wideband IF system that may be used as the basis for a complete radio or IF system for frequencies up to 500 MHz. Another is the RF Micro-Devices RF2411, covering 500 MHz to
1900 MHz.
RF and IF Filters. The first stage of most receivers is a bandpass filter (often called a preselector) that rejects noise and
unwanted signals (particularly unwanted signals at image
frequencies) outside of the desired tuning range. Bandpass
filters at IF keep unwanted mixer products out of the demodulator, select the desired channel, and determine the overall
noise bandwidth of the receiver. The IF filter usually determines the selectivity of a superhet receiver.
Selecting RF and IF filters is similar to selecting mixers.
There are many competing types and usually no immediately
obvious best choice for a given application. RF filter design
and manufacturing are so specialized that receiver designers
usually select filters from catalogs and data sheets instead of
building their own. Selection is based on technical characteristics, price, and manufacturing considerations.
Filters for IF include crystal, ceramic, and SAW (surface
acoustic wave). RF filters can be made with SAW, dielectric,
helical resonator, and transmission line technologies. LC filters tend to be too lossy for these applications. Active filters
are usually not available or not cost effective at RF and IF frequencies.
Filter specifications are based on treating the filter as a
two-port device driven by a source with a specified resistance
RI and feeding a load resistance Ro. The values of RI and Ro
depend on the filter type and frequency range. For example,
ceramic filters for 10.7 MHz IF applications expect to see 330
, while values between 1 and 2.5 k are common for 455
kHz ceramic filters.
Let Vo and Vi be the phasor output and input voltages for
a filter operating at frequency f. The complex transfer function H( f) of the filter is given by
H( f ) =

Vo ( f )
= |H( f )|e j ( f )
Vi ( f )

(35)

ULTRASONIC AND ACOUSTIC MICROMECHANICAL DEVICES

7. D. Heknes and S. Kwok, Intermodulation: Concepts and calculations, Appl. Microw. Wireless, 9 (4): 3843, 1997.

The filter attenuation A in dB is given by

A( f ) = 20 log10 |H( f )|

623

(36)

8. S. Wilson, Evaluate the distortion of modular cascades, Microwaves, 21 (3): 6770, 1981.

Insertion loss (IL) is the value of A at the filters center frequency f 0.

9. W. A. Davis, Radio and Microwave Engineering (EE4605 Class

Notes), Blacksburg, VA: Virginia Polytechnic Inst. State Univ.,
1996.

IL = A( f 0 )

(37)

10. U. Rohde, Digital PLL Frequency Synthesizers Theory and Design,

Englewood Cliffs, NJ: Prentice-Hall, 1983.

Manufacturers normally provide plots of A versus f. A variety

of bandwidths are often specified in addition to the expected
3 dB value. The shape factor of a filter is the ratio of one of
these larger bandwidths (for example, the 60 dB bandwidth)
to the 3 dB bandwidth. An ideal brick wall filter would have
a shape factor of 1.
The phase response ( f) of a filter is also important, but it
is plotted far less frequently. Ideally, ( f) should be a linear
function of frequency. In that case, the spectral components
of a complex waveform would pass through the filter without
changing their relative phases. Phase distortion is particularly important in analog FM and in digital applications.
Phase distortion is measured by group delay, T, which has
units of time and is given by

11. S. Maas, Mixers for wireless applications, in L. Larson (ed.), RF

and Microwave Circuit Design for Wireless Communications, Norwood, MA: Artech House, 1996.

T=

2 f

(38)

Relating receiver performance to filter group delays usually

requires computer simulation. No simple formulas are
available.
Some mixers (diode mixers in particular) are sensitive to
the impedance presented at the IF port at frequencies outside
of the passband. Some crystal filters are particularly troubling in this regard. Diplexer circuits are available to isolate
the mixer from the filters impedance variations. See Ref. 2
for a further discussion of this issue.
Demodulators. The choice of demodulator for a given receiver design depends on the modulation that is to be received. For a given application, demodulators differ in fidelity,
dynamic range, and input and output signal levels.
RF Integrated Circuits for UHF Receivers. The level of integration available in receivers and receiver subsystems is increasing rapidly, particularly for consumer applications. For
further information, see Refs. 1214.
BIBLIOGRAPHY
1. F. Jay (ed.), IEEE Standard Dictionary of Electrical and Electronics Terms, 3rd ed., New York: IEEE Press, 1984.
2. S. Maus, Microwave Mixers, 2nd ed., Norwood, MA: Artech
House, 1993.
3. D. Cheadle, Measure noise power with your power meter, in RF
Signal Processing Components, Palo Alto, CA: Watkins-Johnson
Company, 1980.
4. Fundamentals of RF and Microwave Noise Figure Measurements,
Application Note 57-1. Palo Alto, CA: Hewlett-Packard, 1983.
5. U. Rohde, Microwave and Wireless Synthesizers: Theory and Design, New York: Wiley, 1997.
6. W. Robins, Phase Noise in Signal Sources, London: Peregrinus,
1984.

12. B. Razavi, RF Microelectronics, Upper Saddle River, NJ: PrenticeHall, 1998.

13. T. H. Lee, The Design of CMOS Radio Frequency Circuits, New
York: Cambridge University Press, 1998.
14. A. Abadi and P. Gray, Integrated Circuits for Wireless Communications, Piscataway, NJ: IEEE Press, 1998.

CHARLES W. BOSTIAN
DENNIS G. SWEENEY
Virginia Tech

ULTRASHORT PULSE TECHNOLOGY. See PULSE

COMPRESSION.

VARIABLE-FREQUENCY OSCILLATORS
OSCILLATORS, VARIABLE FREQUENCY
An oscillator is dened as anything that swings back and
forth like a pendulum (vibrates) or travels back and forth
between two points. An electronic oscillator is a device used
for producing alternating current (e.g., a radio frequency
or audio-frequency generator). Frequency is the number of
times that a periodic function repeats the same sequence
of values during a unit of time or the number of complete
oscillations of a wave per second.
Oscillators are abundant all around us: light, sound, the
rotation of the earth, electric ac power, heart beats, musical instruments, motors, microprocessor clocks, and so on.
Some of these oscillatory systems have variable frequency,
and some have xed frequency. We will rst describe all the
different types of electronic oscillators to appreciate what
determines their operating frequency and how it can be
varied.

Figure 1. Simple mechanical damped oscillators.

Figure 2. A windmill produces oscillations of varying frequency

in response to the wind force.

MECHANICAL EXAMPLES
TYPES OF OSCILLATORS
There are two basic kinds of oscillators: sinusoidal and relaxation. The mechanisms that produce these two types of
oscillations are different, as are the required conditions for
oscillation. RC- and LC-tuned circuits represent sinusoidal
oscillations. Their oscillations are continuous and relatively sinusoidal. Relaxation oscillators are represented by
multivibrators and ring oscillators. Their oscillations are
discontinuous and nonsinusoidal.
Sinusoidal oscillations are created when energy stored
in one form is allowed to change uniformly into another
form, going back and forth between the two without stopping. Because energy may be transferred between states
with minimum loss, some sinusoidal oscillators can be energy efcient because only small amounts of energy need to
be supplied externally to keep the action going. This type
of oscillator is associated with linear systems. Sinusoidal
oscillators are of two types: feedback and negative resistance.
Relaxation oscillations are characterized by the sequential accumulation and release of energy in one or several
storage elements. Energy is accumulated up to a certain
level (threshold) and then quickly released (usually dissipated as heat), and then another element (or the same
element) in the system begins to accumulate energy until the cycle repeats. The action exhibits positive feedback
during reset or relaxation, reinforcing itself and occurring
rapidly. This type of oscillator is associated with nonlinear systems. Because all the accumulated energy is periodically dissipated, relaxation oscillators are very energy
inefcient.
This article does not cover chaotic oscillators. Chaotic
oscillators do not have a periodic sequence of events that repeat in a unit of time. Related to nonlinear systems, chaotic
oscillators occur for example in turbulent ows of liquids
or in noise-like random signals generated in certain electronic systems.

The most elementary types of mechanical oscillators are

the spring and mass and the pendulum, as shown in Fig.
1. In the spring and mass, the energy is alternately changing from the spring to the potential and kinetic energy in
the mass. At the top of its swing, all the energy is potential
energy related to the elevation of the mass. Midway down,
there is kinetic, potential, and spring energy. The pendulum is a well-known example of the oscillation between
potential and kinetic energies.
Both systems will slow down because of the friction in
the air. The spring also dissipates energy because of the internal friction of its metal grains. The pendulum has friction at the hinge. Rather than being strictly oscillators,
these mechanical arrangements are examples of damped
oscillators. An energy input is necessary to compensate for
the losses and to deliver power to outside loads, for example to synchronize other mechanical devices.
The windmill is an interesting example of an oscillator (Fig. 2). Its frequency is proportional to the drive level
(e.g., the wind strength). The amplitude of the oscillation
is, however, xed. This is the opposite of electronic oscillators, which increase their signal swing in response to more
supplied power. However, if we think of the windmill as
driving a load, like an ac voltage generator, then there is a
relationship between its energy output and the available
wind energy. The paddles seem to rotate with the same
magnitude, but they deliver changing amounts of energy
at varying frequencies.
An example of an oscillatory system that is not sinusoidal, like the pendulum or the windmill, is shown in Fig.
3. The water drops accumulate in the glass until the surface tension can no longer hold any more liquid, the water
spills over the edge, and the cycle repeats. It is called a
relaxation oscillator because the energy accumulates in a
certain form up to the level that causes the system to relax
and let go of the accumulation; then the system resets and
restarts the sequence.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright 2007 John Wiley & Sons, Inc.

Oscillators, Variable Frequency

Figure 3. Mechanical example of a relaxation oscillator.

Figure 5. An oscillator viewed as a feedback system in which the
output provides its own input.

Figure 4. Electrical damped oscillatory systems: series and parallel resonators with loss.

ELECTRICAL RESONATORS
The electrical equivalents of the mechanical resonator are
the series and parallel resonant tanks shown in Fig. 4.
They are composed ideally of just an inductor and a capacitor, but there are always losses that are modeled by resistors. The energy is alternatively stored in the capacitor (as
an electric eld of potential energy) and in the inductor (as
magnetic energy). When the capacitor is at full charge, the
voltage across the parallel arrangement is at its peak; and
when the current through the inductor is at its peak, then
the voltage across the tank is zero.
Other popular resonators are transmission line, Dielectric, Yttrium-Iron-Garnet (YIG), Crystal, and Surface
Acoustic Wave (SAW). Resonant tank equivalent circuits
at different frequencies of operation can represent all of
these.

SINUSOIDAL OSCILLATORS
Feedback Oscillators
A general way of thinking about an oscillator is in terms
of an amplier that feeds its output back to its own input
(Fig. 5). The feedback is controlled by a resonator or a delay
element in such a way that the desired frequency and amplitude of oscillation are achieved. Note that the resonator
or delay box is still indicated as a two-terminal box with
another two-terminal amplifying box connected across it.
This could be viewed as a negative resistance oscillator, as
will be discussed later.
Conditions For Oscillation

QUALITY FACTOR (Q)

The Q of a resonator is a useful number to calculate. It is
dened as 2 times the ratio of the energy stored in the
system to the energy dissipated per cycle (1). It turns out
that Q has two other useful interpretations. It is a measure
of how many cycles it takes a damped oscillatory system to
decay (2), and it denes the 3 dB bandwidth of a secondorder resonator (3). Q also describes how rapidly the phase
changes with frequency near the resonant frequency, indicating how little the frequency will shift with changes that
affect a delay in an oscillator loop (4). Finally, for a series
resonant circuit, Q is the ratio of impedance in L or C divided by R (5); for the parallel resonant circuit, Q is the
inverse of this equation.

Normally, for oscillation to start, the active device provides

more energy than is being dissipated in the resonator. This
causes the amplitude of the oscillation to grow until it is
limited by changes in the active device that reduce its gain.
The losses in a system may be linearly related to its amplitude over a limited region, but they grow more rapidly
(nonlinearly) over an extended region of amplitude, until
they eventually hard limit the amplitude (e.g., when a barrier is reached).
The requirements for oscillation are that the amplitude
of the signal being fed back be large enough to produce
an output that can reproduce the feedback (greater than
unity loop gain) and that the relative phase between the
input and the fed-back input be near zero (so the feedback
reinforces the output). More simply said, the one-way trip
around the loop needs to have gain greater than one and
zero phase. However, these conditions should not be met
at dc; otherwise, the oscillator will latch into a limit state,

Oscillators, Variable Frequency

Figure 6. RC delay oscillator. For an inverting amplier, there

must be 180 of phase shift in the RC feedback path.

and no ac oscillation will develop. Additionally, stable oscillations develop only if disturbances in amplitude or phase
cause the oscillator to respond by moving back to the unstable point. Finally, reliable oscillators need to have only
one frequency at which the conditions for oscillation are
met; otherwise, frequency jumps could occur.
Rc Delay Oscillator (Phase Shift Oscillator)
The circuit shown in Fig. 6 is known as the RC (resistorcapacitor) delay oscillator. Three stages of RC delay are
used in the feedback path. If the amplier is inverting,
then the RC network needs to produce 180 of phase shift
at the frequency of oscillation. Stated differently, the oscillation will occur at that frequency at which the feedback
has a phase delay of 180 and the gain is greater than one.
Other possibilities to realize the phase delays are to RL
(resistor-inductor) delay or lossy transmission line delay.
A transmission line is just a distributed RLC delay element. LC delay elements and lossless transmission lines
will be covered next.
LC-Tuned Oscillators
When a tuned circuit is used to dene the oscillation frequency, it is desirable to preserve its frequency selective
properties Q. To prevent loading a resonator by the input
of an amplier, a transformer is necessary. Several types
of impedance transformation are possible by using coupled inductors, inductive division, or capacitive division.
Another possibility is to use another amplier as a buffer:
the input impedance of the buffer is high, and the loading
on the resonator is light.
Figure 7 shows two ways of looking at how an amplier
can be connected across a tank circuit using capacitive division of voltage. The arrangement shown on the right is
known as the Colpitts circuit. Capacitors C1 and C2 in series form part of the resonator, and the input loading by the
amplier is reduced by their ratio. The circuit on the left
uses the capacitors as a way of getting 180 of phase shift at
resonance, while internally completing the loop with an additional 180 resulting from signal inversion. However, the
two capacitors are still connected in series to each other
and across the inductor, and voltage division takes place
across this tank. The advantage of capacitive division over
inductive division is that it is easier to realize in an integrated circuit. Split inductors or transformers are more

complicated to build than simple inductors.

The arrangements shown in Fig. 8 are known as Hartley and Armstrong oscillators, respectively. The feedback in
the Hartley circuit is provided by inductive division, using
two inductors or a single inductor with a tap connection.
Inductive division, using two inductors or a single inductor
with a tap connection, provides the feedback in the Hartley circuit. The input loading is therefore decreased. The
Armstrong circuit uses two inductors, L1 and L2 , with inductive coupling between them. This may be attractive if
the objective is to keep the input and output biases isolated
from each other. Moreover, the amount of coupling between
the coils can be varied without changing the values of the
inductors.
A single transistor implementation of the capacitively
divided tank circuit is depicted in Fig. 9. This circuit is
simple because the base bias is provided through the inductor. The value of the collector load resistor needs to be
large enough to prevent decreasing the Q of the resonant
circuit. The coil and the series connection of the two capacitors make up the resonant circuit. This arrangement can be
modied by placing a capacitor in series with the coil (and
providing base bias). The series resonant frequency of the
coil and the added capacitor can dominate the oscillation
frequency, making the circuit less sensitive to variations in
the transistor and in the other two capacitors. This modication is known as the Clapp oscillator.
The dc-coupled LC oscillator in Fig. 10 is based on a differential amplier. It has a single-ended tank and a singleended output. Its output is directly coupled to its noninverting input, and therefore the feedback needs to provide
0 of phase delay because 360 would be impossible with the
circuit shown. At resonance, the LC tank presents a purely
resistive load to the collector output, and therefore it has
no phase delay. Any internal delay through the device will
need to be canceled by adjusting the oscillation frequency
slightly out of resonance. The frequency of this oscillator
would normally be controlled by using a variable capacitor.
Using a variable capacitor would normally control the frequency of this oscillator. A small change in frequency can
also be obtained by changing the bias on the differential
amplier.
Tuned oscillators may also use transmission lines, cavities, dielectric resonators, crystals, or YIG resonators to determine their operating frequency. These resonators have
equivalent circuits of very high Q. For example, because of
the interaction between voltage and mechanical resonance,
piezoelectric quartz crystals are much more stable and of
higher Q than LC resonators.
Use of Varactors
Varactors are used to vary the frequency of resonant LC
circuits (Fig. 11). The combined symbol of a capacitor with
a diode arrow is used to indicate that they are diodes that
vary their junction depletion capacitance. This happens
in response to a change in the reverse voltage applied
across them. The types of varactor diodes that have the
most change of capacitance with voltage are named hyperabrupt. The junction between the n-region and the pregion is made very sharp, and the doping concentrations

Oscillators, Variable Frequency

Figure 7. Oscillators with capacitive division of voltage, also

known as Colpitts arrangements.

Figure 8. Inductive division of voltage in Armstrong and Hartley oscillators.

Figure 9. Single-transistor implementation of a capacitive division oscillator.

are very different. This causes the depletion layer on the

lightly doped side to move considerably with applied voltage. Since varactors also have loss, they must be selected
or designed to minimize the degradation of the resonators
Q.
The drawing on the left side of Fig. 11 shows a common
back-to-back connection of two varactors. Because the voltage that develops in a tank circuit is large, this arrangement offers some cancellation of the variation of the capacitance as a function of the tank voltage. Even order distortion products are canceled, and the voltage at which the
diodes would conduct is increased. The simpler arrangement on the right requires a capacitor to ac couple the varactor to the inductor so that the bias voltage is not shorted
out by the inductor. This circuit is adequate when the signal
level is small or when there is no concern about generating
harmonics of the tanks fundamental frequency.
Negative Resistance Oscillators
Negative resistance oscillators also can be viewed as oneport oscillators, as opposed to the two-port oscillators used

Figure 10. Differential amplier LC-tuned oscillator with singleended output. The emitter follower provides dc-coupled impedance
transformation.

in feedback arrangements. Some electronic devices (e.g.,

microwave diodes) are two-terminal devices and can be operated only as a one-port device. Therefore, negative resistance oscillator analysis is the most general in that it
includes two- and three-terminal (or more) electronic devices.
To compensate for the losses in a resonant circuit, an
active circuit needs to supply power to cancel them. This
can be thought of as paralleling the resonator with a negative resistor (Fig. 12). It turns out that most oscillator
arrangements can be simplied to this type of model, and
an equivalent value for negative R can be calculated. If the
negative resistance black box is a two-port, which is common, then the other port can be tuned to deliver power to
a load.
One possible single-transistor version of a negative resistance oscillator is shown in Fig. 13. The capacitor from
emitter to ground makes the input impedance at the base

Oscillators, Variable Frequency

Figure 11. Resonator arrangements using varactor diodes to

tune the center frequency.

Figure 12. Negative resistance compensates for the losses in a

parallel tank resonator.

Figure 14. A ring oscillator consists of a number of buffers connected in a loop.

random after powering up the circuit.

The frequency of a ring oscillator can be varied in several
ways. One popular way is to change the internal delay of
each buffer by adjusting the amount of current available
to charge and discharge the circuit capacitances. Another
way is to vary the amount of load presented at the output
of each buffer.
Astable Multivibrators

Figure 13. Negative resistance oscillator with series resonant

tuning.

partly negative real and partly capacitive. The inductor at

the base can be either series or parallel resonated with the
input capacitor and with other tuning capacitors or varactors. Note that one could use the collector to deliver power
to a load, instead of connecting it to the power supply.
RELAXATION OSCILLATORS
Ring Oscillators
Ring oscillators are a popular topology for variable frequency oscillators used in integrated circuits because they
have broad tuning range and require no resonators. They
consist of a number of ampliers or delay stages that may
be inverting or noninverting, connected in such a way that
an odd number of inversions exist around the loop (Fig. 14).
The loop is therefore never happy, and the result is that
an edge propagates around the loop. Loops with as little
as two buffers are possible, but for large number of stages
it is customary to choose prime numbers to prevent the occurrence of multiple modes of oscillation. For example, if
we used six buffers, we could have three edges running
around the loop, with the result that the frequency would
sometimes be three times higher. This would happen at

Figure 15 shows the main features of an astable multivibrator. It consists of an amplier with a positive feedback connection that causes hysteresis in the multivibrator. When one of the inputs causes the output to swing in
one direction, the positive feedback changes the switching
threshold, reinforcing the input so that there is no hesitation if the input begins to change back. It behaves like a
comparator with a moving input threshold. This prevents
noisy outputs when the inputs are changing too slowly or
when they sit too close to the threshold. In the case of this
oscillator, the hysteresis allows the operation of the circuit,
which would not occur otherwise. The R and C connected
to the inverting input cause this point to vary exponentially up and down around the hysteresis voltage region.
Multivibrators have a broad tuning range.
The astable mutivibrator in Fig. 16 is a popular oscillator circuit that is often built in university engineering laboratories and by hobbyists. It is nonlinear because the two
transistors take turns being on and off, without spending
much time midway. When transistor Q1 turns on, its collector pulls the base of Q2 down, through C2 , keeping it off.
Resistor R3 will in time recharge C2 and turn Q2 back on.
When this happens, there is positive feedback. As Q2 turns
on, it will turn Q1 off, and as the collector of Q1 goes high, it
will reinforce Q2 being on. Next, R2 will begin to recharge
C1 until Q1 is turned back on. The RC time constants (R2 C1
and R3 C2 ) need not be the same, and nonsymmetrical oscillations can be designed with this circuit. For example, a
narrow pulse can be produced. The frequency of oscillation
can be varied by changing the value of the resistors (most

Oscillators, Variable Frequency

Figure 17. Another multivibrator or astable oscillator that needs

only one capacitor.
Figure 15. Diagram of a bistable oscillator.

Figure 16. Example of common multivibrator. The system has

two stable points: when Q1 is on and when Q1 is off (and Q2 is
therefore on).

commonly R2 and R3 ) or by switching different values for

the capacitors and using the resistors for ne adjustment.
Other possibilities are changing the power supply voltage
or the value of the collector load resistors, which are typically smaller than R2 and R3 .
Another popular astable multivibrator circuit has a single timing capacitor (Fig. 17). Its frequency is adjusted
by changing the value of the current sources. Transistors
Q1 and Q2 form a cross-coupled pair through Q3 and Q4
that acts like an emitter-follower buffer. In this conguration, when one of the two bottom transistors is on, it forces
the other transistor off and vice versa, in a latching arrangement with large hysteresis. For example, Q1 being
on forces Q2 off, which reinforces the state of Q1 being on.
The transistor that is on must supply current to both current sources I and therefore will begin to charge capacitor
C until the voltage at its own emitter rises and turns itself off. This happens quickly. The other transistor begins
to charge the capacitor in the opposite direction, and the
cycle repeats itself. The frequency of oscillation is linearly
proportional to the value of the current in the sources because the capacitor is charged linearly by current and not

through a resistor. The waveforms at the emitters of Q1

and Q2 are linear sawtooth waves.
The Schmitt-trigger oscillator shown in Fig. 18 is also
known as the grounded-timing-capacitor oscillator. The differential amplier and two emitter-followers on the right
are connected in positive feedback. When the transistor directly on top of the timing capacitor is turned on, it quickly
charges it to near the power supply voltage and forces the
trigger to switch states. This turns off the top transistor, and the current source begins to discharge the capacitor linearly. When the capacitor voltage is low enough, the
trigger switches, and the process repeats. The output waveforms of this oscillator consist of narrow complementary
pulses, whereas the voltage across the timing capacitor is
a linear sawtooth waveform.

Voltage-To-Frequency Converters
Voltage-to-frequency converter circuits are used not so
much to produce oscillations but rather to measure voltages precisely. They achieve linear transfer characteristics
from voltage to frequency and allow a frequency counter
(a digital circuit of high repeatability) to measure the input voltage level. However, as an example of a variablefrequency oscillator, this is the most linear of all.
In the schematic drawn in Fig. 19, the input voltage
Vin causes current to ow into the precision integrator circuit containing or including Ci . The comparator with hysteresis periodically switches capacitor Cf from the voltage
reference Vref to the input terminal of the integrator, discharging it fully. This achieves the transfer of a measure of
charge in a way that is independent of the waveform driving the switch, as long as capacitor Cf is given enough time
to discharge fully. Note that the polarity of Vref needs to be
opposite that of Vin , or the capacitor needs to be discharged
inverted. This can be done by connecting the top side of the
capacitor to the input, and the switch to the bottom side.

Oscillators, Variable Frequency

Figure 18. Detailed schematic of

a Schmitt-trigger oscillator with
the single timing capacitor tied to
ground.

Figure 19. Voltage-to-frequency converters are used to measure voltages.

PROGRAMMABILITY DESIGN STYLES: HOW TO VARY

THE FREQUENCY
Most variable-frequency oscillators are voltage controlled
(VCOs). This is a desirable feature because producing a
variable voltage is usually easier than producing a variable current. Even if the frequency control is by variable
capacitance, varactors that require a control voltage can
be used. In cases where the control variable is naturally
current, as in relaxation oscillators or in some ring oscillators, a voltage-to-current converter can be added to make
the circuit a VCO .
For sinusoidal oscillators, the presence of a resonant
circuit imposes a limited tuning range. Frequency change
in these circuits usually uses variable capacitorsor variable resistors in an RC oscillator. In the past, mechanically
tuned air dielectric capacitors and even variable inductors
were used. Modern designs prefer using varactor diodes.
However, the tuning range is limited to less than an octave
in a resonant circuit that uses variable components.
To increase the tuning range, different component values can be switched around for different ranges. Usually
the inductance is switched, while the capacitance is continuously varied. Mechanical switches have been used in
the past, but today switching diodes are preferred because
of their small size, lower cost, and higher frequency perfor-

mance (less parasitics). A popular switching diode is known

as pin. It consists of three layers of p-type (undoped or intrinsic) and n-type semiconductors. When no current ows
through the pin diode, the i-layer acts like a thick dielectric, and the diodes capacitance is low. When current is
forced through the diode, it exhibits low series resistance.
It therefore approximates an ideal switch.
Although their frequency can be varied only over a very
small range, crystal oscillators can change frequencies dramatically by switching the crystal element. In some radios,
channels are changed by switching crystal values in several oscillators, and their outputs are multiplied or mixed
together to produce the desired frequency.
Relaxation and ring oscillators have wide tuning ranges
in spite of their poor stability and noise performance. It
is easy to tune them over a 10:1 ratio, and with careful
circuit design, more than two decades of frequency control
are possible. Voltage-to-frequency converters are also easy
to tune over broad ranges, although they are relatively slow
oscillators.
Table 1 highlights the features of the different oscillators covered. Depending on speed, tuning range, and
method of tuning required, a variable-frequency oscillator that meets the required needs can be found. Of course,
no single oscillator can simultaneously satisfy all possible
needs, and other variables like available materials and cost

Oscillators, Variable Frequency

Figure 20. Fully differential LC oscillator with delay tuning.

need to be evaluated.

ADVANCED CIRCUITS
Further examples of more sophisticated circuits will be
described shortly. The rst three examples are differential versions of previously discussed arrangements. Their
advantages in rejecting power supply noise and in reducing even order distortion more than offset the added complexity. Particularly in integrated circuit design, trading
number of components for enhanced response is always a
winning strategy. The last circuit shown is an elegant arrangement for a crystal oscillator that has improved output
buffering.
A differential LC oscillator with delay tuning has frequency control by varying the delay of the feedback signal (Fig. 20). This works well for low Q tank circuits that
are realized in monolithic implementations. The outputs
are directly coupled to the inputs without inversion. The

resonant circuit is composed of the series sum of the two

inductors and the capacitance across them. The two collectors connected to the tank are operating 180 out of phase.
The current at the bottom of the two emitter-followers, that
connect to the tank inductors followers, which connect to
the tank inductors, is varied to change the oscillation frequency. This is done by using another differential amplier with two output transistors. Less current results in
more delay, which the loop compensates for by lowering the
frequency of oscillation. Because of large emitter degeneration, the control voltage produces a near linear change
in the current going into the emitter-followers. For a tank
with a Q of less than 10, this circuit achieves a tuning range
of over 20% of the central frequency. The inductor is often
a planar spiral layout of thin metal sitting on a lightly conductive substrate. The series resistive loss in the inductor
and the eld-absorbing loss in the substrate dominate the
Q of the tank.
A differential version of the negative resistance oscillators is shown in Fig. 21. During operation, transistors
Q1 and Q2 alternatively turn on and off. The inductor series resonates with the capacitor and with the capacitive
input impedance of the two transistors. They present a
negative real input impedance when they are on; however,
they alternatively turn off, and the real part of the input
impedance goes from negative to positive. This simple arrangement provides differential outputs that are useful in
several applications in integrated circuit design.
A high-speed, two-stage ring oscillator is depicted in
Fig. 22. The buffers consist of slow and fast ampliers connected in parallel and sitting on top of a differential amplier. The control voltage allows us to interpolate between
slow and fast, by splitting the amount of current available
at the current source. The differential amplier has emitter
degeneration resistors to linearize the current partitioning as a function of the differential voltage. Two emitter-

Oscillators, Variable Frequency

Figure 21. Differential version of negative resistance oscillator.

followers buffer the outputs between stages and improve

jitter by improving the voltage transition time. Both the
control and the input/output signals are fully differential,
resulting in a circuit that is very tolerant to common mode
disturbances. Fully differential oscillators do not depend
on reference voltage generators or intrinsic device voltage
thresholds to set their operating points. Furthermore, they
give us complementary outputs, at twice the differential
voltage swing compared to single-ended implementations.
The crystal oscillator with buffered output in Fig. 23
uses two transistors, connected as emitter-followers, in a
Darlington arrangement. The input bias current is small,
and the resistive loading on the crystal is light. Capacitors
C1 and C2 connected across the Darlington pair make the

Figure 23. Crystal oscillator based on Darlington pair used in

negative resistance circuit.

input impedance have a negative real part. This arrangement can therefore be viewed as a negative resistance or
one-port oscillator. The oscillation amplitude will be limited by the voltage increase at the emitter of transistor Q2 ,
which debiases the transistor and limits the maximum current owing through it. However, the amplitude at the base
of transistor Q1 should not be so large that it saturates it.
The output is taken at the collector of transistor Q2 , and
the load is elegantly isolated from the core of the oscillator.

Figure 22. High-speed, two-stage ring oscillator. The frequency

is controlled by interpolating the delay of the buffer stages between fast and slow paths.

10

Oscillators, Variable Frequency

SUMMARY AND SUGGESTIONS FOR FUTURE STUDY

The design of variable-frequency oscillators requires
knowledge of the main topologies, the limits of frequency
selective arrangements, the conditions for reliable oscillation, and the available means of tuning, to name the
main variables. This article has tried to organize the
types of oscillators into two main groupssinusoidal and
relaxationand has described how their frequencies are
changed. A good understanding of a system requires a
model of the system. A sinusoidal oscillator can be modeled in two different ways: using feedback and using negative resistance. Relaxation oscillators operating at high
frequency can sometimes be modeled in the same way, but
in general they are described by their states and their
time constants. Simple equivalent circuits and equations
for the resonators were presented, attempting to highlight
the most intuitive representations.
The variety of oscillators in existence offers many
choices, but it also emphasizes the fact that there are unexplored combinations. Particularly because so much of society is inuenced by the advances in electronic engineering,
and especially integrated circuit engineering, the design of
smaller, faster, and cheaper circuits is a very important
activity. Variable-frequency oscillators of improved quality
are needed today in telecommunications, data transmission, and instrumentation. The components available to
design oscillators are constantly undergoing change, most
particularly in integrated circuits.
BIBLIOGRAPHY
1. A. P. French Vibrations and Waves, New York: Norton, 1971.
2. J. Williams (ed.) Analog Circuit Design: Art, Science and Personalities, Stoneham, MA: Butterworth-Heinemann, 1991.
3. The American Radio Relay League, The ARRL Handbook
for Radio Amateurs, Newington, CT: American Radio Relay
League, 1995.
4. J. J. DeFrance Communications Electronics Circuits, 2nd ed.,
Corte Madera, CA: Rinehart Press, 1972.
5. L. E. Larson (ed.) RF and Microwave Circuit Design for Wireless Communications, Norwood, MA: Artech House, 1996.
6. J. Millman Microelectronics: Digital and Analog Circuits and
Systems, New York: McGraw-Hill, 1979.
7. G. Gonzalez Microwave Transistor Ampliers, Englewood
Cliffs, NJ: Prentice-Hall, 1984.
8. G. D. Vendelin Design of Ampliers and Oscillators by the SParameter Method, New York: Wiley, 1982.
9. M. J. Howes D. V. Morgan (eds.) Microwave Devices, New York:
Wiley, 1976.
10. R. Meyer Advanced Integrated Circuits for Communications,
Univ. California, Berkeley, Course ECE242 Notes, 1994.
11. B. Razavi RF Microelectronics, Upper Saddle River, NJ:
Prentice-Hall, 1998.
12. U. L. Rohde J. C. Whitaker T. T. Bucher Communications Receivers: Principles and Design, New York: McGraw-Hill, 1996.
GUTIERREZ
GERMAN

IC Design Consultant, Carlsbad,

California

MULTIPLIERS, ANALOG CMOS

691

xy

xy

y
x

xy

( )2

x 2 + 2xy + y2

x +y

( )2

x y

( )2

x y

( )2

4xy

xy

x +y

x 2 2xy + y2
8xy

x 2 + 2xy + y2
x 2 2xy + y2

y
(a)

(b)

Figure 1. Pictorial explanations of cancellation method used in MOS

multipliers. (a) Using single-quadrant multipliers and (b) using
square devices correspond to Eqs. (1) and (2) respectively. X and Y
are not shown in the figures for simplicity.

OPERATION PRINCIPLES
Despite many reported MOS multipliers, only two cancellation methods for the four-quadrant multiplication are known.
A fully differential configuration is necessary in a sound multiplier topology to achieve complete cancellation. As a multiplier has two inputs, there are four combinations of two differential signals, i.e., (x, y), (x, y), (x, y), and (x, y). Then,
the multiplication can be obtained based on the following
equalities.
[(X + x)(Y + y) + (X x)(Y y)]

(1)

[(X x)(Y + y) + (X + x)(Y y)] = 4xy

or

[{(X + x) + (Y + y)}2 + {(X x) + (Y y)}2 ]

MULTIPLIERS, ANALOG CMOS

Multipliers produce linear products of two signals x and y
yielding an output z Kxy, where K is a multiplication constant with suitable dimension. Historically, a complete analog
multiplier was invented by Gilbert (1,2) using BJT. Because
digital technology dominates in modern electronics, analog
circuits are required to share the same standard digital
CMOS process for low cost fabrication. Thus, the popular BJT
Gilbert Cell is not suitable in an MOS digital process, and
designers must address low power supply voltage requirements. The Gilbert cell is implemented using lateral BJT in
the CMOS process in Ref. 3. The MOS version of Gilbert multipliers is reported in Ref. 4. Because its linearity is poor, several modified versions including linearization schemes (46),
folded structures (68), and active attenuators (9) have been
reported. However, none of the above multipliers has been
adopted in any commercial product. Many other MOS multipliers that are not based on Gilbert cell structure are reported
in the literature. MOS multipliers can be categorized into two
major groups based on its MOS operating region, linear (10
25) and saturation (39,2648). Beside above major categories multipliers operating in the weak inversion region (49
51), dynamic multipliers for sampled signal system or neural
networks (5257), has been reported. Here, only the MOS
multiplier architectures that have practical performance are
discussed.

(2)

[{(X x) + (Y + y)}2 + {(X + x) + (Y y)}2 ] = 8xy

X and Y are constant terms that include a common mode signal, and any constant terms in device characteristics. Figure
1 depicts an explanation of the above equations. The simple
MOS transistor model expressed for its linear and saturation
regions, as




2
Vds
Vds
Vds = K VgsVds VtVds
Id = K Vgs Vt
2
2
(3)

for |Vgs | > |Vt |, |Vds | < |Vgs Vt |

Id =

K
K 2
[Vgs Vt ]2 =
[V 2VgsVt Vt2 ]
2
2 gs
for |Vgs | > |Vt |, |Vds | > |Vgs Vt |
io

Y+ y

M2

io
Y+ y

Q2

X+ x

(a)

(4)

M2
+

M1

X+ x

(b)

io

A
Y+ y

M1

X+ x

M1

(c)

Figure 2. Programmable transconductor (one-quadrant multiplier).

M1 is operating in linear region while M2 is operating in saturation
region.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

692

MULTIPLIERS, ANALOG CMOS

X+ x
I1

Io1

Zf
+

Vo
+

I2
X x

I1

Io2

I2

Y+ y

X+ x

Y+y

X x

Zf

X+ x

Y y

X x

(a)

Figure 5. Four cross coupled FETs with gate and source signal application.

(b)

Figure 3. Four-quadrant multipliers with two programmable transconductors.

where K oCoxW/L and Vt are the conventional notation for

the transconductance parameter and the threshold voltage of
the MOS transistor, respectively. The terms VgsVds in Eq. (3),
2
or Vgs
in Eq. (4) are commonly used to implement Eqs. (1) and
(2), respectively.
Using Vgs Vds in Linear Region
First we introduce a programmable linear transconductor and
show how it can be used to implement a multiplier. In Fig. 2,
transistor M1 is forced to operate in the linear region while
M2 operates in saturation with proper bias voltage, X and Y.
In Fig. 2(a) (58), vds;M1 is controlled by y through the source
follower M2 when the transconductance of the source follower

is much larger than that of M1. The source follower can be

replaced with the BJT emitter follower (59) [Fig. 2(b)] or the
gain enhanced MOS source follower (6062).
A multiplier is realized by combining two programmable
transconductors as shown in Fig. 3(a). The output current is
obtained from Eq. (3) where X x vgs and y vds.

y

I1 = K1 X + x Vt
y
2
(5)


y

I2 = K1 X x Vt
y
2
The difference of output currents yields
Io = I1 I2 = 2K1 xy

Io1
I1

Io1

I2
I3

I1
+

I2 I3

Y y
M2

X+ x

M1

M1

I4
X x

X+x

(b)

(a)

Io1

Io2

Y+ y

Y+ y
M1

Y y

X+ x

Figure 4. Fully-differential four-quadrant multipliers using VgsVds term.

I4

Y+ y
Vo

Y y

Io2

Io2

Y+ y

(6)

In Fig. 3(a), the op amp keeps the sources of the FETs virtually grounded. This approach has been used in conjunction
with switched-capacitor circuits to implement a weighted-sum

Zf
X+ x

X x

Y+ y

M1

X x
(c)

X+ x

MULTIPLIERS, ANALOG CMOS

Io1

Io2

Io1

693

Io2

X+ x
Y y

X x

X+ x

Y+ y
X x

R
R
Y y

Vss

Y
(a)

(b)

Io1

Io1

Vdd

Io2

Io2

Vdd

X+x

X+ x
M1

M1

Y y

Y+ y

1:k

1:k

Y y

X x

1:k

X x

(c)

1:k

Y+y

(d)
Figure 6. Source signal injection methods for multiplier using v2gs term.

or a weighted-integrator (912). The configuration in Fig. 3(b)

uses MOS source followers and achieves multiplication as in
Eq. (5) except y in Eq. (5) is replaced with Y y Vt. This
configuration is reported in (1317) with gain enhanced
source follower.
A fully differential extension shown in Fig. 4 achieves complete common mode and power supply dependency cancellation and yields
Io = Io1 Io2 = (I1 + I3 ) (I2 + I4 ) = 4K1 xy

(7)

The variations of Fig. 4(a) are reported in Refs. 1821 and

the circuit in Fig. 4(b) is reported in Ref. 22. The Vds of M1,
which is operating in linear region, also can be applied by two
source followers as shown in Fig. 4(c) (23,24).
Using V gs2 with Gate and Source Injection
A four-quadrant multiplier based on the topology in Fig. 1(b)
can be realized by four cross-coupled transistors as shown in
Fig. 5 whose output current, Io, is
Io = Io1 Io2 = 4Kxy

or
Vo = Zf Io = 4K1 Zf xy

Io1

(8)

Io2

X x
X+ x
+
Y y

+
Y+ y

Figure 7. Multiplier that utilizes V2gs using voltage adder. represents voltage adder circuit.

(9)

Varieties of source signal application methods are reported in

the literature. Figure 6(a) uses an op-amp (26), (b) uses a linear differential amplifier (27), and (c) uses source followers. A
separate source follower, as shown in Fig. 6(d) (28), can be
provided to each transistor in cross-coupled transistors. A
gain-enhanced source follower (2934) or a BJT buffer (35)
can be used to apply the source signal. This type is the most
widely implemented multiplier structure.
Using V gs2 with Voltage Adder
2
Another way to utilize the V gs
term of MOS transistor operating in saturation region is to apply the sum or difference
of two input signals to the gate of MOS transistor while the
source voltage is fixed, as shown in Fig. 7(a). This configuration is reported in (3638) using a capacitive adder, in Ref.
39 using resistive adder, in Refs. 4043 using an active adder,

MULTIPLIERS, ANALOG CMOS

2.5

2.5

2
THD (%)

THD (%)

694

1.5
1
0.5
0

Fig.
Fig.
Fig.
Fig.
Fig.

1.5
1

4(b)
4(c)
6(b)
6(c)
6(d)

0.5

0.5

1
2y (V)

1.5

0.5

(a)

1
2x (V)

1.5

(b)

Figure 8. Simulated total harmonic distortion for W/L 10 m/10 m for all transistor. The X
and Y are set to allow IV input range for x, y. (a) 2x 1 V; (b) 2y 1 V.

Io = 4KKa xy

(10)

where Ka is the gain of the voltage summing circuit and K is

the transconductance coefficient as usual. Reference 47 provides a summary of this multiplier type.
REMARKS ON MULTIPLIER STRUCTURES
None of the above analyses includes higher order effects such
as the -effect, -effect, and mobility degradation effect. These
effects are more severe in short channel devices. Besides the
higher order effect of MOS in the multiplier core, the nonidealities of the source follower and voltage adder were not considered. Another practical limitation of the multiplier is the
component mismatch that causes nonlinearity and offset.
The measurements of multiplier performance can include
input range, linearity, common mode effects, minimum power
supply voltage, power consumption, silicon area, frequency
range noise, and so on. Since all these performance measures
are strongly design dependent there is not an absolute standard comparison metric. However, the circuits in Fig. 4(a),
Fig. 6(a), and Fig. 7 require additional circuitry and there is
no clear theoretical advantage. These circuits are not discussed further in this article. Following detailed analysis for
the rest of circuits will suggest the most recommended analog
MOS multiplier structure.
Linearity. The linearity simulation result in Fig. 8 shows
that circuit Fig. 4(c) and Fig. 6(d) have poor linearity. The
performances of the circuits in Fig. 4(b) and Fig. 6(c) are
strongly dependent on the ideality of source follower. Figure
9 shows that the linearity of circuit Fig. 4(b) improves as the
source follower uses larger W/L ratio. On the contrary, this
effect is not clear for circuit Fig. 6(c). This result implies that
circuit Fig. 4(b) can outperform circuit Fig. 6(c) when K2 is
large enough (at least three times larger than K1). Although
the simulated linearity in Fig. 8 of the circuit Fig. 6(b) is comparable with others, Monte Carlo analysis reveals that high
sensitivity to process variation causes poor linearity.
Figure 10 shows the linearity error measured from the fabricated multiplier using Orbit 2m N-well process. These

multipliers were designed with identical transistor size

[(W/L)1 4 m/17 m and 50 m/10 m for all others],
transconductance, power consumption (360 W), and input
range (2 V differential input range for both x and y). The
linearity error of the circuit Fig. 4(b) is lower than 0.5%. It is
much better than the other because the W/L ratio of the
source follower is much larger than that of M1. These results
agree well with the simulation results discussed above.
Input Range and Minimum Power Supply Voltage. Input
ranges of circuits Fig. 4(b) and Fig. 6(c) are obtained from
their bias conditions shown in Fig. 11. The conditions for circuit Fig. 4(b) are

Vt < X x

V1 = Y y Vt < X x Vt
(11)

t <Y y

Y y Vt < Vd
These conditions are depicted in Fig. 12(a). The conditions for
circuit Fig. 6(c) are

Vdssat < V1 = Y y Vt
(12)
V1 + Vt = Y y < X x

X x V < V
t

0.15
Fig. 4(b)
Fig. 6(c)
THD (%)

and in Refs. 4446 using programmable floating voltage

source. This type has the following output:

0.10
2y = 0.5 V
2 x = 0.5 Vp-p
0.05
2x = 0.5 V
2 y = 0.5 Vp-p
0.00

(w/L)2
Figure 9. The effect of source follower transistor W/L ratio on THD.
The length of the source follower is fixed to 10 m. All other transistors have W/L 10 m/10 m. The linearity of circuit Fig. 4(b) improves as the source follower uses larger W/L ratio.

Fig. 4(b)

10

y = 1V
Fig. 6(c)

20

Linearity error (%)

Linearity error (%)

MULTIPLIERS, ANALOG CMOS

Fig. 4(b)

x = 1V
Fig. 6(c)

10
0

0.5
x(V)

695

0.5
y(V)

(a)

(b)

Figure 10. Measured linearity error from a fabricated chip. (W/L)1 5 m/17 m and
(W/L)2 50 m/10 m. For simplicity, only one quadrant is shown. (a) Linearity error for fixed
y; (b) Linearity error for fixed x.

These conditions are depicted in Fig. 12(b). For the same input range and output node voltage swing, Vo, circuit Fig. 4(b)
requires much lower power supply voltage than Fig. 6(c).
Noise. Another performance measure of a multiplier is
noise, especially for small signal applications where the input
range is not a major concern. A thermal noise current power
density of a MOS transistor is conventionally modeled as

i2n;lin = 4kTgds df
8
i 2
= kTgm df
n;sat
3

(13)

for transistor operating in linear and saturation, respectively.

In the case of circuit Fig. 4(b), total output noise current is
given
;

i2n;o = 4 i2n;lin + i2n;sat = 4 4kTgds1 df +



2
g
3 m2

= 16kT gds1 +

8
kTgm2 df
3

In the case of the circuit in Fig. 6(c), if the current source has
the same transistor size as the source follower, then the total
output noise current is given
;

i2n;o = 4 i2n;M2 + i2n;M1 = 4

8
kT ( gm2 + gm1 ) df
3

(17)

As gm1 in Eq. (17) is much larger than gds1 in Eq. (14), the
circuit in Fig. 6(c) has higher output noise. The output noise
floors of fabricated multipliers are measured with 1 K resistor at 1 Khz. The circuit in Fig. 4(b) shows 26 dB lower noise
floor than the circuit in Fig. 6(c).
DESIGN ISSUES OF THE CIRCUIT IN FIG. 4(b)
Table 1 summarizes the above comparisons and proposes that
the circuit in Fig. 4(b) is the most suitable analog CMOS multiplier structure. The circuit in Fig. 4(b) has a clear tradeoff

(14)

df
Vdd

where
V0

gds1 = K1 (VGS1 Vt VDS1 )

= K1 (X Vt (Y Vt )) = K1 (X Y )
gm2 =

2K2 IDQ =

2K2 K1 X Vt


Y V
t

(15)

(Y Vt ) (16)

Vdd
X

Y y

Vd

Saturation
V1

X x

Vdd

Linear

(a)

Y y

X x

Saturation

V1

(b)

Figure 11. Bias conditions. (a) Circuit Fig. 4(b); (b) Circuit Fig. 6(c).

2x

2y

Vt
Vd

2x
V0

Vd

Vt

2y

Vd

Vt
Vdssat; tail

Vt
GND

GND

(a)

(b)

Figure 12. Input range and power supply voltage. When input range
is 1 V for both x and y, threshold voltage Vt 1 V, and output signal
swing is 2 V, the minimum power supply voltages are 3 and 4 V,
respectively for the circuits in Fig. 4(b) and Fig. 6(c). (a) Circuit Fig.
4(b); (b) Circuit Fig. 6(c).

696

MULTIPLIERS, ANALOG CMOS

Table 1. Summary of Comparisons a

Operating
Region

Circuit

Complexity

Fig. 4(a)

Linearity

bad

Fig. 6(c)

Saturation

Fig. 6(d)

bad

Fig. 7(a)

bad

Fig. 7(b)

bad

Gray areas were not analyzed because circuit had already shown poor performance.

between noise and linearity. The input reflected equivalent

noise voltage of the circuit in Fig. 4(b) is obtained by dividing
Eq. (14) by the square of transconductance of multiplier, Gm,
which is determined by K1 as in Eq. (7), yielding

i2n;o
G2m

i2n;o

16K12

kT
K12

gds1 +

2
g
df
3 m2

(18)

when other input is unity. Substituting gds1 and gm2 in Eq. (18)
with Eqs. (15) and (16) results in

bad

bad

Fig. 6(b)

kT
=
K1

bad

bad

Fig. 6(a)

v2n;i

Noise

Linear

Fig. 4(c)

v2n;i =

Minimum
Power Supply

bad

Fig. 4(b)

Sensitivity

2
(X Y ) +
3

K
2 2
K1

Y + Vt
X
2

(Y Vt ) df
(19)

This analysis suggests that (X Y) and K2 /K1 should be reduced to improve the noise performance for given K1. This is
the direct tradeoff with linearity and input range because
K2 /K1 should be increased to improve linearity as illustrated
in Fig. 9 and (X Y) determines the input range as shown in
Fig. 12(a).
Figure 13 shows the noise simulation result. The output
noise is a linear function of K1 as in Eqs. (14)(16). When the
source followers transconductance is large enough [(W/L)2
20], the input reflected noise is inversely proportional to
(W/L)1 as in Eq. (19) because Eq. (19) is based on the assumption that the source follower is an ideal one. If the source
follower is not large enough [(W/L)2 10], Eq. (19) is no
longer valid, as shown in Fig. 13(b). The noise performance
begins to degrade when K2 /K1 ratio is smaller than 3 [(W/L)2
10 and (W/L)1 3]. Figure 14 shows the noise dependency
on source follower size and suggests that the K2 /K1 ratio

should be larger than 3. These analyses lead to two conflicting

observations as follows:
1. From Fig. 13(b) and Fig. 14, the K2 /K1 ratio should be
larger than 3 to make Eq. (19) valid.
2. From Eq. (19), the K2 /K1 ratio should be minimized for
low input reflected noise.
These two observations lead us to the conclusion that the optimal K2 /K1 ratio for low noise design is around 3 in this specific process. Note that the K2 /K1 ratio should be maximized
for high linearity.
Figure 15 shows that the input noise is almost a linear
function of the difference of two input common-mode voltages, (X Y), as expected in Eq. (19). This difference is equivalent to the summation over half of the input range. Therefore, for low noise design, the input range should be
minimized.
In designing the circuit Fig. 4(b), K2 /K1 ratio (X Y) are
key design parameters that determine the direct tradeoffs
among noise, linearity and input range.
CONCLUSION
Although a large number of MOS transconductance multipliers are reported in the literature only few practical MOS multiplier structures are discussed here. As the current trend of
circuit design is low voltage and low power, the circuit shown
in Fig. 4(b) seems to be one of the most attractive low voltage
and high performance MOS transconductance multipliers. A
BiCMOS version that uses BJT instead of source follower, or
a careful design, will improve its performance further.

MULTIPLIERS, ANALOG CMOS

697

925

8
Input noise (mV2)

Output noise (nV2)

(W/L)2 = 20
920

(W/L)2 = 10

915

910

5
(W/L)1

6
0.95

1.25

1.55
X Y(V)

1.85

Figure 15. Noise dependency on (X Y) for L 10 m, W1 10

m, W2 200 m and Vcom 4 V. Input reflected noise is a linear
function of input range, (X Y).

(a)

Input noise (mV2)

10

The reader should be aware that this conclusion might not

hold for all cases. The choice of circuit topology is completely
dependent on design specifications. The reader also should
note that, in general, a BJT multiplier outperforms any MOS
multipliers and no commercial discrete MOS multiplier has
been produced.

(W/L)2 = 10

6
(W/L)2 = 20
4

BIBLIOGRAPHY
2
1

5
(W/L)1

(b)
Figure 13. Noise dependency on W1. L1,2 10 m, (X Y)/2 4 V
and X Y 2 V. The output noise is measured at the one of the
output node with 50 load resistor and integrated within 1 MHz
2 MHz range. (a) Output noise. The output noise is almost a linear
function of W1. (b) Input reflected noise. Input reflected equivalent
noise is inversely proportional to W1.

Input noise (mV2)

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Lett., 30: 21252126, 1994.
26. Z. Wang, A four-transistor four-quadrant analog multiplier using
MOS transistors operating in the saturation region, IEEE Instrum. Meas., 42: 7577, 1993.
27. A. Diaz-Sanchez and J. Ramrez-Angulo, Design and implementation of VLSI analog adaptive filters, Proc. IEEE Midwest Symp.
Circuits Syst., 1996, pp. 13661368.
28. H. Song and C. Kim, An MOS four-quadrant analog multiplier
using simple two-input squaring circuits with source followers,
IEEE J. Solid-State Circuits, 25: 841848, 1990.
29. K. Kimura, Analysis of An MOS four-quadrant analog multiplier
using simple two-input squaring circuits with source followers,
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 41: 7275,
1994.
30. Y. Kim and S. Park, Four-quadrant CMOS analogue multiplier,
Electron. Lett., 28: 649650, 1992.
31. S. Sakurai and M. Ismail, High frequency wide range CMOS analog multiplier, Electron. Lett., 28: 22282229, 1992.

47. K. Kimura, An MOS four-quadrant analog multiplier based on

the multitail technique using a quadritail cell as a multiplier
core, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 42:
448454, 1995.
48. M. Holler et al., An electrically trainable artificial neural network
(ETANN) with 10240 floating gate synapses, Proc. Int. J. Conf.
Neural Netw., Washington, 1989, pp. 191196.
49. S. Liu and C. Chang, CMOS subthreshold four quadrant multiplier based on unbalanced source coupled pairs, Int. J. Electron.,
78: 327332, 1995.
50. R. L. Aalke, S. F. Quigley, and P. W. Webb, Design of an analogue
subthreshold multiplier suitable for implementing an artificial
neural network, IEEE Proc., Part G, 139(2): 261264, 1992.
51. L. Song, M. I. Elmasry, and A. Vannelli, Analog neural network
building blocks based on current mode subthreshold operation,
Proc. IEEE Int. Symp. Circuits Syst., 1993, Vol. 4, pp. 24622465.
52. D. Brodarac et al., Novel sampled-data MOS multiplier, Electron.
Lett., 18: 229230, 1982.
53. M. S. Piedade and A. Pinto, A new multiplier-divider circuit
based on switched capacitor data converters, Proc. IEEE Int.
Symp. Circuits Syst., 1990, Vol. 3, pp. 22242227.

32. S. Liu and Y. Hwang, CMOS four-quadrant multiplier using bias

offset cross coupled pairs, Electron. Lett., 29: 17371738, 1993.

54. L. W. Messengill, A dynamic CMOS multiplier for analog neural

network cells, Proc. IEEE Custom Integr. Circuits Conf., 1990,
pp. 26.4.126.4.4.

33. S. Liu and Y. Hwang, CMOS squarer and four-quadrant multiplier, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 42:
119122, 1995.

55. L. W. Messengill, A dynamic CMOS multiplier for analog VLSI

based on exponential pulse decay modulation, IEEE J. Solid-State
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34. S. Liu, C. Chang, and Y. Hwang, New CMOS four quadrant multiplier and squarer circuits, in Analog Integrated Circuits and
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56. B. A. De Cock, D. Maurissens, and J. Conelis, A CMOS pulsewidth modulator/pulse-amplitude modulator for four-quadrant
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35. J. Ramrez-Angulo, Highly linear four-quadrant analog BiCMOS

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MULTIPLIERS, ANALOG CMOS

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58. U. Gatti, F. Maloberti, and G. Torelli, CMOS triode-transistor

transconductor for high-frequency continuous-time filters, Proc.
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61. E. Sackinger and W. Guggenbuhl, A high-swing, high-impedance

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GUNHEE HAN
Texas A&M University

344

VOLTAGE REFERENCES

VOLTAGE REFERENCES
It is well documented in the annals of the science of electricity
that most early experiments involved qualitative rather than
quantitative information. Experimenters from the first century to the eighteenth century were largely concerned about
how electrically charged objects would attract or repel each
other, and whether this electricity was resinous or vitreousthat is, positive or negative. The only measurement
concerned the polarity of the charge or voltage; the degree
was generally not quantified except as strong or weak.
Nevertheless, as early as 1759 (1), Robert Symmer quantified the amount of charge generated by pulling a white silk
stocking off a black worsted stocking. He would transfer the
charge from one or more stockings into a Leyden jar (a capacitor constructed from a glass jar). He found that the charge
from 2 silk stockings would shock him up to both elbows; but
the charge from 4 silk stockings was sufficient to generate a
shock all the way from his fingers to his elbows to his breast,
and additionally to ignite a spoonful of brandy. It is interesting to note that 4 units of charge was required to ignite the
brandy, but 3 units was not enough (2).
EARLY MEASURING INSTRUMENTS
Some of the earliest meters for detecting the quantity of
electricity were galvanometers and electrometers. A galvanometer originally consisted of a compass needle that was deflected by a current passing nearby. The galvanometers sensitivity was soon increased by passing the current through a
large number of turns of wire coiled around the needle. The
strength of the current was thought to be proportional to the
deflection of the needle, although the linearity of this relationship was not checked quantitatively.
An electrometer was typically made of two parallel strips
of extremely thin metal. When a large voltage was applied
between them, the metal strips would repel each other and be
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

VOLTAGE REFERENCES

deflected. The mystique of this apparatus was enhanced by

the use of gold for the materials; of course, gold was also useful because it is very malleable and can be hammered into
extremely thin, flexible strips. Again, no specific statements
about linearity were entertained, except for the notion of
weak or strong.
Still, it was recognized as early as the 1700s that the measurement of electricity by such meters could be quantified: if
two voltages produced the same deflection, they were presumably equal. Likewise if two currents produced the same deflection in a galvanometer, they were equal. Eventually it was
determined (Becquerel, 1840) that when two voltages were
applied to an electrometeror to a galvanometerif the meter did not deflect, the amount of electricity was equal. This
invention of the null mode (the differential voltmeter) is the
essence of modern metrology. As it was obvious that the resolution of such apparatus depended on the sensitivity of the
galvanometer, galvanometers were designed with exquisite
delicacy. Improvements included adding a mirror, so that a
deflection as small as
 deg (of angle) could be read as a
deflection of several millimeters, for a light beam shining on
a scale several meters away. Torsional balances were designed so that a long thin vertical wire could be sensitive to
very small rotational forces (less than 0.1 mg cm of torque).
Advances in galvanometer resolution occurred quite rapidly
in the 1800s, due to ingenious new structures. Still, as of
1894, only moving-magnet galvanometers were known; the invention of the moving-coil galvanometer lay 20 years in the
future. Galvanometers continued to be used extensively up to
the 1960s, and are sometimes used at present, due to their
simplicity and good resolution. However, mechanical and electrical choppers with ac amplifiers have gradually supplanted
them.
Other experiments were made to quantify electricity. In
1788 Alessandro Volta (3) applied voltage to the plates of a
capacitor connected to an ordinary beam balance. As the voltage increased, the (tiny) amount of weight to balance the attractive force was measured. This provided some linkage and
confirmation to electricity theories being developed at that
time. It was a tedious method to measure voltage, but it was
quantitative. Similarly, the amount of current through a galvanometer could also be related (linearly) to the amount of
silver plated by that current from a solution onto an electrode.
The mass of silver could be weighed precisely to provide a
linear measure of the time integral of the currentagain, a
tedious, slow, messy measurement, but quantitative and linear. For example, a carefully conducted 1875 experiment by
F. Kohlrausch determined that 10 A s would plate out 11,363
2 g of silvera result within 2% of modern data (4).
The invention of the Wheatstone bridge by Samuel H.
Christie (it was popularized by Sir Charles Wheatstone about
1843) (5) constituted a great advance in the measurement of
resistance. The advantage arose because the balance of the
bridge did not depend on the stability of an (unstable) voltage
supply, but only on the ratio of the resistances in the arms of
the bridge. This advance soon led to improved voltage measurement: now any two dc voltages could be compared by attenuating them with precisely known resistor dividers until
an electrometer or galvanometer detected a null. The ratio of
the voltages was easily calculated from the ratios of the resistive dividers. Now a stable referencea good voltage cell,
a standard cellcould be used to make accurate and useful

345

voltage measurements. [Note that many modern reference

books use the term standard cell for a block of integrated
circuit (IC) functions that is stored in a computer and can be
easily brought into a large IC.]
STANDARD CELLS
The earliest electrochemical cells, as discovered by Alessandro Volta in 1800 (6), were able to generate about a volt of
electromotive force, using tin and silver or copper plates in a
mild acid solution. These were not precision references, but
were usable in many experiments, and led to improved cells
with more power and better stability.
In the late 1800s, the best, most stable cell used as a standard was the Daniell cell (invented in 1836 by the English
chemist John F. Daniell) (7). The cell consisted of a copper
electrode in a copper sulfate solution and a zinc electrode in
dilute sulfuric acid, the two solutions being separated by a
porous partition (8). It put out a stable 1.101 V potential, but
with high internal impedance. It was the precursor of modern
ultrastable standard cells.
The saturated cadmium cell was developed by Edward
Weston in the era 1893 to 1905, and was adopted as a standard in 1908. It is made in an H-shaped glass tube, which
contains metallic mercury in the bottom of one leg, and a cadmiummercury amalgam in the other leg (See Fig. 1.) In between the two electrodes are cadmium sulfate solution, mercurous sulfate paste, and cadmium sulfate crystals. This cell
has an output of 1.018636 V at 20C, and excellent stability,
of the order of 1 106 per day, per week, or per month. Its
primary disadvantage is its strong negative temperature coefficient (tempco), about 39.4 V/C at 20C. This problem is
overcome by assembling one or more of such cells in a stable

Glass
H vessel

;
;;

Cadmium
sulfate
solution

Cadmium
sulfate
crystals
Mercurous
sulfate
paste

Cadmium
sulfate
crystals
Cadmium
mercury
amalgam

Mercury

Platinum
wires

Figure 1. Arrangement of the elements of a saturated Weston cadmium cell.

346

VOLTAGE REFERENCES

temperature-controlled chamber maintained at 28 or

30C. Another disadvantage is the degradation that occurs
if even 1 nA dc is drawn from the cell for a long time, or 1 A
for a short time. This degradation can be avoided primarily
by careful procedures to avoid drawing current from the cell,
with the help of current buffers.
The other disadvantage lies in its instability if the cell is
shaken, jiggled, or wobbled. Recovery to 20 106 is usually
adequate in a few hours, but for full stability (2 106)
several days of rest must be allowed. This drawback is usually overcome by never moving the standard cells; unknown
voltages or secondary standards are brought to the standards
lab, where the standard cell is maintained at constant temperature, with no motion or vibration. The saturated standard cell is still in use today in standards laboratories, as it
possesses superior stability, despite its drawbacks.
The unsaturated cadmium cell is constructed similarly, but
without any surplus of cadmium sulfate crystals. It has the
advantage of a lower tempco (around 10 V/C), but is not
as stable as saturated cells.
GAS DISCHARGE TUBES
In the era 1920 to 1960, there was a need for stable references
in portable equipment. Gas discharge tubes such as OA2,
OB2, and 85A2 were used as references for precision regulators. If these tubes and the related amplifiers and resistors
were powered up and warmed up and aged properly, good
short-term voltage stability in the range 0.01% to 0.1% per 24
h could be observed (9). This was considered adequate for
most portable precision equipment. However, the advice in
Ref. 9 stated that a stack of two 42 V mercury batteries such
as Mallory type RM415 would provide improved stability over
the 85A2. The degree of improvement was not stated. Gas
discharge tubes are still used in high-voltage equipment, but
not much in new designs.
ZENER DIODES
Ever since the invention of the Zener diode in the 1950s,
much hope has been engendered for using stable Zener diodes
as stable references. Technically, diodes with breakdown below 5.4 V are true Zener diodes, which depend on a tunneling
mechanism, whereas in diodes that break down above 5.4 V,
the mechanism is avalanche breakdown. But the term Zener
diode is applied to both types, unless there is some reason
for distinguishing the mechanism.
Low-noise alloyed Zener diodes have existed since 1955.
The Zener diode is made simply by doping a silicon pn junction so heavily that it breaks down at some useful voltage
typically in the range of 3 V to 200 V. Some Zener diodes have
displayed good stability, and others have not. Most Zener diodes above 5.4 V have an inherent finite, positive, fairly constant tempco. To provide useful performance with low tempco,
one or more forward diodes are then connected in series with
the Zener. The forward diode chip is typically mounted right
against the Zener chip, inside the conventional DO-35 glass
diode package. The Vf of the forward diode (about 2 mV/C)
is used to cancel out the tempco of the Zener diode. The resulting reference voltage has, under favorable conditions, stability rivaling that of inexpensive standard cells. These refer-

ences have the advantage of portability. They can operate

(with degraded accuracy and stability) over temperature
ranges where standard cells are impractical. Much effort has
been put into evaluating Zener diode references. Not all of it
has been completely successful. Early manufacturers of reference-type Zener diodes included Solitron, Hughes, PSI, and
Motorola.
Alternatively, the Ref-Amp (10), invented by General Electric Corp., utilized an npn transistor with its emitter connected to the cathode of a low-noise alloy Zener diode chip,
acting both as a temperature compensator and as a gain
stage. The TO-5 package provided low stress, low hysteresis,
and good stability.
The author has evaluated a 6.2 V Zener reference from a
Minuteman I nose-cone guidance system. It was hoped that
this reference from about 1960 might exhibit superior stability. Actually, when it was set up in a precision bias circuit
and aged, it had a tendency to drift not much better than 10
106 or 20 106 per week, somewhat inferior to modern
Zener references.
When early integrated circuit references were built, they
were evaluated and compared with the best reference Zener
diodes. Soon a serious problem was noted: the glass-packaged
Zener diodes had a typical thermal hysteresis of 200 106
to 600 106 when cycled over a 100C loop. This is manifested when a Zener diode is cycled cold and then hot and
back to room temperature; its voltage will be different than
when it is cycled hot and then cold and back to room temperature. Integrated circuits assembled in hermetic packages
were observed to have typically 5 or 10 times better hysteresis, due to the smaller stress (and smaller change of stress)
on the die. This is a characteristic of references that is not
usually documented or even mentioned. These reference Zener diodes also showed some sensitivity to stress on their
leads.
The best, most stable Zener references are often packaged
with batteries and heaters in a portable temperature-controlled environment, just as saturated standard cells are.
These instruments can be used as portable transfer standards. However they have not taken over the task from standard cells entirely, because their stability is not always as
good. If the power is ever turned off, these Zener references
sometimes exhibit a shift as large as 5 ppmconsiderably
bigger than that of standard cellsand not always reversible.
A study of low-tempco Zener references available in the
1972 era (11) showed at least 120 different JEDEC-registered
part numbers, rated from 25 to 85C, plus 100 A-grade
versions rated for the military temperature range of 55 to
125C. Many of them were for odd voltages (6.4 V, 8.4 V, 8.5
V, 9.3 V, 9.4 V, 11.7 V, 12.8 V, 19.2 V, 37.0 V, 37.2 V, etc.), at
odd currents (choice of 0.5 mA, 1.0 mA, 2.0 mA, or 4.0 mA of
bias current). However, as of this writing, almost all of these
parts have been obsoleted or discontinued. A small number of
popular, commercially viable reference-grade Zeners are still
available, as listed in Table 1 (12).

INTEGRATED ZENERS
The LX5600 temperature-sensor IC, designed by Robert Dobkin at National Semiconductor Corp. (NSC) and introduced in
1973 (13), had a hidden agenda: in addition to the tempera-

VOLTAGE REFERENCES

347

Table 1. Commercially Available Zener References, 1998 (Ref. 12)

Types
1N821829
1N45654569
1N45704574
1N45754579
a

Voltage a
(V)

Current.
(mA)

Tempcos
(106 C1)

Manufacturers

Price
($/100)

6.2
6.4
6.4
6.4

7.5
0.5
1.0
2.0

1005
1005
1005
1005

Motorola, APD
Motorola, APD
Motorola, APD
Motorola

$0.322.12
$0.716.52
$0.6925.40
$0.6924.21

Tolerance 5%.

ture sensor, this chip had an experimental IC Zener reference. The Zener diode was connected in series with a transistors base-to-emitter voltage Vbe, and a buffer amplifier was
provided. The references actual performance was fairly mediocrethe tempco was typically 30 106 /C, and the longterm stability was stated as 1000 106 per 1000 h at 85C.
Still, this temperature-sensor IC went into production as a
test bed, and the engineers were able to evaluate a large number of the diodes. Best of all, the construction of a temperature sensor on the same chip as the Zener reference made
it easy to operate the temperature sensor as a temperature
controller, and to make a little oven around the Zener, holding it at a very stable temperature (such as 88C). It was
easy to evaluate a large number of these references, operating
at a constant temperature.
This study soon led to the LM129 and LM199 IC references (14).
The LM129 was an improved, simplified, upgraded version
of the LX5600s reference, with a series resistance better than
1 , and a tempco typically in the range 10 106 /C to 60
106 /C. These ICs could be tested (and graded in production test) for 50, 20, or 10 106 /C.
The LM199 was a new design. It used an integrated temperature controller on the die, to hold the die temperature at
88C. It was housed in a four-lead TO-46 package (similar
to a low-profile TO-18). A small plastic thermal shield over
the package was used to minimize the power needed to hold
the whole IC at that temperature. Under these conditions, the
LM199s reference could show a usable tempco better than 2
106 /C, 1 106 /C, or even  106 /C, selected and
tested, over a temperature range from 55 to 85C. Of
course, this temperature-controlled IC did require a significant amount of power for the heater (typically 260 mW at
25C, and even more at low ambient temperatures) to hold
that 88C temperature. But this was an acceptable requirement in many systems.
The temperature sensitivity of any temperature-stabilized
circuit depends at least as much on the layout of the heatsensitive components, and on the gradients caused by the
heater, as on the tempco of the circuit. Thus the LM199s good
tempco is related to good die layout.
Further disadvantages of the LM199 were its tolerance
(2%) and the fact that its nominal voltage (6.95 V) was not
as convenient as 5.000 V or 10.000 V or even 6.20 V. And
unless a charge pump was added, the LM129 or LM199 could
not run on 5 Vit needed at least 8 V, at 1 mA for the reference and at 50 mA for the heater. These disadvantages led
to efforts to develop improved circuits that avoided some of
these drawbacks.
The other significant advantage of the LM129 (and LM199)
resided in its buried (subsurface) Zener diode. In most Zener

references the breakdown occurred at the surface, where the

concentration of impurities (doping) was maximum. Thus, surface contamination (even with high-quality planar processing)
and electron charging of the oxide caused some degradation of
noise and of long-term stability. The invention by Carl Nelson
and Robert Dobkin of shallow diffusion layers with decreased
concentrations at the surface caused the Zener breakdown to
occur about a micron below the surface of the IC, where it is immune to surface conditions. This allowed superior consistency
of low noise and better long-term stability.
Extensive testing of large numbers of LM199s showed that
a large fraction of the units exhibited reference stability consistently better than 10 106 or 5 106 per 1000 h, when
sampled once a week. (However, some units were consistently
worse than 20 106 per 1000 h.) The units that tested better
than 20 106 per 1000 h were designated LM199AH-20 and
LM299AH-20, and were used in many precision systems as
stable references. Also, they were popular in high-resolution
DVMs. The LM199 is still the only successful temperaturestabilized IC in the industry.
Several good selected LM299AH references were evaluated
by the National Bureau of Standards (NBS, now the NIST).
They found that the long-term drift tendency was about 1
106 per 1000 h, a fairly consistent drift, presumably related to operation at the die temperature of 88C.
Other researchers found that if one group of LM299AHs
were kept around room temperature, with their heaters off,
and another group allowed to run at their normal temperature of 88C, the long-term drift trend of the units at room
temperature was considerably lower than that of the warm
units. The room-temperature units could be heated up to their
normal 88C on a specified schedule, perhaps one day per 3
months, and used to calibrate out the long-term drifts of the
units kept at 88C.
The use of buried Zener diodes has spread to other ICs.
The LT1021 (15), designed by Carl Nelson at Linear Technology Corp. (LTC), used a buried Zener diode with temperaturecompensating circuits and after-assembly trims to achieve 2
106 /C, without any heater. The LM169 (16) was engineered by Robert Pease at NSC to do likewise.
The LTZ1000 is a buried Zener designed by Robert Dobkin
of LTC for laboratory standard use. All resistors are off chip,
so that high-stability resistors can be utilized. Its on-chip
heater can be activated for thermal stabilization. The die attach uses bubble material for high thermal impedance, as
high as 400C/W. Long-term stability approaching 1 106 is
claimed (17).
The Analog Devices AD534 Multiplier IC was designed by
Barrie Gilbert (18) using a buried Zener diode. The Analog
Devices AD561 was a complete digital-to-analog converter
(DAC) IC designed by Peter Holloway and Paul Brokaw, uti-

348

VOLTAGE REFERENCES

lizing a buried Zener diode and tempco trim circuits to

achieve a gain tempco better than 10 106 /C (19).
Further research and development into circuits with buried Zener diodes has waned, due to the improvements in
bandgap references and to the concentration of research on
low-voltage circuits and on CMOS technology, which precludes the use of buried Zener diodes.
The design of a good reference on a large CMOS chip is not
trivial. In many cases, a mediocre on-chip bandgap reference
is adequate for a system on a chip. If a superior reference is
needed, an external (off-chip) reference is often added. This
can often provide cost, performance, and yield advantages.

V+

(200 )

R1

R4

3.9 k

13.5 k

Q7
(170 )
Q2

1.22 Vdc

16E
Q1

R5
1.6 k

Q4

Q9
i
V

BANDGAP REFERENCES
Figure 2. Schematic diagram, LM113 (simplified).

The concept of the bandgap reference was first published by

David Hilbiber of Fairchild Semiconductor in 1964 (20). If a
suitable circuit is used to add voltages with both positive and
negative temperature coefficients, until the output voltage is
approximately the same as the bandgap voltage of the material used (1.205 V for silicon, 0.803 V for germanium) a stable,
low-tempco reference can be achieved.
The invention of the LM113 bandgap reference IC (21) by
Robert J. Widlar in 1971 was rather like the birth of a baby
just a beginning. While this small IC was useful for instrument makers who needed a reference that would run on low
voltages (such as 4.5 V or 3 V or even 1.5 V), it definitely did
not have superior performance. The standard LM113 had an
output voltage of 1.220 V with a tolerance of 5%, a fairly
broad spread of temperature coefficients, and mediocre longterm stability. Still, the principle and the feasibility of the
bandgap reference had been proved, and the development of
new bandgap reference circuits with needed improvements
soon commenced. These efforts have continued for well over
25 years without much diminishment.
The bandgap reference was first used in the NSC LM113
reference circuit (1971) and the LM109 Voltage Regulator
(1969) (22). The bandgap circuit employs transistors operating at different current densities, such as 10 A flowing
through one transistor with one emitter, and the same
amount of current flowing through another transistor 10
times as big. This generates a voltage (Vbe) of perhaps 60
mV, which is a voltage proportional to absolute temperature
(VPTAT). This voltage is amplified and added to a voltage
proportional to the transistors baseemitter voltage Vbe,
which decreases fairly linearly with temperature. The addition is scaled so that the total voltage is about 1.24 V dc.
When the reference voltage is set or trimmed to this voltage,
a low tempco is obtained.
The principle of the bandgap reference relies on a good understanding of the Vbe of transistors. Widlars paper (23) on
this subject clarified the mathematics and physics of Vbe and
corrected various misconceptions.
We refer to the example of the LM113. In Fig. 2, the
LM113 schematic diagram shows a basic bandgap circuit.
When V is around 1.22 V dc, Q1 runs at a high current density, about 230 nA/m2. Q2 is operated at a low density, about
15 nA/m2, and so its Vbe is much smaller, by about 70 mV.
Now, lets assume that the circuit is at balance and the output
is near 1.22 V. Then the 70 mV across R5 is magnified by the
ratio of R4 to R5, about 8.5 : 1, up to a level of 600 mV. This

voltage is added to the Vbe of Q4 (about 620 mV at room temperature) to make a total of 1.22 V, as required. Q4 then amplifies the error signal through Q7 and Q9, which provide
enough gain to hold the V bus at 1.22 V. The beauty of the
bandgap reference is the summation of the Vbe term, which
decreases at the rate of about 2 mV/C, and the Vbe term,
which grows at about 2 mV/C, to achieve an overall tempco
that is substantially zero. All bandgap references employ this
summation of a growing and a shrinking voltage to make a
stable low-tempco voltage. Further, it has been shown (23)
that when a circuit has been trimmed to the correct voltage,
the correct tempco will follow, despite process variations in
parameters such as Vbe, , sheet resistivity, etc. Consequently,
bandgap circuits are often trimmed to their ideal voltage so
as to provide a low tempco.
Since the LM109 and LM113 were introduced, many other
circuits and configurations have been invented for bandgap
references. The Brokaw cell is often used for output voltages
larger than 1.25 V, as its Vout can be scaled by the ratio of two
built-in resistors, R3 and R4. This unit, the AD580, was introduced in 1974 (24) (Fig. 3).
A similar circuit is used in the LM117 (25), whose output
can be set by two external resistors R7 and R8 to any voltage
in the range 1.25 V to 37 V (Fig. 4).
The above information was excerpted from an invited paper at the IEEE Bipolar Circuits and Technology Meeting,
1990 (26). The paper includes much information on how to

Vout
R
(1.25 V) ( 3 +1)
R4
R3

1.25 Vdc
E
R2

10E
R1

R4
(Substrate)

Figure 3. Schematic diagram, AD580 (simplified).

VOLTAGE REFERENCES

(Buffer)

this principle has been demonstrated, it is foreseeable that

ICs with fully optimized performance will be available soon.
Most of these IC references are not usable directly as standards. However, the ones with the best specifications have
adequate stability and are suitable for portable standards in
small systems. They may need auxiliary circuits for trims,
calibration, tempco correction, and so onjust as a Weston
standard cell needs an oven to be useful.

+Vs

E
R6

10E

Vout

(Substrate)

R5

349

R7
Adj.

R8

Figure 4. Schematic diagram, LM117 (simplified).

engineer a bandgap reference badly, and a little information

on how to do it right. The paper is accessible on the World
Wide Web at: http://www.national.com/rap/Application/
0,1127,24,00.html
The bandgap reference was soon introduced into many
kinds of voltage regulator ICs, instead of the old Zener references. Many of these ICs showed improved performance in
one aspect or another. But most of these regulators had low
accuracy, and will not be considered here. Our study here will
concentrate on precision references with much better than 1%
accuracy and tempcos much better than 50 106 /C.
Paul Brokaw at Analog Devices, Wilmington, MA, designed a curvature-correction circuit that canceled out the
normal quadratic dependence of the bandgaps output on temperature. The temperature drift over a 70C span was reduced below 5 106 /C. These were introduced in the
AD581, about 1976. The related US patent (27) showed how
to use different types of IC resistors, with different tempcos,
to correct for the curvature.
Robert Widlar designed the NSC LM10 IC bandgap reference (28). This circuit had a reference output of 0.200 V,
which was easily scalable by external resistors up to 39 V.
The basic reference was able to run on a 1.1 V power supply.
It included curvature correction (29).
At NSC, Carl Nelson designed a quadratic curvature correction circuit suitable for curvature correction of bandgap
references and temperature sensors, as described in a US patent (30). This was first introduced on the LM35 temperature
sensor (31). While at LTC, Nelson later designed an improved
logarithmic curvature-correction scheme (32). This circuit was
introduced in the LT1019 (33).
Derek Bowers at Analog Devices designed a modified type
of reference IC circuit that does not rely on the Vbe of transistors operated at different current densities. It depends on the
offset of the threshold voltages of two junction field-effect
transistors (JFETs) made with different implant doses. This
IC was introduced in 1997 as the ADR291 (34). It has a typical long-term stability of only 100 106 per 1000 h at
150C. The ADR291 as introduced does not have sufficiently
low tempco or gain error to permit such excellent long-term
stability to be fully appreciated. But since the feasibility of

HYBRID IC REFERENCES
For many years, makers of hybrid ICs were able to include
chips of different technologies, wired together on a small ceramic substrate. For example, the old NSC LH0075 (introduced in 1975 but now out of production) included a quad
opamp chip, an LM329 IC reference, and several lasertrimmed resistors. The trimming provided advantages of improved output accuracy, and a convenient 10.00 V output voltage level rather than the 6.95 V of the reference itself.
Likewise, modern hybrid IC references such as Thaler
Corp.s Models VRE100/101/102 use chips of different technologies (Zener diodes, precision trimmable resistors, operational amplifiers, and thermistors) to provide the same kinds
of advantages, such as output voltages trimmed to 0.005%,
and temperature coefficients better than 0.6 106 /C or
0.3 106 /C. Output voltages such as 10 V or 10 V dc
(or both) to as low as 1.5 V or 1.5 V are available (35).
FEATURES OF BANDGAP AND INTEGRATED-CIRCUIT
REFERENCES
As mentioned above, many kinds of ingenious internal architectures have been used for bandgap references. The actual
topology of the bandgap elements has been arranged in many
waysways that may (or may not) be transparent to the
user. However, there are also features that are useful to some
users and of no value to other users. A list of typical features
is provided here, along with a brief list of typical ICs that
include those features. This list of ICs is by no means intended to be exhaustive, but merely indicative of what features one might look for.
Low Power. Many users like the advantages of low power,
but often a low-power bandgap reference is noisy, because
transistors operated at small currents tend to have voltage
noise inversely proportional to the square root of the
emitter current. LM185-1.2 (10 A), ADR291 (15 A).
Low Noise. A bandgap reference operated at higher current tends to be less noisy. LM336, ADR291.
Shutdown. Sometimes it is important to turn the device
off for minimum system power drain.
Startup. Not all references start up very quickly.
Shunt-Mode Operation. In some applications, a shuntmode reference (which looks like a Zener) is easier to
apply. LM4040, LM336, LT1009, AD1580.
Series-Mode Operation. For applications where the load
current may vary, series mode can be advantageous.
AD581, LT1019, many others.
Output Can Sink or Source Current. Sometimes it is convenient if the output can drive load currents in both di-

350

VOLTAGE REFERENCES

rections. If you need this, be cautious, as load regulation

when sinking is usually inferior to when sourcing.
MAX6341, AD581, LT1019, many others.
Output Is Trimmablein a Narrow Range. Beware that
if you use this feature to adjust Vout a significant amount,
the tempco may be degraded.
Output Is Adjustableover a Wide Range. This is sometimes a nice feature, but the accuracy, stability, and
tempco of external resistors must be considered. LM385
(adjustable), LM4041-ADJ.
Filter Pin. As band-gap references are fairly noisy (sometimes comparable to 1 LSB of a 10- or 12-bit system) a
provision for an external noise filter capacitor is sometimes very useful. LM369, AD587.
Temperature Sensor. Some units provide a temperature
sensor output at 2.2 mV/C. REF01, LT1019, many others.
Heater. Some units provide a resistor on-chip that can
be used to heat the unit to a constant warm temperature.
LT1019.
Low-Dropout Regulator. Many modern references need a
supply voltage only 0.1 V or 0.2 V larger than Vout: a popular feature. See also below.
Requirement for Capacitive Load. Most low-dropout references require a capacitive load on their output to prevent oscillations: an unpopular feature, as sometimes the
capacitor is bigger or more expensive than the IC.
Tolerance of Cload. Some references will tolerate any capacitive load, and may not require any load capacitor at
all. LM385, LT1009.
Low Tempco. A very desirable feature.
After-Assembly Trim. This is a procedure for optimizing
the low tempco of a reference. However, it uses pins for
connection to in-circuit trims such as fuses or Zener
zapsso that these pins cannot be used for other features. LT1019, LM169.
Small Packages. Many small systems require surfacemount devices. Packages such as SO-8 or SOT-23 are
popular. However, tiny plastic packages tend to cause
stresses which may degrade long-term stability.
Long-Term Stability. A very desirable feature, but not
trivial to find, and not easy or inexpensive to test for. In
fact, stability is just about the most expensive specification that one can buy on a reference.
Compromises. No reference can provide every advantage, so priorities and tradeoffs must be engineered.
Price. Any combination of excellent features and/or specifications is likely to command a high price. This leads to
compromises; see above.

THE JOSEPHSON JUNCTION

As early as 1972, the advent of the ac Josephson junction
promised to provide improved accuracy in its representation
of the volt standard. When microwave energy at a precisely
known frequency is injected into a stacked assembly of Josephson junctions, held at 4 K by liquid helium, it is possible
to generate a voltage that is accurate and stable to better
than 0.1 V/V, both theoretically and in practice (36).

Preliminary research confirmed that even the best Weston

saturated standard cells had unexplained drifts and noises, of
the order of 1 106, which the Josephson junctions did not.
As the Josephson junction equipment became more reliable
and easier to operate, it became obvious that they would soon
make possible a new, more stable standard. After a considerable amount of engineering and development, a new representation of the volt was established. The Josephson constant
KJ-90, adopted on January 1, 1990, was defined as 483,597.900
GHz/V, exactly.
The ac Josephson junction equipment for establishing ultraprecise voltage references has typically a precisely known
72 GHz input frequency, and an output of 2.0678336 V/GHz.
The output of each junction is about 149 V. To provide an
output at a convenient level, an array of 2000 Josephson junctions is integrated, stacked in series, and enclosed in the cryogenic (4 K) microwave-stimulated chamber, thus providing an
output of perhaps 298 mV. This voltage is compared with the
1.018 V level using conventional potentiometric techniques,
to calibrate the standard cells that act as secondary transfer
references. Equipment to implement this stable reference
tends to cost in the vicinity of $100,000, plus considerable labor and operational costs.
Thus on January 1, 1990, the magnitude of the US volt
(as well the voltage standards in most other countries) was
changed. The new 1990 US volt was established as 9.264
V/V larger than the previous (1972) US standard. Since
1990, the international standard volt has still been defined as
1 W/1 A, but the standard representation of the volt is the
output of the Josephson junction apparatus.
THE AMPERE
In theory, the volt is not an absolute standard. The volt has
long been defined as the potential such that 1 V 1 A 1
W. In turn the ampere is defined as an absolute standard,
such that 1 A flowing through a pair of very long wires (of
negligible diameter), separated by 1 m, will cause a force of
2 107 N per meter of length. In practice, the volt is a much
more useful and usable standard. The ampere standard is not
very portable. In fact, when a 1 A standard is required, it is
normally constructed by establishing 1 V and 1 , causing 1
A to flow.
THE OHM
In theory, the ohm is not an absolute standard, but the ratio
1 V/1 A, with the volt and ampere defined as above. As of
1990, the representation of the ohm was redefined using the
quantum Hall effect (QHE), discovered by Klaus von Klitzing (37):
The QHE is characteristic of certain high-mobility semiconductor
devices of standard Hall-bar geometry, placed in a large applied
magnetic field and cooled to a temperature near one kelvin. For a
fixed current I through a QHE device there are regions in the
curve of Hall voltage vs. gate voltage, or of Hall voltage vs magnetic field depending on the device, where the Hall voltage UH
remains constant as the gate voltage or magnetic field is varied.
These regions of constant Hall voltage are termed Hall plateaus.
Under the proper experimental conditions, the quantized Hall re-

VOLTAGE REFERENCES
sistance of the ith plateau RH(I), defined as the quotient of the
ith plateau to the current I, is given by
RH (i) = UH (i)/I = RK /i
where i is an integer and RK is now termed the von Klitzing constant after the discoverer of the QHE . . ..
Numerically, RK is about 25,813 ohms. The value agreed upon
as an international constant was RK-90 25,812.807 ohms.

This was a considerable improvement, as the best older standard resistors were shown to be drifting at about 0.1 /
per year. With the quantum standard, such drifts are banished.
PRECISION MEASUREMENTS
In classical metrology, one uses a precision (six-digit, sevendigit, or eight-digit) voltage divider, known as a potentiometer. This has very little in common with the variable resistor often called a potentiometer or potbut it does act as
a voltage divider. When such a precision potentiometer is
used with a null meter, any voltage can be compared with a
standard or reference voltage. The unknown voltage is thus
well determined, according to the ratio of the potentiometer
and the standard voltage (allowing for its uncertainty.) However, most precision potentiometers are not guaranteed to
maintain their linearity to 1 LSD (Least Significant Digit) for
long-term accuracy, after their resistive dividers are trimmed
and calibrated. A good potentiometer may hold better than
1 106 linearity per year, but it is not guaranteed that
switching from 0.499999 to 0.500000 will not cause a decrease
of its output. Further, an inexperienced user may find it very
time-consuming to use such a divider. When taking a large
number of data, long-term system drift may cause errors that
could be avoided by taking data more quickly.
The authors recommendation is to use a good six-digit or
seven-digit multislope integrating digital voltmeter (DVM),
with 1 106 inherent differential linearity and excellent
overall (end-to-end) linearity. The author has had excellent
experience with HP 3456, 3457, 3468, and other similar integrating voltmeters. Differential nonlinearity has never been
observed to exceed 1 106 of full scale, on 10 V scales. Noise,
offsets, and gain errors are usually acceptably small. For best
absolute accuracy, the DVMs full-scale factor should be compared with other stable references. Note that not all six-digit
or seven-digit DVMs have this inherent linearity.
CONCLUSION
Since most advances in references are designed by IC manufacturers on a commercial basis, to be aware of good new
products, one must inquire of the IC manufacturers, to see
what is available. A list of IC makers is provided here, as
well as a list of companies making precision references and
measuring equipment.
MANUFACTURERS
High-Precision Instruments for Voltage Standards
Datron Systems Division, 200 West Los Angeles Ave.,
Simi Valley, CA 93065-1650. Phone: 805-584-1717. Fax:
805-526-0885.

351

The Eppley Laboratory, Inc., 12 Sheffield Avenue, Newport, RI 02840. Phone: 401-847-1020. Fax: 401-847-1031.
Fluke Corporation, MS 250, P.O. Box 9090, Everett, WA
98206-9090. Phone: 800-44F-LUKE or 425-347-6100.
Fax: 425-356-5116.
Hewlett Packard Co., Electronic Measurement Systems,
815 14th Street SW, P.O. Box 301, Loveland, CO 80538.
Phone: 970-679-5000. Fax: 970-679-5954.
Julie Research Laboratories, Inc., 508 West 26th Street,
New York, NY 10001. Phone: 212-633-6625. Fax: 212691-3320.
Keithley Instruments, 28775 Aurora Road, Cleveland,
OH 44139. Phone: 800-552-1115 or 440-248-0400. Fax:
440-248-6168.
Voltage Reference Integrated Circuits
Analog Devices Inc., 1 Technology Way, P.O. Box 9106,
Norwood, MA 02062-9106. Phone: 781-329-4700. Fax:
781-326-8703.
Burr Brown Corp., International Airport Industrial Park,
6730 South Tucson Boulevard, P.O. Box 11400, Tucson,
AZ 85734. Phone: 800-548-6132 or 520-746-1111. Fax:
520-889-1510.
LTC (Linear Technology Corp.), 1630 McCarthy Boulevard, Milpitas, CA 95035-7417. Phone: 408-432-1900.
Fax: 408-434-0507.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086-9892. Phone: 408-737-7600. Fax: 408737-7194.
NSC (National Semiconductor Corp.), MS D2565, 2900
Semiconductor Drive, Santa Clara, CA 95051. Phone:
408-721-8165 or 800-272-9959. Fax: 800-737-7018.
Thaler Corp., 2015 North Forbes #109, Tucson, AZ
85745. Phone: 800-827-6006 or 520-882-4000. Fax: 520770-9222.
ACKNOWLEDGMENT
The author wishes to thank Paul Brokaw, Derek Bowers, and
Dan Sheingold at ADI; David Fullagar at Maxim; and Robert
Dobkin at LTC for their advice and encouragement.
BIBLIOGRAPHY
1. Phil. Trans., 1759, per The Encyclopaedia Britannica, Vol. VIII,
1894, p. 7.
2. The Encyclopaedia Britannica, Vol. VIII, 1894, p. 7.
3. Ref. 2, Vol. XXIV, p. 284.
4. Ref. 2, Vol. VIII, p. 104.
5. IEEE Spectrum, Charles Wheatstone: genius remembered, W. D.
Jones, (ed.), March 1998, pp. 68T468T7.
6. Ref. 2, Vol. XXIV, p. 284.
7. Websters Third New International Dictionary (Unabridged),
Springfield, MA: G. & C. Merriam, 1961.
8. Ref. 2, Vol. VIII, p. 13.
9. Model R-500 Compound Regulated Dual Power Supply, Data
Sheet, G. A. Philbrick Researches, Boston, 1961.
10. Product Information Bulletin PIB 35.35 for RA1 Ref-Amp, General Electric Corp., 1972.

352

VOLTAMPERE METERS

11. Catalog, Cramer Electronics, Newton, MA, 1972, pp. 7577.

12. Catalog, Newark Electronics, Chicago, IL, 1997, pp. 8387.
13. LX5600 data sheet, National Semiconductor Corp., Santa Clara,
CA, 1972.
14. LM129 and LM199 data sheets, National Semiconductor Corp.,
Santa Clara, CA, 1974.
15. LT1021 data sheet, Linear Technology Corp., Milpitas, CA, 1984.
16. LM169 data sheet, National Semiconductor Corp., 1985.
17. LTZ1000 data sheet and applications notes, Linear Technology
Corp., Milpitas, CA., 1984.
18. B. Gilbert, A high-accuracy analog multiplier, IEEE Int. Solid
State Circuits Conf., 1974, pp. 128129.
19. AD560 data sheet, Analog Devices Inc., Norwood MA: 1977.
20. D. Hilbiber, A high-stability reference, IEEE Int. Solid-State Circuits Conf., 1964, pp. 3233.
21. LM113 data sheet, National Semiconductor Corp., Santa Clara,
CA.
22. R. J. Widlar, New developments in IC voltage regulators, IEEE
Int. Solid-State Circuits Conf., 1970, pp. 158159.
23. R. J. Widlar, An exact expression for the thermal variation of the
emitterbase voltage of bipolar transistors, Proc. IEEE, Jan.
1967.
24. A. P. Brokaw, A simple 3-terminal bandgap reference, IEEE J.
Solid-State Circuits, SC-9: 288293, 1974.
25. LM117 data sheet, National Semiconductor Corp., Santa Clara,
CA, 1975.
26. R. A. Pease, The design of band-gap reference circuits: Trials and
tribulations, National Semiconductor Corp., IEEE Bipolar Circuits and Technology Meeting [Online], 1990. Available www:
http://www.national.com/rap/Application/0,1127,24,00.html
27. A. P. Brokaw, Bandgap voltage reference with curvature correction,
U.S. Patent No. 4,250,445, Feb. 10, 1981.
28. LM10 data sheet, National Semiconductor Corp., 1976.
29. R. J. Widlar, Temperature compensated bandgap IC voltage references, U.S. Patent No. 4,249,122, Feb. 3, 1981.
30. C. T. Nelson, Celsius electronic thermometer circuit, U.S. Patent
No. 4,497,586, Feb. 5, 1985.
31. LM35 data sheet, National Semiconductor Corp., 1983.
32. C. T. Nelson, Nonlinearity correction circuit for bandgap reference,
U.S. Patent No. 4,603,291, July 29, 1986.
33. LT1019 data sheet, Linear Technology Corp., Milpitas, CA, 1984.
34. ADR291 data sheet, Analog Devices, Inc., Norwood, MA, 1997.
35. VRE100/101/102 data sheet, Thaler Corp., Tucson, AZ.
36. J. Res. Nat. Inst. Standards and Technol., 94 (2): para. 2.3, 1989.
37. NIST Technical Note 1263 on the Quantum Hall Effect, National
Institute of Standards and Technology, June 1989 p. 2.

ROBERT A. PEASE
National Semiconductor Corp.

VOLTAGE SAG. See POWER QUALITY.

VOLTAGE STABILITY. See POWER SYSTEM STABILITY.

592

WIDEBAND AMPLIFIERS

WIDEBAND AMPLIFIERS

Table 1. Bandwidth Values for Selected Electronic Signals

When analyzing amplifiers mathematically, it is convenient

to assume that the gain calculations are not affected by the
reactive elements that might be present in the circuit. However, in reality, capacitances and inductances play a major
role in determining how the amplifier performs over a range
of frequencies. The effect of inductances can be minimized but
it is impossible to ignore the presence of capacitances. This
effect is more pronounced particularly while analyzing
multistage amplifiers. Coupling capacitors and bypass capacitors can reduce the gain of an amplifier at lower or higher
frequencies, because the capacitive reactance is inversely proportional to the frequency. In other words, as the frequency
increases, the capacitive reactance decreases because
Xc =

1
j(2 fC)

Therefore, if there is a grounded bypass capacitor, signal currents may be inadvertently diverted to ground instead of being transmitted to the output. This is because bypass capacitors offer low reactances to signal currents at higher
frequencies. However, the bypass capacitors offer high reactances to signals at lower frequencies, and therefore diversion of such currents to ground does not pose a major
problem.
Figure 1 is a representation of a frequency plot of an amplifier. Here, the output voltage or power gain is plotted
against a range of frequencies (for a given constant input voltage). The frequency axis is normally plotted on a logarithmic
scale. The unit for the y axis is decibels (dB); the number of
decibels of gain is given by
20 log10

VO
VI

10 log10

PO
PI

or

Signal Type
Electrocardiograms
Audio signals (human ear)
AM radio waves
FM radio waves
Microwave and satellite signals

0.05 to 100 Hz
20 Hz to 15,000 Hz
550 kHz to 1600 kHz
88 MHz to 100 MHz
1 GHz to 50 GHz

amplifier characteristic be assigned a voltage level of Vflat.

Then the frequencies at which voltage levels have dropped to
0.707Vflat are denoted by f L and f H. The range of frequencies
that lies between f L and f H is known as the bandwidth. In
other words, the bandwidth can be defined as the frequency
range over which the amplifier gain remains within 29.3% of
its maximum value (3 dB level, or 1 0.707 0.293).
The bandwidth of an amplifier depends upon the applications and signal type involved. Bandwidth values for some
selected electronic signals are given in Table 1.
PRINCIPLES OF FEEDBACK
For a simple amplifier the voltage gain is defined as the ratio
of output voltage to input voltage. This is written as AV
VO /VI as shown in Fig. 2(a). Addition of a feedback of magnitude , as shown in Fig. 2(b), will result in a modified value
for the voltage gain given by the equation: AV AV /(1
AV). The term AV, called the feedback factor, can be either
positive or negative. A study of the variation of AV with positive as well as negative values of is shown in Fig. 2(c,d). It
is observed that the value of AV becomes infinite with only
10% of positive feedback. However, this should not be viewed
as advantageous, because positive feedback greatly increases
distortion in the output. Mathematically it is true that the
gain approaches infinity; however, in reality, the circuit begins to oscillate. Positive feedback does not find many applications.

Consider the case when PO 
PI. Then the gain in decibels is

10 log10 21

Frequency Range

Input

= 3.0103

voltage VI

Therefore, for audio engineers the point of interest lies where

the gain falls by 3 dB. The frequencies at which this occurs
are called half-power frequencies. Let the flat portion of the

Amplifier
with voltage
gain AV
(a)

Input voltage
VI

Midfrequency level
Vflat
3 dB
0.707 Vflat

Gain (dB)

P
0.5 P

Output
voltage VO

Amplifier
with gain
AV

Output
voltage
with feedback
VO

Feedback VO

(b)

10

102 103 104

Bandwidth (Hz)

105

Figure 1. Frequency response curve of an audio amplifier.

Figure 2. (a) Block diagram of an amplifier with AV VO /VI. (b)

Block diagram of an amplifier with feedback. The dashed line encloses the entire amplifier including the feedback; its gain is AV
VO /VI.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

WIDEBAND AMPLIFIERS

However, in 1932, Harry Nyquist of Bell Telephone Laboratories extended this theory at length and published his famous paper on regenerative theory. His principles laid the
foundation for the development of feedback oscillators. Therefore, positive feedback is also called regenerative feedback.
While designing frequency-selective feedback circuits for
audio amplifiers, one may use positive feedback either as a
bass or as a treble boost.

For very large values of AV the above equation becomes

AV
1/
Consider a case when AV2 (1 0.707)AV 1.707/. Recalculate the new closed-loop gain with negative feedback:

AV 2
1 + AV 2
1.707/
=
1 + (1.707/ )
= 0.707/

AV
2 =

NEGATIVE FEEDBACK
As shown in Figure 2(d), with 10% negative feedback, the
gain AV drops to half of AV. In other words, negative feedback
reduces the overall gain of an amplifier. Therefore it is called
degenerative feedback. Here, a portion of the amplifier output
is fed back to the input in such way that it opposes the input.
Consider the case when AV AV /100. Since the gain in decibels is defined as 20 log10(VO /VI), the reduction of the gain by
a factor of 100 means a loss of 20 log10 
 40 dB. Thus,
expressed in decibels,

Observe that the above equation is independent of AV, which

is the gain without feedback. (also sometimes called the openloop gain). In other words, even though the open-loop gain
falls by a factor 1.707, the closed-loop gain falls only by 3 dB.
Similarly, we can prove

Now we can revisit Fig. 1 and study the frequency response with and without negative feedback. This is shown in
Fig. 3. We can easily see that the bandwidth of the amplifier
has been increased with negative feedback. This is the greatest advantage of negative-feedback amplifiers. In addition,
negative feedback results in stabilized amplifier gain, extended bandwidth, and reduced noise and distortion. In other
words, it is possible to achieve predictable voltage gains with
negative feedback amplifiers. Besides, the resulting amplifiers are very stable.
It is possible to prove that series voltage feedback increases the input impedance of the circuit. The input impedance can be reduced by incorporating a parallel current
feedback.
We can rewrite the previously considered equation incorporating the negative sign as

Percentage distortion without negative feedback

1 + AV

Negative feedback also helps in reducing the circuit noise.

Thus, the signal-to-noise ratio is greatly improved:
(S/N)feedback = (1 + AV )(S/N)no feedback

MILLER EFFECT
While designing amplifiers, engineers may assume that the
internal capacitances in the transistor are very small compared to the external capacitances. But in reality, capacitances do exist between the base and emitter (CBE) as well as
between base and collector (CBC). This is shown in Fig. 4. It
can be mathematically shown that the total input capacitance
CI = CBE + (1 + AV )(CBC )

AV
1 + AV

In other words, the total input capacitance is the parallel

combination of CBE and (1 AV)CBC. The basecollector capacitance has been amplified by a factor of 1 AV. This is called
the Miller effect.
As mentioned earlier, as the frequency increases, the value
of the total input impedance decreases and thereby the fre-

Without feedback

AV

= 0.707AV

Percentage distortion with negative feedback

AV
= AV 40 dB

AV
=

593

AV/ 2 = AV3 dB
With negative feedback

AV
AV 3 dB = AV/ 2
Voltage gain
in decibles

VCC
RC
IO

Frequency (log scale)

f L1

f L2

Bandwidth
(no feedback)
Bandwidth
(with feedback)

CBC

f H1

VIN

VO

CBE

f H2

Figure 3. Bandwidth increases for an amplifier with negative

feedback.

Figure 4. Miller effect with the transistor internal capacitances CBC

and CBE.

594

WIENER FILTERS

VCC
Coupling
capacitor

RC
VO

VIN
CC
RE

CE
Emitter
by-pass
capacitor

Figure 5. The impedances of CC and CE are large at low frequencies,

and portions of signal voltages may be lost.

quency response characteristics are affected. The Miller effect

is especially pronounced with common-emitter amplifiers, because they introduce a 180 phase shift between the input and
the output. For example, the values of CBE and CBC may be
small, say 5 pF and 4 pF. But when the transistor is used in
an amplifier with a gain of 99, the total input capacitance will
be large enough to affect the frequency output characteristics
of the amplifier. This is because
CI = CBE + (1 + AV )(CBC )
= 5 + (1 + 99)(4) = 405 pF
It is recalled that at low frequencies the coupling capacitor
and the emitter bypass capacitors offer high impedances and
therefore portions of signal voltage may be lost, as shown in
Fig. 5.
The Miller effect is thus an extremely important concept
in discussing feedback. Equations for calculating the Miller
input impedance and Miller output impedance can be developed, and are given below:

ZI,Miller =
ZO,Miller =

Zfeedback
1 AV

AV
Zfeedback
AV
1

where AV is the voltage gain with feedback Zfeedback

MYSORE NARAYANAN
Miami University

594

WIENER FILTERS

formation. A Wiener filter, in particular, is a specialized linear

(nonadaptive) filter, and it is optimal under certain idealized
conditions. It was named after its developer, the famous
mathematician and originator of the field of cybernetics, Norbert Wiener, who derived and helped implement the first filter during World War II.
Estimation is the process of inferring the value(s) of a variable of interest, using some relevant measurements. Almost
everything around us can be considered a dynamic system.
Nearly all physical systems have some dynamic nature, and
precise estimation of any quantity that relates to them must
take into consideration their dynamics. For example, the flow
dynamics of a river system can be used to estimate future
flood levels in surrounding communities, and the accurate position of a spacecraft can be estimated using radar tracking
information. Furthermore, ship navigation can be accomplished by estimation methods using gyroscopic measurements.
Estimation of a quantity or a variable can take numerous
forms depending on the problems being studied. In particular,
when dealing with dynamic systems, estimation problems can
be classified into three categories (1):
1. State estimation, the process of inferring the state(s) (or
outputs related to the state) of a system using measurements collected from the system itself and a prespecified mathematical model of the system,
2. System identification, the process of inferring a mathematical model of a system using measurements collected from the system itself, and,
3. Adaptive estimation, the process of simultaneous state
estimation and system identification.

WIENER FILTERS
In dealing with the operational aspects of dynamic and static
(or memoryless) physical systems one often has to process
many measured (observed) signals for extracting meaningful
and useful information regarding the system under investigation. Such a sequence of signal processing steps (whether analog or digital, and whether implemented in hardware or software) forms the thrust of the field of estimation. Strictly
speaking, filtering is a special form of estimation. Filters (or
more generally estimators) are devices (hardware and/or software) that process noisy measurements to extract useful in-

The function performed by Wiener filters is that of a specialized state estimation. In an effort to put these filters in the
proper framework, an attempt must be made to further categorize state estimation. For the remainder of this article state
estimation will refer to the estimation of system states or outputs, where the latter are functions of the states.
In state estimation problems, the estimate of the variable
of interest is usually denoted by x(tt), indicating the estimated value at time t given measurements up to and including the time t. The actual, and quite often unknown, value of
the variable of interest is denoted by x(t), and the measurements are usually denoted by y(t) in the case of a system output and u(t) in the case of a system input. The estimate of
the measured output y(t) is usually denoted y(t/t). In this article and in most recent presentations of this subject, all developments are presented in the discrete-time domain (1a).
The wide use of digital computers and the increased use of
digital signal processors makes this presentation the preferred approach. The concepts presented are equally applicable in the continuous-time domain. In fact, the original concepts about optimal predictors and optimal filters were first
derived in the continuous-time domain. The interested reader
is referred to Grewal and Andrews (2) and Wiener (3). The
following three types of state estimation problems can now be
defined (1,4):
1. Smoothing: given the measurements, y(t ) for positive integer, up to and including the time instant (t

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

WIENER FILTERS

WIENER FILTERSLINEAR OPTIMAL FILTERING

A more detailed treatment of Wiener filters is now presented
by first defining the precise estimation problem they address.

Filtering Problem Statement

As mentioned at the beginning of this article, the Wiener filter belongs to the class of linear (nonadaptive) optimal filters.
Considering the discrete-time treatment of a single-input
(and a single-output) filter, let us assume that at time t the
signal to be filtered (the input to the filter) consists of an infinite number of measured input samples u(t), u(t 1), . . ..
The input samples are assumed to be random variables, and,
therefore, the input signal represents a random (or stochastic)
process characterized by some known statistics. The filter is
described by an infinite number of constant coefficients, b0,
b1, . . ., known as the filter impulse response. At any discrete-time instant t, the filter generates an output (the filtered signal) denoted by y(t/t). This output is an estimate of
the desired filter response denoted by y(t). Both the filter input and the desired filter response must be known in order to
design a Wiener filter. However, only the former is needed for
filter operation. The deviation of the filter output from the
desired filter response gives rise to the estimation error,
which becomes the key measure of filter performance. A block
diagram representation of a Wiener filter is shown in Fig. 1.
Thus far the only assumption that has been made regarding Wiener filters is of their linear structure. The fact that the
filter operates in the discrete-time domain is not a restrictive
assumption, rather a necessity of the digital world. The continuous-time version of the filter can be developed at the expense of some mathematical complications. Additionally, and

u(t)

bo

z1
+
u(t 1)

z1

b1

.
.
.

.
.
.

Desired
output
y(t)
Output
+
^
y(t/t)

+
Estimation
error
e (t)

.
u(0)

In defining state estimation, it is assumed that there exists

a relation (dynamic and/or static) between the measurements y(t) and the state x(t) to be estimated. In many systems encountered in engineering, however, one does not always have an accurate knowledge of this relation. Therefore,
assumptions must be made regarding the dynamics of the
system, and these assumptions usually take the form of a
mathematical model of the system investigated. The mathematical model (or relation) between the measurements and
the estimated variables can be of varying complexity, ranging
from extracting a signal corrupted by additive white Gaussian
sensor noise, to estimating a time-varying parameter in a
complex process control problem. The nature of this relationship dictates the complexity of the state estimation problem
to be solved.
Even though the earliest sign of an estimation theory can
be traced back to the mid-17th century work of Galileo Galilei, credit for the origin of linear estimation theory is given to
Karl Friedrich Gauss, for his late-18th century invention
called the method of least squares, to study the motion of
heavenly bodies. In one way or another the least squares
method by Gauss forms the basis for a number of estimation
theories developed in the ensuing 200 years, including the
Kalman filter (5). Following the work of Gauss, the next major breakthrough in estimation theory came from the work of
A. N. Kolmogorov in 1941 and N. Wiener in 1942. In the early
years of World War II, Wiener was involved in a military project at the Massachusetts Institute of Technology (MIT) regarding the design of automatic controllers for directing antiaircraft fire using radar information. As the speeds of the
airplane and the bullet were comparable, it was necessary to
account for the motion of the airplane by shooting the bullet
into the future. Therefore, the controller needed to predict
the future position of the airplane using noisy radar tracking
information. This work led first to the development of a linear
optimum predictor, followed by a linear optimum filter, the
so-called Wiener filter. Both the predictor and the filter were
optimal in the mean-squared sense and they were derived in
the continuous-time domain. The filter design equations were
solved in the frequency domain (3). Later in 1947, Levinson
formulated the Wiener filter in the discrete-time domain (6).
An analogous, but by no means identical, derivation of the
optimal linear predictor was developed by Kolmogorov in the
discrete-time domain (7), prior to the widespread publication
of the work by Wiener in 1949.

This is followed by a brief mathematical description of the

filter structure and the method used to design it. The section
ends with a brief treatment of Wiener filter performance. For
the interested reader, additional details of the Wiener filter
derivation can be found in the excellent textbook by Haykin
(8). A mathematically rigorous treatment of the continuoustime filter derivation for scalar and vector signals can be
found in the original text by Wiener (3).

), the state estimate x(tt ) at a past time t is determined.

2. Filtering: given the measurements, y(t), up to and including the time instant t, the state estimate x(tt), at
the present time t is determined.
3. Prediction: given the measurements y(t ), up to and
including the time instant (t ), the state estimate
x(tt ), at the future time t is determined. If 1,
this is referred to as single-step-ahead prediction, and
if p, where p 1, this is referred to as p-step-ahead
or multistep-ahead prediction.

595

bt

.
.
.
Figure 1. Block diagram of infinite impulse response (IIR) implementation of a Wiener filter.

596

WIENER FILTERS

without loss of generality, an implicit assumption is made regarding real-valued observations. The Wiener filter can be derived for complex-valued observations, commonly encountered
in communications applications. The interested reader is referred to the Wiener filter presentation by Haykin (8), which
assumes complex-valued observations.
The filtering problem addressed by Wiener filters can now
be defined as follows:
Design a linear (discrete-time) filter by completely defining all of
its unknown parameters, such that for any given set of inputs
u(t), u(t 1), . . ., the estimation error, defined as the difference
between the desired filter response, y(t), and the filter output,
y(t/t), is minimized in some statistical sense.

In order to solve the forementioned problem for filter design, two important issues must be dealt with as follows:
1. How to select (or restrict) the structure of the filter impulse response?
2. What statistical criterion to use for optimizing the filter design?
The first issue must deal with whether the filter should
have a finite (FIR) or an infinite impulse response (IIR). That
is, whether the filter should have only feedforward, or both
feedforward and feedback signal flow paths. This is of
great practical implication because design and implementation of IIR filters introduces many complications. Therefore,
even though the general theory of Wiener filters was developed based on IIR filters, practical applications are usually
treated employing some form of a FIR filter. The reason for
this choice is the inherent stability of FIR filters, compared
to the potential instabilities that can result from IIR filters.
Nevertheless, properly designed IIR filters are guaranteed to
be stable. Adaptation of such filters, however, raises serious
complications.
The second issue is of mathematical importance. The
choice of a complex statistical criterion to be optimized results
in increased complexity in filter design equations. Generally,
in designing a filter a cost (or objective) function is selected
that is then minimized by choosing the appropriate filter parameters. The choice of the cost function varies, although the
following are possible options:
1. Mean-square estimation error;
2. Expectation of the absolute value of the estimation error; and
3. Expectation of higher powers of the absolute value of
the estimation error.
Additionally, combinations of the above objective functions
are often used in attempts to minimize the effects of bad data.
This is the subject of robust estimation, and the interested
reader is referred to Soderstrom and Stoica (9) and Ljung
(10). The mean-square estimation error is a popular choice,
because it results in a convex optimization problem and a relatively simple set of filter design equations.
Filter Theory and Design
To develop the equations used in the design of Wiener filters,
an expression for the filter output must first be developed. Let

us now return to the depiction of Fig. 1. Considering an infinite observation horizon for the filter inputs u(t), u(t 1),
. . ., and an IIR filter structure described by the coefficients
b0, b1, . . ., we can express the filter response y(t/t) as
y(t/t)

bk u(t k), t = 0, 1, 2, . . .

(1)

k=0

Filter Theory Development. The objective of a Wiener filter

is to provide an optimal estimate of the desired filter response y(t), where the estimate is optimal in some meansquared sense. To obtain an optimal estimate, the estimation
error is defined as
e(t) y(t) y(t/t)

(2)

The estimation error is utilized in the following filter objective

function to be minimized:
J = E{e2 (t)}

(3)

Furthermore, in order to proceed with the Wiener filter development, it is assumed that the filter input and desired filter
response, u(t) and y(t) respectively, are zero-mean jointly
(wide-sense) stationary stochastic processes. For definitions
and other clarifications regarding stationary stochastic processes, the reader is referred to Papoulis (11).
The filter objective function J can now be minimized by
computing the IIR filter coefficients bk such that the gradient
of J with respect to each one coefficient becomes simultaneously zero. As a result of simultaneously setting all of the
gradients to zero, the optimality of the Wiener filter is in the
mean-squared-error sense. Taking the derivative of the objective function given by Eq. (3) with respect to the IIR filter
coefficients b0, b1, . . .. and setting them to zero we obtain


J
e(t)
= 0, k = 0, 1, 2, . . .
(4)
k J =
= E 2e(t)
bk
bk
Using the IIR filter response expressed by Eq. (1) and the
estimation error of Eq. (2), the error gradient in Eq. (4) can
further be expressed as
y(t/t)

e(t)
=
= u(t k)
bk
bk

(5)

Utilizing this expression of the gradient, the following condition is obtained for minimizing the filter objective J:
k J = 2E{e(t)u(t k)} = 0

(6)

In light of the objective function convexity, the filter becomes optimal whenever Eq. (6) is satisfied. Let us denote
with a zero subscript the characteristics of the optimal filter.
That is, bok represents the optimal IIR filter coefficients,
yo(t/t) represents the optimal filter response (or filter output),
and eo(t) represents the optimal filter estimation error. The
value of the objective function for the optimal filter is denoted
by Jmin. The optimality conditions for the Wiener filter can
now be expressed as
E{eo (t)u(t k)} = 0, k = 0, 1, 2, . . .

(7)

WIENER FILTERS

and the minimum mean-squared estimation error is given by

M1

Jmin = E{e2o (t)}

j=0

(8)

Equation (7) brings-up some important points regarding

the operation of optimal filters. Specifically, this equation implies that if the filter operates in its optimal condition, then
at each time t the (optimal) estimation error is orthogonal
with the filter input. In other words, at each time t the optimal estimation error is uncorrelated with the filter input. The
implication of this observation is consistent with filter optimality. It indicates that if a filter operates in optimal conditions, then all useful information carried by the filter inputs
must have been extracted by the filter, and must appear in
the filter response. The (optimal) estimation error must contain no information that is correlated with the filter input;
rather it must contain only information that could not have
been extracted by the filter.
Filter Design Equations. The previous section presented the
development of the Wiener filter theory, but it did not address
issues related to the design of such filters. The filter optimality condition, Eq. (7), becomes the starting point for Wiener filter design. The IIR filter structure can still be used
prior to the selection of a more appropriate structure.
In view of filter response Eq. (1), and the definition of Eq.
(2), substitution of the optimal estimation error in Eq. (7) results in the following expression:
E{u(t k)(y(t)

bok u(t k))} = 0, k = 0, 1, 2, . . .

(9)

597

bo j R( j k) = P(k), k = 0, 1, 2, . . . (M 1)

(12)

where bo0, bo1, . . ., bo(M1) are the optimal FIR filter coefficients. The assumed FIR filter structure is depicted in Fig. 2.
The WienerHopf equations, Eq. (12), can be solved using
one of the many numerical analysis methods for linear algebraic equations. These equations can be reformulated in matrix form
Rbo = P

(13)

where the autocorrelation matrix is defined as

R(0)

R(1)
R=
..

.
R(M 1)

R(1)
R(0)
..
.
R(M 2)

..
.

R(M 1)

R(M 2)

..

(14)

R(0)

the cross-correlation matrix is defined as

P = [P(0), P(1), . . ., P(1 M)]T

(15)

and where the vector containing the filter coefficients is defined as

bo = [bo0 , bo1 , . . ., bo(M1)]T

(16)

Assuming the correlation matrix R is nonsingular, Eq. (13)

can now be solved for bo

k=0

Further expanding and manipulating the expectations in the

above equation results in

bo j E{u(t k)u(t j)} = E{u(t k)y(t)}, k = 0, 1, 2, . . .

j=0

(10)
Notice that the preceding equation includes the unknown filter coefficients and observed quantities. The expectations
present in Eq. (10) are the autocorrelation of the filter input
and the cross correlation between the filter input and the desired filter response. Defining the forementioned autocorrelation and cross correlation by R( j k) and P(k), respectively,
Eq. (10) can be expressed as

bo j R( j k) = P(k), k = 0, 1, 2, . . .

bo = R1 P

(17)

representing the coefficients of the optimal filter. Design of an

optimal Wiener filter requires computation of the right-hand
side of Eq. (17). This computation requires knowledge of the
autocorrelation and cross-correlation matrices R and P. Both
of these matrices depend on observations of the filter input
and the desired filter response.

u(t)

bo

z1
+

(11)

j=0

The set of (infinite) equations given by Eq. (11) is called the

WienerHopf equations.
The structure of the assumed filter must be further simplified before attempting to solve the design equations in Eq.
(11). The solution to these equations can be greatly simplified
by further assumptions regarding the optimal filter structure.
It should be noted that in the original formulation by Wiener,
Eq. (11) was derived in the continuous-time domain at the
expense of significant mathematical complications. Assuming
an M-th order FIR filter, Eq. (11) is simplified as

u(t 1)

z1

b1

.
.
.

.
.
.

Desired
output
y(t)
Output
+
^
y(t/t)

+
Estimation
error
e(t)

u(0)
bM 1
u(t M + 1)
Figure 2. Finite impulse response (FIR) implementation of a Wiener filter.

598

WIENER FILTERS

Filter Performance

J(b)k

The performance of Wiener filters can be explored by expressing the filter objective function in terms of the filter parameters, that is, in terms of the impulse response coefficients b0,
b1, . . ., bM1. Then, the objective function can be investigated
as a function of these coefficients.
For the M-th order FIR Wiener filter shown in Fig. 2, let
us rewrite the objective function of Eq. (3) in terms of the
filter inputs and the desired filter response as follows:

J = E{(y(t)

M1

bk u(t k))2 }

(18)

Optimal
Wiener filter

Jmin
Suboptimal filters

k=0

bok

This equation can be expanded as

J = E{y2 (t)} 2

M1

M1

M1

Figure 3. Wiener filter objective function depicting the impact of filter parameters on filter optimality.

bk E{u(t k)y(t)}

k=0

(19)

b2k E{u(t k)u(t j)}

k=0 j=0

Now, using the definition for the variance

y2 = E{y2 (t)}

(20)

along with the autocorrelation and cross correlation, R( j

k) and P(k), the objective function can be rewritten as

J = y2 2

M1


k=0

bk P(k) +

bk

M1

M1

b2k R( j k)

not discussed in this article.) In practical applications and irrespective of the selected filter structure, use of suboptimal
filters is quite often inevitable because of violations in the
assumptions underlying the optimal Wiener filter, such as the
assumptions of filter input and desired response stationarity
and other practical implementation considerations.
The filter performance analysis can be taken a step further
to determine the optimal filter performance in terms of the
statistics of the filter input and the desired filter response.
The optimal filter response can be expressed as

(21)

yo (t/t) =

k=0 j=0

M1

bok u(t k) = bTo u(t)

(24)

k=0

Equation (21) can now be written in vector form as

J(b) = y2 2bT P + bT Rb

(22)

where the objective function dependence on the filter parameters b is explicitly shown, and where the other parameters
are as previously defined.
In view of the joint stationarity assumptions placed upon
the filter input and the desired filter response signals, the
objective function equation (21) or (22) is a quadratic function
of the filter impulse response parameters bk. Therefore, performance optimization of the Wiener filter is a quadratic optimization problem with a unique minimum. This unique minimum Jmin occurs when the filter parameter values correspond
to the optimal filter bo such that
Jmin = J(bo )

(23)

The shape of the quadratic performance index depicting the

optimal and suboptimal filters is shown in Fig. 3. The optimal
filter parameters are computed by solving Eq. (17) for bks. For
other values of the parameters bk, the resulting filter is suboptimal. In fact, a truly optimal Wiener filter is realized if M is
allowed to approach infinity, that is, M . Therefore, all
FIR implementations of a Wiener filter result in suboptimal
performance. This practical limitation imposed by the need to
select a finite M can be overcome by allowing feedback
paths in the filter structure. Feedback allows implementation
of a Wiener filter via finite-order IIR filters. (IIR filters are

The filter response, a function of the filter input, is a stochastic process itself. The variance of the filter response can be
expressed as
y2 = E{bTo u(t)uT (t)bo } = bTo E{u(t)uT (t)}bo = bTo Rbo

(25)

or, using Eqs. (13) and (17),

y2 = bTo P = PT bo = PT R1 P

(26)

Applying the definition given in Ref. 2 for the optimal filter,

the desired filter response can be expressed as
y(t) = yo (t/t) + eo (t)

(27)

Taking the expectation of the square of both sides of Eq. (27)

results in the following relation between the variance of the
filter response and the desired response:
y2 = y2 + Jmin

(28)

Using Eqs. (26) and (28), the minimum mean-squared error

of the objective function can be expressed as
Jmin = y2 PT R1 P = y2 PT bo

(29)

WIENER FILTERS

Defining the normalized mean-squared error of the optimal

filter as
0 =

Jmin
y2

(30)

Eq. (28) can be expressed as

0 = 1

y2

(31)

y2

Equation (31) is a performance index for the optimal Wiener

filter, expressed as a function of the variance of the filter response and the desired filter response. In view of Eq. (28),
this performance index takes values in the range
0 0 1

(32)

If the optimal filter results in zero mean-squared estimation

error, then the performance index 0 becomes zero. As the
mean-squared estimation error of the optimal filter increases,
the performance index 0 approaches one. The variation in the
performance index for a family of Wiener filters is depicted in
Fig. 4.
It should be noted that the range given by Eq. (32) is valid
only for the optimal Wiener filter. For such a filter, the crosscorrelation between the filter error and filter output is zero,
resulting in the expression of Eq. (28). For suboptimal filters,
the term E y(t/t) e(t) must be included on the right-handside of Eq. (28). Then, the performance index given by Eq.
(31) does not have an upper-bound of 1.
LIMITATIONS OF WIENER FILTERS
Following the successful application of Wiener filters during
World War II, it became clear that the functionality offered
by such a device (a filter) would be immense in many technological applications. Careful consideration of the filter derivation, however, immediately points out a number of key limitations. The three main assumptions of Wiener filters for
optimal operation are as follows:

J(b)k

J 1min

Optimal
Wiener filters

0
b1ok

bk

Figure 4. Wiener filter performance index depicting famlies of filter

performance curves and location of optimal filters.

599

1. The filter input must consist of an infinite number of

observations;
2. The filter input must be stationary; and
3. The filter output must be related to the filter input by
a linear relation.
Furthermore, for designing an optimal Wiener filter the statistics of the desired filter response must be available, and it
also must be stationary. Finally, there are additional limitations imposed by the underlying theory of Wiener filters, but
these limitations relate to filter implementation.
Nonstationary Finite Duration Signals
A close look at the key assumptions made in deriving the Wiener filter reveals that stationarity of the filter input is required. The desired filter response statistics must also be
available, and further the filter input and the desired filter
response must be zero mean, jointly wide sense stationary.
Stationarity of a stochastic signal implies that its statistical
properties are invariant to a shift in time. Furthermore, these
signals are required to be observed for an infinite observation
interval (or window).
In engineering practice many signals that serve as filter
inputs are not stationary and they are subject to finite observation intervals. This is especially true in control engineering
applications of filters. In such applications the essence of the
filter function is performed during periods in which the system generating the signals to be filtered is undergoing a transient. This results in signals with varying means, rendering
them nonstationary. Additionally, in many engineering applications the desired filter response statistics may not be available. This is further complicated by the requirement of a zero
mean, stationarity desired filter response. Finally, it is worth
mentioning that practical implementation forbids excessively
long observation intervals for all signals involved in the filter operation.
The limitation of Wiener filters in processing nonstationary, finite observation interval signals was well known to
Wiener himself, who during the years following the development of the original linear optimal filter rigorously investigated its possible extensions (12). During the 1950s, many
researchers attempted to extend the applicability of Wiener
filters to nonstationary, finite observation interval signals
with little success. Although some theoretical results were obtained that eliminated these assumptions, the rather complicated results did not find much use in practical filter design.
The two main difficulties were associated with filter update
as the number of observations increased, and the treatment
of the multiple (vector) signal case. Both of these limitations
of the Wiener filters were eliminated by the development of
the Kalman filter. This development made the assumption of
a stationary, infinite observation horizon filter input unnecessary.
Nonlinear Systems
Another limitation of Wiener filters results from the assumed
linear relation between the filter input and the desired filter
response. This implies a linear relation between the filter input and output also. Having a linear structure, Wiener filters
can not effectively address filtering problems in which the fil-

600

WIENER FILTERS

ter inputs and outputs must be related by some nonlinear

functional form. That is, if the filter inputs and the desired
filter response is inherently nonlinear, then use of Wiener filters results in suboptimal filtering.
During the 1950s, Wiener conducted extensive research on
the use of a special class of nonlinear functional form to relate
the filter inputs and the desired filter response. He used the
so-called Volterra series, which was first studied in 1880 as a
generalization of the Taylor series expansion of a function.
Wiener used Volterra series to model the input-output relationship of a system (10). The integral approach of Wieners
formulation of the nonlinear extensions to the Wiener filters,
and the lack of computational capabilities during that period,
limited the application and use of his developments until the
mid-1980s (13).
In engineering practice, and especially in the many industrial applications of filtering and of estimation in general,
nonlinearities are widely encountered facts of life. These nonlinearities are currently handled in an ad hoc manner, because an effective nonlinear filtering method has yet to be
developed. The development of the Extended Kalman Filter
(EKF), as a means to account for nonlinear process and/or
noise dynamics, has not eliminated the problems associated
with practical nonlinear filtering problems at all. The main
reason for this inadequacy is the inherent modeling uncertainties in many nonlinear filtering problems. The modeling
uncertainties render the EKF quite often ineffective. More recently during the 1990s, a different type of functional relation, based on the so-called artificial neural networks, has
shown promise in nonlinear input-output modeling (14). In
principle, the application of these mathematical tools has followed the initial attempts by Wiener on the use of Volterra
series to extend the capabilities of linear optimal filters by
the use of black-box nonlinear models.
Relation to Kalman Filters
The Kalman filter, probably the most significant and technologically influential development in estimation theory during
this century, first appeared in the literature in 1959. It is not
a secret that the Kalman filter was initially developed as a
means of circumventing some of the limitations of the Wiener
filters. The relation between these two filters can be best understood by considering the model-based nature of the filtering operation performed on a signal generated by a system.
In effect, the Wiener filter attempts to model the filter inputs
and outputs by an inputoutput (or transfer function)
model. On the contrary, the Kalman filter poses the following
question: Why not apply the concept of state-space to Wiener
filters? The answer to this question was the mathematical development of linear optimal filtering theory based on statespace models. In doing so, many of the limitations imposed
by the Wiener filter are eliminated. Some of the similarities
and relative advantages of the Wiener and Kalman filters can
be summarized as follows (2):

3. The Wiener filter assumes stationary stochastic processes as filter inputs, whereas the inputs to the Kalman filter may be nonstationary.
4. The Wiener filter assumes the availability of a desired
filter response, whereas the Kalman filter assumes the
availability of a model of the system to be filtered.
5. The Wiener filter inputs and outputs are related using
an inputoutput (or transfer function) model represented by the impulse response coefficients. The Kalman filter inputs and outputs are related by a statespace model.
6. Derivation of the linear optimum filter based on the
principles of Kalman filtering requires less mathematical sophistication than the equivalent derivation using
the principles of Wiener filtering.
7. The Kalman filter provides a better framework than the
Wiener filter for the detection and rejection of outliers
(or bad data).
8. The Wiener filter implementation in analog electronics
can operate at much higher effective throughput than
the (digital) Kalman filter.
9. The Kalman filter is best suited for digital implementation. Although this implementation might be slower, it
offers greater accuracy than that which is achievable
with analog filters.
Variations of the Wiener Filter
The first true variation of the Wiener filter came from Levinson in 1947, who reformulated the original derivation in the
discrete-time domain (6). During the 1950s several attempts
were made to relax the infinite observation horizon and the
stationarity requirements of the original Wiener filter formulation. These attempts resulted in mathematically very complex variations of the Wiener filter. Furthermore, handling of
the vector case was excessively difficult. These complications
resulted in Swerlings early attempts at recursive algorithms
(8). They were followed by Kalmans derivation of the Wiener
filter in the time-domain.
One of the most widely used variants of the Wiener filter is
the so-called linearly constrained minimum variance (LCMV)
filter. The derivation of this filter was motivated by the need
to relax the presence of the desired filter response in Wiener
filter design. In some filtering applications the desired filter
response is not always known or available. Furthermore, in
some applications it is desired to minimize a mean-squared
error criterion subject to some constraints. In such circumstances, the LCMV is utilized as an alternative to Wiener filters. Design of an LCMV filter requires the solution of a constrained optimization problem. This is accomplished by using
one of the many constrained optimization methods, such as
the method of Lagrange multipliers. Another variation of
Wiener filters is the linear optimal predictor, which preceded
the development of the Wiener filter and which laid the foundations of the linear optimal filtering theory.

1. Both the Wiener and Kalman filters have linear structure.

WIENER FILTER APPLICATIONS

2. The Wiener filter assumes an infinite observation horizon for the filter inputs, compared to the Kalman filter
assumption of a finite observation horizon.

Since its introduction in the 1940s, the Wiener filter has

found many practical applications in science and technology.
As with all other filters that were developed following World

WIENER FILTERS

War II, the Wiener filter extracts information from noisy signals. Nevertheless, the inherent assumptions made in deriving the Wiener filter place certain limitations on its applicability to many practical problems. In fact, these limitations
have been among the primary motivations for the development of the Kalman filter.
Despite the apparent superiority of the Kalman filter, it is
still advantageous to implement a Wiener filter when proper
conditions arise. Such conditions include either filtering stationary or quasi-stationary signals, or equivalently filtering
signals from systems operating under steady-state or quasisteady-state conditions.
General Uses
In general, Wiener filters are applicable to problems in which
all signals of interest can be assumed stationary, and the desired filter response can be either expressed analytically and/
or measured. These preconditions limit, to a large extent, the
use of Wiener filters. For example, many filtering problems
encountered in control applications are characterized by nonstationary signals. Furthermore, very often the desired filter
response and its statistics are not explicitly known and/or
measured. An exception to this class of problems is the area
of target-tracking and navigation, the very first application of
Wiener filters. Additionally, Wiener filters have found many
applications in communication systems, for example, in channel equalization and beamforming problems. Wiener filters
have also found wide use in two-dimensional image processing applications.
In tracking applications, Wiener filters are used to estimate the position, velocity, and acceleration of a maneuvering
target from noisy measurements. The target being tracked
may be an aircraft, a missile, or a ship. Radar and other instruments measure the range, azimuth, and elevation angles
of the target. If a Doppler radar is available, then range-rate
information is also included. If the target moves at constant
velocity, then the Wiener filter position estimates might be
quite accurate. Because of the limitations inherent in the
Wiener filter, however, evasive maneuvers of the target cannot be accounted for with accuracy. Estimation of target position is usually part of an overall system to improve the accuracy of a fire control system.
A Simple Example
In this section we present a very simplified example of the
Wiener filter in the discrete-time domain. As the example
progresses, comments regarding realistic applications will be
made to inform the reader of some of the difficulties involved
in real-world filtering applications.
The three key issues involved in Wiener filter design are:

601

3. How is the order of the Wiener filter selected?

In many real-world filtering applications the statistics of the
desired response are not easily quantified. Furthermore, in
many instances the desired response may not be a well-behaved stochastic process. Similarly, the relation between the
desired response and the inputs to the Wiener filter may not
be simple. As a result, the third forementioned issue, the order of the Wiener filter, is not easily determined.
For the sake of this example, let us assume that the desired filter response is generated as the output of a zeromean, white-noise driven linear time-invariant system with a
transfer function H(z). The white-noise is denoted by w(t).
This assumption greatly simplifies the analysis of the statistical properties of the desired filter response. Furthermore, let
us assume that the desired response and the filter inputs are
also related by a linear time-invariant system with a transfer
function G(z), corrupted by additive zero-mean, white noise.
It is desired to design a Wiener filter such that the difference
between the filter response y(t/t) and the desired response
y(t) is minimized in the mean-squared sense. The block diagram for this example is shown in Fig. 5.
Let us now assume, for simplicity, that the desired filter
response is generated by the following first-order transfer
function:
H(z) =

1
1
=
1 + h1 z1
1 + 0.5z1

(33)

where the zero-mean, white noise input w(t) driving H(z) has
a variance w2 0.35. It is further assumed that the desired
response is related to the filter input by the following, also
first-order, transfer function:
G(z) =

1
1
=
1
1 + g1 z
1 0.75z1

(34)

The output of the transfer function G(z) is further corrupted

by the additive zero-mean, white noise n(t), with a variance
n2 0.15.
To design a Wiener filter, we need to characterize two correlation functions related to the desired filter response and
the filter input. Specifically, we need to compute the autocorrelation R of the filter input, u(t), and the cross-correlation
P between the filter input and the desired response y(t). Additionally, we need to compute the variance of the desired response. This is accomplished by observing that the variance
of the output of a linear filter driven by white noise is related
to the variance of its input [for details of the appropriate
equations, the reader is referred to Haykin (8) and Papoulis
(9)]. This calculation results in
y2 =

1. What are the statistics of the desired response?

2. How is the filter input related to the desired response?

w2
= 0.47
1 h21

(35)

n(t)
+
x(t) +

y(t)

w (t)
H(z)

G(z)

u(t)

Wiener
Filter

^
y(t/t)

Figure 5. Wiener filter example block diagram.

WIENER FILTERS

In calculating the correlation matrices, it helps to observe

that the two transfer functions specified in the preceding completely define the structural information needed for the design of the Wiener filter. The Wiener filter input can be expressed as the response of a white-noise driven second-order
filter G(z)H(z), corrupted by additive noise. Therefore, the autocorrelation matrix of the filter input is a two-dimensional
matrix and the Wiener filter can be chosen as a second-order
FIR filter. For more realistic problems, the precise characterization of the transfer functions G(z) and H(z) makes filter
design a challenging task.
Let us now return to the calculation of the correlation matrices. The autocorrelation matrix R can be calculated as the
sum of the autocorrelations of the uncorrupted response of
G(z) and additive noise n(t). Furthermore, the autocorrelation
of the uncorrupted response of G(z) can be calculated in terms
of the statistical properties of the desired filter response,
y(t), and the coefficients of G(z). The cross-correlation matrix
P can be calculated using similar arguments, in terms of the
statistical properties of the desired response and the filter input. For this example these calculations result in the following numerical results:


0.6348
0.4
R=
(36)
0.4
0.6348

2
2

1.5

1
0.5
b1

602

0
0.5

1
6
1.5

8
2 9
2 1.5

0.5

0
b0

0.5

1.5

Figure 7. Error performance contours for Wiener filter example.

Jmin = 0.47 [0.1848 0.0364][0.4230 0.2092]T = 0.3961

(40)

The Wiener filter coefficients can now be computed using Eq.

(17),

The variations in the filter error performance, from optimal

to suboptimal, are best visualized by the contour plot shown
in Fig. 7. The objective function value corresponding to the
optimal filter is at the center of the ellipse depicted by contour
value 1.

bo = R1 P = [0.4320 0.2092]T

A PRACTICAL EXAMPLE: ELECTRIC MOTOR RESPONSE FILTER

P = [0.1848 0.0364]

(37)

(38)

In view of Eq. (22), the filter objective function J(b0, b1),

can now be expressed in terms of the filter coefficients

J(b0 , b1 ) = 0.47 0.1848b0 0.0364b1 + 0.8b0 b1

(39)

+ 0.6348(b20 + b21 )

The error performance surface expressed by Eq. (39) is depicted in Fig. 6.

The optimal Wiener filter, corresponding to the filter coefficients given by Eq. (38), has minimum mean-squared error
given by Eq. (29). The numerical value of this mean-squared
error is

10

In the final section of this article, we present a more practicalthough still simplifiedapplication of a Wiener filter. In
particular, we filter the electrical response of an induction
motor assumed to be operating under constant load conditions
and without the presence of a variable speed drive. The power
supply voltage applied to an induction motor is considered to
be a motor input, whereas the electric current drawn by the
motor is considered to be a motor output. In this application
of Wiener filters, the motor current is estimated (or filtered)
using voltage measurements, and the filter response is compared to the actual motor current measurements. If properly
designed, such a filter could be utilized in practice to detect
changes in the motor electrical response that might be due to
power supply variations, load variations, incipient motor
faults, or a combination of these conditions.

Jb0b1

iA

3 phase
power
supply

4
2

VAB iB
Auto
transformer VBC i
C

Induction
motor

dc
generator

VCA

0
2

VAB iA
1
0
b1

1
2

1
2

b0

Figure 6. Error performance surface for Wiener filter example.

VBC iB
VCA iC

To data
acquisition
system

Figure 8. Depiction of experimental set-up for induction motor filter application.

WIENER FILTERS

Induction
motor
3 phase
line
voltage
measurements
Wiener
filter

Electric
current
measurements

y(t)

Electric
current
estimates

^
y(t/t)

Figure 9. Inputoutput depiction of motor filter application.

In this example, several key assumptions are made regarding motor operation that simplify this application problem,
as follows:
1. The motor is assumed to be connected to a balanced
power supply.
2. The motor is assumed to consist of three balanced stator
windings.
3. The motor is assumed to be operating under constant
load conditions.
Under these simplifying assumptions, the three motor phases
can be decoupled, and filtering of a single motor current phase
can be pursued based on a single line voltage measurement.
In this example, voltage and current measurements were obtained from the experimental set-up depicted in Fig. 8.
The three key issues involved in Wiener filter design are
as follows:
1. What are the statistics of the desired response?
2. How is the filter input related to the desired response?

603

3. What is the best way to select the order of the Wiener

filter?
In this application, the desired filter response is the measured
motor current. This is a nonstationary signal with mean 60
Hz fundamental sinusoid. We could attempt to detrend the
fundamental signal and then proceed with the filtering process. In this application, however, detrending was not pursued. Furthermore, the filter input (i.e., the measured motor
line voltage) is related to the desired filter response via the
generally nonlinear induction motor dynamics. Therefore, in
this example two of the key assumptions of Wiener filters are
violated, and an optimal filter cannot be designed. The violated assumptions are the nonstationarity of the filter response and the nonlinear relation between the filter input
and the desired filter response. A block diagram depicting the
filter input and filter response is given in Fig. 9.
To design a suboptimal Wiener filter, we need to deal with
the issue of filter order. In this application, the exact filter
order is not easily determined and an iterative approach must
be followed. In order to determine a satisfactory filter order,
one must compare the performance of various filters against
a predetermined criterion. In this study, we have used two
error criteria for this comparisonthe normalized meansquared error (NMSE) and the relative error (RE), defined as
follows:

[ y(t/t)

y(t)]2
 2
(41)
NMSE
y (t)
RE

| y(t/t)

y(t)|
yrms

(42)

where yrms is the root-mean-square value of the measurements y(t) over a specific time interval and where all other

Measured current

1
0.5
0
0.5
1
0

200

400

600
Time (s)

800

1000

1200

200

400

600
Time (s)

800

1000

1200

Filtered current

1
0.5
0
0.5
1

Figure 10. Normalized desired filter response and filter output.

604

WINDOWS SYSTEMS

variables are as previously defined. The two sums in the

above error equations are carried over a sufficiently long interval to enable meaningful results. A first-order Wiener filter
results in 0.5% NMSE. As the order of the filter increases, the
NMSE decreases from approximately 0.1% (for a 5th order
filter) to 0.06% (for a 10th order filter), 0.05% (for a 20th order
filter), and 0.04% (for a 30th order filter). Further increase in
the filter order does not produce any significant decrease in
the NMSE.
A 10th order Wiener filter has been designed and the results are now presented. The normalized desired filter response and filter output are both shown in Fig. 10. The peak
RE for the steady-state filter response shown in Fig. 10 is
11.2%, and NMSE for the interval shown in Fig. 10 is 0.06%.
With the exception of the initial few cycles, during which the
peak RE reaches 46%, the accuracy of the filter is acceptable
considering that several of the key Wiener filter theory assumptions have been violated. Additionally, the good accuracy
of these results is the direct consequence of the simplifying
assumptions made in this application example. Relaxing some
of these key assumptions, such as allowing for nonconstant
motor load conditions, makes filter design a much more difficult task.

BIBLIOGRAPHY
1. F. C. Schweppe, Uncertain Dynamic Systems, Englewood Cliffs,
NJ: Prentice-Hall, 1973.
1a. G. C. Goodwing and K. S. Sin, Adaptive Filtering, Prediction and
Control, Englewood Cliffs, NJ: Prentice-Hall, 1984.
2. M. S. Grewal and A. P. Andrews, Kalman Filtering, Englewood
Cliffs, NJ: Prentice-Hall, 1993.
3. N. Wiener, Extrapolation, Interpolation, and Smoothing of Stationary Time Series, Cambridge, MA: MIT Press, 1949. (The original work was published in a classified National Defense Research
Report in February 1942.)
4. A. Gelb, Applied Optimal Estimation, Cambridge, MA: MIT
Press, 1974.
5. H. W. Sorenson, Least-squares estimation: from Gauss to Kalman, IEEE Spectrum, 7: 6368, 1970.
6. N. Levinson, The Wiener RMS (root mean square) error criterion
in filter design and prediction, J. Math. Phys., XXV (4): 261
278, 1947.
7. A. N. Kolmogorov, Interpolation and extrapolation of stationary
random sequences, translated by W. Doyle and J. Selin, Rept.
RM-3090-PR, RAND Corp., Santa Monica, Calif., 1962. (Originally published in Bulletin de lacademie des sciences USSR, pp.
314, 1941.)
8. S. Haykin, Adaptive Filter Theory, 3rd ed., Upper Saddle River,
NJ: Prentice-Hall, 1996.
9. T. Soderstrom and P. Stoica, System Identification, Englewood
Cliffs, NJ: Prentice-Hall, 1989.
10. L. Ljung, System Identification: Theory for the User, Englewood
Cliffs, NJ: Prentice-Hall, 1987.
11. A. Papoulis, Probability, Random Variables, and Stochastic Processes, New York: McGraw-Hill, 1991.
12. N. Wiener, Nonlinear Problems in Random Theory, Cambridge,
MA: MIT Press, 1958.
13. I. J. Leontaritis and S. A. Billings, Model selection and validation
methods for nonlinear systems, Int. J. Control, 45: 311341, 1987.

14. S. Haykin, Neural Networks: A Comprehensive Foundation, 2nd

ed., Upper Saddle River, NJ: Prentice-Hall, 1999.

ALEXANDER G. PARLOS
Texas A&M University

WIMP (WINDOWS, ICONS, MENUS, AND POINTING DEVICES) INTERFACES. See GRAPHICAL USER INTERFACES.

WINDOWS, FIR FILTERS. See FIR FILTERS, WINDOWS.

WINDOWS, SPECTRAL ANALYSIS. See SPECTRAL
ANALYSIS WINDOWING.

442

TRANSLINEAR CIRCUITS

TRANSLINEAR CIRCUITS
The concept of a translinear circuit, an approach to the realization of linear and nonlinear functions uniquely suited to
implementation in monolithic bipolar integrated circuit (IC)
form, was first realized by Gilbert in the mid-1960s. The principles were later articulated in two seminal papers, which described the application of translinear concepts to wideband
amplifiers (1) and analog multipliers (2). Their design was
based on the special properties of the bipolar junction transistor (BJT) and the use of a monolithic process was essential
for accurate implementation. This was one of several novel
ways in which translinear circuits differed radically from the
discrete-transistor circuit design principles in use at that
time. Another difference was the use of current-mode signalprocessing, thereby making better use of the inherently large
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

TRANSLINEAR CIRCUITS

dynamic range of the BJT, and achieving very high bandwidths; the dc to 500 MHz response of these circuits was remarkable at the time. Finally, unlike previous analog circuits,
they were transistor-intensive and used few standard components such as resistors and capacitors.
The term translinear was coined only later (3). It now has
a broader meaning and can be found in numerous articles and
textbooks (48). The original translinear circuits consist of
one or more closed loops of junctions operating with both fixed
(bias) currents and variable (signal) currents. These are now
called translinear-loop (TL) circuits. The translinear-loop
principle (TLP) is a powerful rule that permits rapid assessment and analysis of the function of any given TL cell, as well
as providing a route for synthesis.
The fundamental basis for translinear circuits is the accurate and dependable exponential relationship between the
collector current, IC, and the base-emitter voltage, VBE, in the
normal active region of operation, resulting in the well-known
linear dependence of transconductance on the collector current, which is the basis of the word translinear. A remarkable
aspect of the BJT is that this behavior is fundamentally independent of the device geometry (also referred to as device
scaling), the impurity doping levels and profiles, or even of
the technology; thus, a heterojunction transistor (using, for
example, SiGe, GaAs, or InP) exhibits the same translinear
qualities as a silicon homojunction BJT.
The broader contemporary meaning of the term embraces
any cell in which the characteristic exponential behavior of a
BJT is essential to the circuit function. Such circuits need not
employ closed loops of junctions. A simple example is the bipolar differential pair, the basis of numerous monolithic circuits, which may profitably be viewed in translinear terms.
This perspective is particularly valuable in developing complex nonlinear functions using very efficient cell structures.
These are called translinear network (TN) cells. Examples
of advanced TN design include circuits capable of exactly
generating all the trigonometric functions using fully analog means (9), ultralow distortion transconductance cells
(10), all bipolar non-TL analog multipliers, logarithmic and
variable-gain amplifiers (1115), log-domain filters (16,17)
and much else.
Metal-oxide-semiconductor (MOS) transistors, in both
their single-polarity and complementary (CMOS) form, using
devices having a relatively long channel and operating in the
weak inversion (also called subthreshold) region, are capable
of exhibiting approximately exponential behavior, and can be
used to realize the entire families of both TL and TN cells,
but at lower speeds and with lower accuracy than their BJT
counterparts. A considerable body of literature is devoted to
MOS design methods invoking exponential device behavior.
An even broader interpretation of the term has been proposed based on the quite different assumption that the transconductance of MOS transistors in strong inversion is a linear
function of (though not directly proportional to) the gatesource voltage. Several analogous loop topologies, named
MOS translinear (MTL), have been proposed by Seevinck (18)
and others (19,20). Unfortunately, the mathematical relationships and resulting equations are much less tractable, and
few compelling examples of cells based on this idea have been
offered to date. Furthermore, the underlying quadratic IDS assumption, the starting point for the analysis and synthesis of
MTL cells, is only approximate, departing significantly from

443

the ideal due to channel-length modulation and substrate effects, which are rarely addressed in the literature with the
necessary realism.
Accordingly, the word translinear will here be reserved exclusively for cells invoking high-accuracy exponential device
behavior, to avoid going beyond the spirit of the original proposal and risking uncertainty about the intended meaning of
the term. The strong-inversion idealization using MOS technologies should be called voltage-translinear, or VTL, since
the term MTL is ambiguous, and might imply either this
square-law VTL mode or classical translinear operation using
the devices in the subthreshold regime, where they are said
to exhibit exponential behavior.

TRANSLINEAR CELLS
By the time the word translinear was coined in 1975 nearly
10 years had elapsed since the possibility of translinear operation was first realized. The first practical applications, in
1966, were in the context of high-bandwidth (500 MHz) variable-gain cells developed for use in oscilloscope vertical amplifiers. One of many outgrowths of this idea was a linearized
wideband four-quadrant analog multiplier and the concurrent
invention of a monolithic doubly balanced modulator (or
mixer, a nonlinear multiplier), first reported in 1968 (21).
This structure is now widely known as the Gilbert Mixer
(sometimes, Gilbert Cell). However, during the patent search
phase, prior art of a similar kind by Jones, but using discrete
transistors and standard design techniques, was discovered
(22) in the form of a synchronous detector which used an identical core topology, although it did not anticipate the important method for linearizing the multiplier.
An early example of translinear design is illustrated in
Fig. 1; this is a wideband variable-gain amplifier (1), which
in a modern realization can provide a bandwidth of several
gigahertz. These unusual circuits shared certain common features:
1. They required the use of monolithically integrated bipolar junction transistors, because isothermal operation, tight matching of device geometry, and accurately
controlled doping levels are essential. Although their
possibility was conceivable from the invention of the
BJT in 1947, the full realization of their potential had
to await the availability of analog-quality process technologies, now refined to a high art.
2. The cells were simple and elegant, being largely comprised of dc-coupled bipolar transistors and current
sources, with practically no dependence on passive elements (such as resistors and capacitors). Their transistor-intensive schematics seemed more suggestive of
current-mode logic, compared with the familiar analog
circuits of the time, supported by their extensive retinue of passive components.
3. The transistors were arranged in closed loops, each
containing at least two base-emitter junctions (as in a
current mirror) but usually four; occasionally, six,
eight, or more junctions were used. Overlapping loops
were frequently employed.

444

TRANSLINEAR CIRCUITS
IBIAS

IOUT
(1 + X ) I0
(1 + X ) I
(1 X ) I0

Figure 1. An illustrative translinear amplifier.

(1 X ) I
IOUT

I1

4. The signal variablesthe cell inputs, outputs, and

control biaseswere all in current-mode form. Whatever voltages arose across the junctions were of only
incidental importance, and were not used in analysis.
5. The full-scale voltage swings were very small
typically only a few tens of millivolts. (A change in IC
by a factor of ten changes VBE by only 59.2 mV at 27C,
for an ideal BJT.)
6. The minimal branch impedances resulted in the highest bandwidth. The low impedances and low (incidental) voltage gains meant that collector-base and collector-substrate junction capacitances did not impact the
circuit speed as seriously as in extant analog signalprocessing circuits based on resistive loading and voltage-mode concepts.
7. Accurate operation of circuits of significant complexity
was possible at very low, single supply voltagesdown
to 1 V in some cases; this was unusual at a time when
standard supply voltages were 15 V.
8. Unlike prevalent high-frequency analog signal-processing cells, these circuits exhibited highly-predictable, fundamentally exact and temperature insensitive,
linear and nonlinear relationships between the signal
variablespossibly their most valuable property.
9. Functional accuracy persisted right up to the extreme
limits of the available operating range, not just a portion of this range.
10. Translinear-loop cells could implement a wide variety
of continuous-time algebraic functions, including squaring, square-rooting, multiplication and division, multidimensional vector addition and subtraction, the direct
computation of amplitude ratios in an array, polynomial, trigonometric, and implicit-form function generation, often within a few nanoseconds.
In a pre-microprocessor world, capabilities of this sort were
potent assets of outstanding practical value, but their utility
is undiminished today.

I2

I3

I = Io + I1 + I2 + I3

Current Mode Operation

During this period, the growing family of such cells were
called current-mode circuits, since everything of importance
about their behavior could be captured by a consideration of
the junction currents alone. However, all cells in this class
shared certain common topological features, for which a
unique identifier was needed. Referring to them as currentmode was imprecise and lacked rigor, even though at that
time there were few other circuits that operated in this mode.
In recent years, that term has been somewhat abused.
Close inspection of the numerous papers on the topic of current-mode circuits shows that both current and voltage play
an equal role in processing and transforming the signal. For
example, the class of logic cells known as current-mode logic
(CML) is not in any essential way current-mode. Currentmode logic gates merely make use of current-mode biasing,
and steer currents under the control of the resulting gate output voltages. Current-feedback operational amplifiers are erroneously called current-mode circuits. Research papers have
even reported on current-mode filters, which is clearly inappropriate, because an active filter fundamentally involves the
continual interplay of current and voltage in the capacitors
defining the frequency scaling. Thus, although one can
readily conceive of a circuit that performs the nonlinear algebraic operation
U=

(X 2 + Y 2 + Z2 )

(1)

using only currents to represent the inputs X, Y, and Z and

the output U, this is not possible in implementing the function Vout(s) Vin(s)/sT, because analog-signal integration (in
an inductorless embodiment) requires the accumulation of
charge (through current flow) in a capacitor, thereby generating a voltage, which is then converted back to another current
for subsequent integration. This inextricable codependence
between voltage and current is found in the inverse operation
of differentiation.
Translinear circuits are based on the remarkable fact that
the transconductance of a BJT is linearly proportional to its
collector current. Thus, the invented word translinear nicely

TRANSLINEAR CIRCUITS

captured their nature, as well as identifying a certain class

of topologies. The related exponential dependence of collector
current on the base-emitter voltage is extraordinarily exact
over six to eight decades for a modern bipolar transistor, and
of great practical and commercial value. It remains applicable
in the most aggressively scaled modern high-speed devices using fabrication methods radically different from those employed in the 1960s.
This key idea was envisaged as endowing the bipolar transistor with all the potential of a super-high-speed microelectronic slide-rule, the preeminent calculating aid of the time,
whose ability to instantly determine products, quotients, and
reciprocals was well-known to practicing engineers. A visual
icon (Fig. 2) showing a BJT having a slide-rule where the
emitter ought to be was used for many years in presentations
of translinear concepts, to dramatically focus attention on this
potential. Using two junctions in series was like adding
lengths on the slide-rule scales to effect multiplication
(Fig. 3).
Furthermore, the syllable trans- usefully conveyed the
notion of a bridge between the familiar territory of linear circuits and their well-developed mathematics, and the uncharted terrain of nonlinear circuits and their often-transcendental equations, at a time when few nonlinear analog
components were available in low-cost monolithic form. Nowadays, translinear principles are utilized in multipliers, mixers (23), modulators and demodulators, intermediate-frequency (IF) strips with automatic-gain-control (AGC) and
many other variable-gain amplifiers (24,25), programmable
filters (26,27), root-mean-square (RMS) circuits (28) for power
measurement from line frequencies to several GHz (29) and
other nonlinear circuits, such as those perfoming vector manipulation (30), and are hidden in numerous linear integrated

Figure 2. The microelectronic slide rule.

445

circuits. For example, the classical four-transistor class AB

output stage of many operational amplifiers (op-amps), the
current conveyor, and current mirrors can be understood, analyzed, and optimized in translinear terms.
These circuits, which often involve loops of junctions
within which the essential current relationships are generated, are called strictly translinear, or just TL. The cell function is essentially independent of the absolute magnitude of
the operating currents, that is, the bias level. Instead it is a
consequence of current ratios. Extensive use is made of the
idea of a modulation factor to describe signals: this is a dimensionless variable, say x, in the range 0 x 1, which
represents the actual current-mode signals, xIX, (1 x)IX, or
the alternative bipolar form, X, in the range 1 X 1, for
example (1 X)IX /2, and so on. These forms are used in the
simple four-quadrant multiplier cell shown in Fig. 4.
The cell function is invariant over bias levels IO ranging
from nanoamps (when operation is slow) up to milliamps
(where the circuit remains useful at frequencies close to f T,
because voltage swings and internal impedances are at an absolute minimum). All TL functions remain exact right up to
the limits of the available bias range and, most significantly,
they are fundamentally insensitive to variations in temperature over the full range of operation possible with silicon.
These were novel and still unique aspects of TL circuits not
shared by any other basic analog cells. Note that the direction
of current-flow in the transistors (CW or CCW) is an importance aspect of TL cells.
Modern Usage
Interest has recently focused on the possibility of exploiting
translinearity in MOS transistors operated in the subthreshold regime, implying a linear dependence of the transconductance IDS /VGS on the channel current. An early contributor
to this field was Carver Mead (31), who used MOS translinear
techniques to realize a wide variety of nonlinear functions in
the development of artificial cochleas and retinas. Recently,
higher-level learning and cognitive functions have been studied. Nanopower operation of CMOS translinear cells has
broad utility in analog neural networks (32), which is an important and promising next step in the realization of artificial
intelligence, leap-frogging an appeal to ever-faster Turing
machines by replacing serially executed algorithms with
highly interconnected parallel adaptive structures. It is of significance that such structures can benefit from all the nonlinear functions afforded by translinear techniques and implemented in an all-CMOS IC process to adequate accuracy by
operating devices in the subthreshhold region.
Formal algebraic decomposition techniques, as precursors
to cell synthesis, were developed by Seevinck (4), who later
with Wiegerink (18) stretched the notion of translinearity further, asserting that junction field-effect transistors (JFETs)
and MOS transistors in strong inversion exhibit transconductance, which is a linear function of the gate-source bias VGS,
starting with the popularly-assumed quadratic relationship
IGS (VGS VTH)2. Unfortunately, loops constructed of FETs
generate awkward equations involving the sums of squareroots, quite unlike the powerful product/quotient form of classical TL.
More importantly, the underlying assumption is far from
exact, even for long gate-lengths, and it becomes very unrelia-

446

TRANSLINEAR CIRCUITS

Ix

Iy

Vx log Ix

Vz log IxIy

Vy log Iy
Figure 3. Multiplication using the microelectronic slide rule.

ble in a submicron realization, where the gm more nearly approximates a linear function of IDS. In the interest of preserving the important distinctions that first led to proposing the
term translinear, and to minimize the confusion that results
from using it in connection with the style of nonlinear design
using closed loops involving the VGS of MOS transistors in
strong inversion, the latter are called VTL circuits. In this
taxonomy, the unqualified adjective translinear implies classical current-mode translinearity where exponential behavior
applies, which is accurate for all BJTs and other junction devices and approximately correct for MOS transistors in subthreshold operation.
Even beyond the domain of strictly translinear loops, the
uniquely accurate, multidecade translinearity of the BJT has
wide utility. Numerous circuits exist in which this valuable
property, identified either in terms of transconductance lin-

early proportional to collector current, or equivalently, as collector current exponentially proportional to base-emitter voltage, is invoked. Thus, a translinear circuit is one in which the
essential behavior arises directly from the exploitation of the
exponential equations of the BJT, and of functions based on
the intimately related hyperbolic trigonometric relationships.
Translinear Network Cells
A cell that invokes translinearity but does not utilize closed
loops of junctions is called a translinear network (TN). The
differential pair of Fig. 5 provides a simple example. It too
can be analyzed using basic principles that hold for bias
conditions from nanoamps to milliamps and are substantially independent of device scaling. This is a very different
situation from that which prevails for MOS in strong inver-

Difference =
2XYI0
(1 + X) (1 + Y)I0 (1 X) (1 + Y)I0
(1 X) I0

(1 + X) I0

CW

CCW

CCW

CW
2I0 (1 + Y)

(1 X) I0
Figure 4. A basic TL (current-mode)
multiplier.

(1 + X) I0

TRANSLINEAR CIRCUITS

IC1

IC2
Q1

Q2

VIN
IT

Figure 5. The BJT differential pair.

sion, where the choice of bias currents and W/L ratios for
the devices, and back-gate bias, strongly affect the overall
function.
The output current of a BJT differential-pair has precisely
the same reliable form for any IT, involving the hyperbolic
tangent function:
Iout = IC1 IC2 = IT tanh
The transconductance is
gm =

Iout
=
Vin

IT
2VT

V 
in

2VT


sech

VT =

V 
in

2VT

kT
q

(2)

(3)

A related class of TN cells provides the basis for low-noise,

wideband, ultralinear, current-programmable transductors,
useful in high-performance mixers and variable-gain cells.
They are also of value in continuous-time filters and in oscillators whose frequency can be rendered proportional to bias
current over a ratio of at least a million by the rigorous application of translinear principles.
An excellent example of a translinear network is the multitanh cell (10), the term referring to the use of a multiplicity
of basic cells similar to Fig. 5, each exhibiting a hyperbolic
tangent response between input voltage and output current.
By introducing a set of offset voltages between the pairs of
bases, and summing the pairs of collector currents (Fig. 6),
the overlapping tanh functions can generate a very linear gm
function which, unlike a resistive degenerated cell, remains
electronically controllable, being proportional to the currents
IT. A thorough treatment of these cells, including a variety of
practical means to generate the offset voltages, is provided in
Ref. 10. It is interesting to note that the same basic form as
in Fig. 6, but having the pairs of collector currents connected
in alternating antiphase, can provide a very exact synthesis
of the sine function over an angular range of 720 (9).
Other adaptations are characterized by having multiple
emitters tied to a common node and biased by one current
(33,34). Such cells can also provide precise synthesis of the
sine function; an example is shown in Fig. 7. When embedded
in a larger structure, all the trigonometric functions, includ-

447

ing the inverse functions (35), may be accurately generated at

high speeds.
The TN view even extends to such unlikely circuits as the
low-noise amplifiers (LNAs) used in modern communications
systems (whose impedance-matching and intermodulation
performance can be conveniently analyzed using a translinear
approach); to VBE cells, used to generate a voltage proportional to absolute temperature (PTAT), and an integral part
of band-gap voltage references; to CML logic gates; to special
types of current mirrors; and much else.
The essential idea in all these cases is the way in which a
device current IX is exponentially related to an applied voltage VX, thus: IX IOexp(x). In this equation IO is some normalizing current and x VX /VT, where VT kT/q evaluates
to 25.86 mV. (Unless stated, data are for T 27C). The inverse logarithmic relationship VX VTlog(y), where y IX /IO,
is equally valuable in TN cells. This is used in the logarithmic
amplifier shown in Fig. 8; here, the important scaling parameter IO is provided by the saturation current, IS, of the transistor. The TN approach to the design of such cells treats the
BJT as a voltage-controlled current source, rather than relying on the nonrigorous and obsolete beta-view of a currentcontrolled current source.

TRANSLINEAR AMPLIFIERS
Translinear design first arose in the field of monolithic wideband fixed- and variable-gain amplifiers for oscilloscopes.
Prevalent discrete-transistor amplifiers used balanced topologies. Methods were sought to implement fully integrated amplifiers also based on differential structures, but in a way better suited to a monolithic medium, such as a junction-isolated
process having a peak f T of 600 MHz. Using modern BJT processes having one hundred times higher peak f Ts (60 GHz),
translinear variable-gain amplifiers operating at 13 Gbits/s
in optical-fiber receivers (13) and operation at over 30 GHz
have been reported (14,15).
A cascade of cells of the sort shown in Fig. 5 can be continued indefinitely without the need for level shifting as shown
in Fig. 9. Operation at a collector-emitter bias VCE of 200
mV is usually satisfactory, permitting direct coupling of
stages. The incremental voltage gain of each stage is GV
IGRG /2VT and thus proportional to each tail current. Using
PTAT biasing, the voltage gain can be rendered stable with
temperature. More elaborate biasing techniques can also desensitize the gain to variations in, for example, junction resistances and finite current gain and achieve highly robust performance in large-scale production (36).
The input-referred voltage-noise spectral density for an
ideal BJT differential pair evaluates to 0.925 nV/Hz1/2 at a
tail bias IG of 1 mA. This noise is inversely proportional to the
square-root of IG, being for example 2.9 nV/Hz1/2 for IG 100
A. Ohmic resistances generate Johnson noise; a base resistance of 50 in each transistor adds a total of 1.29 nV/Hz1/2,
thus raising the input-referred noise at IG 1 mA to 1.59
nV/Hz1/2.
The high sensitivity and low noise make amplifiers of this
sort useful in many communications applications, in particular, in IF subsystems, where very high gain, and often a variable-gain capability, are required. However, the large-signal
transfer characteristic of this TN amplifier is nonlinear; con-

448

TRANSLINEAR CIRCUITS

IOUT
etc.
Stage 1

Stage 2

Stage 3

etc.

VIN

VOS1

version to TL form can render the amplifier linear while preserving the gain-control feature. Each stage generates a differential output voltage VCC that is related to its differential
input voltage VBB by
VCC
= IG RG tanh(VBB
/2VT )

VCC
= RG


= X IG RG

(5)

From Eqs. (4) and (5) it is apparent that the base-to-base voltage VBB required to result in a modulation factor of X must
have the form
VBB
= VT log

IT2

IT3

on the value of the bias current IG nor on the transistor geometry. Such a voltage can be generated by current-driving a
similar pair of junctions with inputs (which may be the outputs from the preceding amplifier stage) already in currentmode form, as shown in Fig. 10, to generate a voltage of

(4)

For the overall cell function to be linear, the collector currents

need to be a linear function of the input signal. These currents, which may be written as (1 X)IG /2 and (1 X)IG /2,
where X is called is a modulation factor 1 X 1, generate
a collector-to-collector voltage output of
(1 X )IG
(1 + X )IG

2
2

VOS3

IT1

Figure 6. The generalized multi-tanh concept: a translinear

network.

VOS2

1+X
1X

(6)

Thus, the input voltage required to generate a certain value

of X (typically having peak values of 0.75) depends neither

VBB
= VT log

1+Z
1Z

(7)

An input modulation factor of Z 0.5 would correspond to

signal components of 500 A for IZ 1 mA, but only 500
nA for IZ 1 A. Nevertheless, Eq. (7) states that the voltage
swing VBB will be 28.4 mV for all values of IZ. Thus, the
sensitivity of this cell to the magnitude of its input current
(that is, the transresistance 4VT /IZ for small signals) may be
raised through control of IZ.
When this fragment is combined with one of the differential amplifier stages of the sort shown in Fig. 9, we arrive at
the simple four-transistor cell (1) shown in Fig. 11, which is
noteworthy for several reasons:
1. The signal input, IBB, signal output, ICC, and gain-control means IG and IZ, are all in the form of currents, and
the signal-induced voltage variations that arise inside
the cell are purely incidental. The differential voltages

IOUT
IB

RB

Figure 7. A translinear network for

sine synthesis.

+VIN
2

IB

RB

IB

RB

RB
IT

IB

RB
VIN
2

TRANSLINEAR CIRCUITS

449

+
IX

VX = VT log IX/IS

VX

Figure 8. A translinear network for logarithmic conversion.

(VBB) associated with the signal path are small, typically only 50 mV for a full-scale modulation factor
X 0.75. Note that, although VBB is a nonlinear function of the signal, this is quite irrelevant to the accuracy
of current-mode circuit function.
2. The current-mode gain GI is proportional to the bias
current IG and inversely proportional to the bias current IZ, that is
GI =

ICC

I
= G
IBB

IZ

(8)

This ratio can, in principle, be very high, limited only

by the finite beta and device saturation at high currents
due to internal collector resistance. If IG and IZ have the
same shape over temperature, the gain is completely
unaffected by temperature, within the limitations of device imperfections.
3. This is a large-signal result, that is, the transfer function is now fundamentally linear:
ICC
=

IG
I

IZ BB

(9)

Stage 1

Stage 2

Stage 3

RG

RG

RG

Thus, through an appeal to a current-mode synthesis, the

strong nonlinearity of the exponential IC /VBE relationship
has been entirely side-stepped, and relegated to a position
of relevance only inside the cell. This large-signal linearity
extends from zero current right up to the full bias current
limit in each transistor, once again bearing in mind that
certain nonideal aspects of real transistors will somewhat
modify this result.
4. This cell introduces an important feature, namely, a
loop of emitter-base junctions traceable through the
four transistors, two of which have their current flow in
a clockwise direction, two of them counter-clockwise.
This is a necessity in all strictly translinear (TL) circuits, though loops may be of any size (usually between
four and ten junctions) and two or more loops may overlap to produce interesting and useful results.
This cell has a further hidden benefit, namely its substantial
insensitivity to the finite base currents of the output pair,
Q3 /Q4, with these two provisos: (a) the beta is essentially independent of the collector current; and (b) the base currents always remain less than the available input currents. The reason for this behavior, which is unique to this cell, is that the

VOUT

etc.

VIN

IG

IG

IG

Figure 9. A cascade of translinear network voltage-gain stages.

450

TRANSLINEAR CIRCUITS

(1 + Z) IZ

(1 + Z) IZ

B
IZ2

IZ1
VTlog

(1 + Z)
(1 Z)

Figure 10. A predistorting cell: stepping stone to a fully translinear amplifier.

base currents are in the same ratio as the drive currents, so

the all-important ratio of the currents in the input pair
Q1 /Q2, is unaffected (although of course, the actual currents
in these transistors is reduced). The differential cell of Fig. 11
was the first truly current-mode, inherently linear, variablegain amplifier. This cell could also be viewed as a two-quadrant analog multiplier, and by varying IZ it could be used as
a two-quadrant analog divider.
Once the principles and alluring potential of this elementary cell were grasped, the extension to four-quadrant multiplication followed quickly (2). This entailed simply attaching
the linearizing or predistorting cell to a doubly balanced active mixer, already being investigated at the time. (See Ref.
37 for some historical notes about an alternative synthesis
path, using current-mirrors as a starting point.)
This four-quadrant multiplier topology is shown in Fig. 12.
It retained the beta-immunity property mentioned above
and also allowed operation from low supply voltages (down
to 1 V), using appropriate biasing arrangements. In another
topologywhich later became very popularthe polarity of

the linearizing diodes was reversed: they were driven from

input currents flowing toward the negative supply, readily
provided by an npn cell. This alteration forfeited the beta immunity feature; however, because these are multiplier cells,
it is a straightforward matter to introduce beta-compensation
into the bias currents to achieve high accuracy of the complete monolithic function. Second-generation multipliers using such techniques were later presented in the literature
(38).
Since the publication of the first translinear multiplier design (notable for achieving a dc to 500 MHz bandwidth using
a 1960s monolithic technology) these basic cells have been
used innumerable times and have become familiar textbook
entities to analog IC designers.
We now return to the starting point for the early translinear work, namely, wideband linear current-mode amplifiers.
One cell does not provide sufficient gain for many practical
applications. The next step is therefore to cascade several
cells of the form shown in Fig. 11. The resulting topology is
indefinitely cascadable and can provide very high current
gain; it also provides a wide variable-gain range without using excessively large alterations in the bias currents, thus
achieving a more constant bandwidth.
Figure 13 shows a three-stage version of such an indefinitely-cascadable amplifier. The beta-immune form allowed a
high current-gain GI at each stage [in principle, right up to
() without significant gain error] with a bandwidth of approximately f T /GI at each stage. The odd-numbered dc bias
currents were provided by low-beta lateral pnp transistors
the only type available at the time. A minor inconvenience
was that the gain law was nonlinear, not only because of the
multiplication of linear gain factors, but also because as the
tail bias to each cell is raised, the bias to the input diodes
of the subsequent cell is lowered. Thus, for the three-stage
amplifier, the current gain is
GI

TOTAL

I2
I4
I6
I1 (I3 I2 ) (I5 I4 )

(10)

(1 X) IZ

(1 + X) IZ
(1 + X) IG

(1 X) IG

IC2

IC3

IC1

IC4
CW

CCW
3
2

4
CCW

2IG
1
IBB = IC1 IC4 = 2XIZ

Figure 11. A current-mode amplifier/multiplier/divider.

ICC = IC2 IC3 = 2XIG

CW

TRANSLINEAR CIRCUITS

(1 + X)IX

451

IOUT

(1 X)IX

(1 + Y)IY

(1 Y)IY
Figure 12. Current-mode (TL) four quadrant multiplier/divider.

The first such multistage TL amplifier built on a 1.2 GHz process (1) exhibited a clean large-signal pulse response and a 20
GHz gain-bandwidth (GBW) product. Recent implementations have achieved GBW values of over 300 GHz.
Another basic TL topology that became quite popular during the early 1970s is shown in Fig. 14. In this so-called gain
cell, also described in Ref. 1, the differential signal currents
(1 X)IX and (1 X)IX are reused at the collectors of Q1 /Q2
(which now act rather like cascodes) and the additional signal
currents IC3 (1 X)IY and IC4 (1 X)IY were added inphase to IC1 and IC2. The current gain of this cell is
GI =

I
1+ Y
IX

(11)

This was again a true current-mode amplifier and exhibited

somewhat higher bandwidth, partly because of the reuse of
the input currents. It was easy to cascade several such cells
across a supply voltage, without the need for the additional
bias currents used in the circuit of Fig. 13, although the number of cells was limited by the available voltage. That structureshown in the first example of a translinear circuit in
Figure 1accumulates both current gain and peak output

current capacity at each stage. In an early monolithic amplifier, the 50 mA output currents were applied directly to a
final cascode using a pair of discrete high-breakdown transistors, with the collectors driving the CRT vertical plates in an
advanced oscilloscope.
During this period, numerous examples of such true current-mode circuits were developedhaving all inputs, outputs, internal signals and control functions fully in current
form. Mixed-mode signal-processing TN circuits using a combination of currents and voltages followed in the mid-1970s.
In various low-cost rms-dc converters, exemplified by the Analog Devices AD536, the squarer-divider function was implemented in current-mode form, whereas the absolute-value
function (which preceded the translinear core) and the lowpass filter (used to extract the mean value of the squared input) were performed in voltage mode (28). Recent translinear
developments have led to rms-dc converters capable of accurate operation up to 10 GHz, providing true-power (waveform
independent) measurement in such applications as radio frequency power amplifier control.
Translinear network techniques are also exploited in the
design of low phase-noise quadrature voltage-controlled oscillators (VCOs) having a wide-range, current-controlled fre-

V+
BIAS

I1

I5

I3

+ IOUT

IIN
2I2

2I4

2I6
IOUT

I1

I3

I5

BIAS
V+

Current gain = I2/I1

Gain = I4/(I3 I2)

Gain = I6/(I5 I4)

Figure 13. Indefinitely-cascadable current-code amplifier.

452

TRANSLINEAR CIRCUITS

(1 X)(IX + IY)

(1 + X)(IX + IY)

tween IC and VBE, which is the heart of the BJT. Figure 15

shows that this relationship can be viewed in reciprocal ways.
In Fig. 15 the base-emitter junction of the transistor is driven
by an applied voltage, VBE, resulting in a collector current,
IC:
IC = AE JS (T ) exp(VBE /nVT )

VBIAS
Q2

Q1

Q3

Q4

(1 X)IX

(1 + X)IX
2IY
Figure 14. Current-mode gain-cell.

quency. In one useful implementation of a dual-integrator

loop, multi-tanh doublets are used to provide linear, programmable transconductance elements for frequency control. The
differential currents charge capacitors to generate the differential voltages that drive the opposite gm cell in the loop.
Clearly, such circuits cannot be called current mode, because
of the equal importance of both currents and voltages. Yet the
strict proportionality of the gm to the control current is precisely translinear. A further departure from the purity of the
original strictly TL loop concepts was the idea of introducing
fixed PTAT voltages within the loop to modify its behavior in
deliberate and useful ways. A simple example of this would
be the use of a sub-millivolt laser-trimmed voltage to null the
distortion caused by emitter-area mismatches in high-performance analog multipliers, such as the AD734 produced by
Analog Devices Inc.
The practical necessity of interfacing with voltage-mode
signals at the perimeters of translinear signal-processing
cores, such as the four-quadrant multiplier cell of Fig. 12, has
been vigorously addressed, with special emphasis on preserving the excellent linearity and bandwidth inherent in the current-mode core. In low-frequency instrumentation applications, translinear cells can be augmented by op-amps to force
collector currents; but to realize the intrinsic speed of TL circuits, other types of interfaces are needed. The translinear
cross-quad, described later, is useful in this regard.
Reports of poor accuracy were sometimes noted by early
experimenters with translinear current-mode circuits. These
were invariably due to a failure to appreciate the critical importance of using well-matched, isothermal transistors, for
which a monolithic technology was essential, implemented using careful layout techniques. Even among contemporary designers of monolithic ICs, the importance of avoiding spurious
sub-millivolt errors in metalization paths is still not fully appreciated.
TRANSLINEAR DESIGN PRINCIPLES
We next review the foundations of translinear design from a
fundamental starting point, namely, the relationship be-

(12)

where AE is the emitter area and JS(T) is the saturation current density. The factor n is the emission coefficient, generally
close to unity (typically 1.001 to 1.01) for an analog-quality
bipolar transistor operated in its normal forward active mode
at moderate currents (over the range of, say, IC 1 nA to
1 mA, a ratio of one million). We are generally safe in assuming that n is constant over the working current range; its exact value is usually unimportant in TL synthesis.
The saturation current IS(T) AEJS(T) is a scaling parameter arising from a multiplicity of process-related quantities,
including doping levels and profiles, and base thickness, as
well as several fundamental constants, most notably, EGO, the
band-gap energy. The quantity IS cannot be easily measured
directly, except at high temperatures; in practice, it is deduced through measurement of the VBE of a transistor operating at some collector current IC IR and temperature
T TR. It exhibits notorious temperature sensitivity, varying
by a factor of roughly 1013 from 55C to 125C (for a typical
small transistor, from approximately 1024 A to 1011 A).
The collector current, IC, being proportional to IS(T) and
exp(TR /T), would also vary enormously if VBE were held at a
fixed value. For example, applying a fixed VBE of 650 mV to a
BJT having IS 5 1017 A at 27C would result in an IC of
roughly 1 nA to 1 mA over this temperature range. It is therefore hardly surprising that the early applications of discrete
transistors strenuously avoided hard voltage biasing of the
E-B junction, because it seemed dangerously inappropriate.
Design at that time emphasized instead the safer notion of a
current-controlled current sourcethe beta viewbecause
beta varies only mildly over temperature. As we shall see, TL
circuits are dramatically immune to this immense variation
in IS, which has little direct importance.
A plot of log(IC) versus VBE for a modern monolithic npn
transistor shows extraordinary linearity over eight or more
decades (Fig. 16). Differentiating Eq. (12) we find
I
IC
= gm = C
VBE
VT

(13)

that is, the transconductance of an ideal BJT is a linear function of its collector current. Although this property of the BJT
is widely known to be useful in general circuit design, it is
absolutely pivotal to the translinear view.
The literature on BJT circuit design makes generous reference to gm; however, it is not uncommon to find the emphasis
still placed on the current gain, , recalling the pre-monolithic period in which discrete transistors could not be trusted
to have accurate and matching VBEs, or operate under isothermal conditions. Even today, translinearity is rarely presented
as the key to comprehending the behavior of the majority of
BJT circuits, in which the base-emitter voltage and collector
current are the dominant parameters.
In Fig. 15 the transistor is operated in a reciprocal fashion
by forcing IC and observing the resulting VBE. (The amplifier

TRANSLINEAR CIRCUITS

453

IC = AE JS exp (VBE/nVT)
IC
Cause

Effect

VBE

AE

AE

VBE

Cause

(a)

Effect
IC
= nVT log
AE JS

(b)

Figure 15. Reciprocal views of the BJTs VBE-IC relationship.

represented by the triangle, usually realized by a simple emitter-follower or NMOS source-follower, ensures that IC is independent of the base current). In this case, the circuit output
(VBE) is now a mild, almost-linear, function of temperature:
VBE = nVT log

IC
AE JS (T )

(14)

directly from fundamental considerations and is the basis of

the band-gap reference cell. Figure 17 shows the simulated
VBE(T) for a library transistor, over the extreme temperature
range from 250C to 400C; the slight curvature in
VBE(T), an artifact not included in Eq. (15), is quite apparent
in the simulated result. It is typically 0/2 mV over the
range 55C to 125C.

Using an alternative formulation (39):

VBE EGE

Translinear Loops

I
T
(E VBER ) + nVT log C
TR GE
IR

(15)

where EGE is typically 1.15 V, slightly less than the intrinsic

band-gap voltage EGO, and VBER is the VBE at a reference temperature TR and current IR. This important relationship comes

The interplay of current, voltage, and temperature is fundamental to transistor operation. Nevertheless, there exists an
extensive class of circuits whose function depends on the use
of currents as signals or functional variables. These can be
designed using methods in which voltages need not be considered at all and in which temperature effects are completely

10m
1m
100u
10u
1u
100n
10n
1n
100p
10p
1p
0.0

0.1

0.2

0.3

0.4

0.5
VBE

0.6

0.7

0.8

0.9

1.0

Figure 16. log(IC) vs. VBE at 55C, 35C and 125C for an NPN
Transistor (AE 45 2).

454

TRANSLINEAR CIRCUITS

1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Figure 17. VBE(T) for an NPN Transistor
(AE 45 2) at IC 10 A, 100 A and
1 mA.

0.0
250 200 150 100

50

100

150

200

250

300

350

400

TDEGC in degrees C

canceled and are comprised exclusively of BJTs arranged in

one or more closed loops of junctions, augmented by various
biasing means. Cells of this type are called strictly TL, or
just TL.
The simplest TL circuit is the current mirror (Fig. 18). It
can be viewed as a combination of the current-in/voltage-out
subcircuit of Fig. 16 driving the voltage-in/current-out subcircuit of Fig. 15. However, one does not generally think of the
current mirror in this fragmented way; rather, it is immediately recognizable as a current-mode configuration. The baseemitter voltage is of merely incidental interest and one intuitively understands that the output current will be scaled by
the ratio of the emitter areas.
Numerous elaborations of BJT current mirrors can be
found in the literature (40). Note that it is not essential that
the transistors exhibit an exponential IC /VBE relationship.
Thus, the current mirror was one of the few bipolar cell concepts that could be immediately converted to MOS form,
where its current-mode nature was equally apparent, although the incidental voltage swings were now much larger
and could not be overlooked so easily.

IIN

50

IOUT

In more sophisticated TL circuits, involving overlapping

loops of four, six, or more transistors, the cell function may be
less readily apparent. Traditional analyses using full circuit
equations, relating voltages and currents, become needlessly
burdened with factors that do not appear in the final result.
Such factors include the temperature-dependent VT (increasing by 0.33%/C at 27C) and the saturation current IS. On
the other hand, they can be quickly understood when the
translinear principle is applied, making analysis simple and
direct.
The Translinear Principle
Although subject to numerous detailed caveats when the crucial but somewhat ambiguous qualification of ideal is violated
to varying degrees, the following statement is true in broad
terms and has proven to be a reliable design rule in hundreds
of case histories. The wording here is not quite all-embracing
in that it does not yet allow for the use of MOS devices operating in weak inversion; such might be anticipated by substituting the term exponential element for junction, although
this tends to detract from the basic simplicity of the idea.
In a closed loop containing an even number of ideal junctions, arranged so that there are an equal number of clockwise-facing and counterclockwise-facing polarities, with no
further voltage generations inside this loop, the product of
the current densities in the clockwise direction is equal to the
product of the current densities in the counterclockwise direction.
We will now provide a brief proof, based on the analysis of
a general closed loop containing N junction devices. Figure 19
shows an example in which N 8; the junctions are biased
into forward conduction by some means.
The junction voltages, VFk, must algebraically sum to zero:
k=N

(1)kVFk = 0

(16)

k=1

Figure 18. A Current Mirror: The Simplest Translinear-Loop (TL)

Cell.

The pn junctions here will usually represent the base-emitter

terminals of the BJTs in the loop, so that each VFk is actually
the VBE of a transistor and the currents shown in each junc-

TRANSLINEAR CIRCUITS

455

currents of differing device types may have significantly disparate temperature behavior. Given this need for symmetry,
Eq. (18) can be stated as

Ck

J1

J8

J2

J7

CW

I
Ck
I
CCW Sk

J4
J5

I
Ck
Ck
=
A
A
CW Sk
CCW Sk

J=

CW

tion represent the collector currents, ICk (sometimes IEk). Accordingly, we can replace VFk by the value given for VBE in Eq.
(14):

(1)k nVT log

k=1

ICk
=0
ISk

(17)

The use of a separate IS for each junction recognizes the possibility that the junctions may have different areas or even be
made as different device types (for example, a mixture of
npn and pnp transistors). The quantity nVT appears in all
terms; we can generally assume that it is equal for isothermal
junctions of the same polarity.
With this assumption and noting that the summation of a
series of logarithmic terms can be written as a product and
that zero may be written as log(1), we can rewrite Eq. (17) as
k=N

k=1

I (1)k
Ck

ISk

=1

(20)

The ratios ICk /Ak are simply the current densities in each device. Thus, we can write the Translinear Principle in its most
compact form:

Figure 19. An Illustrative Translinear Loop.

k=N

(19)

The saturation currents ISk are proportional to the effective

emitter areas. We can replace ISk in Eq. (19) by factors of the
form AkJSk. Since the saturation current density JSk equally
weights both sides of the equation, we are left with

J3
J6

ISk

(18)

Now, every practical circuit will operate with IC /IS 1. For

example, even at a collector current as low as 1 nA, this ratio
will typically be 106 at 27C. Thus, for the product to remain
unity while maintaining sensible operating currents, there
must be
1. An even number of junctions in the loop.
2. An equal number forward-biased in the clockwise (CW)
and counterclockwise (CCW) directions.
Any mix of junction devices of different polarities, such as
npn and pnp transistors, including SiGe heterojunction bipolar transistors (HBTs), or even Schottky diodes may be used,
provided they appear in opposing pairs, since the saturation

(21)

CCW

which reads as in the verbal definition above. It is the elegance and simplicity of this principle, and the reliability with
which it can be implemented in a modern analog IC process,
that renders it so powerful. It is also a rather wonderful manifestation of the underlying semiconductor physics and the
carrier statistics that determine junction currents: the elimination of not only all the thermal sensitivities, the dependence on doping levels and absolute device size, but also the
exponential function that so strongly characterizes junction
behavior in the usual modes of operation suggest that Eq. (21)
is perhaps the most fundamental relationship of all in BJT
circuits.
Effect of Emitter-Junction Area
Although absolute size is not very important in translinear
circuits, the ratio of emitter areas between pairs of devices in
a TL circuit is crucial, and may be exploited to realize a variety of useful effects. For example, in a current mirror, the
emitter-area ratio directly scales the current gain. Deliberate
use of emitter area ratios is often helpful in reducing, or even
eliminating, errors (most often, distortion) due to finite junction resistance; for example, carefully chosen nonunity ratios
can improve the accuracy of an rms-dc converter for signals
of high crest factor, while leaving the scale-factor unchanged
(28). On the other hand, unwanted random deviations from a
nominal emitter-area ratio can represent a significant practical limit to the accuracy of TL cells.
In a small-geometry transistor, there will be a significant
component of IS due to carrier injection from the emitter sidewall; also, other effects mitigate against a simple proportionality of IS to the drawn emitter area in an IC layout. Therefore, it is generally essential in TL practice to realize area
ratios by repeating a fixed, unit geometry an integral number
of times, rather than by altering either the length or width of
the emitter. In TL schematics, the small letter e beside an
emitter is sometimes used to show the use of a unit emitter,
whereas multiple repetitions of this unit emitter are shown
as 2e, 4e, and so on. Consolidating the emitter areas into a

456

TRANSLINEAR CIRCUITS

composite term, we find

(+)

ICk =
ICk
A
A
CW k CW
CCW k CCW

I1

(22)

I4
Q2

Q3
A2

A3

Q1

hence

J=

CW

Q4
A1

I2

I3

A4

(23)

CCW

where , the area-ratio factor, has the value

Figure 20. A Simple TL Multiplier/Divider.

Ak

CW

Ak

(24)
when

CCW

A1 A2 = A3 A4
Unintentional errors in the effective emitter area ratios are
caused by random variations in junction doping (affecting JS)
and in the delineation of the emitter (affecting Ak). Mismatches can also be caused by thermal gradients on the chip.
VBE varies by about 2 mV/C, and 2 mV is equivalent to an
emitter-area ratio mismatch of 8% [that is, exp(2 mV/26
mV) 1.08], so small variations in temperature can cause
significant errors in TL circuits. For example, the heat from
a power output stage in a mixed-function chip will generate
both fixed and signal-dependent thermal gradients, which
may affect operation of a TL core function.
High-accuracy monolithic circuits invariably use a symmetrical layout in which critical pairs of transistors are crossconnected in quads. This practice is even more important in
TL circuits. In the well-known six-transistor multiplier, a residual VBE mismatch of only 20 Vequivalent to roughly
one-hundredth of a degree Celsiuswill result in parabolic
nonlinearity of approximately 0.04%. Mechanical stresses in
the silicon die, arising from poor layout and assembly techniques, can also cause the VBE of adjacent transistors to differ
in various anomalous ways.
It is for these reasons that one occasionally still meets with
some skepticism about the accuracy potential of TL circuits.
Nevertheless, the practical problems can be surmounted, as
evidenced by the many high-precision circuits that are now
commercially available. For example, the Analog Devices
AD734 Multiplier can exhibit a nonlinearity of 0.01%, equivalent to a 5 V VBE offset around each of the two overlapping
loops in the four-quadrant cell.
The deliberate use of emitter-area ratios is readily illustrated by one of the earliest TL circuits, the one-quadrant
multiplier/divider cell shown in Fig. 20. If we neglect base
currents, it is apparent from Eq. (21) that
J1 J2 = J3 J4
CCW

CW

thus
I4 =

I1 I2
I3

(25)

that is, = 1

It is not necessary for all the emitters to be fabricated with

identical areas for the overall scaling to be unity. For example, one could choose A1 1, A2 6, A3 2, A4 3, which
still yields 1. A common use of unequal areas is in minimizing errors caused by the junction resistance using devices
having sizes in close approximation to the nominal currents.
Often, the overall scaling factor needs to be something other
than unity. A significant limitation to the use of large values
of in this particular cell is the effect of base currents due to
finite beta; this can be addressed by various topological enhancements.
Multiple TL Loops
The above theory involved just one translinear loop, but there
is no limit to how many loops may overlap in a cell. The
Translinear Principle (TLP) stated in Eq. (21) will apply to
each of them independently. Because signal currents are now
shared between these loops, interesting and often valuable
effects can be achieved. The TLP does not require any modification to address this possibility. It is only necessary to use
the appropriate value of currents for the devices contained in
more than one loop. Thus, the four-quadrant multiplier, already shown in Figure 11, contains two overlapping loops:
Q1-Q2-Q3-Q4 and Q1-Q2-Q5-Q6. In this case, however, the loops
are essentially noninteractive (completely so if base currents
are ignored).
The cell shown in Fig. 21 also contains two overlapping
loops, but the function is now less apparent, because the current in Q7 is shared by the two loops. Devised in the early
1970s, this was one of several cells often used as an excellent
didactic example of the remarkable functional sophistication
that could be elicited from just a few transistors; these examples also amply demonstrated the power of TLP to rapidly
reveal the behavior of TL cells.
We might try to determine the function of this cell by noting that when IY is zero, Q3, Q4, and Q6 are nonconducting,
whereas Q1, Q2 and Q5, Q7 form an extended current mirror;
thus IW will just be a linear replication of IX. Likewise, when
IX is zero, Q1, Q2, and Q5 are nonconducting, whereas Q3, Q4
and Q6, Q7 act as a current mirror and simply replicates IY. It
is not immediately obvious, however, what happens when

TRANSLINEAR CIRCUITS

both IX and IY are applied. Using TLP the full analysis is so

easy that such beating-around-the-bush is quite unnecessary.
Applying TLP to Loop A:
IX IX = wIW IW
CCW

(26)

CW

where w is a temporary variable (see figure). For Loop B

IY IY = (1 w)IW IW
CW

(27)

CCW

Adding these two equations and solving, we immediately find

IW =

(IX2 + IY2 )

(28)

that is, the circuit performs the vector-summation function.

This simple two-dimensional processor can be readily extended to generate the three-dimensional vector sum (the cubic diagonal) with the addition of just three more transistors
driven by a third current IZ. It is equally apparent that any
number of input cells can be added in the horizontal direction
to provide n-dimensional operation, and that the function
m

ImK, for m 2, can be realized by adding further diodeconnected transistors in the vertical branches.
In a modern BJT technology an accurate solution can be
available within less than a nanosecond, and even in a microprocessor-rich culture this simple cell deserves consideration
where real-time processing is required. A solution based on
digital-signal-processing (DSP) could perhaps be more accurate, if the basic signal sources and the associated A/D and
D/A operations were impeccable, but it could not be as fast.
There are applications for vector summation in modern communications systems where this rapid response is valuable.
This is a one-quadrant vector summing circuit, that is, IX,
IY 0. Frequently, this function is required to operate in all
four quadrants, for example, in finding the radius amplitude
of a pair of bipolarity in-phase and quadrature (I and Q) signals. This can be achieved using a different, but equally ele-

IX2 + IX2
IX

IY
Q5

Q6

Q1

Q3
wIw

gant, translinear approach. The inputs to this cell must be

currents. Since to this day most signals outside of an IC remain in the voltage domain, conversion of the inputs current
form is needed. Furthermore, these currents flow from the
supply, which implies the use of p-type (pnp or PMOS) transistors in a single-supply context. Finally, IW will usually be
converted back to a voltage, which may require the use of a
p-type mirror. The potential accuracy and speed of the basic
translinear core may thus quickly become compromised by
the auxiliary circuitry. This cell can be embedded into a extended framework, using feedback amplifiers to preserve accuracy. A translinear cross-quad can be very effective in
bridging the gap between voltage-mode and current-mode signals while maintaining high accuracy and bandwidth (41).
Figure 22 shows two more examples of dual-loop vectormanipulation cells; nonunity emitter-area ratios are invoked
to achieve the correct function. The analysis has been presented elsewhere (42) but proceeds along the same lines as
used for the previous circuit.
Figure 23 shows an interesting example of a multiple-loop
TL circuit, in which all loops overlap and two nodes are common to all loops. It is noteworthy that this cell was also included in the first published paper on translinear techniques
(21). Here again, the remarkable processing power that can
be accomplished within the confines of a very rudimentary
circuit, the hallmark of this design methodology, is demonstrated. Using M loops coupled in the tightest possible topology, it performs the M-dimensional array normalization:

Iout

= IE

Iin
j=M

Iin

(29)
j

j=1

that is, it continuously computes the ratio of each input in the

array to the sum of all the inputs and then multiplies the
result by the output scaling current IE. With attention to certain practical details (not included in Fig. 23) the inputs can
span a dynamic range of 80 dB and generate the solution
within nanoseconds.
This sophisticated analog computation proceeds in an extraordinarily compact fashion, being mediated through little
else than the wire connecting all the emitters together. An IC
embodiment of this cell (43) provided a 16-wide input, expandable without limit through three expansion pins. Using
a simple modification, the IC also provided the alternative
function
Iout

= IE

Iin

max(Iin j )

(30)

(1 + w)Iw

A
Q2

457

B
Q7

Q4
Iw

Figure 21. A TL Cell Containing Two Loops.

which results in one of the IOUT values always being at fullscale (IE), whereas the mode shown in Eq. (29) results in a
peak output dynamic range of M : 1. As might be expected,
multiple-loop TL cells have significant potential in executing
the near-instantaneous solution of simultaneous equations
having a large number of variables. Numerous examples of
such highly compact equation solvers have been envisaged
over the years and are routinely utilized in contemporary
commercial ICs.

458

TRANSLINEAR CIRCUITS
2
2
IX
+ IY

2
2
IX + IY

IX

IX
Q4

Q3

2e

Q1
+ / + IY

Q1
2e

+ / + IY

Q3
e

Q2

The Ratiometric Viewpoint

The concept of variables embedded in chained products of current having the dimension of (Amps)M, where M N/2 is the
number of junctions in each (CW and CCW) direction, is
somewhat counterintuitive. An alternative way of thinking
about TL loop behavior is in terms of the current ratios between junctions taken in opposing pairs. These are dimensionless and often within an order of magnitude of unity (0.1
to 10).
Indeed, the great practical value of TL circuits stems from
this ratiometric behavior, which is fundamentally independent of the general magnitude of the bias current or the process on which the devices are made (with appropriate reservations about matching device structures), or the operating
temperature, since the nVT factors canceled in Eq. (18) and
the basic IS factors in Eq. (20). These general expectations
about ratiometric behavior have been proven reliable over a
wide range of circumstances. Such a view is readily applied
to the array normalizer of Fig. 23, where
Iout
Iin

1
1

= ...

Iout
Iin

k
k

= ...

Iout

Iin

(31)

but it is equally applicable to the single loop cells shown in

Figs. 10, 11 and 13 by taking the junctions in opposing pairs,
with due regard for the junction area. In basic TL circuits,
this strict ratiometric behavior arises from setting the net
loop voltage to zero. However, it is certainly possible, and oc-

IIN_1

IIN_2
IOUT_1

IIN_3
IOUT_2

IIN_M
IOUT_M

IOUT_3

M stages
The solution node

Q5

Q2
2e

2e

Figure 22. TL Cells for Two-Quadrant

Vector-Difference (left) and Vector-Sum
(right).

Q5

IE

Figure 23. An Infinitely-Expandable Analog Array Normalizer.

e
Q4
e

casionally even useful, to include one or more voltage sources

in a loop, when the governing equation becomes
k=N

k=1

VT log

ICk
= VL
ISk

(32)

where VL is the net voltage inserted into the loop (using one
or more sources) and the n of nVT is assumed to be unity. This
voltage radically alters the behavior of the circuit, but can be
cast into a form that shows its potential utility. With simple
manipulation, it can be shown to be equivalent to the modification of the emitter-area scaling factor, , that is,

= exp

2VL
NVT

(33)

It follows that if a temperature-stable function is desired, VL

must be PTAT (proportional to absolute temperature). A practical use of such a voltage is to null out the VBE mismatch in
a TL loop where this would degrade accuracy. These mismatches amount to much less than 100 V in a modern BJT
process, using appropriate layout techniques, which is another way of saying that the emitter area ratio of critical pairs
can be held to within better than 0.4%. Nevertheless, this
is quite inadequate matching for a high-performance, low-distortion analog multiplier such as the AD734. This product
achieves very high scaling accuracy and low even-order distortion first by using careful cross-quadding of critical pairs
and second by laser-trimming the VBE mismatch, corresponding the factor , by introducing a VL of up to 200 V, using
synchronous demodulation techniques to measure minuscule
levels of distortion (120 dBc).
In an alternate design approach, one may rely solely on
correct-as-fabricated devices, using extensive interdigitation
of transistors to minimize statistical fluctuations in the effective value of . This has the advantage of requiring no trimming and further reduces the sensitivity to on-chip thermal
gradients and stress-induced errors (particularly those due to
post-packaging stress). On the other hand, this approach will
usually consume more chip area and may result in reduced
bandwidth from the much higher parasitic capacitances of the
large transistors and their lower current densities.
It is often possible to use a short length of the aluminum
interconnect as an approximately PTAT resistor of a few
ohms to generate the needed correction voltage when driven
by a temperature-stable current. This has a temperature coef-

TRANSLINEAR CIRCUITS

ficient of roughly 3900 ppm/C, which makes it almost right

for this purpose. Alternatively, it is a simple matter to generate a PTAT voltage using a VBE cell for this purpose, as is
utilized in the AD734. An example of the use of an inserted
voltage used to bring about a much larger change in circuit
function is shown in Figure 22. Here, the current-gain GI of a
somewhat-elaborated mirror, using complementary transistors, can be altered over a wide range by the voltage VG:
GI = A exp

459

V+
RC
VOUT
Q4
VIN
Q5
IG

VG
2VT

(34)
Q2

This complementary bipolar (CB) cell conveniently provides a

differential pair of nodes, of moderately high impedance, at
which to apply the control voltage, VG. Using CB cells of alternating polarity, a simple wideband current-mode variablegain amplifier can be built.
There has been considerable recent interest in so-called
log-domain filters (16), which seek to advantageously exploit
the bipolar transistors unique exponential properties. In the
work described by Perry and Roberts (17), the cell shown in
Fig. 24 is used as for the log and antilog operations. In another approach, Seevinck (44) adapts the basic multiplier/divider cell shown in Fig. 10. Log-domain filters are attractive
because they offer an alternative to the use of the linear
transductors needed in gm /C filters, which are complicated by
the additional requirement that the gm must invariably be
programmable to effect tuning (in a master/slave configuration). They also provide a wide tuning range.
Figure 25 shows a further example of a TL cell in which an
inserted voltage is used to strongly modify the cell function.
IC1 is forced to IO a primary bias current, which is PTATby
the emitter follower (or NMOS device) Q2. IG is a gain-control
current, which should also be PTAT for stable gain-scaling.
RB serves only to ensure that Q2 is always biased and absorbs
the nonconstant IG. The inserted voltage in this case is VG,
generated across the resistor RG, which lowers the collector
current of Q3:
IC3 = AI0 exp(VG /VT )

(35)

Q1

VG

Q3

RG

IG

Ae

RB

Figure 25. A Linear-in-dB Current-Programmable Gain-Cell.

Thus, IG controls the gain of the associated differential pair,

Q4 /Q5. The exponential relationship results in a linear-in-decibels gain function. The scaling is easily calculated: at T
27C, 1 mV of VG lowers IC3, and thus the gain, by the factor
exp(1 mV/25.86 mV) or 1.0394, which expressed in decibels is
0.336 dB. When RG 1 k, the scaling is approximately 3
A/dB. Several gain cells can be driven from the same basic
interface simply by adding current-source transistors like Q3;
the same linear-in-decibels gain form results.
Mixed TL and TN Cells
Strictly translinear (TL) subcells can be combined with
translinear network (TN) subcells in numerous ways. In the
variable-gain amplifier (VGA) shown in Figure 26, Q1 Q4
form a translinear cross-quad (41). Here, pnp devices are used
for Q1 /Q2 and npn devices for Q3 /Q4. The input current Iin
IO modulates the collector currents. Tracing the build-up of

IIN exp (VG/2VT)

IIN

I0

RX
VX
e

Q1

RG/2

Q2

VOUT

Q5

e
+
VG

Q6
Q3

Q4

2I0

IG

(VNEG or GND)

Figure 24. A Voltage-Programmable Current-Mirror.

Figure 26. A Mixed TN/TL Structure: A Voltage-Input/Output VGA.

460

TRANSLINEAR CIRCUITS

VBEs through these four transistors from the input node back
to the ground node, we find that they fully cancel. [This is not
exactly true when finite current gain () is taken into account, but it is a good approximation.] If we neglect the base
currents of Q5 /Q6 at low frequencies, we find that rin
4kT/qIO, or approximately 1 at IO 1 mA. Thus, the input
voltage VX is accurately converted to the current IX VX /RX
even for quite small values of RX (say, 50 ).
The currents in Q3 and Q4 have exactly the required form
to act as the input pair to a linear multiplier (compare this
with Fig. 10), completed by the addition of the transconductance pair Q5, Q6. Using simple current-to-voltage conversion,
the overall structure can be viewed as a linear VGA, whose
numerical gain is readily shown to be
G=

IG RG
I0 RX

(36)

This scheme integrates the required high-linearity, wideband

voltage-current conversion step with the predistorting devices (Q3, Q4), while the VBEs of Q1 /Q2 usefully provide levelshifting for the output pair. Note also that the cell Q3-Q4-Q5Q6 preserves the desirable beta-immune form. By adding a
second output pair and a suitable interface for the second input variable a four-quadrant multiplier can be realized.
Effect of Device Nonidealities
The reference value of VBE usually assumes a VBC of zero,
when IS is defined in accordance with generally agreed modeling practices. Base-width modulation increases IC by the factor (1 VBC /VAF), where VAF is the forward Early voltage.
Thus, the basic equations need to be amended, to read
IC =

1+

VBC
VAF

IS (T ) exp

VBE
nVT

(37)

or
VBE = nVT log

IC
IS (T )(1 + VBC /VAF )

(38)

For high-frequency transistors, VAF is generally quite low. To

minimize errors, devices should be biased in pairs, so that
the VCB effects cancel (recall that the operation of TL circuits
is invariably based on current ratios, not the absolute currents). It is often possible to use a cascode stage or a specially
provided bias line designed to keep VCB at or near zero. It is
unusual in strict-TL circuits to find the full supply voltage
across any device inside a TL loop.
The increase in VBE due to the junction resistances, most
notably, the base resistance, rBB and the emitter resistance
rEE (particularly in transistor processes using polysilicon
emitters) is often a major limitation to accuracy, since it does
not introduce simple factors into the equations, as for basewidth modulation. Rather, it results in a VBE which is now a
mixture of linear and logarithmic terms:
VBE

I
= VT log C + IC
IS (T )

r

BB

+ rEE


(39)

where is the appropriate value for the current gain, and is

a function of IC, VCB, frequency, temperature and production
tolerances. As evidence of the complications that rBB introduces into TL analysis, note that one can no longer write a
closed-form equation for IC as a function of VBE.
The effect of the junction resistances on cell behavior are
capricious. In four-transistor two-quadrant multipliers (variable-gain cells) they introduce odd-order distortion, which can
vary strongly with the gain. This distortion can be made to
vanish at one specific value of gain by the judicious use of
emitter area sizing (determining rBB), but cannot be eliminated completely. On the other hand, the six-transistor fourquadrant multiplier cell can be designed to exhibit essentially
zero odd-order distortion even in the presence of very large
ohmic errors (2).
Thus, ohmic errors are not readily quantified in general
terms. Analysis is complicated by the fact that rBB is current
and temperature dependent: the subemitter portion of rBB
typically increases by about 1%/C, whereas the extrinsic portion has a temperature coefficient of approximately 0.15 %/
C. Analysis is further complicated by the role of finite beta,
as well as its current and temperature dependence.
The value of bipolar translinear circuits is now well established. The voltage-controlled current-source view of the BJT,
which is captured in the notion of translinearity, is a more
useful one than the older idea of a current-controlled current
source (the beta view) in a modern monolithic context. Many
of the limitations and obstacles that once stood in the way of
actually realizing the full potential of these cells have long
since been removed.
The largest utilization of translinear concepts has been in
analog multiplication. Once a very important general challenge, this function is now more likely to be found in various
specialized forms. Multipliers are used in RF power management (29,45), modulationdemodulation, and gain-control applications at frequencies up to 30 GHz. There are few alternatives to translinear techniques where speed and high
accuracy are required. Heterojunction transistors, often used
in these high-speed applications, also conform to the translinear principle; thus, all of the cell concepts developed for homojunction transistors are fully realizable in HBT form.
Operating in subthreshold, MOS transistors are also
translinear, although the generally low currents in this domain limit the operating speed to much less than the full
capabilities of a given technology. This mode of operation may
become of importance in analog neural networks. In a simple
theory of field-effect devices, the transconductance of an MOS
transistor in strong inversion is a linear function of the gatesource bias. This has led to the adoption of the term translinear in this context, and various TL-like cells have been proposed. The term MOS-translinear (MTL) has been used for
such circuits. Since there is a growing number of ways in
which this word is now being applied, this particular class of
circuits, differing so markedly from bipolar TL and TN circuits, should be called voltage-translinear, or VTL.

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17. D. Perry and G. W. Roberts, Log-domain filters based on LC-ladder synthesis, Proc. IEEE Int. Sym. Circuits Syst., pp. 311314,
1995.
18. E. Seevinck and R. J. Wiegerink, Generalized translinear principle, IEEE J. Solid-State Circuits, 26 (8): 11981102, 1991.
19. R. J. Wiegerink, Computer aided analysis and design of MOS
translinear circuits, Analog Integr. Circuits Signal Process., 9 (2):
181187, 1996.
20. A. G. Andreou and K. A. Boahen, Translinear circuits in subthreshold MOS, Analog Integr. Circuits Signal Process., 9 (2):
141166, 1996.
21. B. Gilbert, A DC-500 MHz amplifier/multiplier principle, ISSCC
Dig. Tech. Pap., 1968, pp. 114115.
22. H. E. Jones, U.S. Patent No. 3,241,078, Dual Output Synchronous Detector Utilizing Transistorized Differential Amplifiers,
Issued Mar. 15, 1966.
23. B. Gilbert, Design considerations for active BJT mixers, in G.
Machado (ed.), Low-power HF Microelectronics; A Unified Approach, London: IEE Circuits and Systems, 1996, Ser. 8, Ch. 23,
pp. 837927.
24. B. Gilbert, IF amplifiers for monolithic bipolar communications
systems, EPFL Electron. Lab. Adv. Eng. Course RF Des. Wireless
Commun. Syst., Lausanne, 1996.
25. P. G. Van Lieshout and R. Van de Plassche, A monolithic wideband variable-gain amplifier with a high gain range and low distortion, ISSCC Tech. Dig., 1996, pp. 358359.

461

26. J. O. Voorman, Analog integrated filters, Eur. Solid-State Circuits

Conf. Rec., 1985, pp. 292292C.
27. H. Tanimoto et al., Realization of a 1-V active filter using a linearization technique employing plurality of emitter-coupled
pairs, IEEE J. Solid-State Circuits, 26: 937945, 1991.
28. B. Gilbert, A monolithic RMS-DC converter with crest-factor compensation, ISSCC Dig. Tech. Pap., 1976, pp. 110111.
29. B. Gilbert, Novel method for amplitude measurement of signals
up to microwave frequencies, Electron. Lett., 13 (4): 107108,
1977.
30. B. Gilbert, High-accuracy vector-difference and vector-sum circuits, Electron. Lett., 12 (11): 293294, 1976.
31. C. A. Mead, Analog VLSI and Neural Systems, Reading, MA: Addison-Wesley, 1989.
32. B. Gilbert, Nanopower nonlinear circuits based on the translinear
principle, Workshop on Hardware Implement. Neural Networks,
San Diego, CA, 1988.
33. B. Gilbert, Monolithic analog READ-ONLY memory for character
generation, IEEE J. Solid-State Circuits, SC-6 (1): 4555, 1971.
34. B. Gilbert, A monolithic 16-channel analog array processor, IEEE
J. Solid-State Circuits, SC-19 (6): 956963, 1984.
35. B. Gilbert, A monolithic microsystem for the analog synthesis of
trigonometric functions and their inverses, IEEE J. Solid-State
Circuits, SC-17 (6): 11791191, 1982.
36. B. Gilbert, Advances in BJT techniques for high-performance
transceiver, Eur. Solid-State Circuits Conf. Rec., 1997, pp. 3138.
37. B. Gilbert, Where do little circuits come from?, in J. Williams
(ed.), Analog Circuit Design: Art, Science and Personalities, EDN
Ser. Des. Eng., Stoneham, MA: Butterworth-Heinemann, 1991,
Ch. 19.
38. B. Gilbert, A high-performance monolithic multiplier using active
feedback, IEEE J. Solid-State Circuits, SC-9 (6): 364373, 1974.
39. R. J. Widlar, An exact expression for the thermal variation of the
emitter base voltage of bi-polar (sic) transistors, Proc. IEEE
(Lett.), 55: 9697, 1967.
40. B. Gilbert, Bipolar current mirrors, in C. Toumazou, F. J. Lidgey,
and D. G. Haigh (eds.), Analogue IC Design: The Current-Mode
Approach, IEE Circuits Syst. Ser., London: Peter Peregrinus,
1990, Vol. 2, pp. 239296.
41. B. Gilbert, Translinear circuits: An historical overview, Analog
Integr. Circuits Signal Process., 9: 95118, 1996.
42. B. Gilbert, Current-mode circuits from a translinear viewpoint: A
tutorial (Use of op-amps to augment TL cells), in C. Toumazou,
J. Lidgey, and D. G. Haigh (eds.), Analogue IC Design: The Current-Mode Approach, IEE Circuits Syst. Ser., London: Peter Peregrinus, 1990, Vol. 2, p. 51.
43. B. Gilbert, An analog array processor, ISSCC Dig. Tech. Pap.,
1984, pp. 286287.
44. E. Seevinck, Companding current-mode integrator: A new circuit
principle for continuous-time monolithic filters, Electron. Lett., 26
(24), 20462947, 1990.
45. B. Gilbert, Novel technique for RMS-DC conversion based on the
difference of squares, Electron. Lett., 11 (8).

BARRIE GILBERT
Analog Devices Inc.

TRANSLINEAR CIRCUITS. See ANALOG INTEGRATED CIRCUITS.

TRANSMISSION ELECTRON MICROSCOPES. See

ELECTRON MICROSCOPES.

462

TRANSMISSION USING CHAOTIC SYSTEMS

TRANSMISSION FORMULA, FREE-SPACE TRANSMISSION. See FRIIS FREE-SPACE TRANSMISSION FORMULA.

TRANSMISSION IMPAIRMENT MITIGATION. See
DIVERSITY RECEPTION.

TRANSMISSION LINE. See SLOT LINE COMPONENTS.

TRANSMISSION LINE FAULT LOCATION. See
FAULT LOCATION.

TRANSMISSION LINE RESONATORS. See CAVITY RESONATORS.

TRANSMISSION LINES. See FINLINES.

TRANSMISSION LINES, HIGH-FREQUENCY. See
HIGH-FREQUENCY TRANSMISSION LINES.

TRANSMISSION LINE SOLUTION METHODS. See

SMITH CHART.

TRANSMISSION LINES, POWER. See POWER TRANSMISSION LINES.

TRANSMISSION LINES, STRIPLINES. See STRIPLINES.

TRANSMISSION NETWORKS. See POWER TRANSMISSION NETWORKS.

TRANSMISSION NETWORKS, DC. See DC TRANSMISSION NETWORKS.

TRANSMISSION OF AC POWER. See AC POWER

TRANSMISSION.

TRANSMISSION, RADIOWAVE. See RADIOWAVE PROPAGATION GROUND EFFECTS.

LOGARITHMIC AMPLIFIERS

517

LOGARITHMIC AMPLIFIERS
Logarithmic amplifiers are specialized nonlinear signal-processing elements used wherever a signal of large dynamic
range must be represented by an output of substantially
smaller range, and where equal ratios in the input domain
are usefully transformed to equal increments in the output
domain. In communications and instrumentation applications, the logarithmic transformation has the additional value
of providing a measure of the input expressed in decibel form.
J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

518

LOGARITHMIC AMPLIFIERS

Nonlinear signal conversion invariably has consequences

that can be puzzling if the fundamental nature of the transformation is not kept clearly in mind. This is especially true of
logarithmic conversion. For example, an attenuator inserted
between the source VIN and a conventional linear amplifier
simply changes the slope VOUT /VIN at the output, which is
simply the gain. But this modification would have no effect
on the slope (defined in the same way) at the output of a logarithmic amplifier. Similarly, a dc offset voltage at the output
of a linear amplifier has no relevance to the processing of an
ac signal, whereas an offset introduced at the output of a demodulating logarithmic amplifier alters the apparent ac magnitude of its input.
These important distinctions might be clearer if a term
such as decibel-to-linear converter were used for such elements, but the description logarithmic amplifier or simply
logamp, the term used throughout this article, has become so
widespread that convention demands the continued use of
this somewhat misleading name. It should be noted, however,
that the logarithmic function can be realized without the use
of amplification in the ordinary sense, though that operation
is often involved.
There are several different types of logamps, having a similar transfer characteristic between their input signal and the
output. Figure 1 shows an idealized inputoutput response of
a generalized logamp, which will later be formalized mathematically. The input might be a signal burst in a cellular
phone; the instantaneous value of a unipolar baseband pulse
in an airborne, marine, or automotive radar system; the
slowly varying carrier envelope in a spectrum analyzer; the
current output of a photodiode, or some other measured variable in a high-dynamic-range analytical instrument; and so
on. The form of the input signal will be quite different in each
case, and the time domain over which events occur ranges
from a few nanoseconds in a high-resolution radar system to
many seconds in chemical analysis equipment.
For the moment we do not need to be concerned with these
distinctions, and it is convenient for now to suppose that the
input is a dc voltage, VX. (Boldface symbols indicate input and
output signals. Scaling parameters and other incidental variables will be in lightface). This simplification will be particu-

VW
5VY

4VY

3VY

2VY

VY
log VX
0
VX = 102Vz

VX = Vz

VX =

102V

VX =

104V

Figure 1. Response of an idealized logarithmic amplifier.

larly useful later, when we undertake a formal analysis of the

behavior of logamps based on piecewise linear techniques.
Over a range of several decades, each ratio (say, an octave
or decade) of change in VX causes a fixed unit of change in the
output VW. The parameter defining this scaling attribute, VY,
will here be called the logarithmic slope, usually expressed in
millivolts per decibel. However, dimensional consistency in
equations requires that formally VY be identified as the slope
voltage.
At a certain value of input signal, the output or, more commonly, the extrapolated output, will pass through zero, which
is here called the intercept voltage, and assigned the variable
VZ. If the logamp were perfect, this intercept would actually
occur at the unique input VX VZ. The need to use an extrapolated value arises because at low input levels, internal amplifier noise or residual offset voltages at the input of a practical circuit will cause significant errors in VW, which will read
higher than the correct value, and the output may never actually pass through zero, as depicted in the figure. The intercept
is an important scaling parameter, since only through knowing both the slope VY and the intercept VZ can the input level
be accurately determined. At high input levels the limited signal-handling capability of the circuit cells, either at the input
or at the output, will eventually impose some limit on the
upper extent of the dynamic range.
Note that the conversion characteristic does not need to be
logarithmic to achieve useful compression. An amplifier having a square-root transfer characteristic would halve the decibel-specified dynamic range; a cube-root response would
reduce it by a factor of three. Compandors performs such
power-law operations on the envelope amplitude of an ac signal. The logarithmic function is especially valuable because it
uniquely provides an output that changes by the same
amount over any given ratio of input amplitudes, rendering
the output particularly easy to interpret. For example, the
output of a logamp with a slope of 1 V/decade changes by 1 V
for any tenfold change in the magnitude of the input within
its dynamic range. Since a factor-of-ten change in input level
corresponds to 20 dB, a logarithmic response is also useful in
representing decibel levels; a slope of 1 V/decade corresponds
to 50 mV/dB.
Specifying logarithmic circuit performance requires care in
defining terms. The literature abounds with incomplete explanations of critical fundamental issues. In calling them amplifiers, their strongly nonlinear nature is in danger of being obscured. In some cases (for example, progressive compression
logamps) they actually do provide the needed amplification,
and in these cases, the logarithmic output, invariably called
the received signal strength indication (RSSI) may be only an
incidental function of the part.
The focus of this article will be on practical circuits that
closely approximate the logarithmic function for a wide variety of signal types. We will exercise constant vigilance in matters of scaling, that is, in ensuring formal traceability of the
constants VY and VZ back to one or more reference voltages, to
ensure the highest possible accuracy in the transformation in
an actual implementation. This challenge in precision nonlinear design has received inadequate attention in the literature.
CLASSIFICATION
Logamps may be placed in three broad groups, according to
the technique used, with one subclassification:

LOGARITHMIC AMPLIFIERS

Direct translinear
Exponential loop
Progressive compression:
Baseband
Demodulating

A = A0 exp(VW /Vs)
VX

x2

VDC

VR

1
sT

Direct translinear logamps invoke the highly predictable

log-exponential properties of the bipolar transistor. (See
TRANSLINEAR CIRCUITS.) Practical translinear logamps can be
designed to provide a dynamic range of well over 120 dB for
current-mode inputs (e.g., 1 nA to 1 mA). They are most useful where the signal is essentially static or only slowly varying. The design challenge here is to achieve excellent dc accuracy, usually with little emphasis on dynamic behavior.
Figure 2 shows a rudimentary translinear logamp having
a current input. It is clearly very incomplete, but it is immediately apparent that this circuit bears no resemblance to any
sort of familiar amplifier; in fact, it is a special kind of transresistance element, that is, an element generating a voltage
output in response to a current input. The practical translinear logamps use operational amplifiers to force the collectorcurrent input signal and further process the voltage-mode
output so as to eliminate temperature and device dependence.
Exponential-loop logamps are essentially high-precision
automatic gain control (AGC) systems. A crucial prerequisite
for accurate implementation is the availability of a variablegain amplifier (VGA) having an exact exponential relationship
between the control variable (usually a voltage) and the gain.
In linear IF strips, the RSSI function is usually derived from
the AGC voltage. The Analog Devices X-AMP technique for
precision low-noise VGA implementation (1) allows the realization of very accurate exponential-loop logamps; practical
examples will be presented.
Figure 3 shows the basic form. The technique is particularly attractive in ac applications, where the envelope amplitude of the signal is changing relatively slowly, such as spectrum analysis. It has the further valuable property that the
calibration metric may now be peak, average, or rms, depending on the choice of detector type: a representative
square-law cell is shown.
The principle is simple: the control loop through the integrator, which seeks to null the difference VDC VR, adjusts
the gain control voltage, which is also the logarithmic output
voltage VW, so that the output of the detector cell, VDC, will be
equal to the fixed reference voltage VR. To do that, the gain
must have a specific value, depending on the input amplitude
VX; using an exponential-controlled VGA, this causes VW to
assume a logarithmic relationship to VX.
Progressive compression is a key concept for high-speed envelope and pulse applications, and most logamps for wideband IF and RF applications are based on this technique,
which utilizes a series-connected chain of amplifier cells, each
having a simple nonlinear transfer characteristic. In one case,
the incremental gain of these cells is A up to a certain instan-

IX

519

VW

Figure 2. A rudimentary translinear logamp.

VW
Figure 3. A demodulating logamp based on an exponential VGA.

taneous input amplitude (called the knee voltage EK) falling

to 1 above this input. We will refer to these as A/1 cells. Using
this technique, the logarithmic output is developed at the output of the last cell in the chain. A/1-based logamps were once
widely used for baseband applications.
In a second type, the gain of the cell drops to zero above
the knee voltage; this will be called an A/0 or limiter cell. The
logarithmic output is now developed by summing the output
of all the cells, either linearly, for baseband applications, or
via a half-wave or full-wave rectifier (called a detector), in demodulating applications. The ease of implementing the A/0
limiter cell in monolithic form, its flexibility (a basic design
can readily be adapted for use in either baseband or demodulating operation), and its high degree of accuracy all make it
an excellent choice.
In both A/0 and A/1 types, the N-stage amplifier chain has
very high incremental gain AN for small signals (which is a
fundamental requirement of any logamp), and this gain progressively declines as the input amplitude increases. The logarithmic response over a given dynamic range can be approximated to arbitrary accuracy by choice of A and N, with some
obvious practical limitations (including noise and offset voltages at the low end, and cell overload at the high end). Because the gain is distributed over many stages, the signal
bandwidth can be very high.
Commonplace bipolar technologies readily provide cell
bandwidths of over 500 MHz, and operation to well over 10
GHz is possible using advanced heterojunction bipolar transistor (HBT) technologies. The AD8313 logamp uses a 25 GHz
process to achieve a 3.5 GHz cell bandwidth and provides accurate operation at signal frequencies of 2.5 GHz. These techniques can also be realized using complementary metal-oxidesemiconductor (CMOS) cells in a submicron process, although
scaling accuracy is somewhat harder to achieve in CMOS designs.
Baseband logamps are also known as video logamps, although they are rarely used in video (that is, display-related)
applications. They respond to the instantaneous value of a
rapidly changing input signal. Many board-level and hybrid
baseband logamps accept inputs having only one polarity, and
they are usually dc-coupled. They are used to compress pulse
signals in which the baseline must be accurately preserved.
When used after a microwave detector (typically a backward
diode), the combination is referred to as a detector video logarithmic amplifier, or DVLA.
Figure 4 shows a typical application. The numbers are for
illustrative purpose only; in practice, the smallest input may
be only a few tens of microvolts, calling for unusually low input-offset voltages, sometimes achieved by using an autonulling or dc restoration technique. The dynamic range of a video
logamp typically ranges between 40 dB and 80 dB. A DVLA

520
A

LOGARITHMIC AMPLIFIERS
32 mV
A

16 mV

C
D
E

8 mV
4 mV
2 mV

VX

Baseboard logamp

VW

16 mV

8 mV

4 mV

Slope = 1 V/octave
Intercept = 1 mV

Pulses
having
large
dynamic
range

32 mV

2 mV

Pulses
having
a small
dynamic
range

Figure 4. Context of a baseband logamp.

will often incorporate some deliberate deviation from an exact

logarithmic response, to first-order compensate the nonlinearities of the preceding microwave detector diode at the extreme
upper and lower ends of the signal range.
A baseband logamp that can accept inputs of either polarity and generate an output whose sign follows that of the input is sometimes called a true logamp, although this is a
misnomer, since a true log response would require the output
to have a singularity of as the input passes through zero,
and anyway the log function has no simple meaning for negative arguments. Instead, the output of a practical logamp of
this type passes through zero when the input does, just as for
any amplifier having a bipolar response. We will later show
that the formal response function for this type of logamp is
the inverse hyperbolic sine (sinh1), also called the ac log
function.
Demodulating logamps rectify the ac signals applied to
their input and those that appear at every cell along the amplifier chain. Detection at each stage is followed by summation and low-pass filtering to extract the running average.
The logarithmic output is then a baseband signal, essentially
a varying dc level, corresponding to the modulation, or envelope, amplitude of the RF input, rather than its instantaneous
value. This structure is called a successive-detection logamp
(SDLA). Practical demodulating logamps provide dynamic
ranges of from 40 dB to over 120 dB. Signal frequencies can
extend from near-dc to several gigahertz. The low-frequency
capability is invariably determined by the use of a high-pass
signal path, needed to suppress the accumulation of small offset voltages. This high-pass corner is typically between a few
tens of kilohertz and several megahertz and can be lowered
to subaudio frequencies in some general-purpose SDLAs, such
as the AD8307. Figure 5 shows the general applications conA
B
C
D
E

0
20
40
60
80

dBm
dBm
dBm
dBm
dBm

RF signal
having
large
dynamic
range

VX

VW
Demodulating logamp
Slope = 25 mV/dB (0.5 V/decade)
Intercept = 80 dBm

A
B
C
D
E

2.0
1.5
1.0
0.5
0.0

V
V
V
V

Quasi-dc
measure
of signal
strength
at input

Figure 5. Context of a successive-detection logamp.

text; the input is an RF carrier, the output is a quasi-dc

voltage.
In all high-frequency logamps, the management of noise
poses a major challenge. Noise is particularly troublesome in
demodulating logamps, because once it has been converted to
a baseband signal, it is indistinguishable (at the output) from
a constant low-level input, thus limiting the attainable dynamic range. Bandpass filters are sometimes inserted between stages to lower the noise bandwidth. A bandpass response may also be desirable as part of the overall system
function, for example, in the IF amplifier of a cordless or cellular phone, or in a spectrum analyzer. However, the design
of bandpass logamps needs great care, since the scaling parameters, which define the logarithmic response, are now inherently frequency-dependent.
Demodulating logamps do not respond directly to input
power, even though their input is often specified in dBm.
Rather, it is the signal voltage that determines the output. A
root mean square (rms) voltage of 223.6 mV represents a
power of 1 mW in a 50 load for a sinusoidal signal; this is
written 0 dBm, meaning 0 dB relative to 1 mW. At this input
level a logamp would respond with a certain output, say 1 V.
Now, if, in the design, we merely alter the impedance of the
input to 100 (without changing the voltage), the input
power halves, but the logamp response is unchanged. On the
other hand, logamps are sensitive to signal waveform: thus an
input of the same rms value but with a square or triangular
waveform would result in a different output magnitude from
that generated by a sinusoidal excitation; specifically, the logarithmic intercept is altered. The topic of waveform dependence will be addressed at length.
SCALING OF LOGAMPS
Generating the logarithm of a signal represents a significant
transformation. Close attention to the matter of scaling is essential. By regarding the logamp as a precision nonlinear element rather than a special kind of amplifier, the designer is
forced to think carefully about the source of these scaling parameters. If they cannot be defined with adequate precision,
it is likely that the circuit will not be stable with respect to
variations in supply voltage and temperature.
Thus, logamp design should begin with a clear formulation
of the basic function to be synthesized. For all voltage-input,
voltage-output logarithmic converters, of whatever type, this
must have the form
V X /VZ )
V W = VY log(V

(1)

where VW is the output voltage, VX is the input voltage, VY is

the slope voltage, and VZ is the intercept voltage. From the
outset, we are careful to use variables of the correct dimensions (all are voltages, in this case). Signals VX and VW are
uniformly shown in bold to differentiate them from constants
and internal voltages; they stand for the instantaneous values
of the input and output, at this juncture.
Normally, VY and VZ are fixed scaling voltages, but they
could be scaling control inputs. For example, it may be useful
to arrange for the slope to track a supply voltage when this
is also used as the scaling reference for an analog-to-digital
converter (ADC), which subsequently processes the logamps
output. Equation (1) is completely general and dimensionally

LOGARITHMIC AMPLIFIERS

consistent; this is important in developing a theory of logamps, and in designing them, since it maintains a strong
focus on the detailed sources of the functions scaling. The
practice of using factors of unclear dimension such as eOUT
K1 log K2eIN is discouraged (2).
The choice of logarithmic base is arbitrary. To preserve
generality, it is not defined in Eq. (1). A change of base merely
results in a change in VY. We will generally adopt base-10
logarithms, identified by the symbol lgt, in keeping with the
decibel-oriented context. However, in order to evaluate certain integrals when discussing the effect of waveform on intercept in demodulating logamps, we will occasionally switch
to ln, that is, natural (base-e) logarithms.
It is apparent from Eq. (1) that VW increases by an amount
VY for each unit increase in the quantity log(VX /VZ). When the
logarithm is to base ten, that statement reads: for each decade increase in VX. In that particular case VY has the meaning of volts per decade. Figure 1 showed this function for
VY 1 V and VZ 1 V. The logarithmic output VW would
ideally cross zero when VX VZ. In other words, VZ represents
the intercept of the transfer function on the horizontal axis.
This may not actually occur; VZ will often be the extrapolated
intercept, and for reasons of design its value may be so small
that the lower boundary on VW will be first limited by noise
or input offset voltage.
It is very easy to arrange for the intercept of a logamp to
have any desired value. This can be readily appreciated from
the following expansion:
V XVN /VZVN )
V W = VY log(V

(2)

V X /VN ) + VA
= VY log(V

where VN is the new value of the intercept achieved by adding

some constant VA to the output of the log converter, having
the value
VA = VY log(VN /VZ )

(2a)

Clearly, VA, and therefore VN, can have whatever value we

wish, and this voltage need not be physically sensible; it could
be as low as, say, 1 nV. Usually, it will be a few microvolts.
The intercept may be repositioned by adding or subtracting a
voltage to the output of a logamp, corresponding to VA (see
Fig. 6), often included as part of a temperature-compensation

technique, though internally the offsetting quantity is conveniently in current-mode form. The introduction of attenuation
at the input of a logamp only changes the effective intercept,
and does not affect the logarithmic slope:
V X /VZ )
V W = VY log(KV
V X /V
V N ),
= VY log(V

where VN = VZ /K

V W = VY log(II X /II Z )

(1a)

where VY, IX, and IZ have equivalent specifications. This is the

function of the rudimentary translinear logamp of Fig. 2,
elaborated in the next section.
Alternatively, all signals may be in current form:
I W = IY log(II X /IZ )

(1b)

This is less common, but certainly quite practical. Finally, the

function could be in the form of voltage input and current
output:
(1c)

This is the form found internally in RF logamps that use

transconductance cells for demodulation; in these cases, the
intermediate output current IW is later converted back to a
voltage VW, using a transresistance cell.

VA
decades
VY

5VY

(3)

These transformations will later prove useful when we need

to compensate basic temperature effects in the gain cells typically used in logamps.
A well-designed logamp has at least one high-accuracy dc
reference source, from which both VY and VZ are derived. The
Analog Devices AD640 provides an early example of a monolithic logamp designed with close attention to the matter of
calibration accuracy. It uses two laser-trimmed reference generators, of which one, a bandgap circuit, sets VY and the other,
a cell providing a bias voltage that is proportional to absolute
temperature (PTAT), accurately determines the cell gains,
which affect both VY and VZ. In a logamp, these voltage references play a role as important as those in an ADC or analog
multiplier. In the case of the AD606 and AD608, the reference
is the supply voltage. This is a deliberate simplification: in
their intended application, the ADC that processes the logarithmic (RSSI) output uses the same supply voltage for its
scaling reference.
The choice of voltage for inputs and outputs is mainly to
provide a suitable frame of reference for formal analysis. We
could have just as easily cast Eq. (1) in terms of a currentinput and voltage-output device:

V X /VZ )
I W = IY log(V
VW

521

4VY

Region Near Zero

VA
3VY

As the input VX tends toward zero from positive values, the

output VW will ideally approach . Differentiating Eq. (1),
using base-e logarithms, and ignoring at this point any resultant scale changes in VY, we can see that the incremental gain
of a logamp approaches as VX approaches zero:

2VY
VY
log VX
0
VX = 102Vz

VX = Vz

VX = 102VZ

VX = 104VZ

Figure 6. Repositioning the intercept.

VW

V
V X lnVZ )
=
V (lnV
VX
VX Y
V
V
V
= Y
VX

(4)

522

LOGARITHMIC AMPLIFIERS

The elimination of VZ in the expression for incremental gain

is consistent with the fact, already pointed out, that we can
arbitrarily alter VZ after logarithmic conversion by the addition or subtraction of a dc term at the output.
Since the overall amplifier gain must ideally tend to infinity for near-zero-amplitude inputs, it follows that the lowlevel accuracy of a practical logamp will be limited at the outset by its maximum small-signal gain (determined by the gain
of the amplifier stages and the number of stages, for the progressive compression logamps described later), and ultimately
by the noise level of its first stage (in the case of demodulating
logamps) or by the input-referred dc offset (in the case of
baseband logamps).
The incremental gaina familiar metric for linear amplifiers, where it ought to be independent of the signal level
will be found to vary radically for a logamp, from a maximum
value of perhaps 100 dB to below 0 dB at high inputs: Eq. (4)
shows that it is unity when the input voltage VX is equal to
the scaling voltage VY. In fact, the incremental gain of a logamp is never of great importance in the design process, but
its tremendous variation demonstrates the inadvisability of
lapsing into the use of small-signal analysis and simulation
studies when dealing with logamps.
So far, we have not mentioned the polarity of the signal
VX. For a baseband converter VX might be a positive dc voltage or pulse input, so Eq. (1) can be used without further
consideration. But what happens when VX becomes negative?
There is no simple meaning to the log function when its argument is negative. Fortunately, we do not have to consider the
mathematical consequences of this, because practical baseband logamps can be designed to handle inputs of either polarity, or, using appropriate techniques, inputs of both polarities. If mathematical rigor is needed, we can adapt Eq. (1) to
handle this situation by assuming that the circuit is arranged
in some way to respond only to the magnitude of VX and then
restore its sign at the output:
V X ) VY ln(|V
V X |/VZ )
V W = sgn(V

(5)

The bisymmetric function described by this equation refers to

what is sometimes called the ac logarithm. This function is
still not practical, however, because it requires that the output undergo a transition from to as VX passes
through zero, whereas in practical amplifiers intended to handle bipolar inputs VW will pass through zero when VX 0,
because of the finite gain of its component sections. The situation described by Eq. (5) and its practical limitations can be
handled by replacing the logarithmic function by the inverse
hyperbolic sine function:
1

sinh

u = ln(u +
ln 2u

u2 + 1)

for u > 1

for u  1

(6)
(7)

Note that
1

sinh

(u) = sinh

Figure 7 compares the ideal bisymmetric logarithmic function in Eq. (5) with the inverse hyperbolic sine in the region

f(u)
sinh1 u

log 2u
5

Imaginary

Real

Figure 7. Log and sinh1 functions for small arguments.

near u 0. The ac log function may thus be very closely

approximated by
1
V X /2VZ )
V W = VY sinh (V

(8)

As a practical matter, the region of operation corresponding

to extremely small values of VX will invariably be dominated
by noise, which appears to occupy an inordinate amount of
the output range. The use of a nonlinear low-pass filter (LPF),
whose corner frequency depends on the instantaneous output
of the logamp, is helpful. For outputs near zero, this filter
idles with a low bandwidth of, say, 1 kHz; a rapid increase
in the input to this adaptive filter immediately raises the
bandwidth, and the step response remains fast. A dead-zone
response near zero can be used to obscure low-level noise. In
marine radar applications, this is called an anti-clutter filter.
Effect of Waveform on Intercept
We have seen that a demodulating logamp operates from an
ac input signal and internally has detector cells that convert
the alternating signals along the amplifier chain into quasidc signals, which become the logamp output after low-pass
filtering. Now, we need to consider not just the amplitude of
VX, but also its waveform, since this can have significant practical consequences. In the performance specifications for a RF
logamp, the signal is invariably assumed to be sinusoidal, and
the intercept, usually specified as a power in dBm, also assumes this. For other waveforms, such as those arising for a
complex modulation mode, as in code-division multiple-access
(CDMA) systems, the effective value of the intercept will be
different.
If the input is an amplitude-symmetric square wave, the
rectification inherent in this type of logamp results in an intercept that would be identical to that for a constant dc level,
assuming the logamp is dc-coupled and uses full-wave detectors. For a sinusoidal input, where VX is specified as the amplitude (not the rms value), it will be exactly double this dc
value. For an amplitude-symmetric triangle wave, the intercept will appear to be increased by a factor of e 2.718. For a
noise input with some prescribed probability density function
(PDF) it will have a value dependent on the PDF: when this
is Gaussian, the effective intercept is increased by a factor of
1.887. While it is unusual for the behavior of a logamp to be
quantified for waveforms other than sinusoidal, it is valuable

LOGARITHMIC AMPLIFIERS

to establish these foundations before proceeding with practical designs (3).

These issues only became of more than academic interest
with the advent of fully calibrated logamps. Prior to that time,
the intercept had to be adjusted by the user, and demodulating RF logamps were calibrated using sinusoidal inputs. Of
course, the waveform dependence of the intercept does not
arise in the case of baseband (video) logamps, where there
is a direct mapping between the instantaneous value of the
input and the output. It is entirely a consequence of the signal
rectification of the detectors and the averaging behavior of the
post-detection low-pass filter, neither of which is present in a
baseband logamp.
We begin with the sine case and use base-ten logarithms,
denoted by lgt. We can write Eq. (1) in the form
VW

E sin
= VY lgt A
VZ

V W) =
Ave(V

/2
0

2VY
=

VY lgt


/2
0

2VY
ln 10

E A sin
d
VZ

lgt sin + lgt

/2

EA
VZ

ln sin + ln

EA
VZ

(10)


d

The definite integral of ln sin over the range of interest is

(/2) ln 2 and the complete integral yields

2VY

ln 2 + ln A
ln 10
2
2
VZ

E

VY
=
ln A ln 2
ln 10
VZ

V W) =
Ave(V

E A /2VZ )
= VY lgt(E

Using a similar approach for the triangular-wave input, we

can write
V W = VY lgt

V W) =
Ave(V
=
=

4
T


(13)

4VY
T

VY lgt


T /4
0

4VY
T ln 10

E

4t
VZ T
A

lgt t + lgt

T /4


dt

EA
4E
VZ T

ln t + ln

EA
4E
VZ T

(14)

dt


dt

The integral of ln t is simply t(ln t 1), yielding

EA
4E
T
T
T
T
4VY
ln + ln
T ln 10 4
4
4
4
VZ T

E

VY
=
ln A 1
ln 10
VZ

V W) =
Ave(V


(15)

In this case, the waveform signature is just 1; however, since

this may be written as ln e, the output becomes
V W ) = VY lgt(E
E A /eVZ )
Ave(V

(16)

Thus, a triangle-wave input will effectively cause the intercept to shift to the right by a factor of e, or 8.69 dB. Intuitively, this is not unreasonable: for any given amplitude the
triwave spends less time at its higher values than a sinusoidal waveform does, and consequently its average contribution
to the filtered output is reduced.
For a noise input having a Gaussian PDF with an rms
value of E, the effective intercept is most easily calculated by
first reducing the formulation to a generalized form. The average value of some variable x having a unit standard deviation, which has been subjected to a logarithmic transformation, can be expressed as

(11)

Simply stated, the response to an input having a sinusoidal

waveform and an amplitude EA will be the same as for a constant dc input having a magnitude of EA /2. The logarithmic
transfer function is shifted to the right by 6.02 dB for the case
of sine excitation, relative to the basic dc response.
The functional form of Eq. (11) deserves further attention.
Inside the parentheses we have the difference between a logarithmic term with the normalized argument EA /VZ and a second term, ln 2, which is a function of the waveform. This term
can be viewed as a waveform signature.

4t
VZ T

T /4

(12)

E

to describe the instantaneous output, where EA is now the

amplitude of a triwave of period T. The demodulated and filtered output is then

(9)

VW describes the instantaneous value of the output; however,

for a demodulating logamp, we will be concerned with the average value of VW, that is, the output of some postdemodulation low-pass filter. In this equation, EA is the amplitude of
the sine input and is its angle, more usually written as the
time-domain function t. The mathematical inconvenience of
negative logarithmic arguments can be avoided by considering the behavior of Eq. (9) over the range for which sin is
positive. In fact, we need only concern ourselves with the
principal range 0 /2, since the average over a full
period will be simply four times the average over this range,
assuming the use of full-wave rectification in the detectors.
The demodulated and filtered output is

523

ex


0

2 /2

ln x dx

ex 2 /2 dx

(17)

Note that the variable x represents the instantaneous value

of the input noise voltage [so it is actually x(t), but the time
argument is an unnecessary complication for this calculation].
The numerator and denominator are both standard forms (4):


ex ln x dx =

( + ln 4)
4

where is Eulers constant, and



ex dx =

524

LOGARITHMIC AMPLIFIERS

Hence

OA1
+

+ ln 2
4

RX

which evaluates to ln(1/1.887). In other words, the average

value of the logarithmic output in response to a Gaussian input of unit rms value is equivalent to a dc input of 1/1.887.
For a general input E,
V W ) = VS lgt(E
E /1.887VZ )
Ave(V

THE TRANSLINEAR LOGAMP

Logamps intended for use at dc or moderate frequencies traditionally invoke a translinear technique, though that term has
not generally been used in a logamp context. The word
translinear (5,6) refers to the remarkably exact logarithmic
relationship between the baseemitter voltage VBE and the
collector current IC in a bipolar junction transistor (BJT), of
pervasive significance in the design of analog bipolar circuits.
In particular, it results in the transconductance being linear
in IC. For the present purposes, this relationship can be written as

IC
IS + 1

(19)

where IS is a basic scaling parameter for the BJT, called the

saturation current, an extremely strong function of temperature, and VT is the thermal voltage kT/q. Thus, there might
at first seem little prospect of taming this temperature variability. In fact, translinear logamps can be developed to a
high degree of refinement. We will first convert Eq. (19) to
base-10 logarithms to bring it into line with the decibel-world
logamp perspective, slightly rearrange things, and again
show the key signal variables in boldface:
V BE = VY lgt

I

C + IS
IS

(20)

where
VY = VT ln 10

Positive
only

IX

Q1

IC

VW
Inverted
sign

Figure 8. Translinear logamp using an opamp to force IC.

(18)

where VS is a scaling parameter. This corresponds to an intercept shift of 5.52 dB. It is interesting to note that this is only
0.5 dB different from the rms calibration for a sine-wave input and might easily be attributed to measurement error in
the evaluation of the noise response of practical logamps.

VBE = VT ln

VX

(21)

The logarithmic slope VY is PTAT, and evaluates to 59.52 mV

per decade at T 300 K. The logarithmic intercept is simply
the saturation current IS, typically between 1018 A and 1015
A at this temperature. In Eq. (20) the signal input IC is augmented by this tiny current; we later address the consequences of this slight anomaly in the otherwise straightforward logamp form of the equation.
Figure 8 shows a scheme often used to force the collector
current IC to equal IX, the signal current applied to the logamp. (Compare with Fig. 2). This is sometimes called a
transdiode connection or Paterson diode (7). The usual

npn form is shown, requiring VX 0, but it is obvious that

use of a pnp transistor would simply reverse the required polarity of input current and the resulting polarity of output
voltage.
The transistor can be replaced by a diode or diode-connected transistor, with certain advantages, one of which is
that a bipolar response can now be achieved by using two
parallel opposed diodes. Another benefit is that the loop gain
around the opamp becomes essentially independent of signal
current, simplifying high-frequency (HF) compensation and
potentially raising the bandwidth. However, this technique
requires the opamp to have very low offset voltage VOS. Also,
since VBE bears a highly accurate, multidecade relationship
only to the collector current IC, logamps built using diode-connected transistors, in which it is IE that is forced, will exhibit
inherently lower accuracy.
The opamp OA1 forces the collector current of the transistor Q1 to equal the input current IX while maintaining its
collectorbase voltage VCB very close to zero. The condition
VCB 0 is not essential: for most purposes little harm will
result if the collector junction is reverse biased (this effectively increases IS), or even becomes slightly forward biased.
It can be shown that there is actually an advantage to using
a very specific value of the reverse collector bias (VCB 50
mV) in certain applications.
The logarithmic output is taken from the emitter node; the
opamp allows this to be loaded while preserving accuracy. In
most cases, IS will be very much less than IX and, replacing
IC by IX, we can simplify Eq. (20) to
V W = VY lgt(II X /IS )

(22)

Figure 9 shows an illustrative simulation result for this rudimentary circuit using an idealized npn, having IS 1016 A
at T 300 K, operating at temperatures of 50C, 50C,
and 150C. (The sign of the output has been flipped to maintain a uniform presentation.) The temperature dependences
of the slope and intercept are apparent. The output converges
on the bandgap voltage EG0 1.2 V at very high currents.
For high-temperature operation at very low currents, IS becomes comparable with the input current IX. The departure
from logarithmic behavior in this region can be corrected by
using a particular values of VCB, which is useful in logamps
that must operate accurately down to low-picoampere inputs.
The details lie beyond this treatment but are included in the
practical design shown in Fig. 10, which also includes means
(CC and RE) to ensure HF stability of the first loop around
OA1.
The basic scheme shown in Fig. 8 would exhibit large temperature variations, due to the dependence of IS in the underlying BJT equations, which directly determines the log inter-

LOGARITHMIC AMPLIFIERS

525

1000
900
800

T=

50

700

mV

600

=5

500
T

400

15

300
200
100
0
10 a

10 f

10 p

10

10 n
IX (A)

cept. The practical design includes a means for canceling the

temperature dependency of IS, using a second transistor Q2,
presumed here to be identical to Q1, and a second operational
amplifier OA2. Now we have

IX
IZ
+ VT ln
IS (T )
IS (T )
= VT ln(II X /IZ )

V W = VT ln

(23)

Thus, the intercept has been altered from a very uncertain

value (IS) to one of arbitrarily high accuracy (IZ) provided from
an external source.
Equation (23) still has a temperature-dependent slope voltage, VT kT/q. Also, the fairly small and awkward scaling
factor (59.52 mV/decade at 300 K) will usually need to be
raised to a larger and more useful value. This is achieved in
Fig. 10 using a temperature-corrected feedback network. RPT
is a resistor with a large positive temperature coefficient (TC),
while RF is a zero-TC component. If the ratio RF /RPT were very
high, RPT would need to be exactly PTAT (3300 106 /C at

EXPONENTIAL AGC LOGAMPS

The logarithm function is the inverse of the exponential function. In classical analog computing tradition, function in-

IZ

CC = 200 pF

RZ = 10 M

(100 nA)

IX

RE = 1k

10 pA to 10 mA
(120 dB)

RF = 1.58 k
Q2

Q1
Optional
VBCZ

OA2
VW

Vout (V)

Q1, Q2
Mat-02

OA1
+

Figure 9. Output of the basic translinear logamp.

T 30C), but for any finite ratio this resistor must have a
higher TC. Such resistors are readily available. Both the slope
and the intercept are now substantially free of temperature
effects. Figure 11 shows a typical result and the improvement
that can be achieved at low input currents by applying a
small PTAT bias to the base of Q1.
While some wide-dynamic-range transducers (photodiodes
and photomultiplier tubes) do generate current-mode signals,
the input signal will often be in the form of a voltage, VX. It
is a simple matter to adapt the logamp shown in Fig. 10 to
voltage-mode signals, using a resistor between VX and the
summing node. When the opamp uses a bipolar input stage,
and therefore exhibits considerable input bias current, the inclusion of an equal resistor in series with the noninverting
input of the opamp will serve to cancel its effect.

VR = +1 V
OA1, OA2
AD549

10 m

VCBZ = 41.6 mV
VCBZ = 0
Ideal logamp

0
2
4

RPT = 100
Ultronix Q811000

Figure 10. A practical design for a translinear logamp.

6
1012 1011 1010 109 108 107 106 105 104 103 102
Input current (A)

Figure 11. Performance of the practical translinear logamp.

526

LOGARITHMIC AMPLIFIERS

verses are generated by enclosing the function in a feedback

path around an opamp, which forces the output of the function to be equal to some input, at which time, the output of
the opamp (that is, the input to the function block) is the desired inverse. This is precisely what happens in the case of
the translinear logamp, where the forward direction through
the function blockin that case a transistoris exponential.
However, there are severe bandwidth limitations in attempting to cover a wide dynamic range in a single stage. A
special type of VGA, having precisely exponential control of
gain, can be used in place of the transistor, as shown in Fig.
12. Here, the gain of the amplifier cell decreases with increasing value of its control input, to which is applied the output
voltage VW, with a scaling voltage of VY. The output is thus
V W /VY )
VA = V X A0 exp(V

(24)

The second active block, essentially an error integrator,

forces VW to the value that results in the VGA output being
maintained at the reference voltage VR applied to the inverting input of the error amplifier. When that condition is
satisfied, we have
V W /VY ) = VR
V X A0 exp(V

(25)

V X /VZ )
V W = VY ln(V

(26)

VZ = VR /A0

(27)

Thus

where

The use of an exponential VGA response and an integrator

results in a simple single-pole low-pass response, for small
perturbations, independent of the magnitude of VX, over many
decades. Thus, we have realized a baseband logamp having a
constant small-signal bandwidth. Good operation can be
achieved even using a single VGA cell, which might use
translinear principles to realize the exponential gain law. In
practice, however, several lower-gain VGA cells will often be
used to realize the main amplifier, which will also be ac-coupled in many applications. For N cells the gain is
V W /VY ]N = AN
V W /VY )
A = [A0 exp(V
0 exp(NV

Gain = [ Ao exp(VW/VY)] N
VX

VGA1

VGAN

VR

Detector

N stages

1
sT
VW

Figure 13. Logamp based on cascaded exponential VGA cells.

stages simply alters the intercept to VZ VR /A0N and the slope

to VY VY /N.
A variety of demodulator styles is possible. The simplest is
a half-wave detector, based on a single junction; this provides
an averaging response. It has a mean output that is 0.318EA
for a sine-wave signal EA sin t, is EA /2 for a square wave
signal of amplitude EA, is EA /4 for a triwave signal, and so on.
A full-wave rectifier would simply double these numbers. Alternatively, we might use a peak detector, changing the dynamics of the loop considerably.
With a two-quadrant square-law detector, that is, one
responding equally to signals of either polarity, followed by
filtering to extract the mean square, the resulting loop
implements a root-mean-square (rms) measurement system
without having to use a square-rooting circuit (Fig. 14). Here,
the loop integrator seeks to null its input by forcing the mean
squared value of the detector output to the fixed reference
VR1. There is obviously no need to include the rooting function
before making this comparison; however, a more careful analysis of the scaling issues will show that a square-law detector
has its own scaling voltage:
VSQR = VOUT (t)2 /VR2

(29)

and the low-pass filtered output is thus

V W = Ave(VOUT (t)2 /VR2

(30)

where VR2 is the squaring cells scaling voltage. From Eq. (28),
V W /VY )
VOUT = VIN AN
0 exp(NV

(31)

(28)
and the loop forces VW to equal VR, so we have

To cover an 80 dB range of inputs, we might use four cells,

each of which provides a gain variation of one decade. A final
detector cell must be added, to convert the ac output to a
quasi-dc value, as shown in Fig. 13. Assuming for now that
the detector cell has an effective gain of unity, the use of N

V W /VY )]2 )
Ave([VIN AN
0 exp(NV
= VR1
VR2

(32)

Gain = [ Ao exp(VW/VY)] N

Gain = A = A0 exp(VW/VY)
VX

VGA

VX

VGA1

VGAN

VA = AVX
1
sT

VOUT

Squarelaw cell

N stages
VR2

VR

VSQR

1
sT

VW
Figure 12. A logamp based on a VGA with exponential gain control.

VR1

VW

Figure 14. Exponential AGC logamp providing rms metric.

LOGARITHMIC AMPLIFIERS

Mixer
L.O.
RF input
95 dBm
to 15 dBm

BPF

IF 1

IF 2

527

IF 3

IFOP

IF output
0 dBm

AGC
det.

Gain
Exponential
gain control

Gain scaling
reference

Gain
TC Comp.

C1
CAGC

Log output
VW
20 mV/dB

Gref
Figure 15. Exponential AGC logamp using AD607.

After some further manipulation, noting that the rms value

2
of the input signal can be equated to VIN through Vrms

2
Ave(VIN), we find

VW
NV
exp
VY

VR1VR2
=
Vrms AN
0

VW =

Vrms
VY
ln
N
VZ

(33)
(34)

where the effective intercept voltage is now

VZ =

VR1VR2
AN
0

(35)

The possibility of measuring true rms is of great value in

power measurements over the entire frequency span from
subaudio to microwave. This is a unique capability of this
type of logamp, which thus combines the rms feature with
the multidecade range of the logarithmic function. As noted
earlier, the effect of waveform on logamp behavior can be
quite complex, and the progressive-compression logamps to be
described next do not respond to the rms input (the true measure of signal power) but in waveform-dependent ways to
the input.
Note one further important advantage of this method. The
squaring circuit is forced to operate at constant output (VR1).
Therefore, it does not need to cope with a large dynamic
range, and can be very simple, provided that it exhibits an
accurate square-law response on peaks of signals of high crest
factor. Note that the amplifiers cells must also have sufficient
dynamic headroom for high-crest-factor operation. A monolithic realization of an exponential AGC logamp using a
mean-responding detector is to be found in the Analog Devices
AD607, a single-chip receiver capable of operation from inputs over at least an 80 dB dynamic range, from 95 dBm to
15 dBm (5.6 V to 56 mV amplitude for sine inputs), at
frequencies up to 500 MHz via its mixer (Fig. 15). The mixer
and three IF stages are each variable-gain elements, each
with a gain range of 25 dB, for a total of 100 dB, providing a
generous 10 dB of overrange at both the top and the bottom
of the signal range. The gain is controlled by the voltage,
which is accurately scaled to 20 mV/dB, and, due to the use
of special circuit techniques, is temperature-stable (8).

Figure 16 shows an AGC-style logamp based on a special

amplifier topology called an X-AMP, in this case, the AD600.
As the name suggests, these provide an exponential gain control function that is very exactly linear in dB but does not
depend on the translinear properties of the BJT to generate
the exponential function (1). The signal input is applied to
a passive resistive attenuator of N sections each having an
attenuation factor A. Thus, the overall attenuation is AN. In
the AD600, A 0.5 (that is, an R2R ladder is used) and
N 7, so the total attenuation is 42.14 dB. By means that
we need not discuss here, the voltage along the continuous
top surface of the ladder network can be sensed and amplified, and the position of the slider can be linearly controlled
by a gain control voltage VG.
It will be apparent that the logarithmic law in this case is
built into the attenuator. The advantage of the X-AMP topology is that a fixed-gain feedback amplifier of constant bandwidth, optimized for ultralow noise, can be used. This is directly connected to the signal at maximum gain, while at high
gains the signal is attenuated in the passive network, maintaining full bandwidth and linearity. Each section of the
AD600 provides a nominal 40 dB gain range (42 dB max), to
achieve a 80 dB logarithmic range. The gain-control interface is differential and at high impedance (50 M). The basic
gain scaling is 37.5 mV/dB for each section, but this is altered
in the Fig. 16 example to provide an overall logarithmic scaling factor of 100 mV/dB.
Further advances in logarithmic amplifiers based on the
use of exponential AGC loops are expected. In particular, the
use of new monolithic variable-gain amplifier cell topologies
combined with wideband square-law detectors has been
shown to provide 60 dB of true-power measurement range at
frequencies up to 2.5 GHz, placing this technique on an equal
footing with the more usual progressive-compression logamps
for microwave applications.

PROGRESSIVE-COMPRESSION LOGAMPS
It was shown in Eq. (4) that a logamp must have high gain
for small signals. Translinear logamps are of little utility in
high-frequency applications, mainly because all the gain is
provided by a single opamp having a very limited gain
bandwidth product. Exponential AGC logamps are valuable

528

R3
133 k

R2 200

VG
15.625 mV/dB

1/2
AD712

+
U3A

Input
1 V rms
max
R1
(sine wave) 115 k

Cal. 0 dB

R4
3.01 k

C2LO

A2HI

A2LO

GAT2

GAT1

A1LO

A1CM

C1LO
+

10

11

12

13

14

15

16

C2HI

A2CM

A2OP

VNEG

VPOS

A1OP

A1CM

C1HI

6 V dec.

+6 V dec.
C2
2 F

6 V
dec.

NC

NC

NC

BFIN

BFOP

NC

NC

NC

R6
3.16 k

+316.2 mV

VOUT

+6V

0.1 F

0.1 F

6V
Power supply
decoupling network

FB

6 V dec.
R7
56.2 k

C3
1 F

FB
+6 V dec.

6 V dec.

+100 mV/dB
0 V = 0 dB (at 10 mV rms)

1/2 U3A
AD712

VRMS

LDLO

VLOG COMM

CAVG

VPOS
U2
AD636
VNEG

C4
4.7 F

VINP

AF/RF
output

Figure 16. An 80 dB demodulating logamp with rms detector.

R5
16.2 k

C1
0.1 F

VRMS

LOGARITHMIC AMPLIFIERS

in high-frequency applications, where the high gain is provided by several variable-gain stages operating in cascade.
But these provide a relatively low loop bandwidth, since signal averaging is needed after the single detector stage. They
are therefore useful in determining the envelope level of a signal whose power is varying at a moderate rate (from hertz
to megahertz).
Baseband and demodulating logamps based on progressive
techniques achieve their high internal gain over a large number of cascaded cells and do not involve any kind of feedback
(2). Very high gainbandwidth products (of over 20,000 GHz
in practical monolithic products) can thus be achieved. They
do not depend on the nonlinearity of a semiconductor device
to achieve the desired logarithmic conversion. Rather, they
approximate a logarithmic law, in a deliberate and formally
correct fashion, through a type of piecewise linear approximation, over a wide dynamic range limited mainly by fundamental noise considerations. Demodulating types provide a logarithmic output that is a measure of signal strength (the RSSI
function), and these may also provide a hard-limited output
for use in applications where the signal modulation is encoded
in FM or PM form. Baseband types provide an output that
bears a point-by-point mapping between input and output.
The internal structure of the two types is similar, and cell
design techniques can often be shared. We will begin with a
development of the underlying theory for a baseband logamp
based on a particular type of amplifier cell, then move to cell
design that is easier to implement in monolithic form, and
finally show how the demodulation function is introduced.
The mathematical theory of progressive-compression logamps
is poorly developed in the literature, particularly with regard
to the essential matter of scaling, that is, the comprehensive
consideration of the fundamentals on which the accuracy of
this nonlinear function depends. In developing a theory from
first principles, we will be paying close attention to this topic.
A baseband logamp operates on the instantaneous value of
its input voltage, VX, to generate
V X /VZ )
V W = VY log(V

(1)

where VW is the output voltage, VX is the input voltage, VY is

the slope voltage, and VZ is the intercept voltage. We start
from these formal foundations, because we wish to develop a
sound theory of progressive-compression logamps, on which
the design of robust, manufacturable products can be based,
rather than simply discuss logamp behavior in general terms.
Our objective will be to find the scaling parameters VY and
VZ for specific circuits, of increasing complexity, starting with
a baseband logamp built from a chain of simple amplifier
cells, each with very simple scaling attributes.
Consider first an amplifier stage having the dc transfer
function shown in Fig. 17. For the time being, we will be concerned only with its response to positive inputs, but the theory is completely applicable to bipolar inputs. Furthermore,
throughout the development of the theory, we will not be concerned with the frequency-dependent aspects of the amplifier.
The gain for small inputs is A, a well-defined quantity
moderately greater than one (typically between 2 and 5), and
remains so up to an input (knee) voltage of EK, at which point
the gain abruptly drops to unity. We will call this a dual-gain
amplifier, or A/1 amplifier. Thus
VOUT = AVIN

for VIN EK

(36)

529

Vout

AEK

Slope = 1

A /1
EK

Slope = A
0

EK

Vin

Figure 17. The dc transfer function of an A/1 amplifier cell.

and
VOUT = AEK + (VIN EK )
= (A 1)EK + VIN

for VIN > EK

(37)

We can immediately reach some conclusions about the behavior of a logamp built from a series-connected set of N such
amplifier sections. First, because the amplifier behavior just
defined is piecewise linear, it follows that the overall function,
while more complicated, can never be anything but a
piecewise linear approximation. It is also clear that when
more stages, of lower gain, are used to cover a given dynamic
range, the closer this approximation can be. That is, we can
expect the approximation error to be some increasing function
of A.
Second, we can be quite certain that the logarithmic slope
VY and the intercept voltage VZ in the target function are both
directly proportional to the knee voltage EK, that is, we can
expect them to have the general form
VY = yEK

and VZ = zEK

where y is some function of A alone and z is a function of A

and N alone. We can predict this simple proportionality with
total assurance, because if some polynomial in EK were
needed, there would need to be other parameters with the
dimension of voltage within the system, in order to restore
dimensional consistency.
Our immediate challenge is to find the functional form of
y and z for the cascade of N dual-gain amplifier sections
shown in Fig. 18. This will provide a firm foundation for understanding all classes of logamps using progressive compression techniques. The overall input is labeled VX and the output VW in observance of the nomenclature already used. For
very small inputs, the overall gain is simply AN. At some critical value VX VX1 the input to the last (that is, Nth) stage

Stage 1

Stage 2

Stage N1

Stage N

VX

VW
A /1
EK

A /1
EK

A /1
EK

A /1
EK

Figure 18. A baseband logamp comprising a cascade of A/1 amplifier cells.

530

LOGARITHMIC AMPLIFIERS

reaches its knee voltage EK. Since the gain of the preceding
N 1 stages is AN1, this must occur at a voltage

AEK, so the output of the next stage, which is also the final
output, is

V X1 = EK /AN1

V W = (A 1)EK + AEK

(38)

= (2A 1)EK
This is called the linlog transition, because for smaller inputs the cascade is simply a linear amplifier, while for larger
values of VX it enters a region of pseudologarithmic behavior.
Above this point, the overall incremental gain falls to AN1. As
the input is raised further, a second critical point is reached,
at which the input to the (N 1)th section reaches its knee.
Then
V X2 = EK /AN2

(39)

which is simply A times larger than the first critical voltage.

We can call this the first midlog transition. Above this point,
the incremental gain falls by a further factor of A, to AN2,
and so on. It will be apparent that the cascade is characterized by a total of N transitions, the last occurring at VXN
EK. Figure 19 shows the voltages in an illustrative four-stage
system at its four transition points, which occur at input voltages separated by a constant ratio, equal to the gain A of each
amplifier section. This already looks promising, since if VX is
represented on a logarithmic axis, these transitions occur at
equally spaced increments on that axis, corresponding to a
ratio of A, while the output changes by equal increments of
(A 1)EK over this ratio.
The next step is to find the corresponding values of VW for
all intervals above the linlog transition and up to VX EK.
From Eq. (37),
V W = (A 1)EK + VNi

V W = (A 1)EK + V X AN1

(41)

We could use this starting point to find an expression for

VW for all values of VX. However, we do not need to delineate
all possible values of VW to determine the effective slope and
intercept of the overall piecewise linear function. At the first
midlog transition, the output of the (N 1)th stage is simply

Stage 1

Stage 2

A /1
EK/A3
EK/A2
EK/A
EK

Stage N1

A /1
EK/A2
EK/A
EK
AEK

So the output increased from AEK to (2A 1)EK, an amount

(A 1)EK, for a ratio change of A in VW. Continuing this line
of reasoning, we can demonstrate that at the next transition
VW (3A 2)EK, and so on: the change in VW is always by the
fixed amount (A 1)EK as VX increases by each factor of A.
Now, a factor of A can be stated as some fractional part of a
decade, which is just lgt A, where lgt denotes a logarithm to
base 10. For example, a ratio of 4 is slightly over six-tenths
of a decade, since lgt 4 0.602. We can therefore state that
the slope of the output function, corresponding to a line
drawn through all the transition points, is
VY =

absolute voltage change in V W

(A 1)EK
=
ratio change in V X
lgt A

Stage N

A /1

A /1

EK/A
EK
AEK

EK
AEK
(2A1)EK

AEK
(2A1)EK
(3A2)EK

(2A1)EK

(3A2)EK

(4A3)EK

Figure 19. Voltages along four cells at the transition points.

(43)

As expected, VY is proportional to EK, while the slope is unaffected by the number of stages, N. Since we are here using
base-10 logarithms, VY can be read as volts per decade. The
slope can be approximated by VY [2.4 0.85(A 1)]EK to
within 2.5% between A 1.2 and 5.5. To determine the intercept, we insert one point into the target equation and use
the resulting value of the slope. We can conveniently choose
the linlog transition, at which point VX EK /AN1 and VW
AEK. Thus
AEK =

(40)

where VNi is the input to the Nth stage. But at the linlog
transition, VNi EK, and therefore VW AEK. Further, because the first N 1 stages of the cascade are still in a linear
mode up to the second transition, VN in this interval is just
VX AN1. Thus,

(42)

EK
(A 1)E
lgt
lgt A
VZ AN1

(44)

EK
AN+1/(A1)

(45)

which solves to
VZ =

Suppose A 4, N 8, and Ek 50 mV. The choice of a

gain of 4 for each section is consistent with high accuracy and
wide bandwidth in a simple amplifier cell; using eight stages,
the dynamic range will be slightly over 48, which corresponds
to 96 dB; the choice EK 50 mV will become apparent later,
when it will be shown to arise from 2kT/q ( 51.7 mV at T
300 K). With these figures, the slope evaluates to 0.25 V/
decade and the intercept is positioned at about 0.5 V; the
response is shown in Fig. 20. In a practical amplifier handling
several decades and operating within the constraints of a 2.7
V supply, a somewhat higher value of EK could be used; values between 15 mV/dB and 30 mV/dB are common. As noted,
the slope and intercept can be readily altered by peripheral
modifications.
The output is seen to deviate from the ideal line, with a
periodic ripple at intervals of A along the horizontal axis. An
analysis of the ripple amplitude, expressed in decibel form,
shows that it is dependent only on A:
errorpk dB

(A + 1 2 A) lgt A
= 10
A1

(46)

LOGARITHMIC AMPLIFIERS

output for a 10 V input is thus 2 lgt(10/104) 10 V. Figure

22 shows a typical result.

1.6
1.5
1.4

Use of Limiting Cells

1.3

A simpler cell topology, more suited to monolithic integration,

can achieve the same function at very high frequencies (over
3 GHz in a practical embodiment such as the AD8313), and
with better accuracy than A/1 cells. In this nonlinear amplifier cell, the incremental gain is A for small signals, but drops
to zero for inputs above the knee voltage EK. This will be
called an amplifierlimiter stage, and is denoted by the symbol A/0. Figure 23 shows the transfer function of this cell,
now for bipolar inputs. The basic equations are

1.2
1.1
1.0
Output (V)

531

0.9
0.8
0.7
0.6

VOUT = AEK

0.5

VOUT = AVIN

for

0.4

VOUT = AEK

for VIN > EK

for VIN < EK

(47a)

EK VIN EK

(47b)
(47c)

0.3
0.2
0.1
0.0
100 n

10

100
1m
Vin (V)

10 m

100 m

Figure 20. Output of an eight-stage system using EK 51.7 mV,

A 4.

For A 4, this evaluates to 2.01 dB; some other values are

0.52 dB for A 2, 1 dB for A 2.65, 1.40 dB for A 10
(10 dB gain), and 2.67 dB for A 5. However, using practical
amplifier cells, which usually have an incremental gain that
is a continuously varying function of input voltage, the ripple
is much lower in amplitude and roughly sinusoidal, rather
than a series of parabolic sections as in the idealized case.
Numerous circuit arrangements are possible to implement
a dual-gain stage at low frequencies. An easily realized practical form, providing operation from dc to a few tens of kilohertz, using off-the-shelf components, is shown in Fig. 21. The
gain A of each opamp section switches from 3.2 (10 dB) to
unity at an effective EK of 0.436 V, determined by the twoterminal bandgap reference and resistor ratios. The last three
cells are slightly modified to improve the low-end accuracy.
The 1 dB dynamic range is 95 dB (220 V to 12 V), the
intercept is at 100 V, and the slope is 100 mV/dB (2 V/decade), making decibel reading on a DVM straightforward. The

8.25 k

RA = 464

1.34 k

15 V
supplies

V W = ANV X + AN1V X + + V X
VX
= (AN + AN1 + + 1)V

(48)

At the linlog transition,

V W = (AN + AN1 + + 1)EK /AN1

= A + 1 + +

1
AN1

(49)

EK

At the first midlog transition,

VW = A + A + 1 + +

1
AN2


EK

(50)

1/4 AD713
+

VX

Figure 24 shows the structure of a baseband logamp made

up of N such A/0 stages. It will be immediately apparent that
we can no longer use just the output of the final stage, since
as soon as this stage goes into limiting, when VX EK /AN1,
the output will simply limit at AEK and will not respond to
further increases in VX. To generate the logarithmic response,
the outputs of all stages must be summed. The milestones
along the log-input axis are at exactly the same values of VX
as for the A/1 case; so the challenge is to find the corresponding values of the output VW for all values of input VX up to,
and slightly beyond, EK.
For small inputs, below the linlog transition, and for
equal weighting of the individual cell outputs,

AD589

Seven similar
stages

VW

2.32 k

1 k

Stg. 6, RA = 392
Stg. 7, RA = 274
Stg. 8, RA omitted
Figure 21. A practical low-frequency logamp using
A/1 cells.

532

LOGARITHMIC AMPLIFIERS

11

Stage 1

10

Stage 2

Stage N1

Stage N

A /0

A /0

A /0

VX

VLIM
A /0

8
Vout (V)

7
6

VW

Figure 24. A baseband logamp using A/0 stages.

Vout

Ideal

1
0
105

104

103

102
101
Vin (V)

100

101

102

For typical values of A and N, this is very close to AEK /lgt A.

At the second midlog transition,

VW = A + A + A + 1 + +
3

Error (dB)

1
AN3

Thus, over the second interval the slope is

VY2 =

(A 1/AN3 )EK
lgt A


EK

(52)

(53)

Again, for typical values of A and N, this remains close to

AEK /lgt A. For example, if A 4 and N 8, the exact value
of VY2 is 6.642EK, while the approximate value is 6.644EK. It
is therefore reasonable to use the expression

1
2
3
105

104

103

102
101
Vin (V)

100

101

102

Figure 22. Measured output and absolute error (dB).

Between these two inputs, the output has changed by

VW = A

V

1
AN2


EK

while the input increased by a factor A, or lgt A decades.

Thus, the slope for this first interval, measured on the transition coordinates, is
VY1 =

(A 1/AN2 )EK
lgt A

(51)

Vout
Slope = 0
AEK
A /0
EK

Slope = A
0

EK

Vin

Figure 23. The dc transfer function of an A/0 cell.

VY =

AEK
lgt A

(54)

for the slope of this logamp over the entire lower portion of
its dynamic range. It can be shown that there is a slight reduction in the slope over the last few transition intervals.
This artifact can be corrected, and the top-end logarithmic
conformance in a high-accuracy design can be improved, by
simply using a higher summation weighting on the output
from the first stage, as will be shown.
To determine the intercept, we follow the procedure used
earlier: insert one inputoutput point into the target equation
and use the known value of the slope. The solution is almost
identical to that derived for the system using A/1 cells, given
in Eq. (45). The ripple calculation also follows the same approach as used above and yields essentially identical results.
The top end of the dynamic range gradually deviates from
the slope established at lower levels when the A/0 system is
used. This can be corrected by a technique first used in the
AD606. The analysis lies beyond the scope of this review; the
result is that the weighting of just the voltage at the input
must be altered by the factor (A 1)/A; when this is done,
the slope for all intervals is now exactly as given in Eq. (54).
It is of interest to note that the slope has a minimum sensitivity to the actual value of the basic gain when this is set to
A e (whatever the base of the logarithm). Thus, the logamp
scaling can be rendered less dependent on lot-to-lot variations
in gain (for example, due to ac beta variations) by using a
gain close to this optimum. Note also that the slope function
for the A/1-style logamp, namely VY (A 1)EK /lgt A, does
not behave so helpfully: it merely increases with A, and can
be approximated by VY [2.4 0.85(A 1)]EK to within
2.5% between A 1.2 and 5.5.

LOGARITHMIC AMPLIFIERS
Stage 1

Stage N1

Stage 2

the change in VW between any adjacent pair of transitions is

exactly VD. Thus

Stage N

VX

VLIM
A /0

A /0

A /0

A /0

VY =

gm

gm

gm

gm

gm

Stage 0

Stage 1

Stage 2

Stage N1

Stage N
IW

Figure 25. An A/0 baseband logamp using gm cells for summation.

Signal Summation
Figure 24 was unclear about the way in which the signals
along the amplifier chain are summed. In a monolithic circuit,
this will be effected in the current domain, using a transconductance (gm) stage at each cell output. This approach is appealing for three reasons. First, current-mode signals can be
summed by simply connecting the outputs of all stages together: the conversion back to voltage form can then be accomplished using either a simple resistive load or a transresistance stage. Second, they provide unilateral transmission
to the output nodes, minimizing the likelihood of unwanted
reverse coupling to sensitive nodes early in the signal path.
Finally, they provide the means to decouple the slope calibration from the parameters that control the behavior of the
main amplifier. This last benefit is central to the scaling of
monolithic logamps using differential bipolar pairs as the
gain cells, since the voltage EK, which controls the slope in all
the structures considered so far, is proportional to absolute
temperature. If totally linear, the interposition of these gm
cells would make no difference to the analysis, but because in
practice they are also in the nature of analog multipliers (being constructed of bipolar differential pairs, whose transconductance is proportional to the bias current), we have full and
independent control of the temperature behavior of scaling.
A voltage input Vj (the signal at any node j) generates a
current output GVj. The maximum output from a G/0 stage
(for Vj EK) is GEK, fully analogous to AEK for the voltagegain stage. The dimensional change inherent in the gm stage
means that this peak output is a current, which will here be
called ID. The subscript D refers to detector, anticipating the
function provided by this cell in demodulating logamps,
though we are here still considering baseband operation. The
currents ID, which will be provided by a precision biasing
means, control the logarithmic slope. The summed outputs
are converted back to the voltage domain using a simple load
resistance RD, or a transresistance stage of the same effective
scaling. We will define a parameter
VD = ID RD

533

VS
Igt A

(56)

that is, the voltage AEK has been replaced by a stable, independently controllable parameter. The intercept, however, remains proportional to EK, which will be PTAT when in a typical monolithic implementation. This will be addressed later.
Fully differential topologies are generally used in monolithic logamps, since they have a high degree of immunity to
noise on supply lines and can provide good dc balance. All
signals, including the summation signals from the G/0 stages,
have completely defined current circulation paths, keeping
unwanted signals away from common and supply lines. At the
very high gains and bandwidths typical of multistage logamps, only a very small amount of feedback from a downstream stage to the input may cause oscillation. For example,
an 80 dB amplifier chain having an overall bandwidth of 2
GHz has a gainbandwidth product of 20,000 GHz.
WIDEBAND MONOLITHIC LOGAMPS
Monolithic logamps of the progressive compression type, utilizing bipolar technologies, have been developed to a high
level of refinement during the past decade. A workhorse
gain cell, providing both the A/0 and G/0 functions, based on
the bipolar differential pair, allows the easy implementation
of both baseband and demodulating logamps, which can operate on a single 2.7 V supply voltage or lower.
We will first discuss baseband logamps. The design of demodulating logamps, which is mainly a matter of adding suitable detector (rectifying) cells to a structure that is otherwise
very much like a baseband logamp, is presented later.
Figure 26 shows the ubiquitous bipolar differential pair
with resistive loads, a simple but versatile amplifierlimiter
cell, which, with special biasing techniques, can have accurate gain even when the transistors have finite beta, ohmic
resistances, and other imperfections. Using ideal transistors,
the small-signal gain is
A=

VOUT
R
R I
= C = C T
VIN
rE
2VT

Thus, the tail current IT should be PTAT if the gain is to be

temperature-stable. It is important to note that the gain is a

Vsup
Rc

Rc

(55)

Figure 25 shows the revised scheme. Consistent with summing all the voltages at the amplifier nodes, we have added
another gm stage at the front, and labeled this the 0th cell.
The current ID for this cells is altered in according with the
above theory to improve the logarithmic-law conformance at
the top end of the dynamic range. With the modified
weighting D0 on just the 0th G/0 stage, it can be shown that

(57)

Vout
Vin
It

Figure 26. Differential amplifierlimitermultiplier cell.

LOGARITHMIC AMPLIFIERS

RC IT

Figure 27. Fitting A/0 to the differential amplifiers tanh function.

linear function of IT, in other words, this is also a multiplier

cell, an important asset in the development of the G/0 and
detector cells.
The peak differential output is
VOUT max = RC IT = 2VT A

(58)

Thus, a 10 dB amplifier (A 10) has a peak output of 51.7

mV 3.162 163.5 mVP. (The suffix P indicates a PTAT
quantity, referenced to T 300 K.) Without further consideration of the precise nonlinearity of this stage, we can already
fit this behavior to that of the ideal A/0 cell, noting that, in
general, an amplifier with a gain of A that limits at an output
of 2VT A implies a knee voltage of
Ek = 2VT

(59)

The full form of the transfer function is

VOUT = RC IT tanh(VIN /2VT )

(60)

Figure 27 shows how this fits the A/0 approximation. Because the transition from a gain of A to a gain of zero is
smooth, we can expect the ripple in the log conformance of an
amplifier constructed from such cells to be lower than that
using ideal A/0 stages with abrupt gain transitions, and such
is the case. In fact, the tanh function is highly desirable in
this application.
The input-referred noise spectral density of this cell evaluates to

en =

0.9255 nV/Hz1/2

IT

Vsup
RD
Aout

(61)

when IT is expressed in milliamperes. The attainment of low

noise is very important for the first one or two stages of a
logamp. To conserve overall current consumption, a tapered
biasing scheme is useful in a fully monolithic multistage design: the first stage will be scaled to use a higher tail current,
with a corresponding reduction in RC and a proportional increase in the size of the transistors. This is done in the
AD608, where the first stage operates at 4IT, the second at
2IT, and all further stages at IT; though not completely optimal, these are convenient in that the transistor and resistor

tanh

VX

VW

tanh

tanh
Stage 1

Figure 28. A baseband logamp using A/0 cells.

Stage 7

VIN

Stage 6

2VT

Stage 5

tanh

sizes bear simple binary ratios. Similar methods are used in

the highly calibrated laser-trimmed AD8306, the low-cost
AD8307, the general-purpose 500 MHz AD8309 with limiter
output, and the 0.1 GHz to 2.5 GHz power-controlling
AD8313.
A valuable property of this gain cell is that, for moderate
gains, it can be dc-coupled and cascaded indefinitely without
level-shifting or other intermediate components, such as emitter followers. Under zero-signal conditions, all transistors in
these cells operate at zero collectorbase bias VCB. Using a
product RCIT 8VT 206.8 mVP, a gain of 4 (12.04 dB) can
be maintained over the temperature range 55C to 125C
using a supply voltage of only 1.2 V. Since even lower gains
may be used in a wideband logamp, it will be apparent that
single-cell operation is possible. A high-f t process is important
in minimizing the ac loading of each cell by the next.
However, most practical designs achieve higher versatility
through the use of a 2.7 V minimum supply, and these may
also include the use of emitter followers between stages,
whose use increases the bandwidth and improves robustness,
through the power gain afforded and consequent reduction in
cell loading, and also because this increases the VCB from zero
to VBE, or about 800 mV. Furthermore, the overload behavior
of the gain cells is improved, by avoiding saturation when in
the limiting condition. However, for a 12 dB gain, now a supply voltage of at least 2.2 V is required at 55C, and the
power consumption is roughly doubled.
The basic (unloaded) cell already has some gain error due
to finite dc beta (0), since the collector current in each transistor is lowered by the factor 0 0 /(1 0), and the tail
current IT is also reduced by this factor. Fortunately, the multiplier aspect of this gain cell allows us to address this problem very simply, by raising the basic bias current according
to suitable corrective algorithms, built into the bias generator; the correction can be precise without knowing the value
of beta a priori.
Likewise, real transistors have ohmic resistances, rbb and
ree, associated with the baseemitter junction, which lower
the gain because they increase the effective value of the incremental emitter resistance re. Once again invoking the multiplier nature of the gain cell, and noting that by increasing the
bias current we can lower the basic re and restore the gain,

Stage 4

+RC IT

Stage 3

VOUT
Maximum gm is
(IT/2Vt ) sech2(VIN /2Vt )

Stage 2

534

LOGARITHMIC AMPLIFIERS

535

Vsup
Iout
2 k

2 k
Q4
Vout

Q3
Vin

Gain bias
VBE + 218 mVP

Q1
Q2
Q5

IT = 109 AP
2 k

ID = 25 AZ

Q6

Slope bias
VBE + 250 mVZ

10 k
Figure 29. One stage of the monolithic baseband
logamp.

In practice, the accuracy of a baseband logamp at the lower

end of the input range will be degraded by the input offset
voltage VOS and by noise. However, once good basic adherence
to the logarithmic function has been achieved, VOS can be
eliminated in critical applications by a corrective loop, while
noise (in this nondemodulating logamp) can be filtered even
after the final amplifier stage. Finally, a fully robust design
requires close attention to many biasing details. The cells
generating ID and IT will be specially designed to essentially
eliminate the sensitivity of all scaling parameters to temperature, supply voltage, lot-to-lot variations in beta and ohmic
resistance, device mismatches, and so on. While most of these
go beyond the scope of this review, we need to briefly discuss
how the intercept may be stabilized.
2.0
1.5

Vout (V)

1.0
0.5
0.0
0.5
1.0
1.5

V
0.4
sin1 in (mV)
2VZ
ln 10

2.0

Vout

correction can be built into the cointegrated bias cell (8,9).

Indeed, the utilization of synergistic biasing means is an essential aspect of contemporary monolithic logamp design.
A fairly complete baseband logamp, for simulation studies,
is shown in Figs. 28 and 29. It uses RC 2 k and IT 109
AP to provide a gain of 12.5 dB (A 4.217). Seven such cells
are used in this example, sufficient to demonstrate typical behavior, plus an eighth gm cell at the input, to extend the dynamic range upward. The current outputs of all G/0 cells are
summed by direct connection, converted to a voltage output
by the load resistors RD, and buffered by a difference amplifier, whose gain, AOUT, is chosen to set up a convenient overall
logarithmic slope, VY. Since the overall gain of the eight cells
is 87.5 dB, we can expect to cover a dynamic range of slightly
more than this with good accuracy, aided by the extra topend cell.
A temperature-stable ID of 25 A is used. With load resistors of RD 2 k, the voltage change over each 12.5 dB interval at the input is 50 mV (that is, 25 A 2 k), or 4 mV/
dB; using AOUT 5, the slope voltage is thus 20 mV/dB. The
input gm cell is operated at Id(A 1)/A, that is, at a current
about 30% higher, to improve the top-end law conformance.
This is a true logamp or ac logamp, since it can handle
either positive or negative inputs. Figure 30 shows the output
for small inputs (10 mV), and the difference between this
and the ideal sinh1 response, as formulated in Eq. (8), exactly
scaled by 0.4 V/ln 10; the peak error of 1.5 mV amounts to
0.075 dB.
Driving the input over a much larger input voltage range,
using an exponential dc sweep, we obtain the output shown
in Fig. 31; the intercept occurs at 0.5 V. The middle panel
shows that the dynamic range for a 1 dB error extends from
1 V to 60 mV, that is, 95.6 dB. The lower panel shows that
the log ripple (the deviation from an ideal logarithmic response) is 0.06 dB. Note that with IT 109 A and ID 25
A, we have used only 963 A, including the top-end correction, or 2.6 mW from a 2.7 V supply. Results of this sort demonstrate that amazingly accurate performance is possible using very simple, low-power cells; these simulation-based
predictions have been amply proven in numerous commercial
products. Using low-inertia IC processes, several-hundredmegahertz bandwidths can be achieved at milliwatt power
levels.

2.5
2.0
1.5
1.0
0.5
0.0
0.5
1.0
1.5
2.0
2.5
10

0
2
Vin (mV)

10

Figure 30. Output of the baseband logamp and deviation from the
sinh1 function.

536

LOGARITHMIC AMPLIFIERS
2.5

Vout (V)

2.0
1.5
1.0
0.5
0.0

Vout
V
20 log10 in
VY
VZ

10
5
dB 0
5
10

Vout
V
20 log10 in
VY
VZ

0.6
0.4
0.2

dB

0.2
0.4
0.6
100 n

10

100
1m
VOUT (V)

10 m

100 m

Figure 31. Output and deviation from ideal log function (expanded
in lower panel).

Temperature Stabilization of Intercept

The use of the G/0 stages eliminates the PTAT form of EK
from the slope calibration, but we have not yet addressed this
direct temperature dependence of the intercept. It can be expressed in decibels per degree Celsius in the following way.
The fundamental Eq. (1) can be written
V W = VY log

V

VZ0

T0
T


(62)

for an input VX that is temperature-stable and an intercept

VZ that is PTAT, having a value of VZ0 at T0. The decibel variation in output for a one-degree temperature change in the vicinity of T0 300 K is

dB = 20 lgt(300/301) = 0.029 dB/ C

(63)

For a 55C to 125C operating range the total change in

intercept is over 5 dB.
There are several solutions to this problem. Two methods,
both of which are provided in the AD640, will be described.
First, note that if we could somehow multiply VX by a factor
that is PTAT, we would completely cancel the reciprocal factor in Eq. (62). It makes no sense to consider doing this using
an analog multiplier based on, say, translinear techniques
(though in principle that is possible): it would be noisy, its
dynamic range would likely be much less than that provided

by the logamp; it would have dc offsets, it would limit the

attainable bandwidth, and so on.
However, a passive attenuator with PTAT loss has none of
these problems. We have already used such an attenuator in
the translinear logamp described earlier. In a monolithic implementation, the PTAT resistor can be made using, in part,
the aluminum interconnect metalization, which may be quite
low in value. If the input impedance is 50 , about 3 of
aluminum is needed, providing a nominal attenuation of
about 24 dB, with a corresponding increase in the intercept.
In the AD640 (where the input resistance is 500 ), laser
trimming is used to eliminate the large ratio uncertainty in
the two resistor layers. The use of an attenuator has the
added advantage, in certain cases, of raising the upper end of
the dynamic range, from about 60 mVP for the basic structure described here, to 1 V. The attenuator has no effect on
the slope voltage VY. This method provides an essentially perfect fix, without any artifacts. The intercept remains within
about 0.2 dB over the full military temperature range, and
the limits of the dynamic range are temperature-invariant.
The second approach illustrates another use of Eq. (2),
which showed that the intercept can be moved by simply adding or subtracting a suitable offset to the output. In this case,
the offset must vary with temperature. For a current-summing system, this can be achieved most simply by adding a
PTAT current directly to one of the log-summing nodes. For
a demodulating logamp, the output is unipolar, and the correction current is easily added. In the case of the baseband
logamp, it may be achieved just as readily, by using a correctly proportioned PTAT bias current for the last G/0 cell in
place of the stable current ID.
Figure 32 shows the result of using this simple modification on the baseband logamp shown in Fig. 28. This result
shows that the leftright shift in the basic response remains;
that is, unlike the use of a PTAT attenuator, this technique
slightly erodes the dynamic range. It can be seen that the net
1 dB range now extends from 2.5 V (at 125C) to 50 mV
(at 55C), which is 86 dB. (In practice, the reduction will be
less, because the lower limit of the dynamic range is determined by the noise floor.) On the other hand, the intercept
now varies by only 0.4 dB at either temperature extreme.
Looking at Eq. (62) more carefully, it is apparent that the
desired temperature compensation shape is not quite PTAT,
even though the intercept is. The reason is simply that there
is a logarithmic transformation between input and output
axes. A more exact function, of the form VFIX VY log(T/T0),
can be readily generated in a monolithic circuit, and is used,
for example, in the AD640.
Range Extension Using an Auxiliary Logamp
The top end of the dynamic range of this BJT logamp is limited by the signal capacity of the first G/0 cell. However, by
using two logamps operating in a parallel manner, the range
can be considerably extended (Fig. 33). The L amplifier, handling the lower part of the range, is driven directly by the
signal; it would be optimized for ultralow noise, and given
special attention with regard to thermal behavior in overload.
The U amplifier is driven via the attenuator and handles the
upper end of the dynamic range.
In this way, a very sensitive low-end response can be combined with the ability to handle input amplitudes that, with

LOGARITHMIC AMPLIFIERS

Motorola MC3356. A large amount of the knowledge about

logamps relates to discrete designs, and must, in a time of 30
GHz monolithic technologies, be regarded as all but obsolete.
The main features of logamps intended for the rapid determination of the envelope amplitude of an RF input are similar
to those delineated for a baseband logamp:

2.5

Vout (V)

2.0
1.5
1.0
0.5
0.0
Vout
V
20 log10 in
VY
VZ

15
10
5
dB

125C

0
5

55C

10

30C

15
1.0
Vout
V
20 log10 in
VY
VZ

537

55C
0.5
dB 0.0

125C

30C

0.5
1.0
100 n

10

100
1m
Vin (V)

10 m

100 m

Figure 32. Output (top panel) and error (lower panels) of baseband
logamp after intercept compensation, at T 55C (solid curves),
30C (dashed curves), and 125C (dotdash curves).

The necessary high gain is distributed over many lowgain, high-bandwidth stages of the amplifierlimiter, or
A/0, type, which subject the input to a process of progressive compression, and the logarithmic function approximation is analyzed using essentially the same mathematics as for the baseband logamp.
The output of all the amplifiers stages, plus the direct
input, is summed through the mediation a type of transconductance (G/0) cell; similar small adjustments to the
weighting of these cells can be used to improve the accuracy of the law conformance.
Differential circuit topologies are used to achieve a high
degree of HF balance and to minimize common-mode effects, such as the intrusion of spurious signals and noise
from the power-supply. L and U sections are used to extend the dynamic range; the attenuator sections are also
built in differential form.
The stabilization of the EK proportional logarithmic intercept over temperature can be achieved using either
signal multiplication by a PTAT attenuator at the input
or the addition of a temperature-dependent correction at
the output.
The chief differences are that:

appropriate design techniques, can be as large as the supplies

(for example, 5 V), provided that the emitterbase breakdown voltage of the input transistors in the L amplifier is not
exceeded. (The U amplifier never sees large inputs.) Both baseband and demodulating types can benefit from this treatment.
The choice of the attenuation ratio depends on several considerations, but it must have one of the values A, A2, A3, . . ..
Thus, using A 4, the choices would be 4, 16, 64, . . ., extending the 1 dB upper input from 62.5 mV to 0.25 V, 1
V, 4 V, . . .. A somewhat different approach is used in the
logamp section of the AD608, the AD8306, and the AD8309.
The upper end of the dynamic range in these cases is extended using independent attenuator sections, each followed
by a detector (G/0) cell.
The demodulation function can be introduced by a modification of the basic structure. The literature contains descriptions of many different practical ways to go about this, and
other methods are found in commercial products such as the

Vlim

VX
gm

A /0
A /0
A /0
gm
gm
gm

A /0
gm

The logamp now incorporates the demodulation function.

Its input is an ac signal (for example, a modulated sinusoidal carrier of from 100 kHz to several gigahertz, or possibly an audio signal), and its output is a single-polarity
(usually positive) voltage proportional to the logarithm of
the amplitude of this input.
This output is generated by rectifying the signals along
the amplifier chain and then averaging the resulting
fluctuating output over some finite time in a low-pass
filter, usually integrated into the output amplifier. Either
full-wave or half-wave rectification can be used. The former is preferable, since it doubles the carrier frequency
and thus reduces the residual carrier feedthrough at the
output of the low-pass filter. These rectifier cells (usually
called detectors in a logamp context) operate in a transconductance mode.
The cyclical ripple in the error curve is lower in a demodulating logamp, for similar values of A, than for baseband operation, because the instantaneous value of a
sinusoidal input voltage is sweeping over a wide range of
values during each cycle of the RF carrier. It is roughly
halved for sine excitation.

VW
RY
gm
Atten.

A /0

gm

gm
A /0

A /0

Slope
bias

Gain
bias

Figure 33. Wide-range logamp uses two parallel-driven sections.

The design of monolithic demodulating logamps is a specialist

topic, the details of which have yet to be fully described in a
comprehensive text. The material provided here has provided
the essential framework and emphasized the importance of
approaching all aspects of logamp synthesis with the fundamental issue of scaling firmly in mind.

538

LOGIC ARRAYS

BIBLIOGRAPHY
1. B. Gilbert, A low-noise wideband variable-gain amplifier using an
interpolated ladder attenuator, IEEE ISSCC Tech. Digest, 1991,
pp. 280281, 330.
2. R. S. Hughes, Logarithmic Video Amplifiers, Norwood, MA: Artech
House, 1971.
3. Analog Devices, High-Speed Amplifier Applications, Boston: Seminar Notebook, 1992.
4. I. S. Gradshteyn and I. M. Ryzhik, Tables of Integrals, Series and
Products, New York: Academic Press, 1980, Art 3.321.3, p. 307;
Art. 4.333, p. 574.
5. B. Gilbert, Translinear circuits: A proposed classification, Electron.
Lett., 11 (1), 1416; Errata, 11 (6), 136.
6. B. Gilbert, Translinear circuits: An historical overview, in Analog
Integrated Circuits and Signal Processing, Norwell, MA: Kluwer,
1996, Vol. 9, pp. 95118.
7. W. L. Paterson, Multiplication and logarithmic conversion by operational amplifiertransistor circuits, Rev. Sci. Instrum., 34, 1311
1316, 1963.
8. B. Gilbert, Advances in BJT techniques for high-performance
transceiver, Eur. Solid-State Circuits Conf. Rec., Sept. 1997, pp.
3138.
9. B. Gilbert, IF amplifiers for monolithic bipolar communications
systems, presented at EPFL Electronics Laboratories Advanced Engineering Course on RF Design for Wireless Communications Systems, Lausanne, 1996.
Reading List
B. Gilbert, Temperature compensated logarithmic circuit, US patent
No. 4,604,532, August 1986.
B. Gilbert, Aspects of translinear amplifier design, in W. Sansen et
al. (eds.), Analog Circuit Design, Norwell, MA: Kluwer, 1996, Part
III, pp. 257290.

BARRIE GILBERT
Analog Devices Inc.

LOGIC. See FORMAL LOGIC; LOGIC DESIGN.