Assignment:

MICROPROCESSER

Topic:
The 88x86 microprocessor Solution of problems 1 to 19 + 22 to 31+33+35 Submitted to: Mr: Talha sab Submitted by: Mr: Asad Amin Roll no 18 M.sc Applied physics

Department of Physics

B.Z.U Multan
Q#1:
Name the features of 8086 that were improvement over 8080/8085?

Ans:

(1) increased memory capacity from 64k to 1 megabyte (2) The 8086 is a 16bit microprocessor instead of 8bit (3) The 8086 was a pipelined processor Q#2: which microprocessor 8086 or 8088 was released first?

Ans: Q#3

8086 was released first

if the 80286 and 80386sx both have 16 bit external data buses what is the difference b/t them? Ans: the architecture of 80286sx is same as the 80386 but is different from the 80286 Q#4: Do program is written for the 88/86 run on 80286, 80386 and 80486 based CPUs? Ans: yes Q#5: what does 16 it or 32 bit microprocessor mean? Does it refer to the internal or external data path? Ans: 16 bit microprocessor means which is internally and externally a 16 bit microprocessor with 16 bit address bus. which can hold the physical memory of up to 2^16 and 32 bit contain 2^32 Q#6: what is the term upward compatibility mean?

Ans: The ability of newer or larger computer to accept program from older is the ability
of a system to gracefully accept input Q#7: which has the larger queue, the 8088 or 8086?

Ans: the queue (buffer) is 4 bytes long in 8088 and6 bytes in 8086 Q#8: state another way to increase the processing power of the CPU other than
increasing the frequency? Ans: there is to ways to make the CPU process information faster increase the working frequency or change the internal architecture of CPU, the internal architecture improving the internal working of CPU Q#9: what do BIU and EU stands for and what are their functions?

Ans: BIU stands for Bus Interface Unit and EU is Execution Unit and BIU access
memory and peripherals fetches instruction .EU execute the instruction that previously fetched Q#10: name the general purpose registers of 8088/86? (a) 16 bit (b) 8 bit Ans: (a) AX(Arithmetic register) ,BX(Base register) ,DX (Data register) , CX(Code register (b) AH , AL , BH , BL CH , CL , DH ,DL Q#11: Which of the following registers cannot be split into high and low bytes?

Ans: Q#12:

CS, DS, SS, SI, DI, cannot be split into high and low bytes

which of the following instructions cannot be coded in 8088/86 Assembly language? Give the reasons why not if any to verify your answer,

Ans:

(a) MOV AX, 27 move 27 in AX (b) MOV AL, 97F cannot move 97Fis big then AL (c) MOV DS, 9BF2 operand cannot directly move to segment register (d) MOV CX, 397 move 397 into CX (e) MOV SI, 9516 move 9516 into SI (f) MOV CS, 3490 operand cannot directly move to segment register (g) MOV DS, BX copy the contents of BX to DS (h) MOV BX, CS copy the contents of CS to BX (i) MOV CH, AX CH is operand which cannot be destination (j) MOV AX, 23FB9 23FB9 move to AX (k) MOV CS, BH operand cannot directly move to segment (l) MOV AX, DL copy the contents of DL into AX Q#13 Name the segment registers and their functions in the 8088/86

legal illegal illegal legal legal illegal legal legal illegal legal illegal legal

(i) Code segment contain the assembly language instructions that perform the tasks that the program was designed (ii) Data segment is used to store information (data) that needs to be processed by the code segment (iii) Stack segment is used to store information temporarily Q#14 if CS=3499H and IP= 2500H, find?

Ans:

Ans

(a) the logical address CS : IP 3499 : 2500 (b) Physical address Shift of CS = 34990 IP = 2500 36E90 (c) lower range Shift of CS =34990 0000 34990 Upper range Shift of CS = 34990 FFFF 4498F Q#15: if CS=1296 and IP = 100H

Ans:

(a) the logical address CS : IP 1296 : 100 (b) Physical address Shift of CS = 12960 IP = 100 12A60 (c) lower range Shift of CS =12960

0000 12960 Upper range Shift of CS = 12960 FFFF 21A5F : if DS : 3499H and offset =2500H find?

Q#16 Ans

(a) the logical address DS : offset 3499 : 2500 (b) Physical address Shift of DS = 34990 offset = 2500 38919 (c) lower range Shift of DS =34990 0000 34990 Upper range Shift of DS = 34990 FFFF 4498F Q#17: if DS: 1298H and offset =7CC8H find? (a) the logical address DS : offset 1298: 7CC8 (b) Physical address Shift of DS = 12980 offset = 7CC8 1A758 (c) lower range Shift of DS =12980 0000 12980 Upper range Shift of DS = 12980 FFFF 21A7F Q#18: Assume that the physical address for a location is 0046CH . Suggest a possible logical address ? Ans : 0000 : 46C

Ans:

Q#19:

if an instruction that needs to be fetched is in physical memory location 389F2 and CS = 2700 does the code segment range include it or not if not then what value should be assigned to CS if IP =1282?

Ans :
Physical memory location = 389F2 CS = 2700 Shift of CS = 27000 FFFF 36FFF So 36FFF is less then 389F2 which is out of range so due to this instruction cannot be fetched so Shift of CS = 27000 IP = 1282 28282 Q#22: the stack is

Ans: A section of RAM used for temporary storage. Q#23: what is the stack pointer? Ans : some memory inside the CPU . Q#24: Ans: when data is pushed onto the stack ,the stack pointer is decremented
when data is popped off the stack , the stack pointer is incremented Q#25: choose the correct ans ?

, but

Ans : to read and write in CPU Q#26: what are the main disadvantages of the stack as temporary storage
compared to having a large number of registers inside the CPU? Ans : the main disadvantage of the stack is its access time since the stack is in the RAM takes much time longer to access compared to the access time registers .

Q#27 : Ans :

SS : 2000

and SP : 4578 find?

(a) the logical address SS : SP 2000 : 4578 (b) Physical address Shift of SS = 20000 SP = 4578 24578 (c) lower range Shift of SS = 20000 0000 20000 Upper range Shift of SS = 20000 FFFF 2FFFF Q#28 : if SS : 24FC , what is the offset address to he first location of the stack that is available to push data into ? Ans : SS : 24FA Assume that SP = FF2EH, AX = 3291H, BX = F43CH and CX= 09.find content of the stack and stack pointer after the execution of the following instructions: PUSH AX PUSH BX PUSH CX Ans : SP = FF2EH AX= 3291H BX = F43CH CX= 09 Now we PUSH the data PUSH AX PUSH BX PUSH CX SS:FF27 SS:FF28 09 SS:FF29 00 SS:FF2 3C 3C A SS:FF2B F4 F4 SS:FF2C 91 91 91 SS:FF2 32 32 32 D SS:FF2E

Q#29:

Start SP : FF2E

PUSH AX AX=3291 SP : FF2C

PUSH BX BX=F43C SP: FF2A

PUSH CX CX=09 SP:FF28

Q#30: Now POP the above question

Ans:
SS:FF2E SS:FF2F SS:FF30 SS:FF31 SS:FF32 SS:FF33 SS:FF34

POP CX POP BX POP AX 09 00 3C F4 91 32

3C F4 91 32

91 32

Start SP : FF2E POP CX CX=09 SP : FF30 POP BX BX=F43C SP: FF32 POP AX AX=3291 SP:FF34

Q#31: the following registers are used as offsets. Assuming that the default segment is
used to get the logical address,

Ans:
(a) (b) (c) (d) (e) (f) BP : SP : SS CS : IP DS : SI DS : BS DS : DI

Q#33: find the status of the CF,PF,AF,ZF, and SF for the following operations.
(a) MOV BL , 9FH ADD BL, 61H Ans : 9F 1001 1111 61 0110 0001 00 0000 0000 th CF = 1 (there is a carry at 7 bit to next) PF = 1 ( no of 1s are even ) AF = 1 (there is a carry 3rd bit to 4th) ZF = 1 (the result is zero) SF = 0 (7th bit is zero shows sine) (b) MOV AL,23H MOV AL, 97H

Ans :

23 0010 0011 97 1001 0111 BA 1011 1010 th CF = 0 (there is no carry at 7 bit to next) PF = o ( no of 1s are odd ) AF = 0 (there is no carry 3rd bit to 4th) ZF = 0 (the result is not zero) SF = 1 (7th bit is 1 shows sine) (c) MOV DX , 10FFH ADD , 1 Ans : 10FF 0001 0000 1111 1111 0001 0000 0000 0000 0001 1100 0001 0001 0000 0000 CF = 0 (there is no carry at 7th bit to next) PF = 1 ( no of 1s are even ) AF = 1 (there is a carry 3rd bit to 4th) ZF = 0 (the result is not zero) SF = 0 (7th bit is zero shows sine)

Q#35: Give the addressing mode for each of the following? Ans:
(a) MOV AX, DS (b) MOV BX, 5678H (c) MOV CX, [3000] (d) MOV AL, CH (e) MOV [DI], BX (f) MOV AL, [BX] (g) MOV DX, [BP+DI+4] (h) MOV CX, DS (i) MOV [BP+6], AL (j) MOV AH, [BX+SI+50] (k) MOV BL, [SI]+10 (l) MOV [BP][SI]+12, AX Operand addressing mode Immediate addressing mode Directed addressing mode Operand addressing mode Based addressing mode Directed addressing mode Indirect addressing mode Operand addressing mode Based addressing mode Indirect addressing mode Indexed addressing mode Based addressing mode