A Synchronous Data Transfer
A Synchronous Data Transfer
A Synchronous Data Transfer
Handshaking
A control signal is accompanied with each data being transmitted to indicate the presence of data The receiving unit responds with another control signal to acknowledge receipt of the data
STROBE CONTROL
Employs a single control line to time each transfer. The strobe may be activated by either the source or the destination unit.
Da ta b us S o urc e unit S tro b e (a ) Blo c k d ia g ra m De s tina tio n unit S o urc e unit Da ta b us S tro b e (a ) Blo c k d ia g ra m De s tina tio n unit
Da ta
Va lid d a ta
Da ta
Va lid d a ta
1- Source-initiated strobe
2- Destination-initiated strobe
To solve this problem, the HANDSHAKE method introduces a second control signal to provide a Reply to the unit that initiates the transfer
Handshake: 1- Source-initiated
Da ta b us S o urc e un it Da ta va lid Da ta a c c e p te d (a ) Blo c k d ia g ra m De s tin a tio n un it
Da ta
Va lid d a ta
Da ta va lid
Da ta a c c e p te d (b ) Tim ing d ia g ra m
Ac c e p t d a ta fro m b u s Ena b le d a ta a c c e p te d
Handshake: 2- Destination-initiated
Da ta b us
a high Handshaking providesreliability degree of flexibility and because the successful completion of a data transfer relies on active participation by both units
S o urc e unit
Da ta va lid Re a d y fo r d a ta (a ) Blo c k d ia g ra m
Re a d y fo r d a ta
Da ta va lid
Va lid d a ta Da ta b us (b ) Timing d ia g ra m
S o urc e unit
Ac c e p t d a ta fro m b us Dis a b le re d a y fo r d a ta
(c ) S e q ue nc e o f e ve nts
Character bits
A character can be detected by the receiver from the knowledge of 4 rules; - When data are not being sent, the line is kept in the 1-state (idle state) - The initiation of a character transmission is detected by a Start Bit , which is always a 0 - The character bits always follow the Start Bit - After the last character , a Stop Bit is detected when the line returns to the 1-state for at least 1 bit time The receiver knows in advance the transfer rate of the bits and the number of information bits to expect
Transmitter Register
- Accepts a data byte(from CPU) through the data bus - Transferred to a shift register for serial transmission Receiver - Receives serial information into another shift register - Complete data byte is sent to the receiver register Status Register Bits - Used for I/O flags and for recording errors Control Register Bits - Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of stop bits
References
Mano. M. Morris, Computer System Architecture/ M.
Morris Mano-- 3rd Edition.