Ring counter:

This is a special type of register in which 1 moves in the output in the ring i.e. initially output of 1st FF is 1. On next edge this 1 is transferred to output of 2nd FF while previous output becomes 0. Similarly on next clock output of 3rd FF becomes 1. Similarly it continuous till last FF goes 1. After this 1st FF goes 1 goes again and whole procedure is repeated. This way 1 is moved in a ring as:

i.e. Clock Initially 1st tick 2nd 3rd 4th And so on Q 4 Q3 Q2 Q1 0001 0010 0100 1000 0001

Hence we use only 4 states out of 16 states possible in Ring counter. Or we can say there are 12 unused states in Ring counter.

Circuit diagram to achieve Ring Counter is as:

To start the Ring counter, we firstly give START=0 and then rightmost FF is set and all others are reset and hence initial output is 0001 We can also realize Ring counter using JK flip-flop as:

Application: We can use Ring counter in the system where we have to perform different operations sequentially and repeatedly. Suppose we have to do operations A, B, C & D. Firstly we have to do A, then B, then C, and then D. after performing all operations we have to perform operation A and so on. In this case we can use Ring counter to initiate these operations sequentially

Johnson Counter:
While Ring counter, we have connected Q of last to D of 1st FF, but in Johnson Counter we connect Q bar of last to D of 1st FF as shown below and we also dont need to connect preset of 1st FF. This is also called Twisted Ring counter:

And JK implementation is as follow:

And we have outputs has follow: Clock Initially 1st tick 2nd 3rd 4th 5th 6th 7th 8th Q 4 Q3 Q2 Q1 0000 0001 0011 0111 1111 1110 1100 1000 0000

We can also note that we use only 8 out of 16 possible states and in general we have used 2n states and hence we have 2n-2n unused states

Q- Design a circuit to transfer data serially from one shift register to other.
Ans: If we have a N-bit shift register then we need only N clock cycles to shift those N-bits to the other register. If we apply more or less than this many clock cycles then our operation of shifting would not be as required. Hence we have to give a control pulse which would control that only N clock cycles are given to the registers. The circuit diagram is as follow:

If we are to transfer data between 4 bit register then control pulse would be 4 clock cycles wide as shown so that only 4 clock cycles are passed.

Following table would show the values of two registers at different clock cycles Register 1 1101 First clock 2nd clock 3rd clock 1110 0111 1011 Register 2 Output 1001 1100 0110 1011 1 0 0

4th

1101

1101

Hence we see that register1 retains its contents and register2 gets the value of register2 which was required.

ASYNCHRONOUS COUNTERS - MOD-2 counter:

If we see that flip-flop is a mod-2 counter with starting count as 0. If we connect J & K to HIGH and supply clock to the flip-flop, well see that flip-flop would count pulses 0, then 1 and as it is a MOD-2 counter so itll reset and again count from 0.

And the output is as:

Also note that output pulse is of half the original frequency of the clock. Hence we can say that flip-flop acts as a Divide by 2 circuit. We can attach more flip-flops to make larger counter. We just use more flip-flops in cascade and give output of first to the clock of 2nd and output of 2nd to clock of 3rdand so on. This way every flip-flop would divide frequency of the clock by 2 and hence we can obtain a divide by larger value circuit. Lets see how we can make larger counters:

And following waveforms would illustrate how the above circuit does counting. It is actually a MOD-8 counter so it would count from 0 to 7 and then again reset itself as shown:

With every negative edge, count is incremented and when the count reaches 7, next edge would reset the value to 0. These waveforms represent count as (Q3 Q2 Q1) 2.

Hence we can design a MOD-2n counter using n flip-lops in cascade

Counter other than MOD-2n

Q-Can we design a ripple counter other than MOD-2n? Ans: Yes we can. For this well first design the counter with value which is multiple of 2 but greater than the count required. Then we use a combinational circuit to reset the counter after the required value of count is achieved. Lets take an example: Design a MOD-14 counter. First we design a counter of 2s multiple greater than 14 which is 16. So we first design a MOD-16 counter as:

Now we need to design a combinational circuit which would take care that counter is reset when count value reaches 13. For this we first draw the waveforms as:

As we have to count till 13 and reset again. We see that when-ever Q4=1, Q3=1 & Q1=1, when have to reset the value of all the flip-flops so that we get the value of count as 0. Hence we take NAND of these 3 variables due to which we get a zero when all 3 variables are 1 and output of NAND gate is connected to all the ACTIVE LOW CLEAR lines to reset all flip-flops as follow. We also have to make sure that the output of this NAND gate is zero only after 13.

And now we the output waveforms as:

And we can clearly observe that we have achieved MOD-14 counter as all count values are reset after 13 but in this method we have to observe the output waveforms and then decide the combinational circuit to reset value after certain count.

USING K-MAPS TO DESIGN COUNTER

Q- Design MOD-3 ripple counter using (a) Observing outputs (b) K-maps to design the circuit. Ans: (a)We can design the MOD 3 counter using 2 FFs as 3 is less than 4 i.e. 2 2 and greater than 2. We can see directly that as we have to reset the counter only after 2 i.e. when output is 3 we reset the counter and hence we need to reset only when we have Q0= 1 & Q1=1. Now firstly design MOD-4 counter using 2 FFs and then take NAND of Q0 & Q1 and feed the output to CLEAR of both FFs.

(b) We firstly draw state diagram of the counter required as:

And we have the general circuit to design the other than MOD 2 n then we have the general circuit as

And now we draw a table to list the different input combinations to Combinational circuit and their corresponding output as: Q1 0 0 1 1 Q0 0 1 0 1 OUTPUT of reset logic 1 1 1 0

And using K-map as

And hence we get the whole circuit for MOD-3 counter as

Q- Can we design a MOD-6 counter using the above method?

Ans: We firstly draw the state diagram

And now we draw the table to represent the desired output of the combinational circuit to reset FFs as: Q2 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 OUTPUT 1 1 1 1 1 1 0 0

And using K-map we get the combinational circuit as

And the complete circuit is as:

QDesign the ripple counter whose output sequence is represented by the following state diagram.

Ans: As it is a 3-bit counter hence we firstly arrange 3 FFs and now we design the combinational circuit to reset the counter at appropriate point. Q2 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 OUTPUT 0 1 1 1 1 1 1 0

And using K-map we get the combinational circuit as:

And the equation we get is Z= Q2. (Q1 bar) + Q0. (Q1bar) + Q1. (Q0bar) = Q2. (Q1 bar) + XOR (Q1, Q0)

OR We can also have the equation as Z= Q0. (Q1 bar) + Q1. (Q2bar) + Q2. (Q0bar)

And hence can have two types of combinational circuits to achieve the above counter. And the whole circuit with first combinational circuit as:

Here well be counting in reverse order i.e. count would start from 15 to 0 and again value goes from 0 to 15. We just make a change in the circuit as we give Q bar to the CLK of next flip-flop or we use positive edged flip-flops and give Q to CLK of next flip-flop.

And the output waveform would be as:

Or

And the output waveform would be as:

In both cases we take (Q4 Q3 Q2 Q1) 2 as value of the count

Or We can just use the same circuit as the UP counter but

Consider the following circuit

And we see that this circuit is a UP counter which count from 0 to 7 and then it is reset but the same circuit can also work as DOWN counter when we take count as combination of inverted outputs for each FF. i.e. . Hence output count of the above circuit would go from 7 to 0 and then again it is set to 7.

Q- Design the ripple counter whose output sequence is represented by the following state diagram.

Ans: As we can see that it is a down counter so well be using Q bar of all flip-flops as clock to next flip-flops (negative edged FFs). We draw the table as Q2 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 OUTPUT 0 0 1 1 1 1 1 1

And using K-map we get the combinational circuit as:

And the equation we get is Z= Q2 + Q1

And the whole circuit is as:

GLITCH:
A glitch is an unwanted pulse which gets generated due to little difference in the delays of signals. Whenever signals with glitches are used as clock then glitches causes unwanted triggering of the flip-flop. e.g.

We can see in the wave-forms given above for MOD-14 counter that there is a glitch in the Q2 signal which is produced due to delay of AND gate to reset the FF. Also a glitch can be generated when we AND two signals and there is a slight delay between two signals. Such a combinational circuit is used when we have to transfer data serially between two registers discussed already and we need limited number of clock cycles for proper working.

The following circuit was designed to produce enable signal (with 4 clock cycles)

But due to slight delay in the one of the input signals there is glitch in the output which would lead to mal-functioning of the circuit.

Synchronous Counter
In synchronous counters we have the same clock signal to all the flip-flops. MOD-4 Synchronous counter: We discuss here a 2-bit synchronous counter. We have the circuit for this as:s

We have the initial outputs as Q0=0 & Q1=0. Whenever the first negative clock edge comes O/P of 1st FF becomes 1 as we have J & K for 1st FF as 1 and hence output of 1st FF toggles and changes from 0 to 1. But when 1st cock edge had come output of 1st FF was 0. Hence J & K for 2nd FF for 1st edge are 0. So output of this FF doesnt change and we get Q1=0. so the output is (Q1Q0)2= 012.

On the next edge, output of 1st FF changes from 1 to 0 as J & K are always 1 for this FF. Inputs for 2nd edge for 2nd FF are J=1 & K=1. Hence output changes from 0 to 1. so we get the count as (Q1Q0)2= 102. Similarly on the next edge well get the output count as (Q1Q0)2= 112. And on the 4th clock edge both the outputs get reset and we get the output as (Q1Q0)2= 002 and again whole procedure is repeated. Well be studying other synchronous counter when we discuss the design of synchronous circuits later. Asynchronous The logic circuit of this type of counters is simple to design and we feed output of one FF to clock of next FF Propagation time delay of this type of counter is : Propagation Time Tpd = N * (Delay of 1 FF) which is quiet high N is number of FFs Maximum operating frequency And hence operating frequency is Low Synchronous The circuit diagram for type of counter becomes difficult as number of states increase in the counter Propagation time delay of this type of counter is: Tpd = (Delay of 1 FF) + delay of 1 gate Inclusion of delay of 1 gate would be illustrated when we design higher counters: And hence operating frequency is Higher

Circuit

It is a phenomenon in which there is a difference between the times at which clock signal reaches different components in synchronous circuits. Or we can say that clock signal from clock circuitry reaches different components in the circuit at different times. e.g. If in the circuit given below, CLK signal reaches the two flip-flops at different times then it is said that CLOCK SKEW exists in the system.

CAUSES: There are basically 2 reasons due to which clock skew exists in the system:

1. Distance: If there is a difference in the distances between the clock circuitry and different components then clock signal has to travel through different length of wires, hence clock signal would reach earlier where there is shorter distance and clock would reach later where there is longer distance. 2. Change in the material of wires: Also if there is a change in the material of wires then clock signal can travel faster in one wire and slower in other and hence there would be change at the time at which clock signal reaches different components.
Effects of clock skew:

Disadvantage: If combinational logic delay is very short or clock skew is large enough then output of 1st FF would change (hence input of 2nd FF is changed overriding the previous input) before HOLD time condition for the input of 2nd FF is satisfied and hence circuit would not work properly due to this HOLD TIME violation. Or input of 2nd FF change to create SETUP time violations. Advantage: We can see in the example given below that due to clock skew, minimum clock period of the clock is decreased (and hence frequency is increased).

Q- Find the maximum clock frequency of the above circuit if specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns. There is a clock skew of +3ns for 2nd FF in the above circuit.
Ans: We firstly represent the delays wrt edge of 1st FF as

And the delayed input must reach before the edge reaches 2nd flip-flop

The clock skew is basically the delay in clock signal reaching 2nd flip-flop. Hence this is quiet similar to the previous question of a buffer in the pathway of clock. Hence Clock time period is T = T CLK to Q + cdelay + Setup time Clock Skew = 9 + 13 + 5 3 = 24 ns And maximum frequency of the circuit is F max = 1 / 24 = 4.16 MHz

QUESTIONS
Q- Find the maximum clock frequency of the following circuit if specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit. Also there is problem of clock skew in the system. We also have to identify the pair of registers between which we need to know the value of clock skew.

Assume value of clock skew between required pair of registers. Ans: This question is very similar to the question done earlier as we have to fulfill the same conditions at clock edges. Its only the clock skew which is going to affect the value of maximum frequency. We represent everything as:

If now we calculate the minimum time period required considering condition at all FF as follow, well find: FF1 FF2 Tmin = setup FF1 = 5 ns Tmin = T1 CLK to Q + cdelay1 + setup FF2 clock skew (b/w FF1 & FF2) = 9 + 13 + 4 clock skew (b/w FF1 & FF2) = 26 3 = 23 ns FF3 Tmin = T2 CLK to Q + cdelay2 + setup FF3 clock skew (b/w FF3 & FF2) = 7 + 16 + 4 3 = 24 ns Note: We can easily notice that we need the value of clock skew between only adjacent pair of Flip-flops. We have assumed the value of skew as 3 ns between the pairs. And the minimum time period to satisfy every condition at every clock edge is 24 ns Hence maximum clock frequency of the circuit is Fmax = 1/24 = 4.16 MHz IMPORTANT: Clock skew is only meaningful between adjacent pair of flip-flops while its meaningless to know about the cock skew between other pair of flipflops. Hence in the above case we only need to know the value of clock skew between FF1 & FF2 and FF2 & FF3 while skew between FF1 & FF3 is meaningless.

Q-Implement binary multiplication using shifter:

Eg. If we are multiply 11 * 4 Then 11 = 1011 4 = 0100

Algorithm: For multiplication we first multiply the LSB of 4 (multiplier) with multiplicand and then shift it towards right. Then we multiply the next bit and then add it to the shifted result. Again we MULTIPLY, ADD & Shift or if bit of multiplier is 1 then ADD multiplicand and SHIFT and if bit of multiplier is 0 then ADD zero (or dont perform ADD but just) SHIFT. We store multiplier in register Q & multiplicand in A and use adder as:

Now Ill show the contents of shifter at every clock tick if we have to find A* B = 1011 * 0100 Clock tick contents of register 0000 0100 Function Initial data is

1st tick 0 stored in register from inputs

2nd tick stored 2nd tick towards right 3rd tick stored 3rd tick 4th tick adder is stored 4th tick 5th tick stored 5th tick shifted

0000

0100

Result of adder is

0000

0010

it is shifted

0000

0010

Result of adder is

0 0

0000 1011

0001 0001

shifted right again firstly result of

0 0

0101 0101

1000 1000

now right shifted Result of adder is

0010

1100

Again right

And we get the answer as 001011002

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and delay of other components is T (buf) = 2ns, T (AND) = 4 ns, T (OR) = 4 ns, T (NOT) = 2 ns in the following circuit.

Ans: We first need to calculate the maximum delay of combinational circuit so that proper input reaches the inputs of 2nd FF. Delay of one path in combinational circuit is T (OR) + T (NOT) = 4 + 2 = 6 ns Delay of other path in combinational circuit is T (NOT) + T (NOT) = 4 ns We take maximum of those hence 6 ns. Hence Clock time period T =T CLK to Q + cdelay + Setup time clock delay for 2nd FF = 9 + 6 + 52 = 18ns Maximum Clock frequency = F max = 1/18 = 5.55 MHz

Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit. And delay of buffer is T (buf) = 2 ns.

Ans: This question is very similar to the question done earlier as we have to fulfill the same conditions at clock edges its only the delay which has been introduced in the path way of clock signal. We represent everything as:

If now we calculate the minimum time period required considering condition at all FF as follow, well find: FF1 Tmin = setup FF1 = 5 ns

FF2 Tmin = T1 CLK to Q + cdelay1 + setup FF2 clock delay= 9 + 13 + 4 2 =24 ns FF3 Tmin = T2 CLK to Q + cdelay2 + setup FF3 clock delay= 7 + 16 + 4 2 =25 ns As for FF3 we are calculating delays wrt the previous clock edge of FF2 for different conditions and there is delay of only 2 ns in clock wrt clock at FF2 hence

only 2 ns is subtracted which can also be seen from the diagram. Note: One can say that there is a total delay of 4 ns for clock of FF3 and hence 4 should be subtracted but as we are calculating all delays wrt the clock edge of FF2 and the delay between clocks of FF2 & FF3 is only 2 ns (not 4 ns). Hence 2 is subtracted. And the minimum time period to satisfy every condition at every clock edge is 25 ns Hence maximum clock frequency of the circuit is Fmax = 1/25 = 4 MHz

- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns and delay of buffer is T (buf) = 2ns. Delay of OR & inverter is 3 ns & 2 ns respectively.

Ans: The combinational circuit after the 2nd FF doesnt affect the clock frequency of the circuit as there is no gated component after that circuit. Hence we represent the delays wrt edge of 1st FF as

And the delayed input must reach before the edge reaches 2nd flip-flop

And we know that for 1st FF clock edge can reach anytime as there is direct input available. Hence we get that Clock time period is T = T CLK to Q + cdelay + Setup time clock delay for 2nd FF = 9 + 13 + 5 2 = 25 ns And maximum frequency of the circuit is F max = 1 / 25 = 4.0 MHz

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 8ns T (CLK to Q) = 2ns and delay of other components is T (buf) = 2ns, T (AND) = 4 ns, T (OR) = 4 ns, T (NOT) = 2 ns in the following circuit.(b) Also tell us if there is HOLD time violation at any of the flip-flops.

Ans: We first need to calculate the maximum delay of combinational circuit so that proper input reaches the inputs of 2nd FF. Delay of one path in combinational circuit is T (OR) + T (NOT) = 4 + 2 = 6 ns Delay of other path in combinational circuit is T (NOT) + T (NOT) = 4 ns We take maximum of those hence 6 ns. Hence Clock time period T =T CLK to Q + cdelay + Setup time clock delay for 2ndFF = 2 + 6 + 52 = 11ns Maximum Clock frequency = F max = 1/11 = 9.99 MHz (b) HOLD TIME: At 1st FF K input & one input of AND gate for J input is given externally which is supposed to be held stable for hold time but the other input is a feedback from 2nd FF and this input changes only after minimum delay of T = T1 CLK to Q + cdelay + Setup time2 + T2 CLK to Q + delay of AND gate = 2 + 5 + 6 + 2 + 4 = 19 ns which is greater than Hold time of 1st FF. hence hold time condition is satisfied for 1st FF.

At 2nd FF K input changes after minimum delay of T = T2 CLK to Q+ delay of AND gate + Setup time1 + T1 CLK to Q + delay (inverter) + delay (inverter) = 2 + 4 + 5 + 2 + 2 + 2 = 17 ns i.e. more than Hold time one J input (o/p of 1st FF) changes after minimum delay of T = T2 CLK to Q+ delay of AND gate + Setup time1 + T1 CLK to Q + delay (inverter) + delay (OR) = 2 + 4 + 5 + 2 + 2 + 4 = 19 ns i.e. more than Hold time While other input to J through OR gate is a feed back from o/p of 2nd FF and changes only after time T = T2 CLK to Q + delay of AND gate = 6 ns which is less than hold time (=8ns).

Hence there is a Hold time violation. To correct this we include a buffer gate of 2 ns delay in the feedback as shown: with this buffer now i/p changes after 8 ns which is equal to hold time. Hence condition satisfied.

Hence we can also note that HOLD time doesnt depend upon the clock frequency while SETUP time violation depends upon the clock frequency.

Q-Implement a MOD-8 counter using Parallel-in Parallel-out register and Adder.

Ans: We have a 3-bit register with two common inputs CLK & CLEAR for all 3 FFs. So we initiate the counter we clear all the FFs and then give clock. Whenever count reaches 7 output of adder becomes 000 with carry 1 and carry is ignored and 000 is fed into register. We have the circuit as:

In the circuit block of 3 FFs is a register with 2 common inputs.