Ripple Counter

A counter is basically used to count the number of clock pulses applied to a flip-flop. It can also be used
for Frequency divider, time measurement, frequency measurement, distance measurement and also for
generating square waveforms. In this, the flip-flops are asynchronous counters and are supplied with
different clock signals, there may be a delay in producing output.

Also, a few numbers of logic gates are needed to design asynchronous counters. So they are elementary
in design and also are less expensive.

Ripple counter –
A n-bit ripple counter can count up to 2n states. It is also known as MOD n counter. It is known as ripple
counter because of the way the clock pulse ripples its way through the flip-flops. Some of the features of
ripple counter are:

1. It is an asynchronous counter.
2. Different flip-flops are used with a different clock pulse.
3. All the flip-flops are used in toggle mode.
4. Only one flip-flop is applied with an external clock pulse and another flip-flop clock is obtained
from the output of the previous flip-flop.
5. The flip-flop applied with external clock pulse act as LSB (Least Significant Bit) in the counting
sequence.

A counter may be an up counter that counts upwards or can be a down counter that counts downwards
or can do both i.e.count up as well as count downwards depending on the input control. The sequence
of counting usually gets repeated after a limit. When counting up, for n-bit counter the count sequence
goes from 000, 001, 010, … 110, 111, 000, 001, … etc. When counting down the count sequence goes in
the opposite manner: 111, 110, … 010, 001, 000, 111, 110, … etc.

A 3-bit Ripple counter using JK flip-flop –

In the circuit shown in above figure, Q0(LSB) will toggle for every clock pulse because JK flip-flop works
in toggle mode when both J and K are applied 1, 1 or high input. The following counter will toggle when
the previous one changes from 1 to 0

Truth Table –
The 3-bit ripple counter used in the circuit above has eight different states, each one of which
represents a count value. Similarly, a counter having n flip-flops can have a maximum of 2 to the power
n states. The number of states that a counter owns is known as its mod (modulo) number. Hence a 3-bit
counter is a mod-8 counter.

A mod-n counter may also be described as a divide-by-n counter. This is because the most significant
flip-flop (the furthest flip-flop from the original clock pulse) produces one pulse for every n pulses at the
clock input of the least significant flip-flop (the one triggers by the clock pulse). Thus, the above counter
is an example of a divide-by-4 counter.

Timing diagram – Let us assume that the clock is negative edge triggered so above counter will act as an
up counter because the clock is negative edge triggered and output is taken from Q.

Counters are used very frequently to divide clock frequencies and their uses mainly involve in digital
clocks and in multiplexing. The widely known example of the counter is parallel to serial data conversion
logic.

Modulus Counters / MOD counter

Modulus Counters, or simply MOD counters, are defined based on the number of states that the counter
will sequence through before returning back to its original value. For example, a 2-bit counter that
counts from 00 to 11 in binary, that is 0 to 3 in decimal, has a modulus value of 4 ( 00 → 1 → 10 → 11,
and return back to 00 ) so would therefore be called a modulo-4, or mod-4, counter. Note also that it
has taken four clock pulses to get from 00 to 11.

As in this simple example there are only two bits, ( n = 2 ) then the maximum number of possible output
states (maximum modulus) for the counter is: 2n = 22 or 4. However, counters can be designed to count
to any number of 2n states in their sequence by cascading together multiple counting stages to produce
a single modulus or MOD-N counter.

Therefore, a “Mod-N” counter will require “N” number of flip-flops connected together to count a single
data bit while providing 2n different output states, (n is the number of bits). Note that N is always a
whole integer value.

Modulus 10 Counter
We have seen in this tutorial about MOD Counters that binary counters are sequential circuits that
generate binary sequences of bits as a result of a clock signal and the state of a binary counter is
determined by the specific combination formed by all the counters outputs together.

The number of different output states a counter can produce is called the modulo or modulus of the
counter. The Modulus (or MOD-number) of a counter is the total number of unique states it passes
through in one complete counting cycle with a mod-n counter being described also as a divide-by-n
counter.

Synchronous Counter

In the previous Asynchronous binary counter tutorial, we saw that the output of one counter stage is
connected directly to the clock input of the next counter stage and so on along the chain.

The result of this is that the Asynchronous counter suffers from what is known as “Propagation Delay” in
which the timing signal is delayed a fraction through each flip-flop.

However, with the Synchronous Counter, the external clock signal is connected to the clock input of
EVERY individual flip-flop within the counter so that all of the flip-flops are clocked together
simultaneously (in parallel) at the same time giving a fixed time relationship. In other words, changes in
the output occur in “synchronisation” with the clock signal.

The result of this synchronisation is that all the individual output bits changing state at exactly the same
time in response to the common clock signal with no ripple effect and therefore, no propagation delay.

Binary 4-bit Synchronous Counter

It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to each of the
J-K flip-flops in the counter chain and that both the J and K inputs are all tied together in toggle mode,
but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic “1” allowing the flip-flop
to toggle on every clock pulse. Then the synchronous counter follows a predetermined sequence of
states in response to the common clock signal, advancing one state for each pulse.

The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA, but the J and
K inputs of flip-flops FFC and FFD are driven from separate AND gates which are also supplied with
signals from the input and output of the previous stage. These additional AND gates generate the
required logic for the JK inputs of the next stage.
If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are
“HIGH” we can obtain the same counting sequence as with the asynchronous circuit but without the
ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time.

Then as there is no inherent propagation delay in synchronous counters, because all the counter stages
are triggered in parallel at the same time, the maximum operating frequency of this type of frequency
counter is much higher than that for a similar asynchronous counter circuit.

4-bit Synchronous Counter Waveform Timing Diagram

Because this 4-bit synchronous counter counts sequentially on every clock pulse the resulting outputs
count upwards from 0 ( 0000 ) to 15 ( 1111 ). Therefore, this type of counter is also known as a 4-bit
Synchronous Up Counter.

However, we can easily construct a 4-bit Synchronous Down Counter by connecting the AND gates to
the Q output of the flip-flops as shown to produce a waveform timing diagram the reverse of the above.
Here the counter starts with all of its outputs HIGH ( 1111 ) and it counts down on the application of
each clock pulse to zero, ( 0000 ) before repeating again.