Instrucciones Del Pic16f84
Instrucciones Del Pic16f84
Instrucciones Del Pic16f84
TABLE 9-2
Mnemonic, Operands
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
C C C,DC,Z Z
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
DS30430C-page 56
PIC16F8X
9.1
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Descriptions
Add Literal and W [label] ADDLW 0 k 255 (W) + k (W) C, DC, Z
11 111x kkkk kkkk The contents of the W register are added to the eight bit literal k and the result is placed in the W register.
AND Literal with W [label] ANDLW 0 k 255 (W) .AND. (k) (W) Z
11 1001 kkkk kkkk The contents of W register are ANDed with the eight bit literal 'k'. The result is placed in the W register.
1 1 Q1
Decode
Words: Cycles: Q2
Read literal k
1 1 Q1
Decode
Q3
Process data
Q4
Write to W
Q Cycle Activity:
Q2
Read literal "k"
Q3
Process data
Q4
Write to W
Example:
ADDLW
Example
ANDLW W W
Add W and f [label] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z
00 0111 dfff ffff Add the contents of the W register with register f. If d is 0 the result is stored in the W register. If d is 1 the result is stored back in register f.
AND W with f [label] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z
00 0101 dfff ffff AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
1 1 Q1
Decode
Words: Cycles: Q2
Read register f
1 1 Q1
Decode
Q3
Process data
Q4
Write to destination
Q Cycle Activity:
Q2
Read register f
Q3
Process data
Q4
Write to destination
Example
ADDWF
Example
ANDWF
Before Instruction
Before Instruction
After Instruction
W = FSR =
After Instruction
W = FSR =
DS30430C-page 57
PIC16F8X
BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: 1 1 Q1
Decode
Bit Test, Skip if Clear [label] BTFSC f,b 0 f 127 0b7 skip if (f<b>) = 0 None
01 10bb bfff ffff If bit b in register f is 1 then the next instruction is executed. If bit b, in register f, is 0 then the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction.
Q2
Read register f
Q3
Process data
Q4
Write register f
1 1(2) Q1
Decode
Example
BCF
Q2
Read register f
Q3
Process data
Q4
No-Operat ion
If Skip:
(2nd Cycle) Q1 Q2
No-Operat ion
Q3
Q4
Example
BTFSC GOTO PC =
FLAG,1 PROCESS_CODE
Before Instruction
address HERE
After Instruction BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: 1 1 Q1
Decode
f,b
Q2
Read register f
Q3
Process data
Q4
Write register f
Example
BSF
FLAG_REG,
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS30430C-page 58
PIC16F8X
BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, Skip if Set [label] BTFSS f,b 0 f 127 0b<7 skip if (f<b>) = 1 None
01 11bb bfff ffff
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None
10 0kkk kkkk kkkk Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two cycle instruction.
If bit b in register f is 0 then the next instruction is executed. If bit b is 1, then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction.
1 1(2) Q1
Decode
Words: Q2
Read register f
1 2 Q1
Decode
Q3
Process data
Q4
No-Operat ion
Q2
Read literal k, Push PC to Stack
Q3
Process data
Q4
Write to PC
If Skip:
(2nd Cycle) Q1 Q2
Q3
Q4 2nd Cycle
No-Opera tion
Example
BTFSC GOTO PC =
FLAG,1 PROCESS_CODE
Example
HERE
CALL
THERE
Before Instruction
PC = Address HERE
After Instruction
address HERE PC = Address THERE TOS = Address HERE+1
DS30430C-page 59
PIC16F8X
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Clear f [label] CLRF 0 f 127 00h (f) 1Z Z
00 0001 1fff ffff The contents of register f are cleared and the Z bit is set.
CLRW f Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles:
1 1 Q1
Decode
1 1 Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Write register f
Q Cycle Activity:
Q2
No-Opera tion
Q3
Process data
Q4
Write to W
Example
CLRF
Example
CLRW
Before Instruction
W W Z = = = 0x5A 0x00 1
After Instruction
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD
00 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
1 1 Q1
Decode
Q2
No-Opera tion
Q3
Process data
Q4
Clear WDT Counter
Example
CLRWDT
Before Instruction
WDT counter = ? 0x00 0 1 1
After Instruction
WDT counter = WDT prescaler= TO = PD =
DS30430C-page 60
PIC16F8X
COMF Syntax: Operands: Operation: Status Affected: Encoding: Description: Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z
00 1001 dfff ffff
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None
00 1011 dfff ffff
The contents of register f are decremented. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f. If the result is 1, the next instruction, is executed. If the result is 0, then a NOP is executed instead making it a 2TCY instruction.
The contents of register f are complemented. If d is 0 the result is stored in W. If d is 1 the result is stored back in register f.
1 1 Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Write to destination
1 1(2) Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Write to destination
Example
COMF
If Skip:
(2nd Cycle) Q1 Q2
Q3
Q4
DECF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity:
Example
HERE
CNT, 1 LOOP
Before Instruction
PC =
After Instruction
CNT if CNT PC if CNT PC = = = =
1 1 Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Write to destination
Example
DECF
Before Instruction
After Instruction
CNT Z
DS30430C-page 61
PIC16F8X
GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None
10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction.
1 2 Q1
Decode
Words: Cycles: Q2
Read literal k
1 1 Q1
Decode
Q3
Process data
Q4
Write to PC
Q Cycle Activity:
Q2
Read register f
Q3
Process data
Q4
Write to destination
No-Operat ion
Example
INCF
After Instruction
PC = Address THERE
After Instruction
CNT Z
DS30430C-page 62
PIC16F8X
INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None
00 1111 dfff ffff The contents of register f are incremented. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead making it a 2TCY instruction.
1 1 Q1
Decode
Q2
Read literal k
Q3
Process data
Q4
Write to W
1 1(2) Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Write to destination
Example
IORLW W W Z
If Skip:
(2nd Cycle) Q1 Q2
Q3
Q4
Example
HERE
CNT, 1 LOOP
Before Instruction
PC = address HERE CNT + 1 0, address CONTINUE 0, address HERE +1
After Instruction
CNT = if CNT= PC = if CNT PC =
DS30430C-page 63
PIC16F8X
IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z
00 0100 dfff ffff Inclusive OR the W register with register f. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f.
MOVLW k
0 k 255
1 1 Q1
Decode
1 1 Q1
Decode
Q2
Read literal k
Q3
Process data
Q4
Write to W
Q2
Read register f
Q3
Process data
Q4
Write to destination
Example
RESULT, 0
MOVLW W
0x5A = 0x5A
Example
IORWF
After Instruction
Before Instruction
RESULT = W = 0x13 0x91 0x13 0x93 1
After Instruction
RESULT = W = Z =
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity:
MOVWF
0 f 127
1 1 Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Write register f
1 1 Q1
Decode
Q2
Read register f
Q3
Process data
Q4
Write to destination
Example
MOVWF
Before Instruction
After Instruction
OPTION = W =
DS30430C-page 64
PIC16F8X
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: 1 1 Q1
Decode
NOP
RETFIE
No operation.
Q2
Q3
Q4 Words:
1 2 Q1
Decode
Example
NOP
Q2
No-Opera tion
Q3
Set the GIE bit
Q4
Pop from the Stack
No-Operat ion
Example
RETFIE
After Interrupt
PC = GIE = TOS 1
OPTION
1 1
To maintain upward compatibility with future PIC16CXX products, do not use this instruction.
DS30430C-page 65
PIC16F8X
RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None
11 01xx kkkk kkkk The W register is loaded with the eight bit literal k. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
RETURN
1 2 Q1
Decode
1 2 Q1
Decode
Q2
Q3
Q4
Q2
Read literal k
Q3
No-Opera tion
Q4
Write to W, Pop from the Stack
No-Opera No-Opera Pop from tion tion the Stack No-Opera No-Opera No-Opera tion tion tion
No-Operat ion
2nd Cycle
No-Operat ion
Example
RETURN
After Interrupt
PC = TOS
;W contains table ;offset value ;W now has table value
Example
CALL TABLE
TABLE ADDWF PC RETLW k1 RETLW k2
RETLW kn ; End of table
Before Instruction
W W = = 0x07 value of k8
After Instruction
DS30430C-page 66
PIC16F8X
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C
00 1101 dfff ffff The contents of register f are rotated one bit to the left through the Carry Flag. If d is 0 the result is placed in the W register. If d is 1 the result is stored back in register f. C Register f
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff The contents of register f are rotated one bit to the right through the Carry Flag. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f. C Register f
RLF
f,d
1 1 Q1
Decode
Words: Cycles: Q2
Read register f
1 1 Q1
Decode
Q3
Process data
Q4
Write to destination
Q Cycle Activity:
Q2
Read register f
Q3
Process data
Q4
Write to destination
Example
RLF
REG1,0 REG1 C
Example
1110 0110 0 1110 0110 1100 1100 1
RRF REG1 C
REG1,0
Before Instruction
= = = = =
Before Instruction
= = = = = 1110 0110 0 1110 0110 0111 0011 0
After Instruction
REG1 W C
After Instruction
REG1 W C
DS30430C-page 67
PIC16F8X
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD
00 0000 0110 0011 The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 14.8 for more details.
Subtract W from Literal [ label ] 0 k 255 k - (W) (W) C, DC, Z 11 110x kkkk kkkk
The W register is subtracted (2s complement method) from the eight bit literal 'k'. The result is placed in the W register.
SUBLW k
1 1 Q1
Decode
Q2
Read literal k
Q3
Process data
Q4
Write to W
1 1 Q1
Decode
Example 1: Q2 Q3 Q4
Go to Sleep
0x02
Example 2:
Before Instruction
W C Z = = = 2 ? ?
After Instruction
W C Z = = = 0 1; result is zero 1
Example 3:
Before Instruction
W C Z = = = 3 ? ?
After Instruction
W C Z = = = 0xFF 0; result is negative 0
DS30430C-page 68
PIC16F8X
SUBWF Syntax: Operands: Operation: Encoding: Description: Subtract W from f [ label ] 0 f 127 d [0,1] (f) - (W) (destination) 00 0010 dfff ffff SUBWF f,d SWAPF Syntax: Operands: Operation: Status Affected: Encoding: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None
00
1110
dfff
ffff
1 1 Q1
Decode
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.
Words: Q2
Read register f
1 1 Q1
Decode
Q3
Process data
Q4
Write to destination
Q2
Read register f
Q3
Process data
Q4
Write to destination
Example 1:
REG1,1 Example
3 2 ? ? SWAPF REG, 0
Before Instruction
REG1 = 0xA5
After Instruction
REG1 W = = 0xA5 0x5A
After Instruction
REG1 W C Z = = = = 1 2 1; result is positive 0
Example 2:
Before Instruction
REG1 W C Z = = = = 2 2 ? ?
TRIS
After Instruction
REG1 W C Z = = = = 0 2 1; result is zero 1
Example 3:
Before Instruction
REG1 W C Z = = = = 1 2 ? ?
1 1
To maintain upward compatibility with future PIC16CXX products, do not use this instruction.
After Instruction
REG1 W C Z = = = = 0xFF 2 0; result is negative 0
DS30430C-page 69
PIC16F8X
XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR Literal with W [label] XORLW k 0 k 255 (W) .XOR. k (W) Z 11 1010 kkkk kkkk
The contents of the W register are XORed with the eight bit literal 'k'. The result is placed in the W register.
Exclusive OR W with f [label] XORWF f,d 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z
00 0110 dfff ffff Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
1 1 Q1
Decode
Words: Q2
Read literal k
1 1 Q1
Decode
Q3
Process data
Q4
Write to W
Q2
Read register f
Q3
Process data
Q4
Write to destination
Example:
0xAF Example
0xB5
XORWF
REG
Before Instruction
REG W = = 0xAF 0xB5
After Instruction
W = 0x1A
After Instruction
REG W = = 0x1A 0xB5
DS30430C-page 70