Instruction Format (1 of 3)

o  The PIC18F instruction format divided into

four groups
n  Byte-Oriented operations
n  Bit-Oriented operations
n  Literal operations
n  Branch operations
PIC18 Instruction Set Overview –

Byte Oriented Operations

15 9 8 7 0

Opcode a f f f f f f f f
OR
Opcode d a f f f f f f f f
File Register Address
Destination( W or F) Access Bank
Or BSF

ADDWF 0x 25 ,W ,A
File Register Address Use Access Bank
Destination ( Optional)
Instruction Set Overview
Bit Oriented Operations

15 11 9 8 7 0

Opcode b b b a f f f f f f f f
File Register Address

Bit Position (0-7)

BSF 0x25, 3, A
File Register Address Access Bank
Bit Position (Optional)
Instruction Set Overview
Literal and Control Operations
15 8 7 Literal Value 0

Opcode k k k k k k k k
OR
Opcode

MOVLW 0 x25
Literal Value
Instruction Set Overview
- Two-word instruction
Byte to Byte Move Operations( 2Words)
15 12 11 Source Register Address 0

Opcode fs fs fs fs fs fs fs fs fs fs fs fs
Opcode fd fd fd fd fd fd fd fd fd fd fd fd
Destination Register Address

MOVFF 0x125 ,0 x140

Source Address Destination Address
Instruction Set Overview
Call and Goto Operations( 2 Words)
15 11 8 7 0

Opcode n8 n7 n6 n5 n4 n3 n2 n1

Opcode n20 n19 n18 n17 n16 n15 n14 n13 n12 n11 n10 n9

CALL 0x 1125
Subroutine Address
 Machine Control Instructions
o  CLRWDT ;Clear Watchdog Timer
n  Helps recover from software malfunction
n  Uses its own free-running on-chip RC oscillator
n  WDT is cleared by CLRWDT instruction

o  RESET ;Reset all registers and flags

n  When voltage < a particular threshold, the device is held in reset
n  Prevents erratic or unexpected operation
o  SLEEP ;Go into standby mode
o  NOP ;No operation
 Sleep Mode
o  The processor can be put into a power-down mode by executing the SLEEP instruction
n  System oscillator is stopped
n  Processor status is maintained (static design)
n  Watchdog timer continues to run, if enabled
n  Minimal supply current is drawn - mostly due to leakage (0.1 - 2.0µA typical)

Events that wake processor from sleep

MCLR Master Clear Pin Asserted (pulled low)
WDT Watchdog Timer Timeout
INT INT Pin Interrupt
TMR1 Timer 1 Interrupt (or also TMR3 on PIC18)
ADC A/D Conversion Complete Interrupt
CMP Comparator Output Change Interrupt
CCP Input Capture Event
PORTB PORTB Interrupt on Change
SSP Synchronous Serial Port (I2C Mode) Start / Stop Bit Detect Interrupt
PSP Parallel Slave Port Read or Write
 PIC18 Instruction Set Overview –
operation types: Byte-oriented, bit-oriented, literal, program redirection

Byte Oriented Operations negf f,a Negate f

addwf f,d,a Add WREG and f rlcf f,d,a Rotate Left f through Carry
addwfc f,d,a Add WREG and Carry bit to f rlncf f,d,a Rotate Left f (No Carry)
andwf f,d,a AND WREG with f rrcf f,d,a Rotate Right f through Carry
clrf f,a Clear f rrncf f,d,a Rotate Right f (No Carry)
comf f,d,a Complement f setf f,a Set f
cpfseq f,a Compare f with WREG, skip = subfwb f,d,a Subtract f from WREG with borrow
cpfsgt f,a Compare f with WREG, skip > subwf f,d,a Subtract WREG from f
cpfslt f,a Compare f with WREG, skip < subwfb f,d,a Subtract WREG from f with borrow
decf f,d,a Decrement f swapf f,d,a Swap nibbles in f
decfsz f,d,a Decrement f, Skip if 0 tstfsz f,a Test f, skip if 0
dcfsnz f,d,a Decrement f, Skip if Not 0 xorwf f,d,a Exclusive OR WREG with f
incf f,d,a Increment f
incfsz f,d,a Increment f, Skip if 0
infsnz f,d,a Increment f, Skip if Not 0 Bit Oriented Operations
iorwf f,d,a Inclusive OR WREG with f bcf f,b,a Bit Clear f
movf f,d,a Move f bsf f,b,a Bit Set f
movff fs,fd Move fs (src) to fd (dst) btfsc f,b,a Bit Test f, Skip if Clear
movwf f,a Move WREG to f btfss f,b,a Bit Test f, Skip if Set
mulwf f,a Multiply WREG with f btg f,b,a Bit Toggle f
 PIC18 Instruction Set Overview
Control Operations Literal Operations
bc n Branch if Carry addlw k Add literal and WREG
bn n Branch if Negative andlw k AND literal with WREG
bnc n Branch if Not Carry iorlw k Inclusive OR literal with WREG
bnn n Branch if Not Negative lfsr f,k Move 12-bit literal to FSR
bnov n Branch if Not Overflow movlb k Move literal to BSR<3:0>
bnz n Branch if Not Zero movlw k Move literal to WREG
bov n Branch if Overflow mullw k Multiply literal with WREG
bra n Branch Always retlw k Return with literal in WREG
bz n Branch if Zero sublw k Subtract WREG from literal
call n,s Call subroutine xorlw k Exclusive OR literal with WREG
clrwdt Clear Watchdog Timer
daw Decimal Adjust WREG
goto n Go to address Data Memory ó Program Memory Operations
nop No Operation tblrd* Table Read
pop Pop top of return stack (TOS) tblrd*+ Table Read with post-increment
push Push top of return stack (TOS) tblrd*- Table Read with post-decrement
rcall n Relative Call tblrd+* Table Read with pre-increment
reset Software device RESET tblwt* Table Write
retfie s Return from interrupt tblwt*+ Table Write with post-increment
return s Return from subroutine tblwt*- Table Write with post-decrement
sleep Go into standby mode tblwt+* Table Write with pre-increment
From: https://en.wikipedia.org/wiki/PIC_instruction_listings#PIC18_high_end_core_devices_(16_bit)

The PIC18 has a 12-bit RAM address space, divided into 16 pages of 256 bytes. The 8-bit f field determines the address in combination with the a bit
and the 4-bit bank select register (BSR). If a=0, the BSR is ignored and the f field is sign-extended to the range 0x000–0x07F (global RAM) or
0xF80–0xFFF (special function registers). If a=1, the f field is extended with the BSR to generate the 12-bit address.

The PIC18 extends the FSR/INDF mechanism used in previous PICmicro processors for indirect addressing in two ways. First, it provides three file
select registers. The FSRn registers are 12 bits long (each split into two 8-bit portions FSR0L through FSR2H), and access to the corresponding
INDFn register (INDF0 through INDF2) acts as an alias for the addressed byte.

Second, there are addressing modes. For each of the three, there is not just one INDFn register, but five, and the one used determines the addressing
mode:

 INDFn: Access the byte at location FSRn

 POSTDECn: Access the byte at FSRn, then decrement FSRn
 POSTINCn: Access the byte at FSRn, then increment FSRn
 PREINCn: Increment FSRn, then access the byte at the incremented FSRn
 PLUSWn: Access the byte at FSRn + W (indexed addressing)

There are also instructions to directly load an FSR pair with a 12-bit address, and a MOVFF instruction that moves a byte between two 12-bit addresses.

PIC18 16-bit instruction set[6]

1 1 1 1 1 1 C Z N
Mnemonic Description
5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ? ? ?
0 0 0 0 0 0 0 0 opcode Miscellaneous instructions
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOP No operation
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 SLEEP Go into standby mode
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 CLRWDT Restart watchdog timer
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 PUSH Push PC on top of stack
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 POP Pop (and discard) top of stack
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 DAW C Decimal adjust W
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 TBLRD∗ Table read: TABLAT ← mem[TBLPTR]
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 TBLRD∗+ Table read with postincrement
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 TBLRD∗− Table read with postdecrement
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 TBLRD+∗ Table read with pre-increment
0 0 0 0 0 0 0 0 0 0 0 0 1 1 mod TBLWR Table write, same modes as TBLRD
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 s RETFIE [, FAST] Return from interrupt
0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 s RETURN [, FAST] Return from subroutine
0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 CALLW* Push PC, jump to PCLATU:PCLATH:W
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RESET 0 0 0 Software reset
0 0 0 0 0 0 0 1 —0— k MOVLB Move literal k to bank select register
0 0 0 0 1 opcode literal Literal operations: W ← OP(k,W)
0 0 0 0 1 0 0 0 k SUBLW k W←k−W
0 0 0 0 1 0 0 1 k IORLW k W ← k | W, logical inclusive or
0 0 0 0 1 0 1 0 k XORLW k W ← k ^ W, exclusive or
0 0 0 0 1 0 1 1 k ANDLW k W ← k & W, logical and
0 0 0 0 1 1 0 0 k RETLW k RETURN W ← k
0 0 0 0 1 1 0 1 k MULLW k W←k×W
0 0 0 0 1 1 1 0 k MOVLW k W←k
0 0 0 0 1 1 1 1 k ADDLW k W←k+W
0 opcode d a register ALU operations: dest ← OP(f,W)
0 0 0 0 0 0 1 a f MULWF f,a PRODH:PRODL ← W × f (unsigned)
0 0 0 0 0 1 d a f DECF f,d,a C Z N dest ← f − 1
0 0 0 1 0 0 d a f IORWF f,d,a Z N dest ← f | W, logical inclusive or
0 0 0 1 0 1 d a f ANDWF f,d,a Z N dest ← f & W, logical and
0 0 0 1 1 0 d a f XORWF f,d,a Z N dest ← f ^ W, exclusive or
0 0 0 1 1 1 d a f COMF f,d,a Z N dest ← ~f, bitwise complement
0 0 1 0 0 0 d a f ADDWFC f,d,a C Z N dest ← f + W + C
0 0 1 0 0 1 d a f ADDWF f,d,a C Z N dest ← f + W
0 0 1 0 1 0 d a f INCF f,d,a C Z N dest ← f + 1
0 0 1 0 1 1 d a f DECFSZ f,d,a dest ← f − 1, skip if 0
0 0 1 1 0 0 d a f RRCF f,d,a C Z N dest ← f>>1 | C<<7, rotate right through carry
0 0 1 1 0 1 d a f RLCF f,d,a C Z N dest ← f<<1 | C, rotate left through carry
0 0 1 1 1 0 d a f SWAPF f,d,a dest ← f<<4 | f>>4, swap nibbles
0 0 1 1 1 1 d a f INCFSZ f,d,a dest ← f + 1, skip if 0
0 1 0 0 0 0 d a f RRNCF f,d,a Z N dest ← f>>1 | f<<7, rotate right (no carry)
0 1 0 0 0 1 d a f RLNCF f,d,a Z N dest ← f<<1 | f>>7, rotate left (no carry)
0 1 0 0 1 0 d a f INFSNZ f,d,a dest ← f + 1, skip if not 0
0 1 0 0 1 1 d a f DCFSNZ f,d,a dest ← f − 1, skip if not 0
0 1 0 1 0 0 d a f MOVF f,d,a Z N dest ← f
0 1 0 1 0 1 d a f SUBFWB f,d,a C Z N dest ← W + ~f + C (dest ← W − f − CC)
0 1 0 1 1 0 d a f SUBWFB f,d,a C Z N dest ← f + ~W + C (dest ← f − W − CC)
0 1 0 1 1 1 d a f SUBWF f,d,a C Z N dest ← f − W (dest ← f + ~W + 1)
0 1 1 0 opcode a register ALU operations, do not write to W
0 1 1 0 0 0 0 a f CPFSLT f,a skip if f < W (unsigned)
0 1 1 0 0 0 1 a f CPFSEQ f,a skip if f == W
0 1 1 0 0 1 0 a f CPFSGT f,a skip if f > W (unsigned)
0 1 1 0 0 1 1 a f TSTFSZ f,a skip if f == 0
0 1 1 0 1 0 0 a f SETF f,a f ← 0xFF
0 1 1 0 1 0 1 a f CLRF f,a 1 f ← 0, PSR.Z ← 1
0 1 1 0 1 1 0 a f NEGF f,a C Z N f ← −f
0 1 1 0 1 1 1 a f MOVWF f,a f←W
0 1 1 1 bit a f BTG f,b,a Toggle bit b of f
1 0 opc bit a register Bit operations
1 0 0 0 bit a f BSF f,b,a Set bit b of f
1 0 0 1 bit a f BCF f,b,a Clear bit b of f
1 0 1 0 bit a f BTFSS f,b,a Skip if bit b of f is set
1 0 1 1 bit a f BTFSC f,b,a Skip if bit b of f is clear
1 1 0 opc address Large-address operations
1 1 0 0 source
MOVFF s,d Move absolute
1 1 1 1 destination
1 1 0 1 0 n BRA n Branch to PC + 2n
1 1 0 1 1 n RCALL n Subroutine call to PC + 2n
1 1 1 0 0 cond n Conditional branch (to PC+2n)
1 1 1 0 0 0 0 0 n BZ n Branch if PSR.Z is set
1 1 1 0 0 0 0 1 n BNZ n Branch if PSR.Z is clear
1 1 1 0 0 0 1 0 n BC n Branch if PSR.C is set
1 1 1 0 0 0 1 1 n BNC n Branch if PSR.C is clear
1 1 1 0 0 1 0 0 n BOV n Branch if PSR.V is set
1 1 1 0 0 1 0 1 n BNOV n Branch if PSR.V is clear
1 1 1 0 0 1 1 0 n BN n Branch if PSR.N is set
1 1 1 0 0 1 1 1 n BNN n Branch if PSR.N is clear
1 1 1 0 1 0 opc k Extensions for using FSR2 as software stack pointer*
1 1 1 0 1 0 0 0 n k ADDFSR n,k* FSRn += k
1 1 1 0 1 0 0 0 1 1 k ADDULNK k* FSR2 += k, pop PC
1 1 1 0 1 0 0 1 n k SUBFSR n,k* FSRn −= k
1 1 1 0 1 0 0 1 1 1 k ADDULNK k* FSR2 −= k, pop PC
1 1 1 0 1 0 1 0 k PUSHL k* [FSR2] ← k, decrement FSR2
1 1 1 0 1 0 1 1 0 s
MOVSF src,f * f ← FSR2[s]
1 1 1 1 f
1 1 1 0 1 0 1 1 0 s
MOVSD src,dst* FSR2[d] ← FSR2[s]
1 1 1 1 —0— d
1 1 1 0 1 1 opc k 2-word instructions
1 1 1 0 1 1 0 s k (lsbits)
CALL k[, FAST] Call subroutine (20-bit address)
1 1 1 1 k (msbits)
1 1 1 0 1 1 1 0 0 0 f k (msb)
LFSR f,k Move 12-bit literal to FSRf
1 1 1 1 0 0 0 0 k (lsbits)
1 1 1 0 1 1 1 1 k (lsbits)
GOTO k Absolute jump, PC ← k (20-bit address)
1 1 1 1 k (msbits)
1 1 1 1 k No operation, second word of 2-word instructions
1 1 1 1 1 1 C Z N
Mnemonic Description
5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ? ? ?
*: These extended instructions are only available on some models, and then only if the XINST configuration bit is set.