Generating A Schematic Symbol For Orcad Capture: September 2006 Application Note An8075
Generating A Schematic Symbol For Orcad Capture: September 2006 Application Note An8075
Generating A Schematic Symbol For Orcad Capture: September 2006 Application Note An8075
Introduction
OrCAD Capture is a popular schematic design entry tool for system-level PCB design. The primary output of Capture is a netlist report used to import component connectivity into a PCB layout product. Since high-density FPGA packages can provide potentially hundreds of pins, the manual methods to create schematic symbols can be tedious and error-prone. This note describes the recommended procedure to create symbols using the data import/export abilities of ispLEVER and Capture. Note: The procedures of this section are compatible with OrCAD Capture 10.5 and ispLEVER 6.0 or later.
The Design Planner produces a comma-separated-value (CSV) report le of all physical device pins and logic details. An example portion of the Pin Layout CSV File is shown in the listing below. Line numbers 1-25 have been added for clarity.
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Figure 1. Pin Layout CSV Example
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
#Pin Layout Report csv format generated by Preference Editor #Generated at Wed Sep 07 11:50:45 2005 #Design : rd1019.ngd #Package : FPBGA256 Pin Name,Bank,Signal Name,Direction,IO_TYPE,PULLMODE,DRIVE,SLEWRATE,PCICLAMP,OPENDRAIN A1,Bank0,GND,,,,,,, A2,Bank0,hostRQ(14),Output Port,LVTTL33,,,,, A3,Bank0,hostRQ(29),Output Port,LVTTL33,,,,, A4,Bank0,hostRA(8),Input Port,LVTTL33,,,,, A5,Bank0,hostWA(0),Input Port,LVTTL33,,,,, A6,Bank0,hostWA(13),Input Port,LVTTL33,,,,, A7,Bank0,hostWD(1),Input Port,LVTTL33,,,,, A8,Bank0,hostWD(11),Input Port,LVTTL33,,,,, A9,Bank0,hostWD(20),Input Port,LVTTL33,,,,, A10,Bank0,hostWD(29),Input Port,LVTTL33,,,,, A16,Bank0,GND,,,,,,, B2,Bank0,hostRQ(15),Output Port,LVTTL33,,,,, B3,Bank0,hostRQ(30),Output Port,LVTTL33,,,,, B4,Bank0,hostRA(9),Input Port,LVTTL33,,,,, B5,Bank0,hostWA(1),Input Port,LVTTL33,,,,, B6,Bank0,hostWA(14),Input Port,LVTTL33,,,,, B7,Bank0,hostWD(2),Input Port,LVTTL33,,,,, B8,Bank0,hostWD(12),Input Port,LVTTL33,,,,, B9,Bank0,hostWD(21),Input Port,LVTTL33,,,,, B10,Bank0,hostWD(30),Input Port,LVTTL33,,,,,
The Pin Layout CSV File is an export of all physical device pins organized by bank number and pin name. Lines 1-4 of the report are preceded with pound signs (#) and provide a report header with details about the le timestamp, ispLEVER database (NGD or NCD) and device package. Line 5 of the report is the data header for each pin record. Lines 6 and later are the pin records. Depending on what stage you are in in the FPGA design ow you may or may not have assigned logical signal names from your design to specic pin locations. If so, any logical names and related preferences will appear in the report. In the example above, hostRQ(14) and hostRQ(29) (lines 7 and 8) have been assigned to pins A2 and A3 respectively of the 256 fpBGA package. The programmed mode (Output Port) and signal standard (LVTTL33) also appear. You may choose to incorporate these details into your Capture schematic depending on your documentation standards. Reserved special purpose pins like power and no-connects appear in the report and will use the default name in the Signal Name eld. In the example above, A1, Bank0 (line 6) is a ground pin (GND).
Preparing the Pin Layout CSV File for Import into Capture
1. Start Microsoft Excel. The following procedure is best performed in a spreadsheet tool like Microsoft Excel. The steps below use Excel but the technique should be similar in any other spreadsheet that supports CSV import. 2. Choose File > Open. 3. From the Files of type list choose Text Files (*.prn; *.txt; *.csv), select the .csv le you created earlier, and click Open. Excel creates a new spreadsheet and places each pin record eld into a column. 4. Choose File > Save As...
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5. From the Save as type list choose Microsoft Excel Workbook (*.xls), specify a new .xls lename and click Save. 6. Delete the report header in rows 1-4. 7. Modify the column headings to use the following OrCAD Capture naming conventions: a. Replace Pin Name with Number b. Replace Bank with Section c. Replace Signal Name with Name d. Replace Direction with Type 8. Add the following columns: Shape, PinGroup, Position. 9. Organize the columns (A-G) into the following order: Number, Name, Type, Shape, PinGroup, Position, Section. 10.Specify a default pin name for any blank cells of the Name column. A good convention is Unused. 11.Use Edit > Replace to replace the contents of the Type column using the following conventions: a. Replace Input Port with Input b. Replace Input Clock with Input c. Replace Output Port with Output d. Replace Bidir Port with Bidirectional At this point you may wish to apply other pin types that can be applied to a Capture symbol pin: 3STATE OPEN COLLECTOR OPEN EMITTER PASSIVE POWER For example its common for GND and VCC pins to be designated as POWER type and Unused pins to be designated as PASSIVE type. This will inuence the netlist output and design rule checks performed with Capture later. For more information on Capture pin types, see the Capture Knowledge System provided with OrCAD software. 12.Specify one of the following Capture symbol pin shapes for each pin record in the Shape column: CLOCK DOT DOT CLOCK LINE SHORT ZERO LENGTH A good default for most FPGA symbol pins is the LINE shape. 13.Specify one of the following Capture symbol pin positions for each pin record in the Position column: Bottom Left Right Top Choose File > Save.
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6. From Capture, select the New Part Creation Spreadsheet. 7. Select the upper left cell in row 1 and type Ctrl+V to paste the pin records. 8. Click Save. A New Part Creation design rule check runs on the denition and you have to option to view Warnings. You can inspect and modify the spreadsheet to correct any potential problems.
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After you inspect the Warnings, click Save again and then choose Continue to generate the part. A new part appears in the lename.olb list. 9. Double-click the new part. The rst section appears. Use Ctrl+N (Next) or Ctrl+P (Previous) to scroll through the part sections.
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The screen shot below illustrates the Package View of the Library Editor.
Revision History
Date January 2006 September 2006 Version 01.0 01.1 Initial release. Replaced references to Preference Editor with Design Planner. Replaced gure 1 with a new screen shot. Change Summary