HDL LAB Manual - One
HDL LAB Manual - One
HDL LAB Manual - One
By
BALAJI B.S.
Asst. Prof, Dept ECE.
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING,
LIST OF EXPERIMENTS………………..
PROGRAMMING USING VHDL & VERILOG – NON INTERFACING (PART – A)
1. Write HDL code to realize all the logic gates.
2. Write a HDL code for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 Multiplexer
d. 4 bit binary to gray code converter
e. Multiplexer, Demultiplexer, Comparator.
3. Write a HDL code to describe the functions of a Full Adder using three modelling
styles.
4. Write a model for 32 bit ALU using the schematic diagram shown below.
A(31:0) B(31:0)
Opcode(3:0)
Enable
Out(31:0)
ALU should use combinational logic to calculate an output based on the four bit op-
code input.
ALU should pass the result to the out bus when enable line is high, and tri-state the
out bus when the enable line is low.
ALU should decode the 4 bit op-code according to the given in example below.
5. Write the HDL code for the following flip-flops: SR, JK, D, T.
6. Design 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset)
and “any sequence” counters.
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i) 4 bit Synchronous reset Binary counter
ii) 4 bit Asynchronous reset Binary counter
iii) 4 bit Synchronous reset BCD counter
iv) 4 bit Asynchronous reset BCD counter
v) 4 bit binary UP-DOWN Counter.
INTERFACING (PART – B)
1. Write HDL code to display messages on the given seven segment display and LCD
and accepting Hex key pad input data.
2. Write HDL code to control speed, direction of DC and Stepper motor.
3. Write HDL code to accept 8 channel Analog signal, Temperature Sensors and display
the data on LCD panel or Seven segment display.
4. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,)
using DAC change the frequency and amplitude.
5. Write HDL code to simulate Elevator operations.
6. Write HDL code to control external lights using relays.
It is one of most popular software tool used to synthesize VHDL code. This tool includes
many steps. To make user feel comfortable with the tool the steps are given below:-
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Select NEW PROJECT in FILE MENU.
Enter following details as per your convenience
Project name : sample
Project location : C:\Xilinx
Top level module : HDL
Double click on synthesis. If error occurs edit and correct VHDL code.
Double click on Launch ISE simulator (or any equivalent simulator if you are
using) for functional simulation of your design.
Double click on Implement, which will carry out translate, mapping, place
and route of your design. Also generate program file by double clicking on it,
in turn which will create .bit file.
Connect JTAG cable between your kit and parallel port of your computer.
Double click on configure device and select mode in which you want to
configure your device. For ex: select slave serial mode in configuration
window and finish your configuration.
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Right click on device and select ‘program’. (Verify your design giving
appropriate inputs and check for the output.) Click OK and run the program
on the FPGA Kit.
Also verify the actual working of the circuit using pattern generator & logic
analyzer.
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (6 downto 0));
end gates;
begin
y(0)<= a and b;
y(1)<= a or b;
y(2)<= a nand b;
y(3)<= a nor b;
y(4)<= a xor b;
y(5)<= a xnor b;
y(6)<= not a;
end Behavioral;
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (6 downto 0));
end gates;
Simulation Result
Before Execution
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After Execution
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THEORY : A decoder is a multiple input, multiple output logic circuit that converts coded
inputs into coded outputs where the input and output codes are different. The enable inputs
must be ON for the decoder to function, otherwise its outputs assumes a ‘disabled’ output
code word. Decoding is necessary in applications such as data multiplexing, seven segment
display and memory address decoding.
a) 2 to 4 Decoder
Block Diagram
Truth table
inputs outputs
en D_in(1) D_in(0) y3 y2 y1 y0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
0 x x 0 0 0 0
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DECODER 2 to 4 – VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Dec24 is
Port ( I : in STD_LOGIC_VECTOR (1 downto 0);
en : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (3 downto 0));
end Dec24;
DECODER 2 to 4 – VERILOG
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else
begin
case (i)
2'b00 : y = 4'b0001;
2'b01 : y = 4'b0010;
2'b10 : y = 4'b0100;
2'b11 : y = 4'b1000;
default: y = 4'b0000;
endcase
end
end
endmodule
Simulation Result
Before Execution
After Execution
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Block Diagram
Truth Table
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity enc83 is
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
en : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (2 downto 0));
end enc83;
Simulation Result
Before Execution
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After Execution
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Block diagram
Truth table
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity penc8_3 is
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
en : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (2 downto 0));
end penc8_3;
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Simulation Result
Before Execution
After Execution
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c. 8 to 1 Multiplexer
THEORY : Multiplexer is a digital switch.It allows digital information from several sources
to be rooted on to a single output line.The basic multiplexer has several data input lines and a
single output line.The selection of a particular input line is controlled by a set of selection
lines.Normally there are 2N input lines and N selection lines whose bit combinations
determine which input is selected.Therefore multiplexer is many into one and it provides the
digital equivalent of an analog selector switch.
Block Diagram:
Truth table:
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8 to 1 Multiplexer – VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux8_1 is
port ( SEL: in STD_LOGIC_VECTOR(2 downto 0); -- Select Lines
I: in STD_LOGIC_VECTOR(7 downto 0); -- Inputs of the Mux.
Y: out STD_LOGIC ); -- OutPut of the Mux.
end Mux8_1;
begin
process (SEL,I)
begin
case SEL is
when "000" => Y <= I(0);
when "001" => Y <= I(1);
when "010" => Y <= I(2);
when "011" => Y <= I(3);
when "100" => Y <= I(4);
when "101" => Y <= I(5);
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when "110" => Y <= I(6);
when "111" => Y <= I(7);
when others => null;
end case;
end process;
end mux8_1_arch;
8 to 1 Multiplexer – VERILOG
module mux8_1
input [7:0]I;
output [2:0]sel;
output y;
input en;
reg y;
always @(en,sel,I)
begin
if (sel == 0)
y = 1’b0;
else
case (sel)
3’b000: y = I[0];
3’b001: y = I[1];
3’b010: y = I[2];
3’b011: y = I[3];
3’b100: y = I[4];
3’b101: y = I[5];
3’b110: y = I[6];
3’b111: y = I[7];
default: y = 1’b0;
endcase
end
endmodule
Simulation Result
Before Execution
After Execution
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d. 4 to 1 Multiplexer
4 to 1 Multiplexer – VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux4_1 is
port ( SEL: in STD_LOGIC_VECTOR(1 downto 0); -- Select Lines
I: in STD_LOGIC_VECTOR(3 downto 0); -- Inputs of the Mux.
Y: out STD_LOGIC ); -- OutPut of the Mux.
end Mux4_1;
begin
process (SEL,I)
begin
case SEL is
when "00" => Y <= I(0);
when "01" => Y <= I(1);
when "10" => Y <= I(2);
when "11" => Y <= I(3);
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when others => null;
end case;
end process;
end mux4_1_arch;
4 to 1 Multiplexer – VERILOG
module mux4_1
input [3:0]I;
output [1:0]sel;
output y;
input en;
reg y;
always @(en,sel,I,y)
begin
if (sel == 0)
y = 1’b0;
else
case (sel)
2’b00: y = I[0];
2’b01: y = I[1];
2’b10: y = I[2];
2’b11: y = I[3];
default: y = 1’b0;
endcase
end
endmodule
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e. De-Multiplexer ( 1 to 4)
Block Diagram
Truth table
i en Sel1 Sel0 y3 y2 y1 y0
1 1 0 0 0 0 0 1
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1 1 0 1 0 0 1 0
1 1 1 0 0 1 0 0
1 1 1 1 1 0 0 0
0 0 x x 0 0 0 0
1 to 4 Demultiplexer – VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Demux1_4 is
port ( I, en : in STD_LOGIC;
sel: in STD_LOGIC_VECTOR (1 downto 0);
Y: out STD_LOGIC_VECTOR (3 downto 0));
end Demux1_4;
1 to 4 Demultiplexer – VERILOG
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input en, i;
input [1:0]sel;
output [3:0]y;
reg [3:0]y;
always @ (en or sel or i)
begin
if(en= =0)
y = 4’b0000;
else
y = 4’b0000;
case(sel)
2’b00 : y[0] = i;
2’b01 : y[1] = i;
2’b10 : y[2] = i;
2’b11 : y[3] = i;
endcase
end
endmodule
f. N-Bit Comparator
Block diagram
Comparator – VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
Generic (N: integer := 3);
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begin
process(A,B)
begin
if ( A < B ) then
ALB <= '1';
AGB <= '0';
AEB <= '0';
end if;
if ( A > B ) then
AGB <= '1';
ALB <= '0';
AEB <= '0';
end if;
if ( A = B ) then
AEB <= '1';
AGB <= '0';
ALB <= '0';
end if;
end process;
end Comparator_arc;
Comparator – VERILOG
// Comparator Nbit
module comparatorNbit( a, b, agb, alb, aeb);
parameter N = 3;
input [N:0] a, b;
output agb, alb, aeb;
reg agb, alb, aeb;
always@(a, b)
begin
if( a > b)
begin
agb = 1;
alb = 0;
aeb = 0;
end
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else if( a < b)
begin
agb = 0;
alb = 1;
aeb = 0;
end
else if( a == b)
begin
agb = 0;
alb = 0;
aeb = 1;
end
end
endmodule
Block diagram
Logic Diagram
Boolean expression
Truth table:
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En B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
1 0 0 1 0 0 0 1 1
1 0 0 1 1 0 0 1 0
1 0 1 0 0 0 1 1 0
1 0 1 0 1 0 1 1 1
1 0 1 1 0 0 1 0 1
1 0 1 1 1 0 1 0 0
1 1 0 0 0 1 1 0 0
1 1 0 0 1 1 1 0 1
1 1 0 1 0 1 1 1 1
1 1 0 1 1 1 1 1 0
1 1 1 0 0 1 0 1 0
1 1 1 0 1 1 0 1 1
1 1 1 1 0 1 0 0 1
1 1 1 1 1 1 0 0 0
VHDL Dataflow Description
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity B2G is
port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end B2G;
Verilog
module b2g(b,g);
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input [3:0] b;
output [3:0] g;
assign g[3]=b[3];
assign g[2] = (b[3]^b[2]);
assign g[1] = (b[1]^b[2]);
assign g[0] = (b[0]^b[1]);
endmodule
AIM: Write HDL code to describe the functions of a full Adder Using three modeling styles.
Block Diagram
Truth table
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VHDL
-- FullAdder_DF - Data_Flow
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FullAdder_DF is
Port ( a_in, b_in, c_in : in STD_LOGIC;
sum, carry : out STD_LOGIC);
end FullAdder_DF;
Verilog
VHDL
-- Full Adder - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FullAdder_Behav is
Port ( a_in, b_in, c_in : in STD_LOGIC;
end FullAdder_Behav;
begin
process ( a_in, b_in, c_in)
begin
end process;
end Behavioral;
Verilog
//FullAdder - Behavioral Model
module FullAdder_Behav( a_in, b_in, c_in, sum, carry );
input a_in, b_in, c_in;
output sum, carry;
end
else if (( a_in==0 & b_in==0 & c_in == 1) | (a_in==0 & b_in==1 & c_in == 0) | (a_in==1 &
b_in==0 & c_in == 0))
begin
sum = 1;
carry = 0;
end
else if (( a_in==0 & b_in==1 & c_in == 1) | (a_in==1 & b_in==0 & c_in == 1) | (a_in==1 &
b_in==1 & c_in == 0))
begin
sum = 0;
carry = 1;
end
else if(a_in==1 & b_in==1 & c_in == 1)
begin
sum = 1;
carry = 1;
end
end
endmodule
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity halfadder1 is
port ( x,y : in std_logic;
sum,carry : out std_logic);
end halfadder1;
library ieee;
use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity or_gate is
port ( p,q : in std_logic;
r : out std_logic);
end or_gate;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fulladder1 is
port (x, y, cin : in std_logic;
sum, cout : out std_logic);
end fulladder1;
component or_gate
port (p, q : in std_logic;
r : out std_logic);
end component;
begin
L1: halfadder1 port map (x, y, temp1, temp2);
L2: halfadder1 port map (temp1, cin, sum, temp3);
L3: or_gate port map (temp2, temp3, cout) ;
end structural;
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output carry, sum;
ha ha1 (y, cin, s0, c0);
ha ha2 (x, s0, sum, c1);
or ( carry, c0, c1);
endmodule
Simulation Result
Before Execution
After Execution
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AIM: Write a model for 32 bit ALU using the schematic diagram shown below.
Block diagram
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Truth table
8 bit ALU
VHDL
--ALU32bit – Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu32bit is
Port ( en : in BIT;
opc : in STD_LOGIC_VECTOR (3 downto 0);
a_in, b_in : in STD_LOGIC_VECTOR (31 downto 0);
y_op : out STD_LOGIC_VECTOR (31 downto 0));
end alu32bit;
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Verilog
// ALU 32bit
module alu32bit( en, opc, a_in, b_in, y_op );
input en;
input [3:0] opc;
input [31:0] a_in, b_in;
output [31:0] y_op;
wire en;
wire [3:0] opc;
wire [31:0] a_in, b_in;
reg [31:0] y_op;
always @ ( en, opc, a_in, b_in)
if (en == 1) // Active High Enabled
case (opc)
4'b0000 : y_op = a_in + b_in;
4'b0001 : y_op = a_in - b_in;
4'b0010 : y_op = ~ a_in;
4'b0011 : y_op = a_in * b_in;
4'b0100 : y_op = a_in & b_in;
4'b0101 : y_op = a_in | b_in;
4'b0110 : y_op = ~ (a_in & b_in);
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4'b0111 : y_op = a_in ^ b_in;
default null;
endcase
else
y_op = 32'bZ;
endmodule
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity ALU is
Port ( A : in std_logic_vector(7 downto 0); -- First Input
B : in std_logic_vector(7 downto 0); -- Second Input
Opcode : in std_logic_vector(2 downto 0); -- Op-code to select the operations
enb : in std_logic; -- Enable Signal
op : out std_logic_vector(7 downto 0)); -- Output of the ALU
end ALU;
architecture Behavioral of ALU is
begin
process(A,B,Opcode,enb)
begin
if enb= '1' then
case Opcode is
when "000" => op<= A+B;
when "001" => op<= A-B;
when "010" => op<= not A;
when "011" => op<= A*B;
when "100" => op<= A and B;
when "101" => op<= A or B;
when "110" => op<= A nand B;
when others => op<= A xor B;
end case;
else
op <= (others =>'Z');
end if;
end process;
end Behavioral;
Verilog
// ALU 8 bit
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module alu8bit( en, opc, a_in, b_in, y_op );
input en;
input [3:0] opc;
input [7:0] a_in, b_in;
output [7:0] y_op;
reg [7:0] y_op;
always @ ( en, opc, a_in, b_in)
if (en == 1) // Active High Enabled
case (opc)
4'b0000 : y_op = a_in + b_in;
4'b0001 : y_op = a_in - b_in;
4'b0010 : y_op = ~ a_in;
4'b0011 : y_op = a_in * b_in;
4'b0100 : y_op = a_in & b_in;
4'b0101 : y_op = a_in | b_in;
4'b0110 : y_op = ~ (a_in & b_in);
4'b0111 : y_op = a_in ^ b_in;
default null;
endcase
else
y_op = 8'bZ;
endmodule
EXPERIMENT 6 FLIPFLOPS
AIM: Develop the HDL code for the following flip-flop: SR, JK, T, D.
THEORY :
SR flip-flop: A SR flip - flop is the simplest possible memory element. The SR flip flop has
two inputs Set and Reset. The SR flip-flop is a basic building block for other flip-flops.
D flip-flop: This is a flip - flop with a delay (D) equal to exactly equal to one cycle of the
clock. The defect with SR FF is the indeterminate output when the data inputs at S and R are
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1. In order to avoid this the input to R is through an inverter from S so that the input to R is
always the complement of S and never same. The S input is redesignated as D.
JK flip-flop: The JK flip flop is called a “universal flip flop” because the other flip flops like
D, SR, T can be derived from it. The “racing or race around condition” takes place in a JK FF
when J=1 and K=1 and clock=1.
T flip-flop: T stands for toggling. It is obtained from JK FF by tying both the inputs J and K.
a. SRFF
BLOCK DIAGRAM
TRUTH TABLE
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SRFF – VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sr_ff is
Port ( s,r,rst,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end sr_ff;
architecture Behavioral of sr_ff is
signal temp : std_logic := '0';
begin
process(clk,rst)
begin
if(rst = '1') then
temp <= '0';
elsif (clk'event and clk = '1') then
if(s = '0' and r ='0') then
temp <= temp;
elsif(s = '0' and r ='1') then
temp <= '0';
elsif(s = '1' and r ='0') then
temp <= '1';
elsif(s = '1' and r ='1') then
temp <= 'X';
end if;
end if;
end process;
q <= temp;
qb <= not temp;
end Behavioral;
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SRFF - VERILOG
b. JK Flipflop
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BLOCK DIAGRAM
Truth table
JKFF – VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jk_ff is
Port ( j,k,rst,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end jk_ff;
architecture Behavioral of jk_ff is
signal temp : std_logic := '0';
begin
process(clk,rst)
begin
if(rst = '1') then
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temp <= '0';
elsif(clk'event and clk = '1') then
if(j = '0' and k ='0') then
temp <= temp;
elsif(j = '0' and k ='1') then
temp <= '0';
elsif(j = '1' and k ='0') then
temp <= '1';
elsif(j = '1' and k ='1') then
temp <= not temp;
end if;
end if;
end process;
q <= temp;
qb <= not temp;
end Behavioral;
JKFF – Verilog
c. D Flipflop
BLOCK DIAGRAM
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Truth table
DFF – VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity d_ff is
Port ( d,clk,rst : in STD_LOGIC;
q,qb : out STD_LOGIC);
end d_ff;
architecture Behavioral of d_ff is
signal temp : std_logic := '0';
begin
process(clk,rst)
begin
if(rst = '1') then
temp <= '0';
elsif(clk'event and clk = '1') then
temp <= d;
end if;
end process;
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q <= temp;
qb <= not temp;
end Behavioral;
DFF – Verilog
d. T Flipflop
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BLOCK DIAGRAM
Truth table
TFF – VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity t_ff is
Port ( t,clk,rst : in STD_LOGIC;
q,qb : out STD_LOGIC);
end t_ff;
architecture Behavioral of t_ff is
signal temp : std_logic := '0';
begin
process(clk,rst)
begin
if(rst = '1') then
temp <= '0';
elsif(clk'event and clk = '1' and t = '1') then
temp <= not temp;
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end if;
end process;
q <= temp;
qb <= not temp;
end Behavioral;
TFF – Verilog
EXPERIMENT 7 COUNTERS
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AIM: Design 4 bit Binary, BCD counter (Synchronous reset and Asynchronous reset and
any sequence counters.
Truth Table
VHDL
-- Binary Synchronous reset 4bit counter
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin_counter_sync_4bit is
Port ( clk,rst : in STD_LOGIC;
bin_out : out STD_LOGIC_VECTOR (3 downto 0));
end bin_counter_sync_4bit;
architecture Behavioral of bin_counter_sync_4bit is
signal temp: std_logic_vector(3 downto 0) := “0000”;
begin
process(clk)
begin
if ( clk'event and clk='1') then
if(rst = '1') then
temp <= "0000";
else
temp <= temp+'1';
end if;
end if;
end process;
bin_out <= temp ;
end Behavioral;
Verilog
// Binary synchronous reset 4bit counter
module bin_sync_4bit ( rst, clk, count);
input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'b0000;
end
always @(posedge clk)
if(rst)
count = 4'b0000;
else
count = count + 4'b0001;
endmodule
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Block Diagram
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin_counter_async_4bit is
Port ( clk,rst : in STD_LOGIC;
bin_out : out STD_LOGIC_VECTOR (3 downto 0));
end bin_counter_async_4bit;
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Verilog
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Block Diagram
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd_counter_sync is
Port ( clk,rst : in STD_LOGIC;
bcd_out : out STD_LOGIC_VECTOR (3 downto 0));
end bcd_counter_sync;
Verilog
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Block Diagram
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd_counter_async is
Port ( clk,rst : in STD_LOGIC;
bcd_out : out STD_LOGIC_VECTOR (3 downto 0));
end bcd_counter_async;
Verilog
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Block Diagram
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin_counter_any_seq is
Port ( clk,rst,load,updown : in STD_LOGIC;
d_in :in STD_LOGIC_VECTOR( 3 downto 0);
bin_out : out STD_LOGIC_VECTOR (3 downto 0));
end bin_counter_any_seq;
architecture Behavioral of bin_counter_any_seq is
signal temp: std_logic_vector(3 downto 0):= "0000";
begin
process(clk, rst)
begin
if(rst = '1') then
temp <= "0000";
elsif(load = '1') then
temp <= d_in;
elsif ( clk'event and clk='1' and load = '0') then
if ( updown = '1') then
temp <= temp+'1';
else
temp <= temp-'1';
end if;
end if;
end process;
bin_out <= temp;
end Behavioral;
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Verilog
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INTERFACING – PART B
Procedure to execute:
Implement design
Connect input port to dip switch and output port to led’s. Vary the inputs and view the
corresponding outputs.
INTERFACING PROGRAMS
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DC MOTOR
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dcmotr is
Port ( dir,clk,rst : in std_logic;
pwm : out std_logic_vector(1 downto 0);
rly : out std_logic;
row : in std_logic_vector(0 to 3));
end dcmotr;
begin
process(clk,div_reg)
begin
if(clk'event and clk='1') then
div_reg<=div_reg+'1';
end if;
end process;
ddclk<=div_reg(12);
tick<= row(0) and row(1) and row(2) and row(3);
process(tick)
begin
if falling_edge(tick) then
case row is
when"1110"=> duty_cycle<=255;
when"1101"=> duty_cycle<=200;
when"1011"=> duty_cycle<=150;
when"0111"=> duty_cycle<=100;
when others => duty_cycle<=100;
end case;
end if;
end process;
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process(ddclk, rst)
begin
if rst='0'then countr<=(others=>'0');
pwm<="01";
elsif(ddclk'event and ddclk='1') then
countr<= countr+1;
if countr>=duty_cycle then
pwm(1)<='0';
else pwm(1)<='1';
end if;
end if;
end process;
rly<='1' when dir='1' else '0';
end Behavioral;
PRODEDURE:1) Make connection between FRC 9 and FPGA board to the dc motor
connector of VTU card 2
2) Make the connection between FRC 7 of FPGA board to the K/B connector of VTU card 2
3) Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTV
card 2.
4) Connect the down loading cable and power supply to FPGA board.
5) Then open xilinx impact s/w, select slave serial mode and select the respective bit file and
click program.
6) Make the reset switch on.
7) Press the Hex keys and analyze speed changes for dc motor.
RESULT: The DC motor runs when reset switch is on and with pressing of different keys
variation of DC motor speed was noticed.
STEPPER MOTOR
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity steppermt is
Port ( clk,dir,rst : in std_logic;
dout : out std_logic_vector(3 downto 0));
end steppermt;
end Behavioral;
PROCEDURE:1) Make connection between FRC 9 and FPGA board to the stepper motor
connector of
VTU card 1
2) Make the connection between FRC 1 of FPGA board to the DIP switch connector of
VTU card 1.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file
and click program.
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4) Make the reset switch on.
5) Visualize the speed variation of stepper motor by changing counter value in the
program.
RESULT: The stepper motor runs with varying speed by changing the counter value
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity extlight is
Port ( cntrl1,cntrl2 : in std_logic;
light : out std_logic);
end extlight;
architecture Behavioral of extlight is
begin
light<= cntrl1 OR cntrl2 ;
end Behavioral;
PROCEDURE:
1.Make the connections b/w FRC9 of fpga board to external light connector of vtu card 2
2.Make connection b/w FRC1 of fpga board to the dip switch connector of vtucard2
3.Connect the Downloading cable and power supply to fpga board.
1. Then open the xilinx impact software select the slave serial mode and select
respective bit file and click program
2. Make the reset switch on and listen to the tick sound.
RESULT: Once the pin p74 (reset) is switched on the tick sound is heard at the external light
junction.
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3. WRITE HDL CODE TO GENERATE DIFFERENT WAVEFORMS
(SAWTOOTH, SINE WAVE, SQUARE, TRIANGLE, RAMP ETC) USING
DAC CHANGE THE FREQUENCY AND AMPLITUDE.
SAWTOOTH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sawtooth is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end sawtooth;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
begin
if rst='1' then cnt<="00000000";
elsif rising_edge(temp(3)) then
cnt<= cnt+1;
end if;
end process;
dac<=cnt;
end Behavioral;
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SQUARE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity squarewg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end squarewg;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process(temp(3))
begin
if rst='1' then cnt<="00000000";
elsif rising_edge (temp(3)) then
if cnt< 255 and en='0' then
cnt<=cnt+1;
en<='0';
dac<="00000000";
elsif cnt=0 then en<='0';
else en<='1';
cnt<=cnt-1;
dac<="11111111";
end if;
end if;
end process;
end Behavioral;
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TRIANGLE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end triangwg;
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RAMP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rampwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end rampwg;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
begin
if rst='1' then cnt<="00000000";
elsif rising_edge(temp(3)) then
cnt<= cnt+15;
end if;
end process;
dac<=cnt;
end Behavioral;
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SINE WAVE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sinewave is
Port ( clk,rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end sinewave;
architecture Behavioral of sinewave is
signal temp: std_logic_vector(3 downto 0);
signal counter: std_logic_vector(0 to 7);
signal en: std_logic;
begin
process(clk) is
begin
if rising_edge (clk) then
temp<= temp+'1';
end if;
end process;
process(temp(3)) is
begin
if rst='1' then counter<="00000000";
elsif rising_edge(temp(3)) then
if counter<255 and en='0' then
counter<= counter+31; en<='0';
elsif counter=0 then en<='0';
else en<='1';
counter<= counter-31;
end if;
end if;
end process;
dac_out<= counter;
end Behavioral;
PROCEDURE:
1) Make connection between FRC 5 and FPGA and DAC connector of VTU card 2.
2) Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTU
card 2.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file and
click program.
4) Make the reset switch on.
RESULT:The waveform obtained Ramp, Saw tooth, Triangular, Sine and Square waves are
as per the graph.
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VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sevkeybrd is
Port ( read : in std_logic_vector(3 downto 0);
clk : in std_logic;
scan : inout std_logic_vector(3 downto 0);
disp_cnt : out std_logic_vector(3 downto 0);
disp1 : out std_logic_vector(6 downto 0));
end sevkeybrd;
PROCEDURE:
1) Make connection between FRC 5 and FPGA board to the seven segment connector of
VTU card 1.
2) Make the connection between FRC 4 to FPGA board to K/B connector of VTU card1.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file
and click program.
4) Make the reset switch on.
5) Change the pressing of Hex Keys to watch the display on LCD’s ranging from 0000 to
FFFF.
RESULT:The values from 0 to F were displayed on all 4 LCD’s with the respective Hex Key
being pressed.
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I/O Pin Assignments
Constraints file
1. External Light Controller
NET "cntrl" LOC="p74"; => FRC1
NET "light" LOC="p7"; => FRC9
2. DC MOTOR
NET "CLK" LOC="p18";
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NET "RESET" LOC="p74";
FRC1
NET "dir" LOC="p75";
NET "pwm<0>" LOC="p5";
NET "pwm<1>" LOC="p141"; FRC9
NET "rly" LOC="p3";
NET "ROW<0>" LOC="p64";
NET "ROW<1>" LOC="p63";
FRC7
NET "ROW<2>" LOC="p60";
NET "ROW<3>" LOC="p58";
3. STEPPER MOTOR
NET "CLK" LOC="p18";
NET "dout<0>" LOC="p7";
NET "dout<1>" LOC="p5";
FRC9
NET "dout<2>" LOC="p3";
NET "dout<3>" LOC="p141";
NET "RESET" LOC="p74";
FRC1
NET "dir" LOC="p75";
4.DAC
NET "CLK" LOC="p18";
NET "dac_out<0>" LOC="p27";
NET "dac_out<1>" LOC="p26";
NET "dac_out<2>" LOC="p22";
NET "dac_out<3>" LOC="p23"; FRC5
NET "dac_out<4>" LOC="p21";
NET "dac_out<5>" LOC="p19";
NET "dac_out<6>" LOC="p20";
NET "dac_out<7>" LOC="p4";
NET "rst" LOC="p74"; FRC1
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1. What is HDL?
Hardware description language is a computer aided design(CAD). Tool to design and
synthesis of digital system. HDL language is similar to language.
10. What is the Verilog HDL standard and who is maintaining it?
IEEE standard 1364-1995 is the verilog HDL standard and it is maintain by verilog
international organization.
11. In VHDL, what are the modes that the ports can take?
in, out, buffer, inout.
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out-The port is only an o/p and appears only on the left and right hand side of the
statement.
buffer-The port can be used as both i/p & o/p but should have only one source.
inout-The port can be used as both an i/p & o/p.
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~^ Reduction XNOR
! Negation.
23. What are Arithmetic Operators. State few arithmetic Operators in HDL?
Arithmetic Operators performs various operators like.
VHDL Arithmetic Operators Verilog Arithmetic Operators
+ Addition + Addition
- Subtraction - Subtraction
* Multiplication * Multiplication
/ Division / Division
Mod Modulus % Modulus
rem Remainder ** Exponent
abs absolute {,} Concatenate
** Exponent
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Physical
User defined type
Severity type
2) Composite Type-Bit vector type
Array type
Record
3) Access Type
4) File Type
5) Other Types - Std_logic_type
Std_logic_vector type
Signed
Unsigned
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In VHDL the signal assignment operator <= is used & in verilog, the predefined word
assign is used.
38. What is the difference between syntax error and semantic error?
Syntax error is those that result from not following the rules of the language. it
terminates compilation of the program.
A semantic error is an error in the mechanics of the statement. it may not terminate the
program, but the outcome of the program may not be as expected.
42. Which are the Sequential statements that are assigned with behavioral description?
If statement, else-if, loop statements, for loop, forever, report, repeat, next-exit.
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Loops is used to repeat the execution of statements written inside the body. The number
of repetitions is controlled by the range of an index parameter. The loop allows the code
to be shortened.
47. What type of statements are written in Structural Description and why?
Statements are “Concurrent “ in nature. At any simulation time, all statements that have
an event are executed concurrently.
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The output or next state of Mealy circuit depends on the inputs and the present state of
flip flops/latches.
60. Name the keyword used to define global constants in VHDL and Verilog.
Generic in VHDL and parameter in Verilog.
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69. What is nmos Switches?
For a strong signal it should Pass0.
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82. Difference between VHDL and Verilog with reference to pocedure.
VHDL allows procedure calls to be written inside functions. Verilog
does not allow such calls.
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93. Tone/Falls: VHDL allows for multi dimensional arrays but Verilog only allows single
dimensional arrays.
105. Give Escape characters which can be used with monitor statement?
\ n, \t, \\, \”,\.
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Record type is a collection of elements, the elements of which can be of the same type
or different types.
Entity system is
port(a, b: in unsigned(3 downto 0);
d: out integer range(-10 to 10));
end system;
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always @(x)
begin y = x;
end
endmodule
QUESTION BANK
1a. Write and execute an VHDL / Verilog code to realize all logic gates and download to
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FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of DC Motor.
2a. Write and execute an VHDL / Verilog code to realize 2:4 decoder and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to display message on the given seven segment
displays accepting Hex key pad input data.
3a. Write and execute an VHDL / Verilog code to realize 8:3 encoder and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different
frequency.
4a. Write and execute an VHDL / Verilog code to realize 8:1 MUX and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different
frequency.
5a. Write and execute an VHDL / Verilog code to realize 4-bit Binary to Gray code converter
and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of Stepper Motor.
6a. Write and execute an VHDL / Verilog code to realize 1:8 DEMUX and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate triangular waveform using DAC.
7a. Write and execute an VHDL / Verilog code to realize N bit comparator and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of DC Motor.
8a. Write and execute an VHDL / Verilog code to realize Full Adder using Behavioral
modeling and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the external lights using relays.
9a. Write and execute an VHDL / Verilog code to realize Full Adder using Structural
modeling and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code the external lights using relays.
10a. Write and execute an VHDL / Verilog code to realize Full Adder using Data Flow
modeling and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code the external lights using relays.
11a. Write and execute an VHDL / Verilog code to realize SR & D-FF and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different
frequency.
12a. Write and execute an VHDL / Verilog code to realize JK FF and download to
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FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different
frequency.
13a. Write and execute an VHDL / Verilog code to realize 4-bit Synchronous counter and
download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code the external lights using relays.
14a. Write and execute an VHDL / Verilog code to realize 4-bit Binary counter and
download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to display message on the given seven segment
displays accepting Hex key pad input data.
15a. Write and execute an VHDL / Verilog code to realize 4-bit BCD counter and download
to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of DC Motor.
16a. Write and execute an VHDL / Verilog code to realize 4-bit ALU and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate triangular waveform using DAC for
different frequency.
=====
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