1 Design methods and their pros and cons

1. Successful chip design Can function properly Can working in the desired clock under different environment Reliable through the chips life Manufacturing-friendly Within power, budget, time to market 2. Design methods Microprocessor based: design circuit using standard uP/DSP (digital signal processor) i. Good: Flexible, easy to upgrade using software patches ii. Bad: Costly, low speed, power consuming and hard to integrate Full custom: do all things by hand from scratch i. Good: highest performance, optimized size, lowest part cost ii. Bad: long design time, complicated, expensive and risky. Require full set of masks for fabrication since all the masks are customized. Programmable logic devices (PLD): using programmable logic array, programmable interconnect, reprogrammable logic and interconnect to be programmed by user to perform some desired function. i. Good: No custom masked layers => fabrication time is few hours instead of few weeks. Can afford 100,000+ gates ii. Bad: High power consumption, high unit cost iii. Programmable logic array: Sum of Product (SOP), both AND plane and OR plan are programmable. iv. Programmable array logic: Product of Sum (POS), AND plane programmable, the OR plane is fixed. Gate array and Sea of Gates: all RTL fixed. Programmer can change the connection, wires and via to implement wanted function. i. Good: low cost (no customized masks), short manufacturing time. ii. Bad: high unit cost, power consuming iii. Example: FPGA Standard cell based: Cells are custom designed and inserted to a library. Those cells then will be connected using Place and Route in CAD tools. (being placed in rows and columns and being wired automatically). Library can consist of simple/complicated cells, can be built from scratches or reused from previous projects.

EEET2365

Traffic Light Controller Design Project

i. Good: ii. Bad: IP design SoC: integrate components on a single chip (uP, uC, memory, PLL, oscillator, USB, UART etc.) i. Good: lower cost, high performance, low power consumption, portable (small in size)

2 Design flow
1. Design flow is a set of procedure all users to process from a specification to a final chip implementation in an error-free way (aka EDA tools) 2. Custom design flow: Physical verification: Parasitic extraction: extract the parasitic components of the circuit (R, L, C). In transistor, the CGD

EEET2365

Traffic Light Controller Design Project

3. ASIC design flow:

Figure 1: See tutorials and assignments for what state do what

3 Transistor operating modes

1. NMOS : base in, source out, n++, p substrate 2. PMOS: base out, source in, p++, n substrate 3. MOSFET gate and body have a oxide layers (insulator) in between => act like a capacitor 4. Threshold voltage = voltage where the inversion layer effect overpower the effect of the bulk (the voltage where the density of the current carriers under gate become noticeable and start to cause current effect). a. Depends on the thickness of gate, gate materials, drain to source voltage, bulk voltage, temperature. 5. Operating a. When apply a voltage vgs < vt(accumulation), the gate voltage push holes/e from the gate and attract some e/hole under gate. But the voltage at gate is not enough to attract much active current carriers to cause any effect in the current (small inversion layer + big depletion region) => cut off, no current b. When increase vgs = vt, the channel is formed under the gate (big inversion region + big depletion region). 2

EEET2365

Traffic Light Controller Design Project

i. If vds = 0 (no bias current) => current carriers do not move so no current ii. If vds > 0, the lateral electronic field increase, the depletion layer at the drain widen while the inversion layer at the gain gets smaller. The potential value where the density of the inversion layer becomes very small it almost reaches zero is called pinch-off. The voltage at that point is called saturation voltage (vsat = vgs vt). Further increase of Vds will not cause any change in current (ideally) 6. Operating regions a. Cut off: no current, when vgs < vt b. Linear/triode region: when vgs > vt and vds < vsat c. Saturation region: when vgs > vt and vds >= vsat (current mostly depends on vgs) 7. Current calculation

8. Drift = movement of current carriers under electric field 9. Mobility = how easy/fast the carriers can move under the effect of E (depends on dopant density, temperature, surface vs. bulk conduction and type of carrier) 10. Mobility of electron is twice (roughly) faster than p => in CMOS need to size the PMOS twice as big for the same current. 11. Id, Vgs, Vds

12. Substrate doped in different type with source and drain to isolate two regions. If the bulk is doped with the same type as the source and drain, the current can go 3

EEET2365

Traffic Light Controller Design Project

from source to drain anytime the voltage Vds is available. This current then will not depend on the gate. 13. VTC: Vin vs. Vout of CMOS The noise margin is the difference between the output of the previous gate and the input of the current gate. If the noise is bigger than noise margin -> wrong output (2nd gate) Switching threshold is the Vout = Vin curve (where both PMOS and NMOS are saturated). To make the design symmetric and this switching voltage is vdd/2 => make PMOS twice bigger than NMOS (best noise margin) 14. Why dont we use NMOS for PUN and PMOS for PDN? - NMOS: strong 0. - PMOS : strong 1 - Transmission gate: transmit both strong 1 and 0 15. Delay definitions:

16. Power: (dynamic is much bigger) - Dynamic : switching load capacitance (charge the load), short circuit - Static: gate leakage, junction leakage, subthreshold leakage (when vg < Vth but the current still flows) 17. Gate oxide tunneling: when the oxide gets thinner => not insulator, electron can go through it (from gate to semiconductor) 18. Fan in/ fan out: - Fan in: number of inputs of an electronic gate - Fan out: number of outputs a gate can drive (the output current still enough to feed the outputs and produce correct outputs) 4

EEET2365

Traffic Light Controller Design Project

- Increase fan out by increase width or insert buffer before load - Bigger fan out -> bigger tpd because bigger fan out ~ bigger output capacitance - Bigger fan in cause the circuit to be slower 19. To characterize complex circuit, we short its input till there is one input transit from 0->1/1->0 and the gate performs like an inverter

4 CMOS Fabrication
1. Silicon is a semiconductor : insulator @ low temperature, conductor @ high temperature (poor conductor) 2. Dopant: the doping material (Group 5 like P, As for n mode and group 3 like B, Ga for p mode) 3. Doping method: a. Diffusion: heat the Si while flow dopant (gas) while using masks to cover areas where we do not want to dope. i. Slow (take long time to process) ii. Shallow doping iii. Cannot control no. of dopant b. Ion implementation: Shoot the ion dopant into the wafer i. Deep ii. Fast iii. Can control the no. iv. Can damage the wafer c. Lithography: using light and masks to print the pattern on to the wafer. It contains an UV light source, a lenses to collect the UV light and masks (provided by the designer) 4. Fabricating process a. Using SiO2 on top of the wafer to protect the wafer b. Cover the wafer with photoresist material c. Put the mask on, put the light on (lithography) to strip away the area we want to dope d. Etching oxide (clear the SiO2 layer) where the photoresist has been stripped (where we want to dope) e. Strip off all the remaining photoresist (the SiO2 will protect the area we dont want to dope) f. Implant the dopant to the area (ion implementation + heating if needed) g. Strip the SiO2

EEET2365

Traffic Light Controller Design Project

5. New MOSFET structure: FINET (one gate on top of two vertical gates), Gate All Around GAA (same idea, gate all around channel regions), SOI (silicon on insulator Silicon Insulator - Substrate)

5 Transistor sizing
1. Transistor sizing is to archive the resistance of the PUN and PDN are equal => switching threshold = vdd/2, best noise margin. 2. Sizing: Series => Size x , Parallel => ignore Example: Lecture 8. (NMOS separate to PMOS) 3. To increase drive strength, increase width of both NMOS and PMOS 4. Capacitance: gs, gb, gd, sb, db 5. Transistor folding (gate to gate, source to source, drain to drain) => decrease the parasitic capacitance

6 Standard cell design

1. Lamda based rule: base on a single parameter (lamda characterize the resolution of the project haft of the minimum drawn transistor length ie. Length = 180nm => lamda = 90nm) scalable (dimension will be rounded up to an integer multiple of lamda) easy to scale, less density, more simple 2. Layout design objectives a. Min size b. Good noise immunity c. Compatible to other cells d. Can be designed automatically and quickly 3. Layout design flow a. Custom design b. Standard cell based 4. Standard cell library a. Contain a set of cells that can work together using CAD tool flow b. The cells has all the necessary views c. Can work with other cells in the same library d. Follow the standard rules e. DRC free when placing 2 cells together 5. Specifications a. Same height b. Power rails run parallel 6

EEET2365

Traffic Light Controller Design Project

c. Fixed origin on the left corner d. Include wells and substrate (ntap, ptap) 6. Layout optimization - Objective: minimum number of diffusion breaks, minimum layout area - Euler path: Path where each edge is visited once

7 Combinational logic
1. Combinational := no FF, output depends on inputs only 2. Sequential := FF, output depends on inputs and previous inputs 3. Dlatch

8 Sequential logic
Mealy vs. Moore: o Mealy: output depends on input and current state o Moore : output depends on current state only Mealy: there is one path from input to output (all combinational) 7

EEET2365

Traffic Light Controller Design Project

Static vs. dynamic: o Static: state stores by feedback o Dynamic: state stores by capacitor (high speed and compact but need to charge/refresh often) Edge trigger FF

Rising edge (AND) falling edge (OR) Setup time: time before the active edge of the clock where the input must be stable Hold time: time after the active edge of the clock where the input must still be stable For each phase, phase period must be longer than combinational delay and register (FF) propagation delay Path is the path from one FF to another FF Clock skew: clock comes to two FF of the same system at different time => clock tree to solve the skew

9
-

ASIC design flow

Highest performance Cheap for mass product Not very configurable Long development time Requires specifications