r05210404 Electronic Circuit Analysis November 2008
r05210404 Electronic Circuit Analysis November 2008
r05210404 Electronic Circuit Analysis November 2008
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(b) For CE amplifier , what is the maximum value of RS for which Ro differs by
no more than 10 percent of its value for RS = 0. The h-parameter values are
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hf e = 50, hi e = 1.1KΩ, hre = 2.5x10−4 , hoe = 25µA/V. (10+6)
3. (a) Draw Hybrid - π model for a transistor in the CE configuration and explain
the significance of every component in this model.
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(b) Given a germanium p-n-p transistor whose basewidth is 10−4 cm. At room
temperature and for a dc emitter current of 2 mA, find
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5. (a) Draw and explain the circuit diagram of a single tuned Capacitance coupled
amplifier. Also explain its operation?
(b) Draw and explain the significance of Gain versus Frequency curve of tuned
amplifiers when they are used in radio amplifiers?
(c) Draw the Ideal and actual frequency response curves of a single tuned ampli-
fier? [8+4+4]
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8. (a) Specify suitable component values to get Vo=7.5V in the circuit of (Given
figure8a). Using a 7805 regulator. From data sheet. IQ =4.2mA and VR =5V,
choose IR1 =25mA.
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Figure 8a
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(b) Draw the functional diagram SMPS and explain its operation.
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1. (a) Draw the circuit diagram of Common Drain amplifier and derive an expression
for its Voltage gain.
(b) The h-parameters of the transistor used in CE amplifier are hf e = 50, hie
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=1.1KΩ, hre = 2.5x10−4 , hoe = 24µ A/V. Find out current gain and voltage
gains with and without source resistance, input and output impedances, given
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that RL = 10K and RS = 1 K. [6+10]
3. (a) Draw the small signal equivalent circuit for an emitter follower stage at high
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frequencies.
(b) Consider a CE stage with a resistive load RL . Using Miller’s theorem Find
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4. (a) In series fed Class - A power amplifier, explain the importance of the position
of operating point on output signal swing. Show that the conversion efficiency
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is 25%.
(b) Discuss the origin of various distortions in transistor amplifier circuits. [10+6]
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Figure 5
6. (a) Draw the Gain versus Frequency response of uncompensated and high fre-
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quency compensated CE wide band amplifier assuming that the lower 3-dB
frequency is zero.
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(b) Explain High frequency compensation and what are the methods provided to
achieve High frequency compensation in a CE amplifier?
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Figure 7a
(b) Draw and explain the regulator which will provide the foldback limiting .[8+8]
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1. (a) For a single stage transistor amplifier, RS =10K and RL = 10K. The h-parameter
values are hf c = - 51, hic =1.1KΩ, hrc ≈1, hoc = 25 µA/V. Find AI , AV , AV S , Ri ,
and Ro for the CC transistor configuration.
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(b) For a single stage transistor amplifier, RS =5K and RL = 10K The h-parameter
values are hf e = 50, hie =1.1KΩ, hre = 2.5x10−4 , hoe = 25 µA/V. Find
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AI , AV , AV S , Ri , and Ro for the CE transistor configuration. [8+8]
2. (a) Draw the circuit diagram of Difference amplifier and explain its operation.
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(b) For the Cascode transistor configuration, which consists of CE stage in series
with CB stage , verify that the cascode combination acts like a single CE
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transistor with negligible internal feedback. [8+8]
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4. (a) With the help of a circuit diagram, explain the principle of operation of a
class-C power amplifier.
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(c) For a linear duration of power dissipation of a transistor with θJC (Junction-
to-case) of 3.12% C/Watts and θCS (Case-to-heatsink) of 0.50 C/Watt and θSA
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Figure 5
6. Explain what you mean by Synchronous tuning of tuned amplifiers? Draw the
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frequency response of a synchronously tuned amplifier showing the response of
individual stages and overall responses? [16]
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7. (a) What type of protection circuits are required in power supplies?
(b) A 50V power supply has line regulation 0.2%V. How large would the 75V
input voltage to the supply have to become for the output voltage to rise to
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52V?
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(c) Give the disadvantages of the series and shunt regulators. [4+6+6]
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8. (a) Specify suitable component values to get Vo=7.5V in the circuit of (Given
figure8a). Using a 7805 regulator. From data sheet. IQ =4.2mA and VR =5V,
choose IR1 =25mA.
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Figure 8a
(b) Draw the functional diagram SMPS and explain its operation.
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1. (a) Derive the expressions for Ai , AV of CE amplifier circuit. Explain how Ai and
AV are effected by RL .
(b) Consider a single stage CE amplifier with RS = 1K, R1 = 50 K, R2 =2 K, RC
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= 1K, RL = 1.2K, hf e = 50, hie =1.1K, hre = hoe = 0; Find AI , Ri , Ro , AV
and power gain. [8+8]
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2. A two stage FET RC coupled amplifier has the following parameters: gm = 10mA/V,
rd = 5.5K and Rg = 0.5 M for each stage. Assume CS is arbitrarily large.
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(a) What must be the value of Cb in order that the frequency characteristic of
each stage be flat within 1 dB down to 10 Hz ?
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(b) Repeat the above part if the overall gain of both stages is to be down 1 dB at
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10 Hz.
(c) What is the overall mid band voltage gain ? [8+4+4]
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(b) Delete all capacitors from the above emitter-follower equivalent circuit and
find the input impedance and output impedance. [8+8]
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4. (a) Compare the series fed and transformer coupled Class - A power amplifiers.
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Figure 7a
(b) Draw and explain the regulator which will provide the foldback limiting .[8+8]
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8. (a) Draw the block diagram of IC 723 and explain its operating principle.
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(b) Draw and explain the Fullwave voltage Doubler and give its applications.
[8+8]
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